Low tunneling current MIM structure and method of manufacturing same

Disclosed herein are new MIM structures having increased capacitance with little or no tunneling current, and related methods of manufacturing the same. In one embodiment, the new MIM structure comprises a first electrode comprising a magnetic metal and having a magnetic moment aligned in a first direction, and a second electrode comprising a magnetic metal and having a magnetic moment aligned in a second direction antiparallel to the first direction. In addition, such an MIM structure comprises a dielectric layer formed between the first and second electrodes and contacting the first and second magnetic metals.

Magnetoresistive structures and fabrication methods

Disclosed herein is a magnetoresistive structure, for example useful as a spin-valve or GMR stack in a magnetic sensor, and a fabrication method thereof. The magnetoresistive structure uses twisted coupling to induce a perpendicular magnetization alignment between the free layer and the pinned layer. Ferromagnetic layers of the free and pinned layers are exchange-coupled using antiferromagnetic layers having substantially parallel exchange-biasing directions. Thus, embodiments can be realized that have antiferromagnetic layers formed of a same material and/or having a same blocking temperature. At least one of the free and pinned layers further includes a second ferromagnetic layer and an insulating layer, such as a NOL, between the two ferromagnetic layers. The insulating layer causes twisted coupling between the two ferromagnetic layers, rotating the magnetization direction of one 90 degrees relative to the magnetization direction of the other.

Method to Minimize MTJ Sidewall Damage and Bottom Electrode Redeposition Using IBE Trimming

An improved method for etching a magnetic tunneling junction (MTJ) structure is achieved. A stack of MTJ layers is provided on a bottom electrode. The MTJ stack is patterned to form a MTJ device wherein sidewall damage or sidewall redeposition is formed on sidewalls of the MTJ device. A dielectric layer is deposited on the MTJ device and the bottom electrode. The dielectric layer is etched away using ion beam etching at an angle relative to vertical of greater than 50 degrees wherein the dielectric layer on the sidewalls is etched away and wherein sidewall damage or sidewall redeposition is also removed and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.

CMP stop layer and sacrifice layer for high yield small size MRAM devices

An array, such as an MRAM (Magnetic Random Access Memory) array formed of a multiplicity of layered thin film devices, such as MTJ (Magnetic Tunnel Junction) devices, can be simultaneously formed in a multiplicity of horizontal widths in the 60 nm range while all having top electrodes with substantially equal thicknesses and coplanar upper surfaces. This allows such a multiplicity of devices to be electrically connected by a common conductor without the possibility of electrical opens and with a resulting high yield.

PASSIVE DEVICES IN BONDING LAYERS

A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.

Liquid crystal reflective polarizer and pancake lens assembly having the same

An optical device is provided. The optical device includes a first optical element configured to output an elliptically polarized light having one or more predetermined polarization ellipse parameters. The optical device also includes a second optical element including a birefringent material with a chirality, and configured to receive the elliptically polarized light from the first optical element and reflect the elliptically polarized light as a circularly polarized light.

FORCE SENSOR AND SENSING ELEMENT THEREOF

A force sensor includes a sensing element, a forced element and strain gauges. There are flexure mechanisms on the sensing element, the forced element is coupled to a free end of each of the flexure mechanisms, and each of the strain gauges is placed on an elastic portion of each of the flexure mechanisms respectively. Each of the strain gauges is provided to detect an elastic strain of the elastic portion when a forced is applied to the forced element, transmitted to the free end via the forced element and transmitted to the elastic portion via a flexure hinge of each of the flexure mechanisms.

Extra doped region for back-side deep trench isolation

The present disclosure relates to a CMOS image sensor having a doped region, arranged between deep trench isolation structures and an image sensing element, and an associated method of formation. In some embodiments, the CMOS image sensor has a pixel region disposed within a semiconductor substrate. The pixel region has an image sensing element configured to convert radiation into an electric signal. A plurality of back-side deep trench isolation (BDTI) structures extend into the semiconductor substrate on opposing sides of the pixel region. A doped region is laterally arranged between the BDTI structures and separates the image sensing element from the BDTI structures and the back-side of the semiconductor substrate. Separating the image sensing element from the BDTI structures prevents the image sensing element from interacting with interface defects near edges of the BDTI structures, and thereby reduces dark current and white pixel number.

Image sensor comprising reflective guide layer and method of forming the same

Various structures of image sensors are disclosed, as well as methods of forming the image sensors. According to an embodiment, a structure comprises a substrate comprising photo diodes, an oxide layer on the substrate, recesses in the oxide layer and corresponding to the photo diodes, a reflective guide material on a sidewall of each of the recesses, and color filters each being disposed in a respective one of the recesses. The oxide layer and the reflective guide material form a grid among the color filters, and at least a portion of the oxide layer and a portion of the reflective guide material are disposed between neighboring color filters.

Free layer with high thermal stability for magnetic device applications by insertion of a boron dusting layer

A boron or boron containing dusting layer such as CoB or FeB is formed along one or both of top and bottom surfaces of a free layer at interfaces with a tunnel barrier layer and capping layer to improve thermal stability while maintaining other magnetic properties of a MTJ stack. Each dusting layer has a thickness from 0.2 to 20 Angstroms and may be used as deposited, or at temperatures up to 400° C. or higher, or following a subsequent anneal at 400° C. or higher. The free layer may be a single layer of CoFe, Co, CoFeB or CoFeNiB, or may include a non-magnetic insertion layer. The resulting MTJ is suitable for STT-MRAM memory elements or spintronic devices. Perpendicular magnetic anisotropy is maintained in the free layer at temperatures up to 400° C. or higher. Ku enhancement is achieved and the retention time of a memory cell for STT-MRAM designs is increased.

Image Sensor Comprising Reflective Guide Layer and Method of Forming the Same

Various structures of image sensors are disclosed, as well as methods of forming the image sensors. According to an embodiment, a structure comprises a substrate comprising photo diodes, an oxide layer on the substrate, recesses in the oxide layer and corresponding to the photo diodes, a reflective guide material on a sidewall of each of the recesses, and color filters each being disposed in a respective one of the recesses. The oxide layer and the reflective guide material form a grid among the color filters, and at least a portion of the oxide layer and a portion of the reflective guide material are disposed between neighboring color filters.

Vibration-actuated micro mirror device

The present invention provides a vibration-actuated micro mirror device comprising a substrate having a swinging frame and a reflection mirror, and a vibration part having a first and a second vibration structures coupled to the substrate, wherein the first vibration structure is driven to generate a first complex wave formed by a first and a second wave signals while the second vibration structure is driven to generate a second complex wave formed by a third and a fourth wave signals, and the first and the third wave signals are formed with the same frequency and phase while the second and the fourth wave signals are formed with the same frequency but opposite phases. The first and the second complex waves actuate the substrate such that the swinging frame is rotated about a first axis while the reflection mirror is rotated about a second axis.

Novel Free Layer Structure in Magnetic Random Access Memory (MRAM) for Mo or W Perpendicular Magnetic Anisotropy (PMA) Enhancing Layer

A perpendicularly magnetized magnetic tunnel junction (p-MTJ) is disclosed wherein a free layer (FL) has a first interface with a MgO tunnel barrier, a second interface with a Mo or W Hk enhancing layer, and is comprised of FexCoyBz wherein x is 66-80, y is 5-9, z is 15-28, and (x+y+z)=100 to simultaneously provide a magnetoresistive ratio >100%, resistance x area product <5 ohm/□m2, switching voltage <0.15V (direct current), and sufficient Hk to ensure thermal stability to 400° C. annealing. The FL may further comprise one or more M elements such as O or N to give (FexCoyBz)wM100-w where w is >90 atomic %. Alternatively, the FL is a trilayer with a FeB layer contacting MgO to induce Hk at the first interface, a middle FeCoB layer for enhanced magnetoresistive ratio, and a Fe or FeB layer adjoining the Hk enhancing layer to increase thermal stability.

Image Sensor Comprising Reflective Guide Layer and Method of Forming the Same

Various structures of image sensors are disclosed, as well as methods of forming the image sensors. According to an embodiment, a structure comprises a substrate comprising photo diodes, an oxide layer on the substrate, recesses in the oxide layer and corresponding to the photo diodes, a reflective guide material on a sidewall of each of the recesses, and color filters each being disposed in a respective one of the recesses. The oxide layer and the reflective guide material form a grid among the color filters, and at least a portion of the oxide layer and a portion of the reflective guide material are disposed between neighboring color filters. 1. A structure comprising:a substrate comprising photo diodes;an oxide layer on the substrate, recesses being in the oxide layer and corresponding to the photo diodes;a reflective guide material on a sidewall of each of the recesses; andcolor filters each being disposed in a respective one of the recesses, the oxide layer and the reflective guide material forming a grid among the color filters, at least a portion of the oxide layer and a portion of the reflective guide material being disposed between neighboring color filters.2. The structure of claim 1 , wherein the reflective guide material comprises a metal.3. The structure of claim 1 , wherein the reflective guide material comprises a material with a refractive index greater than 2.0.4. The structure of claim 1 , wherein the reflective guide material comprises silicon nitride.5. The structure of claim 1 , wherein the reflective guide material is on each sidewall of the recesses.6. The structure of further comprising a nitride layer disposed between the substrate and the oxide layer claim 1 , the recesses extending through the oxide layer to the nitride layer.7. The structure of further comprising a hardmask layer on the oxide layer claim 1 , the oxide layer being disposed between the substrate and the hardmask layer.8. The structure of claim 7 , wherein the hardmask layer ...

Structure and method for MRAM devices

A semiconductor device includes a bottom electrode; a magnetic tunneling junction (MTJ) element over the bottom electrode; a top electrode over the MTJ element; and a sidewall spacer abutting the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacer includes a magnetic material.

MRAM Cells and Circuit for Programming the Same

A circuit includes magneto-resistive random access memory (MRAM) cell and a control circuit. The control circuit is electrically coupled to the MRAM cell, and includes a current source configured to provide a first writing pulse to write a value into the MRAM cell, and a read circuit configured to measure a status of the MRAM cell. The control circuit is further configured to verify whether a successful writing is achieved through the first writing pulse.

Image-stabilization driving device

Disclosed is an image-stabilization driving device including a first sliding member connected to an image sensor; a first piezoelectrical element for driving the first sliding member to move linearly along a first direction; a second sliding member connected to the first piezoelectrical element; and a second piezoelectrical element for driving the second sliding member to move linearly along a second direction intersecting with the first direction. The first and second piezoelectrical elements are adapted to drive the image sensor to move in a plane, thereby providing a structurally simple and miniaturized image-stabilization driving device.

Free layer structure in magnetic random access memory (MRAM) for Mo or W perpendicular magnetic anisotropy (PMA) enhancing layer

A perpendicularly magnetized magnetic tunnel junction (p-MTJ) is disclosed wherein a free layer (FL) has a first interface with a MgO tunnel barrier, a second interface with a Mo or W Hk enhancing layer, and is comprised of FexCoyBz wherein x is 66-80, y is 5-9, z is 15-28, and (x+y+z)=100 to simultaneously provide a magnetoresistive ratio >100%, resistance x area product <5 ohm/□m2, switching voltage <0.15 V (direct current), and sufficient Hk to ensure thermal stability to 400° C. annealing. The FL may further comprise one or more M elements such as O or N to give (FexCoyBz)wM100-w where w is >90 atomic %. Alternatively, the FL is a trilayer with a FeB layer contacting MgO to induce Hk at the first interface, a middle FeCoB layer for enhanced magnetoresistive ratio, and a Fe or FeB layer adjoining the Hk enhancing layer to increase thermal stability.

Hybridized oxide capping layer for perpendicular magnetic anisotropy

A hybrid oxide capping layer (HOCL) is disclosed and used in a magnetic tunnel junction to enhance thermal stability and perpendicular magnetic anisotropy in an adjoining reference layer. The HOCL has an interface oxide layer adjoining the reference layer and one or more transition metal oxide layers wherein each of the metal layers selected to form a transition metal oxide has an absolute value of free energy of oxide formation less than that of the metal used to make the interface oxide layer. One or more of the HOCL layers is under oxidized. Oxygen from one or more transition metal oxide layers preferably migrates into the interface oxide layer during an anneal to further oxidize the interface oxide. As a result, a less strenuous oxidation step is required to initially oxidize the lower HOCL layer and minimizes oxidative damage to the reference layer.

Monolayer-By-Monolayer Growth of MgO Layers Using Mg Sublimation and Oxidation

A MgO layer is formed using a process flow wherein a Mg layer is deposited at a temperature <200° C. on a substrate, and then an anneal between 200° C. and 900° C., and preferably from 200° C. and 400° C., is performed so that a Mg vapor pressure >10−6 Torr is reached and a substantial portion of the Mg layer sublimes and leaves a Mg monolayer. After an oxidation between −223° C. and 900° C., a MgO monolayer is produced where the Mg:O ratio is exactly 1:1 thereby avoiding underoxidized or overoxidized states associated with film defects. The process flow may be repeated one or more times to yield a desired thickness and resistance x area value when the MgO is a tunnel barrier or Hk enhancing layer. Moreover, a doping element (M) may be added during Mg deposition to modify the conductivity and band structure in the resulting MgMO layer.

Method of beam angle optimization for radiation apparatus

A newly developed algorithm and software can effectively and accurately predict the collisions for the accelerator, phantom, and patient setups, and can help physicians to choose the noncolliding and optimized beam sets efficiently via offering the ideal hits of planning target volume (PTV) and constraints of organ at risks (OARs).

Flexible, adjustable lens power liquid crystal cells and lenses

A flexible optical element adopting liquid crystals (LCs) as the materials for realizing electrically tunable optics is foldable. A method for manufacturing the flexible element includes patterned photo-polymerization. The LC optics can include a pair of LC layers with orthogonally aligned LC directors for polarizer-free properties, flexible polymeric alignment layers, flexible substrates, and a module for controlling the electric field. The lens power of the LC optics can be changed by controlling the distribution of electric field across the optical zone. Lens power control can be provided using combinations of electrode configurations, drive signals and anchoring strengths in the alignment layers.

Fabrication of large height top metal electrode for sub-60nm magnetoresistive random access memory (MRAM) devices

A process flow for forming magnetic tunnel junction (MTJ) cells with a critical dimension CD≤60 nm by using a top electrode (TE) hard mask having a thickness ≥100 nm prior to MTJ etching is disclosed. A carbon hard mask (HM), silicon HM, and photoresist are sequentially formed on a MTJ stack of layers. A pattern of openings in the photoresist is transferred through the Si HM with a first reactive ion etch (RIE), and through the carbon HM with a second RIE. After TE material is deposited to fill the openings, a chemical mechanical process is performed to remove all layers above the carbon HM. The carbon HM is stripped and the resulting TE pillars are trimmed to a CD≤60 nm while maintaining a thickness proximate to 100 nm. Thereafter, an etch process forms MTJ cells while TE thickness is maintained at ≥70 nm.

MTJ CD variation by HM trimming

A MTJ stack is deposited on a bottom electrode. A metal hard mask is deposited on the MTJ stack and a dielectric mask is deposited on the metal hard mask. A photoresist pattern is formed on the dielectric mask, having a critical dimension of more than about 65 nm. The dielectric and metal hard masks are etched wherein the photoresist pattern is removed. The dielectric and metal hard masks are trimmed to reduce their critical dimension to 10-60 nm and to reduce sidewall surface roughness. The dielectric and metal hard masks and the MTJ stack are etched wherein the dielectric mask is removed and a MTJ device is formed having a small critical dimension of 10-60 nm, and having further reduced sidewall surface roughness.

Co/X and CoX multilayers with improved out-of-plane anisotropy for magnetic device applications

A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Multiple Hard Mask Patterning to Fabricate 20nm and Below MRAM Devices

A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers on a bottom electrode on a wafer is provided. A metal hard mask layer is provided on the MTJ stack. A stack of multiple dielectric hard masks is formed on the metal hard mask wherein each successive dielectric hard mask has etch selectivity with respect to its underlying and overlying layers. The dielectric hard mask layers are etched in turn selectively with respect to their underlying and overlying layers wherein each successive pattern size is smaller than the preceding pattern size. The MTJ stack is etched selectively with respect to the bottommost combination dielectric and metal hard mask pattern to form a MTJ device having a MTJ pattern size smaller than a bottommost pattern size. 1. A method comprising:forming a magnetic tunneling junction (MTJ) stack on a substrate;forming a first hard mask layer on the MTJ stack;forming a second hard mask layer on the first hard mask layer;forming a third hard mask layer on the second hard mask layer, wherein at least one of the first, second and third hard mask layers is formed of a different material than the other hard mask layers;patterning the third hard mask layer such that the patterned third hard mask layer has a first pattern size;patterning the second hard mask layer by using the patterned third hard mask layer as a mask, the patterned second hard mask layer having a second pattern size that is different than the first pattern size;patterning the first hard mask layer by using the patterned second hard mask layer as a mask, the patterned first hard mask layer having a third pattern size that is different than the second pattern size; andpatterning the MTJ stack by using the patterned first hard mask layer as a mask, the patterned MTJ stack having a fourth pattern size that is different than the third pattern size.2. The method of claim 1 , wherein at least one of the first claim 1 , second and third hard mask ...

Sacrifice layer structure and method for magnetic tunnel junction (MTJ) etching process

A magnetic tunnel junction (MTJ) etching process uses a sacrifice layer. An MTJ cell structure includes an MTJ stack with a first magnetic layer, a second magnetic layer, and a tunnel barrier layer in between the first magnetic layer and the second magnetic layer, and a sacrifice layer adjacent to the second magnetic layer, where the sacrifice layer protects the second magnetic layer in the MTJ stack from oxidation during an ashing process. The sacrifice layer does not increase a resistance of the MTJ stack. The sacrifice layer can be made of Mg, Cr, V, Mn, Ti, Zr, Zn, or any alloy combination thereof, or any other suitable material. The sacrifice layer can be multi-layered and/or have a thickness ranging from 5 Å to 400 Å. The MTJ cell structure can have a top conducting layer over the sacrifice layer.

Extra doped region for back-side deep trench isolation

The present disclosure, in some embodiments, relates to a method of forming an image sensor. The method includes implanting a dopant into a substrate to form a doped region and implanting one or more additional dopants into the substrate to form an image sensing element between the doped region and a front-side of the substrate. The doped region directly contacts a boundary of the image sensing element that is furthest from the front-side of the substrate. The method further includes etching the substrate to form one or more trenches extending into a back-side of the substrate. The back-side of the substrate opposes the front-side of the substrate. The method further includes filling the one or more trenches with one or more dielectric materials to form isolation structures.

HEAT BLOCK

A heat block for holding an electronic device is disclosed. The heat block comprises a base and at least one discharge device. The discharge device is disposed on the base. The discharge device is electrically conductive and is grounded. When the electronic device is placed on the base, the discharge device is in contact with an electrical contact of the electronic device.

Post treatment to reduce shunting devices for physical etching process

A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.

Highly selective ion beam etch hard mask for sub 60nm MRAM devices

A via connection is provided through a dielectric layer to a bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. A top electrode is deposited on the MTJ stack. A selective hard mask and then a dielectric hard mask are deposited on the top electrode. The dielectric and selective hard masks are patterned and etched. The dielectric and selective hard masks and the top electrode are etched wherein the dielectric hard mask is removed. The top electrode is trimmed using IBE at an angle of 70 to 90 degrees. The selective hard mask, top electrode, and MTJ stack are etched to form a MTJ device wherein over etching into the dielectric layer surrounding the via connection is performed and re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.

Raising programming currents of magnetic tunnel junctions using word line overdrive and high-k metal gate

A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector.

SEMICONDUCTOR DEVICE HAVING INDUCTOR AND METHOD OF MANUFACTURING THEREOF

A semiconductor device includes a first die having a first bonding layer; a second die having a second bonding layer disposed over and bonded to the first bonding layer; a plurality of bonding members, wherein each of the plurality of bonding members extends within the first bonding layer and the second bonding layer, wherein the plurality of bonding members includes a connecting member electrically connected to a first conductive pattern in the first die and a second conductive pattern in the second die, and a dummy member electrically isolated from the first conductive pattern and the second conductive pattern; and an inductor disposed within the first bonding layer and the second bonding layer. A method of manufacturing a semiconductor device includes bonding a first inductive coil of a first die to a second inductive coil of a second die to form an inductor.

Ion beam etching fabricated sub 30nm vias to reduce conductive material re-deposition for sub 60nm MRAM devices

A metal layer and first dielectric hard mask are deposited on a bottom electrode. These are patterned and etched to a first pattern size. The patterned metal layer is trimmed using IBE at an angle of 70-90 degrees wherein the metal layer is reduced to a second pattern size smaller than the first pattern size. A dielectric layer is deposited surrounding the patterned metal layer and polished to expose a top surface of the patterned metal layer to form a via connection to the bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. The MTJ stack is etched to a pattern size larger than the via size wherein an over etching is performed. Re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.

Minimal Thickness Synthetic Antiferromagnetic (SAF) Structure with Perpendicular Magnetic Anisotropy for STT-MRAM

A synthetic antiferromagnetic structure for a spintronic device is disclosed and has an FL2/Co or Co alloy/antiferromagnetic coupling/Co or Co alloy/CoFeB configuration where FL2 is a ferromagnetic free layer with intrinsic PMA. Antiferromagnetic coupling is improved by inserting a Co or Co alloy dusting layer on top and bottom surfaces of the antiferromagnetic coupling layer. The FL2 layer may be a L10 ordered alloy, a rare earth-transition metal alloy, or an (A1/A2)n laminate where A1 is one of Co, CoFe, or an alloy thereof, and A2 is one of Pt, Pd, Rh, Ru, Ir, Mg, Mo, Os, Si, V, Ni, NiCo, and NiFe, or A1 is Fe and A2 is V. A method is also provided for forming the synthetic antiferromagnetic structure.

Pneumatic cylinder device

A pneumatic cylinder device includes an outer cylinder, an inner cylinder unit, a piston unit, and a control valve. The inner cylinder unit includes an inner cylinder, and a flow passage formation plate disposed between the inner and outer cylinders. The flow passage formation plate cooperates with a groove bottom wall to define a flow passage communicated with first and second air-guiding holes in the groove bottom wall. The first and second air-guiding holes are communicated respectively with first and second chamber parts of an air chamber in the inner cylinder. The control valve is disposed between the first air-guiding hole and the first chamber part.

MRAM cells and circuit for programming the same

A circuit includes magneto-resistive random access memory (MRAM) cell and a control circuit. The control circuit is electrically coupled to the MRAM cell, and includes a current source configured to provide a first writing pulse to write a value into the MRAM cell, and a read circuit configured to measure a status of the MRAM cell. The control circuit is further configured to verify whether a successful writing is achieved through the first writing pulse.

Low Resistance MgO Capping Layer for Perpendicularly Magnetized Magnetic Tunnel Junctions

A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a first metal oxide (Mox) layer and second metal oxide (tunnel barrier) to produce perpendicular magnetic anisotropy (PMA) in the FL. In some embodiments, conductive metal channels made of a noble metal are formed in the Mox that is MgO to reduce parasitic resistance. In a second embodiment, a discontinuous MgO layer with a plurality of islands is formed as the Mox layer and a non-magnetic hard mask layer is deposited to fill spaces between adjacent islands and form shorting pathways through the Mox. In another embodiment, end portions between the sides of a center Mox portion and the MTJ sidewall are reduced to form shorting pathways by depositing a reducing metal layer on Mox sidewalls, or performing a reduction process with forming gas, H, or a reducing species. 1. A device comprising:a tunnel barrier layer that includes a first metal oxide layer, the tunnel barrier layer disposed between a reference layer and a free layer;a second metal oxide layer physically contacting a second surface of the free layer that is opposite with respect to a first surface of the free layer that contacts the tunnel barrier layer, the second metal oxide layer including a plurality of conductive pathways therein that extend from a top surface to a bottom surface of the second metal oxide layer; andthe free layer physically contacting the tunnel barrier and the second metal oxide layer to generate interfacial perpendicular anisotropy resulting in perpendicular magnetic anisotropy PMA in the free layer.2. The device of claim 1 , wherein the second metal oxide layer includes a central portion having a first oxidation state and opposing end portions disposed on either side of the central portion having a second oxidation state that is less than the first oxidation state.3. The device of claim 1 , wherein the second metal oxide includes a material selected from the group consisting of Mg claim 1 , MgAl ...

Nebulizer

Under-Cut Via Electrode for Sub 60nm Etchless MRAM Devices by Decoupling the Via Etch Process

A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A first dielectric layer is deposited on a bottom electrode and partially etched through to form a first via opening having straight sidewalls, then etched all the way through to the bottom electrode to form a second via opening having tapered sidewalls. A metal layer is deposited in the second via opening and planarized to the level of the first dielectric layer. The remaining first dielectric layer is removed leaving an electrode plug on the bottom electrode. MTJ stacks are deposited on the electrode plug and on the bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and polished to expose a top surface of the MTJ stack on the electrode plug. A top electrode layer is deposited to complete the MTJ structure.

Ion Beam Etching Process Design to Minimize Sidewall Re-Deposition

A first pattern is formed on an MTJ stack as a first array of first parallel bands. A first ion beam etching is performed on the MTJ stack using the first pattern wherein a tilt between an ion beam source and the substrate is maintained such that a horizontal component of the ion beam is parallel to the first parallel bands and the substrate is not rotated. Thereafter, a second pattern is formed on the MTJ stack as a second array of parallel bands wherein the second parallel bands are perpendicular to the first parallel bands. A second ion beam etching is performed using the second pattern wherein a tilt between an ion beam source and the substrate is maintained such that a horizontal component of the ion beam is parallel to the second parallel bands and wherein the substrate is not rotated to complete formation of the MTJ structure. 1. A method for fabricating an array of magnetic tunneling junction (MTJ) structures comprising:depositing a MTJ stack on a substrate;forming a first pattern on said MTJ stack as a first array of first parallel bands;first ion beam etching said MTJ stack using said first pattern wherein a tilt between an ion beam source and said substrate is maintained such that a horizontal component of said ion beam is parallel to said first parallel bands and wherein said substrate is not rotated;thereafter forming a second pattern on said MTJ stack as a second array of second parallel bands wherein said second parallel bands are perpendicular to said first parallel bands; andthereafter second ion beam etching said MTJ stack using said second pattern wherein a tilt between an ion beam source and said substrate is maintained such that a horizontal component of said ion beam is parallel to said second parallel bands and wherein said substrate is not rotated to complete formation of said MTJ structures.2. The method according to wherein said first and second ion beam etching use ions of one or more of: Ar claim 1 , Xe claim 1 , Ne claim 1 , and Kr.3. ...

Under-cut via electrode for sub 60nm etchless MRAM devices by decoupling the via etch process

A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A first dielectric layer is deposited on a bottom electrode and partially etched through to form a first via opening having straight sidewalls, then etched all the way through to the bottom electrode to form a second via opening having tapered sidewalls. A metal layer is deposited in the second via opening and planarized to the level of the first dielectric layer. The remaining first dielectric layer is removed leaving an electrode plug on the bottom electrode. MTJ stacks are deposited on the electrode plug and on the bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and polished to expose a top surface of the MTJ stack on the electrode plug. A top electrode layer is deposited to complete the MTJ structure.

Flexible liquid crystal cells and lenses

A flexible optical element adopting liquid crystals (LCs) as the materials for realizing electrically tunable optics is foldable. A method for manufacturing the flexible element includes patterned photo-polymerization. The LC optics can include a pair of LC layers with orthogonally aligned LC directors for polarizer-free properties, flexible polymeric alignment layers, flexible substrates, and a module for controlling the electric field. The lens power of the LC optics can be changed by controlling the distribution of electric field across the optical zone.

Image sensor comprising reflective guide layer and method of forming the same

Various structures of image sensors are disclosed, as well as methods of forming the image sensors. According to an embodiment, a structure comprises a substrate comprising photo diodes, an oxide layer on the substrate, recesses in the oxide layer and corresponding to the photo diodes, a reflective guide material on a sidewall of each of the recesses, and color filters each being disposed in a respective one of the recesses. The oxide layer and the reflective guide material form a grid among the color filters, and at least a portion of the oxide layer and a portion of the reflective guide material are disposed between neighboring color filters.

Free Layer with Out-of-Plane Anisotropy for Magnetic Device Applications

Synthetic antiferromagnetic (SAF) and synthetic ferrimagnetic (SyF) free layer structures are disclosed that reduce Ho (for a SAF free layer), increase perpendicular magnetic anisotropy (PMA), and provide higher thermal stability up to at least 400° C. The SAF and SyF structures have a FL1/DL1/spacer/DL2/FL2 configuration wherein FL1 and FL2 are free layers with PMA, the coupling layer induces antiferromagnetic or ferrimagnetic coupling between FL1 and FL2 depending on thickness, and DL1 and DL2 are dusting layers that enhance the coupling between FL1 and FL2. The SAF free layer may be used with a SAF reference layer in STT-MRAM memory elements or in spintronic devices including a spin transfer oscillator. Furthermore, a dual SAF structure is described that may provide further advantages in terms of Ho, PMA, and thermal stability. 1. A magnetic device having thermal stability to at least 400° C. , comprising:(a) a synthetic antiferromagnetic (SAF) free layer that has a FL1/DL1/first coupling layer/DL2/FL2 configuration wherein FL1 and FL2 are free layers exhibiting perpendicular magnetic anisotropy, the first coupling layer is a non-magnetic metal that induces RKKY (antiferromagnetic) coupling between the FL1 and FL2 layers, and DL1 and DL2 are Co, Fe, Ni, CoNiFe, or NiFe dusting layers that enhance the RKKY coupling between FL1 and FL2;(b) a synthetic antiferromagnetic (SAF) reference layer that has a RL1/DL5/second coupling layer/DL6/RL2 configuration wherein RL1 and RL2 are reference layers exhibiting perpendicular magnetic anisotropy, the second coupling layer is a non-magnetic metal that induces RKKY (antiferromagnetic) coupling between the RL1 and RL2 layers, and DL5 and DL6 are Co, Fe, Ni, CoNiFe, or NiFe dusting layers that enhance the RKKY coupling between RL1 and RL2; and(c) a non-magnetic spacer formed between the SAF reference layer and SAF free layer wherein the FL1 layer contacts a top surface of the non-magnetic spacer that is a tunnel barrier layer ...

Hybridized oxide capping layer for perpendicular magnetic anisotropy

A method of forming a hybrid oxide capping layer (HOCL) is disclosed and used in a magnetic tunnel junction to enhance thermal stability and perpendicular magnetic anisotropy in an adjoining free layer. The HOCL has a lower interface oxide layer and one or more transition metal oxide layers wherein each of the metal layers selected to form a transition metal oxide has an absolute value of free energy of oxide formation less than that of the metal used to make the interface oxide layer. One or more of the HOCL layers is under oxidized. Oxygen from one or more transition metal oxide layers preferably migrates into the interface oxide layer during annealing to further oxidize the interface oxide. As a result, a less strenuous oxidation step is required to initially oxidize the lower HOCL layer and minimizes oxidative damage to the free layer.

PANCAKES LENS ASSEMBLY

A pancake lens assembly includes a partially reflective mirror, a reflective polarizer, a quarter waveplate, a polarization-dependent optical device, and at least one polarization controller. When a light beam is introduced into the pancake lens assembly along an optical axis in a Z direction to pass through the polarization controller in a first state, a polarization direction of the light beam is converted by the polarization controller. When the light beam is introduced into the pancake lens assembly along the optical axis to pass through the polarization controller in a second state, the polarization direction of the light beam is prevented from being converted by the polarization controller.

Raising Programming Currents of Magnetic Tunnel Junctions Using Word Line Overdrive and High-k Metal Gate

A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector.

PHYSICAL CLEANING WITH IN-SITU DIELECTRIC ENCAPSULATION LAYER FOR SPINTRONIC DEVICE APPLICATION

A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode in a substrate. The MTJ stack is etched to form a MTJ structure wherein portions of sidewalls of the MTJ structure are damaged by the etching. Thereafter, the substrate is removed from an etching chamber wherein sidewalls of the MTJ structure are oxidized. A physical cleaning of the MTJ structure removes damaged portions and oxidized portions of the MTJ sidewalls. Thereafter, without breaking vacuum, an encapsulation layer is deposited on the MTJ structure and bottom electrode. 1. A method comprising:etching a stack of magnetic tunneling junction (MTJ) layers to form a patterned MTJ stack, wherein the etching of the stack of MTJ layers includes using an etchant gas selected from the group consisting of carbon monoxide and ammonia and wherein a portion of the patterned MTJ stack is damaged via the etching;removing the damaged portion of the patterned MTJ stack in a vacuum environment; andafter removing the damaged portion of the patterned MTJ stack, forming an encapsulation layer on the patterned MTJ device stack in the vacuum environment.2. The method of claim 1 , wherein the removing of the damaged portion of the patterned MTJ stack in the vacuum environment includes applying a physical cleaning process to remove the portion of the patterned MTJ stack.3. The method of claim 2 , wherein the applying of the physical cleaning process includes performing a plasma cleaning process.4. The method of claim 2 , wherein the applying of the physical cleaning process includes performing an ion beam etching process.5. The method of claim 4 , wherein the ion beam etching process includes applying a non-reactive gas.6. The method of claim 5 , wherein the non-reactive gas is selected from the group consisting of nitrogen and argon.7. The method of claim 1 , further comprising forming the stack of MTJ layers over a substrate stage claim 1 , ...

Self-Aligned Encapsulation Hard Mask to Separate Physically Under-Etched MTJ Cells to Reduce Conductive R-Deposition

A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure. 1. A method for fabricating a magnetic tunneling junction (MTJ) structure comprising:depositing a MTJ stack on a bottom electrode wherein said MTJ stack comprises at least a pinned layer, a barrier layer on said pinned layer, and a free layer on said barrier layer;depositing a top electrode layer on said MTJ stack;depositing a hard mask on said top electrode layer;first etching said top electrode layer and said hard mask;thereafter second etching said MTJ stack not covered by said hard mask and stopping said etching at or within said pinned layer;thereafter depositing an encapsulation layer over partially etched said MTJ stack and etching away said encapsulation layer on horizontal surfaces leaving a self-aligned hard mask on sidewalls of said partially etched MTJ stack;thereafter third etching remaining said MTJ stack not covered by said hard mask and said self-aligned hard mask to complete said MTJ structure.2. The method according to wherein said top electrode layer comprises Ta claim 1 , TaN claim 1 , Ti claim 1 , TiN claim 1 , W claim 1 , Cu claim 1 , Mg claim 1 , Ru claim 1 , Cr claim 1 , Co claim 1 , Fe claim 1 , Ni or ...

Vibration-actuated micro mirror device

A vibration-actuated micro mirror device comprises a substrate, a swinging frame, a reflection mirror, and a vibration part. The swinging frame is rotatably arranged within a first accommodating space formed on the substrate. The reflection mirror is rotatably arranged within a second accommodating space formed on the swinging frame. The vibration part further comprises a plate coupled to the substrate, and a first and a second vibration structures. The first and the second vibration structures are coupled to the plate and are spaced a distance away from each other, wherein the first vibration structure receives a first driving signal having a first frequency and the second vibration structure receives a second driving signal having a second frequency smaller than the first frequency, thereby enabling the swinging frame to rotate about the first axis while enabling the reflection mirror to rotate about the second axis.

Programming MRAM cells using probability write

A method of writing a magneto-resistive random access memory (MRAM) cell includes providing a writing pulse to write a value to the MRAM cell; and verifying a status of the MRAM cell immediately after the step of providing the first writing pulse. In the event of a write failure, the value is rewritten into the MRAM cell.

EXTRA DOPED REGION FOR BACK-SIDE DEEP TRENCH ISOLATION

The present disclosure relates to a CMOS image sensor having a doped region, arranged between deep trench isolation structures and an image sensing element, and an associated method of formation. In some embodiments, the CMOS image sensor has a pixel region disposed within a semiconductor substrate. The pixel region has an image sensing element configured to convert radiation into an electric signal. A plurality of back-side deep trench isolation (BDTI) structures extend into the semiconductor substrate on opposing sides of the pixel region. A doped region is laterally arranged between the BDTI structures and separates the image sensing element from the BDTI structures and the back-side of the semiconductor substrate. Separating the image sensing element from the BDTI structures prevents the image sensing element from interacting with interface defects near edges of the BDTI structures, and thereby reduces dark current and white pixel number. 1. A CMOS image sensor , comprising:a pixel region disposed within a semiconductor substrate and comprising an image sensing element configured to convert radiation into an electrical signal;a plurality of back-side deep trench isolation (BDTI) structures extending from a back-side of the semiconductor substrate to positions within the semiconductor substrate located on opposing sides of the pixel region; anda doped region laterally arranged between the plurality of BDTI structures.2. The image sensor of claim 1 ,wherein the image sensing element comprises a photodiode having a first region with a first doping type and a second region with a second doping type that is different than the first doping type; andwherein opposing sides of the first region contact the doped region.3. The image sensor of claim 2 , wherein the doped region comprises a p-type region that vertically abuts the first region of the photodiode.4. The image sensor of claim 1 , wherein the doped region has a doping concentration that is greater than ...

Extra doped region for back-side deep trench isolation

The present disclosure, in some embodiments, relates to a CMOS image sensor. The CMOS image sensor has an image sensing element disposed within a substrate. A plurality of isolation structures are arranged along a back-side of the substrate and are separated from opposing sides of the image sensing element by non-zero distances. A doped region is laterally arranged between the plurality of isolation structures. The doped region is also vertically arranged between the image sensing element and the back-side of the substrate. The doped region physically contacts the image sensing element.

Hand-held cracker snap spraying projectile

A hand-held cracker snap for spraying projectile includes a main unit, a button, a disk, an air cylinder and a nozzle. The button is loosely disposed in the main unit. The disk is disposed in the main unit and is connected to the button. The air cylinder is disposed in the main unit and is provided with a central tube that can be extended or compressed along an axis repeatedly to suck or squeeze air to or from the air cylinder. The nozzle is a tubular element in the connecting pipe. An end of the nozzle is connected to the interior part of the air cylinder, allowing air to enter or exit the air cylinder via the nozzle. The nozzle guides air into the bullet.

Free layer structure in magnetic random access memory (MRAM) for Mo or W perpendicular magnetic anisotropy (PMA) enhancing layer

A perpendicularly magnetized magnetic tunnel junction (p-MTJ) is disclosed wherein a free layer (FL) has a first interface with a MgO tunnel barrier, a second interface with a Mo or W Hk enhancing layer, and is comprised of FexCoyBz wherein x is 66-80, y is 5-9, z is 15-28, and (x+y+z)=100 to simultaneously provide a magnetoresistive ratio >100%, resistance x area product <5 ohm/μm2, switching voltage <0.15V (direct current), and sufficient Hk to ensure thermal stability to 400° C. annealing. The FL may further comprise one or more M elements such as O or N to give (FexCoyBz)wM100-w where w is >90 atomic %. Alternatively, the FL is a trilayer with a FeB layer contacting MgO to induce Hk at the first interface, a middle FeCoB layer for enhanced magnetoresistive ratio, and a Fe or FeB layer adjoining the Hk enhancing layer to increase thermal stability.

Post Treatment to Reduce Shunting Devices for Physical Etching Process

A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.

Free layer with out-of-plane anisotropy for magnetic device applications

Synthetic antiferromagnetic (SAF) and synthetic ferrimagnetic (SyF) free layer structures are disclosed that reduce Ho (for a SAF free layer), increase perpendicular magnetic anisotropy (PMA), and provide higher thermal stability up to at least 400° C. The SAF and SyF structures have a FL1/DL1/spacer/DL2/FL2 configuration wherein FL1 and FL2 are free layers with PMA, the coupling layer induces antiferromagnetic or ferrimagnetic coupling between FL1 and FL2 depending on thickness, and DL1 and DL2 are dusting layers that enhance the coupling between FL1 and FL2. The SAF free layer may be used with a SAF reference layer in STT-MRAM memory elements or in spintronic devices including a spin transfer oscillator. Furthermore, a dual SAF structure is described that may provide further advantages in terms of Ho, PMA, and thermal stability.

Metal-insulator-metal structure and method of forming the same

A method of manufacturing a semiconductor device includes forming a metal-insulator-metal (MIM) device having a metal organic chemical vapor deposited (MOCVD) lower electrode and an atomic layer deposited (ALD) upper electrode.

Metal/dielectric/metal hybrid hard mask to define ultra-large height top electrode for sub 60nm MRAM devices

An ultra-large height top electrode for MRAM is achieved by employing a novel thin metal/thick dielectric/thick metal hybrid hard mask stack. Etching parameters are chosen to etch the dielectric quickly but to have an extremely low etch rate on the metals above and underneath. Because of the protection of the large thickness of the dielectric layer, the ultra-large height metal hard mask is etched with high integrity, eventually making a large height top electrode possible.

Low resistance MgO capping layer for perpendicularly magnetized magnetic tunnel junctions

A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a first metal oxide (Mox) layer and second metal oxide (tunnel barrier) to produce perpendicular magnetic anisotropy (PMA) in the FL. In some embodiments, conductive metal channels made of a noble metal are formed in the Mox that is MgO to reduce parasitic resistance. In a second embodiment, a discontinuous MgO layer with a plurality of islands is formed as the Mox layer and a non-magnetic hard mask layer is deposited to fill spaces between adjacent islands and form shorting pathways through the Mox. In another embodiment, end portions between the sides of a center Mox portion and the MTJ sidewall are reduced to form shorting pathways by depositing a reducing metal layer on Mox sidewalls, or performing a reduction process with forming gas, H2, or a reducing species.

High Thermal Stability Free Layer with High Out-of-Plane Anisotropy for Magnetic Device Applications

A CoFeB or CoFeNiB magnetic layer wherein the boron content is 25 to 40 atomic % and with a thickness <20 Angstroms is used to achieve high perpendicular magnetic anisotropy and enhanced thermal stability in magnetic devices. A dusting layer made of Co, Ni, Fe or alloy thereof is added to top and bottom surfaces of the CoFeB layer to increase magnetoresistance as well as improve Hc and Hk. Another embodiment includes a non-magnetic metal insertion in the CoFeB free layer. The CoFeB layer with elevated B content may be incorporated as a free layer, dipole layer, or reference layer in STT-MRAM memory elements or in spintronic devices including a spin transfer oscillator. Thermal stability is increased such that substantial Hk is retained after annealing to at least 400° C. for 1 hour. Ku enhancement is achieved and the retention time of a memory cell for STT-MRAM designs is increased. 1. A multilayer stack in a magnetic device , comprising:(a) a reference layer;{'sub': R', 'S', 'W', 'T, '(b) a free layer containing at least a layer with a CoFeNiBcomposition wherein R, S, W, and T are the content of Co, Fe, Ni, and B respectively, R+S+W+T=100, S>(R+W), and T is from about 25 to 40 atomic %, the free layer maintains perpendicular magnetic anisotropy (PMA) after thermal treatment to above 400° C.; and'}(c) a tunnel barrier layer formed between the reference layer and free layer.2. The multilayer stack of wherein the layer with a CoFeNiBcomposition has a thickness from about 5 to 20 Angstroms.3. The multilayer stack of further comprised of one or more dusting layers each having a thickness from about 5 to 10 Angstroms and made of Co claim 1 , Fe claim 1 , Ni claim 1 , or alloys thereof including CoFe claim 1 , CoTa claim 1 , CoZr claim 1 , CoHf claim 1 , CoMg claim 1 , CoNb claim 1 , CoB claim 1 , or FeBwhere v is from 0 to 40 atomic % claim 1 , at least one dusting layer contacts a bottom surface of the free layer claim 1 , or at least one dusting layer contacts a top ...

Sub 60nm Etchless MRAM Devices by Ion Beam Etching Fabricated T-Shaped Bottom Electrode

A first conductive layer is patterned and trimmed to form a sub 30 nm conductive via on a first bottom electrode. The conductive via is encapsulated with a first dielectric layer and planarized to expose a top surface of the conductive via. A second conductive layer is deposited over the first dielectric layer and the conductive via. The second conductive layer is patterned to form a sub 60 nm second conductive layer wherein the conductive via and second conductive layer together form a T-shaped second bottom electrode. MTJ stacks are deposited on the T-shaped second bottom electrode and on the first bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and planarized to expose a top surface of the MTJ stack on the T-shaped second bottom electrode. A top electrode contacts the MTJ stack on the T-shaped second bottom electrode plug.

Under-cut via electrode for sub 60 nm etchless MRAM devices by decoupling the via etch process

A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A first dielectric layer is deposited on a bottom electrode and partially etched through to form a first via opening having straight sidewalls, then etched all the way through to the bottom electrode to form a second via opening having tapered sidewalls. A metal layer is deposited in the second via opening and planarized to the level of the first dielectric layer. The remaining first dielectric layer is removed leaving an electrode plug on the bottom electrode. MTJ stacks are deposited on the electrode plug and on the bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and polished to expose a top surface of the MTJ stack on the electrode plug. A top electrode layer is deposited to complete the MTJ structure.

Avoiding Oxygen Plasma Damage During Hard Mask Etching in Magnetic Tunnel Junction (MTJ) Fabrication Process

An etch process flow for forming magnetic tunnel junction (MTJ) cells with enhanced throughput that also increases the magnetoresistive ratio and decreases critical dimension (CD) variation is disclosed. A photoresist pattern is formed on a dielectric antireflective coating (DARC), which contacts a top surface of a hard mask (HM) that is an uppermost MTJ layer. After a first ion beam etch (IBE) or reactive ion etch (RIE) transfers the pattern through the DARC, a second etch is used to transfer the pattern through the HM. The second etch includes an oxidant to passivate the pattern sidewalls and completely removes the photoresist layer because of one or both of a thicker DARC and thicker HM than in conventional processing. Accordingly, an oxygen etch typically used to remove the photoresist after the HM etch is avoided and thereby provides improved MTJ performance, especially for CDs<60 nm. 1. A method of etching a magnetic tunnel junction (MTJ) stack of layers , comprising:providing a MTJ stack of layers on a first electrode wherein the MTJ stack of layers includes a hard mask (HM) on a first stack of layers, and forming a second stack of layers comprising a dielectric antireflective coating (DARC) with a first thickness on the HM, and a photoresist layer on the DARC;forming a pattern with a critical dimension (CD) in the photoresist layer and transferring the pattern through the DARC with a first etch process that is an ion beam etch (IBE) or a reactive ion etch (RIE) wherein the pattern after the first etch process includes at least a sidewall that extends from a top surface of the DARC to a top surface of the HM;performing a second etch that is an IBE or RIE wherein the pattern in the DARC is transferred through the HM, and wherein the first thickness is sufficiently large such that the photoresist layer is entirely removed before the end of the second etch, and the sidewall extends from a DARC top surface to a top surface of the first stack of layers, and ...

Post Treatment to Reduce Shunting Devices for Physical Etching Process

A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.

Telescopic pneumatic device

A telescopic pneumatic device comprises an outer cylinder, an inner cylinder disposed in the outer cylinder and having a cylinder wall defining an air chamber, a piston mounted in the air chamber and having a piston rod connected thereto, a flow passage provided between the cylinder wall and the outer cylinder, and a control valve operable to permit or interrupt fluid communication between the flow passage and the air chamber. The inner cylinder is made of a rigid plastic material and includes a valve mounting part for receiving the control valve, the valve mounting part being formed in one piece with the cylinder wall.

Door closer

A door closer includes a closer casing, a pivot unit, and a length-variable damping cylinder. The pivot unit includes a pivot axle, a cam member, and a cam follower member. The pivot axle has a drive end portion that extends into and that is retained rotatably in the closer casing, and a coupling end portion that extends out of the closer casing. The cam member is mounted co-rotatably on the drive end portion of the pivot axle. The cam follower member is disposed in the closer casing, and is acted upon by the cam member. The damping cylinder is disposed in the closer casing, and has one end coupled to the cam follower member and an opposite end anchored to the closer casing.

Magnetic tunnel junction (MTJ) performance by introducing oxidants to methanol with or without noble gas during MTJ etch

A process flow for forming magnetic tunnel junctions (MTJs) with minimal sidewall residue and reduced low tail population is disclosed wherein a pattern is first formed in a hard mask that is an uppermost MTJ layer. Thereafter, the hard mask pattern is etch transferred through the underlying MTJ layers including a reference layer/tunnel barrier/free layer stack. The etch transfer may be completed in a single RIE step based on a first flow rate of O2 and a second flow rate of an oxidant such as CH3OH where the CH3OH/O2 ratio is at least 7.5:1. The RIE may also include a flow rate of a noble gas. In other embodiments, a chemical treatment with an oxidant such as CH3OH, and a volatilization at 50° C. to 450° C. may follow an etch transfer through the MTJ stack when the ion beam etch or plasma etch involves noble gas ions.

Under-Cut Via Electrode for Sub 60nm Etchless MRAM Devices by Decoupling the Via Etch Process

A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A first dielectric layer is deposited on a bottom electrode and partially etched through to form a first via opening having straight sidewalls, then etched all the way through to the bottom electrode to form a second via opening having tapered sidewalls. A metal layer is deposited in the second via opening and planarized to the level of the first dielectric layer. The remaining first dielectric layer is removed leaving an electrode plug on the bottom electrode. MTJ stacks are deposited on the electrode plug and on the bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and polished to expose a top surface of the MTJ stack on the electrode plug. A top electrode layer is deposited to complete the MTJ structure.

Method and related apparatus for image de-interlacing

An image de-interlacing method comprises: (a) defining a first threshold value and a second threshold value, wherein the second threshold value is larger than the first threshold value; (b) generating a parameter according to motion level of a interlaced image; and (c) utilizing a first interpolation method and a second interpolation method to jointly process the interlaced image if the parameter is in a range between the first threshold value and the second threshold value.

Monolayer-By-Monolayer Growth of MgO Layers using Mg Sublimation and Oxidation

A MgO layer is formed using a process flow wherein a Mg layer is deposited at a temperature <200° C. on a substrate, and then an anneal between 200° C. and 900° C., and preferably from 200° C. and 400° C., is performed so that a Mg vapor pressure >10Torr is reached and a substantial portion of the Mg layer sublimes and leaves a Mg monolayer. After an oxidation between −223° C. and 900° C., a MgO monolayer is produced where the Mg:O ratio is exactly 1:1 thereby avoiding underoxidized or overoxidized states associated with film defects. The process flow may be repeated one or more times to yield a desired thickness and resistance x area value when the MgO is a tunnel barrier or Hk enhancing layer. Moreover, a doping element (M) may be added during Mg deposition to modify the conductivity and band structure in the resulting MgMO layer. 1. A method of forming a MgO layer having a 1:1 Mg:O ratio , comprising:(a) sputter depositing a first Mg layer on a substrate;{'sup': '−6', '(b) performing a first anneal at a first temperature between 200° C. and 900° C. in a first chamber such that a Mg vapor pressure reaches at least 10Torr and a substantial portion of the first Mg layer sublimes thereby leaving a first Mg monolayer on the substrate; and'}(c) performing a first oxidation at a second temperature between −223° C. and 900° C. by exposing the first Mg monolayer to oxygen or an oxygen species and thereby forming a first MgO monolayer with a 1:1 Mg:O ratio.2. The method of wherein the first Mg layer is deposited at a third temperature less than 200° C. claim 1 , and the sputter deposition of the first Mg layer is performed in a chamber different from the first chamber.3. The method of wherein sputter depositing the first Mg layer is performed at essentially the first temperature so that sputter deposition of the first Mg layer and the first anneal are both accomplished in the first chamber.4. The method of further comprising:(a) sputter depositing a second Mg layer on the ...

Self-adaptive halogen treatment to improve photoresist pattern and magnetoresistive random access memory (MRAM) device uniformity

A process flow for shrinking a critical dimension (CD) in photoresist features and reducing CD non-uniformity across a wafer is disclosed. A photoresist pattern is treated with halogen plasma to form a passivation layer with thickness (t1) on feature sidewalls, and thickness (t2) on the photoresist top surface where t2>t1. Thereafter, an etch based on O2, or O2 with a fluorocarbon or halogen removes the passivation layer and shrinks the CD. The passivation layer slows the etch such that photoresist thickness is maintained while CD shrinks to a greater extent for features having a width (d1) than on features having width (d2) where d1>d2. Accordingly, CD non-uniformity is reduced from 2.3% to 1% when d2 is 70 nm and is shrunk to 44 nm after the aforementioned etch. After a second etch through a MTJ stack to form MTJ cells, CD non-uniformity is maintained at 1%.

MTJ CD variation by HM trimming

A MTJ stack is deposited on a bottom electrode. A metal hard mask is deposited on the MTJ stack and a dielectric mask is deposited on the metal hard mask. A photoresist pattern is formed on the dielectric mask, having a critical dimension of more than about 65 nm. The dielectric and metal hard masks are etched wherein the photoresist pattern is removed. The dielectric and metal hard masks are trimmed to reduce their critical dimension to 10-60 nm and to reduce sidewall surface roughness. The dielectric and metal hard masks and the MTJ stack are etched wherein the dielectric mask is removed and a MTJ device is formed having a small critical dimension of 10-60 nm, and having further reduced sidewall surface roughness.

Multiply spin-coated ultra-thick hybrid hard mask for sub 60nm MRAM devices

A metal hard mask layer is deposited on a MTJ stack on a substrate. A hybrid hard mask is formed on the metal hard mask layer, comprising a plurality of spin-on carbon layers alternating with a plurality of spin-on silicon layers wherein a topmost layer of the hybrid hard mask is a silicon layer. A photo resist pattern is formed on the hybrid hard mask. First, the topmost silicon layer of the hybrid hard mask is etched where is it not covered by the photo resist pattern using a first etching chemistry. Second, the hybrid hard mask is etched where it is not covered by the photo resist pattern wherein the photoresist pattern is etched away using a second etch chemistry. Thereafter, the metal hard mask and MTJ stack are etched where they are not covered by the hybrid hard mask to form a MTJ device and overlying top electrode.

MRAM cell structure

Disclosed herein is an improved memory device, and related methods of manufacturing, wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and instead forming a conductive via structure that provides the electrical connection from the memory stack or device in the structure to an under-metal layer. By forming only this via structure, rather than separate vias formed on either side of a landing pad, the overall width occupied by the connective via structure from the memory stack to an under-metal layer is substantially reduced, and thus the via structure and under-metal layer may be formed closer to the memory stack (or conductors associated with the stack) so as to reduce the overall width of the cell structure.

Telescopic pneumatic device

A telescopic pneumatic device comprises an outer cylinder, an inner cylinder disposed in the outer cylinder and having a cylinder wall defining an air chamber, a piston mounted in the air chamber and having a piston rod connected thereto, a flow passage provided between the cylinder wall and the outer cylinder, and a control valve operable to permit or interrupt fluid communication between the flow passage and the air chamber. The inner cylinder is made of a rigid plastic material and includes a valve mounting part for receiving the control valve, the valve mounting part being formed in one piece with the cylinder wall.

Multi-mode operation method for capacitive touch panel

A multi-mode operation method for a capacitive touch panel includes the steps of: using an initial mutual capacitance value of the panel as a reference value; obtaining a new mutual capacitance value as an original value after the initial step; comparing the original value with the reference value to obtain a detection value; comparing a current detection value with a previous detection value to obtain a first comparison result; when a touch cell has a detection value smaller than 0 if any of other touch cells in the vertical direction and the horizontal direction of the touch cell has a detection value greater than an effective touch standard value, obtaining a calculated value according to the detection value of the touch cell and an absolute value of the touch cell, as the detection value of the touch cell; and selecting between a normal mode and a waterproof mode as the operation mode according to the first comparison result and the detection values of all the touch cells.

Combined physical and chemical etch to reduce magnetic tunnel junction (MTJ) sidewall damage

A process flow for forming magnetic tunnel junction (MTJ) nanopillars with minimal sidewall residue and minimal sidewall damage is disclosed wherein a pattern is first formed in a hard mask that is an uppermost MTJ layer. Thereafter, the hard mask sidewall is etch transferred through the remaining MTJ layers including a reference layer, free layer, and tunnel barrier between the free layer and reference layer. The etch transfer may be completed in a single RIE step that features a physical component involving inert gas ions or plasma, and a chemical component comprised of ions or plasma generated from one or more of methanol, ethanol, ammonia, and CO. In other embodiments, a chemical treatment with one of the aforementioned chemicals, and a volatilization at 50° C. to 450° C. may follow an etch transfer through the MTJ stack with an ion beam etch or plasma etch involving inert gas ions.

STT-MRAM Reference Layer Having Substantially Reduced Stray Field and Consisting of a Single Magnetic Domain

An STT MTJ cell is formed with a magnetic anisotropy of its free and reference layers that is perpendicular to their planes of formation. The reference layer of the cell is an SAF multilayered structure with a single magnetic domain to enhance the bi-stability of the magnetoresistive states of the cell. The free layer of the cell is etched back laterally from the reference layer, so that the fringing stray field of the reference layer is no more than 15% of the coercivity of the free layer and has minimal effect on the free layer. 1. An STT MTJ cell comprising:a seed layer;a reference layer formed on said seed layer;a tunneling barrier layer formed on said reference layer;a free layer formed on said tunneling barrier layer;a capping layer formed on said free layer; whereina width of said free layer is less than a width of said reference layer; and{'sub': '0', 'said reference layer is formed as a magnetically coupled multi-layer layer or comprises PMA L1tetragonal alloys and wherein'}said free layer and said reference layer have a magnetic anisotropy that is oriented perpendicular to their planes of formation; and whereina stray field of said reference layer is substantially limited to a fringing field at its opposite lateral edges, whereby said stray field does not affect the magnetization of said free layer; and whereina domain state of said reference layer is formed to promote well defined magnetoresistive bi-stability.2. The of wherein a lateral width of said reference layer is substantially larger than a lateral width of said free layer claim 1 , whereby the strength of a stray field of said reference layer is less than approximately 15% of a coercivity of said free layer and whereby said stray field will affect the magnetization of said free layer minimally or not at all.3. The cell of wherein a lateral width of said reference layer is between approximately 50 nm and 500 nm.4. The cell of wherein a lateral width of said free layer is between approximately 20 nm ...

IMAGE PROCESSING APPARATUS AND ASSOCIATED METHOD

An image processing apparatus includes a first memory, a second memory, a buffer, a fetching module and a processing module. The first memory module stores an original image having a first width. The buffer has a second width smaller than the first width. The fetching module fetches a sub-image of the original image from the first memory and stores the fetched sub-image into the buffer. The processing module performs an image processing process on the sub-image stored in the buffer to generate a processed sub-image. The processed sub-image is then stored into the second memory. 1. An image processing apparatus , comprising:a first memory, for storing an original image having a first width;a second memory;a buffer, having a second width smaller than the first width;a fetching module, for fetching a sub-image of the original image from the first memory and storing the sub-image into the buffer; wherein a width of the sub-image is smaller than or equal to the second width; anda processing module, for performing an image processing process on the sub-image image to generate a processed sub-image, and storing the processed sub-image into the second memory.2. The apparatus according to claim 1 , wherein the sub-image comprises P number of rows of pixels claim 1 , the processed sub-image comprises R number of rows of pixels claim 1 , P and R are respectively positive integers claim 1 , and R is smaller than or equal to P.3. The apparatus according to claim 1 , wherein the original image comprises N number of sub-images claim 1 , each of the sub-images having the width smaller than the second width claim 1 , and N is an integer greater than 1; and the fetching module sequentially fetches the N sub-images from the first memory to the buffer for processing of the processing module.4. The apparatus according to claim 3 , wherein the processing module combines the N number of processed sub-images to a processed image corresponding to the original image in the second memory.5. ...

HEIGHT ADJUSTABLE ARMREST ASSEMBLY FOR A CHAIR

An armrest assembly includes a lower part defining a lower chamber, and an upper part defining an upper chamber therein. An abutting member is disposed in the upper chamber. A cylinder-and-piston unit includes a cylinder extending into the upper chamber to abut against the abutting member, and a piston mounted securely in the lower chamber and telescopically extending into the cylinder. A locking member includes a spring-biased button projecting from the cylinder, extending through the abutting member and into the upper chamber, and pressible to move between a locked position, in which, the cylinder is locked by the locking member against axial movement relative to the piston, and an unlocked position, in which, the cylinder is axially movable relative to the piston.

Image sensor with reduced optical path

Among other things, one or more image sensors and techniques for forming image sensors are provided. An image sensor comprises a photodiode array configured to detect light. The image sensor comprises an oxide grid comprising a first oxide grid portion and a second oxide grid portion. A metal grid is formed between the first oxide grid portion and the second oxide grid portion. The oxide grid and the metal grid define a filler grid. The filler grid comprises a filler grid portion, such as a color filter, that allows light to propagate through the filler gird portion to an underlying photodiode. The oxide grid and the metal grid confine or channel the light within the filler gird portion. The oxide grid and the metal grid are formed such that the filler grid provides a relatively shorter propagation path for the light, which improves light detection performance of the image sensor.

Silicon Oxynitride Based Encapsulation Layer for Magnetic Tunnel Junctions

A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a ° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a NO:silane flow rate ratio of at least 1:1 but less than 15:1. A NO plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs. 1. A method comprising:forming a first magnetic tunnel junction (MTJ) and a second MTJ over a bottom electrode; and [{'sub': X1', 'Y1', 'Z1, 'a first sub-layer physically contacting the sidewalls of the first MTJ and the second MTJ, the first sub-layer further physically contacting the bottom electrode, the first sub-layer having a SiONcomposition; and'}, {'sub': X2', 'Y2', 'Z2', '1', '2', '1', '2', '1', '2, 'a second sub-layer disposed on the first sub-layer, the second sub-layer having a SiONcomposition, wherein xand xare a Si content in the first and second sub-layers, respectively, wherein x>x, and wherein zand zare a N content in the first sub-layer and the second sub-layer, respectively.'}], 'forming a first encapsulation layer over sidewalls of the first MTJ and the second MTJ, the first encapsulation layer including2. The method of claim 1 , wherein the second sub-layer interfaces with the first sub-layer.3. The method of claim 1 , wherein the forming of the first encapsulation layer over sidewalls of the first MTJ and the second MTJ includes forming the first sub-layer ...

Multilayer Structure for Reducing Film Roughness in Magnetic Devices

A seed layer stack with a uniform top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer on a smoothing layer such as Mg where the latter has a resputtering rate 2 to 30× that of the amorphous layer. The seed layer stack may be repeated to give a laminate of two amorphous layers and two smoothing layers, and is advantageous for enhancing performance in magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. A template layer such as NiCr may be formed on the uppermost smoothing layer to promote and maintain perpendicular magnetic anisotropy in an overlying magnetic layer during high temperature processing up to 400° C. The amorphous seed layer is SiN, TaN, or CoFeM where M is B or another element with a content that makes CoFeM amorphous as deposited. 1. A multilayer structure for reducing film roughness in a magnetic device , comprising:(a) a buffer layer that is one or more of Zr, ZrN, Nb, NbN, Mo, MoN, TiN, W, WN, and Ru, or one of more of the aforementioned materials with Ta or TaN that is formed on a substrate;{'b': 1', '1, '(b) a first smoothing (S) layer made of a material with a first bond energy, and having a first surface with an “as deposited” first peak to peak roughness, the S layer is formed on the buffer layer;'}{'b': 2', '2', '1', '1', '2', '2, '(c) a second smoothing (S) layer that is non-crystalline or nano-crystalline and is made of a material with a second bond energy that is greater than the first bond energy such that deposition of the S layer results in resputtering of the S layer to give a S layer with a second surface having a second peak to peak roughness substantially less than the “as deposited” first peak to peak roughness, and the S layer formed on the second surface, the S layer has a third surface with the second peak to peak roughness;'}{'b': 3', '2, '(d) a third smoothing (S) layer with the first bond energy that is formed on the S layer; and'}{'b': 4 ...

Low Resistance MgO Capping Layer for Perpendicularly Magnetized Magnetic Tunnel Junctions

A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a first metal oxide (Mox) layer and second metal oxide (tunnel barrier) to produce perpendicular magnetic anisotropy (PMA) in the FL. In some embodiments, conductive metal channels made of a noble metal are formed in the Mox that is MgO to reduce parasitic resistance. In a second embodiment, a discontinuous MgO layer with a plurality of islands is formed as the Mox layer and a non-magnetic hard mask layer is deposited to fill spaces between adjacent islands and form shorting pathways through the Mox. In another embodiment, end portions between the sides of a center Mox portion and the MTJ sidewall are reduced to form shorting pathways by depositing a reducing metal layer on Mox sidewalls, or performing a reduction process with forming gas, H2, or a reducing species.

Vibration-actuated micro mirror device

The present invention provides a vibration-actuated micro mirror device comprising a substrate having a swinging frame and a reflection mirror, and a vibration part having a first and a second vibration structures coupled to the substrate, wherein the first vibration structure is driven to generate a first complex wave formed by a first and a second wave signals while the second vibration structure is driven to generate a second complex wave formed by a third and a fourth wave signals, and the first and the third wave signals are formed with the same frequency and phase while the second and the fourth wave signals are formed with the same frequency but opposite phases. The first and the second complex waves actuate the substrate such that the swinging frame is rotated about a first axis while the reflection mirror is rotated about a second axis.

MRAM cell structure

Disclosed herein is an improved memory device, and related methods of manufacturing, wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and instead forming a conductive via structure that provides the electrical connection from the memory stack or device in the structure to an under-metal layer. By forming only this via structure, rather than separate vias formed on either side of a landing pad, the overall width occupied by the connective via structure from the memory stack to an under-metal layer is substantially reduced, and thus the via structure and under-metal layer may be formed closer to the memory stack (or conductors associated with the stack) so as to reduce the overall width of the cell structure.

Image Sensor Comprising Reflective Guide Layer and Method of Forming the Same

Various structures of image sensors are disclosed, as well as methods of forming the image sensors. According to an embodiment, a structure comprises a substrate comprising photo diodes, an oxide layer on the substrate, recesses in the oxide layer and corresponding to the photo diodes, a reflective guide material on a sidewall of each of the recesses, and color filters each being disposed in a respective one of the recesses. The oxide layer and the reflective guide material form a grid among the color filters, and at least a portion of the oxide layer and a portion of the reflective guide material are disposed between neighboring color filters.

System for adjusting radiation target sites dynamically according to moving states of target object and for creating lookup table of the moving states

A system for adjusting radiation target sites dynamically according to the moving states of a target object and for creating a lookup table of the moving states includes a detection chip, a radiation generation device, and a lookup table. The detection chip can be fixed on the target object to detect the current moving state of the target object. The detection chip or the radiation generation device, both configured for wireless signal transmission to each other, can activate or deactivate the radiation emitters of the radiation generation device individually according to the current moving state of the target object and the contents of the lookup table. As the system uses wireless transmission, and the lookup table has recorded the working state of each radiation emitter in each moving state of the target object, radiotherapy can be performed without a large number of tubes or sensors.

OPTICAL SCANNING PROJECTION SYSTEM

An optical scanning projection system includes a scanning light source component, a second reflecting element, a transparent element, a scanning element, a photosensitive element and a control module. The transparent element receives a main light beam emitted by the scanning light source component and reflects a part of the main light beam to be a reflected light. The reflected light is reflected by the second reflecting element, and the scanning element reflects the reflected light from the second reflecting element in a scanning manner. The photosensitive element receives the reflected light from the scanning element and outputs a sensing signal, and the control module actuates or stops actuating the scanning light source component according to the sensing signal. Therefore, when the scanning element is damaged, the control module may instantly stop actuating the scanning light source component, thereby enhancing the using safety of the optical scanning projection system.

Physical Cleaning with In-situ Dielectric Encapsulation Layer for Spintronic Device Application

A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode in a substrate. The MTJ stack is etched to form a MTJ structure wherein portions of sidewalls of the MTJ structure are damaged by the etching. Thereafter, the substrate is removed from an etching chamber wherein sidewalls of the MTJ structure are oxidized. A physical cleaning of the MTJ structure removes damaged portions and oxidized portions of the MTJ sidewalls. Thereafter, without breaking vacuum, an encapsulation layer is deposited on the MTJ structure and bottom electrode. 1. A method for fabricating a magnetic tunneling junction (MTJ) structure comprising:providing a stack of MTJ layers on a bottom electrode in a substrate;patterning said MTJ stack to form a MTJ structure;thereafter removing said MTJ structure from an etching chamber wherein sidewalls of said MTJ structure are damaged;thereafter performing a physical cleaning on said MTJ structure wherein a damaged portion of said sidewalls is removed; andthereafter, without breaking vacuum, depositing an encapsulation layer on said MTJ structure and said bottom electrode.2. The method according to wherein said hard mask comprises metal or oxide or a combination of the two.3. The method according to wherein said MTJ stack is etched using reactive ion etching claim 1 , wherein sidewalls of said MTJ stack are damaged by said etching claim 1 , and wherein said after removing said MTJ structure from said etching chamber claim 1 , said sidewalls are oxidized causing further sidewall damage.4. The method according to wherein said physical cleaning comprises plasma cleaning or Ion Beam Etching.5. The method according to wherein said physical cleaning comprises Ion Beam Etching with nitrogen claim 1 , argon claim 1 , or other non-reactive gas.6. The method according to wherein said substrate is placed on a substrate stage and wherein said substrate stage is tilted between about 25° ...

Capacitive touch panel and touch position calculation method thereof

Disclosed is a capacitive touch panel having a circuitous conductor pattern structure. The capacitive touch panel contains a number of first axial conductor assemblies and a number of second axial conductor assemblies, wherein each second axial conductor assembly includes a number of second axial conductor cells which are composed of a number of bar shape figures with accordion shape or wave shape edges. Electrical fields and induced capacitors are generated between adjacent axial conductor assemblies with different directions when giving control signals. Then the touched position is detected. Circuitous conductor pattern increases the region of the first axial conductor assembly and the inducing range of electrical field, thus the amount of the axial conductor assemblies and conduction lines can be reduced.

Method to integrate MRAM devices to the interconnects of 30nm and beyond CMOS technologies

A complementary metal oxide semiconductor (CMOS) device comprises a first metal line, a first metal via on the first metal line, a magnetic tunneling junction (MTJ) device on the first metal via wherein the first metal via acts as a bottom electrode for the MTJ device, a second metal via on the MTJ device, and a second metal line on the second metal via.

Sub 60nm etchless MRAM devices by ion beam etching fabricated T-shaped bottom electrode

A first conductive layer is patterned and trimmed to form a sub 30 nm conductive via on a first bottom electrode. The conductive via is encapsulated with a first dielectric layer and planarized to expose a top surface of the conductive via. A second conductive layer is deposited over the first dielectric layer and the conductive via. The second conductive layer is patterned to form a sub 60 nm second conductive layer wherein the conductive via and second conductive layer together form a T-shaped second bottom electrode. MTJ stacks are deposited on the T-shaped second bottom electrode and on the first bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and planarized to expose a top surface of the MTJ stack on the T-shaped second bottom electrode. A top electrode contacts the MTJ stack on the T-shaped second bottom electrode plug.

Etch selectivity by introducing oxidants to noble gas during physical magnetic tunnel junction (MTJ) etching

A process flow for forming magnetic tunnel junction (MTJ) nanopillars with minimal sidewall residue and damage is disclosed wherein a pattern is first formed in a hard mask or uppermost MTJ layer. Thereafter, the hard mask sidewall is etch transferred through the remaining MTJ layers with a RIE process comprising main etch and over etch portions, and a cleaning step. The RIE process features noble gas and an oxidant that is one or more of CH3OH, C2H5OH, NH3, N2O, H2O2, H2O, O2, and CO. Noble gas/oxidant flow rate ratio during over etch may be greater than during main etch to avoid chemical damage to MTJ sidewalls. The cleaning step may comprise plasma or ion beam etch with the noble gas and oxidant mixture. Highest values for magnetoresistive ratio and coercivity (Hc) are observed for noble gas/oxidant ratios from 75:25 to 90:10, especially for MTJ nanopillar sizes ≤100 nm.

Door closer

A door closer includes a closer casing, a pivot unit, and a length-variable damping cylinder. The pivot unit includes a pivot axle, a cam member, and a cam follower member. The pivot axle has a drive end portion that extends into and that is retained rotatably in the closer casing, and a coupling end portion that extends out of the closer casing. The cam member is mounted co-rotatably on the drive end portion of the pivot axle. The cam follower member is disposed in the closer casing, and is acted upon by the cam member. The damping cylinder is disposed in the closer casing, and has one end coupled to the cam follower member and an opposite end anchored to the closer casing.

MRAM cell structure

Disclosed herein is an improved memory device, and related methods of manufacturing, wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and instead forming a conductive via structure that provides the electrical connection from the memory stack or device in the structure to an under-metal layer. By forming only this via structure, rather than separate vias formed on either side of a landing pad, the overall width occupied by the connective via structure from the memory stack to an under-metal layer is substantially reduced, and thus the via structure and under-metal layer may be formed closer to the memory stack (or conductors associated with the stack) so as to reduce the overall width of the cell structure.

MRAM device with continuous MTJ tunnel layers

A method for fabricating a magnetoresistive random access memory (MRAM) device having a plurality of memory cells includes: forming a fixed magnetic layer having magnetic moments fixed in a predetermined direction; forming a tunnel layer over the fixed magnetic layer; forming a free magnetic layer, having magnetic moments aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer; forming a hard mask on the free magnetic layer partially covering the free magnetic layer; and unmagnetizing portions of the free magnetic layer uncovered by the hard mask for defining one or more magnetic tunnel junction (MTJ) units.

Driving apparatus, driving method thereof, and scanning mirror

The disclosure provides a driving apparatus, a driving method thereof, and a scanning mirror. The scanning mirror includes an accumulator unit and a processor unit. The accumulator unit receives and adds up a frequency control word and a first accumulation value to generate a second accumulation value. The processor unit coupled to the accumulator unit receives the second accumulation value. The processor unit generates a driving signal according the second accumulation value and the preset value and adjusts the second accumulation value for outputting the first accumulation value.

MRAM cell structure

Disclosed herein is an improved memory device, and related methods of manufacturing, wherein the area occupied by a conventional landing pad is significantly reduced to around % to % of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and instead forming a conductive via structure that provides the electrical connection from the memory stack or device in the structure to an under-metal layer. By forming only this via structure, rather than separate vias formed on either side of a landing pad, the overall width occupied by the connective via structure from the memory stack to an under-metal layer is substantially reduced, and thus the via structure and under-metal layer may be formed closer to the memory stack (or conductors associated with the stack) so as to reduce the overall width of the cell structure. 1. A magnetoresistive random access memory (MRAM) structure , comprising:a magnetic tunnel junction (MTJ) stack having a bottom electrode and a top electrode;a conductive extender electrically connected to the bottom electrode and having an extended portion laterally extending from the MTJ stack, the MTJ stack formed on a main portion of the conductive extender;a write wordline configured to control a magnetic state of the MTJ stack formed directly under the MTJ stack and the main portion of the conductive extender;a switching device operated using a read wordline, the switching device configured to read the magnetic state of the MTJ stack;an under-metal layer electrically coupled to the switching device and formed partially under the extending portion and partially under the main portion of the conductive extender; anda via structure directly connecting the extending portion to the under-metal layer, and formed directly and laterally adjacent to the write wordline.2. An MRAM structure according to claim 1 , wherein the via structure comprises a first via directly connected to the under-metal ...

VIBRATION-ACTUATED MICRO MIRROR DEVICE

The present invention provides a vibration-actuated micro mirror device comprising a substrate having a swinging frame and a reflection mirror, and a vibration part having a first and a second vibration structures coupled to the substrate, wherein the first vibration structure is driven to generate a first complex wave formed by a first and a second wave signals while the second vibration structure is driven to generate a second complex wave formed by a third and a fourth wave signals, and the first and the third wave signals are formed with the same frequency and phase while the second and the fourth wave signals are formed with the same frequency but opposite phases. The first and the second complex waves actuate the substrate such that the swinging frame is rotated about a first axis while the reflection mirror is rotated about a second axis. 1. A vibration-actuated micro mirror device , comprising:a substrate, configured with a swinging frame and a reflection mirror while being formed with a slot; anda vibration part, configured with a first vibration structure and a second vibration structure in a manner that the first and the second vibration structures are disposed on the substrate respectively at two sides of the slot;wherein, the first vibration structure has ability to receive a first driving signal so as to generate a first complex wave formed by a first wave signal and a second wave signal; andthe second vibration structure has ability to receive a second driving signal to generate a second complex wave formed by a third wave signal and a fourth wave signal;wherein, the first wave signal and the third wave signal are formed with a same first frequency while the second wave signal and the fourth wave signal are formed with a same second frequency, andthe first and the second complex waves actuate the substrate for enabling the swinging frame to rotate about a first axis while enabling the reflection mirror to rotate about a second axis.2. The vibration- ...

Raising Programming Currents of Magnetic Tunnel Junctions Using Word Line Overdrive and High-k Metal Gate

A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector.

Co/Ni multilayers with improved out-of-plane anisotropy for magnetic device applications

A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni) n composition or the like where n is from 2 to 30. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications

A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)or (CoX)composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. A CoFeB layer may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer. 1. A magnetic element , comprising:(a) a seed layer comprising one or more of Hf, NiCr, and NiFeCr that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer; and{'sub': 'n', '(b) the laminated layer having intrinsic PMA and comprising a multilayer stack of two metals, a metal and alloy, or two alloys represented by (A1/A2)where A1 is a first metal or alloy, A2 is a second metal or alloy selected from X, CoX, and FeX where X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, and Si, CoX is “a disordered alloy, and n is the number of laminates in the stack, the laminated layer contacts a top surface of the seed layer, or the laminated layer has an (A1/C/A2) configuration where C is a non-magnetic spacer.'}2. The magnetic element of wherein the seed layer and laminated layer are formed in a magnetic tunnel junction (MTJ) having a seed layer/reference layer/tunnel barrier/free layer configuration claim 1 , the laminated layer is part of the reference layer.3. The magnetic element of wherein the reference layer further comprises a magnetic layer formed between the laminated layer and the tunnel barrier to increase a magnetoresistive (MR) ratio in the MTJ claim 2 , the magnetic layer interfaces with the tunnel barrier and has PMA with a magnetic moment in a same direction as ...

OPTICAL SCANNING PROJECTION MODULE

An optical scanning projection module includes a scanning light component including a plurality of sub light sources and at least one light-splitting element, a main light reflective element, a scanning element and a photosensitive element. Sub light beams of the sub light sources are converged to form a main light beam. One of the sub light beams travels to the light-delivering element to form a partial reflective light beam and a partial penetrating light beam. With a scanning manner, the partial reflective light beam or the partial penetrating light beam is reflected by the scanning element to be an inspection light, and the main light beam is reflected by the scanning element to be a projection light. The photosensitive element outputs a sensing signal according to the inspection light. Thus, the optical scanning projection module controls the operation of the scanning light component according to the sensing signal. 1. An optical scanning projection module , comprising:a scanning light component, comprising a plurality of sub light sources and at least one light-splitting element, wherein sub light beams of the sub light sources are converged to form a main light beam, and one of the sub light beams travels to the at least one light-splitting element to form a partial transmissive light and a partial reflected light;a main light reflective element, for reflecting the main light beam;a scanning element, wherein the main light beam, which travels from the main light reflective element, is reflected by the scanning element with a scanning manner to be a projection light, and one of the partial transmissive light and the partial reflected light is reflected by the scanning element with the scanning manner to be an inspection light; anda photosensitive element, for receiving the inspection light to output a sensing signal;wherein the optical scanning projection module controls the scanning light component in accordance with the sensing signal.2. The optical scanning ...

Engineered Magnetic Layer with Improved Perpendicular Anisotropy using Glassing Agents for Spintronic Applications

A magnetic element is disclosed wherein first and second interfaces of a free layer with a perpendicular Hk enhancing layer and tunnel barrier, respectively, produce enhanced surface perpendicular anisotropy to increase thermal stability in a magnetic tunnel junction (MTJ). The free layer may be a single layer or a composite and is comprised of one or more glassing agents that have a first concentration in a middle portion thereof and a second concentration less than the first concentration in regions near first and second interfaces. As a result, a CoFeB free layer, for example, selectively crystallizes along first and second interfaces but maintains an amorphous character in a middle region containing a glass agent providing the annealing temperature is less than the crystallization temperature of the middle region. The magnetic element may be part of a spintronic device or serve as a propagation medium in a domain wall motion device. 1. A magnetic tunnel junction (MTJ) element including a ferromagnetic layer with at least two interfaces that produce interfacial perpendicular anisotropy , comprising:(a) a tunnel barrier layer;(b) the ferromagnetic layer that has a first interface with said tunnel barrier layer and a second interface with a perpendicular Hk enhancing layer formed on a surface of the ferromagnetic layer that is opposite a surface adjoining the tunnel barrier layer, the ferromagnetic layer comprises a first glassing agent concentration in a middle portion thereof and a second glassing agent concentration less than the first glassing agent concentration in portions of the ferromagnetic layer proximate to the first and second interfaces; and(c) the perpendicular Hk enhancing layer.2. The MTJ element of wherein the glassing agent (G) is one or more of Si claim 1 , Ta claim 1 , P claim 1 , Nb claim 1 , Hf claim 1 , Ti claim 1 , Pd claim 1 , Be claim 1 , Cr claim 1 , Zr claim 1 , Cu claim 1 , Os claim 1 , V claim 1 , or Mg to inhibit crystallization and ...

Engineered Magnetic Layer with Improved Perpendicular Anisotropy using Glassing Agents for Spintronic Applications

A magnetic element in a spintronic device or serving as a propagation medium in a domain wall motion device is disclosed wherein first and second interfaces of a free layer with a perpendicular Hk enhancing layer and tunnel barrier, respectively, produce enhanced surface perpendicular anisotropy to increase thermal stability in a magnetic tunnel junction. The free layer may be a single layer or a composite and is comprised of a glassing agent that has a first concentration in a middle portion thereof and a second concentration less than the first concentration in regions near first and second interfaces. A CoFeB free layer selectively crystallizes along first and second interfaces but maintains an amorphous character in a middle region containing a glass agent providing the annealing temperature is less than the crystallization temperature of the middle region. 1. A magnetic tunnel junction (MTJ) element including a ferromagnetic layer with at least two interfaces that produce interfacial perpendicular anisotropy , comprising:(a) a tunnel barrier layer;(b) the ferromagnetic layer that has a first interface with said tunnel barrier layer and a second interface with a perpendicular Hk enhancing layer formed on a surface of the ferromagnetic layer that is opposite a surface adjoining the tunnel barrier layer, the ferromagnetic layer comprises a glassing agent (G) made of Mo or W and having a first concentration in a middle portion thereof and a second concentration less than the first concentration in portions of the ferromagnetic layer proximate to the first and second interfaces; and(c) the perpendicular Hk enhancing layer.2. The MTJ element of wherein the first concentration of glassing agent inhibits crystallization and maintains an amorphous character in the middle portion of the ferromagnetic layer.3. The MTJ element of wherein a glassing agent content incrementally increases from the second concentration at the first and second interfaces to the first ...

High Thermal Stability Reference Structure with Out-of-Plane Aniotropy for Magnetic Device Applications

Enhanced Hc and Hk in addition to higher thermal stability to 400° C. are achieved in magnetic devices by adding dusting layers on top and bottom surfaces of a spacer in a synthetic antiferromagnetic (SAF) structure to give a RL1/DL1/spacer/DL2/RL2 reference layer configuration where RL1 and RL2 layers exhibit perpendicular magnetic anisotropy (PMA), the spacer induces antiferromagnetic coupling between RL1 and RL2, and DL1 and DL2 are dusting layers that enhance PMA. RL1 and RL2 layers are selected from laminates such as (Ni/Co)n, L1alloys, or rare earth-transition metal alloys. The reference layer may be incorporated in STT-MRAM memory elements or in spintronic devices including a spin transfer oscillator. Dusting layers and a similar SAF design may be employed in a free layer for Ku enhancement and to increase the retention time of a memory cell. 1. A multilayer stack having a thermal stability to at least 400° C. in a magnetic device , comprising:(a) a seed layer formed on a substrate;(b) a first reference (RL1) layer and a second reference (RL2) layer each exhibiting perpendicular magnetic anisotropy;(c) a spacer that induces RKKY (antiferromagnetic) coupling between the RL1 and RL2 layers; and(d) a first dusting layer (DL1) and a second dusting layer (DL2) that enhance the RKKY coupling between the RL1 and RL2 layers, the multilayer stack has a configuration in which RL1, DL1, spacer, DL2, and RL2 layers are consecutively deposited on the seed layer to give a seed/RL1/DL1/spacer/DL2/RL2 configuration.2. The multilayer stack of wherein the RL1 and RL2 layers are made of a laminate that is (Ni/Co)n claim 1 , (Pd/Co)n claim 1 , (Pt/Co)n claim 1 , (Ni/CoFe)n claim 1 , (Ni/CoFeB)n claim 1 , (NiFe/Co)n claim 1 , (NiFeB/Co)n claim 1 , or (NiCo/Co)n where n is the number of laminations and n is between about 2 and 30.3. The multilayer stack of wherein the spacer is Ru claim 1 , Rh claim 1 , Ir claim 1 , Cu claim 1 , or Cr and has a thickness from about 2 to 20 ...

STYLUS

A stylus includes a conductive rod, a circuit board, and an antenna. The conductive rod has a first opening. The circuit board is disposed in the conductive rod and includes a ground portion, wherein the conductive rod is electrically connected to the ground portion. The antenna includes a radiating portion and a feeding portion. The feeding portion is electrically connected to the circuit board and extends to the outside of the conductive rod via the first opening. The radiating portion is disposed at the outside of the conductive rod and is electrically connected to the feeding portion. 1. A stylus , comprising:a conductive rod including a first opening;a circuit board disposed in the conductive rod and including a ground portion, wherein the conductive rod is electrically connected to the ground portion; andan antenna including a radiating portion and a feeding portion, wherein the feeding portion is electrically connected to the circuit board and extends from inside of the conductive rod to outside via the first opening, and the radiating portion is disposed at the outside of the conductive rod and electrically connected to the feeding portion.2. The stylus according to claim 1 , wherein the radiating portion is pivotally connected to the feeding portion around a rotating axis claim 1 , and the radiating portion rotates around the rotating axis to make part of the radiating portion away from the conductive rod.3. The stylus according to claim 2 , wherein the rotating axis is a central axis of the first opening.4. The stylus according to claim 2 , wherein the rotating axis is vertical to a central axis of the first opening.5. The stylus according to claim 1 , wherein the radiating portion is slidably disposed at the feeding portion around a sliding axis claim 1 , and the radiating portion slides around the sliding axis to make part of the radiating portion away from the conductive rod.6. The stylus according to claim 5 , wherein the sliding axis is vertical to a ...

Reverse Partial Etching Scheme for Magnetic Device Applications

A magnetic tunnel junction (MTJ) structure is provided over a device wherein the MTJ comprises a tunnel barrier layer between a free layer and a pinned layer; and a top and bottom electrode inside the MTJ structure. A hard mask layer is formed on the top electrode. The hard mask layer, top electrode, free layer, tunnel barrier layer, and pinned layer are patterned to define the magnetic tunnel junction (MTJ) structures. A first dielectric layer is deposited over the MTJ structures and planarized to expose the top electrode. Thereafter, the top electrode and free layer are patterned. A second dielectric layer is deposited over the MTJ structures and planarized to expose the top electrode. A third dielectric layer is deposited over the MTJ structures and a metal line contact is formed through the third dielectric layer to the top electrode to complete fabrication of the magnetic device. 1. A method of fabricating a magnetic device comprising:providing a magnetic tunnel junction (MTJ) structure over a device wherein said MTJ comprises a tunnel barrier layer between a free layer and a pinned layer, a top electrode over said free layer, and a bottom electrode under said pinned layer;forming a hard mask layer on said top electrode;patterning said hard mask layer, said top electrode, said free layer, said tunnel barrier layer, and said pinned layer to define said magnetic tunnel junction (MTJ) structures;depositing a first dielectric layer over said MTJ structures and planarizing said first dielectric layer to expose said top electrode;thereafter patterning said top electrode and said free layer;thereafter depositing a second dielectric layer over said MTJ structures and planarizing said second dielectric layer to expose said top electrode;thereafter depositing a third dielectric layer over said MTJ structures; andforming a metal line contact through said third dielectric layer to said top electrode to complete fabrication of said magnetic device.2. The method according to ...

Free Layer with High Thermal Stability for Magnetic Device Applications by Insertion of a Boron Dusting Layer

A boron or boron containing dusting layer such as CoB or FeB is formed along one or both of top and bottom surfaces of a free layer at interfaces with a tunnel barrier layer and capping layer to improve thermal stability while maintaining other magnetic properties of a MTJ stack. Each dusting layer has a thickness from 0.2 to 20 Angstroms and may be used as deposited, or at temperatures up to 400° C. or higher, or following a subsequent anneal at 400° C. or higher. The free layer may be a single layer of CoFe, Co, CoFeB or CoFeNiB, or may include a non-magnetic insertion layer. The resulting MTJ is suitable for STT-MRAM memory elements or spintronic devices. Perpendicular magnetic anisotropy is maintained in the free layer at temperatures up to 400° C. or higher. Ku enhancement is achieved and the retention time of a memory cell for STT-MRAM designs is increased. 1. A multilayer stack with thermal stability to at least 400° C. in a magnetic device , comprising:(a) a reference layer;(b) a free layer with perpendicular magnetic anisotropy (PMA) and having a top surface and a bottom surface;(c) a tunnel barrier layer formed between the reference layer and free layer; and(d) one or both of a first dusting layer and a second dusting layer each made of boron or a boron alloy having a B content greater than about 85 atomic % wherein the first dusting layer contacts the bottom surface of the free layer and the second dusting layer contacts a top surface of the free layer.2. The multilayer stack of wherein the free layer has a CoFe claim 1 , Co claim 1 , CoFeB claim 1 , CoFeNiB claim 1 , or CoFeB alloy composition and a thickness from about 5 to 20 Angstroms.3. The multilayer stack of wherein the free layer is further comprised of a non-magnetic layer (M) made of Ta claim 1 , Al claim 1 , Cu claim 1 , Zr claim 1 , Nb claim 1 , Hf claim 1 , Mg claim 1 , or Mo and having a thickness of about 0.5 to 10 Angstroms to give a FL1/M/FL2 configuration wherein FL1 is a bottom portion ...

Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications

A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)or (CoX)composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer. 1. A magnetic tunnel junction (MTJ) , comprising:(a) a seed layer formed on a substrate and comprising one or more of Hf, NiFeCr, and NiCr that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer;{'sub': n', 'n, '(b) a reference layer having a laminated structure with a plurality of “n” layers that are represented by (Co/X)or (CoX)where X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, and Si, CoX is a disordered alloy, and the reference layer contacts a top surface of the seed layer and has intrinsic PMA.'}2. The MTJ of wherein the seed layer has a thickness between about 10 and 300 Angstroms.3. The MTJ of further comprised of a magnetic layer made of CoFeB claim 1 , CoFe claim 1 , or combinations thereof that contacts a top surface of the laminated structure.4. The MTJ of wherein the magnetic layer consists of CoFeB and the MTJ is further comprised of a Ta layer about 0.5 to 3 Angstroms thick that is formed between the top surface of the laminated stack and the magnetic layer.5. The MTJ of wherein n is from 2 to 30.6. A magnetic tunnel junction (MTJ) claim 1 , comprising:(a) a seed layer formed on a substrate;{'sub': n', 'n, ...

Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications

A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)or (CoX)composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer. 1. A method of forming a magnetic tunnel junction (MTJ); comprising:(a) forming a seed layer on a substrate, the seed layer consists of one or more of Hf, NiCr, and NiFeCr, and enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer; and{'sub': n', 'n, '(b) forming the laminated layer having instrinsic PMA that contacts a top surface of the seed layer, the laminated layer has a (Co/X)or (CoX)structure wherein X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, and Si, CoX is a disordered alloy, and n is the number of laminates in the stack.'}2. The method of wherein the MTJ has a bottom spin valve configuration in which the seed layer claim 1 , a composite reference layer claim 1 , a tunnel barrier layer claim 1 , and a free layer are sequentially formed on the substrate claim 1 , and the laminated layer is part of the composite reference layer claim 1 , the composite reference layer is further comprised of a magnetic layer formed between the laminated layer and the tunnel barrier layer claim 1 , the magnetic layer has PMA aligned in the same direction as the PMA in the laminated layer.3. The method of wherein the MTJ has a top spin ...

Solar power system and solar energy collection device thereof

A solar energy connection device is provided, including a C-shaped reflecting plate, a heat pipe and a wing-shaped structure. The C-shaped reflecting plate includes a parabolic surface defining a symmetrical axis and a focusing axis. The heat pipe is disposed on the focusing axis of the parabolic surface with a working fluid flowing therein. The wing-shaped structure connects to the heat pipe and extends outwardly from the heat pipe, wherein the extension direction of the wing-shaped structure is parallel to the symmetrical axis.

MTJ Element for STT MRAM

An all (111) MTJ stack is disclosed in which there are no transitions between different crystalline orientations when going from layer to layer. This is accomplished by providing strongly (111)-textured layers immediately below the MgO tunnel barrier to induce a (111) orientation therein. 1. A process for manufacturing a magnetic tunnel junction (MTJ) device comprising:depositing a seed layer having a (111) crystalline orientation;depositing on said seed layer a first perpendicular magnetic anisotropy (PMA) layer having a fcc crystal lattice structure and a (111) crystalline orientation;depositing on said first PMA layer a first magneto-resistive (MR) layer having a fcc crystal lattice structure and a (111) crystalline orientation;depositing on said first MR layer a tunnel barrier layer of magnesia;depositing on said magnesia layer a second MR layer having a fcc crystal lattice structure and a (111) crystalline orientation;depositing on said second MR layer a second PMA layer having a fcc crystal lattice structure and a (111) crystalline orientation;depositing a capping layer on said a second PMA layer; andthen annealing all layers thereby causing said magnesia tunnel barrier layer to assume a (111) crystalline orientation whereby there are no transitions between different crystalline orientations for all active layers of said MTJ.2. The process recited in wherein said first and second PMA layers are selected from the group consisting of Co/Ni claim 1 , Co claim 1 , Pd claim 1 , Co/Pt claim 1 , Fe/Pd/ claim 1 , Fe/Pt multilayers or any combination thereof and are deposited to a thickness of between about 10 and 150 angstroms3. The process recited in wherein said first MR layer serves as a free layer for said MTJ and said second MR layer serves as a reference layer for said MTJ.4. The process recited in wherein the step of depositing said second MR layer further comprises:depositing a first ferromagnetic layer(FL) on said magnesia layer;depositing an antiparallel ...

Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications

A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)composition or the like where n is from 2 to 30. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer. 1. A magnetic element , comprising:(a) a seed layer comprising one or more of Hf, NiCr, and NiFeCr that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer; and(b) the laminated layer having intrinsic PMA and comprising an alloy with a L10 structure of the form MT where M is Rh, Pd, Pt, Ir, or alloy thereof, and T is Fe, Co, Ni, or alloy thereof.2. The magnetic element of wherein the seed layer and laminated layer are formed in a magnetic tunnel junction (MTJ) having a seed layer/reference layer/tunnel barrier/free layer configuration claim 1 , the laminated layer is part of the reference layer claim 1 , and the reference layer further comprises a magnetic layer formed between the laminated layer and the tunnel barrier to increase the magnetoresistive (MR) ratio in the magnetic element claim 1 , the magnetic layer interfaces with the tunnel barrier and has PMA with a magnetic moment in the same direction as the PMA in the laminated layer.3. The magnetic element of wherein the seed layer and laminated layer are formed in a MTJ having a reference layer/tunnel barrier/free layer/spacer/seed layer/ ...

Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications

A method for forming a MTJ in a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)composition. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer. 1. A method of forming a magnetic tunnel junction (MTJ); comprising:(a) forming a seed layer on a substrate, the seed layer consists of one or more of Hf, NiCr, and NiFeCr, and enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer; and{'sub': 'n', '(b) forming the laminated layer having instrinsic PMA that contacts a top surface of the seed layer, the laminated layer includes two metals, a metal and alloy, or two alloys represented by (A1/A2)or (A1/C/A2) where A1 is a first metal or alloy, A2 is a second metal or alloy, C is a non-magnetic spacer, and n is the number of laminates in the laminated layer.'}2. The method of wherein the MTJ has a bottom spin valve configuration in which the seed layer claim 1 , a composite reference layer claim 1 , a tunnel barrier layer claim 1 , and a free layer are sequentially formed on the substrate claim 1 , and the laminated layer is part of the composite reference layer claim 1 , the composite reference layer is further comprised of a magnetic layer formed between the laminated layer and the tunnel barrier layer claim 1 , the magnetic layer has PMA aligned in the same direction as the PMA in the laminated layer.3. The ...

Minimal Thickness Synthetic Antiferromagnetic (SAF) Structure with Perpendicular Magnetic Anisotropy for STT-MRAM

A synthetic antiferromagnetic (SAF) structure for a spintronic device is disclosed and has an AP2/antiferromagnetic (AF) coupling/CoFeB configuration. The SAF structure is thinned to reduce the fringing (Ho) field while maintaining high coercivity. The AP2 reference layer has intrinsic perpendicular magnetic anisotropy (PMA) and induces PMA in a thin CoFeB layer through AF coupling. In one embodiment, AF coupling is improved by inserting a Co dusting layer on top and bottom surfaces of a Ru AF coupling layer. When AP2 is (Co/Ni), and CoFeB thickness is 7.5 Angstroms, Ho is reduced to 125 Oe, Hc is 1000 Oe, and a balanced saturation magnetization-thickness product (Mst)=0.99 is achieved. The SAF structure may also be represented as FL2/AF coupling/CoFeB where FL2 is a ferromagnetic layer with intrinsic PMA. 1. A synthetic antiferromagnetic (SAF) structure , comprising:(a) an AP2 reference layer with intrinsic perpendicular magnetic anisotropy;(b) a CoFeB layer wherein perpendicular magnetic anisotropy is established by antiferromagnetic coupling with the AP2 reference layer through an antiferromagnetic (AF) coupling layer formed between the AP2 reference layer and CoFeB layer; and(c) the AF coupling layer made of a non-magnetic material to give an AP2/AF coupling/CoFeB configuration or an CoFeB/AF coupling/AP2 configuration.2. The SAF structure of wherein the AP2 layer is comprised of an (A1/A2)laminate where the lamination number “n” is less than 6 claim 1 , A1 is one of Co claim 1 , CoFe claim 1 , or an alloy thereof claim 1 , and A2 is one of Pt claim 1 , Pd claim 1 , Rh claim 1 , Ru claim 1 , Ir claim 1 , Mg claim 1 , Mo claim 1 , Os claim 1 , Si claim 1 , V claim 1 , Ni claim 1 , NiCo claim 1 , and NiFe claim 1 , or A1 is Fe and A2 is V.3. The SAF structure of wherein the AP2 layer is a L10 ordered alloy of the form MT wherein M is Rh claim 1 , Pd claim 1 , Pt claim 1 , Ir claim 1 , or an alloy thereof claim 1 , and T is Fe claim 1 , Co claim 1 , Ni or alloy ...

Storage Element for STT MRAM Applications

An improved PMA STT MTJ storage element, and a method for forming it, are described. By inserting a suitable oxide layer between the storage and cap layers, improved PMA properties are obtained, increasing the potential for a larger Eb/kT thermal factor as well as a larger MR. Another important advantage is better compatibility with high processing temperatures, potentially facilitating integration with CMOS.

Minimal Thickness Synthetic Antiferromagnetic (SAF) Structure with Perpendicular Magnetic Anisotropy for STT-MRAM

A synthetic antiferromagnetic (SAF) structure for a spintronic device is disclosed and has an FL2/AF coupling/CoFeB configuration where FL2 is a ferromagnetic free layer with intrinsic PMA. In one embodiment, AF coupling is improved by inserting a Co dusting layer on top and bottom surfaces of a Ru AF coupling layer. The FL2 layer may be a L10 ordered alloy, a rare earth-transition metal alloy, or an (A1/A2)laminate where A1 is one of Co, CoFe, or an alloy thereof, and A2 is one of Pt, Pd, Rh, Ru, Ir, Mg, Mo, Os, Si, V, Ni, NiCo, and NiFe, or A1 is Fe and A2 is V. A method is also provided for forming the SAF structure. 1. A synthetic antiferromagnetic (SAF) structure , comprising:(a) a FL2 free layer with intrinsic perpendicular magnetic anisotropy;(b) a CoFeB layer wherein perpendicular magnetic anisotropy is established by antiferromagnetic coupling with the FL2 free layer through an antiferromagnetic (AF) coupling layer formed between the FL2 free layer and CoFeB layer; and(c) the AF coupling layer made of a non-magnetic material to give an FL2/AF coupling/CoFeB configuration or an CoFeB/AF coupling/FL2 configuration.2. The SAF structure of wherein the FL2 layer is comprised of an (A1/A2)laminate where the lamination number “n” is less than 6 claim 1 , A1 is one of Co claim 1 , CoFe claim 1 , or an alloy thereof claim 1 , and A2 is one of Pt claim 1 , Pd claim 1 , Rh claim 1 , Ru claim 1 , Ir claim 1 , Mg claim 1 , Mo claim 1 , Os claim 1 , Si claim 1 , V claim 1 , Ni claim 1 , NiCo claim 1 , and NiFe claim 1 , or A1 is Fe and A2 is V.3. The SAF structure of wherein the FL2 layer is a L10 ordered alloy of the form MT wherein M is Rh claim 1 , Pd claim 1 , Pt claim 1 , Ir claim 1 , or an alloy thereof claim 1 , and T is Fe claim 1 , Co claim 1 , Ni or alloy thereof claim 1 , or the FL2 layer is made of a rare earth-transition metal alloy that is TbCo claim 1 , TbFeCo claim 1 , or GdFeCo.4. The SAF structure of wherein the FL2 layer is comprised of a (A1/A2) ...

Method of characterizing a device

A method of characterizing a device may be used to determine a metal work function of the device according to a threshold voltage, a body effect, and an oxide capacitance of the device. The threshold voltage may be determined according to a current to voltage curve. The oxide capacitance may be determined according to a capacitor to voltage curve. 1. A method of characterizing a device , comprising:generating a current to voltage curve of the device;determining a threshold voltage of the device according to the current to voltage curve;determining a body effect of the device;generating a capacitor to voltage curve of the device;determining an oxide capacitance of the device according to the capacitor to voltage curve; anddetermining a metal work function of the device according to the threshold voltage, the body effect, and the oxide capacitance.2. The method of claim 1 , wherein determining the metal work function of the device further comprises determining the metal work function of the device using a threshold voltage equation as follows:{'br': None, 'i': V', 'qNaφ', /C, 'sub': t', 'm', 's', 'B', 's', 'B', 'OX, 'sup': '1/2', '=φ−φ+2φ+[(4ε)'}{'sub': t', 'B', 'OX', 's', 'm', 's, 'wherein Vis the threshold voltage of the device, φis a body potential of the device, Cis the oxide capacitance of the device, Na is a doping density of the device, q is a charge of an electron, εis a permittivity of a silicon, φis the metal work function of the device, and φis a substrate work function of the device.'}3. The method of claim 1 , further comprising:setting a fixed charge of the device; anddetermining a voltage across an oxide of the device corresponding to the fixed charge.4. The method of claim 3 , wherein determining the metal work function of the device further comprises determining the metal work function of the device using a threshold voltage equation as follows:{'br': None, 'i': V', '−Q', '/C', 'qNaφ', '/C, 'sub': t', 'm', 's', 'f', 'OX', 'B', 's', 'B', 'OX, 'sup': '1 ...

TRANSISTOR AND MANUFACTURING METHOD THEREOF

A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the gate structure. The ferroelectric material layer is disposed between the internal electrode and the gate structure. A spacer is disposed on the semiconductor channel layer, and a trench surrounded by the spacer is formed above the semiconductor channel layer. The ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench. The ferroelectric material layer in the transistor of the present invention is used to enhance the electrical characteristics of the transistor. 1. A transistor , comprising:a semiconductor channel layer;a gate structure disposed on the semiconductor channel layer;a gate insulation layer disposed between the gate structure and the semiconductor channel layer;an internal electrode disposed between the gate insulation layer and the gate structure;a ferroelectric material layer disposed between the internal electrode and the gate structure; anda spacer disposed on the semiconductor channel layer, wherein a trench surrounded by the spacer is formed above the semiconductor channel layer, the ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench.2. The transistor of claim 1 , wherein a thickness of the ferroelectric material layer is larger than a thickness of the gate insulation layer.3. The transistor of claim 1 , wherein the ferroelectric material layer comprises a perovskite oxide material.4. The transistor of claim 1 , wherein the semiconductor channel layer includes indium gallium zinc oxide (IGZO).5. The ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate. 1. A method for fabricating semiconductor device , comprising:forming a first fin-shaped structure on a substrate;forming a first single diffusion break (SDB) structure in the first fin-shaped structure;forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure;forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure;forming a patterned mask on the first gate structure; andperforming a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.2. The method of claim 1 , wherein the step of forming the first SDB structure comprises:removing part of the first fin-shaped structure to form a trench for dividing the first fin-shaped structure into a first portion and a second portion; andforming a dielectric layer in the trench to form the first SDB structure.3. The method of claim 2 , wherein the dielectric layer comprises silicon nitride.4. The method of claim 1 , wherein the first fin-shaped structure is disposed extending along a first direction and the first SDB structure is disposed extending along a second direction.5. The method of claim 4 , wherein the first direction is orthogonal to the second direction.6. The method of claim 1 , wherein the substrate comprises a first metal-oxide semiconductor (MOS) region and a second ...

Hybridized Oxide Capping Layer for Perpendicular Magnetic Anisotropy

A hybrid oxide capping layer (HOCL) is disclosed and used in a magnetic tunnel junction to enhance thermal stability and perpendicular magnetic anisotropy in an adjoining free layer. The HOCL has a lower interface oxide layer and one or more transition metal oxide layers wherein each of the metal layers selected to form a transition metal oxide has an absolute value of free energy of oxide formation less than that of the metal used to make the interface oxide layer. One or more of the HOCL layers is under oxidized. Oxygen from one or more transition metal oxide layers preferably migrates into the interface oxide layer during an anneal to further oxidize the interface oxide. As a result, a less strenuous oxidation step is required to initially oxidize the lower HOCL layer and minimizes oxidative damage to the free layer. 1. A hybrid oxide capping layer (HOCL) that induces or enhances perpendicular magnetic anisotropy (PMA) in an adjoining ferromagnetic layer in a magnetic device , comprising:(a) an interface oxide layer made by oxidation of a first metal or alloy layer which forms an interface with the adjoining ferromagnetic layer; and(b) one or more transition metal oxide layers formed by oxidation of one or more transition metal layers wherein each transition metal has an absolute value of free energy of oxide formation less than that of the first metal or alloy.2. The hybrid oxide capping layer of wherein the interface oxide layer is comprised of one or more of MgTaOx claim 1 , SrTiOx claim 1 , BaTiOx claim 1 , CaTiOx claim 1 , LaAlOx claim 1 , MgO claim 1 , TaOx claim 1 , MnOx claim 1 , VOx and BOx.3. The hybrid oxide capping layer of wherein the one or more transition metal oxide layers is comprised of one or more of RuOx claim 1 , PtOx claim 1 , RhOx claim 1 , MoOx claim 1 , WOx claim 1 , SnOx claim 1 , or InSnOx.4. The hybrid oxide capping layer of wherein the ferromagnetic layer is a free layer comprised of one or more of CoFeB claim 1 , CoFe claim 1 , Co Fe ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A semiconductor device includes a PMOS region and a NMOS region on a substrate, a first fin-shaped structure on the PMOS region, a first single diffusion break (SDB) structure in the first fin-shaped structure, a first gate structure on the first SDB structure, and a second gate structure on the first fin-shaped structure. Preferably, the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region. 1. A semiconductor device , comprising:a substrate comprising a PMOS region and a NMOS region;a first fin-shaped structure on the PMOS region;a first single diffusion break (SDB) structure in the first fin-shaped structure;a first gate structure on the first SDB structure;a second gate structure on the first fin-shaped structure, wherein the first gate structure and the second gate structure are of different materials, the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region, and the second gate structure comprises a first U-shape high-k dielectric layer;a first source/drain region adjacent to two sides of the second gate structure, wherein the first source/drain region comprises silicon phosphide;a second fin-shaped structure on the NMOS region;a second SDB structure in the second fin-shaped structure;a third gate structure on the second SDB structure and a fourth gate structure on the second fin-shaped structure, wherein the third gate structure and the fourth gate structure are of same material, the third gate structure disposed directly on top of the second SDB structure is a metal gate and the fourth gate structure disposed on the second fin-shaped structure is also a metal gate in the NMOS ...

HYBRIDIZED OXIDE CAPPING LAYER FOR PERPENDICULAR MAGNETIC ANISOTROPY

A method of forming a hybrid oxide capping layer (HOCL) is disclosed and used in a magnetic tunnel junction to enhance thermal stability and perpendicular magnetic anisotropy in an adjoining free layer. The HOCL has a lower interface oxide layer and one or more transition metal oxide layers wherein each of the metal layers selected to form a transition metal oxide has an absolute value of free energy of oxide formation less than that of the metal used to make the interface oxide layer. One or more of the HOCL layers is under oxidized. Oxygen from one or more transition metal oxide layers preferably migrates into the interface oxide layer during annealing to further oxidize the interface oxide. As a result, a less strenuous oxidation step is required to initially oxidize the lower HOCL layer and minimizes oxidative damage to the free layer.

Packaged Semiconductor Device Including Liquid-Cooled Lid and Methods of Forming the Same

Semiconductor devices including lids having liquid-cooled channels and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first integrated circuit die; a lid coupled to the first integrated circuit die, the lid including a plurality of channels in a surface of the lid opposite the first integrated circuit die; a cooling cover coupled to the lid opposite the first integrated circuit die; and a heat transfer unit coupled to the cooling cover through a pipe fitting, the heat transfer unit being configured to supply a liquid coolant to the plurality of channels through the cooling cover. 1. A semiconductor device comprising:a first integrated circuit die;a lid coupled to the first integrated circuit die, the lid comprising a plurality of channels in a surface of the lid opposite the first integrated circuit die;a cooling cover coupled to the lid opposite the first integrated circuit die; anda heat transfer unit coupled to the cooling cover through a pipe fitting, wherein the heat transfer unit is configured to supply a liquid coolant to the plurality of channels through the cooling cover.2. The semiconductor device of claim 1 , wherein the lid is coupled to the first integrated circuit die by dielectric-to-dielectric bonds.3. The semiconductor device of claim 1 , further comprising an encapsulant laterally surrounding the first integrated circuit die claim 1 , wherein the lid is coupled to the encapsulant by dielectric-to-dielectric bonds.4. The semiconductor device of claim 1 , further comprising an encapsulant laterally surrounding the first integrated circuit die claim 1 , wherein a width of the lid is equal to a width of the first integrated circuit die.5. The semiconductor device of claim 1 , further comprising an encapsulant laterally surrounding the first integrated circuit die claim 1 , wherein a width of the lid is equal to a width of the cooling cover and greater than a width of the encapsulant.6. The semiconductor ...

Dual Magnetic Tunnel Junction (DMTJ) Stack Design

A dual magnetic tunnel junction (DMTJ) is disclosed with a PL/TB/free layer/TB/PL/capping layer configuration wherein a first tunnel barrier (TB) has a substantially lower resistance x area (RA) product than RAfor an overlying second tunnel barrier (TB) to provide an acceptable net magnetoresistive ratio (DRR). Moreover, magnetizations in first and second pinned layers, PL and PL, respectively, are aligned antiparallel to enable a lower critical switching current than when in a parallel alignment. An oxide capping layer having a RAis formed on PL to provide higher PL stability. The condition RA Подробнее

Low Resistance MgO Capping Layer for Perpendicularly Magnetized Magnetic Tunnel Junctions

A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a first metal oxide (Mox) layer and second metal oxide (tunnel barrier) to produce perpendicular magnetic anisotropy (PMA) in the FL. In some embodiments, conductive metal channels made of a noble metal are formed in the Mox that is MgO to reduce parasitic resistance. In a second embodiment, a discontinuous MgO layer with a plurality of islands is formed as the Mox layer and a non-magnetic hard mask layer is deposited to fill spaces between adjacent islands and form shorting pathways through the Mox. In another embodiment, end portions between the sides of a center Mox portion and the MTJ sidewall are reduced to form shorting pathways by depositing a reducing metal layer on Mox sidewalls, or performing a reduction process with forming gas, H 2 , or a reducing species.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate. 1. A method for fabricating semiconductor device , comprising:forming a first fin-shaped structure on a substrate;forming a first single diffusion break (SDB) structure in the first fin-shaped structure;forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure;forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure;forming a patterned mask on the first gate structure; andperforming a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.2. The method of claim 1 , wherein the step of forming the first SDB structure comprises:removing part of the first fin-shaped structure to form a trench for dividing the first fin-shaped structure into a first portion and a second portion; andforming a dielectric layer in the trench to form the first SDB structure.3. The method of claim 2 , wherein the dielectric layer comprises silicon nitride.4. The method of claim 1 , wherein the first fin-shaped structure is disposed extending along a first direction and the first SDB structure is disposed extending along a second direction.5. The method of claim 4 , wherein the first direction is orthogonal to the second direction.6. The method of claim 1 , wherein the substrate comprises a first metal-oxide semiconductor (MOS) region and a second ...

METHOD FOR FORMING IMAGE SENSOR DEVICE STRUCTURE WITH DOPING LAYER IN LIGHT-SENSING REGION

A method for forming an image sensor device structure is provided. The method includes forming a light-sensing region in a substrate, and forming an interconnect structure below a first surface of the substrate. The method also includes forming a trench in the light-sensing region from a second surface of the substrate, and forming a doping layer in the trench. The method includes forming an oxide layer in the trench and on the doping layer to form a doping region, and the doping region is inserted into the light-sensing region. 1. A method for forming an image sensor device structure , comprising:forming a light-sensing region in a substrate;forming an interconnect structure below a first surface of the substrate;forming a trench in the light-sensing region from a second surface of the substrate;forming a doping layer in the trench; andforming an oxide layer in the trench and on the doping layer to form a doping region, wherein the doping region is inserted into the light-sensing region.2. The method for forming the image sensor device structure as claimed in claim 1 , further comprising:forming a plurality of color filters on the oxide layer; andforming a plurality of microlens structure on the color filters.3. The method for forming the image sensor device structure as claimed in claim 1 , further comprising:forming a deep trench in the substrate from the second surface of the substrate, wherein the deep trench has a second depth which is greater than a first depth of the trench;forming the doping layer in the deep trench; andforming the oxide layer in the deep trench and on the doping layer to form a deep isolation ring, wherein the deep isolation ring surrounds the doping region.4. The method for forming the image sensor device structure as claimed in claim 3 , further comprising:forming a high-k dielectric layer in the deep trench before forming the oxide layer in the deep trench.5. The method for forming the image sensor device structure as claimed in claim 1 ...

MIM Capacitors with Improved Reliability

A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer. 1. A device comprising:a bottom electrode comprising a metal nitride layer;a metal oxynitride layer over the bottom electrode, wherein the metal oxynitride layer and the bottom electrode comprise same metals;an insulating layer over the metal oxynitride layer; anda top electrode over the insulating layer.2. The device of claim 1 , wherein the bottom electrode further comprises a metal layer underlying the metal nitride layer claim 1 , and the metal layer and the metal nitride layer comprise same metals.3. The device of claim 1 , wherein a first atom ratio of metal-to-nitrogen in the metal nitride layer is substantially equal to a second metal-to-nitrogen in the metal oxynitride layer.4. The device of further comprising a dielectric layer claim 1 , wherein the bottom electrode and the metal oxynitride layer are in the dielectric layer claim 1 , and wherein each of the insulating layer and the top electrode comprises a first portion extending into the dielectric layer claim 1 , and a second portion overlapping the dielectric layer.5. The device of claim 1 , wherein the metal oxynitride layer comprises titanium oxynitride.6. The device of claim 1 , wherein the metal oxynitride layer comprises tantalum oxynitride.7. The device of claim 1 , wherein the insulating layer contacts the metal oxynitride layer.8. The device of claim 1 , wherein the insulating layer comprises a high-k dielectric material.9. The device of claim 1 , wherein the insulating layer comprises a material selected from the group consisting essentially of HfO claim 1 , AlO claim 1 , ZrO claim 1 , TaO claim 1 , and combinations thereof.10. The device of further ...

High Thermal Stability Reference Structure with Out-of-Plane Anisotropy for Magnetic Device Applications

Enhanced Hc and Hk in addition to higher thermal stability up to at least 400° C. are achieved in magnetic devices by adding dusting layers on top and bottom surfaces of a spacer in a synthetic antiferromagnetic (SAF) structure to give a RL1/DL1/spacer/DL2/RL2 reference layer configuration where RL1 and RL2 layers exhibit perpendicular magnetic anisotropy (PMA), the spacer induces antiferromagnetic coupling between RL1 and RL2, and DL1 and DL2 are dusting layers that enhance PMA. Dusting layers are deposited at room temperature to 400° C. RL1 and RL2 layers are selected from laminates such as (Ni/Co)n, L1alloys, or rare earth-transition metal alloys. The reference layer may be incorporated in STT-MRAM memory elements or in spintronic devices including a spin transfer oscillator. Dusting layers and a similar SAF design may be employed in a free layer for Ku enhancement and to increase the retention time of a memory cell for STT-MRAM designs. 1. A multilayer stack having a thermal stability to at least 400° C. in a magnetic device , comprising:(a) a seed layer formed on a substrate; and (1) a first reference (RL1) layer and a second reference (RL2) layer each exhibiting perpendicular magnetic anisotropy;', '(2) a first spacer that induces RKKY (antiferromagnetic) coupling between the RL1 and RL2 layers;', '(3) a first dusting layer (DL1) and a second dusting layer (DL2) that enhance the RKKY coupling between the RL1 and RL2 layers, DL1 and DL2 have a CoTa, CoZr, CoHf, CoMg, or CoNb composition;', '(4) a third reference layer (RL3) formed as the uppermost layer in the multilayer stack wherein the RL1, RL2, and RL3 layers are made of a laminate that is (Ni/CoFe)n, (Ni/CoFeB)n, (NiFe/Co)n, (NiFeB/Co)n, or (NiCo/Co)n and n is a number of laminations;', '(5) a second spacer that induces RKKY coupling between the RL3 and RL2 layers;', '(6) third (DL3) and fourth (DL4) dusting layers that enhance RKKY coupling between the RL2 and RL3 layers, the multilayer stack has a ...

METHOD FOR FABRICATING SUBSTRATE OF SEMICONDUCTOR DEVICE INCLUDING EPITAXIAL LAYER AND SILICON LAYER HAVING SAME CRYSTALLINE ORIENTATION

A method for fabricating substrate of a semiconductor device includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation. 1. A method for fabricating substrate of a semiconductor device , comprising:providing a first silicon layer;forming a dielectric layer on the first silicon layer;bonding a second silicon layer to the dielectric layer;removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; andforming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.2. The method of claim 1 , further comprising:rotating the second silicon layer by 45 degrees; andbonding the second silicon layer to the dielectric layer so that the second silicon layer and the first silicon layer comprise different channel direction.3. The method of claim 2 , further comprising:forming a patterned hard mask on the second silicon layer after bonding the second silicon layer to the dielectric layer;using the patterned hard mask to remove part of the second silicon layer and part of the dielectric layer for defining the first region and the second region on the first silicon layer; andusing the patterned hard mask for forming the epitaxial layer in the first region of the first ...

EXTRA DOPED REGION FOR BACK-SIDE DEEP TRENCH ISOLATION

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an image sensor disposed within a substrate. The substrate has sidewalls and a horizontally extending surface defining one or more trenches extending from a first surface of the substrate to within the substrate. One or more isolation structures are arranged within the one or more trenches. A doped region is arranged within the substrate laterally between sidewalls of the one or more isolation structures and the image sensor and vertically between the image sensor and the first surface of the substrate. The doped region has a higher concentration of a first dopant type than an abutting part of the substrate that extends along opposing sides of the image sensor. 1. An integrated chip , comprising:an image sensor disposed within a substrate, wherein the substrate comprises sidewalls and a horizontally extending surface defining one or more trenches extending from a first surface of the substrate to within the substrate;one or more isolation structures arranged within the one or more trenches;a doped region arranged within the substrate laterally between sidewalls of the one or more isolation structures and the image sensor and vertically between the image sensor and the first surface of the substrate; andwherein the doped region has a higher concentration of a first dopant type than an abutting part of the substrate that extends along opposing sides of the image sensor.2. The integrated chip of claim 1 , wherein the image sensor is completely laterally confined between outermost edges of the one or more isolation structures.3. The integrated chip of claim 2 , wherein the doped region vertically overlaps the image sensor.4. The integrated chip of claim 1 , wherein the first dopant type is a p-type dopant.5. The integrated chip of claim 1 , wherein the doped region extends from the first surface of the substrate to a depth of greater than or equal to approximately 0. ...

FLEXIBLE LIQUID CRYSTAL CELLS AND LENSES

A flexible optical element adopting liquid crystals (LCs) as the materials for realizing electrically tunable optics is foldable. A method for manufacturing the flexible element includes patterned photo-polymerization. The LC optics can include a pair of LC layers with orthogonally aligned LC directors for polarizer-free properties, flexible polymeric alignment layers, flexible substrates, and a module for controlling the electric field. The lens power of the LC optics can be changed by controlling the distribution of electric field across the optical zone. 1. A flexible electrically tunable liquid crystal lens , comprising:a liquid crystal cell having a cell gap thickness X prior to bending the liquid crystal lens, and a cell gap thickness Y after bending the liquid crystal lens, wherein Y=X±10% X.2. The flexible electrically tunable liquid crystal lens of claim 1 , wherein the liquid crystal cell comprises polymer posts effective in limiting changes in the cell gap thickness to maintain Y=X±10% X.3. The flexible electrically tunable liquid crystal lens of claim 1 , including a polymer lens body encasing the liquid crystal cell.4. The flexible electrically tunable liquid crystal lens of claim 1 , wherein the liquid crystal cell includes first and second alignment layers claim 1 , and a layer of liquid crystal between the first and second alignment layers claim 1 , the first and second alignment layers comprising a flexible polymeric material.5. The flexible electrically tunable liquid crystal lens of claim 4 , wherein the liquid crystal cell comprises an array of polymer posts extending through the layer of liquid crystal bonded to the first and second alignment layers.6. The flexible electrically tunable liquid crystal lens of claim 4 , wherein said bending includes folding the cell on a radius of 1 to 9 mm.7. The flexible electrically tunable liquid crystal lens of claim 4 , wherein at least one of the first and second alignment layers has liquid crystal moieties ...

High Thermal Stability Reference Structure with Out-of-Plane Anisotropy for Magnetic Device Applications

Enhanced Hc and Hk in addition to higher thermal stability to 400° C. are achieved in magnetic devices by adding dusting layers on top and bottom surfaces of a spacer in a synthetic antiferromagnetic (SAF) structure to give a RL1/DL1/spacer/DL2/RL2 reference layer configuration where RL1 and RL2 layers exhibit perpendicular magnetic anisotropy (PMA), the spacer induces antiferromagnetic coupling between RL1 and RL2, and DL1 and DL2 are dusting layers that enhance PMA. Dusting layers are deposited at room temperature to 400° C. RL1 and RL2 layers are selected from laminates such as (Ni/Co)n, L1alloys, or rare earth-transition metal alloys. The reference layer may be incorporated in STT-MRAM memory elements or in spintronic devices including a spin transfer oscillator. A transition layer such as CoFeB/Co may be formed between the RL2 reference layer and tunnel barrier layer in a bottom spin valve design. 1. A method of forming a magnetic device having high perpendicular magnetic anisotropy (PMA) comprising:(a) depositing a seed layer on a substrate;(b) forming a reference layer on the seed layer wherein the reference layer has a RL1/DL1/spacer/DL2/RL2 configuration in which the RL1 and RL2 layers exhibit perpendicular magnetic anisotropy, the spacer induces RKKY (antiferromagnetic coupling) between the RL1 and RL2 layers, and DL1 and DL2 are dusting layers which enhance the RKKY coupling between the RL1 and RL2 layers;(c) forming a CoFeB/Co transitional layer on the RL2 layer;(d) forming a non-magnetic spacer on the reference layer;(e) depositing a free layer on the non-magnetic spacer;(f) depositing a cap layer on the free layer to give a multilayer stack with a seed/reference layer/non-magnetic spacer/free layer/cap layer configuration; and(g) annealing the multilayer stack.2. The method of wherein the dusting layers are comprised of Co claim 1 , CoFe claim 1 , or a Co alloy and are deposited at room temperature or at a temperature up to at least 400° C.3. The ...

Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications

A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)composition or the like where n is from 2 to 30. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a reference layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer. 1. A magnetic tunnel junction (MTJ) , comprising:(a) a seed layer formed on a substrate and comprising one or more of Hf, NiFeCr, and NiCr that enhances PMA in an overlying laminated layer;{'sub': 'n', '(b) a composite reference layer comprising the laminated layer that contacts a top surface of the seed layer, the laminated layer has intrinsic PMA and comprises a multilayer stack that includes two magnetic elements, a magnetic element and alloy, or two alloys represented by (A1/A2)or (A1/C/A2) where A1 is a first metal or alloy, A2 is a second metal or alloy, C is a non-magnetic spacer, and n is the number of laminates in the laminated layer, the composite reference layer also includes an upper magnetic layer that has PMA with a magnetization in the same direction as the PMA in the laminated layer;'}(c) a tunnel barrier layer contacting a top surface of the upper magnetic layer;(d) a free layer formed on the tunnel barrier layer; and(e) a capping layer as the uppermost layer in the MTJ.2. The MTJ of wherein the seed layer is Hf claim 1 , NiFeCr claim 1 , or NiCr claim 1 , or a composite with a Hf/NiCr claim 1 , Hf/NiFeCr claim 1 , NiFeCr claim 1 , or ...

Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications

A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)composition or the like where n is from 2 to 30. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer. 1. A magnetic tunnel junction (MTJ) , comprising:(a) a seed layer formed on a substrate;{'sub': 'n', '(b) a composite free layer comprising a lower laminated layer that contacts a top surface of the seed layer, the laminated layer has intrinsic perpendicular magnetic anisotropy (PMA) and includes two metals, a metal and alloy, or two alloys represented by (A1/A2)or (A1/C/A2) where A1 is a first magnetic element or alloy, A2 is a second magnetic element or alloy, C is a non-magnetic spacer, and n is the number of laminates in the laminated layer, the composite free layer also includes an upper magnetic layer that has PMA with a magnetization in the same direction as the PMA in the lower laminated layer;'}(c) a tunnel barrier layer contacting a top surface of the upper magnetic layer;(d) a reference layer formed on the tunnel barrier layer; and(e) and a capping layer formed on the reference layer.2. The MTJ of wherein the seed layer is Hf claim 1 , NiFeCr claim 1 , or NiCr claim 1 , or a composite with a Hf/NiCr claim 1 , Hf/NiFeCr claim 1 , NiFeCr/Hf claim 1 , or NiCr/Hf configuration and having a thickness between about 5 and 100 Angstroms.3. The MTJ of ...

Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications

A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)composition or the like where n is from 2 to 30. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a dipole layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer. 1. A magnetic tunnel junction (MTJ) , comprising:(a) a reference layer formed on a substrate;(b) a tunnel barrier layer contacting a top surface of the reference layer;(c) a free layer formed on the tunnel barrier layer;(d) a first non-magnetic spacer contacting a top surface of the free layer; and{'sub': 'n', '(e) a dipole layer contacting a top surface of the non-magnetic spacer, the dipole layer has a lower underlayer comprising one or more of Hf, NiFeCr, and NiCr, and an upper laminated layer that has intrinsic perpendicular magnetic anisotropy (PMA) and includes two magnetic elements, a magnetic element and alloy, or two alloys represented by (A1/A2)or (A1/C/A2) where A1 is a first magnetic element or alloy, A2 is a second magnetic element or alloy, C is a second non-magnetic spacer, and n is the number of laminates in the laminated layer.'}2. The MTJ of wherein the underlayer is Hf claim 1 , NiFeCr claim 1 , NiCr claim 1 , or a composite with a Hf/NiCr claim 1 , Hf/NiFeCr claim 1 , NiFeCr/Hf claim 1 , or NiCr/Hf configuration and having a thickness between about 5 and 100 Angstroms.3. The MTJ of wherein the first non-magnetic spacer is Ta with a ...

Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications

A MTJ for a domain wall motion device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)composition or the like where n is from 2 to 30. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer. 1. A domain wall motion device , comprising:{'sub': 'n', '(a) a first stack comprising a lower seed layer and a laminated layer formed thereon wherein the first stack has a first width and wherein the seed layer is one or more of Hf, NiCr, and NiFeCr, and the laminated layer has intrinsic PMA and a composition which includes two metals, a metal and alloy, or two alloys represented by (A1/A2)or (A1/C/A2) where A1 is a metal or alloy, A2 is a second metal or alloy, C is a non-magnetic spacer, and n is the number of laminates in the laminated layer; and'}(b) a second stack with a tunnel barrier/free layer/capping layer configuration and having a second width substantially greater than the first width, the tunnel barrier contacts a top surface of the first stack.2. The domain wall motion device of wherein the seed layer consists of Hf claim 1 , NiCr claim 1 , NiFeCr claim 1 , Hf/NiCr claim 1 , Hf/NiFeCr claim 1 , NiCr/Hf claim 1 , or NiFeCr/Hf.3. The domain wall motion device of further comprised of a magnetic layer made of CoFeB claim 1 , CoFe claim 1 , or combinations thereof that is formed between the laminated layer ...

SUBSTRATE OF SEMICONDUCTOR DEVICE INCLUDING EPITAXAL LAYER AND SILICON LAYER HAVING SAME CRSTALLINE ORIENTATION

A method for fabricating substrate of a semiconductor device is disclosed. The method includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation. 1. A method for fabricating substrate of a semiconductor device , comprising:providing a first silicon layer;forming a dielectric layer on the first silicon layer;bonding a second silicon layer to the dielectric layer;removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; andforming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.2. The method of claim 1 , further comprising:rotating the second silicon layer by 45 degrees; andbonding the second silicon layer to the dielectric layer so that the second silicon layer and the first silicon layer comprise different channel direction.3. The method of claim 2 , further comprising:forming a patterned hard mask on the second silicon layer after bonding the second silicon layer to the dielectric layer;using the patterned hard mask to remove part of the second silicon layer and part of the dielectric layer for defining the first region and the second region on the first silicon layer; andusing the patterned hard mask for forming the epitaxial layer in the first ...

Pfet and cmos containing same

A P-type field effect transistor includes: a gate area; an insulated area, adjacent to the gate area; a source region and a drain region made by silicon germanium, respectively, adjacent to the second side of the insulated area; a channel area, adjacent to the insulated area and formed between the source region and the drain region; a conductive layer, electrically connected to the source region and the drain region, respectively; and a plurality of capping layers, connected between the conductive layer and the source/drain regions, wherein the silicon layer(s) and the silicon germanium layer(s) are stacked alternately, and of which a silicon layer contacts the source/drain silicon germanium regions, while a silicon germanium layer contacts the conductive layer. The present invention also provides a complementary metal oxide semiconductor transistor including the P-type field effect transistor mentioned above.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches. 1. A semiconductor device , comprising:a package, comprising a first die having an active surface and a rear surface opposite to the active surface, wherein the rear surface has a cooling region and a peripheral region enclosing the cooling region, and the first die comprises micro-trenches located in the cooling region of the rear surface; anda cooling cover stacked on the first die, wherein the cooling cover comprises a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.2. The semiconductor device of claim 1 , further comprising a seal ring located over the peripheral region claim 1 , wherein the seal ring seals a space between the cooling cover and the micro-trenches.3. The semiconductor device of claim 2 , wherein the seal ring comprises an adhesive material claim 2 , and the cooling cover is adhered to the first die through the seal ring.4. The semiconductor device of claim 1 , wherein the cooling cover further comprises a fluid inlet channel and a fluid outlet channel claim 1 , the fluid inlet channel is connected to the fluid inlet port and the fluid outlet channel is connected to the fluid outlet port claim 1 , the fluid inlet port and the fluid outlet port respectively extend along a first direction claim 1 , and the fluid inlet channel and the fluid outlet channel respectively extend along a second direction perpendicular to the first direction.5. The ...

Self-Adaptive Halogen Treatment to Improve Photoresist Pattern and Magnetoresistive Random Access Memory (MRAM) Device Uniformity

A process flow for shrinking a critical dimension (CD) in photoresist features and reducing CD non-uniformity across a wafer is disclosed. A photoresist pattern is treated with halogen plasma to form a passivation layer with thickness (t) on feature sidewalls, and thickness (t) on the photoresist top surface where t>t. Thereafter, an etch based on O, or Owith a fluorocarbon or halogen removes the passivation layer and shrinks the CD. The passivation layer slows the etch such that photoresist thickness is maintained while CD shrinks to a greater extent for features having a width (d) than on features having width (d) where d>d. Accordingly, CD non-uniformity is reduced from 2.3% to 1% when d is 70 nm and is shrunk to 44 nm after the aforementioned etch. After a second etch through a MTJ stack to form MTJ cells, CD non-uniformity is maintained at 1%. 1. A method of reducing a feature width in a photoresist pattern , comprising:(a) forming a bottom anti-reflective coating (BARC) or a dielectric anti-reflective coating (DARC) on a substrate;{'b': 1', '2', '1', '2', '1, '(b) coating a photoresist layer having a thickness (h) on the BARC or DARC and patterning the photoresist layer to form a plurality of first features each having a critical dimension (CD) substantially equal to a first width (d), and a plurality of second features each having a CD substantially equal to a second width (d) where d>d, and wherein there is a first CD non-uniformity (v) in the plurality of first and second features across the substrate;'}{'sub': 2', '2', '2, 'b': 1', '2', '1', '2', '1', '2, '(c) performing a halogen treatment in a process chamber wherein the patterned photoresist layer is subjected to a plasma that is generated from one of HBr, HCl, HI, Cl, Br, and Fthereby forming a halogen passivation layer that has a first thickness (t) on a top surface of the plurality of first and second features, a second thickness (s) on a sidewall of each of the plurality of first features, and a ...

Free Layer with Out-of-Plane Anisotropy for Magnetic Device Applications

Synthetic antiferromagnetic (SAF) and synthetic ferrimagnetic (SyF) free layer structures are disclosed that reduce Ho (for a SAF free layer), increase perpendicular magnetic anisotropy (PMA), and provide higher thermal stability up to at least 400° C. The SAF and SyF structures have a FL1/DL1/spacer/DL2/FL2 configuration wherein FL1 and FL2 are free layers with PMA, the coupling layer induces antiferromagnetic or ferrimagnetic coupling between FL1 and FL2 depending on thickness, and DL1 and DL2 are dusting layers that enhance the coupling between FL1 and FL2. The SAF free layer may be used with a SAF reference layer in STT-MRAM memory elements or in spintronic devices including a spin transfer oscillator. Furthermore, a dual SAF structure is described that may provide further advantages in terms of Ho, PMA, and thermal stability. 1. A synthetic antiferromagnetic (SAF) free layer stack having a thermal stability to at least 400° C. in a magnetic device , comprising:(a) a first free layer (FL1) and a second free layer (FL2) each exhibiting perpendicular magnetic anisotropy;(b) a coupling layer that induces RKKY (antiferromagnetic) coupling between the FL1 and FL2 layers; and(c) a first dusting layer (DL1) and a second dusting layer (DL2) made of Fe, Ni, NiFe, or CoFeNi that enhance the RKKY coupling between the FL1 and FL2 layers, the SAF free layer stack has a structure in which FL1, DL1, coupling layer, DL2, and FL2 layers are consecutively deposited on a substrate to give a FL1 /DL1 /coupling layer/DL2/FL2 configuration.2. The SAF free layer stack of wherein one or both of the FL1 and FL2 layers are made of a laminate that is (Ni/Co) claim 1 , (Pd/Co) claim 1 , (Pt/Co) claim 1 , (Co/Ru) claim 1 , (Ni/CoFe) claim 1 , (Ni/CoFeB) claim 1 , (NiFe/Co) claim 1 , (NiFeB/Co) claim 1 , or (NiCo/Co)where n is the number of laminations and n is between about 1 and 10.3. The SAF free layer stack of wherein the coupling layer is Ru claim 1 , Rh claim 1 , Ir claim 1 , Cu claim ...

FLEXIBLE LIQUID CRYSTAL CELLS AND LENSES

A flexible optical element adopting liquid crystals (LCs) as the materials for realizing electrically tunable optics is foldable. A method for manufacturing the flexible element includes patterned photo-polymerization. The LC optics can include a pair of LC layers with orthogonally aligned LC directors for polarizer-free properties, flexible polymeric alignment layers, flexible substrates, and a module for controlling the electric field. The lens power of the LC optics can be changed by controlling the distribution of electric field across the optical zone. 1. A flexible electrically tunable liquid crystal lens , comprising:a liquid crystal cell having a cell gap thickness X prior to bending the liquid crystal lens, and a cell gap thickness Y after bending the liquid crystal lens, wherein Y=X±10%X.2. The flexible electrically tunable liquid crystal lens of claim 1 , wherein the liquid crystal cell comprises polymer posts effective in limiting changes in the cell gap thickness to maintain Y=X±10%X.3. The flexible electrically tunable liquid crystal lens of claim 1 , including a polymer lens body encasing the liquid crystal cell.4. The flexible electrically tunable liquid crystal lens of claim 1 , wherein the liquid crystal cell includes first and second alignment layers claim 1 , and a layer of liquid crystal between the first and second alignment layers claim 1 , the first and second alignment layers comprising a flexible polymeric material.5. The flexible electrically tunable liquid crystal lens of claim 4 , wherein the liquid crystal cell comprises an array of polymer posts extending through the layer of liquid crystal bonded to the first and second alignment layers.6. The flexible electrically tunable liquid crystal lens of claim 4 , wherein said bending includes folding the cell on a radius of 1 to 9 mm.7. The flexible electrically tunable liquid crystal lens of claim 4 , wherein at least one of the first and second alignment layers has liquid crystal moieties ...

EXTRA DOPED REGION FOR BACK-SIDE DEEP TRENCH ISOLATION

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an image sensing element disposed within a semiconductor substrate. One or more isolation structures are arranged within one or more trenches disposed along a first surface of the semiconductor substrate. The one or more isolation structures are separated from opposing sides of the image sensing element by non-zero distances. The one or more trenches are defined by sidewalls and a horizontally extending surface of the semiconductor substrate. A doped region is laterally arranged between the sidewalls of the semiconductor substrate defining the one or more trenches and is vertically arranged between the image sensing element and the first surface of the semiconductor substrate. 1. An integrated chip , comprising:an image sensing element disposed within a semiconductor substrate;one or more isolation structures arranged within one or more trenches disposed along a first surface of the semiconductor substrate and separated from opposing sides of the image sensing element by non-zero distances, wherein the one or more trenches are defined by sidewalls and a horizontally extending surface of the semiconductor substrate; anda doped region laterally arranged between the sidewalls of the semiconductor substrate defining the one or more trenches and vertically arranged between the image sensing element and the first surface of the semiconductor substrate.2. The integrated chip of claim 1 , wherein the doped region continuously extends laterally past opposing sides of the image sensing element.3. The integrated chip of claim 1 , further comprising:a plurality of interconnect layers disposed within a dielectric structure arranged along a second surface of the semiconductor substrate, the second surface of the semiconductor substrate opposing the first surface of the semiconductor substrate.4. The integrated chip of claim 1 , wherein the one or more isolation structures ...

Large Height Tree-Like Sub 30nm Vias to Reduce Conductive Material Re-Deposition for Sub 60nm MRAM Devices

A stack of connecting metal vias is formed on a bottom electrode by repeating steps of depositing a conductive via layer, patterning and trimming the conductive via layer to form a sub 30 nm conductive via, encapsulating the conductive via with a dielectric layer, and exposing a top surface of the conductive via. A MTJ stack is deposited on the encapsulated via stack. A top electrode layer is deposited on the MTJ stack and patterned and trimmed to form a sub 60 nm hard mask. The MTJ stack is etched using the hard mask to form an MTJ device and over etched into the encapsulation layers but not into the bottom electrode wherein metal re-deposition material is formed on sidewalls of the encapsulation layers underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device. 1. A method for fabricating a magnetic tunneling junction (MTJ) structure comprising:forming a conductive via stack on a bottom electrode comprising repeating steps of:depositing a conductive via layer;patterning said conductive via layer and then trimming said conductive layer to form a sub 30 nm first conductive via; andencapsulating said conductive via with a dielectric layer and planarizing said dielectric layer to expose a top surface of said conductive via to form a stack of encapsulated conductive vias;thereafter depositing a MTJ stack on said stack of encapsulated conductive vias wherein said MTJ stack comprises at least a pinned layer, a barrier layer on said pinned layer, and a free layer on said barrier layer;depositing a top electrode layer on said MTJ stack;patterning said top electrode layer and then trimming said top electrode layer to form a sub 60 nm hard mask; andthereafter etching said MTJ stack using said hard mask to form a MTJ device and over etching said MTJ stack into said dielectric layers but not into said bottom electrode wherein any metal re-deposition material is formed on sidewalls of said dielectric layers underlying said MTJ device and not on ...

Metal/Dielectric/Metal Hybrid Hard Mask To Define Ultra-Large Height Top Electrode For Sub 60nm MRAM Devices

An ultra-large height top electrode for MRAM is achieved by employing a novel thin metal/thick dielectric/thick metal hybrid hard mask stack. Etching parameters are chosen to etch the dielectric quickly but to have an extremely low etch rate on the metals above and underneath. Because of the protection of the large thickness of the dielectric layer, the ultra-large height metal hard mask is etched with high integrity, eventually making a large height top electrode possible. 1. A method comprising:providing a bottom electrode on a substrate;forming a stack of magnetic tunneling junction (MTJ) layers on the bottom electrode;forming a top electrode layer on the stack of MTJ layers;forming a hybrid hard mask on the top electrode layer, wherein the hybrid hard mask includes a first mask layer, a second mask layer and a third mask layer, wherein the first mask layer physically contacts the top electrode layer;patterning the third mask layer and the second mask layer;patterning the first mask layer while using the patterned third mask layer and the patterned second mask layer as a first mask;patterning the top electrode layer while using at least the patterned first mask layer as a second mask, wherein a portion of the patterned first mask layer remains disposed on the patterned top electrode layer after the patterning of the top electrode layer, wherein the portion of the patterned first mask layer has a top surface that is exposed after the patterning of the top electrode layer, the top surface of the portion of the first mask layer facing away from the substrate; andperforming an over etching on the stack of MTJ layers and the bottom electrode using the patterned top electrode layer and the portion of the first mask layer as a third mask, wherein the over etching includes over etching the stack of MTJ layers such that re-deposition material is formed on sidewalls of the bottom electrode and not on sidewalls of the stack of MTJ layers.2. The method of claim 1 , wherein ...

LIQUID CRYSTAL PHOTOELECTRIC APPARATUS AND MANUFACTURING METHOD OF LIQUID CRYSTAL PHOTOELECTRIC APPARATUS

A liquid crystal photoelectric apparatus including an upper substrate, a lower substrate, a plurality of alignment layers, and a liquid crystal material is provided. The alignment layers include an upper alignment layer, a lower alignment layer, and at least one intermediate alignment layer. The upper alignment layer has a first orientation direction. The lower alignment layer has a second orientation direction. The at least one intermediate alignment layer has an intermediate orientation direction. The intermediate orientation direction is between the first orientation direction and the second orientation direction. The liquid crystal material includes a plurality of liquid crystal material portions. Each of the liquid crystal material portions is disposed between any adjacent two alignment layers. A manufacturing method of the liquid crystal photoelectric apparatus is also provided. 1. A liquid crystal photoelectric apparatus , comprising:an upper substrate;a lower substrate;a plurality of alignment layers, comprising an upper alignment layer, at least one intermediate alignment layer, and a lower alignment layer, the upper alignment layer being disposed between the upper substrate and the at least one intermediate alignment layer, the lower alignment layer being disposed between the lower substrate and the at least one intermediate alignment layer, the at least one intermediate alignment layer being disposed between the upper alignment layer and the lower alignment layer,wherein the upper alignment layer has a first orientation direction, the lower alignment layer has a second orientation direction, the at least one intermediate alignment layer has an intermediate orientation direction, and the intermediate orientation direction is between the first orientation direction and the second orientation direction; anda liquid crystal material, comprising a plurality of liquid crystal material portions, each of the liquid crystal material portions being disposed between ...

Fabrication of Large Height Top Metal Electrode for Sub-60nm Magnetoresistive Random Access Memory (MRAM) Devices

A process flow for forming magnetic tunnel junction (MTJ) cells with a critical dimension CD≤60 nm by using a top electrode (TE) hard mask having a thickness≥100 nm prior to MTJ etching is disclosed. A carbon hard mask (HM), silicon HM, and photoresist are sequentially formed on a MTJ stack of layers. A pattern of openings in the photoresist is transferred through the Si HM with a first reactive ion etch (RIE), and through the carbon HM with a second RIE. After TE material is deposited to fill the openings, a chemical mechanical process is performed to remove all layers above the carbon HM. The carbon HM is stripped and the resulting TE pillars are trimmed to a CD≤60 nm while maintaining a thickness proximate to 100 nm. Thereafter, an etch process forms MTJ cells while TE thickness is maintained at ≥70 nm. 1. A method , comprising:forming a magnetic tunnel junction (MTJ) stack on a bottom electrode;forming a hard mask layer on the MTJ stack;forming an opening in the hard mask layer, the opening having a first dimension measured in a direction parallel to a top surface of the MTJ stack;filling the opening with a conductive material;after filling the opening, removing the hard mask layer to expose sidewalls of the conductive material;trimming the conductive material to form a top electrode (TE) pillar, the TE pillar having a second dimension, the second dimension being measured in the direction parallel to the top surface of the MTJ stack, the second dimension being less than the first dimension; andetching the MTJ stack using the TE pillar as an etch mask, the etching of the MTJ stack exposing a top surface of the bottom electrode.2. The method of claim 1 , wherein the hard mask layer includes carbon.3. The method of claim 1 , wherein the second dimension is less than or equal to about 60 nanometers.4. The method of claim 1 , wherein a height of the TE pillar is substantially equal to 100 nm prior to the etching of the MTJ stack claim 1 , the height being measured in ...

AUTOMATIC SHOOTING RIBBON DISPENSER

A ribbon dispenser includes a body with a front cover. A cylinder is rotatably located in the body and has multiple chambers in which ribbons are received. An inlet is defined through the rear end of each chamber. A striking unit is located in the body and located behind the cylinder to introduce air into the chambers via the inlets. A revolving unit is connected to the cylinder to revolve the cylinder. A rigger is pivotably connected to the body has a driving portion to drive the striking unit. A stud protrudes from one side of the trigger so as to drive the revolving unit. The ribbons are ejected out from the body when the striking unit introduces air into the chambers. The cylinder is revolved to allow the ribbons in each room are ejected in sequence. 1. A ribbon dispenser comprising:a body being a hollow body;a front cover pivotably connected to a front end of the body and having a hole which communicates with an interior of the body;a cylinder rotatably located in the body and located behind a rear end of the front cover, the cylinder having multiple chambers in which ribbons are received, the chambers being arranged radially about a center of the cylinder, an opening of each chamber located behind the rear end of the front cover, an inlet defined through a rear end of each chamber;a striking unit located in the body and located behind the cylinder so as to introduce air into the chambers via the inlets;a revolving unit located in the body and connected to the cylinder so as to revolve the cylinder, anda rigger pivotably connected to the body and located outside of the body, the trigger having a driving portion on a rear end thereof so as to drive the striking unit, a stud protruding from a side of the trigger so as to drive the revolving unit,wherein the striking unit comprises a tube, a piston, a compression spring, an arm, a link and a pawl, the tube is located behind the rear end of the cylinder and has an outlet defined in a front end thereof, the piston ...

STRUCTURE AND METHOD FOR MRAM DEVICES

A semiconductor device includes a bottom electrode; a magnetic tunneling junction (MTJ) element over the bottom electrode; a top electrode over the MTJ element; and a sidewall spacer abutting the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacer includes a magnetic material.

SEMICONDUCTOR PACKAGE WITH COMPOSITE THERMAL INTERFACE MATERIAL STRUCTURE AND METHOD OF FORMING THE SAME

A semiconductor package is provided. The semiconductor package includes a substrate and a semiconductor die over the substrate. A heat-dissipating feature covers the substrate and the semiconductor die, and a composite thermal interface material (TIM) structure is thermally bonded between the semiconductor die and the heat-dissipating feature. The composite TIM structure includes a metal-containing matrix material layer and polymer particles embedded in the metal-containing matrix material layer. 1. A semiconductor package , comprising:a substrate;a semiconductor die over the substrate;a heat-dissipating feature over the substrate and covering the semiconductor die; and a metal-containing matrix material layer; and', 'a plurality of polymer particles embedded in the metal-containing matrix material layer., 'a composite thermal interface material (TIM) structure thermally bonded between the semiconductor die and the heat-dissipating feature, comprising2. The semiconductor package as claimed in claim 1 , wherein the composite TIM structure further comprises a plurality of metal covers respectively surrounding the plurality of polymer particles.3. The semiconductor device structure as claimed in claim 2 , wherein each of the plurality of metal covers comprises a first layer and a second layer surrounding the first layer claim 2 , and wherein the first layer is made of a metal material that is different from a material of the second layer.4. The semiconductor package as claimed in claim 3 , wherein the second layer is made of copper claim 3 , silver claim 3 , or gold.5. The semiconductor package as claimed in claim 1 , wherein the metal-containing matrix material layer is made of a solder paste claim 1 , a silver paste claim 1 , an indium paste claim 1 , or a nano-metal ink claim 1 , and each of the plurality of polymer particles is made of polystyrene or polymethyl methacrylate.6. The semiconductor package as claimed in claim 1 , further comprising a metallization ...

Dual Magnetic Tunnel Junction (DMTJ) Stack Design

A dual magnetic tunnel junction (DMTJ) is disclosed with a PL/TB/free layer/TB/PL/capping layer configuration wherein a first tunnel barrier (TB) has a substantially lower resistance×area (RA) product than RAfor an overlying second tunnel barrier (TB) to provide an acceptable net magnetoresistive ratio (DRR). Moreover, magnetizations in first and second pinned layers, PL and PL, respectively, are aligned antiparallel to enable a lower critical switching current than when in a parallel alignment. An oxide capping layer having a RAis formed on PL to provide higher PL stability. The condition RA Подробнее

Highly Physical Etch Resistive Photoresist Mask to Define Large Height Sub 30nm Via and Metal Hard Mask for MRAM Devices

A conductive via layer is deposited on a bottom electrode, then patterned and trimmed to form a sub 20 nm conductive via on the bottom electrode. The conductive via is encapsulated with a first dielectric layer, which is planarized to expose a top surface of the conductive via. A MTJ stack is deposited on the encapsulated conductive via wherein the MTJ stack comprises at least a pinned layer, a barrier layer, and a free layer. A top electrode layer is deposited on the MTJ stack and patterned and trimmed to form a sub 30 nm hard mask. The MTJ stack is etched using the hard mask to form an MTJ device and over etched into the encapsulation layer but not into the bottom electrode wherein metal re-deposition material is formed on sidewalls of the encapsulation layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device. 1. A method for fabricating a magnetic tunneling junction (MTJ) structure comprising:depositing a conductive via layer on a bottom electrode;patterning said conductive via layer and then trimming said conductive layer to form a sub 20 nm conductive via on said bottom electrode;encapsulating said conductive via with a first dielectric layer and planarizing said first dielectric layer to expose a top surface of said conductive via;thereafter depositing a MTJ stack on encapsulated said conductive via wherein said MTJ stack comprises at least a pinned layer, a barrier layer on said pinned layer, and a free layer on said barrier layer;depositing a top electrode layer on said MTJ stack;patterning said top electrode layer and then trimming said top electrode layer to form a sub 30 nm hard mask; andthereafter etching said MTJ stack using said hard mask to form an MTJ device and over etching said MTJ stack into said encapsulation layer but not into said bottom electrode wherein metal re-deposition material is formed on sidewalls of said encapsulation layer underlying said MTJ device and not on sidewalls of a barrier layer of said MTJ ...

Self-Aligned Encapsulation Hard Mask To Separate Physically Under-Etched MTJ Cells To Reduce Conductive R-Deposition

A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure. 1. A method comprising:forming a stack of magnetic tunneling junction (MTJ) layers over a bottom electrode;forming a top electrode layer on the stack of MTJ layers;forming a hard mask on the top electrode layer;patterning the top electrode layer while using the hard mask as a mask;patterning a first portion of the stack of MTJ layers while using the hard mask as a mask such that a second portion of the stack of MTJ layers is not patterned by the patterning of the first portion of the stack of MTJ layers;forming an encapsulation layer over the patterned first portion of stack of MTJ layers, the second portion of the stack of MTJ layers and the hard mask;removing a portion of the encapsulation layer thereby forming a self-aligned hard mask on sidewalls of the patterned first portion of the stack of MTJ layers; andpatterning the second portion of the stack of MTJ layers while using the hard mask and the self-aligned hard mask as a mask.2. The method of claim 1 , wherein the second portion of the stack of MTJ layers includes a seed layer.3. The method of claim 1 , wherein the patterned first portion of the stack of MTJ layers ...

FLEXIBLE, ADJUSTABLE LENS POWER LIQUID CRYSTAL CELLS AND LENSES

A flexible optical element adopting liquid crystals (LCs) as the materials for realizing electrically tunable optics is foldable. A method for manufacturing the flexible element includes patterned photo-polymerization. The LC optics can include a pair of LC layers with orthogonally aligned LC directors for polarizer-free properties, flexible polymeric alignment layers, flexible substrates, and a module for controlling the electric field. The lens power of the LC optics can be changed by controlling the distribution of electric field across the optical zone. Lens power control can be provided using combinations of electrode configurations, drive signals and anchoring strengths in the alignment layers. 1. An electrically tunable lens , comprising:a first alignment layer and a second alignment layer;an active layer comprising liquid crystal confined between the first and second alignment layers in an optical path of the lens;a first electrode disposed above the first alignment layer, the first electrode having a first patterned opening disposed over an aperture region of the active layer; anda second electrode disposed below the second alignment layer, the second electrode having a second patterned opening arranged to induce in combination with the first electrode an electric field in the active layer.2. The electrically tunable lens of claim 1 , wherein the first and second patterned openings have circular shapes.3. The electrically tunable lens of claim 1 , wherein the first and second patterned openings have circular shapes with a common radius.4. The electrically tunable lens of claim 1 , including a first resistive layer disposed above the first alignment layer and a second resistive layer disposed below the second alignment layer.5. The electrically tunable lens of claim 1 , including an array of elastic polymer posts in the active layer between the first alignment layer and the second alignment layer claim 1 , posts in the array extending from the first ...

INTAKE SWIRL GASKET

An intake swirl gasket is disclosed herein. It is installed between a cylinder head and an intake manifold and comprises plural airflow holes for respectively communicating with plural intake passages of the cylinder head; and plural diversion devices respectively disposed in the plural airflow holes and each having an axis and plural splitter blades extended from the axis for connecting to an inner wall of each of the plural airflow holes, wherein each of the plural splitter blades is shaped as an arc to form a recessed surface towards the intake manifold at one side thereof and a convex surface towards the cylinder head at the other side thereof, and wherein an included angle between each of the plural splitter blades and an end face of the intake swirl gasket oriented towards the cylinder head ranges from 50 to 80 degrees. 1. An intake swirl gasket , installed between a cylinder head and an intake manifold , comprising:plural airflow holes for respectively communicating with plural intake passages of the cylinder head; andplural diversion devices respectively disposed in the plural airflow holes and each having an axis and plural splitter blades extended from the axis for connecting to an inner wall of each of the plural airflow holes, wherein each of the plural splitter blades is shaped as an arc to form a recessed surface towards the intake manifold at one side thereof and a convex surface towards the cylinder head at the other side thereof, and wherein an included angle between each of the plural splitter blades and an end face of the intake swirl gasket oriented towards the cylinder head ranges from 50 to 80 degrees.2. The intake swirl gasket as claimed in claim 1 , wherein the inner wall of each of the plural airflow holes defines a tapered opening to increase flow velocity of airflows through the plural splitter blades.3. The intake swirl gasket as claimed in claim 1 , further being formed integrally with the intake manifold4. The intake swirl gasket as ...

RATCHET WRENCH AND METHOD FOR ASSEMBLING THE SAME

A ratchet wrench includes wrench body having a head which has a first side and a second side. A through hole is defined through the first and second sides. A first face and a second face are formed on the inner periphery of the through hole. The first face faces the first side. The second face faces the second side. A ratchet wheel is rotatably accommodated in the through hole and includes a first surface formed in a radial direction of the ratchet wheel, and the ratchet wheel further includes a second surface which extends in the axial direction of the ratchet wheel. The first surface contacts the second face. The second surface contacts the first face which is located substantially in an axial direction of the through hole. A sharp angle is formed between the first and second surfaces. 1. A ratchet wrench comprising:a wrench body having a head with a first side and a second side which is located opposite to the first side, a through hole defined through the head of the wrench body and communicating with the first and second sides, a first face and a second face formed on an inner periphery of the through hole, the first face facing the first side, the second face facing the second side, anda ratchet wheel rotatably accommodated in the through hole and including a first surface formed in a radial direction of the ratchet wheel, the ratchet wheel including a second surface which extends in an axial direction of the ratchet wheel, the first surface contacting the second face, the second surface contacting the first face which is located substantially in an axial direction of the through hole, a sharp angle formed between the first and second surfaces.2. The ratchet wrench as claimed in claim 1 , wherein the first face is inclined from the first side of the head of the wrench body toward the second side of the head of the wrench body claim 1 , the first face extends toward an axis of the through hole.3. The ratchet wrench as claimed in claim 1 , wherein the second ...

CONDUCTOR PATTERN STRUCTURE OF CAPACITIVE TOUCH PANEL

Disclosed is a conductor pattern structure of a capacitive touch panel. The structure contains two conductor assemblies with different directions, and each conductor assembly includes a number of conductive cells that are interconnected by conduction lines. Conductor assemblies with different directions are separated by an insulating material. An electrical field and induced capacitors are generated between adjacent conductor assemblies with different directions when giving control signals. Then the touched location is detected. The capacitive induced layer structure also contains a number of floating induced cells, distributed among the adjacent conductive cells. The floating induced cells generate new induced capacitors without connecting to any conduction lines and requiring any control signals. Therefore, the structure has advantages of improving the distribution of the electrical field and enlarging the touch sensing area. 1. A capacitive touch panel , having a conductor pattern structure formed on a surface of a substrate , comprising:a plurality of first axial conductor assemblies, each first axial conductor assembly comprising a plurality of first axial conductive cells formed on the surface of the substrate along a first axial direction;a plurality of second axial conductor assemblies, each second axial conductor assembly comprising a plurality of second axial conductive cells formed on the surface of the substrate along a second axial direction;a plurality of first axial conduction lines, each connecting every adjacent first axial conductive cells in one first axial conductor assembly, respectively;a plurality of insulators, each formed between adjacent second axial conductive cells in one second axial conductor assembly, respectively;a plurality of second axial conduction lines, each crossing surfaces of corresponding insulators and connecting every adjacent second axial conductive cells in one second axial conductor assembly, respectively; anda plurality ...

Mg Discontinuous Insertion Layer for Improving MTJ Shunt

A MTJ is disclosed with a discontinuous Mg or Mg alloy layer having a thickness from 1 to 3 Angstroms between a free layer and a capping layer in a bottom spin valve configuration. It is believed the discontinuous Mg layer serves to block conductive material in the capping layer from diffusing through the free layer and into the tunnel barrier layer thereby preventing the formation of conductive channels that function as electrical shunts within the insulation matrix of the tunnel barrier. As a result, the “low tail” percentage in a plot of magnetoresistive ratio vs Rp is minimized which means the number of high performance MTJ elements in a MTJ array is significantly increased, especially when a high temperature anneal is included in the MTJ fabrication process. The discontinuous layer is formed by a low power physical vapor deposition process. 1. A magnetic tunnel junction (MTJ) , comprising:(a) a free layer having perpendicular magnetic anisotropy (PMA) that contacts a top surface of a tunnel barrier layer;(b) a capping layer as the uppermost layer in the MTJ; and(c) a discontinuous Mg or MgM alloy insertion layer formed between the free layer and the capping layer where M is one of Ta, Ti, V, Mo, Zr, Hf, Pt Pd, W, Nb, Rh, Ru, Cu, Cr, or Ir, and M has a content less than about 5 atomic % in the MgM alloy.2. The MTJ of wherein the discontinuous Mg or MgM alloy insertion layer has a thickness from about 1 to 3 Angstroms.3. The MTJ of further comprised of a reference layer that contacts a bottom surface of the tunnel barrier layer claim 1 , the reference layer is comprised of one or more ferromagnetic layers wherein a magnetic moment in each ferromagnetic layer is aligned in the plane of each ferromagnetic layer claim 1 , or the magnetic moment is aligned perpendicular to the plane in each of the ferromagnetic layers.412121212. The MTJ of wherein the reference layer is comprised of a laminate represented by (A/A)wherein A is a first metal or alloy comprising one or ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A semiconductor device includes a PMOS region and a NMOS region on a substrate, a first fin-shaped structure on the PMOS region, a first single diffusion break (SDB) structure in the first fin-shaped structure, a first gate structure on the first SDB structure, and a second gate structure on the first fin-shaped structure. Preferably, the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region. 1. A semiconductor device , comprising:a first MOS region comprises a PMOS region and a second MOS region comprises a NMOS region on a substrate:a first fin-shaped structure on the PMOS region;a first single diffusion break (SDB) structure in the first fin-shaped structure;a first gate structure on the first SDB structure;a second gate structure on the first fin-shaped structure, wherein the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region of the first MOS region;a second fin-shaped structure on the NMOS region;a second SDB structure in the second fin-shaped structure; anda third gate structure on the second SDB structure and a fourth gate structure on the second fin-shaped structure, wherein the third gate structure and the fourth gate structure are of same material, the third gate structure disposed directly on top of the second SDB structure is a metal gate and the fourth gate structure disposed on the second fin-shaped structure is also a metal gate in the NMOS region of the second MOS region.2. The semiconductor device of claim 1 , wherein the first SDB structure comprises silicon nitride.3. The ...

ELECTRICALLY TUNABLE FOCUSING ACHROMATIC LENS

An electrically tunable focusing achromatic lens includes a first liquid crystal cell, a second liquid crystal cell, and first and second electrode layer units which have two predetermined patterns for permitting two predetermined radially varying electric fields to be generated to across the first and second liquid crystal cells, respectively, to thereby allow one of the first and second liquid crystal cells to acquire a predetermined positive optical power and the other one of the first and second liquid crystal cells to acquire a predetermined negative optical power. When an incident light passes through the first and second liquid crystal cells, chromatic aberration of the first liquid crystal cell can be counterbalanced by that of the second liquid crystal cell. 1. An electrically tunable focusing achromatic lens comprising: a pair of first alignment layers which are spaced apart from each other along a normal line, and', 'a plurality of first liquid crystal molecules which have a first dielectric anisotropy, and which are filled between and aligned by said first alignment layers to orient in a first orientation;, 'a first liquid crystal cell for receiving an incident light, including'} a pair of second alignment layers which are spaced apart from each other along said normal line, and', 'a plurality of second liquid crystal molecules which have a second dielectric anisotropy, and which are filled between and aligned by said second alignment layers to orient in a second orientation that is orthogonal to or parallel to said first orientation; and, 'a second liquid crystal cell which is disposed rearward of said first liquid crystal cell, and which includes'}a first electrode layer unit and a second electrode layer unit, which are disposed to be separated from each other along said normal line, to supply voltage to said first and second liquid crystal cells, and which have two predetermined patterns so as to generate a first predetermined radially varying ...

Etching and Encapsulation Scheme for Magnetic Tunnel Junction Fabrication

A plurality of conductive via connections are fabricated on a substrate located at positions where MTJ devices are to be fabricated, wherein a width of each of the conductive via connections is smaller than or equivalent to a width of the MTJ devices. The conductive via connections are surrounded with a dielectric layer having a height sufficient to ensure that at the end of a main MTJ etch, an etch front remains in the dielectric layer surrounding the conductive via connections. Thereafter, a MTJ film stack is deposited on the plurality of conductive via connections surrounded by the dielectric layer. The MTJ film stack is etched using an ion beam etch process (IBE), etching through the MTJ film stack and into the dielectric layer surrounding the conductive via connections to form the MTJ devices wherein by etching into the dielectric layer, re-deposition on sidewalls of the MTJ devices is insulating.

Multiple Hard Mask Patterning to Fabricate 20nm and Below MRAM Devices

A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers on a bottom electrode on a wafer is provided. A metal hard mask layer is provided on the MTJ stack. A stack of multiple dielectric hard masks is formed on the metal hard mask wherein each successive dielectric hard mask has etch selectivity with respect to its underlying and overlying layers. The dielectric hard mask layers are etched in turn selectively with respect to their underlying and overlying layers wherein each successive pattern size is smaller than the preceding pattern size. The MTJ stack is etched selectively with respect to the bottommost combination dielectric and metal hard mask pattern to form a MTJ device having a MTJ pattern size smaller than a bottommost pattern size. 1. A method for etching a magnetic tunneling junction (MTJ) structure comprising:providing a MTJ stack on a substrate;depositing a metal hard mask layer on said MTJ stack;depositing multiple dielectric hard masks on said metal hard mask wherein each successive dielectric hard mask has etch selectivity with respect to its underlying and overlying layers;forming a photo resist pattern on an uppermost said dielectric hard mask wherein said photo resist pattern has a first pattern size;etching said uppermost dielectric hard mask selectively with respect to said photo resist pattern and underlying said dielectric hard mask to form a dielectric hard mask pattern having a second pattern size smaller than said first pattern size;thereafter etching each succeeding dielectric hard mask selectively with respect to its underlying and overlying layers wherein each successive dielectric hard mask pattern is smaller than its preceding hard mask pattern wherein a bottommost dielectric hard mask is etched in conjunction with said metal hard mask to form a bottommost hard mask pattern; andthereafter etching said MTJ stack selectively with respect to said bottommost hard mask pattern to form a MTJ ...

Multiple Spacer Assisted Physical Etching of Sub 60nm MRAM Devices

A MTJ stack is deposited on a bottom electrode. A top electrode layer and hard mask are deposited on the MTJ stack. The top electrode layer not covered by the hard mask is etched. Thereafter, a first spacer layer is deposited over the patterned top electrode layer and the hard mask. The first spacer layer is etched away on horizontal surfaces leaving first spacers on sidewalls of the patterned top electrode layer. The free layer not covered by the hard mask and first spacers is etched. Thereafter, the steps of depositing a subsequent spacer layer over patterned previous layers, etching away the subsequent spacer layer on horizontal surfaces leaving subsequent spacers on sidewalls of the patterned previous layers, and thereafter etching a next layer not covered by the hard mask and subsequent spacers are repeated until all layers of the MTJ stack have been etched to complete the MTJ structure. 1. A method comprising:forming a first pinned layer over a substrate;forming a tunnel barrier layer over the first pinned layer;forming a free layer over the tunnel barrier layer;forming a patterned hard mask layer over the free layer;forming a first spacer layer on sidewalls of the patterned hard mask layer;patterning the free layer using the first spacer layer and the patterned hard mask layer as a mask to form a patterned free layer;forming a second spacer layer on sidewalls of the patterned free layer;patterning the tunnel barrier layer using the second spacer layer and the patterned hard mask layer as a mask to form a patterned tunnel barrier layer;forming a third spacer layer on sidewalls of the patterned tunnel barrier layer;patterning the first pinned layer using the third spacer layer and the patterned hard mask layer as a mask to form a patterned first pinned layer.2. The method of claim 1 , wherein the patterned free layer has a first width claim 1 ,wherein the patterned tunnel barrier layer has a second width,wherein the patterned first pinned layer has a third ...

Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications

A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)or (CoX)composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer. 1. A magnetic tunnel junction (MTJ) , comprising:(a) a seed layer formed on a substrate;{'sub': n', 'n, '(b) a free layer comprising a laminated stack that contacts a top surface of the seed layer, the laminated layer has intrinsic perpendicular magnetic anisotropy (PMA) and comprises a (Co/X)or (CoX)structure wherein X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, and Si, CoX is a disordered alloy, and n is the number of laminates in the stack;'}(c) a tunnel barrier layer formed on the free layer;(d) a reference layer formed on the tunnel barrier layer; and(e) and a capping layer formed on the reference layer.2. The MTJ of wherein the seed layer is Hf claim 1 , NiFeCr claim 1 , or NiCr claim 1 , or a composite with a Hf/NiCr claim 1 , Hf/NiFeCr claim 1 , NiFeCr/Hf claim 1 , or NiCr/Hf configuration and having a thickness between about 5 and 100 Angstroms.3. The MTJ of further comprised of a magnetic layer made of CoFeB claim 1 , CoFe claim 1 , or combinations thereof formed between the laminated stack and the tunnel barrier layer.4. The MTJ of wherein n is from 2 to 30.5. The MTJ of wherein each of the Co layers in the (Co/X)structure has a thickness ...

Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications

A MTJ for a spintronic device that is a domain wall motion device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)or (CoX)composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer. 1. A domain wall motion device , comprising:{'sub': n', 'n, '(a) a first stack comprising a lower seed layer and a laminated layer formed thereon wherein the first stack has a first width and wherein the seed layer is one or more of Hf, NiCr, and NiFeCr, and the laminated layer has intrinsic PMA and a composition represented by (Co/X)or (CoX)structure wherein X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, and Si, CoX is a disordered alloy, and n is the number of laminates in the stack; and'}(b) a second stack with a tunnel barrier/free layer/capping layer configuration and having a second width substantially greater than the first width, the tunnel barrier contacts a top surface of the first stack.2. The domain wall motion device of wherein the seed layer consists of Hf claim 1 , NiCr claim 1 , NiFeCr claim 1 , Hf/NiCr claim 1 , Hf/NiFeCr claim 1 , NiCr/Hf claim 1 , or NiFeCr/Hf.3. The domain wall motion device of further comprised of a magnetic layer made of CoFeB claim 1 , CoFe claim 1 , or combinations thereof that is formed between the laminated layer and the tunnel barrier layer claim 1 , the magnetic layer has ...

Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications

A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)or (CoX)composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer. 1. A magnetic element , comprising:(a) a seed layer comprising one or more of Hf, NiCr, and NiFeCr that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer; and{'sub': n', 'n, '(b) a layer having intrinsic PMA and comprising pure Co or a laminated stack represented by (Fe/V)where n is the number of laminates in the stack, and the Co or (Fe/V)laminated stack contacts a top surface of the seed layer.'}2. The magnetic element of wherein the seed layer and Co layer or Fe/V)laminated stack are formed in a magnetic tunnel junction (MTJ) having a seed layer/reference layer/tunnel barrier/free layer configuration claim 1 , the Co layer or (Fe/V)laminated stack is part of the reference layer.3. The magnetic element of wherein the reference layer further comprises a magnetic layer formed between the Co layer or (Fe/V)laminated stack and the tunnel barrier to increase a magnetoresistive (MR) ratio in the MTJ claim 2 , the magnetic layer interfaces with the tunnel barrier and has PMA with a magnetic moment in a same direction as the PMA in the Co layer or (Fe/V)laminated stack.4. The magnetic element of wherein the seed layer and Co layer or (Fe/V ...

SEMICONDUCTOR IMAGE SENSOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor image sensor device includes a semiconductor substrate, a radiation-sensing region, and a first isolation structure. The radiation-sensing region is in the semiconductor substrate. The first isolation structure is in the semiconductor substrate and adjacent to the radiation-sensing region. The first isolation structure includes a bottom isolation portion in the semiconductor substrate, an upper isolation portion in the semiconductor substrate, and a diffusion barrier layer surrounding a sidewall of the upper isolation portion. 1. A semiconductor image sensor device , comprising:a semiconductor substrate;a radiation-sensing region in the semiconductor substrate;a first isolation structure in the semiconductor substrate and adjacent to the radiation-sensing region, wherein the first isolation structure comprises:a bottom isolation portion in the semiconductor substrate;an upper isolation portion in the semiconductor substrate; anda diffusion barrier layer surrounding a sidewall of the upper isolation portion.2. The semiconductor image sensor device of claim 1 , wherein the semiconductor substrate has a first doping polarity claim 1 , and the radiation-sensing region has a second doping polarity opposite to the first doping polarity.3. The semiconductor image sensor device of claim 2 , further comprising a doped layer surrounding the sidewall of the bottom isolation portion claim 2 , wherein the doped layer has the first doping polarity.4. The semiconductor image sensor device of claim 1 , wherein the first isolation structure surrounds a periphery of the radiation-sensing region.5. The semiconductor image sensor device of claim 1 , wherein a depth of the first isolation structure is substantially equal to or greater than a depth of the radiation-sensing region.6. The semiconductor image sensor device of claim 1 , wherein a width of the upper isolation structure is substantially equal to a width of the bottom isolation structure.7. The semiconductor ...

Multilayer Structure for Reducing Film Roughness in Magnetic Devices

A seed layer stack with a uniform top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer on a smoothing layer such as Mg where the latter has a resputtering rate 2 to 30× that of the amorphous layer. The uppermost seed (template) layer is NiW, NiMo, or one or more of NiCr, NiFeCr, and Hf while the bottommost seed layer is one or more of Ta, TaN, Zr, ZrN, Nb, NbN, Mo, MoN, TiN, W, WN, and Ru. Accordingly, perpendicular magnetic anisotropy in an overlying magnetic layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The amorphous seed layer is SiN, TaN, or CoFeM where M is B or another element with a content that makes CoFeM amorphous as deposited. 1. A multilayer structure for reducing film roughness in a magnetic device , comprising:(a) a buffer layer that is one or more of Zr, ZrN, Nb, NbN, Mo, MoN, TiN, W, WN, and Ru, or one of more of the aforementioned materials with Ta or TaN that is formed on a substrate;(b) a first smoothing layer (S1) made of a material with a first bond energy, and having a first surface with an “as deposited” first peak to peak roughness, the S1 layer is formed on the buffer layer;(c) a second smoothing layer (S2) that is non-crystalline or nano-crystalline and is made of a material with a second bond energy that is greater than the first bond energy such that deposition of the S2 layer results in resputtering of the S1 layer to give a S1 layer with a second surface having a second peak to peak roughness substantially less than the “as deposited” first peak to peak roughness, and the S2 layer formed on the second surface, the upper second layer has a third surface with the second peak to peak roughness; and(d) an uppermost template layer with a top surface having the second peak to peak roughness, the template layer has a (111) crystal orientation ...

Under-Cut Via Electrode for Sub 60nm Etchless MRAM Devices by Decoupling the Via Etch Process

A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A first dielectric layer is deposited on a bottom electrode and partially etched through to form a first via opening having straight sidewalls, then etched all the way through to the bottom electrode to form a second via opening having tapered sidewalls. A metal layer is deposited in the second via opening and planarized to the level of the first dielectric layer. The remaining first dielectric layer is removed leaving an electrode plug on the bottom electrode. MTJ stacks are deposited on the electrode plug and on the bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and polished to expose a top surface of the MTJ stack on the electrode plug. A top electrode layer is deposited to complete the MTJ structure.

Multiply Spin-Coated Ultra-Thick Hybrid Hard Mask for Sub 60nm MRAM Devices

A metal hard mask layer is deposited on a MTJ stack on a substrate. A hybrid hard mask is formed on the metal hard mask layer, comprising a plurality of spin-on carbon layers alternating with a plurality of spin-on silicon layers wherein a topmost layer of the hybrid hard mask is a silicon layer. A photo resist pattern is formed on the hybrid hard mask. First, the topmost silicon layer of the hybrid hard mask is etched where is it not covered by the photo resist pattern using a first etching chemistry. Second, the hybrid hard mask is etched where it is not covered by the photo resist pattern wherein the photoresist pattern is etched away using a second etch chemistry. Thereafter, the metal hard mask and MTJ stack are etched where they are not covered by the hybrid hard mask to form a MTJ device and overlying top electrode. 1. A method comprising:forming a stack of magnetic tunnel junction (MTJ) layers over a substrate;forming a metal hard mask layer on the stack of MTJ layers;forming a dielectric layer on the metal hard mask layer; a first carbon-containing layer;', 'a first silicon-containing layer disposed on the first carbon-containing layer, the first silicon-containing layer having a first thickness;', 'a second carbon-containing layer disposed on the first silicon-containing layer; and', 'a second silicon-containing layer disposed on the second carbon-containing layer, the second silicon-containing layer having a second thickness that is different than first thickness;, 'forming a hybrid mask layer on the dielectric layer, wherein the hybrid mask layers includespatterning the second silicon-containing layer via a first process;patterning the second carbon-containing layer, the first silicon-containing layer and the first carbon-containing layer via a second process; andpatterning the dielectric layer, the metal hard mask layer and the stack of MTJ layers via a third process.2. The method of claim 1 , wherein the second thickness is greater than the first ...

Highly Selective Ion Beam Etch Hard Mask for Sub 60nm MRAM Devices

A via connection is provided through a dielectric layer to a bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. A top electrode is deposited on the MTJ stack. A selective hard mask and then a dielectric hard mask are deposited on the top electrode. The dielectric and selective hard masks are patterned and etched. The dielectric and selective hard masks and the top electrode are etched wherein the dielectric hard mask is removed. The top electrode is trimmed using IBE at an angle of 70 to 90 degrees. The selective hard mask, top electrode, and MTJ stack are etched to form a MTJ device wherein over etching into the dielectric layer surrounding the via connection is performed and re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device. 1. A method comprising:forming a dielectric layer over a bottom electrode;forming a stack of magnetic tunnel junction (MTJ) layers over the dielectric layer, the stack of MTJ layers includes a barrier layer;forming a top electrode over the stack of MTJ layers;forming a first hard mask layer over the top electrode; andpatterning the top electrode, the stack of MTJ layers and the dielectric layer by using the first hard mask layer as a mask, wherein the patterning re-deposits material on the dielectric layer without redepositing material on the barrier layer of the stack of MTJ layers.2. The method of claim 1 , wherein the stack of MTJ layers further includes a pinned layer claim 1 , the barrier layer disposed over the pinned layer and a free layer disposed over the barrier layer claim 1 , andwherein the patterning further re-deposits material on the pinned layer without redepositing material on the barrier layer and the free layer.3. The method of claim 1 , further comprising:removing the re-deposited material from the dielectric layer; andforming an encapsulating layer on the patterned dielectric layer, ...

IMAGE SENSOR WITH REDUCED OPTICAL PATH

Among other things, one or more image sensors and techniques for forming image sensors are provided. An image sensor comprises a photodiode array configured to detect light. The image sensor comprises an oxide grid comprising a first oxide grid portion and a second oxide grid portion. A metal grid is formed between the first oxide grid portion and the second oxide grid portion. The oxide grid and the metal grid define a filler grid. The filler grid comprises a filler grid portion, such as a color filter, that allows light to propagate through the filler gird portion to an underlying photodiode. The oxide grid and the metal grid confine or channel the light within the filler gird portion. The oxide grid and the metal grid are formed such that the filler grid provides a relatively shorter propagation path for the light, which improves light detection performance of the image sensor. 1. An image sensor , comprising:a photodiode array formed over a substrate;a first oxide grid portion of an oxide grid, the first oxide grid portion formed over the photodiode array;a metal grid formed over the first oxide grid portion;a second oxide grid portion of the oxide grid, the second oxide grid portion formed over the metal grid; anda filler grid formed between a top surface of the first oxide grid portion and a top surface of the second oxide grid portion.2. The image sensor of claim 1 , the filler grid comprising a first filler grid structure formed between a first metal grid structure of the metal grid and a second metal grid structure of the metal grid.3. The image sensor of claim 1 , the filler grid comprising a first filler grid structure formed between a first oxide grid structure of the second oxide grid portion and a second oxide grid structure of the second oxide grid portion.4. The image sensor of claim 1 , a bottom surface of the filler grid formed below the second oxide grid portion.5. The image sensor of claim 1 , a bottom surface of the filler grid formed below a ...

Dual Magnetic Tunnel Junction Devices for Magnetic Random Access Memory (MRAM)

A dual magnetic tunnel junction (DMTJ) is disclosed with a PL/TB/free layer/TB/PL configuration wherein a first tunnel barrier (TB) has a substantially lower resistance x area (RA) product than RAfor an overlying second tunnel barrier (TB) to provide an acceptable magnetoresistive ratio (DRR). Moreover, first and second pinned layers, PL and PL, respectively, have magnetizations that are aligned antiparallel to enable a lower critical switching current that when in a parallel alignment. The condition RA Подробнее

COMBINED PHYSICAL AND CHEMICAL ETCH TO REDUCE MAGNETIC TUNNEL JUNCTION (MTJ) SIDEWALL DAMAGE

A process flow for forming magnetic tunnel junction (MTJ) nanopillars with minimal sidewall residue and minimal sidewall damage is disclosed wherein a pattern is first formed in a hard mask that is an uppermost MTJ layer. Thereafter, the hard mask sidewall is etch transferred through the remaining MTJ layers including a reference layer, free layer, and tunnel barrier between the free layer and reference layer. The etch transfer may be completed in a single RIE step that features a physical component involving inert gas ions or plasma, and a chemical component comprised of ions or plasma generated from one or more of methanol, ethanol, ammonia, and CO. In other embodiments, a chemical treatment with one of the aforementioned chemicals, and a volatilization at 50° C. to 450° C. may follow an etch transfer through the MTJ stack with an ion beam etch or plasma etch involving inert gas ions. 1. A method comprising:providing a stack of magnetic tunnel junction (MTJ) layers on a first electrode wherein the stack of MTJ layers includes a reference layer, a free layer, and a tunnel barrier layer between the reference layer and free layer;patterning the stack of MTJ layers by a reactive ion etch that includes a physical component in the form of noble gas ions and a chemical component; andperforming a volatilization step to remove volatile residue from a sidewall of the patterned stack of MTJ layers after the reactive ion etch, wherein the volatilization step includes an etching process.2. The method of claim 1 , wherein the noble gas ions are selected from the group consisting of Ar claim 1 , Kr claim 1 , Ne claim 1 , and Xe.3. The method of claim 1 , wherein the chemical component includes ethanol claim 1 , ethanol claim 1 , HO claim 1 , HO claim 1 , NO claim 1 , NH claim 1 , and CO.4. The method of claim 1 , wherein the etching process includes a process selected from the group consisting of an ion beam etching process and a plasma sputter etching process.5. The method of ...

MTJ CD VARIATION BY HM TRIMMING

A MTJ stack is deposited on a bottom electrode. A metal hard mask is deposited on the MTJ stack and a dielectric mask is deposited on the metal hard mask. A photoresist pattern is formed on the dielectric mask, having a critical dimension of more than about 65 nm. The dielectric and metal hard masks are etched wherein the photoresist pattern is removed. The dielectric and metal hard masks are trimmed to reduce their critical dimension to 10-60 nm and to reduce sidewall surface roughness. The dielectric and metal hard masks and the MTJ stack are etched wherein the dielectric mask is removed and a MTJ device is formed having a small critical dimension of 10-60 nm, and having further reduced sidewall surface roughness. 1. A method comprising:forming a stack of magnetic tunneling junction (MTJ) layers over a substrate;forming a first mask on the stack of MTJ layers;forming a second mask on the stack of MTJ layers;patterning the first mask and the second mask;trimming the patterned first mask and the patterned second mask to reduce roughness of an outer edge of the patterned first mask and an outer edge of the patterned second mask; andpatterning the trimmed patterned second mask and the trimmed patterned first mask and the stack of MTJ layers, wherein the patterning of the trimmed patterned second mask and the trimmed patterned first mask further reduces the roughness of the outer edge of the trimmed patterned first mask and the outer edge of the trimmed patterned second mask.2. The method of claim 1 , wherein the second mask is formed of a different material than the first mask.3. The method of claim 1 , wherein the second mask includes a dielectric material and the first mask includes a conductive material.4. The method of claim 1 , wherein the trimmed patterned second mask has a critical dimension ranging from about 10 nm to about 60 nm.5. The method of claim 1 , forming a photoresist pattern on the second mask.6. The method of claim 1 , wherein the first mask ...

LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY

A layout pattern for magnetoresistive random access memory (MRAM) includes a first magnetic tunneling junction (MTJ) pattern on a substrate, a second MTJ pattern adjacent to the first MTJ pattern, and a third MTJ pattern between the first MTJ pattern and the second MTJ pattern. Preferably, the first MTJ pattern, the second MTJ pattern, and the third MTJ pattern constitute a staggered arrangement. 1. A layout pattern for magnetoresistive random access memory (MRAM) , comprising:a first word line, a second word line, and a third word line on a substrate;a first magnetic tunneling junction (MTJ) pattern between the first word line and the second word line;a second MTJ pattern adjacent to the first MTJ pattern and between the first word line and the second word line;a third MTJ pattern between the first MTJ pattern and the second MTJ pattern and between the second word line and the third word line, wherein the first MTJ pattern, the second MTJ pattern, and the third MTJ pattern comprise a staggered arrangement;a first metal interconnection pattern directly under the first MTJ pattern, wherein the first metal interconnection pattern overlaps the first word line and the first MTJ patterns; anda second metal interconnection pattern directly under the third MTJ pattern, wherein the second metal interconnection pattern overlaps the third word line and the third MTJ pattern.2. The layout pattern for MRAM of claim 1 , wherein the third MTJ pattern is disposed along a first direction relative to the first MTJ pattern claim 1 , the second MTJ pattern is disposed along a second direction relative to the third MTJ pattern claim 1 , and the second MTJ pattern is disposed along a third direction relative to the first MTJ pattern claim 1 , wherein the first direction claim 1 , the second direction claim 1 , and the third direction comprise a triangle.3. (canceled)4. The layout pattern for MRAM of claim 1 , wherein an angle included by the first direction and the third direction is ...

Image sensor device structure with doping layer in light-sensing region

An image sensor device structure is provided. The image sensor device structure includes a substrate, and the substrate is doped with a first conductivity type. The image sensor device structure includes a light-sensing region formed in the substrate, and the light-sensing region is doped with a second conductivity type that is different from the first conductivity type. The image sensor device structure further includes a doping region extended into the light-sensing region, and the doping region is doped with the first conductivity type. The image sensor device structure also includes a plurality of color filters formed on the doping region.