LOCAL CHECKPOINTING USING A MULTI-LEVEL CELL
Details for sucking paper powder Government The present invention refers to a financial by the Department of energy (Department of Energy) SC0005026-DE contract number in the Government layer with the assistance of works. The Government has rights constant the present invention. The present invention refers to multi-level cell (multi-level cell) using the local check pointing (local checkpointing) relates to a. A high-performance computing (high performance computing; HPC) system are typically complex mathematical and/or science information is side calculations. Such calculations are chemical are inter-reacted, of-simulations, signal analyses, simulation of structural analysis may include a, etc.. Due to complexity of the calculations, HPC systems are complete is calculated the often consumes a significant time (for example, several hours, days, such as weeks can). Calculations during hardware of disturbances, are bug application, memory (memory corruption) are damage, system deficiency (system fault), etc. such as errors occur and calculating data Mar and/or non consistent state to be can be. Such errors when the power, and HPC systems are from that subroutine and then resumes supplying calculations, calculations this processing time completing the may to be significantly increased and. The deflector recalculation the in order to reduce processing time, calculations during data calculated points in various (version) version of checkpoint for storing is carried out by using an acidulous are (checkpoint). Error is generated when, most recent computing system to recover data on from checkpoint, the recovered checkpoint calculated from. is resumed. In this manner, in a system checkpoint must restart completely calculation to prevent calculated by using the of and reducing the processing time can be used. The present purpose of the invention to reduce the calculation time the multi-level cell (multi-level cell) using the local check pointing (local checkpointing) by a rope.. According to one aspect of the present invention, multi-level herein pointing check the local reading data is described method, the method cell data in the multi-number 1 saved data is stored in a level number 1, number 1 of data representing a checkpoint cell data in the multi-number 2 saved data is stored in a level number 2, checkpoint to generate multi-level from the level number 1 data number 1 number 2 cell (copy) copy level includes a step of the dechlorination of. Figure 1 shows a multi-level cell (MLC) also exemplary non-volatile random access memory and (non-volatile random acces memory; NVRAM) configurations, as shown surface. Figure 2 shows a MLC NVRAM using an exemplary of memory block of Figure 1. Figure 3 shows a local time for selecting the memory exemplary implementing checkpointing an exemplary can be used of a memory controller of Figure 2. 2 bits per also Figure 4 shows a cell-having a multi-block. Figure 5 shows a bit 2 per also having an alternative multi-cell block. 3 bits per also Figure 6 shows a cell-having a multi-block. 4 bits per also Figure 7 shows a cell-having a multi-block. 4 bits per also Figure 8 shows a cell-having a multi-block. The memory controller exemplary Figure 9 shows a checkpoint operation to perform the exemplary that may be executed also flow representing readable command machine of Figure 3. The memory controller Figure 10 shows a exemplary checkpoint operation to perform the exemplary that may be executed also flow representing readable command machine of Figure 3. Figure 11 shows a exemplary implementing memory controller encoding of the thin film that may be executed perform a exemplary also flow representing readable command machine of Figure 3. Figure 12 shows a also to implement memory control exemplary 9, 10 and/or also the processor based system to execute readable command machine exemplary of Figure 11 an exemplary lot, and possible a steep of the platform processor of Figure 3. An exemplary disclosure herein is are manufacturing method, device and the articles have multi-level cell (MLC) non-volatile [...] access memory (NVRAM) of version using a memory (versioned).. Version memory in order to render, a disclosure herein and at least one data job data examples checkpoint (are) for encoding use an multi-level cell (MLC). Exemplary multi-level job data stored in bit number 1 cell checkpoint and illustrated multi-level data are stored bit number 2 cell. An exemplary disclosure herein is publicly known techniques are memory version a checkpoint techniques is relatively more than high speed with implementing further energy-efficient checkpointing can be used. NVRAM memory techniques of is more recent than (for example, phase change memory (phase change momory; PCRAM), [...] (memristor), etc.) than legacy (legacy) memory technology have a higher memory densities. Such further high density NVRAM memory technology used in the computing new smaller forward to. However, design users, engineer and user for example for the, memory leakage are, system of disturbances, such as bug application flows into or from the errors to NVRAM facing the risk of damage. According to bar such, examples a disclosure herein to remove or substantially reduced risk of damage to data in NVRAM to return to in a stable state can be used. A plurality a system publicly known version of data structures, checkpoint logging (logging) the procedures permits recovered from errors. However, the previous such plurality in systems the use of structure version of data said plurality version data architectures capable of accessing an specially designed software applications. Therefore, data structure is publicly known is the use of human with having a software application is limited by computing systems. A system in some publicly known, checkpoint logging for generating a checkpoint procedures lead to the memory in a geographically distinct sites to copy at. for their ability to (copy). However, excessively a memory for copying can be time-consuming, checkpoint to generate many memory operations are easily by using a small may still undergo errors. In order to overcome the errors, pointing type tire systems logging checkpoint during the process error can be recovered from to to generates to be big it became the green onion data log (log). However, is of the power performance and mechanisms causes a overhead. An exemplary disclosure herein is are manufacturing method, device and the articles have a high-performance computing (HPC) systems checked in allows the pointing. Examples a disclosure herein where the data is stored in its working data checkpoint the same multi-layer cell by storing an additional layer checkpoint operations realize exemplary. Checkpoint by drives the word same data, further data can be readily accessed and high speed is relatively more operations (write) memory write to the typical data being pointing check are used to irradiate a separate memory cell place (for example, remote check point server, the same computing system in separate memory device, [...] system of identical in a memory device separate memory prepared) is since no transmitted to. Examples a disclosure herein multi-level cell (MLC) non-volatile random access memory (NVRAM) information using the are stored in a. The MLC NVRAM representing stored information, encoding or to represent physical attributes memory cell use an (property value) value. Physical attributes of the memory cell value measuring attributes. referred or characteristic. Examples a disclosure herein, exhibits resistance with physical attributes. However, any other suitable type of attribute for example, capacitance value, atoms, such as value or the like to spindle corresponding to memory technology used in the based. According to bar such, any other type of memory related examples a disclosure herein further or alternatively can be used. Examples a disclosure herein multi-level cell (MLC) non-volatile random access memory (NVRAM) using checkpointing realize. Multi-level cells when lower divided into ranges, additional bit of data in cell can be are stored. For example, 4 of resistance ranges 2-level cells-having a multi-data can be store a pluratliy of bits in a. In such, 0-0 range resistance number 1 number 1 of data state of a memory cell of encoding and; number 2 number 2 resistance range of encoding and data state of a memory cell of 0-1; 1-0 number 3 resistance range of encoding and data state of a memory cell of number 3 ; number 4 resistance range encodes 1-1 of data state of a memory cell of number 4. When multi-level cell, an between the values of the pixels of different resistances time and to. and dissipating the energy. , And a greater resistance range (for example, higher resistivity, which can maintain contact resistance range encoded by) transitioning the mobile range little resistance longer (for example, lower resistivity, which can maintain contact resistance range encoded by) than transitioning the mobile relatively more time and energy is used. In some instances, pointing check are encoding, which can maintain contact resistance range during operation, memory operations are less resistance, and a greater resistance range is modified so the system transition range by checkpoint is used to produce a time and energy is is reduced. Figure 1 shows a multi-level cell (MLC) also exemplary non-volatile random access memory (NVRAM) is in configurations. Number 1 exemplary NVRAM cell (110) (boolean) the fire '0' (for example, state S0) indicative of resistance range of number 1 (for example, low resistance values) and a Buna '1' (for example, state S1) number 2 indicative of range of resistance (for example, high resistance values) using, cell (for example, bit (b0) having single-level NVRAM cell) one bit per are stored in a. Exemplary MLC NVRAM cells (120 and 130) as shown by lower NVRAM cells by partitioning the ranges, more information is within a cell NVRAM may be saved, thereby further density memory and, is made to be greater than about. Exemplary NVRAM cell (120) per the 2 bits (for example, bits (b1 and b0) indicative of resistance of range 4) storing and illustrated NVRAM cell (130) per the 3 bits (for example, bits (b2, b1 and b0) indicative of resistance of range 8) use an. In shown of Figure 1, each MLC NVRAM cell (120 and 130) more a finer granularity positive of to bring the cell resistance by using a store a plurality of bits in. Therefore, MLC NVRAM has an identical number of NVRAM cells since further more bits are stored, is carried out by using an acidulous increase the memory density. Other types of memory (for example, dynamic random access memory (dynamic random access memory; DRAM) alternatively from, has operating characteristics an asymmetric NVRAM. The recorded on the NVRAM NVRAM time and energy than attainable read from is-consuming. Furthermore, MLC NVRAM are read and write operations when using single-level cell (for example, number 1 exemplary NVRAM cell (110)) as compared to use an many memory cycles. In MLC NVRAM, using a plurality of stages read NVRAM stored in the cell (resolve) transferred through a resistance level is used. Furthermore, MLC (for example, cells (120 and 130)) during a manner that reading the most significant bit (most-significant bit) which takes is less time are used to irradiate (leat-significant bit) of least significant bit MLC read circuitry for reading necessary precision, it is then necessary to determine to bring the cell resistance is because. Similarly, MLC NVRAM cells at the time of recording a single-level reprogrammable are used to irradiate the time information is appropriate recording images picked up by the apparatus used is a normal been cell NVRAM series of to validate the is the use of the read operation. According to bar such, MLC NVRAM using publicly known techniques recover data is excessively a time and energy consumption can be effected. One of with their Figure 2 shows a reference number (215) a depicted at 4 having memory cells-level surfaces of an exemplary memory block (200) configured pointing check exemplary a in in (200) is. Other examples, memory block (200) any tack-multi-level cells may include. In shown, memory block (200) cells number 1 level (205) (for example, most significant bit (most significant bit; MSB)) and number 2 level (210) (for example, least significant bit (least significant bit; LSB)) MLC NVRAM cell having (for example, of Figure 1 NVRAM cell (120)) per is implemented using bit 2. In some instances, number 1 level (205) encrypt data to be stored on the work data and indicates the type of the, number 2 level (210) a checkpoint encrypt data to be stored on the. representation of the data. In some instances, as part of operation checking points a job data number 1 level (205) from level number 2 (210) is email transmitted to the. As used herein, a as, for errors that checkpoint, of disturbances and/or damage from for restoring is memory contents for use at a later in the memory is stored as data checkpoint or supports the memory statuses, at a point a specific time. referred. In shown, checkpoint a new check-points are stored as user wants for displaying the memory block (200) computed using a pointing check from an application perform instruction sometimes based on (for example, periodic basis, or-periodically) generated. Further or alternatively, any other checkpoint also results of recording a period and/or non-periodic method can be is used. For example, checkpoint a set number of reading and/or writing operations are followed by (for example, once for reading from and/or write operations after, back burn for reading and/or writing of operations are followed by, 10 and for circuit controlling isolation gates of burn for reading and/or writing of operations are followed by, and the like) can be generated, for a certain period time (1 ingredient, 15 ingredient, a time, and the like) can be generated after, and/or any other suitable time can be produced. Multi-level cell example shown (215) the cell even shown diagrammatically at bit 2-per MLC, a disclosure herein 2 or more bits per examples (for example, per 3 bits, 4 bit, etc. per) having respect to MLC may be embodied in. In some instances, to store checkpoint additional additional bit per is carried out by using an acidulous are. For example, number 1 layer (205) a workpiece can store an data, number 2 layer (210) the number 1 can store an data checkpoint, checkpoint number 2 number 3 layer. capable of storing the data. In some instances, multi-bit bits are can be joined to population. For example, the MLC having 4 bits per 2 of 2-bit groups can be grouped into, thereby 2 number 1 2-is job data of bits from being stored in a bit groups as well as a set of checkpoint data is number 2 2-bit groups from being stored in a.. Figure 3 shows a exemplary memory block (200) using a memory version can be used an exemplary memory controller (305) is of of Figure 2. The memory controller of example shown of Figure 1 (305) the check point processor (310), memory reader (320) and memory recorder (330) includes. Checkpoint exemplary of Figure 3 a processor for executing commands processor by implement, the additionally, or alternatively are have orders filled at type semiconductor (application specific integrated circuit; ASIC), programmable logic device (programmable logic device; PLD) and/or field programmable logic device (field programmable logic device; FPLD) (are) and/or other circuit elements can be implemented by. Processor checkpoint example shown (310) for generating the check point based on instruction generates check point. Of Figure 3 exemplary memory reader (320) has a processor for executing instructions but implemented by, or alternatively further ASIC, DSP, FPGA and/or other circuit elements can be implemented by. In some instances, exemplary memory reader (320) the check point processor (310) the same by a processor that is implemented. In shown, exemplary memory reader (320) a read for providing data in response to a request to checkpoint during operation and/or for using the data memory cell (215) reading data from a layer of. In some instances, memory reader (320) a read memory cell in response to the request (215) of. the method reads the data from the. In some instances, memory reader (320) a read in response to the request work layer does not reading data from layer. In response to read request work layer layer does not reading data from the memory reader (320) the memory cell work layer data stored more rapidly enables reading. Exemplary memory recorder of Figure 3 (330) has a processor for executing instructions but implemented by, or alternatively further ASIC, DSP, FPGA and/or other circuit elements can be implemented by. In some instances, exemplary memory recorder (330) the memory reader (320) and/or checkpoint processor (310) the same by a processor that is implemented. In shown, exemplary memory recorder (330) with the recording in response to the request and/or checkpoint during operation memory cell (215), and records the data on the of.. Figure 4 shows a 2 bits per also having a multi-level cell (400). a block of. In shown, 2 bits are b1 (405) and b0 (410) expressed in a. Exemplary multi-level cell (400) of a multi-level cell (400) modify a resistance 4 encoded by including data state two. Number 1 state S0 (420) the 0-0 and regeneration method of representation of the data number 1 resistance is formed with a plurality. Number 2 state S1 (425) 0-1 regeneration method of representation of the data and the number 2 resistance is formed with a plurality. Number 2 number 1 resistance greater than resistance. Number 3 state S2 (430) the 1-0 and regeneration method of representation of the data number 3 resistance is formed with a plurality. Number 3 resistance force is greater than resistance number 1 number 2 greater than resistance. Number 4 state S3 (435) the 1-1 and regeneration method of representation of the data number 4 resistance is formed with a plurality. Number 4 resistance resistance number 1, number 2 number 3 resistance and greater than each of resistance. According to bar such, resistance encoding are ordered the increase third step is for representing the binary numbers is standard order. In shown, work bits b1 (405) is represented by. Checkpoint bits b0 (410) is represented by. During normal operation, the interleaving device does not alter the bits checkpoint. According to bar such, number 1 state S0 (420) and number 3 state S2 (430) a working bit b1 (405) bit checkpoint modified contents b0 (410) each other when 0 data is checkpoint in. to the. Number 1 work data state transition (450) a working bit (405) 1 a (number 3 state S3 (430) such as) and 0 (number 1 state S0 (420) such as) a varied between. Checkpoint data data state transition work number 1 (450) during 0 being maintained. Additionally, number 2 state S1 (425) and number 4 state S3 (435) a working bit b1 (405) bit checkpoint and can be modified and contents b0 (410) each other when 1 data is checkpoint in. to the. Number 2 work data state transition (455) a working bit (405) 1 a (number 4 state S3 (435) such as) and 0 (number 2 state S2 (425) such as) a varied between. Checkpoint data data state transition work number 2 (455) during is maintained at 1. Checkpoint during operation, work bit b1 (405) encrypt data to be stored on the a checkpoint bit b0 (410) is to copy at. Number 1 checkpoint transition (470) the number 1 state S0 (420) of bit b1 (405) (0) a checkpoint bit b0 (410) email transmitted to the and performs operations to a state transition for representing a. In shown, transition checkpoint number 1 (470) has multi-level cell (400) based on types, and no more than relief area when in the different States (for example, multi-level cell (400) the number 1 state S0 (420) block 7 is slid as is) are used to irradiate work bit b1 (405) (0) checkpoint already is provided with a value that stored in bit b0 (410). because stored. Number 2 checkpoint transition (475) the number 2 state S1 (425) of bit b1 (405) (0) a checkpoint bit b0 (410) email transmitted to the operable to a state transition for representing a. In shown, transition checkpoint number 2 (475) has multi-discriminated cell (400) for number 2 state S1 (425) from state number 1 S0 (420). relief area when in the. According to bar such, multi-level cell (400) encoded by resistance transition checkpoint number 2 (475) is reduced during. Number 3 transition checkpoint (480) the number 3 state S2 (430) of bit b1 (405) (1) a checkpoint bit b0 (410) email transmitted to the operable to a state transition for representing a. In shown, transition pointer check number 3 (480) has multi-level cell (400) for number 3 state S2 (430) from state number 4 S3 (435). relief area when in the. According to bar such, multi-level cell (400) encoded by transition checkpoint number 3 resistance (480) for the color temperature. during. Number 4 transition checkpoint (485) the number 4 state S3 (435) of bit b1 (405) (1) a checkpoint bit b0 (410) email transmitted to the operable to a state transition for representing a. In shown, transition checkpoint number 4 (485) has multi-level cell (400) based on types, and no more than the wtru transitions to different States (for example, multi-level cell (400) the number 4 state S3 (435) block 7 is slid as is) are used to irradiate work bit b1 (405) stored in a value (1) is already checkpoint bit b0 (410). because stored. Figure 5 shows a bit 2 per also having an alternative multi-level cell (500). a block of. In shown, state coding which are (S0, S1, S2 and S3) state S0 is the state corresponding to the minimum resistance of S2 is maximum resistance is ordered so as to correspond to. As described above, multi-level cell (500) transition between a lens ranges different resistances of the. consumes time and energy. , And a greater resistance range (for example, higher resistivity, which can maintain contact resistance range encoded by) transitioning the mobile range little resistance longer (for example, lower resistivity, which can maintain contact resistance range encoded by) than transitioning the mobile more time and energy is used. According to bar such, pointing check encoding resistance of Figure 5 during operation, memory operation, and a greater resistance are lower range is modified so the system by transition range, a checkpoint is used to produce. to reduce time and energy. In an illustrated examples, multi-level cell of Figure 5 (500) state of encoding is carried out by using an acidulous rules of 2. First, work bit (are) b1 (405) (are) a stored value based on where 30 are grouped. Bit work for grouping (are) an upper surface of the internal bit (are) b1 (405) simple fast read and be are multi-level cell are used to irradiate (500) resistance of levels are subjected to an work bit (are) b1 (405) to determine the distinguishable enough to one another must is receives the first signals output from the (for example, work bit (are) b1 (405) and checkpoint bit (are) b0 (410) to determine the more resistance levels instead when they need to be distinguished from each other). Secondly, checkpoint bit (are) b0 (410) multi-level cell pointing type tire (500) is encoded to of the second drive. Therefore, as compared to e.g. of Figure 4, a state number 3 of Figure 5 shown S2 (530) and number 4 state S3 (535) identity of a sequence of encoding resistance to. reversed. In shown of Figure 5, number 1 state S0 (520) the 0-0 number 1 and 2 of a representation of the data is encoded by resistor values. Number 2 state S1 (525) 0-1 regeneration method of representation of the data and the number 2 resistance is formed with a plurality. Number 2 number 1 resistance greater most resistance. Number 3 state S2 (530) the 1-0 and regeneration method of representation of the data number 3 resistance is formed with a plurality. Number 3 resistance force is greater than resistance number 1 number 2 greater than resistance. Number 4 state S3 (535) the 1-1 and regeneration method of representation of the data number 4 resistance is formed with a plurality. Number 4 resistance resistance and number 1 but greater than the resistance number 2, number 3 smaller than rather than resistance. In shown of Figure 5, number 1 state S0 (520) and number 3 state S2 (530) a working bit b1 (405) bit checkpoint and can be modified and contents b0 (410) in checkpoint data is 0 when the instruction processor is to execute transition between a lens of each other during operation is. Number 1 work data state transition (550) the 1 (number 3 state S2 (530) such as) and 0 (number 1 state S0 (520) such as) of operating in the between bit (405) changing a. Checkpoint bit b0 (410) checkpoint data in data state transition work number 1 (550) in the range of power dissipation during a 0. In shown, data state transition work of Figure 5 number 1 (550) the of Figure 4 number 1 data state transition work consumes time and energy more material than would.. Additionally, number 2 state S1 (525) and number 4 state S3 (535) a working bit b1 (405) bit checkpoint and can be modified and contents b0 (410) in checkpoint data is 1 when the instruction processor is to execute during operation will transition amongst one another. Number 2 work data state transition (555) a working bits b1 (405) 1 a (number 4 state S3 (535) such as) and 0 (number 2 state S1 (525) such as) a varied between. Checkpoint bit b0 (410) checkpoint data in data state transition work number 2 (555) in the range of power dissipation during a 1. In shown, job data state transitions (450 and 455), checkpoint transitions of Figure 4 (470, 475, 480 and 480) are on the whole job data state transitions (550 and 555) and of Figure 5 checkpoint transitions (570, 575, 580 and 585) consumes time and energy more material than would.. Checkpoint during operation, work bit b1 (405) encrypt data to be stored on the a checkpoint bit b0 (410) is to copy at. Number 1 checkpoint transition (570) the number 1 state S0 (520) of bit b1 (405) (0) a checkpoint bit b0 (410) copies the a state transition for representing the operable to. In shown, transition checkpoint number 1 (570) has multi-level cell (500) based on types, and no more than the wtru transitions to different States (for example, multi-level cell (500), to be subsequently number 1 state S0 (520) has is still able to be attached to) are used to irradiate work bit b1 (405) stored in a value (0) have checkpoint bit b0 (410). because stored. Number 2 checkpoint transition (575) the number 2 state S1 (525) of bit b1 (405) (0) a checkpoint bit b0 (410) copies the a state transition and performs operations to represent a. In shown, transition checkpoint number 2 (580) has multi-level cell (500) for number 2 state S1 (525) from state number 1 S0 (520) .the wtru transitions to. According and bar such, multi-level cell (400) encoded by resistance transition checkpoint number 2 (575) during is reduced. Number 3 transition checkpoint (580) S2 (530) the number 3 state of bit b1 (405) (1) a checkpoint bit b0 (410) email transmitted to the and performs operations to a state transition for representing a. In shown, transition checkpoint number 3 (575) has multi-level cell (500) for number 3 state S2 (530) from state number 4 S3 (535). relief area when in the. According to bar such, multi-level cell (500) encoded by resistance transition checkpoint number 3 (580) is reduced during. When compared with an example shown of Figure 4, of Figure 5 multi-level cell (500) encoded by rather than increased resistance (such as transition checkpoint of Figure 4 number 3) and affirmatively, transition checkpoint number 3 (580) is reduced during. For reducing resistance of multi-cell of a multi-level transitions a transition for increasing the resistivity cell less than time and energy consumes, of Figure 5 shown example multi-level cell (500) pointing type tire of the existing method for encoding binary its own operations are order (order state of Figure 4 for example) using a multi-level cells further time and energy than a less makes it possible to. Number 4 transition checkpoint (585) S3 (535) the number 4 state of bit b1 (405) (1) a checkpoint bit b0 (410) email transmitted to the and performs operations to a state transition for representing a. In shown, transition checkpoint number 4 (585) has multi-level cell (500) based on types, and no more than the wtru transitions to different States (for example, multi-level cell (500), to be subsequently state number 4 S3 (535) to) are used to irradiate work bit b1 (405) stored in a value (1) have checkpoint bit b0 (410). because stored. 3 bits per also Figure 6 shows a having a multi-level cell (600). a block of. In shown, state coding which are (S0, S1, S2, S3, S4, S5, S6 and S7) state S0 is the state corresponding to the minimum resistance of S4 is maximum resistance is ordered so as to correspond to. In shown of Figure 6, multi-level cell (600) of the 2 stores the States checkpoint. Multi-level cell (600) a work bit b2 (605), number 1 checkpoint bit b1 (610) and number 2 checkpoint bit b0 (615) includes. Work during operation, multi-level cell (600) a variety of between States change from in (630). For example, job data state transitions (630) of a multi-level cell (600) a variable that represents the S0 (0-0-0 representation of the data of.) and state S4 (1-0-0 representation of the data of.), state S1 (0-0-1 representation of the data of.) and state S5 (1-0-1 representation of the data of.), state S2 (0-1-0 representation of the data of.) and state S6 (1-1-0 representation of the data of.) and state S3 (0-1-1 representation of the data of.) 888000083488 8 and checkpoint bits b1 (610) and b0 (615) stored in a check point value corresponding to state S7 (1-1-1-representation of the data of.) to transition between States each. Work bit b2 (605) is changed during such work state transition, number 1 checkpoint bit b1 (610) and number 2 checkpoint bit b0 (615) has continues unchanged has is still able to be attached to. For example, checkpoint data is stored back 0-1, work bit b2 (605) for changing a task status transitions (630) the checkpoint bits b1 (610) and b0 (615) in checkpoint data changes without multi-level cell to be kept at (600) for S1 and S5 to transition between a lens. During operations checkpoint, checkpoint transitions (640) the number 1 checkpoint bit b1 (610) number 2 is encrypt data to be stored on the checkpoint bit b0 (615) bit is inserted by a to copy at b2 (605) number 1 is encrypt data to be stored on the checkpoint bit b1 (610) to States to copy at S0, S1, S2, S3, S4, S5, S6 and S7 between different States of multi-level cell (600) the pressure is reduced to the transition to. During such checkpoint operations, multi-level cell (600) higher resistance is transferred to encoding resistance lower from encoding. For example, state S4 (1-0-0 representation of the data of.) the state S4 state having encoding low resistance than S6 is the wtru transitions to. Figure 7 shows a 4 bits per also having a multi-level cell (700) a block of.. In shown, state coding which are (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14 and S15) state S0 is the state corresponding to the minimum resistance of S8 is maximum resistance is ordered so as to correspond to. In shown of Figure 7, multi-level cell (700) the three checkpoint stores the States. Multi-level cell (700) bit a workpiece b3 (705), number 1 checkpoint bit b2 (710), number 2 checkpoint bit b1 (715) and number 3 checkpoint bit b0 (720) includes. Further or alternatively, that can be stored the state checkpoint for example, 5 bits, 10 bits, 16 bits, 32 at least one bit selected of any other number of bits can be used. Of Figure 7 shown a multi-level cell (700) exemplary of encoding status with respect to. it is shown a order. However, for encoding state or treated in an order different from the order can be used alternatively. Work during operation, task status transitions (730) of a multi-level cell (700) is exemplified States, a S0 (0-0-0-0 representation of the data of.), S1 (0-0-0-1 representation of the data of.), S2 (0-0-1-0 representation of the data of.), S3 (0-0-1-1 representation of the data of.), S4 (0-1-0-0 representation of the data of.), S5 (0-1-0-1 representation of the data of.), S6 (0-1-1-0 representation of the data of.), S7 (0-1-1-1 representation of the data of.), S8 (1-0-0-0 representation of the data of.), S9 (1-0-0-1 representation of the data of.), S10 (1-0-1-0 representation of the data of.), S11 (1-0-1-1 representation of the data of.), S12 (1-1-0-0 representation of the data of.), S13 (1-1-0-1 representation of the data of.), S14 (1-1-1-0 representation of the data of.) and stored corresponding to a check point value S15 (1-1-1-1 representation of the data of.) to transition between States each. During state transitions a workpiece, such as thereof, number 1 checkpoint bit b2 (710), number 2 checkpoint bit b1 (715), number 3 checkpoint bit b0 (720) are unchanged to a non-archived state. For example, checkpoint data is stored back 0-0-0, work bit b3 (705) to change a task status transitions (730) the checkpoint bits b2 (710), b1 (715) and b0 (720) a check-point data do not vary to remain unencrypted multi-level cell (700) for States S0 and S8 to transition between a lens. During operations checkpoint, checkpoint transitions (740) of a multi-level cell (700) for, number 2 checkpoint bit b1 (715) number 3 is encrypt data to be stored on the checkpoint bit b0 (720) is email transmitted to the, number 1 checkpoint bit b2 (710) number 2 is encrypt data to be stored on the checkpoint bit b1 (715) is email transmitted to the, work bit b3 (705) number 1 is encrypt data to be stored on the checkpoint bit b2 (710) transition to in a state that is email transmitted to the. During such checkpoint operations, multi-level cell (700) higher resistance encoding lower resistance is transition encoding. For example, state S4 (0-1-0-0 representation of the data of.) status S2 (0-0-1-0 representation of the data of.) is the wtru transitions to. Figure 8 shows a 4 bits per also having a multi-level cell (800) a block of.. In shown of Figure 8, number of bits bit groups (are) 30 are grouped to form. Work bit groups b3 b2 (805) the 2 bits for representing and checkpoint bit groups b1 b0 (810) representing the 2 bits. Further or alternatively, bit groups to any other number of bits can be used. Furthermore, any number of bit groups are can be used. In shown, number of bits per (for example, 4 bits per) converts a bit group is divided uniformly the number of bit per (for example, 2 bits per bit groups). In some instances, number of bits per bit per bit groups uniformly by the number of divided not. Such examples, remaining bits not used. However, in some instances, remaining bits for example state information or other types of information for storing is carried out by using an acidulous. Of Figure 8 shown a multi-level cell (800) exemplary of encoding status with respect to. it is shown a order. In shown, state coding which are (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14 and S15) state S0 is the state corresponding to the minimum resistance of S14 is maximum resistance is ordered so as to correspond to. In shown as shown, work bit groups b3 b2 (805) the same values 30 are grouped for encoding with each other. Work bit groups b3 b2 (805) group encoding status it is multi-level cell (500) resistance of bit groups this task levels b3 b2 (805) distinguishable enough to one another to determine the, avoiding the need to more rapidly are converted into heat and enables a read operation. Furthermore, in shown as shown, state encoding same work bit groups b3 b2 (805) value of in in group of each of encoding state having, work bit groups b3 b2 (805) having a value equal to the checkpoint bit groups b1 b0 (810) is smallest is ordered to have a feedback circuit including a resistor and. Work bit groups b3 b2 (805) having a value the same checkpoint bit groups b1 b0 (810) by having, an efficient lowest resistance by enabling checkpoint operations, multi-level cell (800) resistance of checkpoint is reduced while operating. Therefore, for example, state S14, S13 and/or S12 can be order of. Work during operation, task status transitions (830) of a multi-level cell (800) for States S0 to S15 to transition between different States of. For example, multi-level cell (800) a work bit groups b3 b2 (805) the state based on data being recorded on a S0, state S4, state S8 and S12. may be transition between a lens. In shown, checkpoint bit groups b1 b0 (810) work values are stored in a as the same state during operation. while the condensed liquid remains liquid. During operations checkpoint, checkpoint transitions (840) of a multi-level cell (800) for, work bit groups b3 b2 (805) encrypt data to be stored on the is checked point bit groups b1 b0 (810) transition to in a state that is to copy at. According to bar such, multi-level cell (800) higher resistance is transition encoding resistance from the encoding (840). For example, state S7 (0-1-1-1 representation of the data of.) status S5 (0-1-0-1 representation of the data of.) is the wtru transitions to. Also to memory control 3 (305) spirit implementing an exemplary scheme is shown, also elements that are shown in 3, processes and/or devices of any other one or more ways to the coupling, separation, rearrangement, omitted, removing and/or may be embodied in. Furthermore, exemplary checkpoint processor (310), exemplary memory reader (320), exemplary memory recorder (330) and/or more generally of Figure 3 exemplary memory controller (305) hardware, software, firmware, and/or hardware, software and/or firmware any combination of, can be implemented by. Therefore, for example, exemplary checkpoint processor (310), exemplary memory reader (320), exemplary memory recorder (330) and/or more generally of Figure 3 exemplary memory controller (305) any one of one or more circuit (are), programmable processor (are), semiconductors on demand (are ASIC), programmable logic devices (PLD are) and/or field programmable logic devices (FPLD are) by may be embodied in. The present patent device of purely multiplet for charging any claims or system software and/or firmware implementation encompasses to during the reading out, exemplary checkpoint processor (310), exemplary memory reader (320) and/or exemplary memory recorder (330) by a backing layer, which is at least one to store firmware which has software and/or by a memory, DVD, CD and BLU-ray (blu-ray) type computer readable storage medium to include is defined it is apparent that. Further additionally, memory controller exemplary of Figure 3 (305) has door 3 in addition to those shown in, or such one or more elements instead, processes and/or devices may include components shown and/or, any of devices processes and comprising at least one or all device can be. Memory controller of Figure 3 (305) for implementing a exemplary machine readable command representing 9 also are also flow, also is shown in 11 also and/or 10. Examples is, machine readable instructions also 12 a refers to connection with the exemplary processor platform (1200) the rotary input device and a processor shown in (1212) executed by the processor, such as one or more program (are) includes. CD-ROM program, floppy disk, hard drive, digital versatile disc (digital versatile disk; DVD), central processing unit BLU-ray discs (1212) associated with the computer-readable storage medium local input/output line and then implemented in software stored on can be degraded and, entire program and/or any portions of thereof are alternatively processor (1212) other is to be executed by the device or dedicated firmware and/or can be implemented in hardware. Furthermore, a program exemplary 9, also 10, 11 also and/or reference to degrees the flow which is shown in even described, exemplary memory controller (305) many other for implementing method treated or alternatively can be used. For example, blocks can be changed in order of execution of which is described and/or change a part of the block, removal or can be combined.. As described above, also 9, also 10, and/or of Figure 11 exemplary processes hard disk drive, flash memory, read only memory (read-only memory; ROM), compact disk (CD), digital versatile disc (DVD), cache (cache), random access memory (RAM) for the duration of and/or any (for example, an extended period of time during the periods of, permanently, short instances, temporarily buffers having a during, and/or during catching of information) core or any other information is stored a storage medium specifies such a computer readable medium (for example, type computer readable storage medium) coding instructions are stored on (for example, computer readable instructions) may be embodied in using. As used herein, a as, terms type computer readable storage medium any type of computer-readable storage medium includes, propagation signals unambiguous clearing the film is defined. Further or alternatively, also 9, also 10, and/or of Figure 11 exemplary processes hard disk drive, flash memory, read only memory, compact disc, digital versatile disc, cache, random access memory and/or any for the duration of (for example, an extended period of time during the periods of, permanently, short instances, temporarily buffers having a during, and/or during catching of information) information, such as a storage medium any other stored on a computer readable medium, temporarily a coding instructions are (for example, computer readable instructions) may be embodied in using. As used herein, a as, computer readable media temporarily non terms any type of computer readable medium while removing the signals and propagating unambiguous is defined. As used herein, a as, expression "at least" is connected at preambles of claims when used as terms, the terms "including" limited in the same manner as the people, Letters and the thing which does not two restrictions. Therefore, "at least" itself can be made using another terms connected at the generic part of Patent claim claims concern, which is referred to, become manifest in other than those may include a elements. Figure 9 shows a exemplary checkpoint the memory controller to perform an operation that may be executed exemplary machine readable instructions (900) is indicating the flow also of Figure 3. Shown example of Figure 9 a single checkpoint state multi-level cell (for example, of Figure 4 multi-level cell (400), of Figure 5 multi-level cell (500), multi-level cell of Figure 8 (800)) can be used when stored in an exemplary machine readable instructions (900). is shown that. Also in connection with 10 as the, exemplary machine readable instructions of Figure 9 (900) a plurality of storage States checkpoint a multi-level cell to accommodate additional instructions can be supplemented. The block method exemplary of Figure 9. starting at 905. In shown, block 905 before work mode operation are generated during operations work mode the one or more task state transitions (for example, also 4, also 5 and/or of Figure 8 task status transitions (450, 455, 550, 555 and/or 830) at least one) is carried out is. During operations work mode, memory controller (305) of Figure 5 and/or 4 door has checkpoint bit b0 (410) of Figure 8 and/or checkpoint bit groups b0 b1 (810) prior transition job data is the same as respectively for uniform expression value (for example, checkpoint bit (are) and/or checkpoint bit groups (are) is less than 4 micrometers) multi-level cell (400, 500 and/or 800) different a to transition between States. Now, for example, in particular a plant processing waste fractions of Figure 9 shown the device by switching the, checkpoint processor (310) the check and decides the should be point is created (block 905). In shown, the received checkpoint in response to the request generated checkpoint. In some instances, checkpoint processor (310) with the recording and/or reading checkpoint from an application requesting receiving a request to create a.. Further or alternatively, any other checkpoint also results of recording a period and/or non-periodic method can be is used. For example, checkpoint processor (310) has after every reading and/or writing operations which can produce check point, checkpoint processor (310) generates a time integrated circuits are included in (for example, 1 ingredient, 15 ingredient, a time, and the like) can be produced check point. Checkpoint processor (310) is checked if transistors generating point, checkpoint wherein went back to 905 block control processor (310) the check point is created and to determine a care-of address to continue to. Checkpoint processor (310) if must generate point is checked (block 905), memory reader (320) has a multi-level cell working position (for example, also 4 and/or of Figure 5 work bit b1 (405), of Figure 8 work bit groups b3 b2 (805) such as) encrypt data to be stored on the 100 reads (block 910). Memory recorder (330) has a multi-level cell or not the data read from working position for checking point positioning (for example, also of Figure 5 and/or 4 bit checkpoint b0 (410), of Figure 8 checkpoint bit groups b1 b0 (810)), and writes the data in a (block 915). Checkpoint processor (310) additional be pointing check to determine whether the multi-level cells are (block 920). Additional multi-level cells are check pointing, and the postfiltering must be surface, control reverts to block 910 wherein additional multi-level cells are check is pointed. Check pointing be further interprets the absence of multi-level cells are, memory controller (305) to request the check point should be continue to monitor and decides the (block 935). Memory controller (305) to the checkpoint is monitoring if the called party determines that the should is continued (block 935), control block 905 said substrate in the areas in which returned to its checkpoint processor (310) the other, the hand of the check-points are, should be generated with. that determines when a. Otherwise, method are terminated exemplary of Figure 10. Figure 10 shows a exemplary checkpoint the memory controller to perform an operation that may be executed exemplary machine readable instructions (1000) is indicating the flow also of Figure 3. Shown of Figure 10 a checkpoint States are multi-level cell (for example, of Figure 6 multi-level cell (600), multi-level cell of Figure 7 (700) such as) can be used when stored in an exemplary machine readable instructions (1000). is shown that. Exemplary of Figure 10. starting at 1005 block procedure. In shown, block 1005 before, work mode operation are generated during operations work mode the one or more task state transitions (for example, also 6 and/or of Figure 7 task status transitions (730 and/or 630) at least one) is carried out is. During operations work mode, memory controller (305) door has checkpoint bits of Figure 7 and/or 6 b0 (615), b1 (610), b0 (720), b1 (715) and/or b2 (710) prior transition job data is of an equivalent value respectively for uniform expression multi-level cell (600 and/or 700) different a to transition between States. Now, for example, in particular a plant processing waste fractions of Figure 10 shown the device by switching the, checkpoint processor (310) the check and decides the should be point is created (block 1005). In shown, a received checkpoint in response to the request generated checkpoint. In some instances, checkpoint processor (310) the reading from and/or writing to checkpoint from an application requesting receiving a request to create a.. Further or alternatively, any other checkpoint also results of recording a period and/or non-periodic method can be is used. For example, checkpoint processor (310) has after every reading and/or writing operations which can produce check point, checkpoint processor (310) generates a time integrated circuits are included in (for example, 1 ingredient, 15 ingredient, a time, and the like) can be produced check point. Checkpoint processor (310) is checked if transistors generating point (block 1005), control said substrate in the areas in which returned to its checkpoint processor 1005 block (310) the check point is created and to determine a care-of address to continue to. Checkpoint processor (310) when it generating point is checked (block 1005), memory reader (320) check point positioning the number 1 (for example, checkpoint bit b1 (610), checkpoint bit b2 (710) such as) stored in a checkpoint for reading data a number 1 (block 1010). Number 1 checkpoint data after memory recorder (330) by number 2 check point positioning multi-cell (for example, checkpoint bit b0 (615), checkpoint bit b1 (715) such as) are stored in (block 1015). Memory reader (320) to working position (for example, work bit b2 (605), work bit b3 (705) such as) from 100 reads job data. Memory recorder (330) number 1 check point positioning a working data (for example, checkpoint bit b1 (610), checkpoint bit b2 (710) such as), and writes the data in a (block 1025). Checkpoint processor (310) the check pointing be additional and decides the multi-level cells are whether (block 1030). Additional multi-level cells are if, and the postfiltering must be pointing check, control block 1010 additional wherein went back to multi-level cells are check is pointed. Check if no cells are multi-level additional pointing it will do , memory controller (305) to the check point request to be is continued monitoring and decides the (block 1035). Memory controller (305) is checked point to request monitoring if the called party determines that the should is continued (block 1035), control block 1005 returned to its checkpoint said substrate in the areas in which, should be generated with check-points are processor that determines when a.. Otherwise, method are terminated exemplary of Figure 10. Figure 11 shows a exemplary memory controller (305) implementing of the thin film that may be executed to perform encoding exemplary machine readable instructions (1100) is indicating the flow also of Figure 3. Exemplary reader memory procedure of Figure 11 (320) of the multi-level cell (for example, of Figure 5 multi-level cell (500), of Figure 6 multi-level cell (600), of Figure 7 multi-level cell (700), of Figure 8 multi-level cells or the like) when reading out the burst cutting area resistance number 1 from starting at block 1105. (block 1105). Checkpoint processor (310) the number 1 number 1 resistance associated to multi-bit value (block 1110). In shown, number 1 multi-bit value (for example, of Figure 5 state S2 (530) is represented by a multi-bit value) of a multi-level cell. that represent plurality of layers. Memory reader (320) has a multi-level from the plurality of memory cells read resistance number 2 (block 1115). In shown, smaller than resistance than the resistance number 1 number 2. Checkpoint processor (310) the number 2 number 1 resistance multi-bit values larger than that of ZnO number 2 having binary representation multi-bit value (for example, of Figure 5 state S3 (535) is represented by a multi-bit value) (block 1120) associated to. In some instances, resistance force is greater than resistance number 1 number 2 number 1 number 1 binary representation resistance multi-bit value smaller than than binary representation. Figure 12 shows a also to implement memory control exemplary 9, exemplary of Figure 11 and 10 also machine readable instructions capable of executing of Figure 3 is an exemplary processor of the platform. Processor platform (1200) for example, server, personal computer, mobile phone (for example, cellular phone), individual digital subsidiary device (personal digital assistant; PDA), Internet device or any other type of computing device can be. Examples of a flash system (1200) a processor (1212) includes. For example, processor (1212) from a communication network and downloads one population or a desired any one or more microprocessors or controllers can be implemented by. Processor (1212) has a local memory (1213) (for example, cache) bus includes (1218) volatile memory through (1214) and a non-volatile memory (1216) including a main memory and a communication the a. Volatile memory (1214) the synchronous random access memory (Synchronous Dynamic Random Access Memory; SDRAM), dynamic random access memory (Dynamic Random Access Memory; DRAM), RAMBUS dynamic random access memory (RDRAM) and/or other types of random access by the memory device may be embodied in. Shown example non-volatile memory (1216) has multi-level cell (MLC) non-volatile random access memory (NVRAM) is implemented by. However, non-volatile memory (1216) a desired any other type of memory device (for example, flash memory, phase-change memory (phase-change memory; PCRAM), such as [...]) can be implemented by. Main memory (1214, 1216) access to memory controller (305) is controlled by. In shown, memory controller (305) has door 3 as described with respect to checkpoint processor (310), memory reader (320) and memory recorder (330) includes. Processor platform (1200) in addition the interface circuit (1220) includes. Interface circuit (1220) the Ethernet interface, universal Serial bus (USB) and/or PCI express interface and of any types of interfaces by the communication standard and may be embodied in. One or more input devices (1222) the interface circuit is (1220) is connected to. Input device (are) (1222) processor instructions data and user (1212) entering allows the. Input device, for instance, (are), keyboard, mouse, touch screen, track-pad, track ball, small point idle (isopoint) and/or speech recognition system can be implemented by. One or more output devices (1224) in addition the interface circuit (1220) is connected to. Output devices (1224) for example, which the display devices are (for example, liquid crystal display, cathode ray tube (CRT) display, printer and/or speakers) can be implemented by. Interface circuit (1220) graphic-scale and, hence, has typically includes protecting data of non-volatile. Interface circuit (1220) the in addition network (1226) (for example, Ethernet connection, digital subscriber line (digital subscriber line; DSL), telephone line, coaxial cable, cellular phone system or the like) out through the vent opening exchange data with to facilitate modem or a network interface card, such as. including the communication device. Processor platform (1200) the in addition for storing software and data's mass storage devices one or more (1228) includes. Such a mass storage devices (1228) of computer processing system employing floppy examples, hard drive disks, compact disc drive sets and a digital versatile disc (DVD) including drive. Also 9, 10 and/or also of Figure 11 coding instructions are (1232) a mass storage device (1228) to, volatile memory (1214) to, non-volatile memory (1216) to, local memory (1213) to, and/or CD or DVD removable can be stored on a storage medium. Said manufacturing method are from a disclosure, device and articles (MLC) multi-level due to non-volatile random access memory (NVRAM) using a local check pointing scalable such that notches at will. Advantageously, check pointing pointing system check of the existing method further time and energy than a less. And since the, check pointing quickly and, NVRAM which the atomic consistently data in. is enabled to manage. One particular exemplary manufacturing method are, are described herein, articles and device even [...] disclosure, the present patent ranged for inclusively is not limited to. Is in contrast to a spatially-, the present patent patent the present range of claim of manufacturing method are all corresponding entirely within, encompasses and articles device. Local checkpointing using a multi-level call is described herein. An example method includes storing a first datum in a first level of a multi-level cell. A second datum is stored in a second level of the multi-level cell, the second datum representing a checkpoint of the first datum. The first datum is copied from the first level to the second level of the multi-level cell to create the checkpoint. Multi-level (multi-level) (local checkpointing) pointing check the local cell as a method, multi-cell number 1 number 1 level data and stores, a checkpoint of data for representing said number 1 number 2 data (represent) said multi-cell number 2 level and stores, said checkpoint to generate said data said number 1 multi-cell copies the level said number 2 from the level said number 1 including step of local check pointing method. According to Claim 1, said number 2 from the level said number 1 data said number 1 the step copies the level data state from data number 1 number 2 including transitioning the mobile local check pointing method. According to Claim 2, said multi-cell said number 1 the data state number 1 physical attributes (physical property value) value is expressed by said number 2 number 2 cell multi-said data state is expressed by value physical attributes, said physical attributes value resistance, capacitance value and atomic spindle pointing check the local which is at least one method. According to Claim 3, said number 1 the data state for representing and value binary number 1 number 2 the data state said number 2 are represented according to the binary value, the binary values said number 1 said number 2 binary value greater than or equal one local check pointing method. According to Claim 4, said number 2 said number 1 physical attributes value less than or equal to the value physical attributes one local check pointing method. According to Claim 1, said number 1 in response to read request reading the data further including local check pointing method. According to Claim 6, said number 2 data is read in response to said read request does the local which is not check pointing method. According to Claim 1, said number 1 method pointing check the local which is a single bit data. Multi-level cells as device implementing a local checkpointing, said multi-cell number 1 of data stored in a level number 1 checkpoint for generating a checkpoint said processor-checkpoint said multi-cell number 2-and are stored at the level, multi-level said reading data stored in memory, data between readers and, multi-level said data a memory cell including a recorder local check pointing device. According to Claim 9, a read request in response to said memory reader said multi-cell reading data from the level number 1 local check pointing device. According to Claim 10, said memory reader in response to said read request said multi-cell not reading data from the level number 2 a local check pointing device. Machine readable as storage medium including instructions, when executed said a discard logic, shuttle type multifunction output relating, non-volatile random access memory and data number 1 (NVRAM) multi-cell saved data is stored in a level number 1, said number 1 number 2 checkpoint of data representing a multi-cell said data saved data is stored in a level number 2, said checkpoint to generate said data said number 1 multi-cell to said number 2 from the level said number 1 copies the level the machine which it does readable storage medium. According to Claim 12, said number 2 from the level said number 1 said number 1 data copies the level data state from the number 1 to number 2 data state transitioning the mobile including machine-readable storage medium. According to Claim 13, said multi-cell number 1 said number 1 the data state is expressed by value physical attributes, said number 1 the data state for representing and binary value as the number 1, number 2 cell multi-said said number 2 the data state is expressed by value physical attributes, said number 2 the data state for representing and value binary number 2, said physical attributes value resistance, capacitance value and atomic spindle the machine which is at least one readable storage medium. According to Claim 14, said number 2 the binary values said number 1 and greater than or equal binary values, said number 2 said number 1 physical attributes value less than or equal to the value physical attributes one machine readable storage medium.