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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 9015. Отображено 100.
05-01-2012 дата публикации

Single transistor memory cell

Номер: US20120002467A1
Принадлежит: Micron Technology Inc

A semiconductor device along with circuits including same and methods of operating same are disclosed. In one particular embodiment, the device may comprise a memory cell including a transistor. The transistor may comprise a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device may be refreshed during hold operations.

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05-01-2012 дата публикации

Circuit and method for controlling standby leakage current in random access memory devices

Номер: US20120002497A1
Автор: Chung Zen Chen

A method for controlling standby current coming from bit line leakage in random access memory devices comprises the steps of: continuously deactivating a pre-charge equalization circuit providing a pre-charge voltage to a pair of complementary bit lines of a memory cell if the memory cell is in a self-refresh mode, a standby mode or an active mode; temporarily activating the pre-charge equalization circuit before the memory cell is refreshed if the memory cell is in a self-refresh mode or a standby mode; and temporarily activating the pre-charge equalization circuit before the memory cell is refreshed or accessed if the memory cell is in an active mode.

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09-02-2012 дата публикации

Apparatus and methods for optically-coupled memory systems

Номер: US20120036303A1
Принадлежит: Round Rock Research LLC

Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module substrate of the first memory module has an aperture formed therein, the aperture being operable to provide an optical path for optical signals between the controller and an optical transmitter/receiver unit of the second memory module.

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16-02-2012 дата публикации

Method for driving semiconductor memory device

Номер: US20120039126A1
Автор: Toshihiko Saito
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A method for driving a semiconductor memory device including a transistor with low leakage current between a source and a drain in an off state and capable of storing data for a long time is provided. In a matrix including a plurality of memory cells in each of which a drain of a write transistor, a gate of an element transistor, and one electrode of a capacitor are connected, a gate of the write transistor is connected to a write word line, and the other electrode of the capacitor is connected to a read word line. The amount of charge stored in the capacitor is checked by changing the potential of the read word line, and if the amount of charge has decreased beyond a predetermined amount, the memory cell is refreshed.

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15-03-2012 дата публикации

System and method of page buffer operation for memory devices

Номер: US20120066442A1
Принадлежит: Mosaid Technologies Inc

Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.

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22-03-2012 дата публикации

Different types of memory integrated in one chip by using a novel protocol

Номер: US20120072647A1
Принадлежит: Aplus Flash Technology Inc

A semiconductor chip contains four different memory types, EEPROM, NAND Flash, NOR Flash and SRAM, and a plurality of major serial/parallel interfaces such as I 2 C, SPI, SDI and SQI in one memory chip. The memory chip features write-while-write and read-while-write operations as well as read-while-transfer and write-while-transfer operations. The memory chip provides for eight pins of which two are for power and up to four pins have no connection for specific interfaces and uses a novel unified nonvolatile memory design that allow the integration together of the aforementioned memory types integrated together into the same semiconductor memory chip.

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03-05-2012 дата публикации

System and Method for Simulating an Aspect of a Memory Circuit

Номер: US20120109621A1
Принадлежит: Google LLC

A memory subsystem is provided including an interface circuit adapted for coupling with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. Such aspect includes a signal, a capacity, a timing, and/or a logical interface.

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14-06-2012 дата публикации

Embedded DRAM having Low Power Self-Correction Capability

Номер: US20120151299A1
Автор: Jungwon Suh
Принадлежит: Qualcomm Inc

Apparatuses and methods for low power combined self-refresh and self-correction of a Dynamic Random Access Memory (DRAM) array. During a self-refresh cycle, a first portion of a first row of the DRAM array is accessed and analyzed for one or more errors, wherein a bit width of the first portion is less than a bit width of the first row. If one or more errors are detected, the one or more errors are corrected to form a corrected first portion. The corrected first portion is selectively written back to the first row. If no errors are detected in the first portion, a write back of the first portion to the first row is prevented.

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12-07-2012 дата публикации

Refresh control circuit, memory apparatus and refresh control method using the same

Номер: US20120176853A1
Автор: Ju Young Seo, Sang Hui Kim
Принадлежит: Hynix Semiconductor Inc

A memory apparatus is configured to generate refresh addresses with different values in response to one refresh command and an address, and perform a plurality of refresh operations with time differences in response to the refresh addresses. Herein, the refresh operations are performed within a refresh row cycle time.

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02-08-2012 дата публикации

Circuits and methods for providing refresh addresses and alternate refresh addresses to be refreshed

Номер: US20120195149A1
Автор: Robert Tamlyn
Принадлежит: Micron Technology Inc

Circuits and refresh address circuits for providing a refresh address, and methods for refreshing memory cells. An example method includes refreshing a first plurality of memory cells and interrupting the refreshing of the first plurality of memory cells. A second plurality of memory cells is refreshed, at least one of the second plurality of memory cells the same as one of the first plurality of memory cells. Refreshing of the first plurality of memory cells is resumed following the refreshing of the second plurality of memory cells. An example refresh address circuit includes a refresh address counter configured to provide addresses to be refreshed and a refresh address interrupt circuit configured to interrupt the provision of addresses. An alternate refresh address circuit is configured to provide an alternate address and the refresh address counter resumes providing the addresses responsive to completing the refreshing of the alternate address.

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02-08-2012 дата публикации

Circuit

Номер: US20120198265A1
Автор: Thomas Hein
Принадлежит: Qimonda AG

An embodiment of a circuit comprises an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer.

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02-08-2012 дата публикации

System and Method for Facilitating Data Transfer Between a First Clock Domain and a Second Clock Domain

Номер: US20120198267A1
Принадлежит: Qualcomm Atheros Inc

System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

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20-09-2012 дата публикации

Method for compensating a timing signal, an integrated circuit and electronic device

Номер: US20120239960A1
Принадлежит: FREESCALE SEMICONDUCTOR INC

A method for compensating a timing signal with which an outputting of data states of at least one data signal is synchronised. The method comprises receiving a current set of data states and a next set of data states, identifying state transitions between the current set of data states and the next set of data states, determining an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, and applying the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states.

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27-09-2012 дата публикации

Neighborhood operations for parallel processing

Номер: US20120246380A1
Принадлежит: Individual

A memory device includes a plurality of storage units in which to store data of a bank, wherein the data has a logical order prior to storage and a physical order different than the logical order within the plurality of storage units and a within-device reordering unit to reorder the data of a bank into the logical order prior to performing on-chip processing. In another embodiment, the memory device includes an external device interface connectable to an external device communicating with the memory device, an internal processing element to process data stored on the device and multiple banks of storage. Each bank includes a plurality of storage units and each storage unit has two ports, an external port connectable to the external device interface and an internal port connected to the internal processing element.

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29-11-2012 дата публикации

Memory system and refresh control method thereof

Номер: US20120300569A1
Автор: Geun Hee Cho
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory system and a refresh control method thereof are provided. The memory system includes a semiconductor memory device including a plurality of memory cells and a memory controller configured to generate a special command for searching for refresh information stored in the semiconductor memory device and to control a refresh operation of the semiconductor memory device. The semiconductor memory device is configured to output the refresh information to the memory controller in response to the special command generated by the memory controller.

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03-01-2013 дата публикации

Digit line comparison circuits

Номер: US20130003467A1
Автор: Dean A. Klein
Принадлежит: Micron Technology Inc

A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.

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03-01-2013 дата публикации

Mechanism for facilitating fine-grained self-refresh control for dynamic memory devices

Номер: US20130007357A1
Автор: Alan Ruberg, Roger Isaac
Принадлежит: Silicon Image Inc

A mechanism for facilitating improved refresh schemes for memory devices is described. In one embodiment, an apparatus includes a memory device having refresh logic and memory cells, the memory cells including data cells and supplemental cells, the supplemental cells to be observed. The supplemental cells emulate a decay characteristic of the data cells performing regular refresh operations according to an existing refresh policy. The apparatus may further include the refresh logic to receive, from the supplemental cells, observation data relating to decaying of the supplemental cells, and correlate the observation data to data cell performance. The refresh logic to generate a policy recommendation based on the observation data collected by the supplemental cells.

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07-02-2013 дата публикации

Apparatus and method for refreshing dram

Номер: US20130033950A1
Автор: Nan-Hsien Yeh
Принадлежит: NOVATEK MICROELECTRONICS CORP

A refresh method for DRAM is provided, in which a memory cell array is arranged to have multiple storing pages. Each storing page has a counter value. The method includes detecting out a portion of the storing pages being no longer used, indicated as a “no-use portion”, and another portion of the storing pages being still in use, indicated as “in-use portion”. Then, only the in-use portion of the storing pages is performed with a refreshing operation.

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14-02-2013 дата публикации

Memory device for managing timing parameters

Номер: US20130039135A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of performing write operations in a memory device including a plurality of banks is performed. Each bank includes two or more sub-banks including at least a first sub-bank and a second sub-bank. The method comprises: performing a first row cycle for writing to a first word line of the first sub-bank, the first row cycle including a plurality of first sub-periods, each sub-period for performing a particular action; and performing a second row cycle for writing to a first word line of the second sub-bank, the second row cycle including a plurality of second sub-periods of the same type as the plurality of first sub-periods. The first row cycle overlaps with the second row cycle, and a first type sub-period of the first sub-periods overlaps with a second type sub-period of the second sub-periods, the first type and second type being different types.

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28-03-2013 дата публикации

Memory storage device, memory controller, and temperature management method

Номер: US20130080680A1
Автор: Chien-Hua Chu
Принадлежит: Phison Electronics Corp

A temperature management method suitable for a memory storage device having a rewritable non-volatile memory module and a memory controller used for controlling the rewritable non-volatile memory module are provided. The temperature management method includes detecting and determining whether the hot-spot temperature of the memory storage device is higher than a predetermined temperature; and when affirmative, making the memory controller execute a cooling process, so as to reduce the hot-spot temperature of the memory storage device. Accordingly, the problem of heat buildup of the (rewritable non-volatile) memory storage device can be mitigated, as well as the problems of data loss and device aging of the (rewritable non-volatile) memory storage device.

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18-04-2013 дата публикации

Memory system

Номер: US20130094316A1
Принадлежит: Hynix Semiconductor Inc

A memory system includes: a controller configured to provide a hidden auto refresh command; and a memory configured to perform a refresh operation in response to the hidden auto refresh command. The controller and the memory communicate with each other so that each refresh address of the controller and the memory has the same value as each other.

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23-05-2013 дата публикации

Method and apparatus for refresh management of memory modules

Номер: US20130132661A1
Принадлежит: Google LLC, MetaRAM Inc

One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices

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04-07-2013 дата публикации

Semiconductor memory device storing memory characteristic information, memory module and memory system having the same, and operating method thereof

Номер: US20130170274A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor memory device includes a cell array including a plurality of regions accessed by first addresses, where the plurality of regions including at least two groups of regions having respectively different memory characteristics. The device further includes a nonvolatile array for nonvolatile storage of group information indicative of which of the least two groups each of the plurality of regions belongs.

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18-07-2013 дата публикации

Memory system temperature calibration

Номер: US20130182507A1
Принадлежит: Sandisk IL Ltd

A nonvolatile memory system includes a memory controller chip with at least one temperature sensor that is individually calibrated, at a single temperature, after the nonvolatile memory system is assembled, so that the calibration data is stored outside the memory controller chip, in a nonvolatile memory chip, thus obviating the need for components to store calibration data in the memory controller chip.

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08-08-2013 дата публикации

Refresh circuit of a semiconductor memory device and refresh control method of the semiconductor memory device

Номер: US20130201777A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A refresh circuit and a semiconductor memory device including the refresh circuit are disclosed. The refresh circuit includes a mode register, a refresh controller and a multiplexer circuit. The mode register generates a mode register signal having information relating to a memory bank on which a refresh operation is to be performed. The refresh controller generates a self-refresh active command and a self-refresh address based on a self-refresh command and an oscillation signal. The multiplexer circuit may include a plurality of multiplexers. Each of the multiplexers selects one of an active command and the self-refresh active command in response to bits of the mode register signal. Each of the multiplexers generates a row active signal based on the selected command, and selects one of an external address and the self-refresh address to generate a row address.

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29-08-2013 дата публикации

Semiconductor system and device, and method for controlling refresh operation of stacked chips

Номер: US20130223169A1
Автор: Byoung-Kwon Park
Принадлежит: SK hynix Inc

A system for controlling a refresh operation of a plurality of stacked semiconductor chips includes a first semiconductor configured to output a refresh signal for performing a refresh operation, and a semiconductor chip discrimination signal, and a plurality of second semiconductor chips configured to perform a refresh operation at different timings in response to the refresh signal, and the semiconductor chip discrimination signal.

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05-09-2013 дата публикации

Line memory device and image sensor including the same

Номер: US20130228672A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A line memory device includes a plurality of memory cells, a data line pair, a sense amplifier and an output unit. The plurality of memory cells are disposed adjacent to each other in a line. The data line pair is coupled to the memory cells to sequentially transfer memory data bits stored in the memory cells to the sense amplifier. The sense amplifier is configured to amplify the memory data bits that are sequentially transferred through the data line pair by corresponding delay times which are different from each other. The output unit samples an output of the sense amplifier to sequentially output retimed data bits of the memory data bits in response to a read clock signal. The read clock signal has a cyclic period which is less than a maximum delay time among the delay times.

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26-09-2013 дата публикации

Refreshing data of memory cells with electrically floating body transistors

Номер: US20130250674A1
Принадлежит: Micron Technology Inc

A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.

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26-09-2013 дата публикации

Memory and method of refreshing a memory

Номер: US20130250711A1
Автор: Chun Shiah, Sen-Fu Hong
Принадлежит: Etron Technology Inc

A memory includes a determination circuit, a plurality of refresh counters, and a plurality of banks. The determination circuit receives a refresh command. The plurality of refresh counters are coupled to the determination circuit. Each refresh counter of the plurality of refresh counters corresponds to one bank of the plurality of banks. The determination circuit detects whether a first bank of the plurality of banks is enabled or a number counted by a first refresh counter of the plurality of refresh counters corresponding to the first bank is equal to a predetermined value. Then, the determination circuit optionally refreshes one bank of the plurality of banks according to a detection result. Thus, the memory still refreshes an idle bank according to a refresh command even if the plurality of banks are not all idle.

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31-10-2013 дата публикации

SEMICONDUCTOR MEMORY

Номер: US20130286752A1
Принадлежит:

A semiconductor memory according to one embodiment includes: a memory cell array including a plurality of memory cells storing data, a first buffer circuit for inputting/outputting data to and from the first memory cell array, a data transfer circuit connected with the first buffer circuit via the first data bus and configured to control data transfer, and a control circuit configured to control a first mode and a second mode. The data transfer circuit performs control such that a bus width of the first data bus differs between the first mode and the second mode. 1. A semiconductor memory , comprising:a first memory cell array including a plurality of memory cells configured to store data;a first buffer circuit for inputting/outputting data to and from the first memory cell array;a data transfer circuit connected with the first buffer circuit via a first data bus and configured to control data transfer based on a first mode for transferring data with a first bit width and a second mode for transferring data with a second bit width different from the first bit width; andan ECC circuit connected with the first data bus via the data transfer circuit and configured to perform ECC processing on data with the second bit width, whereinthe first buffer circuit includes a plurality of pipe circuits each configured to input and output data with the first bit width, and a first data storage unit connected with the first data bus and having a plurality of first latch circuits configured to respectively stored a plurality of data with the first bit width transferred from the pipe circuits, and a selection circuit configured to connect one of the plurality of first latch circuits with a second data bus based on a selection signal, and', 'a second data storage unit connected between the first data bus and the ECC circuit and configured to store the data with the second bit width., 'the data transfer circuit includes'}2. The semiconductor memory according to claim 1 , wherein the ...

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07-11-2013 дата публикации

MEMORY DEVICE FOR PERFORMING MULTI-CORE ACCESS TO BANK GROUPS

Номер: US20130294174A1
Автор: OH TAE YOUNG, SONG HO SUNG
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A memory device has a burst length “b”, performs “k” core accesses per command, and receives a command, where “b” is an integer of at least 2 and “k” is an integer of at least 2 and at most “b”. The memory device includes a memory cell array comprising a plurality of bank groups, a plurality of bank group control units respectively corresponding to the plurality of bank groups, each of the bank group control units configured to generate a multiplexer control signal for selecting part of data read from a corresponding bank group, and a multiplexer configured to sequentially output data read from the plurality of bank groups according to the multiplexer control signal output from the plurality of bank group control units. Data items comprised in output data of the multiplexer have a same time space. 1. A memory device which has a burst length “b” , performs “k” core accesses per command , and receives a command , where “b” is an integer of at least 2 and “k” is an integer of at least 2 and at most “b” , the memory device comprising:a memory cell array comprising a plurality of bank groups;a plurality of bank group control units respectively corresponding to the plurality of bank groups, each of the bank group control units configured to generate a multiplexer control signal for selecting part of data read from a corresponding bank group; anda multiplexer configured to sequentially output data read from the plurality of bank groups according to the multiplexer control signal output from the plurality of bank group control units,wherein data items comprised in output data of the multiplexer have a same time space.2. The memory device of claim 1 , wherein the multiplexer control signal selects a part where data read at a first access among read data is combined with data read at a second access among the read data.3. The memory device of claim 1 , further comprising a third latch configured to output delayed data claim 1 , which results from delaying data read at a first ...

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28-11-2013 дата публикации

Period signal generation circuit

Номер: US20130315009A1
Автор: Dong Kyun Kim
Принадлежит: SK hynix Inc

A period signal generation circuit includes a first discharger configured to discharge first current from a control node which is driven in response to a first reference voltage, and a second discharger configured to discharge second current from the control node. The total current of the first and second currents is substantially constant when an internal temperature of the discharge controller is below a predetermined temperature, and the total current of the first and second currents varies as the internal temperature increases over the predetermined temperature.

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28-11-2013 дата публикации

Memory device

Номер: US20130315013A1
Автор: Bo-Kyeom Kim
Принадлежит: Individual

A memory device includes a first main page buffer array configured to access data of a first main memory array; a second main page buffer array configured to access data of a second main memory array; a redundancy page buffer array configured to access data of a redundancy memory array replacing the first and second main memory array; a first redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside of the memory device through a first redundancy bus, when a first column address indicates one or more defective columns of the first main memory array; and a second redundancy transfer unit configured to transfer data between the redundancy page buffer array and the outside through a second redundancy bus, when a second column address indicates one or more defective columns of the second main memory array.

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19-12-2013 дата публикации

MULTI-LEVEL MEMORY WITH DIRECT ACCESS

Номер: US20130339572A1
Принадлежит:

Embodiments of a method, device, and system for implementing multi-level memory with direct access are disclosed. In one embodiment, the method includes designating an amount of a non-volatile random access memory (NVRAM) in a computer system to be utilized as a memory alternative for a dynamic random access memory (DRAM). The method continues by designating a second amount of the NVRAM to be utilized as a storage alternative for a mass storage device. Then the method re-designates at least a first portion of the first amount of NVRAM from the memory alternative designation to the storage alternative designation during operation of the computer system. Finally, the method re-designates at least a first portion of the second amount of NVRAM from the storage alternative designation to the memory alternative designation during operation of the computer system. 1. A method , comprising:designating a first amount of a non-volatile random access memory (NVRAM) in a computer system to be utilized as a memory alternative for a dynamic random access memory (DRAM);designating a second amount of the NVRAM to be utilized as a storage alternative for a mass storage device;during operation of the computer system, re-designating at least a first portion of the first amount of NVRAM from the memory alternative designation to the storage alternative designation; andduring operation of the computer system, re-designating at least a first portion of the second amount of NVRAM from the storage alternative designation to the memory alternative designation.2. The method of claim 1 , further comprising:cycling through the entire first amount of NVRAM over a first amount of time to be redesignated from the memory alternative designation to the storage alternative designation, wherein the cycling comprises re-designating each of a plurality of portions that make up the entire first amount of NVRAM at each of a plurality of segments of time the sum of the plurality of segments comprising the ...

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02-01-2014 дата публикации

Mechanism for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems

Номер: US20140006702A1
Принадлежит: Intel Corp

A mechanism is described for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems according to one embodiment of the invention. A method of embodiments of the invention includes monitoring movements of a valid data eye associated with a memory device of a plurality of memory devices of a memory system at a computing system. The monitoring may include initiating write commands during one or more refresh periods associated with the valid data eye. The method may include determining drifting in the movement of the data eye, and correcting the drifting based on adjusting one or more existing phase interpolator values associated with the movements of the data eye.

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16-01-2014 дата публикации

Reducing Memory Refresh Exit Time

Номер: US20140016423A1
Принадлежит: RAMBUS INC

Components of a memory system, such as a memory controller and a memory device, that reduce delay in exiting self-refresh mode by controlling the refresh timing of the memory device. The memory device includes a memory core. An interface circuit of the memory device receives an external refresh signal indicating an intermittent refresh event. A refresh circuit of the memory device generates an internal refresh signal indicating an internal refresh event of the memory device. A refresh control circuit of the memory device performs a refresh operation on a portion of the memory core responsive to the internal refresh event, at a time relative to the intermittent refresh event indicated by the external refresh signal.

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23-01-2014 дата публикации

Method of controlling a refresh operation of psram and related device

Номер: US20140022858A1
Автор: Ho-Yin Chen, Shi-Huei Liu
Принадлежит: Individual

A plurality of refresh requests are generated at a predetermined period shorter than the longest time during which a PSRAM is able to retain a data without being refreshed. For two consecutive first and second refresh requests, the second refresh request is ignored if the interval between the first and the second refresh requests is not larger than a predetermined duration. The first refresh request is delayed if the first refresh request conflicts with an external command of the PSRAM.

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23-01-2014 дата публикации

Transactional Memory that Performs a Statistics Add-and-Update Operation

Номер: US20140025884A1
Принадлежит: Netronome Systems Inc

A transactional memory (TM) of an island-based network flow processor (IB-NFP) integrated circuit receives a Stats Add-and-Update (AU) command across a command mesh of a Command/Push/Pull (CPP) data bus from a processor. A memory unit of the TM stores a plurality of first values in a corresponding set of memory locations. A hardware engine of the TM receives the AU, performs a pull across other meshes of the CPP bus thereby obtaining a set of addresses, uses the pulled addresses to read the first values out of the memory unit, adds the same second value to each of the first values thereby generating a corresponding set of updated first values, and causes the set of updated first values to be written back into the plurality of memory locations. Even though multiple count values are updated, there is only one bus transaction value sent across the CPP bus command mesh.

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13-02-2014 дата публикации

Apparatus and method for hidden-refresh modification

Номер: US20140043919A1
Принадлежит: Micron Technology Inc

A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.

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13-02-2014 дата публикации

Method for optimizing refresh rate for dram

Номер: US20140043927A1
Принадлежит: International Business Machines Corp

A method for determining an optimized refresh rate involves testing a refresh rate on rows of cells, determining an error rate of the rows, evaluating the error rate of the rows; and repeating these steps for a decreased refresh rate until the error rate is greater than a constraint, at which point a slow refresh rate is set.

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27-02-2014 дата публикации

Row hammer refresh command

Номер: US20140059287A1
Принадлежит: Intel Corp

A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

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06-03-2014 дата публикации

MULTI-CHIP SEMICONDUCTOR APPARATUS

Номер: US20140063990A1
Автор: KU Young Jun, YUN Tae Sik
Принадлежит: SK HYNIX INC.

A multi-chip semiconductor apparatus includes a plurality of semiconductor chips which are electrically connected through a plurality of through-chip vias (TSVs) and stacked, wherein each of the semiconductor chips includes: a first data input/output line configured to transmit data for a first memory bank; a second data input/output line configured to transmit data for a second memory bank; and a data transmitting/receiving (TX/RX) unit configured to electrically connect any one of the first and second data input/output lines to a first TSV in response to selected memory bank information, during read and write operations for the corresponding semiconductor chip. 1. A multi-chip semiconductor apparatus comprising a plurality of semiconductor chips which are electrically connected through a plurality of through-chip vias (TSVs) and stacked ,wherein each of the semiconductor chips comprises:a first data input/output line configured to transmit data for a first memory bank;a second data input/output line configured to transmit data for a second memory bank; anda data transmitting/receiving (TX/RX) unit configured to electrically connect any one of the first and second data input/output lines to a first TSV in response to selected memory bank information, during read and write operations for the corresponding semiconductor chip.2. The multi-chip semiconductor apparatus according to claim 1 , wherein the data TX/RX unit transmits read data transmitted from any one of the first and second data input/output lines to the first TSV in response to the selected memory bank information claim 1 , during the read operation for the corresponding semiconductor chip.3. The multi-chip semiconductor apparatus according to claim 1 , wherein the data TX/RX unit receives write data transmitted from the first TSV through any one of the first and second data input/output lines in response to the selected memory bank information claim 1 , during the write operation for the corresponding ...

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06-03-2014 дата публикации

SELECTIVE REFRESH WITH SOFTWARE COMPONENTS

Номер: US20140068172A1
Принадлежит: RAMBUS INC.

A method of refreshing a memory is disclosed. The method includes accessing from active memory an active memory map. The active memory map is generated by software and identifies addresses corresponding to the active memory and associated refresh criteria for the addresses. The refresh criteria are evaluated for a portion of the active memory, and an operation initiated to refresh a portion of the active memory is based on the refresh criteria. 1. A method of refreshing a memory , the method comprising:accessing from active memory an active memory map, the active memory map generated by software and identifying addresses corresponding to the active memory and associated refresh criteria for the addresses;evaluating the refresh criteria for a portion of the active memory; andinitiating an operation to refresh a portion of the active memory based on the refresh criteria.2. The method of wherein the software comprises operating system software.3. The method of wherein the operation comprises a software instruction claim 1 , and the method further comprises:decoding the software instruction to generate one or more memory refresh commands; andrefreshing the portion of the active memory in response to the one or more memory refresh commands.4. The method of wherein accessing the active memory map comprises accessing an allocated page table.5. The method of wherein accessing the allocated page table comprises:tabulating plural active memory page addresses; andtracking the refresh status for each active memory page address.6. The method of wherein tracking the refresh status comprises:sorting the active memory page addresses by the refresh criteria.7. The method of and further comprising: loading information representing the active memory map into an addressable storage element of a memory device; and', 'activating hardware in the memory device to selectively self-refresh the active memory of the memory device based on the loaded information., 'selectively initiating a self ...

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03-04-2014 дата публикации

INTERMEDIATE CIRCUIT AND METHOD FOR DRAM

Номер: US20140092699A1

An intermediate circuit and method for hiding refresh confliction. The intermediate circuit includes: a first control circuit configured to generate a Command Output Enable signal CON, a Data Read Enable signal DRN and a Refresh Enable signal REFN based on the second clock, wherein a ration of duration the signal CON is in a first state to duration in a second state equals to CLK/(CLK-CLK), the signal REFN has a state that is reverse to that of the signal CON and is used to refresh the DRAM; a command buffer configured to store the access commands received from the user interface and output the stored access commands to the DRAM in response to the first state of the signal CON; a data buffer configured to read data from the DRAM in response to the first state of the signal CON and output the read data. 1. An intermediate circuit for DRAM , the intermediate circuit coupled between a user interface and the DRAM , the user interface transmitting access commands at a first clock , the DRAM operating at a second clock and being refreshed via a refresh controller , wherein clock cycle of the first clock is greater than clock cycle of the second clock , the intermediate circuit comprising:a first control circuit configured to generate a Command Output Enable signal and a Refresh Enable signal based on the second clock, wherein the Command Output Enable signal has a first state and a second state, wherein a ratio of duration of the first state to that of the second state is the second clock cycle divided by the difference between the first clock cycle and the second clock cycle, and wherein the Refresh Enable signal has a state that is reverse to that of the Command Output Enable signal and is applied to the refresh controller;a command buffer configured to i) store the access commands received from the user interface and ii) output the stored access commands to the DRAM when the Command Output Enable signal is in the first state; anda data buffer configured to read data ...

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03-04-2014 дата публикации

SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF

Номер: US20140095824A1
Принадлежит:

A semiconductor device comprises: a read queue configured to store one or more read requests to a semiconductor memory device; a write queue configured to store one or more write requests to the semiconductor memory device; and a dispatch block configured to determine a scheduling order of the one or more read requests and the one or more write requests and switch to the read queue or to the write queue if a request exists in a Row Hit state in the read queue or in the write queue. 1. A method of a semiconductor device comprising:if one or more read requests in a Row Hit state exist in a read queue, processing the one or more read requests;if no read request in the Row Hit state exists in the read queue, switching to a write queue;if one or more write requests in the Row Hit state exist in the write queue, processing the one or more write requests; andif no write request in the Row Hit state exists in the write queue, switching to the read queue.2. The method of a semiconductor device of claim 1 , further comprising:if a length of the write queue exceeds a first threshold value, processing one or more write requests in the write queue.3. The method of a semiconductor device of claim 1 , further comprising:if a length of the write queue is zero, processing one or more read requests in the read queue.4. The method of a semiconductor device of claim 1 , further comprising:if a length of the read queue is zero, processing one or more write requests in the write queue.5. The method of a semiconductor device of claim 1 , further comprising:if a length of the write queue is less than a second threshold value, processing one or more read requests in the read queue.6. A semiconductor device comprising:a read queue configured to store one or more read requests to a semiconductor memory device;a write queue configured to store one or more write requests to the semiconductor memory device; anda dispatch block configured to determine a scheduling order of the one or more read ...

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03-04-2014 дата публикации

Semiconductor device and operating method thereof

Номер: US20140095825A1
Принадлежит: SK hynix Inc

An operating method of a semiconductor device may comprise determining whether a read request is pending, setting a delay interval in accordance with a density of requests if there is no read request pending; and processing a write request after the delay interval.

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01-01-2015 дата публикации

SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF

Номер: US20150003180A1
Автор: Kim Chang-Hyun
Принадлежит: SK HYNIX INC.

A semiconductor device includes: a plurality of memory cell blocks, a counting unit suitable for counting the number of active operations on each of the memory cell blocks, based on an active command and a row address, and a refresh control unit suitable for determining a target memory cell block among the memory cell blocks and controlling an additional refresh operation for the target memory cell block to be performed based on the counting result. 1. A semiconductor device comprising:a plurality of memory cell blocks;a counting unit suitable for counting the number of active operations on each of the memory cell blocks, based on an active command and a row address; anda refresh control unit suitable for determining a target memory cell block among the memory cell blocks and controlling an additional refresh operation for the target memory cell block to be performed based on the counting result.2. The semiconductor device of claim 1 , wherein the refresh control unit controls a normal refresh operation to be sequentially performed on the memory cell blocks during a normal refresh mode claim 1 , and controls the additional refresh operation to be performed on the target memory cell block.3. The semiconductor device of claim 2 , wherein the refresh control unit controls the normal refresh operation and the additional refresh operation to be sequentially performed in a unit of row claim 2 , when a refresh command is inputted.4. A semiconductor device comprising:a plurality of mats;a counting unit suitable for counting the number of active operations on each of the mats, based on an active command and a row address;a target mat determination unit suitable for generating a mat information signal corresponding to a target mat among the mats and an enable signal for enabling an additional refresh operation based on the counting result; anda refresh operation unit suitable for generating a row active signal and a refresh address for controlling a normal refresh operation ...

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07-01-2016 дата публикации

DATA STORAGE DEVICE

Номер: US20160005444A1
Принадлежит:

A data storage device includes a first memory device suitable for performing an internal operation in response to a first internal operation command; and a state checking block suitable for performing a state read operation by transmitting a state read command one or more times to the first memory device during one of an initial mode and a repeat mode which is set based on a type of the internal operation. 1. A data storage device comprising:a first memory device suitable for performing an internal operation in response to a first internal operation command; anda state checking block suitable for performing a state read operation by transmitting a state read command one or more times to the first memory device during one of an initial mode and a repeat mode which is set based on a type of the internal operation.2. The data storage device according to claim 1 , wherein the state checking block sets an initial standby time during the initial mode based on an expected performance time of the internal operation claim 1 , and transmits an initial state read command to the first memory device when the initial standby time passes.3. The data storage device according to claim 2 ,wherein the first memory device outputs initial response data in response to the initial state read command, andwherein the state checking block determines whether the internal operation is completed based on the initial response data, and ends the state read operation or enters the repeat mode according to a determination result.4. The data storage device according to claim 3 , wherein the state checking block sets a repeat standby time during the repeat mode based on the expected performance time of the internal operation when it is determined that the internal operation is not completed claim 3 , and transmits a repeat state read command to the first memory device when the repeat standby time passes.5. The data storage device according to claim 4 ,wherein the first memory device outputs repeat ...

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07-01-2016 дата публикации

SEMICONDUCTOR MEMORY DEVICE FOR CONTROLLING HAVING DIFFERENT REFRESH OPERATION PERIODS FOR DIFFERENT SETS OF MEMORY CELLS

Номер: US20160005452A1
Принадлежит:

Provided is a semiconductor memory device for controlling a refresh operation of redundancy memory cells. The semiconductor memory device may include normal memory cells and redundancy memory cells that are used to repair normal memory cell(s) to which a defective cell is connected, and an error-correction code (ECC) memory cell row that stores parity bits for controlling the defective cell. Memory cells on the normal memory cell rows are refreshed during a first refresh cycle. Other memory cells on, such as redundancy memory cell rows, an edge memory cell row that is adjacent to the redundancy memory cell row(s) from among the normal memory cell rows, and/or the ECC memory cell row may be refreshed during a second refresh cycle that is different from the first refresh cycle. 1. A semiconductor memory device comprising:a memory cell array including a plurality of memory cells arranged in rows and columns, wherein the rows are divided into a first set of rows and a second set of rows, and wherein one or more rows of the first set of rows are configured to be replaced with one or more rows of the second set of rows; anda refresh address generator configured to generate first and second refresh addresses such that memory cells of the first set of rows are refreshed during a first refresh cycle in response to the first refresh addresses and memory cells of the second set of rows are refreshed during a second refresh cycle in response to the second refresh addresses,wherein a period of time of the second refresh cycle is different from a period of time of the first refresh cycle, andwherein the refresh address generator is configured to generate the first refresh addresses by a first counting operation and the second refresh addresses by a second counting operation.2. The semiconductor memory device of claim 1 , wherein a period of time of the second refresh cycle is shorter than a period of time of the first refresh cycle.3. The semiconductor memory device of claim 2 , ...

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13-01-2022 дата публикации

READING A MULTI-LEVEL MEMORY CELL

Номер: US20220013167A1
Принадлежит:

Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred. 1. A method , comprising:applying a first read voltage with a first polarity to a memory cell to determine a logic state stored by the memory cell configured to store three or more logic states;determining whether a first snapback event occurred after applying the first read voltage;applying a second read voltage with a second polarity different than the first polarity to the memory cell based at least in part on determining that the first snapback event failed to occur;determining whether a second snapback event occurred after applying the second read voltage; anddetermining the logic state stored by the memory cell from the three or more logic states based at least in part on determining whether the first snapback event or the second snapback event occurred.2. The method of claim 1 , further comprising:applying a third read voltage with the first polarity and a magnitude greater than a magnitude of the second read voltage to the memory cell based at least in part on determining that the second snapback event failed to occur; anddetermining whether a third snapback event occurred after applying the third read voltage, wherein determining the logic state stored by the memory cell is based at least in part on determining whether the third snapback event occurred.3. A method claim 1 , comprising:applying a ...

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07-01-2021 дата публикации

Apparatuses and methods for monitoring word line accesses

Номер: US20210005240A1
Принадлежит: Micron Technology Inc

An apparatus may include multiple memory devices. Each memory device may include multiple memory banks. Addresses of accessed word lines for a particular portion of memory and the number of times those word lines are accessed may be tracked by each memory device. When a memory device determines that an accessed word line is an aggressor word line, the memory device alerts other memory devices of the apparatus. The memory devices may then perform targeted refresh operations on victim word lines of the aggressor word line.

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07-01-2021 дата публикации

Periodic calibrations during memory device self refresh

Номер: US20210005245A1
Принадлежит: Intel Corp

A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.

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20-01-2022 дата публикации

HIGH SPEED SRAM USING ENHANCE WORDLINE/GLOBAL BUFFER DRIVE

Номер: US20220020405A1
Автор: ARYA Dipti, Kumar Ashish
Принадлежит: STMICROELECTRONICS INTERNATIONAL N.V.

A row decoder includes decoder logic generating an initial word line signal, and two inverters. The first inverter is formed by a first p-channel transistor having a source coupled to a supply voltage and a gate receiving the initial word line signal. The second inverter is formed by a first n-channel transistor having a drain coupled to a drain of the first p-channel transistor, a source coupled to a shared ground line, and a gate receiving the initial word line signal. An inverse word line signal is generated at the drain of the first n-channel transistor. A second inverter inverts the inverse word line signal to produce a word line signal. Negative bias generation circuitry generates a negative bias voltage on the shared ground line when the initial word line signal is logic high, and otherwise couples the shared ground line to ground. 1. Decoder circuitry for a memory , comprising: decoder logic configured to generate an initial word line signal;', a first p-channel transistor having a source coupled to a supply voltage, a drain, and a gate coupled to the decoder logic to receive the initial word line signal; and', 'a first n-channel transistor having a drain coupled to the drain of the first p-channel transistor, a source coupled to a shared ground line, and a gate coupled to the decoder logic to receive the initial word line signal;', 'wherein an inverse word line signal is generated at the drains of the first p-channel transistor and the first n-channel transistor;, 'a first inverter comprising, 'a second inverter configured to invert the inverse word line signal to produce a word line signal; and, 'a row decoder comprisingnegative bias generation circuitry configured to generate a negative bias voltage on the shared ground line when the initial word line signal is at a logic high, and to couple the shared ground line to ground when the initial word line signal is at a logic low.2. The decoder circuitry of claim 1 , wherein the negative bias generation ...

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20-01-2022 дата публикации

Write broadcast operations associated with a memory device

Номер: US20220020424A1
Принадлежит: Micron Technology Inc

Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable write broadcast operations. A write broadcast may occur from one or more signal development components or from one or more multiplexers to multiple locations of the memory array.

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12-01-2017 дата публикации

MEMORY INTERFACE CONFIGURABLE FOR ASYNCHRONOUS AND SYNCHRONOUS OPERATION AND FOR ACCESSING STORAGE FROM ANY CLOCK DOMAIN

Номер: US20170011786A1
Принадлежит:

A system comprising a memory controller coupled to a memory device is described. The memory device is coupled to, and is external to, the memory controller. The memory device includes a storage array having dual configurability to support both synchronous and asynchronous modes of operation. 1. A system comprising:a memory controller; anda memory device coupled to and external to the memory controller, the memory device comprising a storage array having dual configurability to support both synchronous and asynchronous modes of operation.2. The system of claim 1 , wherein the memory controller controls access to the storage array in a first mode of operation during a first time period and in a second mode of operation during a second time period.3. The system of claim 2 , wherein the first mode of operation is a synchronous mode and the second mode of operation is an asynchronous mode.4. The system of claim 1 , wherein the storage array is one of a Static Random Access Memory (SRAM) array claim 1 , an array of registers claim 1 , and an array of latches.5. The system of claim 1 , wherein the memory controller is one of a microprocessor claim 1 , a microcontroller claim 1 , and an application specific integrated circuit (ASIC). This application is a continuation of U.S. patent application Ser. No. 13/312,929, filed on Dec. 6, 2011, which is a continuation of U.S. patent application Ser. No. 11/954,622, filed on Dec. 12, 2007, which claims priority to U.S. Provisional Application No. 60/869,784, filed on Dec. 13, 2006, all of which are incorporated by reference herein in their entirety.1. Field of the InventionThis invention relates to electronic circuits and, more particularly, to a memory interface circuit, which can be configured for asynchronous and synchronous operation. In addition, the memory interface circuit can be configured for accessing a storage element using one of multiple clock signals available to the memory device.2. Description of the Related ArtThe ...

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11-01-2018 дата публикации

GRACEFUL SHUTDOWN WITH ASYNCHRONOUS DRAM REFRESH OF NON-VOLATILE DUAL IN-LINE MEMORY MODULE

Номер: US20180011714A1
Принадлежит: SUPER MICRO COMPUTER, INC.

A graceful shutdown of a computer system is initiated by sending a command to an asynchronous dynamic random access memory refresh (ADR) trigger device to assert an ADR trigger. Responsive to the command, the ADR trigger device asserts the ADR trigger to initiate an ADR of a non-volatile dual in-line memory module (NVDIMM) of the computer system. In response to the ADR trigger being asserted by the ADR trigger device, an ADR of the NVDIMM is performed before completing the graceful shutdown of the computer. 1. A method of performing a graceful shutdown of a computer system , the method comprising:enabling trapping of write operations to a power management control register;in response to receiving an instruction to perform a graceful shutdown of the computer system, writing to the power management control register to place the computer system in a soft off state;in response to the writing to the power management control register to place the computer system in the soft off state, entering, by a central processing unit (CPU) of the computer system, a system management mode and running a system management interrupt (SMI) handler;sending an original equipment manufacturer (OEM) command to assert an asynchronous dynamic random access memory refresh (ADR) trigger; andin response to receiving the OEM command, asserting the ADR trigger to perform the ADR before completing the graceful shutdown of the computer system,wherein the ADR transfers contents from a volatile memory of a non-volatile dual in-line memory module (NVDIMM) to a non-volatile memory of the NVDIMM.2. The method of claim 1 , wherein asserting the ADR trigger comprises:asserting a power button pin of a controller hub.3. The method of claim 2 , wherein the power button pin is asserted for 4 seconds or longer.4. The method of claim 1 , wherein a basic input output system (BIOS) of the computer system enables the trapping of write operations to the power management control register before the instruction to ...

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14-01-2016 дата публикации

CIRCUIT FOR MIXED MEMORY STORAGE AND POLYMORPHIC LOGIC COMPUTING

Номер: US20160012876A1
Принадлежит:

A circuit utilizing memcapacitive elements for mixed memory storage and polymorphic computing is introduced. The circuit includes a plurality of memory cells each selectively or fixedly connected to a word line, bit line and dual bit line. Each memory cell includes a memcapacitive element. Voltage pulse generators can selectively applying voltage pulses to the memory cells. A method for mixed memory storage and polymorphic computing in at least two memory cells is provided. Data is stored by selectively applying voltage pulses to an individual memory cell to set an internal charge level of the memcapacitive element. Logic functions are conducted by applying voltage pulses having independent amplitudes to at least two memory cells to achieve internal charges in the memcapacitive elements of the cells to store an output bit according to a logic map that depends upon applied independent voltage pulse amplitudes. 1. A circuit for mixed memory storage and polymorphic computing , comprising:a plurality of memory cells each selectively or fixedly connected to a word line, bit line and dual bit line, wherein each memory cell includes a memcapacitive element;voltage pulse generators for selectively applying voltage pulses the memory cells; andcontrol circuitry apply to control the voltage generators amplifiers to conduct logic operations using two or more of the memory cells.2. The circuit of claim 1 , further comprising sense amplifiers for refreshing reading contents of the memory cells.3. The circuit of claim 1 , wherein the memory cells are selectively connected via a switch.4. The circuit of claim 1 , wherein the memcapacitive element comprises a solid state element.5. The circuit of claim 2 , wherein the solid state element comprises a memcapactor have a plurality of metal layers separated by dielectric including a central low-K dielectric layer and outer high-K dielectric layers.6. The circuit of claim 1 , wherein each of the memory cells comprise a FET transistor ...

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14-01-2016 дата публикации

SEMICONDUCTOR MEMORY APPARATUS

Номер: US20160012877A1
Принадлежит:

A semiconductor memory apparatus may include a row address control block configured to output an address as a row address or output a counted signal as the row address in response to a refresh signal and the address, and generate an auto-precharge signal and a pre-bank active signal in response to the refresh signal and a bank active signal. The semiconductor memory apparatus may include a bank control block configured to generate the bank active signal in response to an active signal, a precharge signal, a bank address signal, the auto-precharge signal and the pre-bank active signal. 1. A semiconductor memory apparatus comprising:a row address control block configured to output an address as a row address or output a counted signal as the row address in response to a refresh signal and the address, and generate an auto-precharge signal and a pre-bank active signal in response to the refresh signal and a bank active signal; anda bank control block configured to generate the bank active signal in response to an active signal, a precharge signal, a bank address signal, the auto-precharge signal and the pre-bank active signal.2. The semiconductor memory apparatus according to claim 1 , wherein the row address control block outputs the address as the row address when the refresh signal is disabled claim 1 , and outputs the counted signal as the row address when the refresh signal is enabled.3. The semiconductor memory apparatus according to claim 2 , wherein the row address control block outputs a counted signal generated when the refresh signal is enabled claim 2 , stores the address at a time when the bank active signal is enabled and outputs the stored address as the row address in response to a first setting signal claim 2 , a second setting signal and the bank active signal.4. The semiconductor memory apparatus according to claim 2 , wherein the row address control block outputs the address as the row address in response to a first setting signal claim 2 , a second ...

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14-01-2021 дата публикации

POWER DOMAIN SWITCHES FOR SWITCHING POWER REDUCTION

Номер: US20210012827A1
Принадлежит:

Methods, systems, and devices for power domain switches for switching power reduction are described. A device, such as a memory device, may receive an indication (e.g., a command) for a power domain component of the device to transition between states. The device may float first and second gate drivers. A pass gate may be used to connect (e.g., short) the first switch to the second switch. The pass gate may be deactivated to isolate the gates. The first and second gate drivers may be enabled, and the first and second gate drivers drive the first and second switches to disconnect the power domain component from a power source to deactivate the power domain component, or connect to the power source to activate the power domain component. The energy to switch between active and inactive states may thereby be reduced. 1. A method , comprising:receiving, from a host device, an indication to transition one or more power domain components from a first power state to a second power state;determining, based at least in part on receiving the indication, to transition a power domain component from an active state to an inactive state, the power domain component supplied with power from a power source via a first switch and a second switch during the active state;floating, during the transition of the power domain component, a first gate driver for the first switch and a second gate driver for the second switch;activating, during the transition of the power domain component and based at least in part on the floating, a pass gate to short the first switch and the second switch;deactivating the pass gate; anddisconnecting the power domain component from the power source by driving, after deactivating the pass gate, the first switch using the first gate driver and the second switch using the second gate driver.2. The method of claim 1 , further comprising:supplying power from a power source to the power domain component during the active state via the first switch and the second ...

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14-01-2021 дата публикации

Storage device and method for operating storage device

Номер: US20210012830A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A storage device may include a monitoring module which monitors a characteristic degradation rate of a plurality of blocks included in a cell array of a nonvolatile memory; a group management module which designates the plurality of blocks as one or more groups, on the basis of a monitoring result of the monitoring module; a refresh period management module which determines refresh periods for each of the one or more groups; and a processor which performs refresh on the one or more groups in accordance with the determined refresh periods.

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14-01-2021 дата публикации

Memory device and memory system comprising the same

Номер: US20210012831A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory device includes a plurality of memory chips for writing and reading data in response to a control command and an address signal, and a control logic circuit for transferring the control command and the address signal to the plurality of the memory chips, and receiving a first command from a memory controller to perform a first operation, different from a refresh operation, on at least one of a plurality of the memory chips. The control logic circuit, in response to a refresh command, transmits the first command to at least one of a plurality of the memory chips and performs the first operation during a pre-determined refresh time interval without carrying out the refresh operation.

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09-01-2020 дата публикации

APPARATUSES AND METHODS FOR PROVIDING POWER FOR MEMORY REFRESH OPERATIONS

Номер: US20200013448A1
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatuses and methods for providing power for memory refresh operations are described. An example apparatus includes refresh circuits, a power amplifier, a power circuit, and a power control circuits. The refresh circuits are configured to refresh memory cells of a memory bank. The power amplifier is configured to provide power when activated to the refresh circuits. The power provided by the power amplifier has a first voltage. The power circuit is configured to receive a power supply voltage and to provide power when activated to the refresh circuits. The power provided by the power amplifier has a second voltage. The power control circuit is configured to compare the first voltage and the target voltage and to provide an activation signal to control activation of the power circuit having an active duration based at least in part on the comparison. 1. An apparatus , comprising:refresh circuits configured to refresh memory cells of a memory bank;a power amplifier configured to provide power when activated to the refresh circuits, the power provided by the power amplifier having a first voltage;a power circuit configured to receive a power supply voltage and further configured to provide power when activated to the refresh circuits, the power provided by the power circuit having a second voltage; anda power control circuit configured to receive a target voltage, the first voltage, and a refresh activation signal, the power control circuit configured to compare the first voltage and the target voltage and further configured to provide an activation signal to control activation of the power circuit having an active duration based at least in part on the comparison.2. The apparatus of claim 1 , wherein the power provided by the power amplifier is based on the power supply voltage.3. The apparatus of claim 1 , wherein the target voltage is equal to a target first voltage for the power amplifier.4. The apparatus of claim 1 , wherein the power circuit comprises:a p-type ...

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09-01-2020 дата публикации

NON-VOLATILE MEMORY DEVICE

Номер: US20200013787A1
Принадлежит:

A non-volatile memory device includes an upper semiconductor layer vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. 1. A non-volatile memory , comprising:an upper semiconductor layer vertically stacked on a lower semiconductor layer, wherein the upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region,the lower semiconductor layer includes a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group.2. The non-volatile memory of claim 1 , further comprising:a control logic that generates a connection control signal, wherein the bypass circuit selectively connects the first bit line with the second bit line in response to the connection control signal.3. The non-volatile memory of claim 1 , wherein the bypass circuit includes a transistor including a first source/drain region and a second source/drain region claim 1 , and a first contact plug extending from the first source/drain region through the separation region to connect the first bit line; and', 'a second contact plug extending from the second source/drain region through the separation region to connect the second bit line., 'the non-volatile memory device further comprises4. (canceled)5. The non-volatile memory of claim 1 , wherein a portion of the lower semiconductor layer underlying the first memory group includes a first portion of a first row decoder claim 1 , a second portion ...

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15-01-2015 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20150016201A1
Принадлежит: SK HYNIX INC.

A semiconductor device includes first and second bank groups coupled to first and second data lines which are electrically isolated from each other. The semiconductor device includes a register unit suitable for providing predetermined data to the second data line in a specific mode, a data transfer and output unit suitable for externally outputting the predetermined data loaded onto the second data line and simultaneously transferring the predetermined data to the first data line in the specific mode, and a data output unit suitable for externally outputting the predetermined data loaded onto the first data line in the specific mode. 1. A semiconductor device comprising first and second bank groups coupled to first and second data lines which are electrically isolated from each other , the semiconductor device comprising:a register unit suitable for providing predetermined data to the second data line in a specific mode;a data transfer and output unit suitable for externally outputting the predetermined data loaded onto the second data line and simultaneously transferring the predetermined data to the first data line in the specific mode; anda data output unit suitable for externally outputting the predetermined data loaded onto the first data line in the specific mode.2. The semiconductor device of claim 1 , whereinthe register unit is disposed in a second peripheral area closer to a second memory area in which the second bank group is disposed than to a first memory area in which the first bank group is disposed, andthe data transfer and output unit and the data output unit are disposed in a first peripheral area closer to the first memory area than to the second memory area.3. The semiconductor device of claim 1 , wherein the register unit comprises a multi-purpose register (MPR).4. The semiconductor device of claim 1 , whereinthe data output unit externally outputs first normal data of the first bank group loaded onto the first data line in a normal mode, ...

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15-01-2015 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME

Номер: US20150019832A1
Автор: OK Sung-Hwa
Принадлежит: SK HYNIX INC.

A semiconductor device includes a pipeline latch unit including a plurality of write pipelines, and suitable for latching data, and a control unit suitable for controlling at least one write pipeline of the write pipelines based on an idle signal. 1. A semiconductor device , comprising:a pipeline latch unit including a plurality of write pipelines, and suitable for latching data; anda control unit suitable for controlling at least one write pipeline of the write pipelines based on an idle signal'.2. The semiconductor device of claim wherein the control unit comprises:a pipeline control signal generation unit suitable for generating a pipeline control signal based on the idle signal and a reset signal;a pipeline selection signal generation unit suitable for generating the pipeline selection signals based on the pipeline control signal; anda pipeline input control signal output unit suitable for generating the pipeline input control signals based on the pipeline selection signals so that the at least one write pipeline is activated.3. The semiconductor device of claim 1 , wherein the idle signal is a signal indicating an idle period of the semiconductor device claim 1 , wherein the idle period denotes a period from an entry of a precharge operation accompanied with a write operation to a start time point of a next write operation.4. The semiconductor device of claim 2 , wherein the pipeline control signal generation unit comprises a pulse period control unit suitable for reducing a pulse width of a signal generated in a pulse form by delaying a rising edge of the signal.5. The semiconductor device of claim 2 , wherein the pipeline control signal generation unit comprises:a latch suitable for latching the idle signal;a pulse period control unit suitable for controlling a pulse width of the latched idle signal; anda signal generation unit suitable for generating the pipeline control signal based on the latched signal.6. The semiconductor device of claim 2 , wherein a ...

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19-01-2017 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND I/O CONTROL CIRCUIT THEREFOR

Номер: US20170018294A1
Автор: SONG Choung Ki
Принадлежит:

An I/O control circuit, includes a mode setting unit configured to generate a first mode signal, a second mode signal, a third mode signal, and a fourth mode signal in accordance with one of a plurality of I/O option modes, a first control signal generation unit configured to generate a first mode determination signal and a first control signal enable signal in response to the first I/O option signal and the first mode signal, and a second control signal generation unit configured to generate a second control signal enable signal, a third control signal enable signal, and a fourth control signal enable signal in response to a second I/O option signal, the first mode determination signal, the second mode signal, the third mode signal, and the fourth mode signal. 1. A semiconductor memory device , comprising:a mode control unit configured to generate an output signal in response to a first control signal enable signal, a second control signal enable signal, a third control signal enable signal, a fourth control signal enable signal, and a buffer enable signal received from an I/O control circuit;a pad unit comprising an I/O mode control pad, a data I/O pad, and a data I/O strobe pad;an input driving unit configured to be driven in response to the output signal of the mode control unit and electrically coupled to the pad unit;an output driving unit configured to be driven in response to the output signal of the mode control unit and electrically coupled to the pad unit; andan I/O conversion unit configured to provide a memory region with data received from the input driving unit and to provide the output driving unit with data received from the memory region in response to the fourth control signal enable signal.2. The semiconductor memory device of claim 1 , wherein the I/O control circuit comprises:a mode setting unit configured to generate a first mode signal, a second mode signal, a third mode signal, and a fourth mode signal in accordance with one of a plurality ...

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21-01-2016 дата публикации

ADDRESS GENERATION CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME

Номер: US20160019944A1
Принадлежит:

An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

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03-02-2022 дата публикации

METHOD OF PERFORMING INTERNAL PROCESSING OPERATIONS WITH PRE-DEFINED PROTOCOL INTERFACE OF MEMORY DEVICE

Номер: US20220036929A1
Принадлежит:

A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode. 1. A memory device comprising:a memory cell array including a first memory region and a second memory region;a processing-in-memory (PIM) engine configured to perform an internal processing operation on the first memory region;a mode selector circuit configured to activate a processing mode selection signal for controlling the memory device to enter the internal processing operation based on a PIM mode entering code, the PIM mode entering code being stored in the mode selector circuit and corresponding to a first back-to-back address sequence along with sequential write commands; anda command converter circuit configured to convert a received command into a PIM command in response to the activation of the processing mode selection signal.2. The memory device of claim 1 , wherein the mode selector circuit is further configured to receive first addresses sequentially claim 1 , compare the PIM mode entering code with the first addresses claim 1 , and activate the processing mode selection signal when the sequential first addresses coincide with the PIM mode entering code.3. The memory device of claim 1 , wherein the command converter circuit is further configured ...

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18-01-2018 дата публикации

METHOD FOR OPERATING A SERIAL NON-VOLATILE SEMICONDUCTOR MEMORY

Номер: US20180019016A1
Автор: STUHLFELNER FRIEDBERT
Принадлежит:

A method for operating a serial non-volatile semiconductor memory in which, for safely writing data into the semiconductor memory, a serial write sequence is applied to an input terminal. The sequence is formed at least with a sequence of command bits, a sequence of address bits and a sequence of data bytes. During the transmission of the bits of the write sequence, a clock signal is present at a clock input and a sufficiently high supply voltage is present at a supply voltage terminal. On occurrence of a supply voltage that is too low, the write sequence and/or the clock signal is subsequently transmitted incorrectly during the transmission of the write sequence and of the clock signal to the semiconductor memory. In the alternative, the write sequence is not transmitted at all. 1. A method for operating a serial non-volatile semiconductor memory , the method which comprises:applying a serial write sequence to an input terminal for safely writing data into the semiconductor memory, the write sequence being formed at least with a sequence of command bits, a sequence of address bits and a sequence of data bytes;during a transmission of the bits of the write sequence, applying a clock signal at a clock input;supplying a supply voltage at a supply voltage terminal; andon occasion of a low supply voltage, subsequently transmitting at least one of the write sequence or the clock sequence incorrectly during the transmission of the write sequence and of the clock signal to the semiconductor memory.2. The method according to claim 1 , which comprises claim 1 , subsequently to transmitting a last data byte of the write sequence claim 1 , transmitting a sequence of clock signal pulses having a number of at least 1 and at most 7.3. A method for operating a serial non-volatile semiconductor memory claim 1 , the method which comprises:applying a serial write sequence to an input terminal for safely writing data into the semiconductor memory, the write sequence being formed at ...

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21-01-2021 дата публикации

MEMORY MANAGEMENT OF COMPUTING DEVICES

Номер: US20210019068A1
Принадлежит:

In one embodiment, a method includes allocating, by an operating system of a computing device, computer-implemented memory into a discardable portion and a durable portion; receiving, from a computer-executable program, a designation indicator of a particular data file that is associated with the computer-executable program indicating that the particular file is to be stored in the discardable portion of the memory and in response, storing the particular data file in one or more particular pages of the discardable portion of the memory; identifying an occurrence of a computing condition and in response, marking the one or more particular pages that include the particular data file as invalid for the computer-executable program; receiving, from the computer-executable program, a request for the particular data file; and in response to receiving the request, providing, to the computer-executable program, a notification that the particular data file is invalid for the computer-executable program. 1. A computer-implemented method , comprising:allocating, by an operating system of a computing device, computer-implemented memory into a discardable portion and a durable portion;receiving, from a computer-executable program, a designation indicator of a particular data file that is associated with the computer-executable program indicating that the particular file is to be stored in the discardable portion of the memory;in response to receiving the designation indictor of the particular data file, storing the particular data file in one or more particular pages of the discardable portion of the memory;identifying an occurrence of a computing condition;in response to identifying the occurrence of the computing condition, marking the one or more particular pages that include the particular data file as invalid for the computer-executable program;receiving, from the computer-executable program, a request for the particular data file; andin response to receiving the request, ...

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21-01-2021 дата публикации

PERFORMING A REFRESH OPERATION BASED ON A WRITE TO READ TIME DIFFERENCE

Номер: US20210019084A1
Автор: Chen Zhengang, Xie Tingjun
Принадлежит:

A read operation can be performed to retrieve data of a write unit at a memory sub-system. An indication of a time of the performance of the read operation can be received. Another indication of another time of a performance of a write operation to store the data of the write unit at the memory sub-system can be received. A difference between the time of the performance of the read operation and the another time of the performance of the write operation can be determined. A refresh operation can be performed for the data of the write unit at the memory sub-system based on the difference between the time of the performance of the read operation and the another time of the performance of the write operation 1. A method comprising:performing a read operation to retrieve data of a write unit at a memory sub-system;receiving an indication of a time of the performance of the read operation;receiving another indication of another time of a performance of a write operation that stored the data of the write unit at the memory sub-system;determining a difference between the time of the performance of the read operation and the another time of the performance of the write operation; andperforming, by a processing device, a refresh operation for the data of the write unit at the memory sub-system based on the difference between the time of the performance of the read operation and the another time of the performance of the write operation.2. The method of claim 1 , further comprising:determining whether the difference between the time of the performance of the read operation and the another time of the performance of the write operation satisfies a threshold difference, wherein the refresh operation is performed responsive to the difference satisfying the threshold difference.3. The method of claim 2 , wherein the threshold difference corresponds to an amount of time that has elapsed since the performance of the write operation that stored the data of the write unit at the ...

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16-01-2020 дата публикации

REFRESH SCHEME IN A MEMORY CONTROLLER

Номер: US20200020384A1
Автор: Yao YuBin, Zhao Liang
Принадлежит: Advanced Micro Devices, Inc.

In one form, a memory controller includes a command queue, an arbiter, a refresh logic circuit, and a final arbiter. The command queue receives and stores memory access requests for a memory. The arbiter selectively picks accesses from the command queue according to a first type of accesses and a second type of accesses. The first type of accesses and the second type of accesses correspond to different page statuses of corresponding memory accesses in the memory. The refresh logic circuit generates a refresh command to a bank of the memory and provides a priority indicator with the refresh command whose value is set according to a number of pending refreshes. The final arbiter selectively orders the refresh command with respect to memory access requests of the first type accesses and the second type accesses based on the priority indicator. 1. A memory controller , comprising:a command queue for receiving and storing memory access requests for a memory;an arbiter for selectively picking accesses from the command queue according to a first type of accesses and a second type of accesses, wherein the first type of accesses and the second type of accesses correspond to different page statuses of corresponding memory accesses in the memory;a refresh logic circuit for generating a refresh command to a bank of the memory, and providing a priority indicator with the refresh command whose value is set according to a number of pending refreshes, wherein the refresh logic circuit assigns the priority indicator one of a first priority status and a second priority status; anda final arbiter for selectively ordering the refresh command with respect to memory access requests of the first type accesses and the second type accesses based on the priority indicator, wherein the final arbiter elevates the refresh command between the first type of accesses and the second type of accesses in response to the first priority status.2. (canceled)3. The memory controller of claim 1 , wherein ...

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21-01-2021 дата публикации

APPARATUS AND METHOD FOR IMPROVING INPUT/OUTPUT THROUGHPUT OF MEMORY SYSTEM

Номер: US20210020208A1
Автор: PARK Jeen
Принадлежит:

A memory system includes: a plurality of memory dies, and a controller selects a second read request, including at least a portion of a plurality of first read requests, so that the memory dies interleave and output data corresponding to the first read requests, and performs a correlation operation for the selected second read request, when the second read request is selected, the controller determines whether the correlation operation is performed or not before a time at which the second read request is selected, determines whether the correlation operation is successful or not, determines a pending credit in response to an operation state of the memory dies at the time at which the second read request is selected, and determines whether to perform the correlation operation or not for the second read request that is selected at the time at which the second read request is selected based on the pending credit. 1. A memory system , comprising:a plurality of memory dies; anda controller that is coupled to the memory dies through a plurality of channels, the controller comprising circuitry that:selects a second read request, including at least a portion of a plurality of first read requests transferred from an external device, so that the memory dies interleave and output data corresponding to the first read requests through the channels, andperforms a correlation operation for the selected second read request,wherein, when the second read request is selected, the controller determines whether the correlation operation is performed or not before a time at which the second read request is selected, determines whether the correlation operation is successful or not, determines a pending credit in response to an operation state of the memory dies at the time at which the second read request is selected, and determines whether to perform the correlation operation or not for the second read request that is selected at the time at which the second read request is selected ...

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21-01-2021 дата публикации

APPARATUSES AND METHODS FOR TRACKING ROW ACCESSES

Номер: US20210020223A1
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatuses and methods for tracking all row accesses in a memory device over time may be used to identify rows which are being hammered so that ‘victim’ rows may be identified and refreshed. A register stack may include a number of count values, each of which may track a number of accesses to a portion of the word lines of the memory device. Anytime a row within a given portion is accessed, the associated count value may be incremented. When a count value exceeds a first threshold, a second stack with a second number of count values may be used to track numbers of accesses to sub-portions of the given portion. When a second count value exceeds a second threshold, victim addresses may be provided to refresh the victim word lines associated with any of the word lines within the sub-portion. 1. An apparatus comprising:a memory array comprising a plurality of word lines;a first register stack configured to store a first plurality of count values, wherein each of the first plurality of count values is associated with a portion of the plurality of word lines;a first counter circuit configured to update a first count value of the first plurality of count values responsive to a row address associated with the portion of the plurality of word lines associated with the first count value and configured to compare the updated first count value to a first threshold;a second register stack configured to store a second plurality of count values, wherein each of the second plurality of count values is associated with a sub-portion of a selected one of the portions of the plurality of word lines;a second counter circuit configured to update a second count value of the second plurality of count values responsive to a row address associated with the sub-portion associated with the second count value and configured to compare the updated second count value to a second threshold; andan address circuit configured to provide a plurality of victim addresses based on the sub-portion of the ...

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21-01-2021 дата публикации

APPARATUSES AND METHODS FOR ADJUSTING VICTIM DATA

Номер: US20210020262A1
Принадлежит: MICRON TECHNOLOGY, INC.

Addresses of accessed word lines are stored. Data related to victim word lines associated with the accessed word line are also stored. The victim word lines may have data stored in relation to multiple accessed word lines. The data related to the victim word lines is adjusted when the victim word line is refreshed during a targeted refresh operation or an auto-refresh operation. The data related to the victim word lines is adjusted when the victim word line is accessed during a memory access operation. 1. An apparatus comprising:a reverse scrambler configured to provide an aggressor row address associated with at least one of a refresh address or an accessed row address; anda victim data logic circuit configured to adjust victim data associated with a row address stored in a stack that matches the aggressor row address.2. The apparatus of claim 1 , wherein the victim data comprises a plurality of bits claim 1 , wherein each bit of the plurality of bits corresponds to a victim word line associated with the accessed word line of a corresponding row address of the plurality of row addresses.3. The apparatus of claim 2 , wherein a bit in a first state indicates the victim word line has not been healed and the bit in a second state indicates the victim word line has been refreshed or accessed.4. The apparatus of claim 1 , wherein the victim data logic circuit adjusts the victim data to indicate the at least one victim word line has been refreshed or accessed.5. The apparatus of claim 1 , wherein the reverse scrambler is further configured to provide a plurality of aggressor row addresses associated with at least one of the refresh address or the accessed row address.6. An apparatus comprising:a victim data logic circuit configured to set a victim flag to a refreshed state, wherein the victim flag is associated with a row address that matches an aggressor row address of a plurality of aggressor row addresses.7. The apparatus of claim 6 , further comprising an aggressor ...

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22-01-2015 дата публикации

MEMORY DEVICE WITH OVER-REFRESH AND METHOD THEREOF

Номер: US20150026537A1

A method for over-refreshing a memory device comprises in a refreshing cycle, refreshing normal cells and a weak cell, and additionally refreshing the weak cell at least once. 1. A method , comprising: refreshing normal cells and a weak cell in a memory device; and', 'additionally refreshing the weak cell at least once., 'in a refreshing cycle,'}2. The method according to claim 1 , further comprising:extracting a row address of the weak cell for additionally refreshing the weak cell in the refreshing cycle based on the extracted row address.3. The method according to claim 2 , whereinif the weak cell is detected during testing of the memory device, extracting the row address of the weak cell is performed after power-up and before operation of the memory device.4. The method according to claim 1 , wherein when the memory device is in use and if the weak cell is detected by monitoring a result of error detection and correction of the memory device claim 1 , the method further comprises:reading data stored in the weak cell;performing error detection and correction on the read data; andwriting data obtained from performing error detection and correction into the weak cell.5. The method according to claim 4 , further comprising:in the same clock cycle of reading the data stored in the weak cell or writing the data into the weak cell, extracting a row address of the weak cell for additionally refreshing the weak cell in the refreshing cycle based on the extracted row address.6. The method according to claim 1 , wherein when the memory device is in use and if the weak cell is detected by monitoring a result of error detection and correction of the memory device claim 1 , the method further comprises:performing error detection and correction on data stored in the weak cell; andwriting the data obtained from performing external error detection into the weak cell.7. The method according to claim 6 , further comprising:in the same clock cycle of writing the data into the weak ...

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26-01-2017 дата публикации

Methods of Retaining and Refreshing Data in a Thyristor Random Access Memory

Номер: US20170025163A1
Принадлежит:

A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read, write, retain and refresh data stored therein. 1. A method of operating a volatile memory array having anode lines , cathode lines , and an array of vertical thyristors having anodes coupled to the anode lines and having cathodes coupled to the cathode lines , the method to retain stored data in all of the thyristors comprising:applying to all anode lines a first potential;applying to all cathode lines a second potential; whereinthe difference between the first and second potentials is sufficient to keep thyristors which are on turned on.2. A method as in wherein:the first potential is about 0.5-0.7 volts; andthe second potential is about 0.0 volts. This patent application is a divisional of U.S. patent application Ser. No. 14/841,140, filed Aug. 31, 2015, which is related to U.S. patent application Ser. No. 14/841,140, filed of even date and entitled, “Thyristor Volatile Random Access Memory and Methods of Manufacture,” U.S. patent application Ser. No. 14/841,521, filed of even date and entitled, “Methods of Reading and Writing Data in a Thyristor Random Access Memory,” U.S. patent application Ser. No. 14/841,615, filed of even date and entitled, “Power Reduction in Thyristor Random Access Memory;” all of which claim priority from U.S. Provisional Patent No. 62/186,336, filed Jun. 29, 2015, and entitled, “High-Density Volatile RAMs, Method of Operation and Manufacture Thereof,” and is a continuation-in-part of U.S. application Ser. No. 14/590,834, filed Jan. 6, 2015 and entitled, “Cross-Coupled Thyristor SRAM Circuits and Methods of Operation,” which claims priority from U.S. Provisional Patent Application No. 62/055,582, filed Sep. 25, 2014; all of which are incorporated by reference herein for all purposes.This invention is related to integrated circuit devices and in particular to volatile random access memories, commonly known as dynamic random ...

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28-01-2016 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT

Номер: US20160027483A1
Автор: Kim Jae Il
Принадлежит:

A semiconductor integrated circuit may include: a memory block partitioned into a first region and a second region; a data latch unit configured to latch data outputted from the memory block in response to a control signal; and a control circuit configured to generate a source signal separated into an odd order and an even order in response to a column access signal consecutively inputted to access the first region or the second region, and to generate the control signal in response to the source signal. 1. A semiconductor integrated circuit comprising:a memory block partitioned into a first region and a second region;a data latch unit configured to latch data outputted from the memory block in response to a control signal; anda control circuit configured to generate a source signal separated into an odd order and an even order in response to a column access signal consecutively inputted to access the first region or the second region, and to generate the control signal in response to the source signal.2. The circuit according to claim 1 , wherein the data latch unit comprises a pipe latch.3. The circuit according to claim 1 , wherein the column access signal is generated according to a read command.4. The circuit according to claim 1 , wherein the control circuit is configured to generate a first strobe signal for access the first region and a second strobe signal for access the second region using the consecutively inputted column access signal.5. The circuit according to claim 4 , wherein the control circuit is configured to separate each of a first strobe signal and a second strobe signal into an odd order and an even order claim 4 , and to generate the source signal. The present application is a Division of U.S. application Ser. No. 14/148,254, filed on Jan. 6, 2014, and the present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2013-0132393, filed on Nov. 1, 2013, in the Korean Intellectual Property Office, which is ...

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28-01-2016 дата публикации

Refresh circuit

Номер: US20160027491A1
Автор: Hong Jung Kim
Принадлежит: SK hynix Inc

A refresh circuit is configured to perform a first refresh operation for a plurality of memory banks. The first refresh operation may be performed within a first time period determined according to a first parameter. The refresh circuit may be configured to perform a second refresh operation for a partial number of memory banks among the plurality of memory banks. The second refresh operation may be performed for the partial number of memory banks that have completed the first refresh operation. The second refresh operation may be performed within the first time period.

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28-01-2016 дата публикации

Semiconductor memory device, method of performing a refresh for semiconductor memory device and refresh counter in semiconductor memory device

Номер: US20160027492A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor memory device may include a memory cell array, a first decoder and a second decoder. The memory cell array includes a plurality of memory cell rows. The first decoder is configured to select a first number of memory cell rows of the plurality of memory cell rows based on a selected refresh row address of a set of row addresses. The second decoder is configured to select a second number of memory cell rows of the plurality of memory cell rows based on the selected refresh row address. A total number of the first number and the second number is varied in response to the selected refresh row address.

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28-01-2016 дата публикации

DYNAMIC RANDOM ACCESS MEMORY FOR COMMUNICATIONS SYSTEMS

Номер: US20160027493A1
Автор: Ling Curtis
Принадлежит:

An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells. The first DRAM cell(s) may be refreshed by the memory refresh circuit whereas the second DRAM cell(s) is not refreshed by any memory refresh circuit. Each of the first DRAM cell(s) and the second DRAM cell(s) may be a one-transistor cell. The first DRAM cell(s) may be used for storage of data which is overwritten at less than a threshold frequency. The second DRAM cell(s) may be used for storage of data which is overwritten at greater than the threshold frequency. A rate at which the first DRAM cell(s) are refreshed may be adjusted during run-time of the integrated circuit. 1. A system comprising: said one or more DRAM cells is refreshed by said memory refresh circuit;', 'said one or more DRAM cells store data received via a communication link; and', 'a rate at which said one or more DRAM cells is refreshed is adjusted based on a symbol rate at which said data is received via said communication link., 'an integrated circuit comprising a digital logic circuit, a memory refresh circuit, and one or more dynamic random access memory (DRAM) cells, wherein2. The system of claim 1 , wherein each of said one or more DRAM cells and said second one or more DRAM cells is a one-transistor (“1T”) cell.37-. (canceled)8. The system of claim 1 , wherein said adjustment of said rate at which said one or more DRAM cells is refreshed comprises an enabling of refresh of said one or more DRAM cells by said memory refresh circuit during a first time interval and a disabling of refresh of said one or more DRAM cells by said memory refresh circuit during a second time interval.9. The system of claim 1 , wherein said adjustment of said rate at which said one or more DRAM cells is refreshed is based on a forward error correction code rate of said data.1020-. (canceled)21. The system of claim 1 , wherein:said ...

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28-01-2016 дата публикации

PRIORITIZING REFRESHES IN A MEMORY DEVICE

Номер: US20160027494A1
Принадлежит:

A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate refresh circuit. The intermediate refresh circuit may be configured to detect a triggering event and request a refresh for a row of the memory array in response to detecting a triggering event. 1. A memory device comprising:a memory array including a plurality of memory cells, the memory array configured to be refreshed at a first refresh time interval; andan intermediate refresh circuit, the intermediate refresh circuit configured to detect a triggering event and request a refresh for a row of the memory array in response to detecting a triggering event.2. The memory device of claim 1 , wherein the refresh for the row of the memory array is configured to occur at a second refresh time interval claim 1 , the second refresh time interval being less than the first refresh time interval.3. The memory device of claim 1 , wherein the memory array includes a dynamic random access memory (DRAM) array.4. The memory device of claim 1 , wherein the intermediate refresh circuit comprises:a field-effect transistor (FET);a current source configured to drain a tank capacitor, wherein a voltage of the tank capacitor corresponds to a reference voltage;a comparator configured to determine whether the voltage of the tank capacitor is outside a threshold; anda refresh requester configured to request the refresh in response to a determination of the comparator.5. The memory device of claim 4 , wherein the FET is at least one of a positive channel field-effect transistor and a negative channel field-effect transistor.6. The memory device of claim 1 , wherein the intermediate refresh circuit comprises:a row access calculator, the row access calculator configured to charge a tank capacitor; an OR gate ...

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28-01-2016 дата публикации

Reduced refresh power

Номер: US20160027498A1
Принадлежит: RAMBUS INC

N out of every M number of refresh commands are ignored (filtered out) by a buffer chip on a memory module. N and M are programmable. The buffer receives refresh commands (e.g., auto-refresh commands) from the command-address channel, but does not issue a proportion of these commands to the DRAMs on the module. This reduces the power consumed by refresh operations. The buffer may replace some auto-refresh (REF) commands with activate (ACT) and precharge (PRE) commands directed to specific rows. These rows may have known ‘weak’ cells that require refreshing more often than a majority of the other rows on the module (or component). By ignoring some auto-refresh commands, and directing some others to specific rows that have ‘weak’ cells, the power consumed by refresh operations can be reduced.

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28-01-2016 дата публикации

APPARATUSES AND METHODS FOR TARGETED REFRESHING OF MEMORY

Номер: US20160027531A1
Принадлежит:

Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory. 1. An apparatus , comprising:a predecoder configured to receive a target row address and determine whether a target row of memory associated with the target row address is a row of primary memory or a row of redundant memory, the predecoder being further configured to cause one or more rows of memory physically adjacent the row of primary memory to be refreshed in association with a first case in which the row of primary memory is the target row of memory and to cause one or more rows of memory physically adjacent the row of redundant memory to be refreshed in association with a second case in which the row of redundant memory is the target row of memory.2. The apparatus of claim 1 , wherein the predecoder is further configured to generate a row address for the one or more rows of memory physically adjacent the row of primary memory in association with the first case and the row of redundant memory in association with the second case based claim 1 , at least in part claim 1 , on the target row address.3. The apparatus of claim 2 , wherein the predecoder is configured to cause the row of redundant memory to be refreshed in association with a third case in which the row redundant memory is enabled and not cause the row of redundant memory to be refreshed in associate with a fourth case in which the row of redundant memory is disabled.4. The apparatus of claim 1 , wherein the ...

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28-01-2016 дата публикации

MEMORY DEVICE

Номер: US20160027532A1
Автор: Kim Sang-Hee
Принадлежит:

A memory device includes a plurality of redundancy word lines each of which is coupled with a plurality of redundancy memory cells, and a redundancy refresh circuit suitable for sequentially refreshing first redundancy word lines that are selected as target word lines for an additional refresh operation among the plurality of the redundancy word lines. 1. A memory device , comprising:a plurality of redundancy word lines, each of which is coupled with a plurality of redundancy memory cells; anda redundancy refresh circuit suitable for sequentially refreshing first redundancy word lines that are selected as target word lines for an additional refresh operation among the plurality of the redundancy word lines.2. The memory device of claim 1 , wherein the first redundancy word lines are selected as the target word lines based on the number of second redundancy word lines that are used for a repair operation among the plurality of the redundancy word lines.3. The memory device of claim 1 , wherein redundancy word lines that are used for a repair operation among the plurality of the redundancy word lines are included in the first redundancy word lines.4. The memory device of claim 1 , wherein odd-numbered redundancy word lines are used for a repair operation after even-numbered redundancy word lines are all used for the repair operation claim 1 , among the plurality of the redundancy word lines.5. The memory device of claim 4 , wherein the first redundancy word lines are selected as the target word lines based on the number of third redundancy word lines that are used for the repair operation among the odd-numbered redundancy word lines.6. The memory device of claim 4 , wherein when no word line is used for the repair operation among the odd-numbered redundancy word lines claim 4 , there is no target word line for the additional refresh operation.7. The memory device of claim 1 , wherein even-numbered redundancy word lines are used for a repair operation after odd- ...

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25-01-2018 дата публикации

DIRECTED PER BANK REFRESH COMMAND

Номер: US20180025771A1
Автор: Bains Kuljit S.
Принадлежит:

A memory device includes a per bank refresh counter applicable to multiple banks in a group. The memory device increments a row address counter only when the per bank refresh counter is reset. The memory device receives a per bank refresh command from an associated memory controller, and performs a per bank refresh in response to receiving the per bank refresh command. The memory device refreshes a row identified by a row address counter for a bank identified by the per bank refresh command. The memory device increments the per bank refresh counter in response to receiving the per bank refresh command, and increments the row address counter when the per bank refresh counter is reset, either by rolling over or by a reset condition. 1. A method comprising:receiving a per bank refresh command at a memory device from a memory controller;performing a per bank refresh in response to receiving the per bank refresh command for a bank identified by the command at a row identified by a row address counter;incrementing a per bank refresh counter in response to receiving the per bank refresh command;determining if incrementing the per bank refresh counter causes the per bank refresh counter to roll over; andwhen the per bank refresh counter rolls over, incrementing the row address counter;otherwise, maintaining the row address counter at a current value for a subsequent per bank refresh command.2. The method of claim 1 , wherein receiving the per bank refresh command comprises receiving a command to refresh a bank out of bank address order.3. The method of claim 2 , wherein receiving the command out of bank address order comprises receiving the command to refresh the banks in a random order.4. The method of claim 1 , wherein performing the per bank refresh comprises refreshing all banks via per bank refresh command prior to repeating a per bank refresh of any of the banks.5. The method of claim 1 , wherein incrementing the per bank refresh counter comprises incrementing a ...

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25-01-2018 дата публикации

PRECHARGING AND REFRESHING BANKS IN MEMORY DEVICE WITH BANK GROUP ARCHITECTURE

Номер: US20180025773A1
Принадлежит:

Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command. 126-. (canceled)27. A dynamic random access memory (DRAM) device comprising:multiple banks of memory addressable by bank group identifier and by bank identifier;interface hardware to couple to multiple signal lines of a command and address bus; andlogic to identify a signal pattern at the interface hardware as a same bank command including a bank identifier and not including a bank group identifier, the logic to apply the same bank command to banks identified by the bank identifier across multiple different bank groups.28. The DRAM device of claim 27 , wherein the same bank command comprises a same bank refresh command.29. The DRAM device of claim 28 , wherein the logic includes both an internal bank counter to track a refresh count to specific banks claim 28 , and a global refresh counter.30. The DRAM device of claim 27 , wherein the same bank command comprises a same bank precharge command.31. The DRAM device of claim 27 , wherein the same bank command comprises a sequence of a same bank precharge command and a same bank refresh command to access the same bank identifier in different bank groups.32. The DRAM device of claim 27 , wherein the signal pattern includes a single signal line logic value to differentiate the same bank command from a command directed to bank and bank group.33. The DRAM device of claim 27 , wherein the multiple bank groups includes 2 or 4 bank groups.34. The DRAM device of claim 33 , wherein the multiple banks includes 8 banks in each bank group.35. The DRAM device of claim 27 , wherein the DRAM device comprises a memory device ...

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24-04-2014 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20140111251A1
Автор: KIM Yong-Mi
Принадлежит: SK HYNIX INC.

A semiconductor device includes an information generation circuit configured to generate first information, an information multiplexing circuit configured to multiplex the first information and second information, and an information driving circuit configured to drive an output pad in response to an output signal of the information multiplexing circuit. 1. A semiconductor device , comprising:a first driving circuit configured to drive an output pad in response to first information in an operation mode using the First information; anda second driving circuit configured to precharge the output pad in response to a precharge control signal.2. The semiconductor device of wherein the first driving circuit and the second driving circuit are switched on at different times claim 1 , respectively.3. The semiconductor device of claim 1 , wherein the first driving circuit is configured to be pull-down driven and the second driving circuit is configured to be pull-up driven.4. The semiconductor device of claim 1 , wherein the first information includes information about an error detected from a signal transferred through a signal transfer line.5. The semiconductor device of claim 1 , further comprising:a data output unit configured to receive and output internal data and perform a calibration operation on the output pad in response to a calibration code. This application is a division of U.S. patent application Ser. No. 13/445,455 filed on Apr. 13, 2012, which claims priority of Korean Patent Application No. 10-2011-0139553, filed on Dec. 21, 2011. The disclosure of each of the foregoing application is incorporated herein by reference in its entirety.1. FieldExemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a semiconductor device including a driving circuit for outputting specific information.2. Description of the Related ArtGenerally, semiconductor devices including Double Data Rate Synchronous Dynamic ...

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24-01-2019 дата публикации

MINIMIZING PERFORMANCE DEGRADATION DUE TO REFRESH OPERATIONS IN MEMORY SUB-SYSTEMS

Номер: US20190026028A1
Принадлежит:

Disclosed are techniques for minimizing performance degradation due to refresh operations in a dynamic volatile memory sub-system. In an aspect, a refresh scheduler coupled to the dynamic volatile memory sub-system generates a batch memory refresh command comprising an identification of a plurality of rows of each of one or more banks of the dynamic volatile memory sub-system to refresh, and issues the batch memory refresh command to the dynamic volatile memory sub-system. 1. A method for minimizing performance degradation due to refresh operations in a dynamic volatile memory sub-system , the method comprising:generating, by a refresh scheduler coupled to the dynamic volatile memory sub-system, a batch memory refresh command comprising an identification of a plurality of rows of each of one or more banks of the dynamic volatile memory sub-system to refresh; andissuing, by the refresh scheduler, the batch memory refresh command to the dynamic volatile memory sub-system.2. The method of claim 1 , wherein the one or more banks of the dynamic volatile memory sub-system to refresh comprise multiple banks of the dynamic volatile memory sub-system claim 1 , all banks of the dynamic volatile memory sub-system claim 1 , or a single bank of the dynamic volatile memory sub-system.3. The method of claim 1 , wherein the plurality of rows comprise two rows or four rows.4. The method of claim 1 , wherein the batch memory refresh command comprises a precharge field claim 1 , the identification of the plurality of rows claim 1 , and a plurality of activate fields.5. The method of claim 1 , wherein the generating the batch memory refresh command is based on a temperature of the dynamic volatile memory sub-system being greater than a temperature threshold claim 1 , high bandwidth performance being requested claim 1 , or latency-critical performance not being requested.6. The method of claim 5 , further comprising:receiving, from one or more clients of the dynamic volatile memory sub- ...

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10-02-2022 дата публикации

STAGGERING REFRESH ADDRESS COUNTERS OF A NUMBER OF MEMORY DEVICES, AND RELATED METHODS, DEVICES, AND SYSTEMS

Номер: US20220044720A1
Принадлежит:

Methods of operating a number of memory devices are disclosed. A method may include receiving, at each of a number of memory devices, a refresh command. The method may also include refreshing, at each of the number of memory devices and in response to the refresh command, a number of memory cells based on a count of an associated refresh address counter, wherein a count of a refresh address counter of at least one memory device of the number of memory devices is offset from a count of a refresh address counter of at least one other memory device of the number of memory devices. Related systems and memory modules are also described. 1. A method , comprising:receiving, at each of a number of memory devices, a refresh command; andrefreshing, at each of the number of memory devices and in response to the refresh command, a number of memory cells based on a count of an associated refresh address counter, a count of a refresh address counter of at least one memory device of the number of memory devices being offset from a count of a refresh address counter of at least one other memory device of the number of memory devices.2. The method of claim 1 , further comprising adjusting the count of the refresh address counter of the at least one memory device such that the count of the refresh address counter of the at least one memory device is offset from the count of the refresh address counter of the at least one other memory device.3. The method of claim 1 , further comprising incrementing an associated count of a refresh address counter of each memory device of the number of memory devices in response to refreshing the number of memory cells.4. The method of claim 1 , further comprising adjusting an associated count of a refresh address counter of more than one memory device of the number of memory devices such that a device-to-device counter offset amongst the number of memory devices is equal.5. The method of claim 1 , further comprising adjusting the count of the refresh ...

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10-02-2022 дата публикации

Signal development caching in a memory device

Номер: US20220044723A1
Принадлежит: Micron Technology Inc

Methods, systems, and devices related to signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In various examples, accessing the memory device may include accessing information from the signal development cache, or the memory array, or both, based on various mappings or operations of the memory device.

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28-01-2021 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20210026788A1
Принадлежит:

A semiconductor device includes a first master and a second master configured to issue requests for accessing to a memory, a first request issuing controller coupled to the first master, and configured to hold the request issued from the first master, a second request issuing controller coupled to the second master, and configured to hold the request issued from the second master, a bus arbiter coupled to the first request issuing controller and the second request issuing controller, a memory controller coupled to the bus arbiter, and including a buffer configured to store the requests issued from the first master and the second master, and a central bus controller configured to grant access rights to the first request issuing controller and the second request issuing controller based on space information of the buffer. 1. A semiconductor device comprising:a first master and a second master configured to issue requests for accessing to a memory;a first request issuing controller coupled to the first master, and configured to hold the request issued from the first master;a second request issuing controller coupled to the second master, and configured to hold the request issued from the second master;a bus arbiter coupled to the first request issuing controller and the second request issuing controller;a memory controller coupled to the bus arbiter, and including a buffer configured to store the requests issued from the first master and the second master; anda central bus controller configured to grant access rights to the first request issuing controller and the second request issuing controller based on space information of the buffer,wherein the first request issuing controller and the second request issuing controller are configured to output the held request to the bus arbiter in response to the access right,wherein the bus arbiter is configured to receive the requests output from the first request issuing controller and the second request issuing controller, to ...

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23-01-2020 дата публикации

CONFIGURING DYNAMIC RANDOM ACCESS MEMORY REFRESHES FOR SYSTEMS HAVING MULTIPLE RANKS OF MEMORY

Номер: US20200027499A1
Принадлежит:

An electronic device including a memory functional block having multiple ranks of memory and a memory controller functional block coupled to the memory. The memory controller includes refresh logic that detects, based on buffered memory accesses for each rank of memory of the ranks of memory, two or more ranks of memory for which a refresh is to be performed during a refresh interval. Based at least in part on one or more properties of buffered memory accesses for the two or more ranks of memory, the refresh logic determines a refresh order for performing refreshes for the two or more ranks of memory during the refresh interval. The memory controller then performs, in the refresh order, refreshes for the two or more ranks of memory during the refresh interval. 1. An electronic device , comprising:a memory functional block that includes multiple ranks of memory; and detect, based on buffered memory accesses for each rank of memory of the ranks of memory, two or more ranks of memory for which a refresh is to be performed during a refresh interval;', 'based at least in part on one or more properties of buffered memory accesses for the two or more ranks of memory, determine a refresh order for performing refreshes for the two or more ranks of memory during the refresh interval, wherein each rank of memory is included at a respective place in the refresh order relative to other ranks of memory from the two or more ranks of memory based at least in part on the one or more properties of the buffered memory accesses; and', 'perform, in the refresh order, refreshes for the two or more ranks of memory during the refresh interval., 'a memory controller functional block coupled to the memory, the memory controller including refresh logic that is configured to2. The electronic device of claim 1 , wherein claim 1 , when performing claim 1 , in the refresh order claim 1 , the refreshes for the two or more ranks of memory during the refresh interval claim 1 , the refresh logic is ...

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28-01-2021 дата публикации

ADAPTIVE WRITE OPERATIONS FOR A MEMORY DEVICE

Номер: US20210027813A1
Принадлежит:

Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations). 1. A method , comprising:identifying a quantity of access operations performed on a memory array, the memory array comprising a plurality of memory cells each associated with a respective memory element storing a value based at least in part on a change in a material property associated with the memory element, wherein the quantity of access operations comprises a quantity of write operations and a quantity of read operations;modifying one or more parameters for a write operation based at least in part on the identified quantity of access operations; andwriting a logic state to one or more of the plurality of memory cells by performing the write operation according to the one or more modified parameters.2. The method of claim 1 , further comprising:determining that the identified quantity of access operations exceeds a threshold, wherein modifying the one or more parameters is based at least in part on the determining.3. The method of claim 1 , wherein the modifying the one or more parameters of the write operation comprises:modifying a current magnitude of the write operation.4. ...

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24-04-2014 дата публикации

DEVICE, SYSTEM, AND METHOD OF MEMORY ALLOCATION

Номер: US20140115248A1
Принадлежит:

Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System. 1. A non-transitory machine-readable medium storing instructions , the instructions , when read by a machine to cause the machine to:allocate a first portion of a dynamic random access memory (DRAM) bank to refresh at a first refresh rate to maintain a context of data stored in the first portion; andallocate a second portion of the DRAM bank to not refresh at the first refresh rate, the second portion of the DRAM bank to at least maintain a context of data stored in the second portion for a period of time.2. The medium of claim 1 , wherein a circuitry comprising a memory location in the allocated first portion of the DRAM bank consumes a greater amount of power claim 1 , at least during a refresh cycle claim 1 , than a circuitry comprising a memory location in the allocated second portion of the DRAM bank.3. The medium of claim 1 , wherein at least a portion of the second portion of the DRAM bank to be allocated at a first time.4. The medium of claim 3 , wherein the at least portion of the second portion of the DRAM bank to not refresh after the first time.5. The medium of claim 1 , wherein the second portion of the DRAM bank to change an allocation size during operation of the DRAM bank.6. An apparatus claim 1 , comprising: a first portion of the DRAM bank allocated to refresh at a first refresh rate to maintain a context of data stored in the first portion; and', 'a second portion of the DRAM bank allocated ...

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05-02-2015 дата публикации

Data output circuits

Номер: US20150035575A1
Автор: Jae Woong Yun
Принадлежит: SK hynix Inc

Data output circuits are provided. The data output circuit includes a latch control signal generator and a data output portion. The latch control signal generator generates an input pulse signal and a latch control signal i, and the latch control signal includes a pulse whose width is controlled to have a predetermined time period. The data output portion latches a data loaded on an input/output (I/O) line during a pulse width period of the latch control signal to generate a latch data. Moreover, the data output portion buffers the latch data according to an output control signal generated from a read command signal to output the buffered latch data as an output data.

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04-02-2016 дата публикации

DYNAMIC RANDOM ACCESS MEMORY AND BOOSTED VOLTAGE PRODUCER THEREFOR

Номер: US20160035407A1
Автор: PYEON Hong Beom

A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode. 1. (canceled)2. A method comprising:providing an output voltage to be used for operation of a Dynamic Random Access Memory (DRAM);determining whether the output voltage reaches a predetermined level to provide a determination result;providing a plurality of enable signals in response to a refresh time when the DRAM is in a sleep mode, the refresh time being user-changeable; andactivating a number of a plurality of pump circuit segments of a charge pump in response to respective asserted enable signals of the plurality of enable signals, the charge pump for producing the output voltage, and the number of the plurality of pump circuit segments that are activated being inversely related to the refresh time.3. The method of further comprising:receiving a plurality of refresh time signals representing the refresh time; andcontrolling the activating of the number of a plurality of pump circuit segments based on the plurality of refresh time signals.4. The method of further comprising performing a refresh operation using the output voltage.5. The method of wherein the providing of the output voltage includes pumping the output voltage in response to an oscillation signal provided in the sleep mode.6. The method of further comprising generating the oscillation signal in a sleep mode oscillator.7. The method of wherein at least one of the plurality of pump circuit segments receives a respective de-asserted enable signal of the plurality of enable signals and is thus not activated.8. The method of wherein the charge pump is a sleep mode pump circuit ...

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04-02-2016 дата публикации

MEMORY CONTROL DEVICE AND A DELAY CONTROLLER

Номер: US20160035408A1
Автор: IWASAKI Keiichi
Принадлежит:

A memory control device includes a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory. Further, the memory control device includes a first register to store a first DLL value output by a delay locked loop circuit, a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits, and a delay controller to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value. 1. A memory control device including a delay locked loop circuit , the memory control device comprising:a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory;a first register to store a first DLL value output by the delay locked loop circuit;a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits; anda delay controller to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value, wherein{'b': '1', 'claim-text': {'br': None, 'i': B', 'B', '/A', 'A, 'sub': n', 'n-1', 'n-1', 'n, '=()×'}, 'the delay controller calculates the second setting value at n times, where n is a natural number equal to or greater than , using the following equation,'}{'sub': 'n-1', 'the Ais the first DLL value ...

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04-02-2016 дата публикации

MEMORY AND MEMORY SYSTEM INCLUDING THE SAME

Номер: US20160035410A1
Автор: SONG Choung-Ki
Принадлежит:

A memory includes a first cell array including a plurality of first memory cells connected to a plurality of word lines, a bit line selection unit configured to select one or more bit lines among a plurality of bit lines based on repair information, a second cell array including a plurality of second memory cells connected to the plurality of word lines and the plurality of bit lines, wherein a group of the plurality of second memory cells connected to a corresponding word line stores the number of activations of the corresponding word line when the one or more connected bit lines are selected and an activation number update unit configured to update a value stored in the second memory cells, which are connected to the one or more selected bit lines and the activated word line among the plurality of word lines. 16-. (canceled)7. A memory system comprising:a memory including a first cell array including a plurality of first memory cells connected to a plurality of word lines, and a second cell array including a plurality of second memory cells connected to the plurality of word lines and a plurality of bit lines, wherein a group of the plurality of second memory cells connected to a corresponding word line stores the number of activations of the corresponding word line when the one or more connected bit lines are selected, and wherein the memory is configured to generate an alert signal when the number of activations of the corresponding word line is equal to or greater than a reference number; anda memory controller configured to apply an excessive address and at least one adjacent address having a value adjacent to the excessive address, to the memory in a special refresh mode, wherein the excessive address corresponds to a word line of which the number of activation is equal or greater than the reference number.8. The memory system according to claim 7 , wherein the memory controller is configured to control the memory to enter the special refresh mode when the ...

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17-02-2022 дата публикации

Content-addressable memory for signal development caching in a memory device

Номер: US20220050776A1
Принадлежит: Micron Technology Inc

Methods, systems, and devices related to content-addressable memory for signal development caching are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may also include storage, such as a content-addressable memory, configured to store a mapping between addresses of the signal development cache and addresses of the memory array. In various examples, accessing the memory device may include determining and storing a mapping between addresses of the signal development cache and addresses of the memory array, or determining whether to access the signal development cache or the memory array based on such a mapping.

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