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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 191. Отображено 126.
16-08-2016 дата публикации

Estimating read reference voltage based on disparity and derivative metrics

Номер: US0009417797B2
Автор: Zhengang Chen, Erich F. Haratsch, Sundararajan Sankaranarayanan, Yunxiang Wu, CHEN ZHENGANG, HARATSCH ERICH F, SANKARANARAYANAN SUNDARARAJAN, WU YUNXIANG, Chen Zhengang, Haratsch Erich F., Sankaranarayanan Sundararajan, Wu Yunxiang
Принадлежит: Seagate Technology LLC, SEAGATE TECHNOLOGY LLC

An adaptive channel tracking algorithm performed by a flash memory system obtains disparity metrics and derivative metrics and uses a combination of the disparity and derivative metrics to estimate an optimal read reference voltage. The estimation of the optimal read reference voltage does not rely on assumptions about the underlying cell voltage distributions and results in a good estimate of the read reference voltage even if the standard deviations of the cell voltage distributions are different. In addition, the algorithm is relatively simple and less computationally intensive to perform than the known tracking algorithms.

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Номер записи: 1
08-06-2017 дата публикации

Reduction or Elimination of a Latency Penalty Associated With Adjusting Read Thresholds for Non-Volatile Memory

Номер: US20170162268A1
Автор: Zhengang Chen, Erich F. Haratsch, Sundararajan Sankaranarayanan, CHEN ZHENGANG, HARATSCH ERICH F, SANKARANARAYANAN SUNDARARAJAN, Chen Zhengang, Haratsch Erich F., Sankaranarayanan Sundararajan
Принадлежит:

Channel information and channel conditions determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is so adjusted. This latter approach is advantageous in that relatively fewer adjustments will be made during normal read operations. 1. A data storage system , comprising:a controller having a host interface, a buffer, and a device interface, the host interface arranged to communicate with at least one external computing device and at least one data processor, the buffer arranged to temporarily store data in transit between the host interface and the device interface as directed by the at least one data processor, the buffer further arranged to store system information including a set of operational read threshold values; anda nonvolatile memory device (NVMD) comprising at least one flash memory die having a plurality of memory cells coupled to the device interface;wherein in response to a write operation received from the host interface, the controller modifies data in transit between the host interface and the device interface such that data bits stored in the NVMD are randomly distributed in a desired storage state distribution;wherein in response to a read operation received from the host interface, the controller attempts to recover original data and when uncorrectable errors are identified, the ...

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Номер записи: 2
25-05-2017 дата публикации

MANUFACTURER SELF-TEST FOR SOLID-STATE DRIVES

Номер: US20170148530A1
Автор: Zhengang Chen, David Patmore, Yingji Ju, Erich F. Haratsch, CHEN ZHENGANG, PATMORE DAVID, JU YINGJI, HARATSCH ERICH F, Chen Zhengang, Patmore David, Ju Yingji, Haratsch Erich F.
Принадлежит:

An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list. 1. An apparatus comprising:a memory configured to store data; anda controller configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list.2. The apparatus according to claim 1 , wherein the code rate test is performed as part of a manufacturer self-test prior to processing the input/output requests.3. The apparatus according to claim 1 , wherein the three or more code rates of the code rate test are arranged in a plurality of tiers in an adaptive code rate technique used by the controller to process the plurality of input/output requests claim 1 , and at least one of the plurality of tiers includes at least two of the code rates.4. The apparatus according to claim 1 , wherein the code rate test initializes a code rate table used by the controller to process the plurality of input/output requests.5. The apparatus according to claim 1 , wherein the code rate test is configured to stop at an intermediate code rate of the three or more code rates based on a number of decoding iterations.6. The apparatus according to claim 1 , wherein the code rate test includes a low-density parity-check code to program the plurality of blocks.7. The apparatus according to ...

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Номер записи: 3
08-12-2016 дата публикации

SYSTEMS AND METHODS FOR LATENCY BASED DATA RECYCLING IN A SOLID STATE MEMORY SYSTEM

Номер: US20160357485A1
Автор: Yu Cai, Yunxiang Wu, Ning Chen, Erich F. Haratsch, Zhengang Chen, CAI YU, WU YUNXIANG, CHEN NING, HARATSCH ERICH F, CHEN ZHENGANG, Cai Yu, Wu Yunxiang, Chen Ning, Haratsch Erich F., Chen Zhengang
Принадлежит: SEAGATE TECHNOLOGY LLC

Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.

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Номер записи: 4
22-08-2017 дата публикации

Systems and methods for latency based data recycling in a solid state memory system

Номер: US0009740432B2
Автор: Yu Cai, Yunxiang Wu, Ning Chen, Erich F. Haratsch, Zhengang Chen, CAI YU, WU YUNXIANG, CHEN NING, HARATSCH ERICH F, CHEN ZHENGANG, Cai Yu, Wu Yunxiang, Chen Ning, Haratsch Erich F., Chen Zhengang
Принадлежит: SEAGATE TECHNOLOGY LLC

Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.

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Номер записи: 5
14-03-2017 дата публикации

Manufacturer self-test for solid-state drives

Номер: US0009595352B2
Автор: Zhengang Chen, David Patmore, Yingji Ju, Erich F. Haratsch, CHEN ZHENGANG, PATMORE DAVID, JU YINGJI, HARATSCH ERICH F, Chen Zhengang, Patmore David, Ju Yingji, Haratsch Erich F.
Принадлежит: Seagate Technology LLC, SEAGATE TECHNOLOGY LLC

An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to process a plurality of I/O requests to blocks of the memory that are not marked as bad on a block list. The controller is configured to track a plurality of bad blocks of the memory. The controller is configured to perform a plurality of scans on the memory. The scans are configured to (a) identify the bad blocks, and (b) mark the bad blocks as bad on the block list.

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Номер записи: 6
29-07-2015 дата публикации

Internet-of-Things platform of full-automatic electric vehicles

Номер: CN104802738A
Автор: Bu Yanzhu, Liu Zhuyuan, Chen Zhengang, He Jincheng, Li Yugang, Hu Yibao, Wang Wei, Wang Qing
Принадлежит:

The invention discloses an internet-of-Things platform of full-automatic electric vehicles. The platform comprises a full-automatic electric vehicle driving system and a cloud calculator device. The driving system comprises a central control device, an electrical control device, a smart phone device and a power supply device. The central control device comprises a signal acquisition module used for detecting electric vehicle signals, an MCU module, a drive circuit module, and a central control communication module. The smart phone device comprises a phone user APP interface, a phone communication module and a phone wireless module which are respectively connected with a phone system module. The cloud calculator device comprises a cloud calculator module and a cloud calculation wireless module which are connected with each other. The cloud calculation wireless module is in wireless connection with a central control wireless module and the phone wireless module. The platform provided by the ...

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Номер записи: 7
09-02-2017 дата публикации

NONVOLATILE MEMORY DATA RECOVERY AFTER POWER FAILURE

Номер: US20170038985A1
Автор: Zhengang Chen, Earl T. Cohen, Alex G. Tang, CHEN ZHENGANG, COHEN EARL T, TANG ALEX G, Chen Zhengang, Cohen Earl T., Tang Alex G.
Принадлежит:

A method for recovery after a power failure. The method generally includes a step of searching at least some of a plurality of pages of a memory to find a first erased page in response to an unsafe power down. A step may move stored data located between a particular word line in the memory that contains the first erased page and a previous word line that is at least two word lines before the particular word line. Another step may write new data starting in a subsequent word line that is the at least two word lines after the particular word line that contains the first erased page. 1. A method for recovery after a power failure , comprising the steps of:searching at least some of a plurality of pages of a memory to find a first erased page in response to an unsafe power down;moving stored data located between a particular word line in the memory that contains the first erased page and a previous word line that is at least two word lines before the particular word line; andwriting new data starting in a subsequent word line that is the at least two word lines after the particular word line that contains the first erased page.2. The method according to claim 1 , wherein the stored data is moved by:reading the stored data;generating corrected data by correcting the stored data; andwriting the corrected data in the memory at or beyond the subsequent word line.3. The method according to claim 1 , further comprising the step of:writing random data between the particular word line and the subsequent word line.4. The method according to claim 3 , wherein the random data is not written in each upper page of the plurality of pages that has a corresponding lower page of the plurality of pages that is programmed.5. The method according to claim 1 , further comprising the step of:restoring a map of the memory using data located prior to the previous word line.6. The method according to claim 1 , further comprising the step of:leaving one or more of the plurality of pages between ...

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Номер записи: 8
13-03-2018 дата публикации

Periodically updating a log likelihood ratio (LLR) table in a flash memory controller

Номер: US0009916906B2
Автор: Yunxiang Wu, Yu Cai, Zhengang Chen, Erich Haratsch, WU YUNXIANG, CAI YU, CHEN ZHENGANG, HARATSCH ERICH, Wu Yunxiang, Cai Yu, Chen Zhengang, Haratsch Erich
Принадлежит: Seagate Technology LLC, SEAGATE TECHNOLOGY LLC

Log likelihood ration (LLR) values that are computed in a flash memory controller during read retries change over time as the number of program-and-erase cycles (PECs) that the flash memory die has been subjected to increases. Therefore, in cases where an LLR table is used to provide pre-defined, fixed LLR values to the error-correcting code (ECC) decoding logic of the controller, decoding success and the resulting BER will degrade over time as the number of PECs to which the die has been subjected increases. In accordance with embodiments, a storage system, a flash memory controller for use in the storage system and method are provided that periodically measure the LLR values and update the LLR table with new LLR values. Periodically measuring the LLR values and updating the LLR table with new LLR values ensures high decoding success and a low BER over the life of the flash memory die.

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Номер записи: 9
14-11-2017 дата публикации

Read threshold voltage adaptation using bit error rates based on decoded data

Номер: US0009818488B2
Автор: Sundararajan Sankaranarayanan, AbdelHakim Salem Alhussien, Zhengang Chen, Erich F. Haratsch, SANKARANARAYANAN SUNDARARAJAN, ALHUSSIEN ABDELHAKIM SALEM, CHEN ZHENGANG, HARATSCH ERICH F, Sankaranarayanan Sundararajan, Alhussien AbdelHakim Salem, Chen Zhengang, Haratsch Erich F.
Принадлежит: Seagate Technology LLC, SEAGATE TECHNOLOGY LLC

A read threshold voltage for a memory is adjusted based on a bit error rate based on decoded data for a plurality of read threshold voltages. The read threshold voltage can be adjusted by reading the memory at a current read threshold voltage to obtain a read value; applying a hard decision decoder to the read value; determining if the hard decision decoder converges for the read value to a converged word; storing bits corresponding to the converged word as reference bits and, if the hard decision decoder converges, (i) computing a bit error rate for the current read threshold voltage based on the reference bits; (ii) adjusting the current read reference voltage to a new read threshold voltage; and (iii) reading the memory at the new read threshold voltage to obtain a new read value, until a threshold is satisfied; and once the threshold is satisfied, selecting the read threshold voltage based on the bit error rates.

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Номер записи: 10
11-04-2017 дата публикации

Internal copy-back with read-verify

Номер: US0009619321B1
Автор: Erich F. Haratsch, Zhengang Chen, Stephen Hanna, Abdelhakim Alhussien, HARATSCH ERICH F, CHEN ZHENGANG, HANNA STEPHEN, ALHUSSIEN ABDELHAKIM, Haratsch Erich F., Chen Zhengang, Hanna Stephen, Alhussien Abdelhakim
Принадлежит: SEAGATE TECHNOLOGY LLC

Systems and methods for internal copy-back with read-verify are described. In one embodiment, a storage device includes a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page. The controller, in conjunction with an error correcting code (ECC) decoder, read-verifies the first SLC page. Read-verifying the first SLC page includes reading the first SLC page to an internal page buffer, decoding the first SLC page read into the internal page buffer, determining a number of errors contained in the first SLC page based at least in part on the decoding, and verifying whether the number of errors contained in the first SLC page satisfies an error threshold. The controller transfers the first SLC page to the TLC page according to a result of read-verifying the first SLC page.

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Номер записи: 11
29-07-2015 дата публикации

Method for displaying remainder range in full-automatic electric vehicle driving system

Номер: CN104802660A
Автор: Bu Yanzhu, Liu Zhuyuan, Chen Zhengang, He Jincheng, Li Yugang, Hu Yibao, Wang Wei, Wang Qing
Принадлежит:

The invention discloses a method for displaying the remainder range in a full-automatic electric vehicle driving system. The method for displaying the remainder range in runtime comprises the following steps: (B10) detecting the battery voltage, riding current, and current riding speed of an electric vehicle in runtime; (B20) calculating the speed according to the previous residual battery capacity and the detected running current of the electric vehicle; (B30) calculating the remainder range according to the running time and the current running speed of the electric vehicle; (B40) performing data transmission and driving a liquid crystal screen of the electric vehicle to display the result of the remainder range in runtime; (B50) calculating the residual battery capacity according to the current voltage and temperature through table look-up; (B60) repeating the step (B10), etc. The method disclosed by the invention is very simple and convenient. The full-automatic electric vehicle driving ...

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Номер записи: 12
25-08-2016 дата публикации

Flash Channel with Selective Decoder Likelihood Dampening

Номер: US20160246674A1
Автор: Zhengang Chen, Yunxiang Wu, AbdelHakim S. Alhussien, Erich F. Haratsch, CHEN ZHENGANG, WU YUNXIANG, ALHUSSIEN ABDELHAKIM S, HARATSCH ERICH F, Chen Zhengang, Wu Yunxiang, Alhussien AbdelHakim S., Haratsch Erich F.
Принадлежит: SEAGATE TECHNOLOGY LLC

An apparatus for reading a flash memory includes a read controller operable to read the flash memory to yield read patterns, a likelihood generator operable to map the read patterns to likelihood values, a decoder operable to decode the likelihood values, a data state storage operable to retrieve the likelihood values for which decoding failed, and a selective dampening controller operable to select at least one dampening candidate from among the likelihood values for which decoding failed, to dampen the likelihood values of the at least one dampening candidate to yield dampened likelihood values, and to provide the dampened likelihood values to the decoder for decoding. 1. A device comprising: a circuit configured to map received data patterns to likelihood values;', 'a decoder configured to decode the likelihood values;', select at least one dampening candidate from the likelihood values that failed decoding;', 'dampen the at least one dampening candidate to generate dampened likelihood values; and, 'a control circuit configured to, 'the decoder configured to decode the dampened likelihood values to output decoded data., 'a digital read channel circuit including2. The device of further comprising the digital read channel includes a memory configured to store the likelihood values.3. The device of further comprising the decoder includes a low density parity check decoder.4. The device of further comprising a retry circuit configured to perform additional recovery operations when a maximum number of retry read operations has been reached.5. The device of further comprising:the decoder configured to determine syndrome weights and provide the syndrome weights to the control circuit; andthe control circuit configured to select the at least one dampening candidate based on the syndrome weights.6. The device of comprising the control circuit further configured to select the at least one dampening candidate when the at least one dampening candidate's syndrome weight is ...

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Номер записи: 13
14-08-2013 дата публикации

Five-level multilateral well seal tool

Номер: CN103244070A
Автор: Zhang Zongren, Yu Lei, Shang Xianfei, Li Min, Deng Xu, Yang Lin, Zhao Zhan, Chen Zhengang, Wu Ning, Li Hu, Zhao Yun, Liu Yanqiang, Kong Dongliang, Gao Yang, Hu Jing, Yan Rentian
Принадлежит:

The invention relates to multilateral well completion tool, in particular to a five-level multilateral well seal tool. A main borehole pre-reserved hole pipe side wall of the tool is provided with a branch hole. A lower connector is connected to the lower end of the main borehole pre-reserved hole pipe. An arc hollow deflector is mounted in the main borehole pre-reserved hole pipe. A multilateral well pre-reserved hole inserting tool is inserted into the main borehole pre-reserved hole pipe. An upper connector is connected to the upper end of the multilateral well pre-reserved hole inserting tool. An axial ditch and an annular ditch are machined on the outer wall where the multilateral well pre-reserved hole inserting tool is closely matched with the main borehole pre-reserved hole pipe. Seal rubber is vulcanized in the axial ditch and the annular ditch. An arc notch is obliquely machined on the upper end side pipe wall of the arc hollow deflector, and the arc pipe wall face at the notch ...

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Номер записи: 14
29-12-2016 дата публикации

SYSTEMS AND METHODS FOR LAST WRITTEN PAGE HANDLING IN A MEMORY DEVICE

Номер: US20160378598A1
Автор: Zhengang Chen, Yu Cai, Erich F. Haratsch, Zhimin Dong, CHEN ZHENGANG, CAI YU, HARATSCH ERICH F, DONG ZHIMIN, Chen Zhengang, Cai Yu, Haratsch Erich F., Dong Zhimin
Принадлежит: SEAGATE TECHNOLOGY LLC

Systems and method relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. In one embodiment, the systems and methods include providing a flash memory circuit including a superset of memory cells, accessing a data set from a group of memory cells using a standard reference value to distinguish bit values in the group of memory cells, and based at least in part on determining that the group of memory cells was a last written group of memory cells, re-accessing a data set from the group of memory cells using a last written reference value to distinguish bit values in the group of memory cells. 1. A system for reading data , the system comprising:a memory read circuit operable to access a data set from a group of memory cells; determine that the group of memory cells was a last written group of memory cells; and', 'based at least in part on determining that the group of memory cells was the last written group of memory cells, cause the memory read circuit to re-access the data set from the group of memory cells., 'a controller circuit operable to2. The system of claim 1 , wherein the memory read circuit accesses the data set using a standard reference value to distinguish bit values in the group of memory cells.3. The system of claim 1 , wherein the memory read circuit re-accesses the data set using a last written reference value to distinguish bit values in the group of memory cells.4. The system of claim 1 , wherein the system further comprises a memory circuit including a superset of memory cells claim 1 , and wherein the group of memory cells is a subset of the superset of memory cells.5. The system of claim 4 , wherein each of the cells of the superset of memory cells are selected from a group consisting of: a single bit memory cell claim 4 , a two-bit memory cell claim 4 , and a three bit memory cell.6. The system of claim 4 , the system further comprising:a last written group memory ...

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Номер записи: 15
03-04-2018 дата публикации

Capacitance coupling parameter estimation in flash memories

Номер: US0009934867B2
Автор: Meysam Asadi, Zhengang Chen, Erich F. Haratsch, ASADI MEYSAM, CHEN ZHENGANG, HARATSCH ERICH F, Asadi Meysam, Chen Zhengang, Haratsch Erich F.
Принадлежит: SEAGATE TECHNOLOGY LLC, Seagate Technology LLC

A method for capacitance coupling parameter estimation is disclosed. Step (A) of the method determines a plurality of voltages in a plurality of memory cells of a nonvolatile memory in response to a plurality of writes to the memory cells. The voltages are determined in each of a plurality of cases related to inter-cell interference. Step (B) generates a system of equations of a capacitance coupling model in response to the voltages from all of the cases. Step (C) generates one or more parameters in response to the system of equations. The parameters include one or more couplings between a perturbed memory cell and a plurality of neighboring memory cells adjacent to the perturbed memory cell.

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Номер записи: 16
06-12-2016 дата публикации

Priori information based post-processing in low-density parity-check code decoders

Номер: US0009513989B2
Автор: Zhengang Chen, Abdel-Hakim S. Alhussien, Erich F. Haratsch, CHEN ZHENGANG, ALHUSSIEN ABDEL-HAKIM S, HARATSCH ERICH F, Chen Zhengang, Alhussien Abdel-Hakim S., Haratsch Erich F.
Принадлежит: Seagate Technology LLC, LSI CORP, SEAGATE TECHNOLOGY LLC, LSI Corporation

A low-density parity-check decoder utilizes information about hard errors in a storage medium to identify bit locations to flip log-likelihood ratios while attempting to decode codewords. The decoder iteratively flips and saturates log-likelihood ratios for bits at hard error locations and re-decodes until a valid codeword is produced. The decoder also identifies variable nodes associated with trapping sets for iterative log-likelihood ratio bit flipping.

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Номер записи: 17
27-03-2018 дата публикации

Systems and methods for last written page handling in a memory device

Номер: US9928139B2
Автор: CHEN ZHENGANG, CAI YU, HARATSCH ERICH F, DONG ZHIMIN, Chen Zhengang, Cai Yu, Haratsch Erich F., Dong Zhimin
Принадлежит: SEAGATE TECHNOLOGY LLC

Systems and method relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. In one embodiment, the systems and methods include providing a flash memory circuit including a superset of memory cells, accessing a data set from a group of memory cells using a standard reference value to distinguish bit values in the group of memory cells, and based at least in part on determining that the group of memory cells was a last written group of memory cells, re-accessing a data set from the group of memory cells using a last written reference value to distinguish bit values in the group of memory cells.

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Номер записи: 18
23-03-2017 дата публикации

Priori Information Based Post-Processing in Low-Density Parity-Check Code Decoders

Номер: US20170085277A1
Автор: Zhengang Chen, Abdel-Hakim S. Alhussien, Erich F. Haratsch, CHEN ZHENGANG, ALHUSSIEN ABDEL-HAKIM S, HARATSCH ERICH F, Chen Zhengang, Alhussien Abdel-Hakim S., Haratsch Erich F.
Принадлежит:

A low-density parity-check decoder utilizes information about hard errors in a storage medium to identify bit locations to flip log-likelihood ratios while attempting to decode codewords. The decoder iteratively flips and saturates log-likelihood ratios for bits at hard error locations and re-decodes until a valid codeword is produced. The decoder also identifies variable nodes associated with trapping sets for iterative log-likelihood ratio bit flipping. 1. A memory storage system , comprising:a processor;memory connected to the processor;a data storage element connected to the processor; andnon-transitory computer executable program code embodied in the memory, configured to execute on the processor, receive a low-density parity-check encoded codeword;', 'identify one or more variable nodes associated with one or more unsatisfied check nodes in the codeword;', 'identify all backtracking nodes also belonging to a trapping set of a low-density parity-check code associated with the codeword;', 'select one of the backtracking nodes based on a probability that each of the one or more variable nodes belongs to a trapping set;', 'flip a log-likelihood ratio associated with the selected backtracking node;', 'saturate a magnitude of the log-likelihood ratio associated with the selected backtracking node; and', 'decode the codeword based on the erased log-likelihood ratios., 'wherein the computer executable program code is configured to2. The memory storage system of claim 1 , wherein the computer executable program code is further configured to:select a hard error location from one or more hard error locations associated with bits in the codeword; anderase a log-likelihood ratio associated with the selected hard error location.3. The memory storage system of claim 2 , wherein the computer executable program code is further configured to receiving a list of one or more hard error locations associated with a bit in the codeword.4. The memory storage system of claim 2 , ...

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Номер записи: 19
25-10-2016 дата публикации

Eliminating or reducing programming errors when programming flash memory cells

Номер: US0009477423B2
Автор: Yu Cai, Yunxiang Wu, Zhengang Chen, Erich Haratsch, CAI YU, WU YUNXIANG, CHEN ZHENGANG, HARATSCH ERICH, Cai Yu, Wu Yunxiang, Chen Zhengang, Haratsch Erich
Принадлежит: Seagate Technology LLC, SEAGATE TECHNOLOGY LLC

Mis-programming of MSB data in flash memory is avoided by maintaining a copy of LSB page data that has been written to flash memory and using the copy rather than the LSB page data read out of the flash cells in conjunction with the MSB values to determine the proper reference voltage ranges to be programmed into the corresponding flash cells. Because the copy is free of errors, using the copy in conjunction with the MSB values to determine the proper reference voltage ranges for the flash cells ensures that mis-programming of the reference voltage ranges will not occur.

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Номер записи: 20
24-10-2012 дата публикации

Transformer structure and assembling method thereof

Номер: CN102751078A
Автор: Chen Zhengang, Huang Kelan, Lai Jifang
Принадлежит:

The invention provides a transformer structure which comprises a winding support, a first coil, an insulation casing, a second coil and a core group. The winding support is provided with a winding portion, a first lateral portion and a second lateral portion are respectively formed on two sides of the winding portion, a plurality of first pins and a plurality of second pins are arranged on the first lateral portions and the second lateral portion respectively, the first coil is wound on the winding portion of the winding support and connected with the first pins, the insulation casing is sleeved outside the first coil, the second coil is wound outside the insulation casing, the second coil is connected with the second pins, and the core group is arranged on the winding support. The invention further provides a transformer assembling method. The transformer structure and the transformer assembling method can be favorable for winding operation of a transformer and can save device investment ...

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Номер записи: 21
11-04-2017 дата публикации

Reduction or elimination of a latency penalty associated with adjusting read thresholds for non-volatile memory

Номер: US0009620202B2
Автор: Zhengang Chen, Erich F. Haratsch, Sundararajan Sankaranarayanan, CHEN ZHENGANG, HARATSCH ERICH F, SANKARANARAYANAN SUNDARARAJAN, Chen Zhengang, Haratsch Erich F., Sankaranarayanan Sundararajan
Принадлежит: Seagate Technology LLC, SEAGATE TECHNOLOGY LLC

Channel information and channel conditions that are determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is adjusted with that precision. This latter approach is advantageous in that a determination that the precision with which the adjustments can be made is relatively low leads to fewer adjustments having to be made during normal read operations.

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Номер записи: 22
27-03-2013 дата публикации

Preparation method of high-purity esomeprazole sodium salt

Номер: CN102993177A
Автор: Zheng Zushuang, Liang Fei, Chen Zhengang
Принадлежит:

The invention provides a refining method of industrial esomeprazole sodium salt. The preparation method is characterized by comprising the following steps: adding esomeprazole sodium salt to methanol, the amount of which is 1.6-4 times of that of the esomeprazole sodium salt; stirring and dissolving the esomeprazole sodium salt under the room temperature; filtering the mixture to obtain a settled solution; cooling the settled solution at 0 DEG C and stirring the settled solution for 2-4 hours; filtering and drying the precipitate; using poor solvents such as acetone, acetonitrile, isopropyl ether and the like for heating and refluxing the mixture for 2-4 hours; cooling the mixture to room temperature, and filtering and drying the mixture. Through the preparation method, high-purity esomeprazole sodium salt can be obtained, single purity content does not exceed 0.1%, the moisture content is smaller than 1%; and the moisture content does not exceed 5% after placing the mixture for 12 hours ...

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Номер записи: 23
25-10-2016 дата публикации

Nonvolatile memory data recovery after power failure

Номер: US0009478271B2
Автор: Zhengang Chen, Earl T. Cohen, Alex G. Tang, CHEN ZHENGANG, COHEN EARL T, TANG ALEX G, Chen Zhengang, Cohen Earl T., Tang Alex G.
Принадлежит: Seagate Technology LLC, SEAGATE TECHNOLOGY LLC

A method for data recovery after a power failure is disclosed. The method may include steps (A) to (D). Step (A) may determine that a last power-down of a solid-state drive was an unsafe power-down. Step (B) may search at least some of a plurality of pages of a nonvolatile memory of the solid-state drive to define an unsafe zone in response to the determining that the last power-down of the solid-state drive was the unsafe power-down. Step (C) may define a pad zone comprising one or more of the pages subsequent to the unsafe zone. Step (D) may resume operation of the solid-state drive by writing new data subsequent to the pad zone.

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Номер записи: 24
28-11-2012 дата публикации

Systems and methods for generating soft information in nand flash

Номер: CN102800351A
Автор: Chen Zhengang, Burd Gregory, Chilappagari Shashi Kiran, Yang Xueshi
Принадлежит:

The invention relates to systems and methods for generating soft information in NAND flash. Systems and methods are provided to generate soft information related to the threshold voltage of a memory cell. A range of threshold voltages for the memory cell is divided into sub-regions of threshold voltage values herein referred to as bins. An output of the memory cell in response to an applied reference signal is measured. The applied reference signal includes a voltage value and position information. A single bin is identified based on the position information of the reference signal. The identified bin is split into more than one bin based on the output of the memory cell and the voltage value of the reference signal. The newly split bins and all the other bins that were not split are assigned new bin indices.

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Номер записи: 25
19-12-2017 дата публикации

Flash channel parameter management with read scrub

Номер: US0009847139B2
Автор: Zhengang Chen, Erich F. Haratsch, CHEN ZHENGANG, HARATSCH ERICH F, Chen Zhengang, Haratsch Erich F.
Принадлежит: SEAGATE TECHNOLOGY LLP, SEAGATE TECHNOLOGY LLC, SEAGATE TECH LLP, Seagate Technology LLC

An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate statistics of a region of a memory circuit as part of a read scrub of the region. The region may have multiple units of data. The memory circuit may be configured to store the data in a nonvolatile condition. The second circuit is generally configured to (i) track one or more parameters of the region based on the statistics, (ii) determine when one or more of the statistics of one or more outliers of the units in the region exceeds a corresponding threshold and (iii) track the parameters of the outlier units separately from the parameters of the region in response to exceeding the corresponding threshold. The parameters generally control one or more reference voltages used to read the data from the region.

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Номер записи: 26
13-09-2016 дата публикации

Bad memory unit detection in a solid state drive

Номер: US0009443616B2
Автор: Zhengang Chen, Earl T. Cohen, Erich F. Haratsch, Jeremy Werner, CHEN ZHENGANG, COHEN EARL T, HARATSCH ERICH F, WERNER JEREMY, Chen Zhengang, Cohen Earl T., Haratsch Erich F., Werner Jeremy
Принадлежит: Seagate Technology LLC, SEAGATE TECHNOLOGY LLC

An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory unit granularities each having a size less than a total size of the memory. The controller is configured to process a plurality of I/O requests to the memory units of the memory that are not marked as bad on a memory unit list. The controller is configured to track a plurality of bad blocks of the memory. The controller is configured to determine which of the memory units to mark as bad based on a test of whether a unit of memory larger than a block of the memory has failed. The test is based on a threshold of the bad blocks in the unit of memory.

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Номер записи: 27
04-10-2016 дата публикации

Data decoder with trapping set flip bit mapper

Номер: US0009459956B2
Автор: Alexander Hubris, Zhengang Chen, AbdelHakim S. Alhussien, YingQuan Wu, HUBRIS ALEXANDER, CHEN ZHENGANG, ALHUSSIEN ABDELHAKIM S, WU YINGQUAN, Hubris Alexander, Chen Zhengang, Alhussien AbdelHakim S., Wu YingQuan
Принадлежит: SEAGATE TECHNOLOGY LLC

A low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages, a check node processor operable to generate the check node to variable node message vectors and to calculate checksums based on the variable node to check node messages, and a convergence detector and bit map generator operable to convergence of the perceived values and to generate at least one bit map that identifies variable nodes that are connected to check nodes with unsatisfied parity checks.

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Номер записи: 28
10-04-2018 дата публикации

Systems and methods for soft decision generation in a solid state memory system

Номер: US0009941901B2
Автор: Zhengang Chen, Yunxiang Wu, Erich F. Haratsch, CHEN ZHENGANG, WU YUNXIANG, HARATSCH ERICH F, Chen Zhengang, Wu Yunxiang, Haratsch Erich F.
Принадлежит: SEAGATE TECHNOLOGY LLC

Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory. A data processing system includes a solid state memory device, a soft data generation circuit operable to receive multiple instances of an element of a read data set accessed from the solid state memory device, and access a scramble compensating extended look up table using the multiple instances of the element to receive corresponding soft data, and a data decoder circuit operable to yield a decoded output from the soft data.

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Номер записи: 29
27-09-2016 дата публикации

Multiple retry reads in a read channel of a memory

Номер: US0009455004B2
Автор: AbdelHakim S. Alhussien, Yunxiang Wu, Sundararajan Sankaranarayanan, Zhengang Chen, Erich F. Haratsch, ALHUSSIEN ABDELHAKIM S, WU YUNXIANG, SANKARANARAYANAN SUNDARARAJAN, CHEN ZHENGANG, HARATSCH ERICH F, Alhussien AbdelHakim S., Wu Yunxiang, Sankaranarayanan Sundararajan, Chen Zhengang, Haratsch Erich F.
Принадлежит: Seagate Technology LLC, SEAGATE TECHNOLOGY LLC

An apparatus having a circuit and a decoder is disclosed. The circuit is configured to adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting the initial reference voltage an amount toward a center of a window and read a codeword from the memory a number of times. The window bounds a sweep of the reference voltages. Each retry of the reads uses a respective reference voltage from a pattern of the reference voltages. The pattern is symmetrically spaced about the initial reference voltage. The pattern fits in the window. The decoder is configured to generate read data by performing an iterative decoding procedure on the codeword based on the reads.

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Номер записи: 30
23-08-2016 дата публикации

Systems and methods for latency based data recycling in a solid state memory system

Номер: US0009424179B2
Автор: Yu Cai, Yunxiang Wu, Ning Chen, Erich F. Haratsch, Zhengang Chen, CAI YU, WU YUNXIANG, CHEN NING, HARATSCH ERICH F, CHEN ZHENGANG, Cai Yu, Wu Yunxiang, Chen Ning, Haratsch Erich F., Chen Zhengang
Принадлежит: SEAGATE TECHNOLOGY LLC

Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.

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Номер записи: 31
29-07-2015 дата публикации

Central processing device for full automatic electric vehicle driving system

Номер: CN104802739A
Автор: Bu Yanzhu, Liu Zhuyuan, Chen Zhengang, He Jincheng, Li Yugang, Hu Yibao, Wang Wei, Wang Qing
Принадлежит:

The invention discloses a central processing device for a full automatic electric vehicle driving system. The driving system comprises the central processing device, an electric control device and a power source device, wherein the central processing device comprises a signal collecting module, an MCU (microprogrammed control unit) module, a driving circuit module and a central control communication module; the signal collecting module is used for detecting a signal of an electric vehicle; the driving circuit module is used for driving a second part of the electric vehicle to run; the signal collecting module, the driving circuit module, the central control communication device and the power source device are respectively accessed into the MCU module. The central processing device has the advantages that the manufacturing cost is reduced, the control is simple and convenient, the maintenance is convenient, the fault rate is low, the installation technology is simple, the production efficiency ...

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Номер записи: 32
22-11-2016 дата публикации

Cell-level statistics collection for detection and decoding in flash memories

Номер: US0009502117B2
Автор: Zhengang Chen, Erich F. Haratsch, CHEN ZHENGANG, HARATSCH ERICH F, Chen Zhengang, Haratsch Erich F.
Принадлежит: Seagate Technology LLC, SEAGATE TECHNOLOGY LLC

Methods and apparatus are provided for collecting cell-level statistics for detection and decoding in flash memories. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits in a page of the flash memory device; and generating cell-level statistics for the flash memory device based on a probability that a data pattern was read from the plurality of bits given that a particular pattern was written to the plurality of bits. The cell-level statistics are optionally generated substantially simultaneously with a reading of the read values, for example, as part of a read scrub process. The cell-level statistics can be used to convert the read values for the plurality of bits to a reliability value for a bit among the plurality of bits.

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Номер записи: 33
04-05-2017 дата публикации

READ THRESHOLD VOLTAGE ADAPTATION USING BIT ERROR RATES BASED ON DECODED DATA

Номер: US20170125111A1
Автор: Sundararajan Sankaranarayanan, AbdelHakim Salem Alhussien, Zhengang Chen, Erich F. Haratsch, SANKARANARAYANAN SUNDARARAJAN, ALHUSSIEN ABDELHAKIM SALEM, CHEN ZHENGANG, HARATSCH ERICH F, Sankaranarayanan Sundararajan, Alhussien AbdelHakim Salem, Chen Zhengang, Haratsch Erich F.
Принадлежит: Seagate Technology LLC

A read threshold voltage for a memory is adjusted based on a bit error rate based on decoded data for a plurality of read threshold voltages. The read threshold voltage can be adjusted by reading the memory at a current read threshold voltage to obtain a read value; applying a hard decision decoder to the read value; determining if the hard decision decoder converges for the read value to a converged word; storing bits corresponding to the converged word as reference bits and, if the hard decision decoder converges, (i) computing a bit error rate for the current read threshold voltage based on the reference bits; (ii) adjusting the current read reference voltage to a new read threshold voltage; and (iii) reading the memory at the new read threshold voltage to obtain a new read value, until a threshold is satisfied; and once the threshold is satisfied, selecting the read threshold voltage based on the bit error rates. 1. A device comprising:a controller configured to adjust a read threshold voltage for a memory based on a bit error rate based on decoded data for a plurality of read threshold voltages.2. The device of claim 1 , wherein the controller adjusts the read threshold voltage by:reading the memory at a current read threshold voltage to obtain a read value;applying a hard decision decoder to the read value;determining if the hard decision decoder converges for the read value to a converged word;storing one or more bits corresponding to the converged word as reference bits; andselecting the read threshold voltage based on one or more bit error rates.3. The device of claim 2 , wherein the controller performs the following steps if the hard decision decoder converges for the read value:computing a bit error rate for the current read threshold voltage based on the reference bits;adjusting the current read reference voltage to a new read threshold voltage;reading the memory at the new read threshold voltage to obtain a new read value;repeating the computing, ...

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Номер записи: 34
24-10-2012 дата публикации

Standby circuit and display device

Номер: CN102752563A
Автор: Chen Zhengang, Lai Qingnan
Принадлежит:

The invention relates to a standby circuit and a display device. The standby circuit is coupled with an electronic device, and standby voltages are output to the electronic device when the electronic device is not started. The standby circuit comprises an illumination module and an energy conversion component, wherein the illumination module receives alternating currents and is driven by the alternating currents to generate light, and the energy conversion component receives the light generated by the illumination module and converts the light into the standby voltages. Accordingly, according to the standby circuit and the display device, designs of traditional standby circuits in televisions are simplified.

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Номер записи: 35
16-08-2016 дата публикации

Preventing programming errors from occurring when programming flash memory cells

Номер: US0009417960B2
Автор: Yu Cai, Yunxiang Wu, Zhengang Chen, Erich Haratsch, CAI YU, WU YUNXIANG, CHEN ZHENGANG, HARATSCH ERICH, Cai Yu, Wu Yunxiang, Chen Zhengang, Haratsch Erich
Принадлежит: Seagate Technology LLC, SEAGATE TECHNOLOGY LLC

Mis-programming of MSB data in flash memory is prevented by using ECC decoding logic on the flash die that error corrects the LSB values prior to the LSB values being used in conjunction with the MSB values to determine the proper reference voltage ranges. Error correcting the LSB page data prior to using it in combination with the MSB page data to determine the reference voltage ranges ensures that the reference voltage ranges will be properly determined and programmed into the flash cells.

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Номер записи: 36
31-07-2013 дата публикации

Inter-cell interference cancellation

Номер: CN103226974A
Автор: Chilappagari Shashi Kiran, Chen Zhengang, Burd Gregory
Принадлежит:

A method includes selecting a first memory cell located along a first bit line and a first word line of a memory array. The method further includes selecting a second memory cell located along (i) the first word line, (ii) a second word line that is adjacent to the first word line, or (iii) a second bit line that is adjacent to the first bit line. A location of the second memory cell is selected based on a predetermined sequence of programming the memory cells. The method further includes writing data in the first memory cell, subsequently writing data in the second memory cell, and reading the first memory cell and the second memory cell. The method further includes detecting one or more states of the second memory causing interference to the first memory cell.

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Номер записи: 37
20-06-2013 дата публикации

Inter-cell interference cancellation

Номер: US20130155776A1
Автор: Gregory Burd, Shashi Kiran CHILAPPAGARI, Zhengang Chen
Принадлежит: MARVELL WORLD TRADE LTD

A method includes selecting a first memory cell located along a first bit line and a first word line of a memory array. The method further includes selecting a second memory cell located along (i) the first word line, (ii) a second word line that is adjacent to the first word line, or (iii) a second bit line that is adjacent to the first bit line. A location of the second memory cell is selected based on a predetermined sequence of programming the memory cells. The method further includes writing data in the first memory cell, subsequently writing data in the second memory cell, and reading the first memory cell and the second memory cell. The method further includes detecting one or more states of the second memory causing interference to the first memory cell.

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Номер записи: 38
11-07-2013 дата публикации

Cell-level statistics collection for detection and decoding in flash memories

Номер: US20130176778A1
Автор: Erich F. Haratsch, Zhengang Chen
Принадлежит: LSI Corp

Methods and apparatus are provided for collecting cell-level statistics for detection and decoding in flash memories. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits in a page of the flash memory device; and generating cell-level statistics for the flash memory device based on a probability that a data pattern was read from the plurality of bits given that a particular pattern was written to the plurality of bits. The cell-level statistics are optionally generated substantially simultaneously with a reading of the read values, for example, as part of a read scrub process. The cell-level statistics can be used to convert the read values for the plurality of bits to a reliability value for a bit among the plurality of bits.

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Номер записи: 39
11-07-2013 дата публикации

INTER-CELL INTERFERENCE CANCELLATION IN FLASH MEMORIES

Номер: US20130176779A1
Автор: Chen Zhengang, Haratsch Erich F.
Принадлежит: LSI Corporation

Inter-cell interference cancellation is provided for flash memory devices. Data from a flash memory device is processed by obtaining one or more quantized threshold voltage values for at least one target cell of the flash memory device; obtaining one or more hard decision read values for at least one aggressor cell of the target cell; determining an aggressor state of the at least one aggressor cell; determining an interference amount based on the aggressor state; determining an adjustment to the quantized threshold voltage values based on the determined interference amount; and adjusting the quantized threshold voltage values based on the determined adjustment. The quantized threshold voltage values for at least one target cell are optionally re-used from a previous soft read retry operation. The adjusted quantized threshold voltage values are optionally used to determine reliability values and are optionally applied to a soft decision decoder and/or a buffer. 1. A method for processing data from a flash memory device , comprising:obtaining one or more quantized threshold voltage values for at least one target cell of said flash memory device;obtaining one or more hard decision read values for at least one aggressor cell of said target cell;determining an aggressor state of said at least one aggressor cell;determining an interference amount based on said aggressor state;determining an adjustment to said one or more quantized threshold voltage values based on said determined interference amount; andadjusting said one or more quantized threshold voltage values based on said determined adjustment.2. The method of claim 1 , wherein said one or more quantized threshold voltage values for at least one target cell are re-used from a previous soft read retry operation.3. The method of claim 1 , wherein said one or more quantized threshold voltage values comprises one or more of hard decision read values obtained by a plurality of read retries of said target cell at a ...

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Номер записи: 40
23-01-2014 дата публикации

FLASH MEMORY READ ERROR RATE REDUCTION

Номер: US20140026003A1
Автор: Chen Zhengang, WU Yunxiang
Принадлежит:

An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate a reference voltage used by a memory circuit in a first read of a set of data and (ii) adjust the reference voltage based on a plurality of parameters to lower an error rate in a second read of the set from the memory circuit. The second circuit may be configured to update the parameters in response to an error correction applied to the set after the first read from the memory circuit. The memory circuit is generally configured to store the data in a nonvolatile condition by adjusting a plurality of threshold voltages. 1. An apparatus comprising:a first circuit configured to (i) generate a reference voltage used by a memory circuit in a first read of a set of data and (ii) adjust said reference voltage based on a plurality of parameters to lower an error rate in a second read of said set from said memory circuit; anda second circuit configured to update said parameters in response to an error correction applied to said set after said first read from said memory circuit, wherein said memory circuit is configured to store said data in a nonvolatile condition by adjusting a plurality of threshold voltages.2. The apparatus according to claim 1 , wherein (i) said memory circuit comprises a flash memory and (ii) said parameters corresponding to said set track (a) a drift of a mean voltage among said threshold voltages in said set and (b) a spread of said threshold voltages about said mean voltage in said set.3. The apparatus according to claim 1 , further comprising a third circuit configured to generate a plurality of statistics as part of said error correction of said set claim 1 , wherein said second circuit updates said parameters based on said statistics.4. The apparatus according to claim 1 , wherein said set is read in response to a read request received from a host.5. The apparatus according to claim 1 , wherein (i) an address space of said ...

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Номер записи: 41
06-02-2014 дата публикации

Mixed granularity higher-level redundancy for non-volatile memory

Номер: US20140040530A1
Автор: Yunxiang Wu, Zhengang Chen
Принадлежит: LSI Corp

Mixed-granularity higher-level redundancy for NVM provides improved higher-level redundancy operation with better error recovery and/or reduced redundancy information overhead. For example, pages of the NVM that are less reliable, such as relatively more prone to errors, are operated in higher-level redundancy modes having relatively more error protection, at a cost of relatively more redundancy information. Concurrently, blocks of the NVM that are more reliable are operated in higher-level redundancy modes having relatively less error protection, at a cost of relatively less redundancy information. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively less error protection, techniques described herein provide better error recovery. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively more error protection, the techniques described herein provide reduced redundancy information overhead.

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Номер записи: 42
06-02-2014 дата публикации

Single-read based soft-decision decoding of non-volatile memory

Номер: US20140040531A1
Автор: Ning Chen, Yunxiang Wu, Zhengang Chen
Принадлежит: LSI Corp

A Solid-State Disk (SSD) controller performs soft-decision decoding with a single read, thus improving performance, power, and/or reliability of a storage sub-system, such as an SSD. In a first aspect, the controller generates soft-decision metrics from channel parameters of a hard decode read, without additional reads and/or array accesses. In a second aspect, the controller performs soft decoding using the generated soft-decision metrics. In a third aspect, the controller generates soft-decision metrics and performs soft decoding with the generated soft-decision metrics when a hard decode read error occurs.

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Номер записи: 43
06-03-2014 дата публикации

FLASH MEMORY READ SCRUB AND CHANNEL TRACKING

Номер: US20140068365A1
Автор: Chen Zhengang, Cohen Earl T.
Принадлежит:

An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) read data from a region of a memory circuit during a read scrub of the region and (ii) generate a plurality of statistics based on (a) the data and (b) one or more bit flips performed during an error correction of the data. The memory circuit is generally configured to store the data in a nonvolatile condition. One or more reference voltages may be used to read the data. The second circuit may be configured to (i) update a plurality of parameters of the region based on the statistics and (ii) compute updated values of the reference voltages based on the parameters. 1. An apparatus comprising:a first circuit configured to (i) read data from a region of a memory circuit during a read scrub of said region and (ii) generate a plurality of statistics based on (a) said data and (b) one or more bit flips performed during an error correction of said data, wherein (a) said memory circuit is configured to store said data in a nonvolatile condition and (b) one or more reference voltages are used to read said data; anda second circuit configured to (i) update a plurality of parameters of said region based on said statistics and (ii) compute updated values of said reference voltages based on said parameters.2. The apparatus according to claim 1 , wherein (i) said memory circuit comprises a flash memory claim 1 , (ii) said memory circuit is configured to store said data by adjusting a plurality of respective charge states in a plurality of memory cells claim 1 , (iii) each of said respective charge states corresponds to one of a plurality of threshold voltages and (iv) said parameters of said region track (a) a drift of one or more mean voltages among said threshold voltages in said region and (b) a respective spread of said threshold voltages about said mean voltages in said region.3. The apparatus according to claim 1 , wherein said first circuit is further ...

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Номер записи: 44
03-04-2014 дата публикации

FLASH CHANNEL PARAMETER MANAGEMENT WITH READ SCRUB

Номер: US20140095110A1
Автор: Chen Zhengang, Haratsch Erich F.
Принадлежит: LSI Corporation

An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate statistics of a region of a memory circuit as part of a read scrub of the region. The region may have multiple units of data. The memory circuit may be configured to store the data in a nonvolatile condition. The second circuit is generally configured to (i) track one or more parameters of the region based on the statistics, (ii) determine when one or more of the statistics of one or more outliers of the units in the region exceeds a corresponding threshold and (iii) track the parameters of the outlier units separately from the parameters of the region in response to exceeding the corresponding threshold. The parameters generally control one or more reference voltages used to read the data from the region. 1. An apparatus comprising:a first circuit configured to generate a plurality of statistics of a region of a memory circuit as part of a read scrub of said region, wherein (i) said region comprises a plurality of units of data and (ii) said memory circuit is configured to store said data in a nonvolatile condition; anda second circuit configured to (i) track one or more parameters of said region based on said statistics, (ii) determine when one or more of said statistics of one or more outliers of said units in said region exceeds a corresponding threshold and (iii) track said parameters of said outlier units separately from said parameters of said region in response to exceeding said corresponding threshold, wherein said parameters control one or more reference voltages used to read said data from said region.2. The apparatus according to claim 1 , wherein (i) said memory circuit comprises a flash memory claim 1 , (ii) said memory circuit is configured to store said data by adjusting a plurality of respective charge states in a plurality of memory cells claim 1 , (iii) each of said respective charge states corresponds to one of a plurality of ...

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Номер записи: 45
14-01-2021 дата публикации

MANAGEMENT OF UNMAPPED ALLOCATION UNITS OF A MEMORY SUB-SYSTEM

Номер: US20210011769A1
Автор: Chen Zhengang, Shen Zhenlei, Xie Tingjun
Принадлежит:

An indication that an allocation unit of a memory sub-system has become unmapped can be received. In response to receiving the indication that the allocation unit of the memory sub-system has become unmapped, the allocation unit can be programmed with a data pattern. Data to be written to the unmapped allocation unit can be received. A write operation can be performed to program the received data at the unmapped allocation unit by using a read voltage that is based on the data pattern. 1. A method comprising:receiving an indication that an allocation unit of a memory sub-system has become unmapped;in response to receiving the indication that the allocation unit of the memory sub-system has become unmapped, programming, by a processing device, the allocation unit with a data pattern;receiving data to be written to the unmapped allocation unit; andperforming a write operation to program the received data at the unmapped allocation unit by using a read voltage that is based on the data pattern2. The method of claim 1 , wherein the performing of the write operation comprises:performing a pre-read operation of the unmapped allocation unit by applying the read voltage to the unmapped allocation unit to retrieve a stored value;comparing the stored value with a value of the received data; anddetermining whether to write the value of the received data at the allocation unit based on the comparison of the stored value with the value of the received data.3. The method of claim 1 , wherein the allocation unit comprises a plurality of memory cells claim 1 , and wherein the programming of the allocation unit with the data pattern corresponds to programming the plurality of memory cells to be at a high voltage state claim 1 , and wherein the read voltage is lower than a voltage level of the high voltage state.4. The method of claim 1 , wherein the allocation unit comprises a plurality of memory cells claim 1 , and wherein the programming of the allocation unit with the data ...

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Номер записи: 46
14-01-2021 дата публикации

SELF-ADAPTIVE READ VOLTAGE ADJUSTMENT USING DIRECTIONAL ERROR STATISTICS FOR MEMORIES WITH TIME-VARYING ERROR RATES

Номер: US20210012856A1
Автор: Chen Zhengang, Xie Tingjun
Принадлежит:

A processing device in a memory system identifies a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range. The processing device further identifies a first set of the plurality of write-to-read delay times at a first end of the first range and determines a first directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times. The processing device determines whether a correspondence between the first directional error rate and the second directional error rate satisfies a first threshold criterion and, responsive to the correspondence between the first directional error rate and the second directional error rate not satisfying the first threshold criterion, modifies the read voltage level associated with the first range. 1. A system comprising:a memory component; and identify a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range;', 'identify a first set of the plurality of write-to-read delay times at a first end of the first range;', 'determine a first directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times ...

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Номер записи: 47
14-01-2021 дата публикации

Self-adaptive read voltage adjustment using boundary error statistics for memories with time-varying error rates

Номер: US20210012857A1
Автор: Tingjun Xie, Zhengang Chen
Принадлежит: Micron Technology Inc

A processing device in a memory system identifies a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range. The processing device further identifies a first set of the plurality of write-to-read delay times at a first end of the first range and a second set of the plurality of write-to-read delay times at a second end of the first range, and determines a first error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second error rate for the memory component corresponding to the second set of the plurality of write-to-read delay times. The processing device determines whether a correspondence between the first error rate and the second error rate satisfies a first threshold criterion, and, responsive to the correspondence between the first error rate and the second error rate not satisfying the first threshold criterion, modifies the read voltage level associated with the first range.

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Номер записи: 48
21-01-2021 дата публикации

PERFORMING A REFRESH OPERATION BASED ON A WRITE TO READ TIME DIFFERENCE

Номер: US20210019084A1
Автор: Chen Zhengang, Xie Tingjun
Принадлежит:

A read operation can be performed to retrieve data of a write unit at a memory sub-system. An indication of a time of the performance of the read operation can be received. Another indication of another time of a performance of a write operation to store the data of the write unit at the memory sub-system can be received. A difference between the time of the performance of the read operation and the another time of the performance of the write operation can be determined. A refresh operation can be performed for the data of the write unit at the memory sub-system based on the difference between the time of the performance of the read operation and the another time of the performance of the write operation 1. A method comprising:performing a read operation to retrieve data of a write unit at a memory sub-system;receiving an indication of a time of the performance of the read operation;receiving another indication of another time of a performance of a write operation that stored the data of the write unit at the memory sub-system;determining a difference between the time of the performance of the read operation and the another time of the performance of the write operation; andperforming, by a processing device, a refresh operation for the data of the write unit at the memory sub-system based on the difference between the time of the performance of the read operation and the another time of the performance of the write operation.2. The method of claim 1 , further comprising:determining whether the difference between the time of the performance of the read operation and the another time of the performance of the write operation satisfies a threshold difference, wherein the refresh operation is performed responsive to the difference satisfying the threshold difference.3. The method of claim 2 , wherein the threshold difference corresponds to an amount of time that has elapsed since the performance of the write operation that stored the data of the write unit at the ...

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Номер записи: 49
17-04-2014 дата публикации

ACCELERATED SOFT READ FOR MULTI-LEVEL CELL NONVOLATILE MEMORIES

Номер: US20140104943A1
Автор: Chen Zhengang, Zhong Hao
Принадлежит: LSI Corporation

A memory device includes a memory array comprising multi-level memory cells, and control circuitry coupled to the memory array. The control circuitry is configured to perform accelerated soft read operations on at least a portion of the memory array. A given one of the accelerated soft read operations directed to a non-upper page of the memory array comprises at least one hard read operation directed to a corresponding upper page of the memory array. For example, the given accelerated soft read operation may comprise a sequence of multiple hard read operations including a hard read operation directed to the non-upper page and one or more hard read operations directed to the corresponding upper page. 1. A memory device comprising:a memory array comprising a plurality of multi-level memory cells; andcontrol circuitry coupled to the memory array and configured to perform accelerated soft read operations on at least a portion of the memory array;wherein a given one of the accelerated soft read operations directed to a non-upper page of the memory array comprises at least one hard read operation directed to a corresponding upper page of the memory array.2. The memory device of wherein the given accelerated soft read operation comprises a sequence of multiple hard read operations including a hard read operation directed to the non-upper page and one or more hard read operations directed to the corresponding upper page.3. The memory device of wherein the hard read operation directed to the corresponding upper page has multiple voltage reference values associated therewith.4. The memory device of wherein the hard read operation directed to the corresponding upper page is performed utilizing a predetermined command established by a vendor of the memory array.5. The memory device of wherein the control circuitry comprises:a soft read accelerator configured to specify a sequence of hard read operations to be performed as part of the given accelerated soft read operation;a soft ...

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Номер записи: 50
21-01-2021 дата публикации

PERFORMING A REFRESH OPERATION BASED ON A CHARACTERISTIC OF A MEMORY SUB-SYSTEM

Номер: US20210020229A1
Автор: Chen Zhengang, JEON SEUNGJUNE, Kwong Charles See Yeung, Shen Zhenlei, Xie Tingjun
Принадлежит:

A refresh operation can be performed at a memory sub-system The refresh operation can performed at a current frequency. A write count associated with the memory sub-system can be received. A determination can be made as to whether the write count associated with the memory sub-system satisfies a write count threshold. In response to determining that the write count associated with the memory sub-system satisfies the write count threshold, the refresh operation can be performed at an increased frequency relative to the current frequency. 1. A method comprising:performing a refresh operation at a memory sub-system, the refresh operation being performed at a current frequency;receiving a write count associated with the memory sub-system;determining, by a processing device, whether the write count associated with the memory sub-system satisfies a write count threshold; andin response to determining that the write count associated with the memory sub-system satisfies the write count threshold, performing the refresh operation at an increased frequency relative to the current frequency.2. The method of claim 1 , further comprising:receiving an operating temperature of the memory sub-system; anddetermining whether the operating temperature of the memory sub-system satisfies an operating temperature threshold, wherein the performing of the refresh operation at the increased frequency is further in response to the operating temperature of the memory sub-system satisfying the operating temperature threshold.3. The method of claim 1 , wherein the refresh operation corresponds to a plurality of write operations to re-write data based on alternating states at one or more units of the memory sub-system.4. The method of claim 1 , wherein determining whether the write count associated with the memory sub-system satisfies the write count threshold comprises:determining whether a number of write operations performed at a particular unit of the memory sub-system satisfies a threshold ...

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Номер записи: 51
22-01-2015 дата публикации

Data Decoder With Trapping Set Flip Bit Mapper

Номер: US20150026536A1
Автор: Alhussien AbdelHakim S., Chen Zhengang, Hubris Alexander, Wu Yingquan
Принадлежит: LSI Corporation

A low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages, a check node processor operable to generate the check node to variable node message vectors and to calculate checksums based on the variable node to check node messages, and a convergence detector and bit map generator operable to convergence of the perceived values and to generate at least one bit map that identifies variable nodes that are connected to check nodes with unsatisfied parity checks. 1. A low density parity check decoder comprising:a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages;a check node processor operable to generate the check node to variable node message vectors and to calculate checksums based on the variable node to check node messages; anda convergence detector and bit map generator operable to detect convergence of the perceived values and to generate at least one bit map that identifies variable nodes that are connected to check nodes with unsatisfied parity checks.2. The decoder of claim 1 , wherein the convergence detector and bit map generator comprises a plurality of barrel shifters used both to detect the convergence and to generate the at least one bit map.3. The decoder of claim 2 , wherein the convergence detector and bit map generator further comprises input selectors operable to select signals derived from hard decisions or signals derived from syndromes.4. The decoder of claim 3 , wherein the convergence detector and bit map generator further comprises a shift memory claim 3 , a plurality of shift selectors claim 3 , and a plurality of reverse shift calculators operable to configure the plurality of barrel shifters claim 3 , wherein the plurality of shift selectors are operable to select shift values during ...

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Номер записи: 52
23-01-2020 дата публикации

WRITE BUFFER MANAGEMENT

Номер: US20200026595A1
Автор: Chen Ning, Chen Zhengang, TAI YING YU, Wang Wei, Wu Cheng Yuan, Zhu Jiangli
Принадлежит:

A read operation to retrieve data from memory component and that bypasses a prior search for the data at a buffer in a read data path associated with the read operation can be performed. Responsive to performing the read operation that bypasses the prior search for the data at the buffer, the data is returned to a host system. 1. A system comprising:a memory component; and receive a request from a host system to read data stored at the memory component;', 'responsive to the request to read the data, perform a read operation to retrieve the data from the memory component;', 'determine whether the data retrieved from the memory component comprises an error that is not correctable; and', 'responsive to determining that the data retrieved from the memory component comprises an error that is not correctable, search for the data at a buffer in a data path associated with the memory component., 'a processing device, coupled to the memory component, the processing device to2. The system of claim 1 , wherein to perform the read operation to retrieve the data from the memory component claim 1 , the processing device is further to:read the data directly from the memory component without a prior performance of an initial search of the buffer to determine whether the data is stored at the buffer.3. The system of claim 1 , the processing device further to:perform one or more error correcting code operations on the data retrieved from the memory component.4. The system of claim 3 , the processing device further to:determine that the data retrieved from the memory component is absent the error in view of the performance of the one or more error correcting code operations; andresponsive to determining that the data retrieved from the memory component is absent the error, return the data retrieved from the memory component to the host system.5. The system of claim 3 , the processing device further to:determine that the one or more error correcting code operations performed on the ...

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Номер записи: 53
23-01-2020 дата публикации

HYBRID ITERATIVE ERROR CORRECTING AND REDUNDANCY DECODING OPERATIONS FOR MEMORY SUB-SYSTEMS

Номер: US20200026602A1
Автор: Chen Zhengang, TAI YING YU, Zhu Jiangli
Принадлежит:

Data stored on each of a set of memory components can be read. Corresponding data stored on a number of the set of memory components that cannot be decoded using an error correction code decoding operation can be identified. A determination can be made whether the number of the set of memory components that include the corresponding data that cannot be decoded from the ECC decoding operation satisfies a threshold condition. Responsive to determining that the number of the set of memory components that include the corresponding data that cannot be decoded from the second ECC decoding operation satisfies the threshold condition, a processing device, can perform a redundancy error correction decoding operation to correct the data stored on each of the set of memory components. 1. A method comprising:reading data stored on each of a plurality of memory components;identifying that corresponding data stored on a number of the plurality of memory components cannot be decoded using an error correction code (ECC) decoding operation;determining whether the number of the plurality of memory components that include the corresponding data that cannot be decoded from the ECC decoding operation satisfies a threshold condition; andresponsive to determining that the number of the plurality of memory components that include the corresponding data that cannot be decoded from the ECC decoding operation satisfies the threshold condition, performing, by a processing device, a redundancy error correction decoding operation to correct the data stored on each of the plurality of memory components.2. The method of claim 1 , further comprising:responsive to determining that the number of the plurality of memory components that include the corresponding data that cannot be decoded from the ECC decoding operation does not satisfy the threshold condition, performing a redundancy reconstruction operation to reconstruct the corresponding data stored at the number of the plurality of memory ...

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Номер записи: 54
28-01-2021 дата публикации

SELECTING READ VOLTAGE USING WRITE TRANSACTION DATA

Номер: US20210026562A1
Автор: Chen Zhengang, Xie Tingjun
Принадлежит:

A system includes a memory component; and a processing device, operatively coupled with the memory component. The processing device is to receive a request to perform a read operation on data stored at a physical address of the memory component and determine whether the data satisfies a threshold criterion pertaining to when the data was written to the physical address. In response to the data satisfying the threshold criterion, the processing device is to perform the read operation on the data stored at the physical address using a first read voltage level, and in response to the data not satisfying the threshold criterion, perform the read operation on the data stored at the physical address using a second read voltage level. 1. A system comprising:a memory component; and receive a read request on data stored at a physical address of the memory component;', 'determine whether the data satisfies a threshold criterion, wherein the threshold criterion is satisfied when the data is written within a threshold period of time;', 'responsive to the data satisfying the threshold criterion, perform a first read operation on the data stored at the physical address using a first read voltage level;', 'responsive to the data not satisfying the threshold criterion, perform the first read operation on the data stored at the physical address using a second read voltage level; and', 'responsive to receiving a read error from performing the first read operation on the data stored at the physical address using the second read voltage level, performing a second read operation on the data stored at the physical address using a third read voltage level., 'a processing device, operatively coupled with the memory component, to2. The system of claim 1 , wherein to determine whether the data satisfies the threshold criterion claim 1 , the processing device is further to:search a write catalog for an entry corresponding to the physical address; anddetermine whether a time stamp associated ...

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Номер записи: 55
08-02-2018 дата публикации

DATA COMPRESSION USING PARTIAL STATISTICS

Номер: US20180039426A1
Автор: Chen Zhengang, Eskandari-Gharnin Bijan, Haratsch Erich F., Xie Hongmei
Принадлежит:

A data storage device includes at least one data storage medium and a controller that is operably coupled to the at least one data storage medium. The controller receives the bit stream in a data storage device and performs a first level of compression on the received bit stream to obtain a symbol frame including a plurality of symbols. The controller encodes an initial portion of the plurality of symbols contained in the symbol frame by a fixed encoding scheme. The controller also collects statistics for the initial portion of the symbol frame. The controller then selects at least one data compression algorithm based on the collected statistics. The controller then performs compression encoding on a remaining portion of the symbol frame with the selected at least one data compression algorithm. 1. A method comprising:receiving a bit stream in a data storage device;performing, by a processor of the data storage device, a first level of compression on the received bit stream to obtain a symbol frame comprising a plurality of symbols;storing less than all of the plurality of symbols in a buffer memory having a pre-defined size;obtaining, by the processor, statistics for the symbols stored in the buffer memory;selecting, by the processor, at least one data compression algorithm based on the obtained statistics; andperforming, by the processor, a second level of compression on all of the plurality of symbols with the selected at least one data compression algorithm.2. The method of and wherein the plurality of symbols comprises different types of symbols.3. The method of and wherein obtaining the statistics for the symbols stored in the buffer memory comprises obtaining frequencies of symbols for each of the different types of symbols.4. The method of and wherein the different types of symbols comprise literals claim 3 , lengths and offsets.5. The method of and wherein selecting the at least one data compression algorithm based on the obtained statistics comprises ...

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Номер записи: 56
13-02-2020 дата публикации

ADJUSTMENT OF A PRE-READ OPERATION ASSOCIATED WITH A WRITE OPERATION

Номер: US20200050383A1
Автор: Chen Zhengang, Shen Zhenlei E., Xie Tingjun, Zhu Jiangli
Принадлежит:

Data can be received at a memory sub-system. A characteristic of the memory sub-system can be identified. A read voltage level can be determined based on the characteristic of the memory sub-system. A read operation can be performed at the memory sub-system based on the read voltage level to retrieve stored data. The received data can be stored at the memory sub-system based on the stored data that was retrieved from the read operation that is based on the read voltage level. 1. A method comprising:receiving first data at a memory sub-system;identifying a characteristic of the memory sub-system, the characteristic being based on an amount of time that has elapsed since a prior write operation has been performed at the memory sub-system;determining, by a processing device, a read voltage level based on the characteristic of the memory sub-system that is based on the amount of time that has elapsed since the prior write operation has been performed at the memory sub-system;performing a read operation at the memory sub-system based on the determined read voltage level to retrieve second data; andstoring the first data at the memory sub-system based on the second data retrieved by the read operation that was based on the determined read voltage level.2. The method of claim 1 , wherein performing the read operation at the memory sub-system based on the determined read voltage level to retrieve the second data comprises:applying the determined read voltage level to one or more memory cells of the memory sub-system, and wherein the determined read voltage level is different than a prior read voltage level applied to another memory cell of the memory sub-system.3. The method of claim 1 , wherein storing the first data at the memory sub-system based on the second data that was retrieved from the read operation comprises:determining whether the first data matches with the second data that was retrieved from the read operation based on the read voltage level; andchanging a ...

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Номер записи: 57
11-03-2021 дата публикации

WRITE BUFFER MANAGEMENT

Номер: US20210073068A1
Автор: Chen Ning, Chen Zhengang, TAI YING YU, Wang Wei, Wu Cheng Yuan, Zhu Jiangli
Принадлежит:

A read operation to retrieve data stored at a memory device is performed. Whether the data retrieved from the memory device includes an error that is not correctable is determined. Responsive to determining that the data retrieved from the memory device comprises the error that is not correctable, a buffer in a data path along which a write operation was performed to write the data at the memory device is searched for the data. 1. A system comprising:a memory device; and performing a read operation to retrieve data stored at the memory device;', 'determining whether the data retrieved from the memory device comprises an error that is not correctable; and', 'responsive to determining that the data retrieved from the memory device comprises the error that is not correctable, searching for the data at a buffer in a data path along which a write operation was performed to write the data at the memory device., 'a processing device, coupled to the memory device, the processing device to perform operations comprising2. The system of claim 1 , wherein performing the read operation to retrieve the data stored at the memory device comprises:reading the data directly from the memory device without a prior performance of an initial search of the buffer to determine whether the data is stored at the buffer.3. The system of claim 1 , wherein the processing device to perform operations further comprising:performing one or more error correcting code operations on the data retrieved from the memory device.4. The system of claim 3 , wherein the processing device to perform operation further comprising:determining that the one or more error correcting code operations performed on the data corrects the error of the data retrieved from the memory device; andresponsive to determining that the one or more error correcting code operations corrects the error, return the corrected data to a host system.5. The system of claim 3 , wherein the processing device to perform operations further ...

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Номер записи: 58
19-03-2015 дата публикации

METHOD OF ERASE STATE HANDLING IN FLASH CHANNEL TRACKING

Номер: US20150082121A1
Автор: CAI Yu, Chen Zhengang, Haratsch Erich F., WU Yunxiang
Принадлежит: LSI Corporation

An apparatus includes a non-volatile memory and a controller. The controller may be configured to track one or more channel parameters of the non-volatile memory. The controller may be further configured to estimate an erase state voltage distribution of the non-volatile memory by selecting one or more parameters of the erase state distribution from a look-up table based upon at least one of the one or more channel parameters. 1. An apparatus comprising:a non-volatile memory; anda controller configured to track one or more channel parameters of said non-volatile memory, wherein said controller estimates an erase state voltage distribution of said non-volatile memory by selecting one or more parameters of the erase state distribution from a look-up table based upon at least one of the one or more channel parameters.2. The apparatus according to claim 1 , wherein said one or more channel parameters comprise a parameter indicating a number of program and erase cycles claim 1 , a parameter indicating a retention time claim 1 , a parameter indicating an amount of write disturb claim 1 , and a parameter indicating an amount of read disturb.3. The apparatus according to claim 1 , wherein said one or more parameters of the erase state distribution comprise pre-determined mean and variance values of the erase state distribution.4. The apparatus according to claim 1 , wherein said one or more parameters of the erase state distribution comprise mean and standard deviation values of the erase state distribution.5. The apparatus according to claim 1 , wherein said look-up table associates a set of parameters of the erase state distribution with each of a plurality of values of said one or more channel parameters.6. The apparatus according to claim 1 , wherein said controller is further configured to perform error correction on data read from said non-volatile memory using a soft decode error correction code.7. The apparatus according to claim 6 , wherein said soft decode error ...

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Номер записи: 59
12-06-2014 дата публикации

SYSTEMS AND METHODS FOR GENERATING SOFT INFORMATION IN NAND FLASH

Номер: US20140160855A1
Автор: Burd Gregory, Chen Zhengang, Chilappagari Shashi Kiran, Yang Xueshi
Принадлежит: MARVELL WORLD TRADE LTD.

Systems and methods are provided to generate soft information related to the threshold voltage of a memory cell. A range of threshold voltages for the memory cell is divided into subregions of threshold voltage values herein referred to as bins. An output of the memory cell in response to an applied reference signal is measured. The applied reference signal includes a voltage value and position information. A single bin is identified based on the position information of the reference signal. The identified bin is split into more than one bin based on the output of the memory cell and the voltage value of the reference signal. The newly split bins and all the other bins that were not split are assigned new bin indices. 120-. (canceled)21. A method for generating soft information for a memory cell , the method comprising:identifying a range of threshold voltages for the memory cell;applying a reference signal to the memory cell;measuring an output of the memory cell in response to applying the reference signal; andsegmenting the range of threshold voltages based on the output of the memory cell and the reference signal.22. The method of claim 21 , wherein the reference signal comprises a voltage value and position information.23. The method of claim 22 , wherein the position information of the reference signal comprises a relative position of the reference signal with respect to a previously applied reference signal.24. The method of claim 22 , wherein the position information of the reference signal comprises a subset of the range of threshold voltages that includes the voltage value of the reference signal.25. The method of claim 21 , wherein segmenting the range of threshold voltages comprises splitting the range of threshold values into at least two bins.26. The method of claim 25 , further comprising assigning the range of threshold voltages and each of the at least two bins respective indices.27. The method of claim 26 , wherein each of the at least two bins are ...

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Номер записи: 60
12-06-2014 дата публикации

FLASH MEMORY READ ERROR RECOVERY WITH SOFT-DECISION DECODE

Номер: US20140164868A1
Автор: Chen Ning, Chen Zhengang, Cohen Earl T., Haratsch Erich F., Werner Jeremy, WU Yunxiang
Принадлежит: LSI Corporation

An apparatus having a circuit and one or more processor is disclosed. The circuit is configured to receive a codeword from a memory. The memory is nonvolatile. The codeword generally has one or more errors. The processors are configured to generate read data by decoding the codeword repeatedly. The decoding includes a soft-decision decoding that uses a plurality of parameters calculated by (i) a first procedure, (ii) a second procedure in response to a plurality of failures of the decoding to converge using the first procedure and (iii) a third procedure in response to another failure of the decoding to converge using the second procedure. 1. An apparatus comprising:a circuit configured to receive a codeword from a memory, wherein (i) said memory is nonvolatile and (ii) said codeword has one or more errors; andone or more processors configured to generate read data by decoding said codeword repeatedly, wherein said decoding comprises a soft-decision decoding that uses a plurality of parameters calculated by (i) a first procedure, (ii) a second procedure in response to a plurality of failures of said decoding to converge using said first procedure and (iii) a third procedure in response to another failure of said decoding to converge using said second procedure.2. The apparatus according to claim 1 , wherein (i) said memory comprise a Flash memory claim 1 , (ii) said soft-decision decoding comprises a soft-decision low-density parity-check decoding claim 1 , (iii) said first procedure is more likely to converge said decoding than said second procedure and (iv) said second procedure is more likely to converge said decoding than said third procedure.3. The apparatus according to claim 1 , wherein said first procedure is configured to (i) change one or more reference voltages in said memory during each of a plurality of reads of said codeword from said memory and (ii) calculate a plurality of log-likelihood ratio values in a log-likelihood ratio table to be used in said ...

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Номер записи: 61
12-06-2014 дата публикации

ERROR CORRECTION CODE RATE MANAGEMENT FOR NONVOLATILE MEMORY

Номер: US20140164880A1
Автор: Alhussien AbdelHakim S., Chen Ning, Chen Zhengang, Cohen Earl T., Haratsch Erich F., Werner Jeremy
Принадлежит: LSI Corporation

An apparatus having an interface and a circuit is shown. The interface is coupled to a memory that is nonvolatile. The circuit is configured to (i) read a plurality of codewords from a block in the memory based on a program/erase count associated with the block, (ii) count a number of iterations used to decode the codewords and (iii) decrease a code rate of an error correction coding used to program the block in response to the number of iterations exceeding a threshold. 1. An apparatus comprising:an interface coupled to a memory that is nonvolatile; anda circuit configured to (i) read a plurality of codewords from a block in said memory based on a program/erase count associated with said block, (ii) count a number of iterations used to decode said codewords and (iii) decrease a code rate of an error correction coding used to program said block in response to said number of iterations exceeding a threshold.2. The apparatus according to claim 1 , wherein said apparatus comprises a solid-state drive.3. The apparatus according to claim 1 , wherein (i) said circuit comprises an iterative decoder configured to decode said codewords and (ii) said iterations are an average number of iterations used by said decode of said codewords.4. The apparatus according to claim 1 , wherein said circuit is further configured to test an ability of said block to store a plurality of test codewords in response to a failure to decode another codeword as read from said block.5. The apparatus according to claim 4 , wherein said circuit is further configured to decrease said code rate in response to said block failing said testing.6. The apparatus according to claim 4 , wherein said circuit is further configured to (i) count a number of other failures to decode said test codewords as read from said block and (ii) decrease said code rate in response to said number of other failures exceeding a test threshold.7. The apparatus according to claim 4 , wherein said circuit is further configured to ...

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Номер записи: 62
12-06-2014 дата публикации

POLICY FOR READ OPERATIONS ADDRESSING ON-THE-FLY DECODING FAILURE IN NON-VOLATILE MEMORY

Номер: US20140164881A1
Автор: Chen Zhengang, Cohen Earl T., Haratsch Erich F., Werner Jeremy
Принадлежит: LSI Corporation

An apparatus includes a non-volatile memory and a controller. The controller is operatively coupled to the non-volatile memory and configured to perform read and write operations on the non-volatile memory using codewords as a unit of read access. The controller includes an error correction engine configured to perform an error correction on codewords read from the non-volatile memory, and, if the error correction fails, to perform one or more retry procedures. The controller is further configured to perform one or more background procedures as a result of the error correction or one or more of the retry procedures not being successful and send an error message as a result of all of the retry procedures not being successful. The one or more background procedures are directed to determining a cause of the error correction failure. 1. An apparatus comprising:a non-volatile memory; anda controller operatively coupled to said non-volatile memory and configured to perform read and write operations on said non-volatile memory using codewords as a unit of read access, said controller comprising an error correction engine,wherein said error correction engine is configured to perform an error correction on codewords read from said non-volatile memory and, if said error correction fails, to perform one or more retry procedures,wherein said controller is further configured to perform one or more background procedures as a result of said error correction or one or more of said retry procedures not being successful and send an error message as a result of all of said one or more retry procedures not being successful, andwherein said one or more background procedures are directed to determining a cause of the error correction failure.2. The apparatus according to claim 1 , wherein the controller is operatively coupled to a host system.3. The apparatus according to claim 1 , wherein:said error correction comprises a hard decision low-density parity-check (HDLDPC) decoding; andsaid ...

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Номер записи: 63
02-04-2015 дата публикации

Flash memory reference voltage detection with tracking of cross-points of cell voltage distributions using histograms

Номер: US20150092489A1
Автор: Abdel-Hakim Alhussien, Erich F. Haratsch, Sundararajan Sankaranarayanan, Yunxiang Wu, Zhengang Chen
Принадлежит: LSI Corp

Cross-points of flash memory cell voltage distributions are determined by reading data from a portion of the flash memory two or more times using two or more different candidate reference voltages and determining corresponding decision patterns. The frequency of occurrence of the decision patterns in the data read from the flash memory is used to conceptually construct a histogram. The histogram is used to estimate the cross-points. Employing decision patterns enables multiple cross-point voltages to be determined with a minimum of read operations.

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Номер записи: 64
25-03-2021 дата публикации

SELF-ADAPTIVE READ VOLTAGE ADJUSTMENT USING DIRECTIONAL ERROR STATISTICS FOR MEMORIES WITH TIME-VARYING ERROR RATES

Номер: US20210090683A1
Автор: Chen Zhengang, Xie Tingjun
Принадлежит:

A processing device in a memory system determines a first error rate associated with a first number of bits written to the memory device as a first logical value and erroneously read as a second logical value and corresponding to a first range of a plurality of write-to-read delay times and a second error rate associated with a second number of bits written to the memory device as the second logical value and erroneously read as the first logical value and corresponding to the first range of the plurality of write-to-read delay times. The processing device further determines whether a ratio of the first error rate to the second error rate satisfies a first threshold criterion, and responsive to the ratio of the first error rate to the second error rate not satisfying the first threshold criterion, adjusts a read voltage level associated with the first range. 1. A system comprising:a memory device; and determining a first error rate associated with a first number of bits written to the memory device as a first logical value and erroneously read as a second logical value and corresponding to a first range of a plurality of write-to-read delay times and a second error rate associated with a second number of bits written to the memory device as the second logical value and erroneously read as the first logical value and corresponding to the first range of the plurality of write-to-read delay times;', 'determining whether a ratio of the first error rate to the second error rate satisfies a first threshold criterion; and', 'responsive to the ratio of the first error rate to the second error rate not satisfying the first threshold criterion, adjusting a read voltage level associated with the first range., 'a processing device, operatively coupled with the memory device, to perform operations comprising2. The system of claim 1 , wherein determining the first error rate comprises:monitoring read operations performed on segments of the memory device having write-to-read delay ...

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Номер записи: 65
16-04-2015 дата публикации

Inter-cell interference cancellation

Номер: US20150103594A1
Автор: Gregory Burd, Shashi Kiran CHILAPPAGARI, Zhengang Chen
Принадлежит: MARVELL WORLD TRADE LTD

A read module reads memory cells along a first word line by applying a plurality of threshold voltages to the first word line; generates first information about a first memory cell located along the first word line and a first bit line indicating a location of a threshold voltage distribution of the first memory cell relative to the plurality of threshold voltages; reads a second memory cell located along the first word line, a second word line near the first word line, or a second bit line near the first bit line; and generates second information about the second memory cell indicating a state of the second memory cell causing interference to the first memory cell. A compensation module compensates for the interference by assigning one or more of a log-likelihood ratio and a hard decision to the first memory cells based on the first information and the second information.

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Номер записи: 66
13-04-2017 дата публикации

INTERNAL COPY-BACK WITH READ-VERIFY

Номер: US20170102991A1
Автор: Alhussien Abdelhakim, Chen Zhengang, Hanna Stephen, Haratsch Erich F.
Принадлежит: SEAGATE TECHNOLOGY LLC

Systems and methods for internal copy-back with read-verify are described. In one embodiment, a storage device includes a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page. The controller, in conjunction with an error correcting code (ECC) decoder, read-verifies the first SLC page. Read-verifying the first SLC page includes reading the first SLC page to an internal page buffer, decoding the first SLC page read into the internal page buffer, determining a number of errors contained in the first SLC page based at least in part on the decoding, and verifying whether the number of errors contained in the first SLC page satisfies an error threshold. The controller transfers the first SLC page to the TLC page according to a result of read-verifying the first SLC page. 1. A storage device , the storage device comprising:a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page; reading the first SLC page to an internal page buffer;', 'decoding the first SLC page read into the internal page buffer;', 'determining a number of errors contained in the first SLC page based at least in part on the decoding; and', 'verifying whether the number of errors contained in the first SLC page satisfies an error threshold; and, 'the controller, in conjunction with an error correcting code (ECC) decoder, to read-verify the first SLC page, read-verifying the first SLC page comprisingthe controller to transfer the first SLC page to the TLC page according to a result of read-verifying the first SLC page.2. The storage device of claim 1 , comprising:upon detecting no errors in the first SLC page, the controller to program a word line of the TLC page with the first SLC page read into the internal page buffer.3. The storage device of claim 1 , comprising:upon detecting errors in the first SLC page ...

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Номер записи: 67
02-06-2022 дата публикации

METADATA AWARE COPYBACK FOR MEMORY DEVICES

Номер: US20220171703A1
Автор: Chen Zhengang, Huang Jianmin
Принадлежит:

Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, in order to update the meta-data, the meta-data and host-data are separated and the only the meta-data is sent to the controller to be updated during a modified internal copyback operation. The host-data is not transmitted to the controller. While sending the meta-data utilizes resources of the communication link between the memory dies and the controller, it uses much fewer resources than if the host-data were also transmitted. 1. A method comprising: receiving scrambled meta-data without its corresponding host-data from a memory die, the scrambled meta-data stored in a first location on the memory die of the memory device with the corresponding host-data;', 'unscrambling the scrambled meta-data to produce unscrambled meta-data;', 'updating the unscrambled meta-data to produce updated meta-data;', 'scrambling the updated meta-data to produce scrambled updated meta-data; and', 'sending the scrambled updated meta-data to the memory die, the scrambled updated meta-data combined by the memory die with host-data and written to a second location on the memory die., 'at a memory controller of a memory device2. The method of claim 1 , further comprising:send a copyback command instructing the memory die to copy the host-data between the first location on the memory die and the second location on the memory die; andwherein the receiving the scrambled meta-data is responsive to the copyback command.3. The method of claim 1 , further comprising:decoding the scrambled meta-data prior to unscrambling the scrambled meta-data; andencoding the updated meta-data prior to scrambling the updated meta-data.4. The method of claim 3 , wherein encoding the updated meta-data comprises using an Error Correction Encoder.5. The method of claim 1 , wherein unscrambling ...

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Номер записи: 68
23-04-2015 дата публикации

Systems and Methods for Latency Based Data Recycling in a Solid State Memory System

Номер: US20150113205A1
Автор: CAI Yu, Chen Ning, Chen Zhengang, Haratsch Erich F., WU Yunxiang
Принадлежит: LSI Corporation

Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. 1. A data processing system , the system comprising:a memory device operable to maintain a data set;a data decoder circuit operable to apply one or more iterations of a data decoding algorithm to the data set accessed from the memory device to yield a decoded output, and to provide an iteration count indicating a number of iterations that the data decoding algorithm was applied to the data set; anda recycle control circuit operable to recycle a read data corresponding to the data set, wherein the recycle is triggered based at least in part on the iteration count.2. The data processing system of claim 1 , wherein the data decoding algorithm is a low density parity check decoding algorithm.3. The data processing system of claim 1 , wherein the recycle control circuit comprises a comparator circuit operable to compare the iteration count with a threshold level.4. The data processing system of claim 3 , wherein the threshold level is programmable.5. The data processing system of claim 1 , wherein the system further comprises: access the data set from the memory device; and', 'calculate a frequency of access corresponding to the data set; and, 'a memory access circuit operable towherein the recycle is triggered based at least in part on the iteration count and the frequency of access.6. The data processing system of claim 5 , wherein the recycle control circuit comprises a comparator circuit operable to compare the iteration count with one of a first threshold level or a second threshold level.7. The data processing system of claim 6 , wherein the first threshold level is selected when the frequency of access exceeds a third threshold level claim 6 , and the second threshold level is selected when the frequency of access is less than the third threshold level.8. The data processing system of claim 7 , wherein at least one ...

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Номер записи: 69
23-04-2015 дата публикации

GENERATING SOFT DECODING INFORMATION FOR FLASH MEMORY ERROR CORRECTION USING HARD DECISION PATTERNS

Номер: US20150113354A1
Автор: Chen Zhengang, Haratsch Erich F., WU Yunxiang
Принадлежит: LSI Corporation

A flash memory controller having soft-decoding error correcting code (ECC) logic generates log likelihood ratio or similar ECC decoder soft input information from decision patterns obtained from reading data from the same portion of flash memory two or more times. Each decision pattern corresponds to a voltage region bordering one of the reference voltages. Each decision pattern represents a combination of flash memory bit value decisions for a cell voltage within the voltage region corresponding to the decision pattern when a corresponding combination of the reference voltages are used to read the cell. Numerical values are then computed in response to combinations of the flash memory bit value decisions represented by the decision patterns. The numerical values are provided to the soft-decoding ECC logic to serve as soft input information. 1. A method for operation of a flash memory controller having soft-decoding error correcting code logic , comprising:reading data from a portion of a flash memory a plurality of times using a plurality of different reference voltages, each time reading data from the portion of the flash memory using a different reference voltage from all other times, the plurality of different reference voltages distributed over a voltage range, the voltage range substantially centered on an estimated mid-point between a pair of adjacent target cell voltages;determining a plurality of decision patterns, each decision pattern corresponding to a voltage region bordering one of the reference voltages, each decision pattern representing a combination of flash memory decision values for a cell voltage within the voltage region corresponding to the decision pattern when a corresponding combination of the reference voltages are used to read the cell;generating a plurality of numerical values, each numerical value computed in response to the combination of the flash memory decision values represented by each decision pattern; andinputting the plurality ...

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Номер записи: 70
28-04-2016 дата публикации

MULTIPLE RETRY READS IN A READ CHANNEL OF A MEMORY

Номер: US20160118093A1
Автор: Alhussien AbdelHakim S., Chen Zhengang, Haratsch Erich F., Sankaranarayanan Sundararajan, WU Yunxiang
Принадлежит:

An apparatus having a circuit and a decoder is disclosed. The circuit is configured to adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting the initial reference voltage an amount toward a center of a window and read a codeword from the memory a number of times. The window bounds a sweep of the reference voltages. Each retry of the reads uses a respective reference voltage from a pattern of the reference voltages. The pattern is symmetrically spaced about the initial reference voltage. The pattern fits in the window. The decoder is configured to generate read data by performing an iterative decoding procedure on the codeword based on the reads. 1. An apparatus comprising:an interface configured to process a plurality of read/write operations to/from a memory; anda control circuit configured to shift an initial read voltage in the memory by an amount toward a center of a read voltage sweep range of the memory in response to a predetermined condition being met, read a codeword from the memory a number of times using a pattern that comprises a plurality of read voltages spaced on both sides of the initial read voltage as shifted, and generate read data by a decode of the codeword based on the number of reads.2. The apparatus according to claim 1 , wherein the decode uses a plurality of soft log likelihood ratio values that are based on the number of times that the codeword is read.3. The apparatus according to claim 2 , wherein the plurality of soft log likelihood ratio values comprises a plurality of first log likelihood ratio values when the predetermined condition is not met and a plurality of second log likelihood ratio values when the predetermined condition is met.4. The apparatus according to claim 2 , wherein the control circuit is further configured to generate the plurality of soft log likelihood ratio values by adjusting a plurality of original log likelihood ratio values based on the amount that the initial ...

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Номер записи: 71
07-05-2015 дата публикации

REDUCTION OR ELIMINATION OF A LATENCY PENALTY ASSOCIATED WITH ADJUSTING READ THRESHOLDS FOR NON-VOLATILE MEMORY

Номер: US20150127883A1
Автор: Chen Zhengang, Haratsch Erich F., Sankaranarayanan Sundararajan
Принадлежит: LSI Corporation

Channel information and channel conditions that are determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is adjusted with that precision. This latter approach is advantageous in that a determination that the precision with which the adjustments can be made is relatively low leads to fewer adjustments having to be made during normal read operations. 1. A storage system comprising:a nonvolatile memory (NVM) comprising at least a first flash memory die having a plurality of memory cells; and{'sub': READ', 'READ', {'sub2': '—'}, 'CURRENT', 'READ', {'sub2': '—'}, 'LAST', 'READ', {'sub2': '—'}, 'LAST', 'READ', {'sub2': '—'}, 'CURRENT, 'a solid-state disk (SSD) controller in communication with the NVM memory via a first interface (I/F) that interfaces the NVM with the SSD controller, the SSD controller being configured to execute read commands in order to read the memory cells, wherein the SSD controller uses a read reference voltage, V, to read the memory cells, and wherein the SSD controller is configured to determine a difference between a value of a current read reference voltage, V, to be used during a current read operation for reading a group of memory cells of said at least a first flash memory die and a value of a last read reference voltage, V, that was used during a previous read operation to ...

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Номер записи: 72
21-05-2015 дата публикации

Systems and Methods for Soft Decision Generation in a Solid State Memory System

Номер: US20150143202A1
Автор: Erich F. Haratsch, Yunxiang Wu, Zhengang Chen
Принадлежит: LSI Corp

Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory.

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Номер записи: 73
28-05-2015 дата публикации

ELIMINATING OR REDUCING PROGRAMMING ERRORS WHEN PROGRAMMING FLASH MEMORY CELLS

Номер: US20150149698A1
Автор: CAI Yu, Chen Zhengang, HARATSCH Erich, WU Yunxiang
Принадлежит: LSI Corporation

Mis-programming of MSB data in flash memory is avoided by maintaining a copy of LSB page data that has been written to flash memory and using the copy rather than the LSB page data read out of the flash cells in conjunction with the MSB values to determine the proper reference voltage ranges to be programmed into the corresponding flash cells. Because the copy is free of errors, using the copy in conjunction with the MSB values to determine the proper reference voltage ranges for the flash cells ensures that mis-programming of the reference voltage ranges will not occur. 1. A data storage system comprising:a host system, the host system including at least one host processor that controls operations of the host system and a host memory device that stores data and computer instructions that are used by the host processor; anda solid state drive (SSD) device interfaced with the host system, the SSD device including an SSD controller and at least one nonvolatile memory (NVM), the NVM including at least a first flash memory having a plurality of flash cells for storing data, the first flash memory including reference voltage determination logic, the SSD controller including at least one SSD processor and at least one buffer, the SSD controller receiving write data from the host system to be programmed into flash cells of the NVM, the SSD controller buffering the write data in the buffer prior to programming the write data into the flash cells, the buffered write data comprising at least a first most significant bit (MSB) page of data and at least a first least significant bit (LSB) page of data, the SSD controller sending the first LSB page of data to the first flash memory and maintaining a copy of the first LSB page of data in a temporary memory, and wherein subsequent to sending the first LSB page of data to the first flash memory the SSD controller sends the copy of the first LSB page of data and sends the first MSB page of data to the first flash memory, and wherein ...

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Номер записи: 74
28-05-2015 дата публикации

DECODING WITH LOG LIKELIHOOD RATIOS STORED IN A CONTROLLER

Номер: US20150149856A1
Автор: Chen Zhengang, Haratsch Erich F., WU Yunxiang
Принадлежит: LSI Corporation

An apparatus having one or more lookup tables and a decoder is disclosed. The lookup tables are configured to store a plurality of sets of values of log likelihood ratios. The decoder is configured to (i) receive a codeword read from a memory, (ii) receive an initial one of the sets from the lookup tables and (iii) generate read data by decoding the codeword based on the values. 1. An apparatus comprising:one or more lookup tables configured to store a plurality of sets of values of log likelihood ratios; anda decoder configured to (i) receive a codeword read from a memory, (ii) receive an initial one of said sets from said lookup tables and (iii) generate read data by decoding said codeword based on said values.2. The apparatus according to claim 1 , wherein another of said sets is read from said lookup tables in response to said decoding failing to converge with said initial set.3. The apparatus according to claim 1 , wherein said codeword is reread from said memory in response to said decoding failing to converge with an initial group of said sets.4. The apparatus according to claim 3 , wherein another of said sets in an additional group of said sets is received from said lookup tables in response to said rereading of said codeword.5. The apparatus according to claim 3 , wherein a plurality of patterns are generated based on said reading of said codeword and said rereading of said codeword.6. The apparatus according to claim 5 , wherein said values are selected from said tables to use in said decoding of said codeword based on said patterns.7. The apparatus according to claim 1 , wherein a group of said sets has (i) a normal set of said values and (b) a plurality of compensated sets of said values.8. The apparatus according to claim 7 , wherein (i) each of said sets is divided into a plurality of pages and (ii) each page is divided into a plurality of said values claim 7 , one of said values corresponding to each of a plurality of possible patterns created by a ...

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Номер записи: 75
28-05-2015 дата публикации

Flash Channel With Selective Decoder Likelihood Dampening

Номер: US20150149871A1
Автор: Alhussien AbdelHakim S., Chen Zhengang, Haratsch Erich F., WU Yunxiang
Принадлежит: LSI Corporation

An apparatus for reading a flash memory includes a read controller operable to read the flash memory to yield read patterns, a likelihood generator operable to map the read patterns to likelihood values, a decoder operable to decode the likelihood values, a data state storage operable to retrieve the likelihood values for which decoding failed, and a selective dampening controller operable to select at least one dampening candidate from among the likelihood values for which decoding failed, to dampen the likelihood values of the at least one dampening candidate to yield dampened likelihood values, and to provide the dampened likelihood values to the decoder for decoding. 1. An apparatus for reading a flash memory , comprising:a read controller operable to read the flash memory to yield read patterns;a likelihood generator operable to map the read patterns to likelihood values;a decoder operable to decode the likelihood values;a data state storage device operable to retrieve the likelihood values for which decoding failed; anda selective dampening controller operable to select at least one dampening candidate from among the likelihood values for which decoding failed, to dampen the likelihood values of the at least one dampening candidate to yield dampened likelihood values, and to provide the dampened likelihood values to the decoder for decoding.2. The apparatus of claim 1 , wherein the likelihood values comprise log likelihood ratios.3. The apparatus of claim 1 , wherein the decoder comprises a low density parity check decoder.4. The apparatus of claim 1 , wherein the data state storage device is operable to store lookup tables used to map the read patterns to the likelihood values.5. The apparatus of claim 1 , wherein the data state storage device is operable to store syndrome weights from the decoder for the likelihood values for which decoding failed.6. The apparatus of claim 5 , wherein the selective dampening controller is operable to select the at least one ...

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Номер записи: 76
04-06-2015 дата публикации

MIXED GRANULARITY HIGHER-LEVEL REDUNDANCY FOR NON-VOLATILE MEMORY

Номер: US20150154070A1
Автор: Chen Zhengang, WU Yunxiang
Принадлежит:

Mixed-granularity higher-level redundancy for NVM provides improved higher-level redundancy operation with better error recovery and/or reduced redundancy information overhead. For example, pages of the NVM that are less reliable, such as relatively more prone to errors, are operated in higher-level redundancy modes having relatively more error protection, at a cost of relatively more redundancy information. Concurrently, blocks of the NVM that are more reliable are operated in higher-level redundancy modes having relatively less error protection, at a cost of relatively less redundancy information. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively less error protection, techniques described herein provide better error recovery. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively more error protection, the techniques described herein provide reduced redundancy information overhead. 1operating in a first higher-level redundancy mode comprising storing M information portions in M respective areas of memory, each of the M respective areas being a same first size;operating in a second higher-level redundancy mode comprising storing N information portions in N respective areas of the memory, each of the N respective areas being a same second size;wherein the M information portions comprise respective M-J data information portions and respective J redundant information portions computed to protect the respective M-J data information portions;wherein the N information portions comprise respective N-K data information portions and respective K redundant information portions computed to protect the respective N-K data information portions;wherein each of the M respective areas and the N respective areas are non-overlapping areas of the memory;wherein the first size is different than the second size; andwherein each of the M respective areas is in a ...

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Номер записи: 77
15-09-2022 дата публикации

ITERATIVE ERROR CORRECTION WITH ADJUSTABLE PARAMETERS AFTER A THRESHOLD NUMBER OF ITERATIONS

Номер: US20220294473A1
Автор: Chen Zhengang, Gad Eyal En, Parthasarathy Sivagnanam, Weinberg Yoav
Принадлежит:

A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after a threshold number of iterations is performed. 1. A system comprising:a memory device; and receiving a request to read data from the memory device; and', 'in response to receiving the request, performing an iterative error correction process on the data, wherein the iterative error correction process uses a first criterion for a first set of a threshold number of iterations, and uses a second criterion based at least partially on a previous iteration for a second set of iterations after the threshold number of iterations is performed., 'a processing device, operatively coupled with the memory device, to perform operations comprising2. The system of claim 1 , wherein performing the iterative error correction process comprises:determining an energy level associated with each bit of the data;determining a maximum energy level associated with any one bit of the data;determining whether a current iteration of the error correction process is a first iteration; andresponsive to the current iteration being the first iteration, flipping any bits in the data having an energy level that satisfies an energy threshold condition.3. The system of claim 2 , wherein performing the iterative error correction process further comprises:responsive to the current iteration not being the first iteration, determining ...

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Номер записи: 78
11-06-2015 дата публикации

MULTIPLE RETRY READS IN A READ CHANNEL OF A MEMORY

Номер: US20150162057A1
Автор: Alhussien AbdelHakim S., Chen Zhengang, Haratsch Erich F., Sankaranarayanan Sundararajan, WU Yunxiang
Принадлежит: LSI Corporation

An apparatus having a circuit and a decoder is disclosed. The circuit is configured to (i) adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting the initial reference voltage an amount toward a center of a window and (ii) read a codeword from the memory a number of times. The window bounds a sweep of the reference voltages. Each retry of the reads uses a respective reference voltage from a pattern of the reference voltages. The pattern is symmetrically spaced about the initial reference voltage. The pattern fits in the window. The decoder is configured to generate read data by performing an iterative decoding procedure on the codeword based on the reads. 1. An apparatus comprising:a circuit configured to (i) adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting said initial reference voltage an amount toward a center of a window and (ii) read a codeword from said memory a number of times, wherein (a) said window bounds a sweep of said reference voltages, (b) each retry of said reads uses a respective reference voltage from a pattern of said reference voltages, (c) said pattern is symmetrically spaced about said initial reference voltage and (d) said pattern fits in said window; anda decoder configured to generate read data by performing an iterative decoding procedure on said codeword based on said reads.2. The apparatus according to claim 1 , wherein (i) said decoder is further configured to use a plurality of soft values of log likelihood ratios in said iterative decoding procedure and (ii) said soft values are based on said number of said reads.3. The apparatus according to claim 2 , wherein (i) a plurality of original values and a plurality of modified values are stored in one or more lookup tables claim 2 , (ii) said original values are used as said soft values when said initial reference voltage is unshifted and (iii) said modified values are use as said soft values ...

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Номер записи: 79
28-08-2014 дата публикации

REDUCED COMPLEXITY RELIABILITY COMPUTATIONS FOR FLASH MEMORIES

Номер: US20140241056A1
Автор: Chen Zhengang, WU Yunxiang
Принадлежит: LSI Corporation

Methods and apparatus are provided for computing reliability values, such as log likelihood ratios (LLRs), with reduced complexity for flash memory devices. Data from a flash memory device that stores M bits per cell using 2̂M possible states is processed by obtaining at least two soft read voltage values corresponding to two reference voltages Vand V, wherein the two reference voltages Vand Vare between two adjacent states of the 2̂M possible states; and converting the at least two soft read voltage values to a log likelihood ratio for a region between the two reference voltages Vand Vusing probability density functions only for the two adjacent states. The soft read voltage values comprise, for example, hard decision read values obtained by a plurality of read retries of a given cell at a plurality of reference voltages and/or soft values obtained from the flash memory device. 1. A method for processing data from a flash memory device that stores M bits per cell using 2̂M possible states , comprising:{'sub': 0', '1', '0', '1, 'obtaining at least two soft read voltage values corresponding to two reference voltages Vand V, wherein said two reference voltages Vand Vare between two adjacent states of said 2̂M possible states; and'}{'sub': 0', '1, 'converting said at least two soft read voltage values to a log likelihood ratio for a region between said two reference voltages Vand Vusing probability density functions only for said two adjacent states.'}2. The method of claim 1 , wherein said probability density functions for each of said two adjacent states Sand Scan be expressed as f(ν;μ claim 1 ,σ) and f(ν;μ claim 1 ,σ) claim 1 , where said probability density functions are defined by a mean μand a variance σand ν is the soft read voltage.6. The method of claim 1 , wherein said soft read voltage values comprise one or more of hard decision read values obtained by a plurality of read retries of a given cell at a plurality of reference voltages and soft values obtained ...

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Номер записи: 80
07-06-2018 дата публикации

Periodically Updating a Log Likelihood Ratio (LLR) Table in a Flash Memory Controller

Номер: US20180158536A1
Автор: CAI Yu, Chen Zhengang, HARATSCH Erich, WU Yunxiang
Принадлежит:

Log likelihood ratio (LLR) values that are computed in a flash memory controller during read retries change over time as the number of program-and-erase cycles (PECs) that the flash memory die has been subjected to increases. Therefore, in cases where an LLR table is used to provide pre-defined, fixed LLR values to the error-correcting code (ECC) decoding logic of the controller, decoding success and the resulting BER will degrade over time as the number of PECs to which the die has been subjected increases. In accordance with embodiments, a storage system, a flash memory controller for use in the storage system and method are provided that periodically measure the LLR values and update the LLR table with new LLR values. Periodically measuring the LLR values and updating the LLR table with new LLR values ensures high decoding success and a low BER over the life of the flash memory die. 1. A data storage system , comprising:a flash memory including a set of cells for storing data in multiple storage states; identify a select portion of the set of cells;', 'write a known pattern of the multiple storage states to the select portion of the set of cells;', 'read the select portion of the set of cells k times with k different reference voltages, respectively, where k is a positive integer greater than two;', 'record a respective decision pattern responsive to the storage state read while applying the k different reference voltages, where each decision pattern corresponds to a decision region bordering at least one of the k different reference voltages;', 'generate a new LLR value responsive to the frequency of occurrence of the respective decision patterns; and', 'replace a respective value in the LLR table with the new LLR value., 'a memory controller communicatively coupled to the flash memory, the memory controller including a processor, a log likelihood ratio (LLR) table including values for use when decoding data read from the flash memory, and a LLR measurement and ...

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Номер записи: 81
25-06-2015 дата публикации

PREVENTING PROGRAMMING ERRORS FROM OCCURRING WHEN PROGRAMMING FLASH MEMORY CELLS

Номер: US20150178152A1
Автор: CAI Yu, Chen Zhengang, HARATSCH Erich, WU Yunxiang
Принадлежит: LSI Corporation

Mis-programming of MSB data in flash memory is prevented by using ECC decoding logic on the flash die that error corrects the LSB values prior to the LSB values being used in conjunction with the MSB values to determine the proper reference voltage ranges. Error correcting the LSB page data prior to using it in combination with the MSB page data to determine the reference voltage ranges ensures that the reference voltage ranges will be properly determined and programmed into the flash cells. 1. A data storage system comprising:a host system; anda solid state drive (SSD) interfaced with the host system, the SSD including an SSD controller and at least one nonvolatile memory (NVM), the SSD controller including at least one SSD processor, a tier 1 error-correcting code (ECC) encoder/decoder, and a tier 2 ECC encoder/decoder, wherein the NVM includes at least a first flash memory having a plurality of flash memory cells, reference voltage range determination logic and tier 2 ECC decoding logic, the SSD controller receiving write data from the host system to be programmed into flash cells of the NVM, the write data comprising at least a first most significant bit (MSB) page of data and at least a first least significant bit (LSB) page of data, the tier 1 ECC encoder/decoder performing tier 1 ECC encoding of the first LSB page of data to produce a tier 1-encoded first LSB page of data, the tier 2 ECC encoder/decoder performing tier 2 ECC encoding of the tier 1-encoded first LSB page of data to produce a tier 1/tier 2-encoded first LSB page data, the SSD controller sending the tier 1/tier 2-encoded first LSB page of data to the first flash memory, the tier 1 ECC encoding/decoding logic performing tier 1 ECC encoding of the first MSB page of data to produce a tier 1-encoded first MSB page of data, the SSD controller sending the tier 1-encoded first MSB page of data to the first flash memory, the tier 1 ECC encoding and the tier 2 encoding being different types of encoding, ...

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Номер записи: 82
23-06-2016 дата публикации

SYSTEMS AND METHODS FOR SOFT DECISION GENERATION IN A SOLID STATE MEMORY SYSTEM

Номер: US20160182086A1
Автор: Chen Zhengang, Haratsch Erich F., WU Yunxiang
Принадлежит: SEAGATE TECHNOLOGY LLC

Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory. A data processing system includes a solid state memory device, a soft data generation circuit operable to receive multiple instances of an element of a read data set accessed from the solid state memory device, and access a scramble compensating extended look up table using the multiple instances of the element to receive corresponding soft data, and a data decoder circuit operable to yield a decoded output from the soft data. 1. A data processing system , the system comprising:a solid state memory device; receive multiple instances of an element of a read data set accessed from the solid state memory device; and', 'access a scramble compensating extended look up table using the multiple instances of the element to receive corresponding soft data; and, 'a soft data generation circuit operable toa data decoder circuit operable to yield a decoded output from the soft data.2. The data processing system of claim 1 , wherein the data decoder circuit is operable to apply a soft decoding algorithm to the soft data to yield the decoded output.3. The data processing system of claim 1 , wherein each instance of the element is read using a different reference value.4. The data processing system of claim 1 , further comprising a data de-randomizer circuit operable to de-randomize the soft data.5. The data processing system of claim 2 , wherein the soft decoding algorithm is a low density parity check decoding algorithm.6. The data processing system of claim 1 , wherein the solid state memory device comprises a single bit per cell flash memory.7. The data processing system of claim 4 , wherein the scramble compensating extended look up table includes a number of soft data values corresponding to different possible values for the multiple instances of the element claim 4 , wherein a first portion of the soft data values ...

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Номер записи: 83
22-06-2017 дата публикации

INTERNAL COPY-BACK WITH READ-VERIFY

Номер: US20170177236A1
Автор: Alhussien Abdelhakim, Chen Zhengang, Hanna Stephen, Haratsch Erich F.
Принадлежит: SEAGATE TECHNOLOGY LLC

Systems and methods for internal copy-back with read-verify are described. In one embodiment, a storage device includes a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page. The controller, in conjunction with an error correcting code (ECC) decoder, read-verifies the first SLC page. Read-verifying the first SLC page includes reading the first SLC page to an internal page buffer, decoding the first SLC page read into the internal page buffer, determining a number of errors contained in the first SLC page based at least in part on the decoding, and verifying whether the number of errors contained in the first SLC page satisfies an error threshold. The controller transfers the first SLC page to the TLC page according to a result of read-verifying the first SLC page. 1. A storage device , the storage device comprising: select a first single level cell (SLC) page on the storage device;', 'decode the first SLC page;', 'determine a number of errors contained in the first SLC page based at least in part on the decoding;', 'verify whether the number of errors contained in the first SLC page satisfies an error threshold; and', 'transfer the first SLC page to a triple level cell (TLC) page according to a result of verifying whether the number of errors contained in the first SLC page satisfies the error threshold., 'a controller, the controller to2. The storage device of claim 1 , comprising:upon detecting no errors in the first SLC page, the controller to program a word line of the TLC page with the first SLC page.3. The storage device of claim 1 , comprising:upon detecting errors in the first SLC page that do not satisfy the error threshold, the controller to program a word line of the TLC page with the first SLC page containing the errors.4. The storage device of claim 1 , comprising:upon detecting errors that satisfy the error threshold, the controller to transfer the ...

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Номер записи: 84
18-09-2014 дата публикации

RETENTION DETECTION AND/OR CHANNEL TRACKING POLICY IN A FLASH MEMORY BASED STORAGE SYSTEM

Номер: US20140269048A1
Автор: Chen Zhengang, Haratsch Erich F., Werner Jeremy, Wu Ying Quan
Принадлежит: LSI Corporation

A method for determining a retention time in a solid state device (SSD), comprising the steps of providing a plurality of write operations to a memory, determining a reference voltage for each of the write operations, determining a difference between (i) the reference voltage after each of the write operations and (ii) a target reference voltage and if the difference is above a predetermined value, generating a flag indicating an excessive retention has occurred. 1. A method for determining a retention time in a solid state drive (SSD) , comprising the steps of:providing a plurality of write operations to a memory;determining a reference voltage for each of said write operations;determining a difference between (i) said reference voltage after each of said write operations and (ii) a target reference voltage; andif said difference is above a predetermined value, generating a flag indicating an excessive retention has occurred.2. The method according to claim 1 , further comprising the step of:adjusting a channel tracking procedure in response to said flag.3. The method according to claim 1 , wherein said target voltage level is calculated after an erase operation.4. The method according to claim 1 , wherein said method is invoked on an R-block level.5. The method according to claim 1 , wherein said memory comprises a flash based memory.6. The method according to claim 1 , wherein said method operates without invoking time or temperature calculations.7. The method according to claim 1 , wherein said method generates said flag as an estimate of a number of a program/erase cycle count.8. The method according to claim 1 , wherein said method is implemented with a channel/tracking procedure of a controller of said solid state drive.9. The method according to claim 8 , wherein said method is integrated on a digital signal processor of said controller.10. The method according to claim 1 , wherein said flag triggers a retention policy operation.11. An apparatus comprising:a ...

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Номер записи: 85
18-09-2014 дата публикации

NONVOLATILE MEMORY DATA RECOVERY AFTER POWER FAILURE

Номер: US20140269053A1
Автор: Chen Zhengang, Cohen Earl T., Tang Alex G.
Принадлежит: LSI Corporation

A method for data recovery after a power failure is disclosed. The method may include steps (A) to (D). Step (A) may determine that a last power-down of a solid-state drive was an unsafe power-down. Step (B) may search at least some of a plurality of pages of a nonvolatile memory of the solid-state drive to define an unsafe zone in response to the determining that the last power-down of the solid-state drive was the unsafe power-down. Step (C) may define a pad zone comprising one or more of the pages subsequent to the unsafe zone. Step (D) may resume operation of the solid-state drive by writing new data subsequent to the pad zone. 1. A method for data recovery after a power failure , comprising the steps of:(A) determining that a last power-down of a solid-state drive was an unsafe power-down;(B) searching at least some of a plurality of pages of a nonvolatile memory of said solid-state drive to define an unsafe zone in response to said determining that said last power-down of said solid-state drive was said unsafe power-down;(C) defining a pad zone comprising one or more of said pages subsequent to the unsafe zone; and(D) resuming operation of said solid-state drive by writing new data subsequent to said pad zone.2. The method according to claim 1 , further comprising the step of:writing random data to said pages of said pad zone.3. The method according to claim 1 , further comprising the step of:restoring a map of said solid-state drive according to data prior to said unsafe zone.4. The method according to claim 1 , wherein the nonvolatile memory is a multi-level cell NAND Flash memory.5. The method according to claim 4 , wherein (i) said searching comprises finding a first lower page that is erased and (ii) said unsafe zone comprises a specified number of said pages prior to said first lower page that is erased.6. The method according to claim 4 , where said first page subsequent to said pad zone is a lower page.7. The method according to claim 1 , wherein said ...

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Номер записи: 86
28-06-2018 дата публикации

CAPACITANCE COUPLING PARAMETER ESTIMATION IN FLASH MEMORIES

Номер: US20180180654A1
Автор: ASADI Meysam, Chen Zhengang, Haratsch Erich F.
Принадлежит:

A method for capacitance coupling parameter estimation includes determining a plurality of mean voltages among a plurality of memory cells of the memory in each of a plurality of cases related to inter-cell interference, generating a plurality of middle state mean voltages in response to the mean voltages, and adjusting one or more threshold voltages used to read from the memory based on the middle state mean voltages to operate independently of knowledge of middle state distributions in the memory cells. 1. A method for capacitance coupling noise accommodation , comprising the steps of:determining a plurality of mean voltages among a plurality of memory cells of the memory in each of a plurality of cases related to inter-cell interference;generating a plurality of middle state mean voltages in response to the mean voltages; andadjusting one or more threshold voltages used to read from the memory based on the middle state mean voltages to operate independently of knowledge of middle state distributions in the memory cells.2. The method according to claim 1 , further comprising the step of: the adjustment of the threshold voltages is further based on the coupling parameters, and', 'the coupling parameters comprise one or more couplings between a plurality of perturbed memory cells and a plurality of neighboring memory cells adjacent to the perturbed memory cells in the memory., 'estimating a plurality of coupling parameters in response to the mean voltages, wherein'}3. The method according to claim 2 , wherein the coupling parameters are determined under one or more conditions ofthe memory is off-line and the coupling parameters are estimated, andthe memory is on-line and the coupling parameters are updated a plurality of times.4. The method according to claim 2 , whereinthe memory is a flash memory configured to store at least two bits in each of the memory cells,one of the coupling parameters represents a horizontal capacitance coupling between the perturbed memory ...

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Номер записи: 87
09-07-2015 дата публикации

CAPACITANCE COUPLING PARAMETER ESTIMATION IN FLASH MEMORIES

Номер: US20150194219A1
Автор: ASADI Meysam, Chen Zhengang, Haratsch Erich F.
Принадлежит: LSI Corporation

A method for capacitance coupling parameter estimation is disclosed. Step (A) of the method determines a plurality of voltages in a plurality of memory cells of a nonvolatile memory in response to a plurality of writes to the memory cells. The voltages are determined in each of a plurality of cases related to inter-cell interference. Step (B) generates a system of equations of a capacitance coupling model in response to the voltages from all of the cases. Step (C) generates one or more parameters in response to the system of equations. The parameters include one or more couplings between a perturbed memory cell and a plurality of neighboring memory cells adjacent to the perturbed memory cell. 1. A method for capacitance coupling parameter estimation , comprising the steps of:(A) determining a plurality of voltages in a plurality of memory cells of a nonvolatile memory in response to a plurality of writes to said memory cells, wherein said voltages are determined in each of a plurality of cases related to inter-cell interference;(B) generating a system of equations of a capacitance coupling model in response to said voltages from all of said cases; and(C) generating one or more parameters in response to said system of equations, wherein said parameters comprise one or more couplings between a perturbed memory cell and a plurality of neighboring memory cells adjacent to said perturbed memory cell.2. The method according to claim 1 , wherein (i) said nonvolatile memory is a flash memory claim 1 , (ii) one of said parameters represents a horizontal capacitance coupling between said perturbed memory cell and said neighboring memory cells and (iii) another of said parameters is a vertical capacitance coupling between said perturbed memory cell and said neighboring memory cells.3. The method according to claim 1 , wherein said cases include (i) a final voltage case claim 1 , (ii) a no inter-cell interference case claim 1 , (iii) a vertical capacitance coupling case and (iv ...

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Номер записи: 88
04-06-2020 дата публикации

FAILURE-TOLERANT ERROR CORRECTION LAYOUT FOR MEMORY SUB-SYSTEMS

Номер: US20200177205A1
Автор: Chen Zhengang, Shen Zhenlei, Wu Wei
Принадлежит:

Codewords of an error correcting code can be received. The codewords can be separated into multiple segments. The segments of the codewords can be distributed in an error correcting layout across a plurality of dies where at least a portion of the error correcting layout constitutes a Latin Square (LS) layout. 1. A method comprising:receiving a plurality of codewords of an error correcting code;dividing the plurality of codewords of the error correcting code into a plurality of segments; anddistributing, by a processing device, the plurality of segments of the plurality of codewords in an error correcting layout across a plurality of dies, wherein at least a portion of the error correcting layout constitutes a Latin Square (LS) layout.2. The method of claim 1 , wherein each codeword of the plurality of codewords is divided into an equal number of segments.3. The method of claim 2 , wherein the number of segments in each codeword is equal to a number of dies in the plurality of dies.4. The method of claim 3 , wherein each die of the plurality of dies includes a number of memory units.5. The method of claim 4 , wherein the number of memory units in each die is equal to the number of segments in each codeword.6. The method of claim 1 , further comprising:calculating an exclusive-OR (XOR) value based on a combination of the plurality of codewords.7. The method of claim 6 , further comprising:storing the XOR value in an additional die outside of the LS layout and within the error correcting layout.8. The method of claim 6 , further comprising:storing the XOR value within the LS layout that spans the entire error correcting layout, wherein the XOR value is distributed uniformly across the plurality of dies.9. A method comprising:obtaining a plurality of codewords, wherein each codeword is an element of an error correcting code (ECC);assigning a plurality of dies of a memory-subsystem to each codeword of the plurality of codewords;separating each codeword of the plurality ...

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Номер записи: 89
18-09-2014 дата публикации

METHOD AND APPARATUS FOR GENERATION OF SOFT DECISION ERROR CORRECTION CODE INFORMATION

Номер: US20140281822A1
Автор: Chen Zhengang, Haratsch Erich F., WU Yunxiang
Принадлежит: LSI Corporation

A method and apparatus for generating soft decision error correction code information. The method includes generating or creating a lookup table (LUT), such as a log likelihood ratio (LLR) lookup table, characterizing a flash memory device. The method also includes loading the lookup table into the SSD controller. The method also includes accessing the lookup table to assign LLR or other characteristic values to the cells of a flash memory device. The method also includes decoding the data in a flash memory device using the soft decision information provided by the lookup table and assigned to the appropriate cells of the flash memory device. 1. A method for providing soft decision information for error correction codes for a flash memory device , comprising:generating an offline lookup table of characteristic values of the flash memory device;loading the lookup table into a solid state device (SSD) controller to which the flash memory device is coupled;accessing the lookup table to assign characteristic values to one or more cells of the flash memory device; anddecoding data in the flash memory device using the characteristic values provided by the lookup table and assigned to the one or more cells of the flash memory device to provide soft decision information for error correction codes.2. The method as recited in claim 1 , wherein the lookup table is a log likelihood ratio (LLR) lookup table.3. The method as recited in claim 1 , wherein the lookup table is a log likelihood ratio (LLR) lookup table based on a plurality of program-erase cycles (PEC) and retention times for the flash memory device.4. The method as recited in claim 1 , wherein the lookup table is loaded into the solid state device controller during the manufacture of the solid state device controller.5. The method as recited in claim 1 , wherein the lookup table is loaded into the solid state device controller after the solid state device controller has been manufactured.6. A solid state device (SSD) ...

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Номер записи: 90
11-06-2020 дата публикации

MANAGEMENT OF CORRUPTIVE READ IN MEMORY SYSTEMS

Номер: US20200183783A1
Автор: Chen Zhengang, Xie Tingjun
Принадлежит:

Described herein are embodiments related to one-direction error recovery flow (ERF) operations on memory components of memory systems. A processing device determines that data from a read operation is not successfully decoded because of a partial write of the data. The partial write results from a number of memory cells written as a first state and read as a second state. The processing device performs a one-direction ERF on the memory cells by monotonically adjusting a read voltage level for one or more re-read operations from a first discrete read voltage level towards a second read voltage level in a first direction until the data from the one or more re-read operations is successfully decoded. The first direction corresponds to an opposite direction of a state shift of the partial write. The processing device can also can determine a directional EBC and perform a refresh write if necessary. 1. A system comprising:a memory component; and issue a read operation with an initial read voltage level on a plurality of memory cells of the memory component;', 'determine that data from the read operation is not successfully decoded because of a partial write of the data, wherein the partial write results from a number of the plurality of memory cells written as a first state and read as a second state; and', 'perform a one-direction error recovery flow (ERF) on the plurality of memory cells by monotonically adjusting a read voltage level for one or more re-read operations from a first discrete read voltage level towards a second read voltage level in a first direction until the data from the one or more re-read operations is successfully decoded, the first direction corresponding to an opposite direction of a state shift of the partial write., 'a processing device, operatively coupled with the memory component, to2. The system of claim 1 , wherein the processing device is further to:select the read voltage level of a corresponding re-read operation of the one or more re- ...

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Номер записи: 91
25-09-2014 дата публикации

Method of Optimizing Solid State Drive Soft Retry Voltages

Номер: US20140286102A1
Автор: Ning Chen, Yingquan Wu, Yunxiang Wu, Zhengang Chen
Принадлежит: LSI Corp

A method of optimizing solid state drive (SSD) soft retry voltages comprises limiting a number of voltage reads and properly spacing and determining the reference voltage at which each voltage is read based on desired Bit Error Rate (BER) and channel throughput. The method determines each reference voltage for a number of soft retry voltage reads based on a hard decision read. The spacing between each read reference voltage is constant since each SSD type requires a number of reads for an accurate presentation of soft retry voltages. The voltage distance between each successive read is limited to a multiple of the constant spacing while the multiple is based on success or failure of the first read. The method determines a limited number of reads, the constant spacing between reads, and a desired reference voltage for each read, thereby increasing valuable throughput of the channel and decreasing BER.

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Номер записи: 92
11-06-2020 дата публикации

DEFECT DETECTION IN MEMORIES WITH TIME-VARYING BIT ERROR RATE

Номер: US20200185045A1
Автор: Chen Zhengang, Kwong Charles S., Mylavarapu Sai Krishna, Shen Zhenlei, Xie Tingjun
Принадлежит:

Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device performs an error recovery flow (ERF) to recover a unit of data comprising data and a write timestamp indicating when the unit of data was written. The processing device determines whether to perform a defect detection operation to detect a defect in the memory component using a bit error rate (BER), corresponding to the read operation, and the write timestamp in the unit of data. The processing device initiates the defect detection operation responsive to the BER condition not being expected for the calculated WR (based on the write timestamp). The processing device can use an ERF condition and the write timestamp to determine whether to perform the defect detection operation. The processing device initiates the defect detection operation responsive to the ERF condition not being expected the calculated WR (based on the write timestamp). 1. A system comprising:a memory component; and perform a read operation to read a unit of data comprising data and a write timestamp indicating when the unit of data was written to the memory component;', 'detect an error recovery flow (ERF) condition, wherein the ERF condition is detected responsive to the ERF being performed to recover the unit of data responsive to one or more errors being detected in the read operation;', 'detect a bit error rate (BER) condition, wherein the BER condition is detected responsive to a BER, corresponding to the read operation, satisfying a threshold criterion;', 'determine a write-to-read (W2R) delay for the read operation using a current time of the read operation and the write timestamp;', 'determine whether the BER condition or the ERF condition is expected for the W2R delay; and', 'initiate a defect detection operation responsive to the BER condition or the ERF condition not being expected for the W2R delay., 'a processing device, operatively ...

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Номер записи: 93
29-07-2021 дата публикации

PREEMPTIVE READ REFRESH IN MEMORIES WITH TIME-VARYING ERROR RATES

Номер: US20210233603A1
Автор: Chen Zhengang, Xie Tingjun
Принадлежит:

A processing device in a memory sub-system determines a write-to-read delay time for a segment of a memory device read during a first read operation using a first read voltage level. The processing device further determines that the write-to-read delay time is associated with a second read voltage level and performs a read refresh operation on at least a portion of the segment of the memory device using the second read voltage level. 1. A system comprising:a memory device; and determining a write-to-read delay time for a segment of the memory device read during a first read operation using a first read voltage level;', 'determining that the write-to-read delay time is associated with a second read voltage level; and', 'performing a read refresh operation on at least a portion of the segment of the memory device using the second read voltage level., 'a processing device, operatively coupled with the memory device, to perform operations comprising2. The system of claim 1 , wherein performing the read refresh operation on the at least the portion of the segment of the memory device comprises performing the read refresh operation on a subset of a plurality of codewords in a RAID stripe across the memory device claim 1 , wherein the subset of the plurality of codewords fail to be decoded and are recovered using RAID.3. The system of claim 1 , wherein the first read voltage level is a lowest read voltage level of a plurality of read voltage levels associated with the memory device claim 1 , and wherein the write-to-read delay time represents a difference between a first time when the data was written to the segment and a second time when a read request identifying data stored in the segment was issued to the memory device.4. The system of claim 3 , wherein determining the write-to-read delay time for the segment of the memory device comprises reading a timestamp stored with the data in the segment of the memory device claim 3 , the timestamp indicating the first time when ...

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Номер записи: 94
02-10-2014 дата публикации

Priori Information Based Post-Processing in Low-Density Parity-Check Code Decoders

Номер: US20140298131A1
Автор: Alhussien Abdel-Hakim S., Chen Zhengang, Haratsch Erich F.
Принадлежит: LSI Corporation

A low-density parity-check decoder utilizes information about hard errors in a storage medium to identify bit locations to flip log-likelihood ratios while attempting to decode codewords. The decoder iteratively flips and saturates log-likelihood ratios for bits at hard error locations and re-decodes until a valid codeword is produced. The decoder also identifies variable nodes associated with trapping sets for iterative log-likelihood ratio bit flipping. 1. A memory storage system , comprising:a processor;memory connected to the processor;a data storage element connected to the processor; andcomputer executable program code configured to execute on the processor, select a hard error location associated with a bit in a codeword;', 'flip a log-likelihood ratio associated with the selected hard error location; and', 'decode the codeword based on the flipped log-likelihood ratio., 'wherein the computer executable program code is configured to2. The memory storage system of claim 1 , wherein the computer executable program code is further configured to receive a list of one or more hard error locations associated with a bit in a codeword.3. The memory storage system of claim 1 , wherein the computer executable program code is further configured to saturate the selected log-likelihood ratio.4. The memory storage system of claim 1 , wherein the computer executable program code is further configured to:iteratively select a previously unselected hard error location associated with a bit in a codeword from a list of potential hard error locations;flip a log-likelihood ratio associated with the previously unselected hard error location; anddecode the codeword based on the flipped log-likelihood ratio.5. The memory storage system of claim 4 , wherein the computer executable program code is further configured to saturate the log-likelihood ratio.6. The memory storage system of claim 1 , wherein the computer executable program code is further configured to flip the log- ...

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Номер записи: 95
06-08-2015 дата публикации

IDENTIFICATION AND MITIGATION OF HARD ERRORS IN MEMORY SYSTEMS

Номер: US20150220391A1
Автор: Burd Gregory, Chen Zhengang, Chilappagari Shashi Kiran
Принадлежит:

Embodiments provide a method comprising estimating a first set of log-likelihood ratio (LLR) values for a plurality of memory cells of a memory; based on the first set of LLR values, performing a first error correcting code (ECC) decoding operation; in response to determining a failure of the first ECC decoding operation, generating, by adjusting the first set of LLR values, a second set of LLR values for the plurality of memory cells; and based on the second set of LLR values, performing a second ECC decoding operation. 1. A method for detecting a fault in a multi-level memory cell in a memory , wherein the multi-level memory cell is configured to store at least a first bit and a second bit , the method comprising: in response to failing to decode the second bit of the multi-level memory cell,', 'identifying a first threshold voltage range associated with the second bit of the multi-level memory cell,', 'determining whether the first threshold voltage range is adjacent to, or included in at least one of the N number of threshold voltage ranges, and', 'In response to the first threshold range being neither adjacent to, nor included in, at least one of the N number of threshold voltage ranges, identifying the multi-level memory cell as potentially having a fault., 'decoding the first bit of the multi-level memory cell by correcting a first value of the first bit to a second value, wherein the second value corresponds to N number of threshold voltage ranges of the multi-level memory cell; and'}2. The method of claim 1 , further comprising:In response to the first threshold range being neither adjacent to, nor included in, at least one of the N number of threshold voltage ranges, (i) assigning a log-likelihood ratio (LLR) of zero to the second bit of the multi-level memory cell, and (ii) attempting to re-decode the second bit of the multi-level memory cell based on the LLR of zero assigned to the second bit of the multi-level memory cell.3. The method of claim 1 , ...

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Номер записи: 96
13-08-2015 дата публикации

Systems and Methods for Last Written Page Handling in a Memory Device

Номер: US20150227314A1
Автор: CAI Yu, Chen Zhengang, Dong Zhimin, Haratsch Erich F.
Принадлежит: LSI Corporation

Systems and method relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. 1. A data read system , the system comprising:a memory read circuit operable to access a data set from a group of memory cells using a standard reference value to distinguish bit values in the group of memory cells; determine that the group of memory cells was a last written group of memory cells; and', 'based at least in part on determining that the group of memory cells was a last written group of memory cells, cause the memory read circuit to re-access a data set from the group of memory cells using a last written reference value to distinguish bit values in the group of memory cells., 'a controller system operable to2. The system of claim 1 , wherein the system further comprises a memory circuit including a superset of memory cells claim 1 , and wherein the group of memory cells is a subset of the superset of memory cells.3. The system of claim 2 , wherein each of the cells of the superset of memory cells are selected from a group consisting of: a single bit memory cell claim 2 , a two-bit memory cell claim 2 , and a three bit memory cell.4. The system of claim 2 , wherein the superset of memory cells are flash memory cells.5. The system of claim 1 , the system further comprising:a last written group memory operable to maintain a location of the last written group of memory cells in the superset of memory cells.6. The system of claim 5 , wherein the controller circuit determines that the group of memory cells was the last written group of memory cells based at least in part on a comparison of a read address with the location of the last written group of memory cells accessed from the last written group memory.7. The system of claim 1 , wherein the system further comprises: apply a hard decision decode algorithm to the data set from the group of memory cells accessed using the standard reference value to yield a ...

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Номер записи: 97
09-08-2018 дата публикации

SYSTEMS AND METHODS FOR SOFT DECISION GENERATION IN A SOLID STATE MEMORY SYSTEM

Номер: US20180226991A1
Автор: Chen Zhengang, Haratsch Erich F., WU Yunxiang
Принадлежит: SEAGATE TECHNOLOGY LLC

Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory. A data processing system includes a solid state memory device, a soft data generation circuit operable to receive multiple instances of an element of a read data set accessed from the solid state memory device, and access a scramble compensating extended look up table using the multiple instances of the element to receive corresponding soft data, and a data decoder circuit operable to yield a decoded output from the soft data. 1. A data storage system , the system comprising:a solid state memory device;a soft data generation circuit operable to receive multiple instances of an element of a read data set accessed from the solid state memory device; and access a scramble compensating extended look up table using the multiple instances of the element to receive corresponding soft data, wherein the scramble compensating extended look up table includes modified soft data values and unmodified soft data values; anda data decoder circuit operable to yield a decoded output from the soft data.2. The data storage system of claim 1 , wherein the data decoder circuit is operable to apply a soft decoding process to the soft data to yield the decoded output.3. The data storage system of claim 2 , wherein the soft decoding process is a low density parity check decoding process.4. The data storage system of claim 1 , wherein each instance of the element is read using a different reference value.5. The data storage system of claim 1 , wherein the scramble compensating extended look up table includes a number of soft data values corresponding to different possible values for the multiple instances of the element.6. The data storage system of claim 1 , wherein the solid state memory device comprises a single bit per cell flash memory.7. The data storage system of claim 1 , further comprising:a data de-randomizer circuit operable to de- ...

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Номер записи: 98
27-08-2015 дата публикации

ADJUSTING LOG LIKELIHOOD RATIO VALUES TO COMPENSATE MISPLACEMENT OF READ VOLTAGES

Номер: US20150243363A1
Автор: Alhussien AbdelHakim S., Chen Zhengang, Haratsch Erich F., Sankaranarayanan Sundararajan, WU Yunxiang
Принадлежит: LSI Corporation

An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) perform one or more attempts of a soft-decision decode of data stored in the nonvolatile memory, where soft-decision decode uses a plurality of log likelihood ratio values stored in a table, (ii) generate one or more adjusted log likelihood ratio values by adding a constant value to one or more of the log likelihood ratio values in response to a failure to decode the data using the log likelihood ratio values and (iii) re-decode the data using the adjusted log likelihood ratio values. 1. An apparatus comprising:an interface to a nonvolatile memory; anda circuit configured to (i) perform one or more attempts of a soft-decision decode of data stored in said nonvolatile memory, wherein said soft-decision decode uses a plurality of log likelihood ratio values stored in a table, (ii) generate one or more adjusted log likelihood ratio values by adding a constant value to one or more of said log likelihood ratio values in response to a failure to decode said data using said log likelihood ratio values and (iii) re-decode said data using said adjusted log likelihood ratio values.2. The apparatus according to claim 1 , wherein said circuit is configured to generate further adjusted log likelihood ratio values by adding a plurality of different values to said log likelihood ratio values in response to a failure of said re-decoding.3. The apparatus according to claim 2 , wherein said circuit is configured to re-decode said data using said further adjusted log likelihood ratio values.4. The apparatus according to claim 2 , wherein said different values are related to a plurality of misplacements of a plurality of read voltages from an initial set of said read voltages used to sense said data.5. The apparatus according to claim 4 , wherein said different values have a corresponding linear relationship to said misplacements of said read voltages.6. The apparatus ...

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Номер записи: 99
17-09-2015 дата публикации

Manufacturer self-test for solid-state drives

Номер: US20150262712A1
Автор: David Patmore, Erich F. Haratsch, Yingji JU, Zhengang Chen
Принадлежит: SEAGATE TECHNOLOGY LLC

An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to process a plurality of I/O requests to blocks of the memory that are not marked as bad on a block list. The controller is configured to track a plurality of bad blocks of the memory. The controller is configured to perform a plurality of scans on the memory. The scans are configured to (a) identify the bad blocks, and (b) mark the bad blocks as bad on the block list.

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Номер записи: 100
23-09-2021 дата публикации

PERFORMING A REFRESH OPERATION BASED ON A CHARACTERISTIC OF A MEMORY SUB-SYSTEM

Номер: US20210295900A1
Автор: Chen Zhengang, JEON SEUNGJUNE, Kwong Charles See Yeung, Shen Zhenlei, Xie Tingjun
Принадлежит:

A media management operation can be performed at a memory sub-system at a current frequency. An operating characteristic associated with the memory sub-system can be identified. The operating characteristic can reflect at least one of a write count, a bit error rate, or a read-retry trigger rate. A determination can be made as to whether the identified operating characteristic satisfies an operating characteristic criterion. In response to determining that the operating characteristic satisfies the characteristic criterion, the media management operation can be performed at a different frequency relative to the current frequency. 1. A method comprising:performing, at a current frequency, a media management operation at a memory sub-system;identifying an operating characteristic associated with the memory sub-system, wherein the operating characteristic reflects at least one of a write count, a bit error rate, or a read-retry trigger rate;determining whether the identified operating characteristic satisfies an operating characteristic criterion; andresponsive to determining that the operating characteristic satisfies the characteristic criterion, performing the media management operation at a different frequency relative to the current frequency.2. The method of claim 1 , wherein the media management operation comprises a refresh operation.3. The method of claim 2 , wherein the refresh operation corresponds to at least one of one or more write operations to re-write data stored at one or more units of the memory sub-system or one or more read operations to read of the data stored at the one or more units of the memory sub-system.4. The method of claim 3 , wherein the one or more write operations are to re-write data based on alternating states at the one or more units of the memory sub-system.5. The method of claim 1 , wherein the operating characteristic reflects the write count claim 1 , and wherein determining whether the identified operating characteristic ...

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Номер записи: 101
30-09-2021 дата публикации

DEFECT DETECTION IN MEMORIES WITH TIME-VARYING BIT ERROR RATE

Номер: US20210304826A1
Автор: Chen Zhengang, Kwong Charles S., Mylavarapu Sai Krishna, Shen Zhenlei, Xie Tingjun
Принадлежит:

Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device determines that a bit error rate (BER) corresponding to a read operation to read a unit of data in a memory component satisfies a threshold criterion, determines a write-to-read (W2R) delay for the read operation, wherein the W2R delay comprises a difference between a time of the read operation and a write timestamp indicating when the unit of data was written to the memory component, and determines whether the W2R delay is within a W2R delay range corresponding to an initial read voltage level used by the read operation to read the unit of data. The processing device initiates a defect detection operation responsive to the W2R delay being within the W2R delay range, the defect detection operation to detect time-varying defects in the memory component.

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Номер записи: 102
07-10-2021 дата публикации

Self-seeded randomizer for data randomization in flash memory

Номер: US20210311868A1
Автор: Jianmin Huang, Zhengang Chen
Принадлежит: Micron Technology Inc

Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, improved data distribution techniques decouple the scrambling key from a physical address to allow for copyback operations while maintaining data distribution requirements across a memory device. The controller may generate a seed value that is used by a scrambling algorithm to scramble the host-data and meta-data prior to the data being written. The seed value is then encoded and written to the page with encoded versions of the scrambled user data and meta-data—the random seed is written without scrambling the random seed.

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Номер записи: 103
07-10-2021 дата публикации

METADATA AWARE COPYBACK FOR MEMORY DEVICES

Номер: US20210311869A1
Автор: Chen Zhengang, Huang Jianmin
Принадлежит:

Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, in order to update the meta-data, the meta-data and host-data are separated and the only the meta-data is sent to the controller to be updated during a modified internal copyback operation. The host-data is not transmitted to the controller. While sending the meta-data utilizes resources of the communication link between the memory dies and the controller, it uses much fewer resources than if the host-data were also transmitted.

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Номер записи: 104
01-10-2015 дата публикации

Flash memory read error recovery with soft-decision decode

Номер: US20150278015A1
Автор: Earl T. Cohen, Erich F. Haratsch, Jeremy Werner, Ning Chen, Yunxiang Wu, Zhengang Chen
Принадлежит: SEAGATE TECHNOLOGY LLC

An apparatus comprising a memory and a controller. The memory may be configured to store data. The controller may process a plurality of input/output requests to read/write to/from the memory. The controller may generate read data by performing a hard-decision decode on a codeword received from the memory. If the hard-decision decode fails, the controller may enter an error-recovery process comprising a plurality of recovery procedures. At least one of the recovery procedures may apply an inter-cell interference cancellation technique. The error-recovery process may (a) determine parameters for a soft-decision decode by performing one of the recovery procedures on the codeword, (b) execute the soft-decision decode using the parameters from the recovery procedure performed to generate the read data and (c) if the soft-decision decode fails, repeat (a) and (b) using a next one of the recovery procedures.

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Номер записи: 105
08-10-2015 дата публикации

Read policy for system data of solid state drives

Номер: US20150286421A1
Автор: Earl T. Cohen, Erich F. Haratsch, Gordon J. Coleman, Ivana Djurdjevic, Zhengang Chen
Принадлежит: LSI Corp

An apparatus includes a plurality of memory dies and a controller. The controller may be communicatively coupled to the plurality of memory dies and configured to utilize multiple copies of a root record containing system data during a boot-up process. The multiple copies of the root record are stored using at least two of the plurality of memory dies.

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Номер записи: 106
18-11-2021 дата публикации

SELF-ADAPTIVE READ VOLTAGE ADJUSTMENT USING BOUNDARY ERROR STATISTICS FOR MEMORIES WITH TIME-VARYING ERROR RATES

Номер: US20210358561A1
Автор: Chen Zhengang, Xie Tingjun
Принадлежит:

A processing device in a memory system determines a first error rate corresponding to a first set of write-to-read delay times at a first end of a range of write-to-read delay times for a memory device and a second error rate corresponding to a second set of write-to-read delay times at a second end of the range of write-to-read delay times, and determines whether a ratio of the first error rate to the second error rate satisfies a threshold criterion. Responsive to the ratio of the first error rate to the second error rate not satisfying the threshold criterion, the processing device adjusts a read voltage level associated with the range of write-to-read delay times 1. A system comprising:a memory device; and determining a first error rate corresponding to a first set of write-to-read delay times at a first end of a range of write-to-read delay times for the memory device and a second error rate corresponding to a second set of write-to-read delay times at a second end of the range of write-to-read delay times;', 'determining whether a ratio of the first error rate to the second error rate satisfies a first threshold criterion; and', 'responsive to the ratio of the first error rate to the second error rate not satisfying the first threshold criterion, adjusting a read voltage level associated with the range of write-to-read delay times., 'a processing device, operatively coupled with the memory device, to perform operations comprising2. The system of claim 1 , wherein determining the first error rate comprises:monitoring read operations performed on segments of the memory device having write-to-read delay times that fall within the first set of the plurality of write-to-read delay times;incrementing a first counter in response to each failed bit detected in the read operations;incrementing a second counter in response to each bit in each code word that is decoded in the read operations;determining that a value of the first counter satisfies a second threshold ...

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Номер записи: 107
08-10-2015 дата публикации

Bad memory unit detection in a solid state drive

Номер: US20150287478A1
Автор: Earl T. Cohen, Erich F. Haratsch, Jeremy Werner, Zhengang Chen
Принадлежит: LSI Corp

An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory unit granularities each having a size less than a total size of the memory. The controller is configured to process a plurality of I/O requests to the memory units of the memory that are not marked as bad on a memory unit list. The controller is configured to track a plurality of bad blocks of the memory. The controller is configured to determine which of the memory units to mark as bad based on a test of whether a unit of memory larger than a block of the memory has failed. The test is based on a threshold of the bad blocks in the unit of memory.

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Номер записи: 108
15-10-2015 дата публикации

ONLINE HISTOGRAM AND SOFT INFORMATION LEARNING

Номер: US20150294739A1
Автор: CAI Yu, Chen Zhengang, Haratsch Erich F., WU Yunxiang
Принадлежит: LSI Corporation

A system includes a processor configured to read information from a plurality of memory cells. The processor initiates a first read of raw data from a group of memory cells using a first reference voltage. The processor also initiates a second read of raw data from the group of memory cells using a second reference voltage different from the first reference voltage. The processor further compares the first read to the second read to identify memory cells read with a bit value that changes between the first and second reads. The processor also assigns the memory cells read with a bit value that changes between the first and second reads to a region associated with the second reference voltage. The processor further counts the number of cells read with a bit value that changes to generate a histogram corresponding to soft information for the group of memory cells. 1. A system comprising:a processor configured to read information from a plurality of memory cells; and initiate a first read of raw data from a group of memory cells using at least a first reference voltage;', 'initiate a second read of raw data from the group of memory cells using at least a second reference voltage different from the at least the first reference voltage;', 'compare the first read of raw data to the second read of raw data to identify memory cells of the group of memory cells read with a bit value that changes between the first read of raw data and the second read of raw data; and', 'assign the memory cells read with a bit value that changes between the first read of raw data and the second read of raw data to at least one region associated with the at least the second reference voltage., 'a memory having computer executable instructions stored thereon, the computer executable instructions configured for execution by the processor to2. The system as recited in claim 1 , wherein the computer executable instructions are configured for execution by the processor to count the number of memory ...

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Номер записи: 109
09-11-2017 дата публикации

SYSTEMS AND METHODS FOR LATENCY BASED DATA RECYCLING IN A SOLID STATE MEMORY SYSTEM

Номер: US20170322750A1
Автор: CAI Yu, Chen Ning, Chen Zhengang, Haratsch Erich F., WU Yunxiang
Принадлежит: SEAGATE TECHNOLOGY LLC

Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count. 1. A data processing system , comprising:a memory device operable to maintain a data set;a data decoder circuit operable to determine a decoded output based on the data set and provide an iteration count indicating a number of iterations that a data decoding algorithm is applied to the data set;and a recycle control circuit operable to compare a frequency of access corresponding to the data set with an access frequency threshold, compare the iteration count to a first iteration threshold when the frequency of access satisfies the access frequency threshold, compare the iteration count to a second iteration threshold different from the first iteration threshold when the frequency of access fails to satisfy the access frequency threshold, and recycle read data corresponding to the data set upon determining the iteration count satisfies the first or second iteration threshold.2. The data processing system of claim 1 , wherein the data decoder circuit determines the decoded output by applying one or more iterations of the data decoding algorithm to the data set.3. The data processing system of claim 1 , wherein the data decoding algorithm includes at least a low density parity check decoding algorithm.4. The data processing system of claim 1 , further comprising a memory access circuit operable to calculate the frequency of access corresponding to the data set.5. The data ...

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Номер записи: 110
10-12-2015 дата публикации

Estimating read reference voltage based on disparity and derivative metrics

Номер: US20150355838A1
Автор: Erich F. Haratsch, Sundararajan Sankaranarayanan, Yunxiang Wu, Zhengang Chen
Принадлежит: SEAGATE TECHNOLOGY LLC

An adaptive channel tracking algorithm performed by a flash memory system obtains disparity metrics and derivative metrics and uses a combination of the disparity and derivative metrics to estimate an optimal read reference voltage. The estimation of the optimal read reference voltage does not rely on assumptions about the underlying cell voltage distributions and results in a good estimate of the read reference voltage even if the standard deviations of the cell voltage distributions are different. In addition, the algorithm is relatively simple and less computationally intensive to perform than the known tracking algorithms.

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Номер записи: 111
17-12-2015 дата публикации

INTER-CELL INTERFERENCE ESTIMATION BASED ON A PATTERN DEPENDENT HISTOGRAM

Номер: US20150364205A1
Автор: Chen Zhengang, Haratsch Erich F., WU Yunxiang
Принадлежит:

An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/program operations. The memory may comprise a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform a plurality of reads on a victim cell. The controller may be configured to store measured victim information from the plurality of reads on the victim cell. The controller may be configured to perform one or more reads on a plurality of aggressor cells. The controller may be configured to store measured aggressor information from the one or more reads on the plurality of aggressor cells. The controller may be configured to generate inter-cell interference parameters based on the measured victim information and the measured aggressor information. The controller may be configured to mitigate inter-cell interference based on the inter-cell interference parameters. 1. An apparatus comprising:a memory configured to process a plurality of read/program operations, said memory comprising a plurality of memory units each having a size less than a total size of said memory; anda controller configured to (i) perform a plurality of reads on a victim cell, (ii) store measured victim information from said plurality of reads on said victim cell, (iii) perform one or more reads on a plurality of aggressor cells, (iv) store measured aggressor information from said one or more reads on said plurality of aggressor cells, (v) generate inter-cell interference parameters based on said measured victim information and said measured aggressor information, and (vi) mitigate inter-cell interference based on said inter-cell interference parameters.2. The apparatus according to claim 1 , wherein said measured victim information and said measured aggressor information comprises a histogram of decision regions.3. The apparatus according to claim 1 , wherein said controller calculates said inter-cell interference ...

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Номер записи: 112
14-11-2019 дата публикации

REDUCTION OR ELIMINATION OF A LATENCY PENALTY ASSOCIATED WITH ADJUSTING READ THRESHOLDS FOR NON-VOLATILE MEMORY

Номер: US20190348133A1
Автор: Chen Zhengang, Haratsch Erich F., Sankaranarayanan Sundararajan
Принадлежит:

Channel information and channel conditions determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is so adjusted. This latter approach is advantageous in that relatively fewer adjustments will be made during normal read operations. 1. An apparatus comprising:a nonvolatile solid state memory; perform a set of reads to the selected region with a corresponding set of sample read reference voltages;', 'determine threshold voltage distributions for the selected region based on the set of reads;', 'update the first read reference voltage from an initial value to an updated value based on the threshold voltage distributions; and', 'perform a first read operation to the selected region by issuing a read command including the first read reference voltage., 'a central processing unit (CPU) configured to perform offline tracking of a condition of a selected region of the nonvolatile solid state memory to determine a first read reference voltage to apply during reads to the selected region, including, 'a controller circuit in connection with the nonvolatile solid state memory, including2. The apparatus of further comprising: perform an initial read operation to randomly selected blocks from the selected region by applying the first read reference voltage at the initial value;', 'determine whether a target ...

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Номер записи: 113
12-11-2020 дата публикации

HYBRID ITERATIVE ERROR CORRECTING AND REDUNDANCY DECODING OPERATIONS FOR MEMORY SUB-SYSTEMS

Номер: US20200356441A1
Автор: Chen Zhengang, TAI YING YU, Zhu Jiangli
Принадлежит:

Data stored on each of a set of memory components can be read. Corresponding data stored on a number of the set of memory components that cannot be decoded using an error correction code decoding operation can be identified. A determination can be made whether the number of the set of memory components that include the corresponding data that cannot be decoded from the ECC decoding operation satisfies a threshold condition. Responsive to determining that the number of the set of memory components that include the corresponding data that cannot be decoded from the second ECC decoding operation satisfies the threshold condition, a processing device, can perform a redundancy error correction decoding operation to correct the data stored on each of the set of memory components. 1. A method comprising:performing an error correction code (ECC) decoding operation to decode one or more units of data stored in a stripe across a plurality of memory devices;responsive to the ECC decoding operation being unsuccessful, determining whether a number of memory devices of the plurality of memory devices that include a first subset of the one or more units of data for which the ECC decoding operation was unsuccessful satisfies a threshold criterion; andresponsive to determining that the number of memory devices satisfies the threshold criterion, performing, by a processing device, one or more iterations of a redundancy error correction decoding operation to correct the first subset of the one or more units of data stored in the stripe across the plurality of memory devices until the number of memory devices fails to satisfy the threshold criterion.2. The method of claim 1 , further comprising:responsive to determining that the number of memory devices does not satisfy the threshold criterion, performing a redundancy reconstruction operation to reconstruct the first subset of the one or more units of data stored in the stripe across the plurality of memory devices.3. The method of ...

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Номер записи: 114
19-11-2020 дата публикации

ADJUSTMENT OF A PRE-READ OPERATION BASED ON AN OPERATING TEMPERATURE

Номер: US20200363969A1
Автор: Chen Zhengang, Shen Zhenlei E., Xie Tingjun, Zhu Jiangli
Принадлежит:

First data can be received at a memory sub-system. An operating temperature of the memory sub-system can be identified. An adjusted read voltage level can be determined in response to the operating temperature satisfying a threshold criterion pertaining to a threshold temperature. A read operation can be performed at the memory sub-system based on the adjusted read voltage level to retrieve second data. The first data can be stored at the memory sub-system based on the second data that was retrieved from the read operation that is based on the adjusted read voltage level. 1. A method comprising:receiving first data at a memory sub-system;identifying a characteristic of the memory sub-system, the characteristic comprising an operating temperature of the memory sub-system;adjusting, by a processing device, a prior read voltage level to determine an adjusted read voltage level responsive to the operating temperature satisfying a threshold criterion pertaining to a threshold temperature;performing a read operation at the memory sub-system based on the adjusted read voltage level to retrieve second data; andstoring the first data at the memory sub-system based on the second data retrieved by the read operation.2. The method claim 1 , wherein the threshold criterion is satisfied if the operating temperature is different than the threshold temperature.3. The method of claim 1 , wherein the operating temperature comprises a temperature at which the second data was stored at the memory sub-system.4. The method of claim 1 , wherein performing the read operation at the memory sub-system based on the adjusted read voltage level to retrieve the second data comprises applying the adjusted read voltage level to one or more memory cells of the memory sub-system claim 1 , and wherein the adjusted read voltage level is different than a prior read voltage level applied to another memory cell of the memory sub-system.5. The method of claim 1 , wherein storing the first data at the ...

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Номер записи: 115
19-12-2019 дата публикации

MANUFACTURER SELF-TEST FOR SOLID-STATE DRIVES

Номер: US20190385694A1
Автор: Chen Zhengang, Haratsch Erich F., Ju Yingji, Patmore David
Принадлежит:

An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list. 1. An apparatus comprising:a memory including a storage element having a plurality of planes, each plane including a plurality of individual storage blocks; [ a multi-plane block including a selected grouping of individual storage blocks from multiple planes of the plurality of planes,', 'accessing the memory using the multi-plane blocks allowing individual storage blocks from the multi-plane block to be accessed in parallel;, 'access the memory via a multi-plane block data storage configuration,'}, 'a single-plane block including an individual storage block from a single plane of the plurality of planes;', 'access the memory via a single-plane block data storage configuration,'}, perform a first scan on a selected multi-plane block by accessing the individual storage blocks within the multi-plane block in parallel;', 'when the scan indicates a failure in the multi-plane block, perform a second scan on the individual storage blocks of the multi-plane block as single-plane blocks; and', 'add individual storage blocks that fail the second scan to a bad block list., 'perform a defect scan to identify bad storage locations of the memory, including], 'a controller configured to2. The apparatus of claim 1 , further comprising: erase, in parallel, the individual storage blocks from the selected multi-plane block; and', 'determine the scan indicates the failure when an error is encountered during the erase., 'the controller configured to perform the first scan including3. The ...

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Номер записи: 116
29-12-2022 дата публикации

MEMORY ACCESS MODE SELECTION

Номер: US20220413714A1
Автор: Chen Zhengang, HU Guang, Huang Jianmin
Принадлежит:

A method includes determining one or more quality attributes for memory cells of a memory device, receiving a memory access request involving data written to at least a portion of the memory cells, and determining whether the memory access request corresponds to a random read operation or a sequential read operation. The method further includes responsive to determining that the memory access request corresponds to a random read operation or responsive to determining that the one or more quality attributes for memory cells are greater than a threshold quality level, or both, selecting a read mode for use in performance of the random read operation and performing the random read operation using the selected read mode. 1. A method , comprising:determining one or more quality attributes for memory cells of a memory device;receiving a memory access request involving data written to at least a portion of the memory cells;determining whether the memory access request corresponds to a random read operation or a sequential read operation;responsive to determining that the memory access request corresponds to a random read operation or responsive to determining that the one or more quality attributes for memory cells are greater than a threshold quality level, or both, selecting a read mode for use in performance of the random read operation; andperforming the random read operation using the selected read mode.2. The method of claim 1 , further comprising performing the random read operation using the selected read mode to sense data written to at least a set of the memory cells claim 1 , wherein the set of the memory cells comprises fewer memory cells than a page size of the memory device.3. The method of claim 1 , further comprising increasing an allowed raw bit error rate (RBER) for the set of memory cells based claim 1 , at least in part claim 1 , on the determined quality attributes for the set of memory cells being greater than the threshold quality level or ...

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Номер записи: 117
22-09-2020 дата публикации

Read voltage-assisted manufacturing tests of memory sub-system

Номер: US10783978B1
Автор: Steven M. Pope, Tingjun Xie, Zhengang Chen
Принадлежит: Micron Technology Inc

A system includes memory dice, each having a register to store multiple read voltage levels. A processing device is to test each memory die by verification, via access to the multiple read voltage levels, whether each read voltage level falls within a corresponding relative voltage range. The processing device selects an initial read voltage level that achieves bit error rates not satisfying a threshold criterion at one of a first or a second shortest write-to-read (W 2 R) delay for the memory die and determines a bit error rate, using the initial read voltage level, of storage units of the memory die. The processing device reports the memory die as defective in response to one of: (i) a read voltage level, of the multiple read voltage levels, failing to verify; or (ii) the bit error rate of one or more storage units of the memory die satisfying the threshold criterion.

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Номер записи: 118
07-10-2014 дата публикации

Mixed granularity higher-level redundancy for non-volatile memory

Номер: US8856431B2
Автор: Yunxiang Wu, Zhengang Chen
Принадлежит: LSI Corp

Mixed-granularity higher-level redundancy for NVM provides improved higher-level redundancy operation with better error recovery and/or reduced redundancy information overhead. For example, pages of the NVM that are less reliable, such as relatively more prone to errors, are operated in higher-level redundancy modes having relatively more error protection, at a cost of relatively more redundancy information. Concurrently, blocks of the NVM that are more reliable are operated in higher-level redundancy modes having relatively less error protection, at a cost of relatively less redundancy information. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively less error protection, techniques described herein provide better error recovery. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively more error protection, the techniques described herein provide reduced redundancy information overhead.

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Номер записи: 119
06-09-2022 дата публикации

Failure-tolerant error correction layout for memory sub-systems

Номер: US11438012B2
Автор: Wei Wu, Zhengang Chen, Zhenlei Shen
Принадлежит: Micron Technology Inc

Codewords of an error correcting code can be received. The codewords can be separated into multiple segments. The segments of the codewords can be distributed in an error correcting layout across a plurality of dies where at least a portion of the error correcting layout constitutes a Latin Square (LS) layout.

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Номер записи: 120
31-08-2021 дата публикации

Self-adaptive read voltage adjustment using boundary error statistics for memories with time-varying error rates

Номер: US11107550B2
Автор: Tingjun Xie, Zhengang Chen
Принадлежит: Micron Technology Inc

A processing device in a memory system identifies a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range. The processing device further identifies a first set of the plurality of write-to-read delay times at a first end of the first range and a second set of the plurality of write-to-read delay times at a second end of the first range, and determines a first error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second error rate for the memory component corresponding to the second set of the plurality of write-to-read delay times. The processing device determines whether a correspondence between the first error rate and the second error rate satisfies a first threshold criterion, and, responsive to the correspondence between the first error rate and the second error rate not satisfying the first threshold criterion, modifies the read voltage level associated with the first range.

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Номер записи: 121
16-04-2014 дата публикации

Accelerated soft read for multi-bit cell nonvolatile memories

Номер: EP2720229A1
Автор: Hao ZHONG, Zhengang Chen
Принадлежит: LSI Corp

A memory device includes a memory array comprising multi-bit memory cells, and control circuitry coupled to the memory array. The control circuitry is configured to perform accelerated soft read operations on at least a portion of the memory array. A given one of the accelerated soft read operations directed to a non-upper page of the memory array comprises at least one hard read operation directed to a corresponding upper page of the memory array. For example, the given accelerated soft read operation may comprise a sequence of multiple hard read operations including a hard read operation directed to the non-upper page and one or more hard read operations directed to the corresponding upper page.

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Номер записи: 122
17-11-2015 дата публикации

Generating soft decoding information for flash memory error correction using hard decision patterns

Номер: US9189333B2
Автор: Erich F. Haratsch, Yunxiang Wu, Zhengang Chen
Принадлежит: SEAGATE TECHNOLOGY LLC

A flash memory controller having soft-decoding error correcting code (ECC) logic generates log likelihood ratio or similar ECC decoder soft input information from decision patterns obtained from reading data from the same portion of flash memory two or more times. Each decision pattern corresponds to a voltage region bordering one of the reference voltages. Each decision pattern represents a combination of flash memory bit value decisions for a cell voltage within the voltage region corresponding to the decision pattern when a corresponding combination of the reference voltages are used to read the cell. Numerical values are then computed in response to combinations of the flash memory bit value decisions represented by the decision patterns. The numerical values are provided to the soft-decoding ECC logic to serve as soft input information.

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Номер записи: 123
01-06-2021 дата публикации

Performing a refresh operation based on a write to read time difference

Номер: US11023171B2
Автор: Tingjun Xie, Zhengang Chen
Принадлежит: Micron Technology Inc

A read operation can be performed to retrieve data of a write unit at a memory sub-system. An indication of a time of the performance of the read operation can be received. Another indication of another time of a performance of a write operation to store the data of the write unit at the memory sub-system can be received. A difference between the time of the performance of the read operation and the another time of the performance of the write operation can be determined. A refresh operation can be performed for the data of the write unit at the memory sub-system based on the difference between the time of the performance of the read operation and the another time of the performance of the write operation.

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Номер записи: 124
21-01-2021 дата публикации

Self-adaptive read voltage adjustment using boundary error statistics for memories with time-varying error rates

Номер: WO2021011202A1
Автор: Tingjun Xie, Zhengang Chen
Принадлежит: MICRON TECHNOLOGY, INC.

A processing device is configured to: identify a first range of a plurality of write-to-read delay ranges for the memory component; identify a first set of the plurality of write-to-read delay times at a first end of the first range and a second set of the plurality of write-to-read delay times at a second end of the first range; determine a first error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second error rate for the memory component corresponding to the second set of the plurality of write -to -read delay times; determine whether a correspondence between the first error rate and the second error rate satisfies a first threshold criterion; and modify the read voltage level associated with the first range.

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Номер записи: 125
13-02-2020 дата публикации

Adjustment of a pre-read operation associated with a write operation

Номер: WO2020033487A1
Автор: Jiangli Zhu, Tingjun Xie, Zhengang Chen, Zhenlei E. SHEN
Принадлежит: MICRON TECHNOLOGY, INC.

Data can be received at a memory sub-system. A characteristic of the memory subsystem can be identified. A read voltage level can be determined based on the characteristic of the memory sub-system. A read operation can be performed at the memory sub-system based on the read voltage level to retrieve stored data. The received data can be stored at the memory sub-system based on the stored data that was retrieved from the read operation that is based on the read voltage level.

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Номер записи: 126