СХЕМА ДЛЯ ГЕНЕРАЦИИ ОТРИЦАТЕЛЬНЫХ НАПРЯЖЕНИЙ

FIELD: electrical engineering. SUBSTANCE: circuit to generate negative voltage has first transistor Tx2 which first lead is connected to input lead E and which second lead is connected to output lead A of circuit and gate lead of it is connected via first capacitor Cb2 to first lead of clock signal, to second transistor Ty2 which first lead is connected to gate lead of transistor Tx2, which second lead is connected to second lead of transistor Tx2 and which gate lead is connected to first lead of transistor Tx2 and to second capacitor Cp2. First lead of capacitor Cp2 is connected to second lead of transistor Tx2 and second lead of capacitor is connected to second lead of clock signal. Transistors Tx2 and Ty2 are MOS transistors built in accord with technology of triple pocket. First lead of third transistor Tz2 is connected to second lead of transistor Tx2, second lead of transistor Tz2 is connected to pocket/pockets Kw carrying transistors Tx2, Ty2, Tz2 and gate lead of transistor Tz2 is connected to first lead of transistor Tx2. EFFECT: enhanced efficiency thanks to reduction of leakage currents. 6 cl, 6 dwg (19) 13) ВИ "” 2 189 686 ^С2 (51) МК’ 4 02 м 3/07, С 11 С 5/14, 16/06 РОССИЙСКОЕ АГЕНТСТВО ПО ПАТЕНТАМ И ТОВАРНЫМ ЗНАКАМ 12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ РОССИЙСКОЙ ФЕДЕРАЦИИ (21), (22) Заявка: 9911822509, 23.09.1997 (71) Заявитель: СИМЕНС АКЦИЕНГЕЗЕЛЛЬШАФТ (0Е) (24) Дата начала действия патента: 23.09.1997 (72) Изобретатель: БЛОХ Мартин (0Е), (30) Приоритет: 24.01.1997 ОЕ 197 02 535.8 ЛАУТЕРБАХ Кристл (ОЕ) (46) Дата публикации: 20.09.2002 (73) Патентообладатель: СИМЕНС АКЦИЕНГЕЗЕЛЛЬШАФТ (0Е) 4 (56) Ссылки: МО 96/23356 АЛ, 01.08.1996. КУ о 2009602 СЛ, 15.03.1994. ЕР 0616329 АЛ, (74) Патентный поверенный: 21.09.1994. ЕР 0319063 АЛ, 07.06.1989. ЦЗ Емельянов Евгений Иванович 5422586 А, 06.06.1995. ®) (85) Дата перевода заявки РСТ на национальную фазу: 24.08.1999 со (86) Заявка РСТ: < ОЕ 97/02154 (23.09.1997) © (87) Публикация РСТ: ©о М/О 98/33264 (30.07.1998) ...

Halbleitergerät, das Schwankungen im Substratpotenzial zu verhindern fähig ist

REGULATED SUBSTRATE VOLTAGE GENERATOR

Substratvorspannungsgenerator ohne Oszillator

Halbleiterspeichereinrichtung mit einem Normalbetriebsmodus und einem Eigenauffrischungsmodus und einem reduzierten Stromverbrauch und stabilen Betrieb in einem Datenhaltezustand

BACKUP POWER CIRCUIT FOR BIASING BIT LINES OF A STATIC SEMICONDUCTOR MEMORY

CIRCUIT D'ALIMENTATION DE SECOURS PAR BATTERIE DE FAIBLE PUISSANCE POUR UNE MEMOIRE A SEMI-CONDUCTEUR

L'INVENTION CONCERNE UN CIRCUIT D'ALIMENTATION DE SECOURS PAR UNE BATTERIE A FAIBLE PUISSANCE POUR UNE MEMOIRE A SEMI-CONDUCTEUR. UN COMPARATEUR DE TENSION 10 DETECTE SI L'ALIMENTATION PRINCIPALE EST INFERIEURE A UNE TENSION DE SECOURS SUR UNE BORNE DE COMMANDE WE. A LA DETECTION D'UNE BAISSE DE L'ALIMENTATION PRINCIPALE, LA MATRICE DES CELLULES DE MEMOIRE 50 EST ALIMENTEE PAR L'INTERMEDIAIRE DE LA BORNE DE COMMANDE. UN GENERATEUR 92 AUXILIAIRE A FAIBLE PUISSANCE PRODUIT ALORS UNE POLARISATION SUFFISANTE DU SUBSTRAT POUR MAINTENIR LES DONNEES MEMORISEES DANS LA MEMOIRE EN MODE DE SECOURS. L'INVENTION S'APPLIQUE A DES MEMOIRES DE CALCULATEURS.

CIRCUIT AND PROCESS Of EMERGENCY POWER SUPPLY TO POLARIZE the BINARY LINES Of a STATIC STORAGE HAVE SEMICONDUCTOR

CIRCUIT ET PROCEDE D'ALIMENTATION DE SECOURS POUR POLARISER LES LIGNES BINAIRES D'UNE MEMOIRE STATIQUE A SEMI-CONDUCTEUR

L'INVENTION CONCERNE UN CIRCUIT ET UN PROCEDE D'ALIMENTATION DE SECOURS POUR POLARISER LES LIGNES BINAIRES D'UNE MEMOIRE STATIQUE A SEMI-CONDUCTEUR. UN DISPOSITIF 44 DETECTE LA DISPARITION DE L'ALIMENTATION PRINCIPALE, UN DISPOSITIF 42 CONNECTE UNE SOURCE D'ALIMENTATION DE SECOURS 48 AUX CELLULES DE MEMOIRE 50 PAR L'UNE SELECTIONNEE WE DES BORNES DE COMMANDE A LA DETECTION DE LA DISPARITION DE L'ALIMENTATION ET UN DISPOSITIF 54 APPLIQUE UNE TENSION PREDETERMINEE PRODUITE PAR LA SOURCE D'ALIMENTATION DE SECOURS A CHACUNE DES LIGNES BINAIRES A LA DETECTION DE LA DISPARITION DE L'ALIMENTATION PRINCIPALE. L'INVENTION S'APPLIQUE NOTAMMENT A DES MEMOIRES DE CALCULATEURS.

CIRCUIT FOR ADJUSTING SUBSTRATE-BIAS VOLTAGE IN SEMICONDUCTOR MEMORY DEVICE

1. 청구범위에 기재된 발명이 속한 기술분야 1. TECHNICAL FIELD OF THE INVENTION 반도체 메모리장치의 전압발생회로 Voltage Generation Circuit of Semiconductor Memory Device 2. 발명이 해결하려고 하는 기술적 과제 2. The technical problem to be solved by the invention 반도체 메모리장치의 리프레시 특성에 따라 조절되는 기판전압을 발생시킴 Generates substrate voltage that is adjusted according to the refresh characteristics of semiconductor memory devices 3. 발명의 해결 방법의 요지 3. Summary of the Solution of the Invention 반도체 메모리장치의 기판전압발생회로는 발진제어신호에 의해 발진신호를 발생하는 발진수단과, 상기 발진신호에 의해 기판전압의 전위를 낮추어 차지펌핑하여 백바이어스전압을 발생하는 수단 및 기판전압의 레벨을 감지한 후 리프레시 특성에 따라 상기 발진제어신호의 주기를 조절하는 전압조절수단들을 구비한다. 그러므로 전압조절수단은 스위칭소자들을 선택적으로 제어되어 채널트랜지스터들의 채널 저항을 가변시킴으로서 반도체 메모리장치의 리프레시 특성에 따라 감지전압을 상승 또는 하강 조절할 수 있는 발진제어신호를 발생한다. The substrate voltage generation circuit of the semiconductor memory device includes oscillation means for generating an oscillation signal by an oscillation control signal, means for generating a back bias voltage by charge pumping by lowering the potential of the substrate voltage by the oscillation signal, and the level of the substrate voltage. And a voltage regulating means for adjusting the period of the oscillation control signal according to the refresh characteristic after sensing. Therefore, the voltage regulating means selectively controls the switching elements to vary the channel resistance of the channel transistors, thereby generating an oscillation control signal capable of raising or lowering the sensing voltage according to the refresh characteristics of the semiconductor memory device. 4. 발명의 중요한 용도 4. Important uses of the invention 반도체 메모리장치에서 리프레시 특성에 따라 조절된 기판전압을 발생시킴 Generates substrate voltage adjusted according to refresh characteristics in semiconductor memory device

BACK BIAS VOLTAGE GENERATOR

A back bias voltage generator is provided to improve a reliability of transistor junction by maintaining constant level to the back bias voltage regardless of change of external voltage(Vcc). The generator comprises: a reference voltage generating part(23) for generating an internal voltage(VREG) of constant level compared to internal voltage control signal(VREF); a back bias voltage sensor(24) for outputting an oscillation enable signal(OSCEN) according to the exteranl voltage(Vcc) and an oscillation enable signal(OSCEN) accroding to the internal voltage(VREG); an oscillator(25) for generating an oscillation signal in accordance with the OSCEN and outputting VBBOKB signal to the reference voltage generating part(23); and a back bias voltage pumping part(26) for generating a back bias voltage(VBB). Copyright 1999 KIPO ...

DRIVER CIRCUIT FOR CHARGING CHARGE NODE

The present invention relates to a driver circuit. The driver circuit of the present invention includes a clamp transistor having a clamp gate, a first clamp node, and a second clamp node connected to a charging node, a comparison voltage transistor, an amplification transistor, a bias transistor, and a charge circuit. The comparison voltage transistor includes a comparison voltage gate configured to receive a reference voltage, a first comparison voltage node configured to receive a first voltage, and a second comparison voltage node configured to output a comparison voltage. The amplification transistor includes an amplification gate connected to the charging node, a first amplification node connected to the second comparison voltage node of the comparison voltage transistor and configured to receive the comparison voltage, and a second amplification node connected to the clamp gate of the clamp transistor. The bias transistor includes a bias gate configured to receive a bias voltage, ...

MULTI-GENERATOR, PARTIAL ARRAY Vt, TRACKING SYSTEM TO IMPROVE ARRAY RETENTION TIME

Improved transistor array device performance is obtained by use of bias voltage regulation which tracks with a fraction of a monitor transistor threshold voltage. The circuitry and methods are especially useful for improving the performance of transistor array devices such as DRAM and embedded DRAM. These benefits are obtained especially when at least two bias voltages normally supplied to the array are regulated by tracking with a fraction of an actual threshold voltage of at least one monitor transistor. Performance improvements include improved reliability, wider operational bias conditions, reduced power consumption and (in the case of memory cells) improved retention time.

Semiconductor device

A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Semiconductor memory device having the operating voltage of the memory cell controlled

Disclosed is an SRAM circuit which can be operated at a reduced operation margin, especially at a low operating voltage by increasing or optimizing the operation margin of the SRAM circuit. The threshold voltage of the produced transistor in the SRAM circuit is detected to compare the operating voltage of a memory cell with the operating voltage of a peripheral circuit in order to adjust it to the optimum value, and the substrate bias voltage is further controlled.

Multiple level voltage generator for semiconductor memory device

A multiple level voltage generator for a semiconductor memory device, comprising a back bias voltage charge pumping circuit for pumping charge to a back bias voltage node, a back bias voltage level detector for detecting the level of a back bias voltage at the back bias voltage node and generating first and second back bias voltage detection signals in accordance with the detected result, a high voltage charge pumping circuit for pumping charge to a high voltage node, a high voltage level detector for detecting the level of a high voltage at the high voltage node and generating first and second high voltage detection signals in accordance with the detected result, a control logic circuit for generating a control signal in response to the second back bias voltage detection signal from the back bias voltage level detector and the second high voltage detection signal from the high voltage level detector, and an oscillator for generating first and second output signals in response to the control ...

Oscillator receiving variable supply voltage depending on substrate voltage detection

A low voltage current source generates low voltage signals for powering a variable frequency oscillator. The low voltage signals are at a slightly higher voltage until a negative substrate bias is achieved. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed and at a higher frequency when charge pumping is in fact needed or when charge pumping will most likely be needed. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump system. Voltage translation circuitry translates the low voltage current source signals into higher voltage signals which are used to translate the substrate voltage from its negative value to a positive value so that the substrate voltage may be compared to a reference voltage using a conventional comparator. When the substrate voltage is above the desired level, the comparator generates a pump activating signals ...

Low-voltage bias generator based on high-voltage supply

Apparatus and methods are disclosed for providing a bias, comprising a bias generator circuit including a high voltage (HV) circuit configured to generate a regulated high voltage (HV) from an HV line and provide the regulated HV at an HV regulated line and a low voltage (LV) circuit configured to generate a low voltage (LV) differential from the HV line and to provide the LV differential at an LV line, wherein the LV circuit is configured to direct current used to generate the LV differential into the HV regulated line.

Circuits, systems and methods for controlling substrate bias in integrated circuits

Substrate bias control circuitry 100 is provided which includes a bias sensor 101 for measuring a bias voltage of a substrate and generating a control signal and response. A master oscillator 102 is provided for generating a first driving signal, a frequency of the first driving signal adjusted by the control signal generated by the bias sensor 101. A first charge pump 103 is provided for pumping electrons into a substrate in response to the first driving signal. A slave oscillator generates a second driving signal, a frequency of the second driving signal is determined from the frequency of the first driving signal using a phase-locked loop. A second charge pump 105 is provided for pumping electrons into the substrate in response to the second driving signal.

SEMICONDUCTOR MEMORY DEVICE HAVING BURN-IN TEST FUNCTION

BULK VOLTAGE DETECTOR

A bulk voltage detector comprises a voltage sensor configured to receive a bulk voltage and compare the received bulk voltage with a target level to provide a first detection signal having a voltage gain that is increased within a predetermined voltage range around the target level, and an amplifier coupled with the voltage sensor, the amplifier configured to receive the first detection signal and invert and amplify the first detection signal.

SIGNAL PROCESSING CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SIGNAL PROCESSING CIRCUIT

Provided is a semiconductor device that can operate stably. All transistors included in the semiconductor device are transistors each of which contains an oxide semiconductor in a channel formation region. The transistor includes a front gate and a back gate. The threshold voltage of the transistor can be shifted in the positive direction or the negative direction depending on a potential applied to the back gate. To make the transistor in a conducting state, the threshold voltage is shifted in the negative direction to increase the amount of current flowing in the transistor, and to make the transistor in a non-conducting state, the threshold voltage is shifted in the positive direction to decrease the amount of current flowing in the transistor. A circuit of the semiconductor device that utilizes this effect and includes transistors all having the same polarity is formed.

Systems and methods for dual standby modes in memory

The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.

BACK BIAS VOLTAGE GENERATOR

PURPOSE: To keep the back bias voltage at a fixed level to avoid breakage of integrated circuit elements, irrespective of the variation of an external voltage by cutting off the output path of the external voltage and outputting an oscillate-enable signal with the internal voltage before this voltage reaches a desired level. CONSTITUTION: In the initial stage beginning feeding an external voltage VCC, a back bias voltage sensor 24 generates an oscillate enable signal OSCEN with the external voltage VCC before an internal voltage VREG reaches a fixed level. When this voltage VRGE reaches desired level, the output path of the voltage VCC is cut off and internal voltage generator 23 outputs an oscillate enable signal OSCEN with the internal voltage VREG, thereby keeping a back bias voltage VBB at a fixed level, irrespective of the variation of the external voltage VCC. COPYRIGHT: (C)1995,JPO ...

Semiconducting memory device on substrate - contains voltage supply converter, bias voltage generator drive by external or internal supply depending on memory state

The device contains a converter (2) of an external supplyvoltage (Vcc) to a lower internal supply voltage (IVcc), a memory device (1) supplied by the internal voltage for storing data, a substrate bias voltage generator (3) for holding the substrate (CH) at a constant voltage and a switching device. The bias voltage generator is driven by the external or internal supply voltage. The switching device changes from one supply to the other according to whether the memory device is active or not. USE/ADVANTAGE - For a semiconducting memory device on a substrate. The current consumption of the substrate bias voltage generator device is reduced.

Halbleiterspeichereinrichtung

Substratspannungs-Generatorschaltung

Analog MISFET mit Schwellspannungsregler

SCHALTUNG ZUR ERZEUGUNG EINER RUECKWAERTSREGELSPANNUNG

Halbleiterspeicheranordnung mit verschiedenen Substrat-Vorspannungsschaltungen.

Composite mode substrate voltage generation circuit for dynamic random access memory

Switching driver circuitry

A switching driver circuit 400 includes an output stage 201 and a switch network (Fig.2, 202). The output stage includes an output switch SWO1 connected between a first switching voltage node N1 and an output node 203 for driving a load. The switching network is operable in a plurality of modes where the first switching voltage is different in each mode. In one mode the switching voltage node N1 is coupled to a positive voltage and in another mode the node N1 is coupled to a ground voltage supply via a first switching path (Fig.2, SW1C, SW1B). The driver circuit further includes an n-well switching block 410 operable, when the first switching voltage node is coupled to a positive voltage, to connect the n-well of the first output switch to the switching voltage node, and, when the first switching voltage node is coupled to the ground voltage, to connect the n-well of the first output switch to a first ground which is separate to the first switching voltage node and independent of the first ...

CIRCUIT DE GENERATION DE TENSION DE POLARISATION DE SUBSTRAT

L'INVENTION CONCERNE LA TECHNOLOGIE DES SEMICONDUCTEURS. UN CIRCUIT DE GENERATION DE TENSION DE POLARISATION DE SUBSTRAT POUR UN DISPOSITIF DE MEMOIRE A SEMICONDUCTEURS COMPREND UN OSCILLATEUR 10 QUI GENERE UN SIGNAL CARRE DE FREQUENCE SPECIFIEE, UN AMPLIFICATEUR-SEPARATEUR 20 ET UN CIRCUIT DE POMPE DE CHARGE 30 QUI PRODUISENT UNE TENSION DE POLARISATION DE SUBSTRAT, ET UN CIRCUIT DE LIMITATION 40 QUI EST BRANCHE ENTRE LA SORTIE DU CIRCUIT DE POMPE DE CHARGE ET LA MASSE, DE FACON A LIMITER A UNE PLAGE SPECIFIEE LA TENSION DE POLARISATION DE SUBSTRAT QUE FOURNIT LE CIRCUIT, MALGRE LES VARIATIONS DE LA TENSION D'ALIMENTATION. APPLICATIONS AUX MEMOIRES MOS.

SUBSTRATE BIAS GENERATING CIRCUIT FOR A SEMICONDUCOR MEMORY DEVICE

SUBSTRATE BIAS GENERATOR CIRCUIT

SEMICONDUCTOR DEVICE WITH LESS INFLUENCE OF NOISE

VOLTAGE GENERATING CIRCUIT, SEMICONDUCTOR MEMORY APPARATUS HAVING SAME, AND OPERATING METHOD

According to an embodiment of the present invention, a voltage generation circuit includes: a comparison unit which compares a reference voltage and a feedback voltage to output a comparison signal to a first node; an output unit which generates an internal voltage and a feedback voltage in response to a potential level applied to the first node; and a control unit which discharges the first node when a level of the internal voltage falls below a preset level. COPYRIGHT KIPO 2016 (130) Control unit (120) Output unit (110) Comparison unit ...

REFERENCE CIRCUIT TO COMPENSATE FOR PVT VARIATIONS IN SINGLE-ENDED SENSE AMPLIFIERS

Voltage supply switching device for nonvolatile memories in MOS technology

Two P channel selection transistors are inserted in respective connecting circuit branches between two external pins with voltages Vcc and Vpp respectively and an internal node. A switching circuit controls said selection transistors. Circuit means are provided to hold the body bias of the selection transistors at a voltage equal to the highest voltage present from time to time at said external pins.

Analogue misfet with threshold voltage adjuster

A threshold voltage or a channel potential of a MIS device can be set in an analogue fashion. A MIS device includes a multi-layer structure having a gate insulating film in which an oxide film, a nitride film and an oxide film are laminated in that order. The threshold voltage or channel potential of the MIS device can be controlled by an amount of electric charges injected into the nitride film.

A METHOD AND A CIRCUIT FOR ADAPTIVE REGULATION OF BODY BIAS VOLTAGES CONTROLLING NMOS AND PMOS TRANSISTORS OF AN IC

A method and a circuit for adaptive regulation of body bias voltages controlling nmos and pmos transistors of an integrated circuit includes a digital circuit, a counter, a control unit and a charge pump. A first ring oscillator monitor measures a period duration of nmos transistors and a second ring oscillator monitor measures a period duration of pmos transistors. A first closed control loop adaptively regulates the performance cn of the body bias controlled nmos transistors of the digital circuit by comparing the measured period duration of nmos dominated first ring oscillator monitor to a period duration of a reference clock and a second closed control loop adaptively regulating the performance cp of the body bias controlled pmos transistors of the digital circuit by comparing the measured period duration of pmos dominated second ring oscillator monitor to the period duration of the reference clock.

Internal voltage generator with reduced power consumption

A first periodic pulse is rectified to generate an internal voltage by a charge pump circuit. A level detector is provided for detecting whether or not the internal voltage reaches a desired level. The charge pump circuit is controlled by a controller in accordance with the detection signal so that the internal voltage may take the desired level. A switch element switched by a second periodic pulse is provided in the current path of the level detector. A leakage current path for allowing a lower electric current than the electric current to flow through the former current path is provided between the output terminal of the charge pump circuit and a predetermined power supply terminal.

Non-volatile memory with a well bias generation circuit

A leakage measuring circuit includes a bias input node control circuit and provides a signal indicative of a leakage current through the bias input node. The bias input node control circuit includes a first input to receive an indication of a reference voltage, a second input to receive an indication of a voltage of the bias input node, and an output to bias the bias input node at the reference voltage based on a relationship between the first and second input. A well voltage bias circuit provides a well bias voltage and includes a well bias control circuit including a first input to receive the signal indicative of the leakage current, a second input to receive a signal indicative of a reference leakage current value, and an output for controlling the well bias voltage based on a relationship between the first and second input of the well bias control circuit.

Programmable logic switch

One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory.

Semiconductor integrated circuit device having a hierarchical power source configuration

A main source voltage transmission line for transmitting a source voltage VCH as one power source and a sub source voltage transmission line are provided corresponding to a gate circuit. A resistive element having a high resistance is provided between the main source voltage transmission line and the sub source voltage transmission line. A capacitor comprised of an insulated gate field effect transistor is connected to the sub source voltage transmission line. The gate circuit is operated with a voltage on the sub source voltage transmission line as an operating source voltage. Thus, the voltage on the sub source voltage transmission line can be maintained at a voltage level that balances with a sub-threshold current flowing through the gate circuit, and the voltage on the sub source line can be stably maintained by the capacitor. A semiconductor memory device can be realized which reduces the sub-threshold current that flows upon standby of the gate circuit and minimizes a difference in ...

Time domain ramp rate control for erase inhibit in flash memory

When performing an erase on a flash type non-volatile memory with a NAND type of structure, techniques are presented for inhibiting erase on selected word lines, select lines of programmable select transistors, or some combination of these. The voltage along the selected control lines are initially ramped up by the level on a corresponding input line, but then have their voltage raised to an erase inhibit level by capacitive coupling with the well structure. The level of these input signals are ramped up with the erase voltage applied to the well structure, but with a delay based upon the coupling ratio between the control line and the well.

Dual level substrate voltage generator

A dual-level substrate voltage generator for generating a second voltage with a level higher than that of a first voltage and maintaining the level of the first voltage quickly and stably, thereby reducing sudden current dissipation during an active or pre-charge mode is disclosed. The dual-level substrate voltage generator includes a first substrate voltage generation block and a first voltage detecting block are used to provide the first substrate voltage at an optimum level. A second voltage generating block having a level lower than that of the first substrate voltage and a second voltage detecting block are used to provide the second substrate voltage at the optimum level to the second voltage generating block. A switching block divides a charge between the first and second substrate voltages.

Charge pump for a semiconductor substrate

MULTI-GENERATOR, PARTIAL ARRAY V t?, TRACKING SYSTEM TO IMPROVE ARRAY RETENTION TIME

Verbesserungen in oder in Beziehung zu integrierten Schaltungen

Semiconductor memory device e.g. DRAM

The memory device includes several memory blocks, a CBR determn. circuit (121), and two wordline pumps (123,125). Also provided is a separate operations circuit which operates different numbers of memory blocks depending on the particular mode shown be the determn. circuit. The two wordline pumps produce an internal voltage, from the basis of an external voltage source, to supply each of the memory blocks being operated at a given time. The internal voltage is produced in response to the CBR mode signal and has different delivery capabilities depending on the CBR signal. That is, one wordline pump (123) supplies an internal voltage regardless of the mode signal while the other (125) is active for one particular mode signal and inactive for another mode signal.

SWITCHING CONFIGURATION FOR PRODUCING NEGATIVE TENSIONS

RULE CIRCUIT FOR A SUBSTRATE PRE-LOADING GENERATOR

REGULATED MOS SUBSTRATE BIAS VOLTAGE GENERATOR FOR A STATIC RANDOM ACCESS MEMORY

Semiconductor memory device with reduced power consumption and stable operation in data holding state

VOLTAGE GENERATING CIRCUIT SUBSTRATE BIAS

반도체 장치

... 산화물 반도체를 사용한 기능 회로의 문턱 전압을 안정적으로 제어한다. 가변 바이어스 회로, 백 게이트를 포함한 모니터용 산화물 반도체 트랜지스터, 전류원, 차동 증폭기, 기준 전압원, 및 백 게이트를 포함한 산화물 반도체 트랜지스터를 포함한 기능 회로가 제공된다. 전류원은 모니터용 산화물 반도체 트랜지스터의 소스와 드레인 사이에 전류를 공급하여 이 전류에 따른 게이트-소스 전압을 생성한다. 차동 증폭기는 이 전압과 기준 전압원의 전압을 비교하고, 차분을 증폭하고, 이 결과의 전압을 가변 바이어스 회로에 출력한다. 가변 바이어스 회로는 차동 증폭기의 출력에 의하여 제어되고, 모니터용 산화물 반도체 트랜지스터의 백 게이트 및 기능 회로에 포함되는 산화물 반도체 트랜지스터의 백 게이트에 전압을 공급한다.

SEMICONDUCTOR MEMORY DEVICE

PURPOSE: To reduce the power consumption in a data holding state by generating a first substrate voltage and supplying it to the substrate if an internal power supply voltage is larger than a prescribed value and generating a second substrate voltage which is smaller than the first substrate voltage, and supplying the second substrate voltage to the substrate if the internal power supply voltage is smaller than the prescribed value. CONSTITUTION: During a self-refresh operation mode, a signal/BBUL is activated to an L level, a VBB level detecting circuit 501 is deactivated and a VBB level detecting signal, which is always in the L level regardless of the absolute value of the substrate voltage, is outputted. If a VBB level detecting circuit 503 is activated and the absolute value of the substrate voltage is less than a voltage VB2, which is determined by the threshold value of an N channel MOS transistor NT3, the VBB level detecting signal is activated to an H level. If the absolute value ...

VOLTAGE GENERATOR CIRCUIT GENERATING STABLE MEGATIVE POTENTIAL

본 발명에 따른 전압 발생기 회로는 정의 전압으로 발진하는 제1클럭신호에 응답하여 부의 전압으로 발진하는 제1의 부성클럭신호를 발생시키기 위한 제1부성전위발생기회로와, 정의 전압으로 발진하는 제2클럭신호에 응답하여 부의 전압으로 발진하는 제2의 부성클럭신호를 발생시키며, 제1의 클럭신호가 부가되는 크기 전압의 크기보다 큰 크기를 갖는 제2의 부성전위발생기회로와, 제2클럭신호가 부가됨에 따라 가장 낮은 제1클럭신호의 전압을 전달하는 출력회로를 갖는다. The voltage generator circuit according to the present invention includes a first negative potential generator circuit for generating a first negative clock signal oscillating with a negative voltage in response to a first clock signal oscillating with a positive voltage, and a second oscillating voltage with a positive voltage. A second negative clock signal generating a second negative clock signal oscillating with a negative voltage in response to the clock signal, the second negative potential generator circuit having a magnitude larger than the magnitude of the magnitude voltage to which the first clock signal is added, and the second clock signal; Has an output circuit which delivers the voltage of the lowest first clock signal as is added.

HIGH-VOLTAGE SWITCH CIRCUIT, AND CONDUCTIVE MEMORY DEVICE INCLUDING SAME

The present invention relates to a HIGH-VOLTAGE SWITCH CIRCUIT AND a CONDUCTIVE MEMORY DEVICE INCLUDING the SAME. The present invention comprises: a switching portion including a first depletion-mode high-voltage transistor and a first high-voltage transistor connected in series between an input terminal and an output terminal; and a control signal generator configured to apply a control signal having a potential level identical to input voltage applied to the input terminal of the first depletion-mode high-voltage transistor in response to a first enable signal and a second enable signal. Thus, the present invention is able to switch high voltage without a potential drop. COPYRIGHT KIPO 2017 ...

DATA PIN REFERENCE VOLTAGE GENERATING CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING SAME

A data pin reference voltage generating circuit according to the present invention includes a voltage difference storing part which accumulates a difference between a reference voltage and an input signal received by a data pin during a predetermined time, in response to an amplification activation signal, and stores it, a code generator which generates a voltage generation code based on a voltage difference stored in the voltage difference storing part, and a reference voltage generator which renews the reference voltage and generates it based on the voltage generation code. So, reliability can be improved. COPYRIGHT KIPO 2016 (100) Voltage difference storing part (200) Code generator (300) Reference voltage generator (400) Input buffer ...

BACKUP POWER CIRCUIT FOR BIASING BIT LINES OF A STATIC SEMICONDUCTOR MEMORY

A circuit for biasing the bit lines of a static semiconductor memory when each of the cells (150) within the memory is being powered by a backup power source due to failure of the primary power source. The bit lines (52) connected to the cells within the array (50) are connected to transistors (54) which bias the bit lines (52) to a high voltage upon detection of failure of the primary power for the computer. The bit lines (52) are maintained at a high voltage level to prevent discharge of a data storage node (156) through an access transistor (164) of a memory cell (150). Biasing of the bit lines (52) further prevents the integrated circuit substrate (150) from being driven excessively positive by capacitive coupling between the substrate (150) and the bit lines (52) when the primary power is restored to the circuit.

Charge pump substrate bias with antiparasitic guard ring

The region constituting the rectify-charge pump circuit of a self substrate bias circuit is surrounded by a capacitive region, and the fluctuated minority carriers induced in this region are absorbed.

Semiconductor integrated circuit incorporated with substrate bias control circuit

The semiconductor IC according to this invention comprises an internal circuit including a plurality of transistors formed on a P-type or an N-type substrate (or a well) which carries out a prescribed signal processing operation during the time of operation mode, a standby detection circuit which generates a standby detection signal of active level by detecting standby mode, a bias potential generating circuit which generates a forward bias potential from the substrate (well) of the transistor to the source electrode, and a switching circuit which supplies to the substrate (well) the potential of the source electrode and the bias potential in response to the active level and the inactive level, respectively, of the standby detection signal. At the time of the operation mode, a high speed operation is secured by bringing the transistors to a low threshold voltage by receiving the supply of the bias potential, while at the time of the standby mode, the generation of malfunctions and defective ...

Voltage generator circuit generating stable negative potential

The voltage generator circuit according to the invention has a first negative potential generator circuit to generate a first clock signal going negative and oscillating at negative voltage in response to a first clock signal oscillating at positive voltage, a second negative potential generator circuit to generate, in response to a second clock signal oscillating at positive voltage, a second clock signal going negative and oscillating at negative voltage and having an amplitude greater than the amplitude voltage of the first clock signal going negative, and an output circuit to deliver the lowest voltage of the first clock signal in response to the second clock signal going negative.

Method and apparatus for biasing the substrate of an integrated circuit to an externally adjustable voltage

A substrate biasing circuit operates in either a test mode or a normal operating mode. The substrate biasing circuit includes a voltage generating circuit generating a substrate biasing voltage at an output terminal and a control terminal controlling the magnitude of the substrate voltage. When the voltage at the control terminal is more positive than a predetermined value, the voltage generating circuit gradually drives the substrate more negative. When the voltage at the control input of the voltage generating circuit is less than the predetermined value, the output terminal of the voltage generating circuit essentially floats. In normal operation, the output terminal of the voltage generating circuit is also coupled to the control terminal so that the substrate voltage is regulated at the predetermined negative voltage. Alternatively, the substrate may be coupled to ground and the voltage generating circuit disabled during normal operation. In a test mode, the control terminal is coupled ...

Apparatus and method for adjusting the threshold voltage of MOS transistors

An apparatus and method for adjusting the effective threshold voltage of a MOS transistor is disclosed. Reference voltage generation circuitry is used for generating a first voltage signal. Threshold voltage monitoring circuitry that includes the MOS transistor is used for measuring the effective threshold voltage of the MOS transistor and for generating a second voltage signal. Feedback circuitry compares the first voltage signal to the second voltage signal and adjusts the effective threshold voltage of the MOS transistor so that the first voltage signal is substantially equal to the second voltage signal. The effective threshold voltage of the MOS transistor is adjusted by adjusting its source-body voltage potential. The method includes the steps of generating a first voltage signal, measuring the effective threshold voltage of the MOS transistor, generating a second voltage signal, comparing the first voltage signal to the second voltage signal, and adjusting the effective threshold ...

Semiconductor integrated circuit

Transistors are supplied with either a first power supply voltage or a second power supply voltage lower than the first power supply voltage. During an operation period of the transistors, substrate voltages of the transistors are set at a value between the first power supply voltage and the second power supply voltage. The substrate voltages are changed to lower threshold voltages of the transistors so that the transistors improve in drivability and operating speed. Therefore, neither a booster for generating higher voltages nor a pumping circuit for generating negative voltages is particularly required. This allows a reduction in layout size. Besides, in accordance with the operating state of the semiconductor integrated circuit, the transistor characteristics can be easily changed by changing the threshold voltages of the transistors.

Applying adaptive body bias to non-volatile storage based on number of programming cycles

Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.

Semiconductor integrated circuit device having a hierarchical power source configuration

A main source voltage transmission line for transmitting a source voltage VCH as one power source and a sub source voltage transmission line are provided corresponding to a gate circuit. A resistive element having a high resistance is provided between the main source voltage transmission line and the sub source voltage transmission line. A capacitor comprised of an insulated gate field effect transistor is connected to the sub source voltage transmission line. The gate circuit is operated with a voltage on the sub source voltage transmission line as an operating source voltage. Thus, the voltage on the sub source voltage transmission line can be maintained at a voltage level that balances with a sub-threshold current flowing through the gate circuit, and the voltage on the sub source line can be stably maintained by the capacitor. A semiconductor memory device can be realized which reduces the sub-threshold current that flows upon standby of the gate circuit and minimizes a difference in ...

VERTICAL MEMORY DEVICE INCLUDING SUBSTRATE CONTROL CIRCUIT AND MEMORY SYSTEM INCLUDING THE SAME

A nonvolatile memory device comprises a first semiconductor layer including, an upper substrate, and a memory cell array in which a plurality of word lines on the upper substrate extend in a first direction and a plurality of bit lines extend in a second direction. The nonvolatile memory device comprises a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions, the second semiconductor layer including, a lower substrate, and a substrate control circuit on the lower substrate and configured to output a bias voltage to the upper substrate. The second semiconductor layer is divided into first through fourth regions, each of the first through fourth regions having an identical area, and the substrate control circuit overlaps at least a portion of the first through fourth regions in the third direction.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, FABRICATION THEREOF AND INTERNAL VOLTAGE GENERATION CIRCUIT

PURPOSE: To obtain a high speed low power consumption semiconductor memory by reducing the sub-threshold current at the time of stand-by of a gate circuit and lowering the voltage difference between a main and sub power supply voltage transmission lines. CONSTITUTION: A main power supply voltage transmission line 100 for transmitting a power supply voltage VCH and a sub-power supply voltage transmission line 110 are provided, as one power supply, for a gate circuit G. A high resistance element R is connected between main and sub-power supply voltage transmission lines 100, 110 and a capacitor C comprising an insulated gate FET is connected with the sub-power supply voltage transmission lines 110. The fate circuit G is operated with a voltage VC on the sub-power supply voltage transmission lines 110. Consequently, the voltage on the sub-power supply voltage transmission lines 110 is sustained at a level being balanced with the sub- threshold current of the gate circuit G and the voltage ...

Low-power battery backup circuit for semiconductor memory

A battery backup circuit for an MOS memory which has a multiplexed pin (WE) that functions to provide backup power to a memory cell array (50) upon loss of primary power Vcc. A voltage comparator (10) detects when the primary power Vcc becomes less than the backup voltage on the WE terminal. Upon detection of loss of primary power the memory cell array (50) is powered by a connection to the WE terminal. A primary power status signal (POK) indicates the status of the primary power and is driven to a state indicating insufficient circuit voltage for normal operation when Vcc drops below an acceptable limit or when there is inadequate substrate bias. The circuit of the present invention further generates an inhibit signal to prevent the operation of peripheral circuits (70) to write data into the memory cell array (50) upon detection of a failure of primary power. The inhibit signal is generated when primary power is lost or when the substrate bias is inadequate. A low-power auxiliary pump ...

TWO-FASHION PRE-LOADING GENERATOR WITH SMALL ACHIEVEMENT

Super low-power generator system for embedded applications

Circuit for detecting the level of reverse bias in a semiconductor memory device

Détecteur de niveau de polarisation inverse utilisé pour un dispositif à semiconducteurs dans lequel un courant de détection (150) pour détecter la tension de polarisation inverse (VBB) est empêché de s'écouler directement dans le substrat (ou dans la borne de tension de polarisation inverse). La grille d'un transistor PMOS (50) est alimentée avec la tension de polarisation inverse tandis que la source est alimentée avec la tension de la masse, de sorte qu'un circuit de pompage (300) effectue l'opération de pompage pour augmenter la tension de polarisation inverse lorsque la tension de polarisation inverse (VBB) est plus petite qu'un niveau de tension prédéterminé; autrement, le circuit de pompage (300) est coupé, en réduisant par ce moyen la tension de polarisation inverse.

MULTI-GENERATOR, PARTIAL ARRAY Vt, TRACKING SYSTEM TO IMPROVE ARRAY RETENTION TIME

REGULATING CIRCUIT FOR A SUBSTRATE BIAS VOLTAGE GENERATOR

Internal source voltage generator of semiconductor memory device

Nonvolatile memory device having single-layer gate, method of operating the same, and memory cell array thereof

SEMICONDUCTOR MEMORY

A semiconductor memory in which the driving power can be improved during operation and the leak current can be reduced during standby without needing a significant change of the design of the current semiconductor memory. The semiconductor memory comprises a memory cell composed of a transistor having a back gate to which the back gate voltage is supplied, a switching transistor which is connected to the input/output side of the memory cell, switched by a row line signal and has a back gate to which the back gate voltage is supplied and a back gate voltage control circuit for controlling the back gate voltage according to an address signal.

Method and apparatus for controlling substrate and well biases for reduced power requirements

An SRAM circuit that includes a biasing circuit adapted to selectively bias the transistors of the SRAM array to lower the threshold voltage of selected transistors. The SRAM circuit includes well voltages and positive voltages that are selectively different, and substrate voltages and ground voltages that are selectively different.

System and interface circuit for driving data transmission line to termination voltage

A system includes a data transmission unit, a termination resistor and a data reception unit. The data transmission unit may drive a data transmission line based on data, and drive the data transmission line to a voltage level corresponding to a termination voltage during a specified operation period. The termination resistor may be coupled between the data transmission line and a termination node. The data reception unit may receive a signal transmitted through the data transmission line.

Voltage pump switch

A standard single well (e.g., n-well) complementary metal-oxide-semiconductor (CMOS) process compatible voltage pump switch routes -10 Volt for erasing a floating gate transistor when an IC substrate is grounded at 0 Volts. The voltage pump switch also routes extreme positive voltages for programming or reading the floating gate transistor. P-channel field-effect transistors (PFETs) multiplex both the read/write/programming and erasing voltages, such as in a block-erasable flash electrically erasable and programmable read only memory (EEPROM). The voltage pump switch includes a charge pump for providing to the PFET routing the erasing voltage a gate voltage that is more negative than the erasing voltage by the PFET turn-on threshold voltage (VT) magnitude.

Substrate voltage generating circuit of semiconductor memory device

A substrate voltage generating circuitry for a dynamic random access memory (DRAM) generates the substrate voltage using an intermittently enabled charge pump. The value to which the substrate voltage is regulated is adjusted responsive to the static refresh and dynamic refresh characteristics of the memory cells. The adjustment is made in the portion of the substrate voltage generating circuit used for sensing the substrate potential, using fusible links that can be interrupted or cut with a laser beam. Novel circuitry for sensing the substrate potential, which does not load the substrate so as to dissipate charge placed thereon by the charge pump, is used in preferred substrate voltage generating circuitry.

Circuit for clamping enable clock in a semiconductor memory device

A circuit for a clamping an /RAS signal in a DRAM. The bit line pre-charge generator is activated after the set-up of the VBB voltage, so that /RAS signals may be supplied to the chip after the bit line pre-charge voltage (VBLP) has reached the desired level, thereby preventing malfunction of the sense amplifiers. The circuit includes: a VBB sensor for producing VBB set-up signal S1 when a back bias voltage VBB in the semiconductor memory device has reached a desired level; a power-up generator for producing a power-up signal S2 when power in the semiconductor memory device is set-up; a VBLP generator for generating a bit line pre-charge voltage VBLP; a VBLP controller for holding the VBLP voltage to a ground voltage level according to the S1 and S2 signals; a VBLP sensor for generating VBLP set-up signal S3 when the VBLP voltage has reached a desired level; a /RAS pass signal generator for producing a /RAS pass signal S4 according to the S3 and S2 signals; a NOR circuit for controlling ...

Semiconductor device

A substrate voltage control technique that prevents the operating speed from being decreased and suppresses a leakage current due to a lower threshold voltage with respect to a low voltage use. Since a center value of the threshold voltages is detected by plural replica MOS transistors, and a substrate voltage is controlled to control a center value of the threshold voltages, thereby making it possible to satisfy a lower limit of the operating speed and an upper limit of a leakage current of the entire chip. On the other hand, the substrate voltage is dynamically controlled during the operation of the chip, thereby making it possible to decrease the center value of the threshold voltages when the chip operates to improve the speed, and to increase the center value of the threshold voltages after the operation of the chip to reduce the leakage current of the entire chip.

Semiconductor device with multiple power sources

Well bias voltages are generated in accordance with a logic power supply voltage and a memory power supply voltage. The transistor included in a control circuit in a memory core is constituted of a logic transistor manufactured through the same manufacturing steps as those for the transistors of a logic formed on the same semiconductor substrate. Well bias voltages (VBB, VPP) are applied to a back gate of this logic transistor. A memory integrated with a logic on a common semiconductor substrate is provided which allows a transistor of a control circuit therein to be manufactured through the same manufacturing process as that of the logic and allows reduction of current consumption.

INTERNAL SOURCE VOLTAGE GENERATING CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE

An internal source voltage generating circuit includes a comparison voltage generator which receives reference and internal source voltages, outputs to a second node a comparison voltage differentially amplified responsive to a voltage of a first node according to a difference between the reference and internal source voltages, and allows a driving current to flow from a third node to a fourth node. An internal voltage driver transfers an external source voltage to an output node responsive to the comparison voltage. A driving current generator increases the driving current flowing from the third node to the fourth node responsive to the voltage of the first node which rises when the internal source voltage abruptly drops. The internal source voltage generating circuit is insensitive to variation of an external source voltage, exhibits improved response time when an internal source voltage abruptly drops, and stably generates an internal source voltage.

Method and system for regulating memory, and semiconductor device

A method for regulating the memory includes operations as follows. A mapping relationship among temperatures of a transistor, body bias voltages of the transistor, and data writing time of the memory is acquired, a current temperature of the transistor is acquired, the body bias voltage is regulated based on the current temperature and the mapping relationship, to enable the data writing time corresponding to the regulated body bias voltage to be within a preset writing time.

Semiconductor device capable of preventing fluctuations of substrate potential

SEMICONDUCTOR STORAGE DEVICE

PROBLEM TO BE SOLVED: To realize a DRAM(dynamic random access memory) shallowing a substrate voltage in its level at the time of a disturb test mode and a self refresh mode without increasing an area penalty. SOLUTION: This storage device is provided with a switch circuit 40 activating a shallow level detector 38 and inactivating a deep level detector 36 when a disturb test signal TESTUBBS or a self refresh signal/BBU is activated. Thus, the shallow level of substrate voltage VBB equal to the detection level of the shallow level detector 38 is generated by a substrate voltage generation circuit 34 not only at the time of the disturb test mode, but also at the time of the self refresh mode. COPYRIGHT: (C)1999,JPO ...

Spannungsgenerator für eine Halbleiterspeichervorrichtung mit Standby-Betriebsart

Semiconductor DRAM device for portable computer

The device has a substrate voltage detector activating a substrate voltage generator when a detected value is below a threshold value. A second substrate voltage detector activates the substrate voltage generator when the detected value is less than a second threshold value. An activation device activates the first detector (36) in the normal operation mode and activates the second detector (38) in the test and refresh modes.

MOS SUBSTRATE BIAS REGULATOR FOR RAM

WELL REGIONS OF SEMICONDUCTOR DEVICES

Semiconductor devices

A semiconductor device includes a delay time adjustment circuit and an address input circuit. The delay time adjustment circuit adjusts a point in time when charges are supplied to internal nodes according to a voltage level of a back-bias voltage in response to a test mode signal. The delay time adjustment circuit also delays an active signal by a first delay time varying according to amounts of charge of the internal nodes to generate a bank selection signal. The address input circuit is driven by the back-bias voltage. The address input circuit receives an address in response to the bank selection signal to generate an internal address. The address input circuit delays the address by a second delay time varying according to a voltage level of the back-bias voltage.

LOW-VOLTAGE BIAS GENERATOR BASED ON HIGH-VOLTAGE SUPPLY

Apparatus and methods are disclosed for providing a bias, comprising a bias generator circuit including a high voltage (HV) circuit configured to generate a regulated high voltage (HV) from an HV line and provide the regulated HV at an HV regulated line and a low voltage (LV) circuit configured to generate a low voltage (LV) differential from the HV line and to provide the LV differential at an LV line, wherein the LV circuit is configured to direct current used to generate the LV differential into the HV regulated line. 1. A system , comprising: a high voltage (HV) circuit configured to generate a regulated high voltage (HV) from an HV line and provide the regulated HV at an HV regulated line; and', 'a low voltage (LV) circuit configured to generate a low voltage (LV) differential from the HV line and to provide the LV differential at an LV line, wherein the LV circuit is configured to direct current used to generate the LV differential into the HV regulated line., 'a bias generator circuit, comprising2. The system of claim 1 , wherein the HV circuit is configured to generate the regulated HV using current from the HV line claim 1 , andwherein the LV circuit is configured to generate the LV differential using current from the HV line.3. The system of claim 2 , wherein the LV circuit is configured to direct current from the HV line used to generate the LV differential to a load connected to the HV regulated line claim 2 , and not waste the current from the HV line to ground.4. The system of claim 2 , wherein the LV circuit is coupled between the HV line and the H V regulated line.5. The system of claim 4 , wherein the LV circuit is configured to generate the LV differential with respect to the HV line.6. The system of claim 1 , wherein the HV circuit comprises a main diode and a first current mirror claim 1 , wherein the main diode is coupled to the HV line.7. The system of claim 6 , wherein the H V circuit comprises an impedance between the main diode and ground ...

MEMORY DEVICE AND AN OPERATING METHOD THEREOF

A memory device includes: a first circuit; a second circuit; and an adaptive body bias generator configured to receive frequency detection information or temperature detection information, to apply a first forward body bias or a first reverse body bias to the first circuit in response to the frequency detection information or the temperature detection information, and to apply a second forward body bias or a second reverse body bias to the second circuit in response to the frequency detection information or the temperature detection information. 1. A memory device , comprising:a first circuit;a second circuit; andan adaptive body bias generator configured to receive frequency detection information or temperature detection information, to apply a first forward body bias or a first reverse body bias to the first circuit in response to the frequency detection information or the temperature detection information, and to apply a second forward body bias or a second reverse body bias to the second circuit in response to the frequency detection information or the temperature detection information.2. The memory device of claim 1 , wherein the first circuit is part of a speed path claim 1 , andthe second circuit is part of a leakage path.3. The memory device of claim 1 , further comprising a frequency detector configured to detect a frequency of a clock received from an external device and generate the frequency detection information.4. The memory device of claim 3 , wherein the adaptive body bias generator applies the first forward body bias to the first circuit in response to the frequency detection information indicating that the frequency is higher than a reference frequency claim 3 , andapplies the first reverse body bias to the first circuit in response to the frequency detection information indicating that the frequency is lower than the reference frequency.5. The memory device of claim 4 , wherein the adaptive body bias generator applies the second forward body bias ...

METHOD AND SYSTEM FOR REGULATING MEMORY, AND SEMICONDUCTOR DEVICE

A method for regulating the memory includes operations as follows. A mapping relationship among temperatures of a transistor, body bias voltages of the transistor, and data writing time of the memory is acquired, a current temperature of the transistor is acquired, the body bias voltage is regulated based on the current temperature and the mapping relationship, to enable the data writing time corresponding to the regulated body bias voltage to be within a preset writing time.

Power network for providing power supply to memory device

Various implementations described herein are related to a device having memory circuitry with a bitcell array. The device may include a frontside power network that is coupled to the bitcell array, and the device may include a backside power network that provides power to the bitcell array. The device may include transition vias that couple the backside power network to the frontside power network, and the backside power network may provide power to the bitcell array by way of the transition vias being coupled to the frontside power network.

PHYSICAL UNCLONABLE FUNCTION (PUF)-BASED METHOD FOR ENHANCING SYSTEM RELIABILITY

A physical unclonable function (PUF)-based method for enhancing system reliability is provided, including: requesting, by a client, data transmission with a server; randomly selecting, by the server, a plurality of metal oxide semiconductor (MOS) devices in an MOS array, and acquiring positional information of the plurality of MOS devices; calculating, by the server, a probabilistic PUF that the trap in each of the plurality of MOS devices is occupied by a carrier and constructing a probabilistic model; randomly generating, by the server, detection time according to the probabilistic model and sending the detection time and the positional information to the client; and determining, by the server, an occupancy probability of the trap in each of the plurality of MOS devices at the detection time according to the probabilistic model, and generating a theoretical code key. 1: A physical unclonable function (PUF)-based method for enhancing system reliability , comprising:requesting, by a client, data transmission with a server;randomly selecting, by the server, a plurality of metal oxide semiconductor (MOS) devices in an MOS array, and acquiring positional information of the plurality of MOS devices;calculating, by the server, according to a stored intrinsic parameter of a trap in each of the plurality of MOS devices, a time constant of the trap, calculating a probabilistic PUF for each of the plurality of MOS devices and constructing a probabilistic model;randomly generating, by the server, detection time according to the probabilistic model and sending the detection time and the positional information to the client; anddetermining, by the server, a probability that the trap in each of the plurality of MOS devices is occupied at the detection time according to the probabilistic model, and generating a theoretical code key, the theoretical code key comprising a theoretical authentication bit and a theoretical uncertain bit.2: The PUF-based method for enhancing system ...

Driver circuit charging charge node

Disclosed is a driver circuit. The driver circuit includes a clamp transistor, a comparison voltage transistor, an amplification transistor, a bias transistor, and a charge circuit. The comparison voltage is configured to provide a comparison voltage. The amplification transistor includes an amplification gate connected to a first node of the clamp transistor, a first amplification node configured to receive the comparison voltage, and a second amplification node connected to a gate of the clamp transistor. The bias transistor is configured to supply a bias voltage. The charge circuit is at least one of configured to drain a current from the first node through the clamp transistor and configured to supply a current to the first node through the clamp transistor.

POSITIVE AND NEGATIVE FULL-RANGE BACK-BIAS GENERATOR CIRCUIT STRUCTURE

Embodiments of the disclosure provide a circuit structure for producing a full range biasing voltage including: a logic control node; first and second voltage generators, coupled to the logic control node, the first and second voltage generators configured to generate a positive voltage output at a positive voltage node and a negative voltage output at a negative voltage node; first and second multiplexer cells, coupled to the logic control node, configured to multiplex the positive voltage level received from the first or the second positive voltage node and the negative voltage level received from the first or the second negative voltage node to provide a multiplexed output; and an output node coupled to each of the first multiplexer cell and the second multiplexer cell configured to receive the multiplexed output to provide a biasing voltage range to at least one transistor having a back-gate terminal. 1. A circuit structure for producing a biasing voltage range , the circuit structure comprising:a logic control node;a first voltage generator and a second voltage generator, coupled to the logic control node, the first voltage generator configured to generate a positive voltage output at a first positive voltage node and a negative voltage output at a first negative voltage node, the second voltage generator configured to generate a positive voltage output at a second positive voltage node and a negative voltage output at a second negative voltage node;a first multiplexer cell and a second multiplexer cell, coupled to the logic control node, wherein the first and the second multiplexer cells are configured to multiplex the positive voltage level received from the first or the second positive voltage node and the negative voltage level received from the first or the second negative voltage node to provide a multiplexed output;an output node coupled to the first multiplexer cell and configured to receive the multiplexed output to provide a biasing voltage range to ...

Semiconductor device

A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

SIGNAL PROCESSING CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SIGNAL PROCESSING CIRCUIT

Provided is a semiconductor device that can operate stably. All transistors included in the semiconductor device are transistors each of which contains an oxide semiconductor in a channel formation region. The transistor includes a front gate and a back gate. The threshold voltage of the transistor can be shifted in the positive direction or the negative direction depending on a potential applied to the back gate. To make the transistor in a conducting state, the threshold voltage is shifted in the negative direction to increase the amount of current flowing in the transistor, and to make the transistor in a non-conducting state, the threshold voltage is shifted in the positive direction to decrease the amount of current flowing in the transistor. A circuit of the semiconductor device that utilizes this effect and includes transistors all having the same polarity is formed. 1. (canceled)2. A semiconductor device comprising:a transistor; anda back gate voltage control circuit;wherein the transistor comprises a gate, a back gate and a channel formation region,wherein the channel formation region comprises an oxide semiconductor,wherein the gate of the transistor is electrically connected to a wiring, andwherein the back gate of the transistor is electrically connected to the back gate voltage control circuit.3. The semiconductor device according to claim 2 ,wherein the back gate voltage control circuit is configured to apply a potential corresponding to a command to the back gate of the transistor.4. The semiconductor device according to claim 2 ,wherein the oxide semiconductor comprises indium.5. A semiconductor device comprising:a memory cell array comprising a memory cell; anda back gate voltage control circuit;wherein the memory cell comprises a transistor and a capacitor,wherein the transistor comprises a gate, a back gate and a channel formation region,wherein the channel formation region comprises an oxide semiconductor,wherein one of a source and a drain of ...

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND WEARABLE DEVICE

To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. 18-. (canceled)9. A semiconductor integrated circuit device comprising:a memory cell array which includes:a plurality of memory cells, each of the memory cells having a P-type SOTB transistor and an N-type SOTB transistor;a plurality of word lines coupled to the memory cells, respectively; anda plurality of bit lines coupled to the memory cells, respectively;a plurality of word drivers coupled to the word lines respectively, each of the word drivers having a P-type MOS transistor and an N-type MOS transistor,wherein the semiconductor integrated circuit has a first mode and a second mode,wherein a first voltage is supplied to a substrate of the P-type SOTB transistor, a second voltage is supplied to a substrate of the N-type SOTB transistor, a third voltage is supplied to a substrate of the P-type MOS transistor, and a fourth voltage is supplied to a substrate of the N-type MOS transistor when the semiconductor integrated circuit is in the first mode, andwherein an operating frequency of the first mode is lower than that of the second mode.10. The semiconductor integrated circuit device according to claim 9 ,wherein the first and second voltages are not supplied to the substrates of the P-type and the N-type SOTB transistors when the semiconductor integrated circuit is in the second mode.11. The semiconductor integrated circuit device according to claim 9 , further comprising:a substrate bias generation circuit supplying the first, second, third and fourth voltages.12. The semiconductor integrated circuit device according to claim 9 ,wherein a static random access memory circuit includes the memory cell array and the word drivers and is coupled to a central processing unit via a bus,wherein the central processing unit has a P-type MOS transistor and an N-type MOS transistor, andwherein the third voltage is supplied to a substrate of the P-type MOS ...

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND WEARABLE DEVICE

To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. 18-. (canceled)9. A semiconductor integrated circuit device comprising:a first circuit including a P-type transistor and an N-type transistor;a second circuit including a P-type SOTB transistor and an N-type SOTB transistor; anda voltage supplying circuit for supplying a voltage to the first circuit and the second circuit,wherein the P-type SOTB transistor includes a first gate electrode, a first source region, a first drain region, a first channel region, which is arranged between the first source region and the first drain region and in which a channel is formed, a first insulation film, and a first region which faces the first channel region through the first insulation film,wherein the N-type SOTB transistor includes a second gate electrode, a second source region, a second drain region, a second channel region, which is arranged between the second source region and the second drain region and in which a channel is formed, a second insulation film, and a second region which faces the second channel region through the second insulation film,wherein the first circuit includes an input/output circuit,wherein the second circuit includes a memory cell,wherein the semiconductor integrated circuit device has a first operation mode and a second operation mode,wherein the voltage supplying circuit outputs a first voltage and a second voltage, andwherein, in the first operation mode, the first voltage is supplied to the first region of the P-type SOTB transistor and the second voltage is supplied to the second region of the N-type SOTB transistor.10. The semiconductor integrated circuit device according to claim 9 ,wherein the P-type transistor includes a third gate electrode, a third source region, a third drain region, a third channel region, which is arranged between the third source region and the third drain region and in which a channel is formed, and ...

Semiconductor memory device

A semiconductor memory device includes a sense amplifier, a voltage supply circuit and a voltage supply control circuit. The sense amplifier may be activated by receiving driving voltages from first to third voltage supply lines to detect and amplify voltage levels of a data line and a data bar line. The voltage supply circuit may apply the driving voltages to the first to third voltage supply lines in response to first to third voltage supply signals and a bias control signal. The voltage supply control circuit may generate the first to third voltage supply signals and the bias control signal in response to an active signal.

SEMICONDUCTOR DEVICE

A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current. 116-. (canceled)17. A semiconductor device comprising:a first line for a first voltage;a second line for a second voltage lower than the first voltage;a first P channel MOS transistor having a gate coupled to receive a first control signal and having a source-drain path; first static memory cells, each first static memory cell having a first voltage supply point which is coupled to the first line via the source-drain path of the first P channel MOS transistor, and each first static memory cell being coupled to the second line;', 'first word lines coupled to the first static memory cells;', 'first word drivers coupled to the first word lines, each first word driver having a second voltage supply point which is coupled to the first line, and each first word driver being coupled to the second line; and', 'first bit lines coupled to the first static memory cells,, 'a first static random access memory circuit which includes second static memory cells, each second static memory cell being directly coupled to the first line and coupled to the second line;', 'second word lines coupled to the second static memory cells;', 'second word drivers coupled to the second word lines, each second word driver coupled to the first line and the second line; and', 'second bit lines coupled to the second static memory cells., 'a second static random access memory circuit which includes18. A semiconductor device according to claim 17 ,wherein each first static memory cell includes:a flip-flop having a first storage node, a second storage node, a first CMOS inverter having an output coupled to the first storage node and an input coupled to the second storage node, and a second CMOS inverter having an output coupled to the second storage node and an ...

NON-VOLATILE MEMORY (NVM) WITH WORD LINE DRIVER/DECODER USING A CHARGE PUMP VOLTAGE

A word line driver that includes a pull up transistor for biasing a node of a stack of transistors that are located between a high supply voltage terminal and a low supply voltage terminal. The node is biased at a voltage that is between the high supply voltage and the low supply voltage. The stack of transistors includes a stack of decode transistors and a cascode transistor. The cascode transistor is located between the node and a second node of the stack that is coupled to an inverting circuit. 1. A word line driver comprising: a plurality of decode transistors coupled in a stack between a first node of the first stack of transistors and a first voltage supply terminal for supplying a first supply voltage, wherein each of the decode transistors includes a control electrode to receive a decode signal of a plurality of decode signals;', 'a cascode transistor having a first current electrode connected to the first node, the cascode transistor including a control electrode coupled to a source voltage terminal for providing a source voltage;', 'a third transistor, a first current electrode of the third transistor is connected to a second node of the first stack of transistors, wherein the second current electrode of the third transistor is coupled to a second supply voltage terminal for supplying a second supply voltage, the second node is coupled to a second current electrode of the cascode transistor;, 'a first stack of transistors, the first stack includinga pull up transistor having a first current electrode coupled to the first node, a second current electrode coupled to a third supply voltage terminal for supplying a third supply voltage, and a control electrode coupled to a decode signal of the plurality of decode signals, wherein the second supply voltage is higher than the first supply voltage and higher than the third supply voltage, wherein the third supply voltage is higher than the first supply voltage; andan inverting circuit including an input and an ...

MEMORY DEVICE WITH REDUCED ON-CHIP NOISE

In some examples, a memory device includes multiple memory banks equipped with an isolation switch and dedicated power supply pins. The isolation switch of each memory bank is configured to isolate the memory bank from global signals. The dedicated power supply pins are configured to connect each of the memory banks to a dedicated local power supply pads on the package substrate to provide local dedicated power supplies to each of the memory banks and to reduce voltage transfer between memory banks over conductors on the device, the device substrate, or the package substrate of the memory device. 120-. (canceled)21. A memory device comprising:a plurality of memory banks;a global bias system to generate a voltage bias for controlling the plurality of memory banks;a local power supply dedicated to a particular memory bank of the plurality of memory banks; andan isolation switch coupled to the global bias system and the particular memory bank to decouple the particular memory bank from the global bias system during an access operation associated with the particular memory bank.22. The memory device as recited in claim 21 , further comprising a plurality of local power supply pins for coupling the local power supply to the particular memory bank.23. The memory device as recited in claim 21 , wherein the first isolation switch is at least one of:a transfer gate;a PMOS; oran NMOS.24. The memory device as recited in claim 21 , further comprising a charge pump coupled to the local power supply and the particular memory bank.25. The memory device as recited in claim 21 , further comprising a local bias generator coupled to the local power supply and the particular memory bank.26. The memory device as recited in claim 25 , wherein the local power supply and the local bias generator are configured to maintain a local bias voltage on the particular the memory bank during the access operation.27. The memory device as recited in claim 21 , further comprising a local sense ...

LOW-VOLTAGE BIAS GENERATOR BASED ON HIGH-VOLTAGE SUPPLY

Apparatus and methods are disclosed for providing a bias. A main diode has first and second terminals that connect to a high voltage (HV) line and to an HV regulated line, respectively. The main diode provides a voltage on the HV regulated line lower than a voltage of the HV line. A first current mirror provides a first current. The current mirror connects to the first terminal of the main diode and the HV regulated line. A second current mirror provides a second current. The second current mirror connects to the HV line, the first current mirror, and a low-voltage (LV) line. An impedance is between the LV line and the HV regulated line. A voltage differential between the HV regulated line and the LV line below a low-voltage threshold, and a voltage differential between the HV regulated line and the HV line above the low-voltage threshold are provided. 1. A system , comprising:a main diode having first and second terminals, the first terminal coupled to a high-voltage (HV) line and the second terminal coupled to an HV regulated line, wherein the main diode is configured to provide a voltage on the HV regulated line lower than a voltage of the HV line;a first current mirror configured to provide a first current, the first current mirror having a gate and first and second terminals, the gate coupled to the first terminal of the main diode and the second terminal coupled to the HV regulated line; anda second current mirror configured to provide a second current, the second current mirror having first, second, and third terminals, the first terminal coupled to the HV line, the second terminal coupled to the first terminal of the first current mirror, and the third terminal coupled to a low-voltage (LV) line.2. The device of claim 1 , wherein the second current mirror comprises LV p-type metal-oxide-semiconductor (PMOS) devices.3. The device of claim 2 , comprising:a first transistor connected to the HV line and an input of the second current mirror; anda second ...

SRAM WITH ACTIVE SUBSTRATE BIAS

An SRAM circuit that includes a biasing circuit adapted to selectively bias the transistors of the SRAM array to lower the threshold voltage of selected transistors. The SRAM circuit includes well voltages and positive voltages that are selectively different, and substrate voltages and ground voltages that are selectively different. 2. The method of wherein:said mode is further characterized as a retention mode;said third voltage is further characterized as being lower than said first voltage; andsaid fourth voltage is further characterized as being higher than said second voltage.3. The method of wherein:said mode is further characterized as an active mode;said third voltage is further characterized as being equal to said first voltage; andsaid fourth voltage is further characterized as being equal to said second voltage.5. An SRAM facility configured to perform the steps of a method according to any one of to .6. A memory system comprising an SRAM facility according to .7. A computer readable medium including executable instructions which claim 5 , when executed in a processing system claim 5 , causes the processing system to perform the steps of a method according to any one of to . This application is a Continuation of application Ser. No. 15/412,039, filed 22 Jan. 2017 (“Parent Application”).This application claims priority to the Parent Application and hereby claims benefit of the filing dates thereof pursuant to 37 CFR § 1.78(a)(4).The subject matter of the Parent Application is expressly incorporated herein by reference.The present invention relates to low power semiconductor memory circuits and methods. More specifically, the present invention relates to Static Random Access Memory (“SRAM”) circuits and methods having controlled substrate and well biases and reduced power requirements. The novel low power SRAM circuits and methods are suitable for use in low power microprocessors, microcontrollers, or power management devices.In general, in the descriptions ...

REVERSE BIAS VOLTAGE ADJUSTER

A reverse bias voltage adjuster is provided. The reverse bias voltage adjuster includes an operating voltage generating circuit and a voltage adjusting circuit. The operating voltage generating circuit generates an operating voltage according to a burnin-test signal, a power start signal, and a reverse bias enable signal. In a normal operation mode, the operating voltage is a first voltage value, and in a burnin-test mode, the operating voltage is a second voltage value, wherein the second voltage value is less than the first voltage value. The voltage adjusting circuit is provided with a switch, and in an initial time interval in the burnin-test mode, the voltage adjusting circuit adjusts voltage value of the reverse bias by turning on the switch. 1. A reverse bias voltage adjuster , comprising:an operating voltage generating circuit, which generates an operating voltage according to a burnin-test signal, a power start signal, and a reverse bias enable signal, wherein in a normal operation mode, the operating voltage is a first voltage value, and in a burnin-test mode, the operating voltage is a second voltage value, and the second voltage value is less than the first voltage value; anda voltage adjusting circuit, which is coupled to the operating voltage generating circuit, and is provided with a switch, wherein the switch is coupled between transfer trajectories of a reference grounding voltage and a reverse bias voltage, and in an initial time interval in the burnin-test mode, the voltage adjusting circuit adjusts voltage value of the reverse bias voltage by turning on the switch.2. The reverse bias voltage adjuster according to claim 1 , wherein the reverse bias voltage adjuster further comprises:a reverse bias generating circuit, which is coupled to the voltage adjusting circuit, and generates the reverse bias voltage by a capacitor according to the reverse bias enable signal.3. The reverse bias voltage adjuster according to claim 1 , wherein in the initial ...

SOURCE SIDE PRECHARGE AND BOOSTING IMPROVEMENT FOR REVERSE ORDER PROGRAM

This disclosure relates to apparatuses and a method for retaining a bias in a NAND string channel during source-side precharge. The apparatuses include a memory array and a die controller configured to mitigate formation of a potential gradient in the channel of the memory array NAND strings during a program storage operation. To this end, a plurality of source-side select gates is activated, then each of the plurality of source side dummy word line select gates is activated. Next, a NAND string channel is biased by biasing the source line coupled to the NAND string by the plurality of source-side select gates. Finally, the plurality of source-side select gates and the plurality of source side dummy word line select gates are discharged such that the channel maintains an electrical path to the source line. 1. An apparatus comprising: a first source-side select gate having a first threshold voltage, the first source-side select gate located on a source side of the NAND string, the first source-side select gate configured to couple the NAND string to a source line;', 'a drain-side select gate on a drain side of the NAND string, the drain-side select gate configured to couple the NAND string to a bit line;', 'a set of memory cells positioned along the NAND string between the source-side select gate and the drain-side select gate, the memory cells coupled to word lines;', 'a second source-side select gate having a second threshold voltage that is greater than the first threshold voltage, the second source-side select gate located on the source side of the NAND string; and', 'a channel that extends from the source side to the drain side of the NAND string; and, 'a three-dimensional memory array of NAND strings, each NAND string comprisingone or more control circuits connected to the first and second source-side select gates to:discharge a first voltage on the first source-side select gate at a first time, andat a second time, after discharge of the first voltage on the ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device may include a memory cell array area, a peripheral area, and an interface area. The memory cell array area may include at least one memory plane. The peripheral area may be formed adjacent to one side of the memory cell array area. The interface area may be formed adjacent to one side of the peripheral area and include a plurality of data input/output pads. The peripheral area may include a data path logic area formed between the memory cell array area and the interface area. The interface area may include at least one SerDes (serializer/deserializer) area configured to transmit, to the memory cell array area, data inputted through the data input/output pads, or output, through the data input/output pads, data received from the memory cell array. 1. A semiconductor memory device comprising:a memory cell array area including at least one memory plane;a peripheral area formed adjacent to one side of the memory cell array area; andan interface area formed adjacent to one side of the peripheral area, the interface area comprising a plurality of data input/output pads,wherein the peripheral area comprises a data path logic area formed between the memory cell array area and the interface area, andwherein the interface area comprises at least one SerDes (serializer/deserializer) area configured to transmit, to the memory cell array area, data inputted through the data input/output pads, or output, through the data input/output pads, data received from the memory cell array.2. The semiconductor memory device according to claim 1 , wherein a plurality of SerDes devices are formed in the SerDes area claim 1 , and each of the SerDes devices comprises a serializer and a deserializer.3. The semiconductor memory device according to claim 2 , wherein the SerDes area is disposed adjacent to the plurality of data input/output pads.4. The semiconductor memory device according to claim 2 , wherein each of the SerDes devices is coupled with a corresponding ...

Time domain ramp rate control for erase inhibit in flash memory

When performing an erase on a flash type non-volatile memory with a NAND type of structure, techniques are presented for inhibiting erase on selected word lines, select lines of programmable select transistors, or some combination of these. The voltage along the selected control lines are initially ramped up by the level on a corresponding input line, but then have their voltage raised to an erase inhibit level by capacitive coupling with the well structure. The level of these input signals are ramped up with the erase voltage applied to the well structure, but with a delay based upon the coupling ratio between the control line and the well.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND WEARABLE DEVICE

To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. 18-. (canceled)9. A semiconductor integrated circuit device comprising:a first circuit including a P-type SOTB transistor;a second circuit including a P-type MOS transistor and coupled to the first circuit,wherein the P-type SOTB transistor includes a first source region, a first drain region, a first channel region arranged between the first source region and the first drain region, a first gate electrode arranged over the first channel region, an insulation film arranged under the first channel region, and a first region arranged under the insulation film,{'b': '1', 'wherein the P-type MOS transistor includes a second source region, a second drain region, a second channel region arranged between the second source region and the second drain region, a second gate electrode arranged over the second channel region, and a second region arranged under the second channel region, p wherein a first voltage is supplied to the first region of the P-type SOTB transistor, and a second voltage is supplied to the second region of the P-type MOS transistor for reducing a leakage current, and'}wherein a value of the first voltage is different from a value of the second voltage.10. The semiconductor integrated circuit device according to claim 9 ,wherein the first circuit includes an N-type SOTB transistor, the N-type SOTB transistor including a third source region, a third drain region, a third channel region arranged between the third source region and the third drain region, a third gate electrode arranged over the third channel region, an insulation film arranged under the third channel region, and a third region arranged under the insulation film,wherein the second circuit includes a N-type MOS transistor, the N-type MOS transistor including a fourth source region, a fourth drain region, a fourth channel region arranged between the fourth source region and the ...

DUAL MODE MEMORY SYSTEM AND METHOD OF WORKING THE SAME

A dual mode memory system is provided in the present invention, which includes a memory cell array with a plurality of oxide-semiconductor field effect transistors, each said oxide-semiconductor field effect transistor has a ferroelectric layer in the bottom gate to modulate the bottom gate bias voltage according to the polarization voltages provided by the dual mode control unit. 1. A memory cell with an oxide-semiconductor field effect transistor , comprising:a channel layer;source and drain on said channel layer;a gate dielectric layer on said channel layer and on said source/drain;a top gate on one side of said channel layer and on said gate dielectric layer;a bottom-gate oxide layer under said channel layer;a buffer layer under said bottom-gate oxide layer;a bottom gate on the other side of said channel layer and under said buffer layer; anda ferroelectric layer between said bottom gate and said buffer layer, wherein said gate dielectric layer is a silicon oxide layer, a nitrogen-containing silicon oxide layer, or a high dielectric constant (high-k) material.2. The memory cell with an oxide-semiconductor field effect transistor of claim 1 , wherein the material of said ferroelectric layer comprises HfZrO(HZO) claim 1 , BaTiO claim 1 , PbTiO claim 1 , BiOSrTa(SBT) claim 1 , PbZrTiO(PZT) claim 1 , KNbO claim 1 , LiNbO claim 1 , LiTaO claim 1 , SrBaNbO claim 1 , BaNaNbO claim 1 , BiFeO claim 1 , polyvinyledenedifluoride-trifluoroethylene (PVDF-TrFE) claim 1 , or any combination thereof.3. The memory cell with an oxide-semiconductor field effect transistor of claim 1 , wherein said buffer layer comprises titanium nitride or aluminum oxide.4. The memory cell with an oxide-semiconductor field effect transistor of claim 1 , wherein said channel layer comprises an oxide semiconductor material.5. The memory cell with an oxide-semiconductor field effect transistor of claim 4 , wherein said oxide semiconductor material comprises c-IGZO claim 4 , a-IGZO claim 4 , or CAAC- ...

PUMP SYSTEM OF A DRAM AND METHOD FOR OPERATING THE SAME

The present disclosure provides a pump system of a DRAM and a method for operating the same. The pump system includes a pump device and a spare pump assembly. The pump device provides a current sufficient to allow a bank of the DRAM to operate at a normal refresh rate without other spare pump devices in response to a normal instruction which indicates that the bank is instructed to operate at the normal refresh rate. The spare pump assembly includes a first spare pump device configured to provide, in combination with the pump device, a current sufficient to allow the bank to operate at a first refresh rate greater than the normal refresh rate in response to a first instruction which indicates that the bank is instructed to operate at the first refresh rate. 1. A pump system of a DRAM , comprising:a pump device configured to provide a first current sufficient to allow a bank of the DRAM to operate at a normal refresh rate without other spare pump devices in response to a normal instruction which indicates that the bank is instructed to operate at the normal refresh rate;a spare pump assembly, coupled with the pump device in parallel, which would otherwise provide, in combination with the pump device, the first current sufficient to allow the bank of the DRAM to operate at the normal refresh rate only when a circuit structure of the DRAM is redesigned by metal option, wherein the spare pump assembly includes a first spare pump device configured to provide, in combination with the pump device, a second current sufficient to allow the bank to operate at a first refresh rate greater than the normal refresh rate in response to a first instruction which indicates that the bank is instructed to operate at the first refresh rate; anda controller configured to disable the first spare pump device in response to the normal instruction, and to enable the first spare pump device in response to the first instruction.2. The pump system of claim 1 , wherein the first refresh rate is ...

Semiconductor integrated circuit device with low power consumption in a standby mode using an on-chip substrate bias generator

A mode switching transistor which is controlled by a chip enable signal is connected between a power supply terminal and a MOS inverter including transistors. The transistor functions as a weak depletion or depletion type MOS transistor to provide sufficient current with a first back gate bias given in an active mode and functions as a perfect enhancement type transistor to completely cut off current with a second back gate bias given in a standby mode.

Substrate potential generating circuit generating substrate potential of lower level and semiconductor device including the same

A substrate potential generating circuit can generate a lower substrate potential. The substrate potential generating circuit includes a clock signal generating circuit and first and second charge pump circuits. The first charge pump circuit including a p-channel MOS transistor having its source electrode connected to the semiconductor substrate applies a first negative potential to the drain electrode by capacitive coupling of a capacitor. The second charge pump circuit including first and second sub-charge pump circuit applies a third negative potential to the gate electrode when the first negative potential is applied to the drain electrode, and thereafter provides a second potential by lowering the third potential. As a result, the p-channel MOS transistor is turned on until a substrate potential is brought into a potential equal to the first potential applied to the drain electrode, lowering the substrate potential to the first potential.

VBB reference for pumped substrates

An embodiment of a pumped substrate system includes an oscillator, capacitive pump, comparing circuit, and a level shifter. The level shifter is coupled between the substrate and the positive input lead of the comparator and shifts the voltage level present on the substrate by a voltage Vbg. The comparator compares ground potential to the shifted substrate voltage. The oscillator, capacitive pump and comparing circuit form a negative feedback loop which operates to maintain the substrate voltage substantially equal to -Vbg. In one embodiment, the level shifter includes a band gap reference.

Semiconductor memory device including boost circuit

Disclosed is a semiconductor memory device, which comprises a plurality of circuits using a voltage obtained by boosting an external power source voltage and power source noises produced by operations of these circuits have no influence on other circuits. The semiconductor memory device including a boost circuit comprises a plurality of circuits using boost voltages, for example, a memory cell array, an output circuit and a plurality of boost circuits, each being provided for the corresponding one of these circuits. With such constitution, a problem of noise interference among the circuits using the boost voltages can be removed.

method for controlling voltage generator for use in wafer burn-in test and voltage generator controlling circuit

웨이퍼 번인 테스트에 사용하기 적합한 전압 발생기 제어방법 및 전압 발생기의 동작제어를 위한 제어회로를 갖는 반도체 메모리 장치가 개시된다. 노말 전원전압보다 높거나 낮은 레벨의 전압을 발생하기 위한 전압 발생기를 적어도 하나이상 구비한 반도체 메모리 장치에서 특정 동작모드 동안에 상기 전압 발생기를 제어하기 위한 방법은, 상기 특정 동작모드의 진입을 알리는 신호에 응답하여 상기 전압 발생기(들)의 동작을 차단하고, 상기 특정 동작모드에서 필요한 전압을 상기 장치의 외부에서 전압 패드를 통해 인가하는 것을 특징으로 한다. A semiconductor memory device having a voltage generator control method suitable for use in a wafer burn-in test and a control circuit for controlling the operation of the voltage generator is disclosed. A method for controlling the voltage generator during a specific operation mode in a semiconductor memory device having at least one voltage generator for generating a voltage higher or lower than a normal power supply voltage may include a signal indicating an entry of the specific operation mode. In response to interrupting operation of the voltage generator (s) and applying a voltage required in the particular mode of operation via a voltage pad external to the device.

반도체장치의 기판전압발생기

본 발명은 전원전압 변동에 의한 영향을 최소화하여 안정된 기판전압을 생성하기 위한 기판전압발생기를 제공하고자 하는 것으로, 이를 위한 본 발명의 기판전압 발생기는, 반도체장치의 기판전압 발생기에 있어서, 공급되는 전류량에 따라 오실레이션 주기를 가변가능한 가변오실레이터; 상기 가변오실레이터의 출력을 펌핑하여 기판전압을 발생시키기 위한 전하펌프; 전원전압하에 구동하며 상기 기판전압의 레벨을 검출하여 상기 가변오실레이터를 인에이블하기 위한 전위검출기; 상기 전위검출수단의 상기 전원전압에 대응되는 전원전압센싱신호를 얻기 위한 전원전압센싱수단; 기준전압 발생을 위한 기준전압발생기; 상기 전원전압센싱신호와 상기 기준전압을 비교하기 위한 비교기; 및 상기 비교기의 출력에 따라 상기 가변오실레이터에 공급되는 전류량을 조절하는 전원공급기를 포함하여 이루어진다.

Word line switch circuit

본 발명은 워드라인 스위치 회로에 관한 것으로, 메모리 셀에 워드라인 전압을 인가하기 위한 워드라인 스위치 회로에서 고전압을 전송하는 트랜지스터의 웰 바이어스를 소스와 동일한 레벨의 전압을 인가함으로 인해 소자의 바디바이어스 효과를 방지할 수 있고, 펌핑된 워드라인 전압을 트랜지스터의 문턱 전압만큼의 전압강하 없이 셀의 워드라인에 전달할 수 있는 워드라인 스위치 회로를 제공한다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a word line switch circuit, wherein a body bias effect of a device is applied by applying a voltage at the same level as that of a source to a well bias of a transistor for transmitting a high voltage in a word line switch circuit for applying a word line voltage to a memory cell. And a word line switch circuit capable of transferring the pumped word line voltage to the word line of the cell without dropping as much as the threshold voltage of the transistor.

기준전압 발생기

온도의 변화에도 일정한 출력전압을 형성할 수 있는 저전압용 기준전압 발생기가 개시된다. 기준전압 발생기는 기준전류의 생성을 통해 기준전압을 발생하는 기준전압 발생부와 기준전압 발생부의 스타트-업 동작을 유도하는 스타트-업 제어부를 가진다. 스타트-업 제어부는 온도변화에도 일정한 기준전류의 생성을 유도하는 온도 보상부에 연결된다. 특히, 온도 보상부의 바이폴라 트랜지스터에 직렬 연결된 감지 저항의 양단 전압을 수신하고, 수신된 신호를 근거로 기준전압 발생부의 스타트-업 동작을 유도한다. 따라서, 온도 보상 동작을 수행하는 온도 보상부의 동작 상태를 정확히 감지하여 스타트-업 동작을 수행할 수 있다.

Semiconductor integrated circuit

반도체 집적 회로는 기판전위를 안정화할 수 있게 하고 전원투입시 이상전류의 발생을 억제할 수 있게 한다. 웰이 네 개의 P웰로 분할되고, 이 P웰들에는 각각 백 바이어스 발생회로(BBG)가 제공된다. The semiconductor integrated circuit makes it possible to stabilize the substrate potential and to suppress the occurrence of abnormal current when the power is turned on. The well is divided into four P wells, each of which is provided with a back bias generation circuit BBG.

Clamping circuit of row address strobe(/ras)

내용 없음. No content.

외부전원전압의 변동이나 환경온도의 변화에 대한 출력전압의 변동을 억제할 수 있는 기판전위발생회로

반도체 메모리등의 집적회로장치에 필요한 기판바이어스전위를 소정 전압범위내로 제어하는 회로의 구성에 관한 것으로, 전원전압이나 외부 환경온도에 영향을 받지 않고 안정하게 기판전위를 공급할 수 있도록 하기 위해, 기판전위발생회로는 제1 기판전위레벨검출호로, 발진회로, 차지펌프회로를 구비하고 제1 기판레벨검출회로는 기판전위와 제1 소정전위의 비교결과에 따라서 제1 제어신호를 출력하고, 제1 기판 전위레벨검출회로는 제1 제어신호를 출력하는 제1 출력노드, 기판전위와 결합하는 제1 입력노드, 전류미러회로를 이루는 적어도 한쌍의 MOSFET를 갖고 출력이 제1 출력노드에 접속되는 제1 정전류발생회로 및 드레인 제1 출력노드에 접속되어 게이트가 기준전위와 결합하고 소오스가 제1 입력노드에 접속되는 제1 도전형의 제1 MOSFET를 포함하는 구성으로 하였다. 상기한 구성으로 하는 것에 의해, 외부동작조건의 변동에 거의 영향을 받지 않고 안정한 기판전위의 제어를 할 수 있게 된다.

Back bias generater

The circuit prevents the mulfunction of cell and reduces power consumption keeping a minus value for the output voltage of the pumping capacitor. The circuit is composed of a control unit (IC2), inverter gates (I1)(I2) and a ring oscillator (IC1), such that the output of the ring oscillator (IC1) is connected to a pumping capacitor (PC1) through the inverter gates (I1-I3), the control unit (IC2) controls the voltage of gate in switching transistor (MN3), the P-MOS transistor (MP2) applies the voltage of power source and ground terminal to the gate of switching transistor (MN3) according to the output voltage of ring oscillator (IC1), the N-MOS transistor (MN4) applies the voltage of the back bias terminal (VBB) to the gate of switching transistor (MN3).

Charge pump leakage current adjusts circuit

本发明提供了一种电荷泵漏电流调节电路，所述电荷泵漏电流调节电路包括偏置电压产生电路和第一晶体管，其中：所述偏置电压产生电路产生一偏置电压，所述偏置电压与电源电压成正比；所述第一晶体管的栅极耦合至所述偏置电压；所述第一晶体管的漏极耦合至一电荷泵的输出端，所述第一晶体管的漏极电压与所述电源电压成正比，所述第一晶体管的源极接地；流过所述第一晶体管源漏极的电流与所述电源电压成正比，所述电源电压为所述电荷泵供电。

Row Decoder in Nonvolatile Memory Device

본 발명은 파워 셋업 타임을 향상시키고 트랜스퍼링 전압 범위를 크게하여 동작 특성을 향상시키는데 적당하도록한 비휘발성 메모리 장치의 로우 디코더에 관한 것으로, 복수개의 비휘발성 메모리 셀들이 배열되는 메인 셀 어레이;상기 메인 셀 어레이의 워드 라인을 선택하기 위한 워드 라인 스위칭 유닛들을 하나 이상 포함하는 워드 라인 스위칭부;상기 워드 라인 스위칭부에 의해 선택되어진 워드 라인을 드라이빙하기 위한 워드 라인 드라이버부;상기 워드 라인 스위칭부의 하나 이상의 워드 라인 스위칭 유닛들을 선택적으로 on/off를 제어하는 블록들을 하나 이상 포함하는 세그먼트 디코더 드라이버;상기 워드 라인 스위칭 유닛들을 구성하는 pMOS 트랜지스터들의 n 웰 바이어스를 공급하는 블록들을 하나 이상 포함하는 웰 바이어스 드라이버부를 포함하여 구성된다. The present invention relates to a row decoder of a nonvolatile memory device suitable for improving power set-up time and increasing a transfer voltage range to improve operating characteristics, comprising: a main cell array in which a plurality of nonvolatile memory cells are arranged; A word line switching unit including one or more word line switching units for selecting a word line of a cell array; a word line driver unit for driving a word line selected by the word line switching unit; one or more word line switching units A segment decoder driver including one or more blocks selectively controlling on / off of word line switching units; a well bias driver unit including one or more blocks for supplying n well biases of pMOS transistors constituting the word line switching units;It is configured to hereinafter.

Semiconductor device

듀티 싸이클 감지 회로 및 이를 포함하는 반도체 장치

본 기술은 입력 클럭의 듀티를 감지하여 듀티 감지 신호를 생성하도록 구성된 감지 블록; 및 상기 입력 클럭에 응답하여 상기 감지 블록의 전류량을 상기 입력 클럭의 주파수 변동과 무관하게 제어하도록 구성되는 전류량 제어부를 포함할 수 있다.

Semiconductor memory device including boost circuit

외부 전원 전압을 부스팅하므로써 얻어지는 전압을 사용하는 다수의 회로들을 구비하고 이들 회로들의 동작들에 의해 발생되는 전원 잡음들이 다른 회로들에 영향을 미치지 않게하는 반도체 메모리 장치가 서술되어 있다. 부스트 회로를 구비하는 반도체 메모리 장치는 예를들어 메모리 셀 어레이 및 출력 회로와 같이 부스트 전압들을 사용하는 다수의 회로들 및 다수의 부스트 회로들을 구비하는데, 각각의 회로는 이들 회로들중 대응하는 하나의 회로를 위해 제공된다. 이와같은 구성에 따라서, 부스트 전압들을 사용하는 회로들간의 잡음 간섭 문제가 제거될 수 있다.

Semiconductor memory device, internal power supply voltage generation circuit, internal high voltage generation circuit, intermediate voltage generation circuit, constant current source, and reference voltage generation circuit

Semiconductor memory device and voltage generating method thereof

본 발명은 반도체 메모리 장치 및 이 장치의 전압 발생방법을 공개한다. 이 장치는 메모리 셀 어레이, 메모리 셀 어레이로/로부터의 데이터 전송 동작을 제어하기 위한 주변회로, 외부 전원전압이 인가되면 메모리 셀 어레이를 위한 메모리 셀 어레이용 기준전압을 발생하기 위한 메모리 셀 어레이용 기준전압 발생회로, 외부 전원전압이 인가되면 메모리 셀 어레이용 기준전압보다 소정 전압만큼 높은 주변회로를 위한 주변회로 수단용 기준전압을 발생하기 위한 주변회로용 기준전압 발생회로, 외부 전원전압이 인가되면 고전압을 위한 고전압용 기준전압을 발생하기 위한 고전압용 기준전압 발생회로, 및 고전압용 기준전압을 입력하여 고전압을 발생하기 위한 고전압 발생회로로 구성되어 있다. 따라서, 장치 내부의 복수개의 직류 전압 발생회로들이 별도의 기준전압을 이용하여 복수개의 직류 전압들을 발생하기 때문에 장치의 동작 성능이 개선될 수 있고, 이에 따라 수율이 증가된다.

The generator of back-bias voltage

내용 없음.

Semiconductor integrated circuit

반도체 집적회로는 전원공급 노드(211a)와 접속노드(212) 사이에 접속된 풀업회로(212f)와 상기 접속 노드(212)와 접지 전위 노드(211b) 사이에 접속된 캐패시터(212c)를 포함하는 전원 전위 응답회로(212g)와, 전원 공급 노드(211a)와 접속 노드(212) 사이에서 상기 접속노드(212)에서 상기 전원공급 노드(211a)로 순방향으로 배치되도록 다이오드 접속되고, 백 게이트(213bg)가 그의 게이트(213g)에 접속되는 방전용 MOS 트랜지스터(213)와, 상기 접속 노드(212)의 전위를 받고, 제1레벨로부터 전원 전위가 상승하기 시작하는 시간으로부터 소정 시간 후에 소정의 레벨을 넘은 접속노드(212)의 전위에 대응하는 제2레벨로 변화하는 파워온 리세트 신호를 출력하여, 상기 파워온 리세트 신호의 상기 제2레벨을 유지하는 유지회로(216)를 포함한다. The semiconductor integrated circuit includes a pull-up circuit 212f connected between the power supply node 211a and the connection node 212 and a capacitor 212c connected between the connection node 212 and the ground potential node 211b. A diode is connected between the power supply potential response circuit 212g and the power supply node 211a and the connection node 212 so as to be disposed in the forward direction from the connection node 212 to the power supply node 211a, and a back gate 213bg. ) Receives a potential of the discharge MOS transistor 213 connected to its gate 213g and the connection node 212, and a predetermined level is increased after a predetermined time from the time when the power supply potential starts to rise from the first level. And a holding circuit 216 for outputting a power-on reset signal that changes to a second level corresponding to the potential of the connection node 212 that is exceeded, and for holding the second level of the power-on reset signal.

Back-bias voltage generating circuit

본 발명은 백-바이어스 전압 발생회로에 관한 것으로, 종래 기술에 있어서 트리플 웰(Triple Well) 구조가 되었을 경우, 코어 회로의 엔-웰(N-Well)의 래치업(latch-up)을 방지하기 위하여 사용하는 승압전압과 피-웰(P-Well)의 바이어스인 백-바이어스 전압간의 접합커패시턴스값이 증가되는 문제점이 있었다. 또한, 상기 승압전압과 백-바이어스 전압이 내부 전압으로 인가되어 동작시 상기 승압전압이 상승시 상기 백-바이어스 전압도 함께 상승함과 아울러 상기 백-바이어스 전압이 하강함에 따라 상기 승압전압이 함께 하강하는 커플링 현상에 따라 계속적으로 백바이어스 펌프와 승압전압 펌프가 구동됨에 따라 불필요한 전력을 소모하고, 또한, 대기 전류(stndby-current) 소모로 인하여 동작이 빠른 전압 검출 수단을 사용할 수 없으므로 전체적인 동작속도가 늦어지는 문제점이 있었다. 따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 파워업 수행 이전에는 전원전압을 사용하고, 그 후에는 승압전압을 사용하여 상기 백-바이어스 전압을 펌핑함에 따라 상기 승압전압과 백-바이어스 전압 간의 간섭을 최소화하여 백바이어스 펌프의 불필요한 구동을 방지하여 전력 소모를 최소화하고, 이에 따라 대기 전류 소모를 최소화하여 전체적인 동작속도가 향상되는 효과가 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a back-bias voltage generation circuit, and to prevent latch-up of an N-well of a core circuit when a triple well structure is provided in the prior art. There is a problem in that the junction capacitance value between the boosted voltage used and the back-bias voltage, which is a bias of the P-well, is increased. In addition, the boosted voltage and the back-bias voltage are applied as an internal voltage, and when the boosted voltage rises during operation, the back-bias voltage also increases, and as the back-bias voltage falls, the boosted voltage decreases together. According to the coupling phenomenon, the back bias pump and the boosted voltage pump are continuously driven, consuming unnecessary power. Also, the fast operation of the voltage detection means cannot be used due to the consumption of standby current (stndby-current). There was a problem of being delayed. Accordingly, the present invention was devised to solve the above-mentioned conventional problems. The boost voltage is obtained by using a power supply voltage before performing power-up and then boosting the back-bias voltage using a boost voltage. By minimizing the interference between the back-bias voltage and the unnecessary driving of the back- ...

Oscillator-free substrate bias generator

본 발명의 회로는 발진기 대신에 클록회로를 구비한 전압 안정기 회로를 구비하므로, 스탠드바이 모드일때 상당한 전력을 절감한다. 저전류를 동작시키고 저전력을 소비하는 DC 전압 레귤레이터는 항시 작동하고 전력을 소비하는 유일한 회로이다. 전하펌프가 펌핑되지 않을때, 회로의 전류는 수 마이크로암페아 이하가 된다. DC 전압 레귤레이터회로는 기판 전압 V bb 가 너무 높을때 자기타이밍회로를 인에이블(enable) 한다. 셀프 타임회로는 기판 전압 V BB 를 더욱 네가티브한 수치로 펌프하는 전하 펌프를 제어한다. 상기 자기타이밍호로는 V BB 가 소망 레벨에 도달할때까지 그리고 DC 전압 레귤레이터 신호가 그것을 정지시킬때까지 전하 펌프를 클록(clock)한다. The circuit of the present invention has a voltage stabilizer circuit having a clock circuit instead of an oscillator, thus saving considerable power when in standby mode. DC voltage regulators that operate low current and consume low power are the only circuits that always operate and consume power. When the charge pump is not pumped, the current in the circuit is below a few microamps. The DC voltage regulator circuit enables the self-timing circuit when the substrate voltage V bb is too high. The self-time circuit controls a charge pump that pumps the substrate voltage V BB to a more negative value. The self-timing arc clocks the charge pump until V BB reaches the desired level and the DC voltage regulator signal stops it.

Semiconductor device capable of preventing fluctuations of substrate potential

검출 회로(3)는 기입 인에이블 신호(/W), 컬럼 어드레스 스트로브 신호(/CAS) 및 출력 제어 신호(OEM)를 수신하여 입/출력 단자(6)로부터 데이터가 입력되는 모드를 사전 검출한다. 기판 전위 발생 회로(2)는 정상적으로 동작하며, 검출 회로(3)가 데이터가 입력되는 모드를 검출한 경우 기판 전위 유지 회로(4)가 또한 동작하여 입/출력 단자(6)로부터 실제로 입력되기 전에 기판 전위 발생부(1) 바이어스 능력이 증가된다. The detection circuit 3 receives the write enable signal / W, the column address strobe signal / CAS and the output control signal OEM and detects in advance the mode in which data is input from the input / output terminal 6 . The substrate potential generating circuit 2 operates normally and when the detection circuit 3 detects a mode in which data is input, the substrate potential holding circuit 4 also operates before it is actually input from the input / output terminal 6 The bias potential of the substrate potential generating portion 1 is increased.

Back bias voltage generator ciruit of semiconductor memory apparatus

1. 청구범위에 기재된 발명이 속한 기술분야 1. TECHNICAL FIELD OF THE INVENTION 반도체 메모리 장치의 백바이어스 전압 발생회로에 관한 것이다. The present invention relates to a back bias voltage generating circuit of a semiconductor memory device. 2. 발명이 해결하려고 하는 기술적 과제 2. The technical problem to be solved by the invention 셀프 리프레쉬 모드에서 소모되는 전류를 감소시키고, 일정 레벨의 백바이어스 전압을 발생하며, 셀프 리프레쉬 모드에서 노말 모드로의 동작을 수행할 시 백바이어스 전압레벨을 용이하게 셋업시키는 백바이어스 전압 발생회로를 구현한다. Implementing back bias voltage generation circuit that reduces current consumption in self refresh mode, generates a certain level of back bias voltage, and easily sets up back bias voltage level when performing normal mode in self refresh mode. do. 3. 발명의 해결방법의 요지 3. Summary of Solution to Invention 리프레쉬 활성화 신호에 응답하여 리프레쉬 모드 동작시 비활성화되고, 노말모드 동작시 활성화되어 충전 펌프 클럭을 발생하는 발진수단과; 상기 충전펌프 클럭에 응답하여 노말모드 동작시 정상레벨의 백바이어스 전압을 발생하고, 리프레쉬 모드 동작시 기준레벨의 백바이어스 전압을 발생하는 충전 펌핑 수단으로 구성한다. An oscillating means which is deactivated in the refresh mode operation in response to the refresh activation signal and activated in the normal mode operation to generate a charge pump clock; And a charge pumping means for generating a back bias voltage at a normal level in normal mode operation and generating a back bias voltage at a reference level in refresh mode operation in response to the charge pump clock. 4. 발명의 중요한 용도 4. Important uses of the invention 셀프 리프레쉬 모드에서 소모되는 전류의 양을 감소시킬 수 있다. The amount of current consumed in the self refresh mode can be reduced.

Semiconductor integrated circuits that can prevent variations in substrate potential

검출 회로(3)는 기입 인에이블 신호(/W), 컬럼 어드레스 스트로브 신호(/CAS) 및 출력 제어 신호(OEM)를 수신하여 입/출력 단자(6)로부터 데이타가 입력되는 모드를 사전검출한다. 기판 전위 발생 회로(2)는 정상적으로 동작하며, 검출회로(3)가 데이타가 입력되는 모드를 검출한 경우 기판 전위 유지 회로(4)가 또한 동작하여 입/출력 단자(6)로부터 실제로 입력되기 전에 기판 전위 발생부(1) 바이어스 능력이 증가된다.

Potential generation circuit

一个电势生成电路，包括至少一对MOS晶体管，每个晶体管都是连成二极管的且串联连接于一个输出节点与一给定电势节点间，以便按同一正方向排列，此两晶体管的各自的背栅极与栅极相连。一个电容连接在所说一对MOS晶体管的连接节点与一输入接点间，交流信号由此输入节点输入。

Current reference circuit and electronic device including the current reference circuit

본 발명에 따른 기준전류 발생회로는, 목표전류레벨에 해당하는 기준전류를 생성하는 기준전류 제공부, 상기 기준전류 제공부로부터 상기 기준전류에 대응하는 제 1 임시기준전류를 수신하여, 상기 수신된 제1 임시기준전류에 기초하여, 제1 비교클록신호를 생성하는 전류-주파수 변환부 및 상기 제 1임시기준전류가 상기 목표전류레벨에 도달하도록, 외부로부터 수신한 기준클록신호의 주파수 및 상기 제 1 비교클록신호의 주파수에 기초하여 상기 제 1임시기준전류를 보상하는 제1 전류 보상부를 포함한다. The reference current generating circuit according to the present invention includes a reference current providing unit generating a reference current corresponding to a target current level, receiving a first temporary reference current corresponding to the reference current from the reference current providing unit, and receiving the received A current-frequency converter generating a first comparison clock signal based on the first temporary reference current and the frequency of the reference clock signal received from the outside and the frequency of the reference clock signal received from the outside so that the first temporary reference current reaches the target current level and a first current compensator for compensating for the first temporary reference current based on the frequency of the first comparison clock signal.

Substrate bias generation circuit

Semiconductor device

Device and Method for training reference voltage

기준 전압 트레이닝 장치 및 방법이 제공된다. 상기 기준 전압 트레이닝 장치는 토글(toggle) 신호 및 기준 전압을 비교하여 비교 신호를 출력하는 비교기부, 상기 비교 신호의 듀티비(duty ratio)를 검사하는 듀티 사이클 디텍터부 및 상기 듀티비가 미리 설정된 조건에 만족하는 경우에는 상기 기준 전압을 확정하고, 상기 듀티비가 미리 설정된 조건에 만족하지 않는 경우에 상기 기준 전압의 레벨을 변경하는 기준 전압 레벨 변경부를 포함하되, 상기 비교기부는 상기 변경된 기준 전압을 이용하여 다시 상기 비교 신호를 출력한다. A reference voltage training apparatus and method are provided. The reference voltage training apparatus compares a toggle signal and a reference voltage to a comparator for outputting a comparison signal, a duty cycle detector for checking a duty ratio of the comparison signal, and a condition in which the duty ratio is set in advance. a reference voltage level changing unit for determining the reference voltage when satisfied, and changing the level of the reference voltage when the duty ratio does not satisfy a preset condition, wherein the comparator unit uses the changed reference voltage to Again, the comparison signal is output.

Unstability preventing circuit of the semiconductor chip

내용 없음. No content.

Vpp level detector of high voltage generator

본 발명은 고전위 발생장치의 Vpp 레벨 감지기에 관한 것으로서, 고전위 발생장치에서 Vpp 전압 레벨이 떨어질 때 이를 감지하여 펌핑하도록 함으로써 항상 일정한 Vpp 전압 레벨을 갖도록 하는 Vpp 레벨 감지기를 간단하게 NMOS트랜지스터와 저항을 사용하여 감지 속도를 향상시킬 뿐만 아니라 동시에 소비되는 전류량을 줄일 수 있도록 하여 레이아웃 면적을 줄일 수 있으며, Vpp 레벨의 변화에 의한 페일 양상을 줄일 수 있는 이점이 있다. The present invention relates to a Vpp level detector of a high potential generator, wherein a high voltage generator (Vpp) level detector, which has a constant Vpp voltage level by detecting and pumping when the Vpp voltage level falls, is simply a NMOS transistor and a resistor. In addition to improving the detection speed by using, it is possible to reduce the amount of current consumed at the same time, thereby reducing the layout area and reducing the fail pattern caused by the change of the Vpp level.

Semiconductor memory device

Semiconductor memory device having the operating voltage of the memory cell controlled

An SRAM circuit operates at a reduced operation margin, especially at a low operating voltage by increasing or optimizing the operation margin of the SRAM circuit. The threshold voltage of the produced transistor in the SRAM circuit is detected to compare the operating voltage of a memory cell with the operating voltage of a peripheral circuit in order to adjust it to the optimum value, and the substrate bias voltage is further controlled.

Substrate bias voltage control circuit of semiconductor memory apparatus

1. 청구범위에 기재된 발명이 속한 기술분야 1. TECHNICAL FIELD OF THE INVENTION 반도체 메모리장치 Semiconductor memory device 2. 발명이 해결하려고 하는 기술적 과제 2. The technical problem to be solved by the invention 반도체 메모리장치의 기판전압을 모드에 따라 제어함 Control the substrate voltage of semiconductor memory device according to the mode 3. 발명의 해결 방법의 요지 3. Summary of the Solution of the Invention 감지신호에 의해 활성화되어 기판전압을 발생하는 회로를 구비하는 반도체 메모리장치에서, 감지신호를 발생하는 회로가 제1전원과 제2전원 사이에 공통 연결되고 제어단이 상기 기판전압에 연결되며, 상기 기판전압이 설정된 제1전위레벨 보다 높을시 제1감지신호를 발생하는 수단과, 상기 제1전원과 제2전원 사이에 연결되고 제어단이 특정모드신호에 연결되며, 상기 모드신호가 활성화될 시 스위칭되어 제2전위레벨의 기판전압을 발생하기 위한 제2감지신호를 발생하는 수단으로 구성함 In a semiconductor memory device having a circuit activated by a detection signal to generate a substrate voltage, a circuit for generating a detection signal is commonly connected between a first power supply and a second power supply, and a control terminal is connected to the substrate voltage. Means for generating a first sensing signal when the substrate voltage is higher than the set first potential level, between the first power source and the second power source, a control terminal connected to a specific mode signal, and when the mode signal is activated Means for generating a second sensed signal for switching to generate a substrate voltage of a second potential level 4. 발명의 중요한 용도 4. Important uses of the invention 반도체 메모리장치에서 특정모드시 노말모드에서 사용하는 기판전압과 다른 전위로 기판전압을 발생할 수 있으며, 기판전압을 사용하지 않는 모드시 기판전압의 발생을 중단시킴 In the semiconductor memory device, the substrate voltage can be generated at a potential different from the substrate voltage used in the normal mode in the specific mode, and the generation of the substrate voltage is stopped in the mode not using the substrate voltage.

Detecting circuit of semiconductor devices back bias level

내용 없음. No content.

Circuit for generating negative voltages

用于产生负电压的电路装置，具有第一个晶体管(Tx2)，它的第一个端子与电路装置的一个输入端(E)而它的第二个端子与电路装置的一个输出端(A)相连接，并且它的栅极通过第一个电容(Cb2)与第一个时钟信号端子相连接，具有第二个晶体管(Ty2)，它的第一个端子与第一个晶体管(Tx2)的栅极端子相连接，它的第二个端子与第一个晶体管(Tx2)的第二个端子相连接，并且它的栅极端子与第一个晶体管(Tx2)的第一个端子相连接，并且具有第二个电容(Cp2)，它的第一个端子与第一个晶体管(Tx2)的第二个端子相连接，并且它的第二个端子与第二个时钟信号端子相连接，并且其中该晶体管(Tx2，Ty2)是在一个三重槽(Triple-well)中构成的MOS晶体管，第三个晶体管(Tz2)的第一个端子与第一个晶体管(Tx2)的第二个端子相连接，第三个晶体管(Tz2)的第二个端子与含有该晶体管(Tx2，Ty2，Tz2)的槽(Kw)相连接，并且第三个晶体管(Tz2)的栅极端子与第一个晶体管(Tx2)的第一个端子相连接。

Semiconductor integrated circuit device

Apparatus and Method for Generating Substrate Bias Voltage

본 발명은 반도체 메모리 장치에서 노멀 동작 및 리프레쉬 동작 시에 각기 다른 전압 레벨을 제공하기 위한 기판 바이어스 전압 발생 장치 및 방법에 관한 것으로, 본 발명의 기판 바이어스 전압 발생 장치는 셀프 리프레쉬 신호, 아이들 신호 및 리프레쉬 카운트 신호에 응답하여 기준전압과 기판 바이어스 전압의 레벨을 비교하여 발진 구동 신호를 출력하며, 노멀 모드에서 기판 바이어스 전압이 제 1 레벨 이상이면 발진 구동 신호를 인에이블하고, 셀프 리프레쉬 모드에서 기판 바이어스 전압이 제 2 레벨이면 발진 구동 신호를 디스에이블하고, 셀프 리프레쉬 모드에서 기판 바이어스 전압이 제 3 레벨이면 발진 구동 신호를 디스에이블하는 기판 바이어스 전압 검출부, 발진 구동 신호에 따라 발진 신호를 출력하는 발진부, 및 발진부의 출력 신호에 따라 기판 바이어스 전압의 펌핑을 제어하여 펌핑 제어된 기판 바이어스 전압을 출력하는 전압 펌핑부를 포함하여, 리프레쉬 동작의 신뢰성을 보장할 수 있고, 리프레쉬 동작시에 노멀 동작시보다 높은 레벨의 기판 바이어스 전압을 사용함으로써 누설 전류를 감소시킬 수 있다. The present invention relates to a substrate bias voltage generator and a method for providing different voltage levels during normal operation and refresh operation in a semiconductor memory device. The substrate bias voltage generator of the present invention provides a self refresh signal, an idle signal and a refresh operation. In response to the count signal, the oscillation drive signal is output by comparing the level of the reference voltage and the substrate bias voltage. When the substrate bias voltage is greater than or equal to the first level in the normal mode, the oscillation drive signal is enabled, and the substrate bias voltage is in the self refresh mode. A substrate bias voltage detector for disabling the oscillation drive signal at the second level, and disabling the oscillation drive signal at the third level in the self-refresh mode; an oscillator for outputting an oscillation signal according to the oscillation drive signal; Depending on the output signal of the oscillator (D) including a voltage pumping unit for controlling the pumping of the substrate bias voltage to output the pumped controlled substrate bias voltage, thereby ensuring the reliability of the refresh operation, and using the substrate bias voltage at a higher level than the normal operation during the refresh operation. By doing so, leakage current can be reduced. 셀프 리프레쉬, 기판 바이어스 전압 Self Refresh, Board Bias Voltage

Semiconductor Memory Device with Multiple Ground Power Supplies

1. 청구범위에 기재된 발명이 속한 기술분야 반도체 메모리장치. 2. 발명이 해결하려고 하는 기술적 과제 반도체 메모리 장치에 서로 다른 전압레벨을 갖는 두 종류의 접지전압을 공급하여 반도체 메모리장치의 동작을 안정화시키고 전력소모를 감소시킴. 3. 발명의 해결 방법의 요지 내부접지전압을 동작전원으로 입력하는 제1회로들과 외부접지전압을 동작전원으로 입력하는 제2회로들로 구성되며, 상기회로들이 메모리코어 및 주변회로들인 반도체 메모리장치가, 제1전압레벨을 갖는 외부전원전압과, 제4 전압레벨을 갖는외부접지전압과, 제2전압레벨의 내부전원전압을 발생하는 수단과, 제3전압레벨의 내부접지전압을 발생하는 수단들을 구비하여, 내부접지전압을 칩내부의 접지전압으로 공급하고 외부접지전압을 칩 내부의 특정 회로에 공급하여 전압 스윙폭을작게 유지하므로써 전력 소모를 감소시킴. 4. 발명의 중요한 용도 반도체 메모리장치에서 서로 다른 레벨의 접지전압을 공급하여, 별도의 백바이어스전원발생기를 사용하지 않으며, 승압전압을 효율적으로 발생하고, 메모리셀의 누설전류를 감소시키는 동시에 센스앰프의 감지속도를 향상시킴.

bias compensating circuit

PURPOSE: A circuit for compensating a bias is provided maintain voltage ratio applied to a main system by minimizing the variation of current due to the fluctuation of a voltage source. CONSTITUTION: A first register is connected to a voltage source(Vdd) to maintain an adequate voltage. An NMOS transistor is connected to a first node. The drain of the NMOS transistor is coupled to the first resistor and the source thereof is connected to a main system. A bias is applied to the gate of the NMOS transistor. A second resistor is connected to the voltage source(Vdd) to maintain an adequate voltage. A PMOS transistor is coupled to the first node. The source of the PMOS transistor is connected to the second resistor and the drain thereof is coupled to the main system. As to the gate of the NMOS transistor, the bias is applied to the gate of the PMOS transistor.

Parallel Nonvolatile Semiconductor Memory and How to Use It

대규모 집적회로에 의해 구성하는 경우에 적용해서 적합한 병렬형 불휘발성 반도체기억장치 및 그 장치의 사용방법에 관한 것으로, 매우 고밀도의 전기적 리라이트 가능한 불휘발성 기억장치를 용이하게 실현하기 위해, 반도체기판상에 형성된 제어게이트, 부유게이트, 게이트절연막, 드레인영역 및 소오스영역을 구비한 MOS트랜지스터로 이루어지는 여러개의 메모리셀을 매트릭스형상으로 배치하고, 제어게이트의 상호간을 행마다 개별의 워드선에 의해 접속하고, 드레인영역의 상호간을 열마다 개별의 데이타선에 의해 접속하고 또한 소오스영역의 상호간을 열마다 개별의 소오스선에 의해 접속하는 것에 의해서 구성한 병렬접속의 메모리어레이로 이루어지는 반도체 기억장치에 있어서, 메모리셀을 구성하는 개개의 MOS트랜지스터는 하나의 도전형의 반도체기판상에 이 기판과 전기적으로 분리해서 형성된 동일 도전형의 웰층내에 드레인영역 및 소오스영역을 각각 형성해서 이루어지는 것이고, 또한 각 메모리셀의 웰층의 상호간은 웰배선에 의해서 공통으로 접속되는 구성으로 하였다. The present invention relates to a parallel type nonvolatile semiconductor memory device and a method of using the device, which are suitable for use in a large-scale integrated circuit. In order to easily realize a very high density electrically rewritable nonvolatile memory device, A plurality of memory cells comprising a control gate, a floating gate, a gate insulating film, a drain region, and a source region formed in the MOS transistor are arranged in a matrix form, and the control gates are connected to each other by individual word lines for each row; In a semiconductor memory device comprising a parallel array of memory arrays formed by connecting the drain regions to each other by a separate data line for each column and connecting the source regions to each other by a separate source line for each column, Each MOS transistor that constitutes one conductive type A drain region and a source region are formed in a well layer of the same conductivity type formed on the semiconductor substrate electrically separated from the substrate, and the well layers of each memory cell are connected in common by well wiring. It was. 이러한 구성으로 하는 것에 의해, 드레인영역에 있어서의 누설전류의 발생이 방지되어 누설전류에 따른 절연막의 열화를 회피할 수 있고, 고집적 반도체기억장치를 실현할 수 있게 된다. This configuration prevents the occurrence of leakage current in the drain region, thereby avoiding deterioration of the insulating film due to the leakage current, and achieving a highly integrated semiconductor memory device.

Word line switch circuit

본 발명은 워드라인 스위치 회로에 관한 것으로, 메모리 셀에 워드라인 전압을 인가하기 위한 워드라인 스위치 회로에서 고전압을 전송하는 트랜지스터의 웰 바이어스를 소스와 동일한 레벨의 전압을 인가함으로 인해 소자의 바디바이어스 효과를 방지할 수 있고, 펌핑된 워드라인 전압을 트랜지스터의 문턱 전압만큼의 전압강하 없이 셀의 워드라인에 전달할 수 있는 워드라인 스위치 회로를 제공한다.

Signal transmission method, signal transmission circuit, and semiconductor integrated circuit using the same

각 부하용량을 각각 신호선에 의해 구동하는 신호전송회로에 있어서, 각 신호선은 서로 다른 신호선과 스위치를 통해 접속가능하고, 다른 전위에 있는 2개의 신호선을 상기 스위치에 의해 서로 접속하는 것에 의해, 신호선의 전위를 전하재분배로 변화하고 전원선, 접지선을 통한 전하의 충방전을 없앤다. 따라서, n개의 부하용량이 서로 같은 경우는 각 신호선의 전위변화의 위상이 1 / n씩 어긋나도록 스위치를 제어하면, n개의 부하용량을 독립하여 구동한 경우와 비교하여, 1/n의 전하량으로 부한용량을 구동할 수 있고, 소비전류의 저감을 도모할 수 있다. In a signal transmission circuit for driving each load capacitance by a signal line, each signal line is connectable through a different signal line and a switch, and two signal lines at different potentials are connected to each other by the switch. The potential is changed by the charge redistribution, and the charge and discharge of the charge through the power supply line and the ground line are eliminated. Therefore, when the n load capacities are equal to each other, if the switch is controlled so that the phase shift of the signal line shifts by 1 / n, the amount of charge is 1 / n, compared with the case where the n load capacities are driven independently. Infinite capacitance can be driven, and the consumption current can be reduced.

Dual back bias voltage supplying device

동일한 반도체칩의 기판상에 형성되는 엔모오스 트랜지스터 및 상기 엔모오스트랜지스터들로 구성된 로직회로들의 동작 특성을 고려하여 백 바이어스 전압을 다르게 공급할 수 있도록 서로다른 영역에 서로다른 레벨의 백 바이어스를 공급하는 장치에 관한 것이다. 상기의 듀얼 백 바이어스 전압 발생기는 동일 반도체 기판상에 형성되어 소정 레벨의 백 바이어스 전압을 입력받는 제1 및 제2기판영역과, 전원전압의 입력에 응답하여 제1레벨의 백 바이어스 전압을 발생하여 상기 제1기판영역에 공급하는 백 바이어스 전압 발생수단과, 상기 백 바이어스 전압 발생수단의 출력노드와 상기 제2기판영역 사이에 접속되어 상기 발생된 제1레벨의 백 바이어스 전압을 제2레벨의 백 바이어스 전압으로 변환하여 출력하는 전압레벨변환수단을 포함하여 구성된다.

Circuit for Generating of Back Bias Voltage

본 발명은 저전압 디램을 구현하기 위한 백바이어스전압(VBB) 발생회로에 관한 것으로, 제 1 내지 제 4 클럭 신호를 각각 제 1 내지 제 4 노드로 인가하는 제 1 내지 제 4 클럭 신호 입력 회로부와, 상기 제 1 노드 및 제 2 노드의 최고 전압을 제로(Zero)로 클램핑하는 클램프 회로부와, 상기 제 1 노드 신호에 따라서 상기 제 3 노드를 프리차지하는 제 1 프리차지부 및 상기 제 2 노드 신호에 따라서 상기 제 4 노드를 프리차지하는 제 2 프리차지부와, 상기 제 4 노드 신호에 따라서 음(-)전위의 제 3 노드의 전하를 백바이어스전압 단자(VBB)에 선택적으로 출력하는 제 1 펌핑 회로부 및 상기 제 3 노드 신호에 따라서 음(-)전위의 상기 제 4 노드의 전하를 백바이어스전압 단자에 선택적으로 출력하는 제 2 펌핑 회로부를 포함하여 구성된다. The present invention relates to a back bias voltage (VBB) generation circuit for implementing a low voltage DRAM, the first to fourth clock signal input circuit unit for applying the first to fourth clock signal to the first to fourth node, respectively; The clamp circuit unit clamps the highest voltages of the first and second nodes to zero, and the first precharge unit and the second node signal to precharge the third node according to the first node signal. A second precharge unit for precharging the fourth node, a first pumping circuit unit for selectively outputting a charge of a third node having a negative potential to a back bias voltage terminal VBB according to the fourth node signal; And a second pumping circuit unit for selectively outputting a charge of the fourth node having a negative potential to a back bias voltage terminal according to the third node signal. 백바이어스전압(VBB : Back Bias Voltage) Back Bias Voltage (VBB)

Voltage generator

본 발명은 전압 발생기에 관한 것으로서, 특히, 센스앰프 영역에 사용되는 전압을 펌핑전압(VPP)과 전원전압(VDD)의 중간 레벨의 전압(VDP)으로 생성하여 전류 소모를 줄일 수 있도록 하는 기술을 개시한다. 이러한 본 발명은 펌프 인에이블 신호의 활성화 여부에 따라 펌핑 제어를 위한 발진신호를 주기적으로 출력하는 오실레이터와, 발진신호에 따라 차지 펌핑 동작을 수행하여 펌핑전압과 전원전압의 중간 레벨을 갖는 전압을 출력하는 차지펌핑부, 및 차지펌핑부의 출력 전압의 레벨을 검출하여 그 검출 결과에 따라 펌프 인에이블 신호를 출력하는 레벨 검출부를 포함하여, 센스앰프 영역과 서브 워드라인 드라이버의 동작 전류를 줄일 수 있도록 한다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage generator. In particular, a technique for reducing current consumption by generating a voltage used in a sense amplifier region as a voltage VDP at an intermediate level between a pumping voltage VPP and a power supply voltage VDD. It starts. The present invention outputs a voltage having an intermediate level between the pumping voltage and the power supply voltage by performing an oscillator that periodically outputs an oscillation signal for pumping control according to whether the pump enable signal is activated, and a charge pumping operation according to the oscillation signal. And a level detector for detecting a level of an output voltage of the charge pump and outputting a pump enable signal according to the detection result, thereby reducing the operating current of the sense amplifier region and the sub word line driver. .

Internal source voltage generating circuit of semiconductor memory device

An internal source voltage generating circuit includes a comparison voltage generator which receives reference and internal source voltages, outputs to a second node a comparison voltage differentially amplified responsive to a voltage of a first node according to a difference between the reference and internal source voltages, and allows a driving current to flow from a third node to a fourth node. An internal voltage driver transfers an external source voltage to an output node responsive to the comparison voltage. A driving current generator increases the driving current flowing from the third node to the fourth node responsive to the voltage of the first node which rises when the internal source voltage abruptly drops. The internal source voltage generating circuit is insensitive to variation of an external source voltage, exhibits improved response time when an internal source voltage abruptly drops, and stably generates an internal source voltage.

Semiconductor device

Bulk voltage supply circuit for semiconductor memory device and its method

1. 청구범위에 기재된 발명이 속하는 기술 분야 : 1. The technical field to which the invention described in the claims belongs: 본 발명은 반도체 메모리 장치의 벌크전압 인가회로 및 벌크전압 인가방법에 관한 것이다. The present invention relates to a bulk voltage application circuit and a bulk voltage application method of a semiconductor memory device. 2. 발명이 해결하려고 하는 기술적 과제 : 2. The technical problem to be solved by the invention: 종래의 반도체 메모리 장치에서는 트랜지스터들의 드레시홀드전압이 고정되어 제조되므로 비활성상태에서 전력소비가 작으면서 활성상태에서 동작속도가 빠른 반도체 메모리장치를 구현하기가 어려웠다. In the conventional semiconductor memory device, since the threshold voltages of the transistors are manufactured to be fixed, it is difficult to implement a semiconductor memory device having a low power consumption in an inactive state and a fast operation speed in an active state. 3. 발명의 해결방법의 요지 : 3. Summary of the solution of the invention: 본 발명에서는 활성 및 비활성상태에 따라 피모오스 트랜지스터의 벌크로 인가되는 전압레벨을 다르게 하는 반도체 메모리 장치의 벌크전압 인가회로를 구현하여 트랜지스터들의 드레스홀드값을 조정가능하게 하므로서 상기 두가지 측면을 모두 만족하는 반도체 메모리 장치를 구현하였다. The present invention implements a bulk voltage application circuit of a semiconductor memory device which varies a voltage level applied to bulk of a PMOS transistor according to active and inactive states, thereby making it possible to adjust the dresshold values of transistors, thereby satisfying both aspects. A semiconductor memory device is implemented. 4. 발명의 중요한 용도 : 4. Important uses of the invention: 비활성시 전력소비가 줄어들고 활성시 동작속도가 빠른 반도체 메모리 장치가 제공되므로써 효과적인 동작을 하는 반도체 메모리 장치가 구현된다. By providing a semiconductor memory device that reduces power consumption when inactive and has a high operating speed when activated, a semiconductor memory device that operates effectively is implemented.

Semiconductor Memory Operating in Response to Layered Internal Potentials

반도체 기억장치는, 반도체기판과, 복수의 메모리 블록과, 제1 및 제2의 기판전위발생회로와, 선택회로를 포함한다. 반도체기판은, 메모리블록에 대응하는 복수의 웰을 포함한다.각 메모리블록은, 대응하는 웰상에 형성된 복수의 메모리셀을 포함한다. 선택회로는, 활성화된 메모리블록의 웰에 제1의 기판전위 발생회로로 부터의 기판전위 발생회로로 부터의 깊은 기판전위를 공급하고, 또한 비활서의 메모리 블록의 웰에 제2위의 기판전위 발생회로로 부터의 얕을 기관전위를 공급한다. 이것에 의해 비활성메모리블록에서의 소비전력이 저강되는데도 불구하고, 비활성메모리 블록에서의 최저한의 동작이 보증된다.

Semiconductor memory

(57)【要約】 【課題】 リフレッシュの必要なＤＲＡＭ等において、 プロセスパラメータのバラツキ等によりリフレッシュの 実力が小さいデバイスを使えるようにする。 【解決手段】 半導体記憶装置の中に、半導体基板に形 成されたメモリセルと同様に形成されたダミーメモリセ ルのリークを検知してそのリーク量に応じた出力信号を 発生するリーク検知手段と、このリーク検知手段の出力 信号によって半導体基板の基板電圧を制御する基板電圧 発生手段とを備える。

Circuit for generating negative voltages

본 발명은 음의 전압을 생성하기 위한 회로에 관한 것이고, 상기 회로는 제 1 단자가 입력 단자(E)에 접속되고 제 2 단자가 회로의 출력 단자(A)에 접속되고, 게이트 단자가 제 1 캐패시터(Cb2)를 통하여 제 1 클럭 펄스 단자에 접속되는 제 1 트랜지스터(Tx2)를 포함한다. 상기 회로는 제 1 단자가 제 1 트랜지스터(Tx2)의 게이트 단자에 접속되고, 제 2 단자가 제 1 트랜지스터(Tx2)의 제 2 단자에 접속되고, 게이트 단자가 제 1 트랜지스터(Tx2)의 제 1 단자에 접속되는 제 2 트랜지스터(Ty2)를 더 포함한다. 게다가, 상기 회로는 제 1 단자가 제 1 트랜지스터(Tx2)의 제 2 단자에 접속되고 제 2 단자가 제 2 클럭 펄스 단자에 접속되는 제 2 캐패시터(Cp2)를 포함한다. 트랜지스터(Tx2, Ty2)는 3중-웰 구조로 구성된 MOS 트랜지스터이다. 제 3 트랜지스터(Tz2)의 제 1 단자는 제 1 트랜지스터(Tx2)의 제 2 단자에 접속되고, 상기 제 3 트랜지스터(Tz2)의 제 2 단자는 트랜지스터(Tx2, Ty2, Tz2)를 하우징하는 쓰로우(Kw)에 접속되고, 제 3 트랜지스터(Tz2)의 게이트 단자는 제 1 트랜지스터(Tx2)의 제 1 단자에 접속된다. The present invention relates to a circuit for generating a negative voltage, in which the first terminal is connected to the input terminal (E), the second terminal is connected to the output terminal (A) of the circuit, and the gate terminal is connected to the first terminal. The first transistor Tx2 is connected to the first clock pulse terminal through the capacitor Cb2. The circuit has a first terminal connected to the gate terminal of the first transistor Tx2, a second terminal connected to the second terminal of the first transistor Tx2, and a gate terminal connected to the first terminal of the first transistor Tx2. It further comprises a second transistor Ty2 connected to the terminal. In addition, the circuit includes a second capacitor Cp2 having a first terminal connected to a second terminal of the first transistor Tx2 and a second terminal connected to a second clock pulse terminal. The transistors Tx2 and Ty2 are MOS transistors having a triple-well structure. The first terminal of the third transistor Tz2 is connected to the second terminal of the first transistor Tx2, and the second terminal of the third transistor Tz2 houses a throw housing the transistors Tx2, Ty2, and Tz2. It is connected to Kw, and the gate terminal of the third transistor Tz2 is connected to the first terminal of the first transistor Tx2.

Parallel type nonvolatile semiconductor memory device and method of using the same

대규모 집적회로에 의해 구성하는 경우에 적용해서 적합한 병렬형 불휘발성 반도체기억장치 및 그 장치의 사용방법에 관한 것으로, 매우 고밀도의 전기적 리라이트 가능한 불휘발성 기억장치를 용이하에 실현하기 위해, 반도체기판상에 형성된 제어게이트, 부유게이트, 게이트절연막, 드레인영역 및 소오스영역을 구비한 MOS트랜지스터로 이루어지는 여러개의 메모리셀을 매트릭스형상으로 배치하고, 제어게이트의 상호간을 행마다 개별의 워드선에 의해 접속하고, 드레인영역의 상호간을 열마다 개별의 데이타선에 의해 접속하고 또한 소오스영역의 상호간을 열마다 개별의 소오스선에 의해 접속하는 것에 의해서 구성한 병렬접속의 메모리어레이로 이루어지는 반도체 기억장치에 있어서, 메모리셀을 구성하는 개개의 MOS트랜지스터는 하나의 도전형의 반도체기판상에 이 기판과 전기적으로 분리해서 형성된 동일 도전형의 웰층내에 드레인영역 및 소오스영역을 각각 형성해서 이루어지는 것이고, 또한 각 메모리셀의 웰층의 상호간은 웰배선에 의해서 공통으로 접속되는 구성으로 하였다. 이러한 구성으로 하는 것에 의해, 드레인영역에 있어서의 누설전류의 발생이 방지되어 누설전류에 따른 절연막의 열화를 회피할 수 있고, 고집적 반도체기억장치를 실현할 수 있게 된다.

Power-up circuit

PURPOSE: A power-up circuit is provided to arbitrarily control the initial state of an inner signal of a memory chip regardless of a bias voltage of a substrate. CONSTITUTION: The circuit includes a substrate bias potential sensing portion(30), a power-up signal controlling portion(40) and a power-up signal generating portion(60). The substrate bias potential sensing portion senses a substrate bias potential level. The power-up signal controlling portion controls generation of a power-up signal from the outside regardless of the substrate bias potential. The power-up signal generating portion generates a power-up enabling signal regardless of the substrate bias potential when an output signal from the power-up signal controlling portion is in the first logic state. The substrate bias potential sensing portion consists of the first P channel MOS transistor(MP1), the second P channel MOS transistor(MP2), a capacitor(C1), and an inverter(11).

Semiconductor integrated circuit

(57)【要約】 【課題】基板電位を安定化するとともに電源投入時にお ける異常電流の発生を抑圧する。 【解決手段】ウェルを４つのＰウェル１１〜１４に分割 し、これらＰウェル１１〜１４の各々がＢＢＧ２１〜２ ４の各々をそれぞれ備える。

Bulk voltage application circuit and bulk voltage application method of semiconductor memory device

1. 청구 범위에 기재된 발명이 속한 기술분야 본 발명은 반도체 메모리장치의 벌크전압 인가회로 및 벌크전압 인가방법에 관한 것이다. 2. 발명이 해결하려고 하는 기술적 과제 종래의 반도체 메모리장치에서는 트랜지스터들의 드레시홀드전압이 고정되어 제조되므로 비활성상태에서 전력소비가 작으면서 활성화상태에서 동작속도가 빠른 반도체 메모리장치를 구현하기가 어려웠다. 3. 발명의 해결방법의 요지 본 발명에서는 활성화 및 비활성화상태에 따라 피모오스 트랜지스터의 벌크로 인가되는 전압레벨을 다르게 하는 반도체 메모리장치의 벌크전압 인가회로를 구현하여 트랜지스터들의 드레시홀드값을 조정가능하게 하므로써 상기 두가지 측면을 모두 만족하는 반도체 메모리장치를 구현하였다. 4. 발명의 중요한 용도 비활성화시 전력소비가 줄어들고 활성화시 동작속도가 빠른 반도체 메모리장치가 제공되므로써 효과적인 동작을 하는 반도체 메모리장치가 구현된다.

Enable signal clamp circuit for semiconductor memory device

Semiconductor memory apparatus

1.청구범위에 기재된 발명이 속한 기술분야 1. Technical field to which the invention described in the claims belongs 반도체 메모리장치 Semiconductor memory device 2. 발명이 해결하려고 하는 기술적 과제 2. The technical problem to be solved by the invention 반도체 메모리 장치에 서로 다른 전압레벨을 갖는 두 종류의 접지전압을 공급하여 반도체 메모리장치의 동작을 안정화시키고 전력소모를 감소시킴. By supplying two types of ground voltages having different voltage levels to the semiconductor memory device, the operation of the semiconductor memory device is stabilized and power consumption is reduced. 3. 발명의 해결 방법의 요지 3. Summary of the Solution of the Invention 내부접지전압을 동작전원으로 입력하는 제1회로들과 외부접지전압을 동작전원으로 입력하는 제2회로들로 구성되며, 상기 회로들이 메모리코어 및 주변회로들인 반도체 메모리장치가, 제1전압레벨을 갖는 외부전원전압과, 제4 전압레벨을 갖는 외부접지전압과, 제2전압레벨의 내부전원전압을 발생하는 수단과, 제3전압레벨의 내부접지전압을 발생하는 수단들을 구비하여, 내부접지전압을 칩내부의 접지전압으로 공급하고 외부접지전압을 칩 내부의 특정 회로에 공급하여 전압 스윙폭을 작게 유지하므로써 전력 소모를 감소시킴. And a first circuit for inputting an internal ground voltage as an operating power source and a second circuit for inputting an external ground voltage as an operating power source, wherein the semiconductor memory device, wherein the circuits are memory cores and peripheral circuits, sets the first voltage level. An internal ground voltage comprising means for generating an external power supply voltage, an external ground voltage having a fourth voltage level, means for generating an internal power supply voltage of a second voltage level, and means for generating an internal ground voltage of a third voltage level. Supply power to the ground voltage inside the chip and supply the external ground voltage to a specific circuit inside the chip to keep the voltage swing width small to reduce power consumption. 4. 발명의 중요한 용도 4. Important uses of the invention 반도체 메모리장치에서 서로 다른 레벨의 접지전압을 공급하여, 별도의 백바이어스전원발생기를 사용하지 않으며, 승압전압을 효율적으로 발생하고, 메모리셀의 누설전류를 감소시키는 동시에 센스앰프의 감지속도를 향상시킴. Provides ground voltages of different levels in semiconductor memory devices, eliminating the need for a separate back bias power generator, efficiently generating boosted ...

Semiconductor device

로직 회로와 SRAM 회로가 혼재된 시스템 LSI에서, 누설 전류를 저감하여, 스탠바이 상태의 소비 전력을 저감한다. 시스템 LSI 내의 로직 회로에는 전원 스위치를 설치하여, 스탠바이 시에는 그 스위치를 차단하여 누설 전류를 저감한다. 동시에 SRAM 회로에서는, 기판 바이어스를 제어하여 누설 전류를 저감한다. In a system LSI in which logic and SRAM circuits are mixed, leakage current is reduced to reduce power consumption in the standby state. Logic circuits in the system LSI are provided with a power switch, and in standby, the switch is cut off to reduce leakage current. At the same time, in the SRAM circuit, the substrate bias is controlled to reduce the leakage current. MIS 트랜지스터, 스태틱형 메모리 셀, 메모리 어레이, 로직 회로 MIS transistors, static memory cells, memory arrays, logic circuits

Pumping voltage regulation circiut

본 발명은 펌핑 전압 레귤레이션 회로에 관한 것으로, 소정의 전압으로 펌핑하기 위한 펌핑 회로와, 상기 펌핑 전압을 분배하기 위한 전압 분배 수단과, 상기 펌핑 전압이 소정 전압으로 상승할 때 발생하는 인에이블 신호에 따라 상기 분배 전압을 레벨 쉬프트하기 위한 레벨 쉬프터와, 상기 레벨 쉬프터의 출력 신호에 따라 상기 분배 전압 또는 접지 전압을 출력하기 위한 제 1 스위칭 수단과, 상기 제 1 스위칭 수단의 출력 신호에 따라 상기 펌핑 회로의 펌핑 전압을 출력 단자로 출력하기 위한 제 2 스위칭 수단을 포함하여 이루어져, 펌핑 전압의 리플을 획기적으로 줄일 수 있어 셀에 안정적인 바이어스를 공급할 수 있고, 이에 의해 셀의 프로그램 또는 소거 효율을 향상시킬 수 있으며, 소자의 수율을 향상시킬 수 있는 펌핑 전압 레귤레이션 회로가 제시된다. The present invention relates to a pumping voltage regulation circuit, comprising: a pumping circuit for pumping to a predetermined voltage, a voltage distribution means for distributing the pumping voltage, and an enable signal generated when the pumping voltage rises to a predetermined voltage. A level shifter for level shifting the divided voltage, first switching means for outputting the divided voltage or the ground voltage according to an output signal of the level shifter, and the pumping circuit according to an output signal of the first switching means. It comprises a second switching means for outputting the pumping voltage of the output terminal, can significantly reduce the ripple of the pumping voltage can supply a stable bias to the cell, thereby improving the program or erase efficiency of the cell And a pumping voltage regulation circuit to improve device yield It is poetry.

A high voltage detector for a high voltage generator

본 발명은 고전압의 소모가 크지 않은 경우에는 일반적인 고전압 검출기와 동일하게 동작하고 고전압의 소모가 큰 경우에는 고전압 발생기의 고전압 유지 시간을 늘려줄 수 있는 고전압 검출기에 관한 것이다. 본 발명에 따른 고전압 발생기용 고전압 검출기는 제 1 기준전압 및 제 2 기준전압(고전압의 전압 분배에 의하여 얻은 전압)을 수신하여 제 1 신호를 출력하는 제 1 차동 증폭기와, 제 1 기준전압 및 제 3 기준전압(고전압의 전압 분배에 의하여 얻은 전압으로, 제 2 기준전압 보다 낮은 전압)을 수신하여 제 2 신호를 출력하는 제 2 차동 증폭기와, 제 1 신호의 인에이블 시점을 검출하여 제 1 검출신호를 출력하는 제 1 검출기와, 제 2 신호의 디스에이블 시점을 검출하여 제 2 검출신호를 출력하는 제 2 검출기와, 제 1 검출신호와 제 2 검출신호를 수신하여 제 3 검출신호를 출력하는 플립플롭 회로와, 제 1 신호, 제 3 검출신호 및 동작 모드 신호를 수신하여 고전압 검출기의 출력신호를 출력하는 출력부를 포함한다. 본 발명의 고전압 검출기는 스탠드바이 모드 및 번인 모드에서는 기존의 회로 동작과 동일하게 동작하지만, 액티브 모드의 경우에는 펌핑 회로가 비활성화되는 시점을 늦춤으로써 종래의 경우보다 상대적으로 안정된 고전압 레벨을 출력할 수 있도록 한다. The present invention relates to a high voltage detector that can be operated in the same way as a general high voltage detector when the consumption of high voltage is not large, and to increase the high voltage holding time of the high voltage generator when the consumption of the high voltage is large. A high voltage detector for a high voltage generator according to the present invention includes a first differential amplifier for receiving a first reference voltage and a second reference voltage (voltage obtained by voltage division of a high voltage) and outputting a first signal; A second differential amplifier for receiving a three reference voltage (voltage obtained by voltage division of the high voltage and lower than the second reference voltage) and outputting a second signal, and detecting an enable time of the first signal to detect the first A first detector for outputting a signal, a second detector for detecting a disable point in time of the second signal, and outputting a second detection signal, and receiving a first detection signal and a second detection signal and outputting a third detection signal And a flip-flop circuit and an output unit for receiving the first signal, the third detection signal, and the operation mode signal and outputting an output signal of the high voltage detector. In the ...

A device and method for maintaining a high voltage for low power applications

A voltage generator for low power applications includes a circuit for generating, controlling and maintaining a high voltage (VCCP) for low power applications in an integrated circuit. The circuit includes separate standby circuits (110, 300, 478) and active circuits (200, 478', 500) for pumping V CCP of a DRAM under different circumstances. The standby and active circuits operate independently of one another, but may operate simultaneously, to pump charge to V CCP . The standby circuit is generally a low power circuit activated in response to power up and leakage current conditions to maintain the high voltage (V CCP ). The active circuit is generally a larger circuit and can pump more current. The active circuit is generally responsive to the word lines being driven. Accordingly, the voltage generator can maintain V CCP while minimizing power consumption in DRAM.

Low-power semiconductor memory device

A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

DEVICE FOR GENERATING A VOLTAGE PULSE

Current leakage reduction in 3d nand memory

본 개시 내용의 실시예들은 누설 전류를 감소시키기 위해 바이어스 전압이 제공될 수 있는 메모리 어레이를 포함하는 장치를 제공하는 기법들 및 구성들에 관한 것이다. 하나의 실시예에서, 이 장치는 적어도 제1 및 제2 블록들을 가지는 3차원(3D) 메모리 어레이; 및 3D 메모리 어레이에 액세스하기 위해 3D 메모리 어레이와 결합된 회로부를 포함할 수 있다. 회로부는 제1 블록을 선택 해제하고 제2 블록을 선택하며, 3D 메모리 어레이에서의 누설 전류를 감소시키기 위해, 제1 바이어스 전압을 선택 해제된 제1 블록에 그리고 제2 바이어스 전압을 선택된 제2 블록에 공급하는 회로를 포함할 수 있다. 제1 바이어스 전압은 제2 바이어스 전압과 상이할 수 있다. 다른 실시예들이 기술되고 그리고/또는 청구될 수 있다.

EMERGENCY POWER SUPPLY CIRCUIT AND METHOD FOR POLARIZING THE BINARY LINES OF A STATIC SEMICONDUCTOR MEMORY

L'INVENTION CONCERNE UN CIRCUIT ET UN PROCEDE D'ALIMENTATION DE SECOURS POUR POLARISER LES LIGNES BINAIRES D'UNE MEMOIRE STATIQUE A SEMI-CONDUCTEUR. UN DISPOSITIF 44 DETECTE LA DISPARITION DE L'ALIMENTATION PRINCIPALE, UN DISPOSITIF 42 CONNECTE UNE SOURCE D'ALIMENTATION DE SECOURS 48 AUX CELLULES DE MEMOIRE 50 PAR L'UNE SELECTIONNEE WE DES BORNES DE COMMANDE A LA DETECTION DE LA DISPARITION DE L'ALIMENTATION ET UN DISPOSITIF 54 APPLIQUE UNE TENSION PREDETERMINEE PRODUITE PAR LA SOURCE D'ALIMENTATION DE SECOURS A CHACUNE DES LIGNES BINAIRES A LA DETECTION DE LA DISPARITION DE L'ALIMENTATION PRINCIPALE. L'INVENTION S'APPLIQUE NOTAMMENT A DES MEMOIRES DE CALCULATEURS. THE INVENTION RELATES TO A BACKUP POWER SUPPLY CIRCUIT AND PROCESS FOR POLARIZING THE BINARY LINES OF A STATIC SEMICONDUCTOR MEMORY. A DEVICE 44 DETECTS THE DISAPPEARANCE OF THE MAIN POWER SUPPLY, A DEVICE 42 CONNECTS AN EMERGENCY POWER SOURCE 48 TO THE MEMORY CELLS 50 BY A SELECTION OF THE CONTROL TERMINALS ON DETECTION OF THE DISAPPEARANCE OF THE POWER SUPPLY AND A DEVICE 54 APPLIES A PREDETERMINED VOLTAGE PRODUCED BY THE EMERGENCY POWER SOURCE TO EACH OF THE BINARY LINES ON DETECTION OF THE DISAPPEARANCE OF THE MAIN POWER SUPPLY. THE INVENTION APPLIES IN PARTICULAR TO MEMORIES OF COMPUTERS.

SUBSTRATE POLARIZATION VOLTAGE GENERATION CIRCUIT

L'INVENTION CONCERNE LA TECHNOLOGIE DES SEMICONDUCTEURS. UN CIRCUIT DE GENERATION DE TENSION DE POLARISATION DE SUBSTRAT POUR UN DISPOSITIF DE MEMOIRE A SEMICONDUCTEURS COMPREND UN OSCILLATEUR 10 QUI GENERE UN SIGNAL CARRE DE FREQUENCE SPECIFIEE, UN AMPLIFICATEUR-SEPARATEUR 20 ET UN CIRCUIT DE POMPE DE CHARGE 30 QUI PRODUISENT UNE TENSION DE POLARISATION DE SUBSTRAT, ET UN CIRCUIT DE LIMITATION 40 QUI EST BRANCHE ENTRE LA SORTIE DU CIRCUIT DE POMPE DE CHARGE ET LA MASSE, DE FACON A LIMITER A UNE PLAGE SPECIFIEE LA TENSION DE POLARISATION DE SUBSTRAT QUE FOURNIT LE CIRCUIT, MALGRE LES VARIATIONS DE LA TENSION D'ALIMENTATION. APPLICATIONS AUX MEMOIRES MOS. THE INVENTION RELATES TO SEMICONDUCTOR TECHNOLOGY. A SUBSTRATE POLARIZATION VOLTAGE GENERATION CIRCUIT FOR A SEMICONDUCTOR MEMORY DEVICE INCLUDES AN OSCILLATOR 10 WHICH GENERATES A SPECIFIED FREQUENCY SQUARE SIGNAL, AN AMPLIFIER-SEPARATOR 20, AND A CHARGING PUMP CIRCUIT 30 WHICH GENERATE POLARIZATION SUBSTRATE, AND A LIMITATION CIRCUIT 40 WHICH IS CONNECTED BETWEEN THE CHARGE PUMP CIRCUIT OUTPUT AND GROUND, SO AS TO LIMIT TO A SPECIFIED RANGE THE SUBSTRATE POLARIZATION VOLTAGE PROVIDED BY THE CIRCUIT, DESPITE VARIATIONS IN VOLTAGE D 'FOOD. APPLICATIONS TO MOS MEMORIES.

Back bias voltage generation circuit

Voltage generator of semiconductor memory device

본 발명은 반도체 메모리 소자의 전압발생장치에 관한 것으로, 셀 플레이트 전압/비트라인 프리챠지 드라이버에 코어전압(CVdd)보다 높은 안정된 내부전원전압(Vint22)을 공급하여 셀 플레이트 전압/비트라인 프리챠지 전압의 구동능력을 향상시키는 것을 목적으로 한다. 이러한 목적을 달성하기 위해, 본 발명에 따른 반도체 메모리 소자의 전압발생장치는, 반도체 메모리 소자의 모든 내부전원전압의 기준전압을 발생시키는 기준전압 발생부; 상기 기준전압 발생수단에서 발생된 기준전압을 이용하여 코어 기준전압을 발생시키는 코어 기준전압 발생부; 상기 코어 기준전압 발생수단에서 발생된 코어 기준전압을 이용해서 반도체 메모리 소자의 셀에 사용되는 코어 전압을 발생시키는 코어 전압 발생부; 상기 코어 기준전압 발생수단에서 발생된 코어 기준전압을 이용해서 반도체 메모리 소자의 셀에 사용되는 코어 전압보다 높은 내부전원전압을 발생시키는 내부전원전압 발생부; 및 상기 코어 전압 발생수단에서 발생된 코어전압과 상기 내부전원전압 발생수단에서 발생된 내부전원전압을 이용해서 셀 플레이트 전압 또는 비트라인 프리챠지 전압을 발생시키는 셀 플레이트전압/비트라인 프리차지 전압 발생부를 구비한 것을 특징으로 한다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage generator of a semiconductor memory device. The present invention relates to a cell plate voltage / bitline precharge voltage by supplying a stable internal power supply voltage Vint22 higher than the core voltage CVdd to a cell plate voltage / bitline precharge driver. The purpose is to improve the driving ability of the. In order to achieve this object, the voltage generator of the semiconductor memory device according to the present invention, the reference voltage generator for generating a reference voltage of all the internal power supply voltage of the semiconductor memory device; A core reference voltage generator configured to generate a core reference voltage by using the reference voltage generated by the reference voltage generator; A core voltage generator configured to generate a core voltage used in a cell of a semiconductor memory device by using the core reference voltage generated by the core reference voltage generator; An internal power supply voltage generator configured to generate an internal power supply voltage higher than a core voltage used in a cell of a semiconductor memory device by using the core reference voltage generated by the core reference voltage generator; And a cell plate voltage / bit line precharge voltage generator configured to ...