부스트 회로를 구비하는 반도체 메모리 장치
It is shown a semiconductor memory device of the present invention number 1 embodiment the first deoxygenator also Figure 1 shows a block. Also Figure 2 shows a circuit boost circuit. Figure 3 shows a circuit boost voltage generating circuit also. Timing operation of boost voltage generating circuit also Figure 4 shows a timing chart. It is shown a semiconductor memory device of the present invention number 2 embodiment the first deoxygenator also Figure 5 shows a block. It is shown a semiconductor memory device of the present invention number 3 embodiment the first deoxygenator also Figure 6 shows a block. Figure 7 shows a the conventional system block it is shown a semiconductor memory device. * Description of the sign for major part * of the drawings 1, 2:3, 4 ring oscillator: boost voltage generating circuit 5: memory cell array 6: output circuit The present invention refers to semiconductor memory including boost circuit relates to device, in particular memory cell array and voltage boost for both output circuit using relates to semiconductor memory device. Recent, in semiconductor memory device is used for applying external power supply then. However, such low voltage rather than driven by for higher voltages part where it is desirable semiconductor memory circuits are contained in internal circuit of a device constitution :. Such circuit for example output circuit and notifies a user word line drive circuits. Therefore, the voltage output from external power word line driving circuit output circuit and supplied to the booth by boost circuit rather than these voltage [...]. supplied to. This situation a reference to 7 is may be described. Semiconductor memory device 7 also shown in a memory cell array (26) circuit which controls and outputs (27) has a. Memory cell array (26) to, many memory cells are is included for access these memory cells a number of word line is are provided. As is publicly known, selected to be connected to a word line voltage to be applied as greater than the threshold voltage of the transistor. voltage higher than a power supply voltage. Furthermore, to increase the speed of output, output voltage in addition be a high voltage, above the power supply voltage (27) are used in. As mentioned above, where the lighting is, memory cell array (26) circuit which controls and outputs (27) a power supply voltage with a higher voltage than the patterned and thereby a requiring, boost voltage generating circuit (25) joining a boosting external voltage by a voltage (VBOOT) comprising a memory cell array (26) circuit which controls and outputs (27) is applied to a multi-. However, such semiconductor memory of the existing method the following device has these problems. In particular, boost voltage generating circuit (25) the voltage produced by the (VBOOT) generally memory cell array (26) circuit which controls and outputs (27) is used for. Therefore, voltage (VBOOT) is output circuit (27) when varies due to the operation of, which are running at a memory cell array varies the driving voltage of word lines. In particular, the semiconductor memory device is a synchronous DRAM when higher than operating frequencies are, output circuit (27) of an installation space, having a, a change in voltage (VBOOT) is more important. Word lines are voltage (VBOOT) is changed outputs wherein an array of memory cells (26) when driven to in, recording operation is output/read poor caused sensing rate is results is a problem of the slow. , By using a time hopping code, voltage (VBOOT) in addition the memory cell array (26) is varies due to the operation of. Therefore, voltage (VBOOT) a memory cell array (26) when varies due to the operation of, output circuit (27) by service performance of is, output circuit to be less of the engine load is less than the output timing output circuit [...] results is a problem of the variations of the is. Synchronization DRAM with a, and data outputting word line driving simultaneously the, . it was a very important the above-mentioned problem. On the other hand, increase in output current and high speed data output and, if desired, output circuit (27) for driving the voltage (VBOOT) is must be free. However, voltage (VBOOT) is in addition memory cell array (26) is used for, voltage (VBOOT) can't may have an arbitrary and is set. As other words, the spot, voltage (VBOOT) comprising a memory cell array (26) circuit which controls and outputs (27) by satisfying growing the conditions required to within such a range that are interconnected by the interface part since, is restricts the range. As mentioned above, where the lighting is, semiconductor memory device produced in boost voltage (VBOOT) comprising a memory cell array (26) circuit which controls and outputs (27) when is to be shared by, output circuit (27) and a memory cell array (26) is noise interference between causes boost voltage (VBOOT) for setting restricts range is formed, having free (VBOOT) voltage is make it difficult to. Plates are parallel each other, and the present invention refers to and in view of the problems being comprised. The present purpose of the invention the boosted voltage (VBOOT) of noise interference between circuit adopting are not problem semiconductor memory with separate boost circuit electrode 104 is provided under the device. It is another object of the present invention using boost voltage an output circuit and a memory cell array between noise interference problems are not boost circuit semiconductor memory with separate electrode 104 is provided under the device. Another problem boost voltage (VBOOT) of the present invention that the program guide settings that were other circuits which is not restricted by semiconductor memory with separate boost circuit electrode 104 is provided under the device. Of the present invention semiconductor memory with separate boost circuit using boost voltage circuit a plurality of circuit, and wherein the boost circuit, each said circuit a corresponding circuit is provided for. The rotatable lever is rotated when the semiconductor memory device according to by configuring the, using boost voltage noise between circuit said results is not a problem. Furthermore, plurality of boost circuit generated by the one or more boost voltages are different. can be obtained. Furthermore, at least one of the boost circuit CLK signal and a synchronous circuit is driven by a signal. Furthermore, each of the boost circuit memory cell wordline interface method of forming one pixel boost power (VBOOT) for supplying boost voltage generating circuit and output circuit (VBOOTQ) in input voltage gate output transistor for supplying has a boost voltage generating circuit number 2. Now based on a text content of the from reference to drawing will the present invention is detailed. Figure 1 shows a semiconductor memory device of the present invention number 1 embodiment also the first deoxygenator. a circuit it is shown a. Number 1 embodiment the first deoxygenator semiconductor memory device a memory cell array (5) circuit which controls and outputs (6) is having DRAM. Memory cell array (5) has a plurality of memory cells, said cells each line of a corresponding word line is selected by. Corresponding selected memory cells of the bit line is connected to bit line potential storage selected memory cell changes in accordance with the dislocations. The amplitude of the potential change is amplified by a sense amplifier D and internal output data ., Would appear as a. Internal output data D and The output circuit (6) is applied to a multi-. Wherein, memory cell array (5) included word line are selected when state, distance of transistor be a high voltage, above the power supply voltage is applied to the word line. As is publicly known, such application of a voltage of the transistor distance voltage higher than supply voltage applied to a word line joining a bit line charge migration law and. easy. Output circuit (6) the growth of hematopoietic stem cell, a circuit configurations is shown in a 2. Output circuit (6) to make the memory cell array (5) supplied from an internal output data D and To output data outputs DQ is supply of pin. N channel MOS transistor (N10) internal output data therein and is supplied to the gate of the output data N the channel is supplied to the gate of the MOS transistor (N11). N the D internal output data channel directly to the gate of MOS transistor (N10) that are not as level converting circuit (7) via channel N (N10) is supplied to the gate of the MOS transistor. Wherein, level converting circuit (7) within the interior output data D converting voltage of data internal output circuit when D is level (Vcc level), the current plural weights internal output data D N channel MOS transistor (N10) is supplied to the gate of the. Internal output data when D is low level (GND level), internal output data D N the (VBOOT) is boost level supplied to the gate of the transistor MOS channel. As mentioned above, where the lighting is, any memory cell array (5) circuit which controls and outputs (6) a power supply voltage Vcc with a higher voltage than the requiring a. Also with a 1, semiconductor memory device in the first deoxygenator number 1 embodiment, a power boost circuit requiring be a high voltage, above the Vcc voltage an output circuit (6) and a memory cell array (5) is provided in each of. Boost circuit each of the ring oscillator and boost voltage generating circuit constitution :. For example, memory cell array (5) corresponding to ring oscillator that boost circuit (1) and boost voltage generating circuit (3) connected to the first and second signal output circuit (6) corresponding to ring oscillator that boost circuit (2) and boost voltage generating circuit (4). is composed. Ring oscillator (1 and 2) (Φb and Φa), pulse signals each for outputting, the pulse signals (Vcc) power each GND level and a level between level changed on a periodic to. Control signal (READU) is ring oscillator (2) scratches on that supplied to defect/deficiency. Boost voltage generating circuit (3) the growth of hematopoietic stem cell, a circuit configurations is shown in a 3. Also is as shown to 3, number 1 N transistor (N1) and for forming the source and drain one of boost power (VBOOT) connected to said transistor gate and, while the remaining one is connected to capacitor (C1). Number 2 N transistor (N2) and for forming the source and drain one of boost power (VBOOT) connected to said transistor gate and, while the remaining one is connected to number 2 capacitor (C2). Number 3 N transistor (N3) and for forming the source and drain one (VCC) connected to the power source voltage, while the remaining one is connected to number 1 capacitor (c1). Number 2 number 3 N transistor (N3) of gate is connected to capacitor (C2). Number 4 N transistor (N4) and for forming the source and in drain the power one (VCC) connected to capacitor (C2), while the remaining one is connected to number 2. Number 4 N transistor (N4) of gate is connected to number 1 capacitor (C1). Number 1 capacitor (C1) a terminal of an inverter (INV1) of output terminal number 2 is connected to a terminal of capacitor (C2) is connected to output terminal of an inverter (INV2). Number 3 capacitor (C3) connected to the boost power (VB00T) a terminal and ground potentials, the point (GND) has terminal other devices coupled to. Boost generating circuit (3) of action with the content is to also by referring to number 4 will described. Boost voltage generating circuit (3) the input signal to ring oscillator that (1) is the output of the current position and size in the (Φa). Number 1 in each of the cycles with a predetermined (Φ1) control signal GND level and VCC interlevel to update and manufacture a level is changed to. Number 2 control signal (Φ2) VCC is the number 1 (Φ1) control signal period and the only level GND level (Φ2) control signal number 1 the number 1 control signal (Φ1) and the only level GND is VCC period. level. Number 1 control signal (Φ1) the power source voltage level (Φ2) is number 2 control signal GND level (0V) when, number 2 and number 4 N transistor (N4) has the turn node of a terminal other capacitor (C2) a power supply voltage (T2) is filled (VCC). Furthermore, number 1 capacitor (C1) (T2) node of a terminal other at that person or (VBOOT +Vt) level of (Vt: threshold voltage of transistor) when the same as the, current through node number 1 N transistor (N1) (VBOOT) output terminal boost voltage in (T1) of the, output terminal boost voltage (VBOOT) to raise a level higher than a level of the power voltage (VCC) so. Furthermore, ground voltage level (Φ1) control signal number 1 and can be modified and number 2 control signal (Φ2) when to change from an is a supply voltage level, node (T2) in approximate and a 2VCC level is on a level with the number 3 N transistor (N3) has the turn is glidably node is filled VCC a power supply voltage (T1). Furthermore, charge through number 2 N transistor (N2) is supplied to output terminal boost voltage (VBOOT). Then is subjected to repeated of operation, such as a power voltage (VBOOT) boost voltage rises be a high voltage, above the (VCC).. Number 3 capacitor (C3) the boost voltage (VBOOT) which function to them is capacitor not. Boost voltage generating circuit (4) is in addition boost voltage generating circuit (3) and a similarly configured even is, control signal (READU) a ring oscillator (2) in addition to boost voltage generating circuit (4) that supplied to defect/deficiency disposed, minimizing. As mentioned above, where the lighting is, the present embodiment the first deoxygenator semiconductor memory device two ring oscillators (1 and 2) and two boost voltage generating circuits (3 and 4) is provided with a boost voltage generating circuit (3) comprising a memory cell array (VBOOT) output of (5) is applied to a multi-. Boost voltage generating circuit (4) is applied to a multi-output of an output circuit (VBOOTG). Output signals (Φb and Φa) the GND level and VCC interlevel at their levels of a predetermined a pulse signals change the cycle. Control signal (READU) a read data of the time, i.e. time for outputting data control signal signals activated only (READU) a ring oscillator (2) and boost voltage generating circuit (4) is input to. Furthermore, as mentioned above, where the lighting during structuring for producing the present embodiment the first deoxygenator will are described operation boost circuit. Boost voltage generating circuit (3) a ring oscillator (1) and an output pulse and provided periodically from (Φa) and is rotated by an internal electrical boost voltage generating circuit (3) the correlate the rectangular areas to a preset boost voltage (VBOOT) generated, wherein. Boost voltage (VBOOT), typically at memory cell array (5) is used as difference of. On the other hand, boost voltage generating circuit (4) a ring oscillator (2) and an output pulse and provided periodically from (Φb) and is rotated by an internal electrical boost voltage generating circuit (4) the correlate the rectangular areas to a preset boost voltage (VBOOTQ) generated, wherein. Boost voltage (VBOOTQ) is used as the gate input voltage. Control signal (READU) a read data of the time, i.e. for outputting data is signal activated only time. Boost voltage (VBOOTQ) reads out a the data requiring only since the time, the signal is control signal (READU) due to the selection part is a switching button set, ring oscillator and boost voltage generating circuit (4) be strong level of the boost voltage (VBOOTQ) operating mode. taken. Therefore, power consumption can be reduces a current. As mentioned above, where the lighting is, boost voltage generating circuit (3) (VBOOT) boost voltage generated by each other (VBOOTQ) and separated from one another. To this end, boost voltage (VBOOT) level of memory cell wordline interface method of varied by forming one pixel even when opposed, boost voltage (VBOOT), a change in boost voltage do not affect the (VBOOTQ) since the problems of access delay is not. Furthermore, , by using a time hopping code, device cell base, or a 180° rotating memo data is read from output line and outputs a boost voltage (VBOOT) of a high frequency the memory cell device is changed in operating time even when opposed, boost voltage (VBOOTQ) separates from the boost voltage (VBOOT), never dispersed arranging the sensing speed does not caused. Altered output or requiring high speed [...] when there is the need, output circuit of current voltage can be acquired by back boost voltage (VBOOT) by modified level of, output current may be varied very efficient high speed can be can be easily made [...]. Boost voltages (BVOOTQ and VBOOT) is when connected with as semiconductor memory of the existing method, one voltage order to satisfy the characteristics when determining changing the up-link, other characteristics of one its other properties affected by changing a, part for freely setting the voltage level even numbers of character codes from outside. However, the present embodiment as the first deoxygenator semiconductor memory device of the present invention, boost voltages (VBOOTQ and VBOOT) if the enclosure is separated each other, boost voltage, the level of the (VBOOTQ) without impacting the memory cell array is provided to improve a characteristic freely to be set up. As mentioned above, where the lighting is, processes a booster voltages are completely separated from each other (VBOOTQ and VBOOT), memory cell array and interference noise between output circuit panel and a property the level of boost voltage order to satisfy the can be set independently. Furthermore, of the present invention number 2 embodiment 5 also substracte is may be described by referring to. The internal CLK generating circuit (11) upon receipt of the control signal (READU) CLK signal in the Image data signal and the high level and low level source circuit as a power source voltage (VCC) and a ground voltage by the (GND) for use in an the CLK signal (ICLK) is a circuit for generating. Ring oscillators (8 and 12) of output signals (Φb and Φa) the predetermined level between level GND level and VCC is altered in signals (Φb and Φa) the ring oscillator (2) and boost voltage generating circuit (4) is input to. The data reads out a control signal (READU) time, i.e. for outputting data inverter signals activated only time (INV4) inverts the (READU) signal controlled by an inverted operated, e.g. at lower ring oscillator signal (12) is input to. Boost voltage generating circuit (9) comprising a memory cell array (VBOOT) output of (10) is subjected to a catalytic oxidation of boost voltage generating circuit (13) (VBOOTG) output of an output circuit (14) is applied to a multi-. Synchronous DRAM in (synchronization DRAM), supplied from the external is-data signals, and outputs signal and a synchronous CLK. Ring oscillator output pulses (Φb) is output circuit supplied to boost voltage used to generate a boost voltage generating circuit (13) when ratio of a driving signal to be used for, is slowly cooled and full-fat cycle comprises a boost thereof is, output and boost cycle comprises a generally it is different is. In this case, boost voltage (VBOOT) of the case of relatively large changes of the level of the, each output terminal [...] further includes a boost voltage can be change is effected. To this end, in data output time, internal CLK generating circuit (11) on the outside by an inner received signal is generated signal CLK CLK signal (ICLK) the boost voltage generating circuit (13) for driving a by used for signal, upon synchronized with data output cycle boost efficient can be is. As mentioned above, where the lighting is, internal CLK generating circuit (11) according to the use of, efficient even boost is performed, ring oscillator (12) is in addition will required. External CLK signal is self-refreshing (self-refreshing) by a constant level when of input signals are, internal CLK generating circuit (11) internal generated by CLK signal (ICLK) in addition the projection beam according to a desired pattern is glidably, boost voltage generating circuit (13) is cannot be a drive. Therefore, boost voltage is dropped, the level of the (VBOOTQ). In this situation, self-refresh oscillation completed and the data reading is output is then immediately the beginning of self-refresh element, the (VBOOTQ) boost voltage for the Q signal without using filters level at the predetermined time, the register is upgrade in base station is especially results is. To this end, time other than output status, boost voltage to to maintain the level of an (VBOOTQ), ring oscillator (12) is in addition require. As mentioned above, where the lighting is, external CLK signal (ICLK) signal CLK internal made from the output circuit used for boost voltage (VBOOTQ) for generating boost voltage generating circuit (13) by ratio of a driving signal used for, upon synchronized with data output cycle boost efficient internal a CLK generating circuit (11) in addition to ring oscillator (12) is in addition require. Figure 6 shows a. is a block of the present invention number 3 embodiment also shown thereby, the cold air flows. Is embodiment relate boost voltage generating circuits (18, 19 and 20) one of boost voltage generating circuit, for example boost voltage generating circuit (20) for number 1 stage circuit (23) of the capacitor is is used. Ring oscillators (15, 16 and 17) of outputs (Φa, Φb, Φc) the boost voltage generating circuits (18, 19, and 20) is input each. Boost voltage generating circuit (18) (VBOOT) boost voltage generated by a memory cell array (21) is used as difference of. Boost voltage generating circuit (19) (VBOOTQ) boost voltage generated by an output circuit an input voltage and is used by for. Boost voltage generating circuit (20) the boost voltage generated by number 1 stage circuit (23) to employ one having an supply voltage of. In semiconductor memory device, in particular, synchronization in DRAM, semiconductor memory device upon request of an action to the low-voltage internal source voltage in (VCC) voltages lower than the power supply voltage when be, characteristics, increases to a some internal circuits are may be present. Built-in elements such and for boost voltage generating circuits (18, 19 and 20) boost generated by operated, e.g. at lower voltages, these internal circuit a property satisfying growing is enabled. Furthermore, a plurality of generated within semiconductor memory device into different boost voltage is able to set the voltage but, boost voltages (VBOOTS and VBOOT) of Figure 6 the dotted lines such as illustrated at are developed when level by the same voltage, in addition is connected to each other.. This boost voltage generating circuits (19 and 20) are not driven boost voltage (VBOOTS and VBOOTQ) levels of a to stabilize the when contribute to, as well as network caused by a a it is conceivable that the problem of noise so as to avoid an influence of and efficient when. As mentioned above, where the lighting is, according to the present invention, semiconductor memory device produced in boost voltage a memory using inverted write-back between output circuit cell array and a low valve lift condition to prevent noise interference. Furthermore, memory cell array and used for output circuit part for freely setting the desired boost voltages can cause characteristics of. Disclosed is a semiconductor memory device, which comprises a plurality of circuits using a voltage obtained by boosting an external power source voltage and power source noises produced by operations of these circuits have no influence on other circuits. The semiconductor memory device including a boost circuit comprises a plurality of circuits using boost voltages, for example, a memory cell array, an output circuit and a plurality of boost circuits, each being provided for the corresponding one of these circuits. With such constitution, a problem of noise interference among the circuits using the boost voltages can be removed. In semiconductor memory device, Memory cell array and, Data output pin and, Said memory cell array and read out from said data and an output circuit supplied to output pin data, By boost power supply voltage and for generating a voltage with boost number 1 number 1 boost circuit and, Said number 2 by boost power supply voltage and for generating a voltage with boost and boost circuit number 2, Said memory cell array part and an auxiliary boosted voltage to the number 1, Said said number 2 output circuit supplying boost voltage semiconductor memory device that includes a means for venting. According to Claim 1, Said number 1 and number 2 boost voltage different semiconductor memory device. According to Claim 1, A boost circuit said number 2 number 1 and number 2 modes, the, said number 2 number 1 during the active mode, and for a boost circuit driving force (driving ability) in said number 1 generates boost voltage said number 2, said number 2 during the active mode, and for a boost circuit said number 2 and compressed air stronger than when the driving force said number 1 number 2 driving force device dry etching method such as a boost voltage said number 2. According to Claim 1, A read boost circuit said number 2 in response to the control signal said number 2 mode semiconductor memory device. In semiconductor memory device, Number 1 number 1 supplied from power line by boost power supply voltage and for generating a voltage with boost number 1 number 1 boost circuit and, Said number 1 said number 1 supplied from a power line by boost power supply voltage and for generating a voltage with boost number 2 and boost circuit number 2, Said number 1 boost voltage end receives the memory cell array and, Output read from said memory cell array for receiving data lines data number 1 number 1, Said memory cell array is reverted to data output read from said number 1 number 2 a data line number 2 for receiving data, Said number 1 data lines has an input node and an output node, said number 1 supplied to input node said said number 2 read data and level converting circuit converting a boost voltage, Number 1 and data output power line is connected to between terminals, said level conversion circuit to an output node said having control electrodes number 1 transistor and, Number 2 the power line and the data output terminal the data between the number 2 semiconductor memory device.