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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 11853. Отображено 100.
12-01-2012 дата публикации

System-in-a-package based flash memory card

Номер: US20120007226A1
Автор: Hem Takiar, Michael W. Patterson, Robert C. Miller, Shrikar Bhagath, Warren Middlekauff
Принадлежит: SanDisk Technologies LLC

A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.

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Номер записи: 1
02-02-2012 дата публикации

Semiconductor memory apparatus having sense amplifier

Номер: US20120026773A1
Автор: Myoung Jin LEE
Принадлежит: Hynix Semiconductor Inc

Disclosed is a semiconductor memory apparatus comprising an upper mat and a lower mat with a sense amplifier array region in between, where the sense amplifier array region includes a plurality of sense amplifiers. There is also a plurality of bit lines configured to extend toward the sense amplifier array region from the upper mat, and a plurality of complementary bit lines configured to extend toward the sense amplifier array region from the lower mat. Bit lines of the upper mat and complementary bit lines of the lower mat are configured to be alternately disposed at a predetermined interval in the sense amplifier array region, and the sense amplifier is configured to be formed between a bit line and a corresponding complementary bit line.

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Номер записи: 2
08-03-2012 дата публикации

Semiconductor integrated circuit

Номер: US20120057395A1
Автор: Ki Myung Kyung, Myoung Jin LEE
Принадлежит: Hynix Semiconductor Inc

A semiconductor integrated circuit includes a cell block including a plurality of cell mats having a plurality of word lines and a plurality of bit lines perpendicular to the plurality of word lines, a cell plate electrode formed over a whole area of the cell block, and a plate power mesh line including a first plate power mesh line electrically connected to the cell plate electrode while extending in a direction parallel to the word lines, and a second plate power mesh line extending in a direction parallel to the bit lines. The first plate power mesh line includes at least one cutting part.

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Номер записи: 3
15-03-2012 дата публикации

Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same

Номер: US20120063194A1
Автор: Chul-woo Park, Hak-soo Yu, Hong-Sun Hwang, In-Gyu Baek
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

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Номер записи: 4
15-03-2012 дата публикации

Apparatus and method for read preamble disable

Номер: US20120066433A1
Автор: Clifford Alan Zitlaw, Feng Liu, Wendy P. Lee-kadlec
Принадлежит: SPANSION LLC

A memory device is provided. The memory device includes a preamble disable memory and a memory controller. The preamble disable memory is arranged to store preamble disable data. The preamble disable data includes an indication as to whether a read preamble should be enabled or disabled. In response to a read command, if the preamble disable data includes an indication that the read preamble should be enabled, the memory controller provides the read preamble. Alternatively, in response to the read command, if the preamble disable data includes an indication that the read preamble should be disabled, the memory controller disables the read preamble.

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Номер записи: 5
22-03-2012 дата публикации

Massively Parallel Interconnect Fabric for Complex Semiconductor Devices

Номер: US20120068229A1
Автор: Farhang Yazdani, Majid Bemanian
Принадлежит: Individual

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

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Номер записи: 6
22-03-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120069530A1
Автор: Kazushige Kanda, Satoshi Inoue, Yuui Shimizu
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor device includes a stacked chip includes semiconductor chips which are stacked, the semiconductor chips comprises semiconductor substrates and through electrodes formed in the semiconductor substrates, respectively, the through electrodes being electrically connected, and deactivating circuits provided in the semiconductor chips, respectively, and configured to deactivate a failed semiconductor chip.

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Номер записи: 7
19-04-2012 дата публикации

Semiconductor package

Номер: US20120096322A1
Автор: Kwi-Dong Kim, Tae-Hyoung HUH
Принадлежит: Hynix Semiconductor Inc

A semiconductor package includes a memory controller chip, a plurality of first memory chips configured to store normal data, a second memory chip configured to store error information for correcting or detecting error of the normal data, and an interface unit configured to interface the memory controller chip, the plurality of first memory chips, and the second memory chip.

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Номер записи: 8
26-04-2012 дата публикации

Memory module with memory stack and interface with enhanced capabilities

Номер: US20120102292A1
Автор: David T. Wang, Frederick Daniel Weber, Keith R. Schakel, Michael J.S. Smith, Suresh N. Rajan
Принадлежит: Google LLC

A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.

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Номер записи: 9
10-05-2012 дата публикации

Semiconductor device

Номер: US20120114086A1
Автор: Junichi Hayashi
Принадлежит: Elpida Memory Inc

A semiconductor device includes: an interface chip including a read timing control circuit that outputs, in response to a command signal and a clock signal supplied from the outside, a plurality of read control signals that are each in synchronization with the clock signal and have different timings; and core chips including a plurality of internal circuits that are stacked on the interface chip and each perform an operation indicated by the command signal in synchronization with the read control signals. According to the present invention, it is unnecessary to control latency in the core chips and therefore to supply the clock signal to the core chips.

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Номер записи: 10
17-05-2012 дата публикации

Semiconductor memory device

Номер: US20120120706A1
Автор: Takeshi Ohgami
Принадлежит: Elpida Memory Inc

A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.

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Номер записи: 11
24-05-2012 дата публикации

Memory controller and information processing system

Номер: US20120131382A1
Автор: Masanori Higeta
Принадлежит: Fujitsu Ltd

A information processing system comprises a memory module having a plurality of unit memory regions, a memory controller, connected to the memory module via memory interface, configured to control access to the memory module, an error detector, which is in the memory controller, configured to perform an error detection on data read from the memory module, a failure inspection controller configured to switch a mode of the memory controller from a normal mode to a failure inspection mode, read data from an address, where data was written, to be inspected for each of the plurality of unit memory regions, causes the error detector to detect an error in the read data and perform a failure inspection and a determining unit configured to determine a memory failure or a transmission path failure on the basis of the state of the error detected from the unit memory regions.

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Номер записи: 12
31-05-2012 дата публикации

Memory Modules and Devices Supporting Configurable Core Organizations

Номер: US20120134084A1
Автор: Craig E. Hampel, Donald C. Stark, Ely K. Tsern, Frederick A. Ware, Richard E. Perego
Принадлежит: RAMBUS INC

Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.

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Номер записи: 13
31-05-2012 дата публикации

Semiconductor device

Номер: US20120135356A1
Автор: Makoto Sakuma, Takuya Futatsuyama
Принадлежит: Individual

A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area including nonvolatile semiconductor memory cells, linear wirings extending from inside of the cell area to an area outside the cell area, and lower layer wirings in a lower layer than the linear wirings in the boundary area and electrically connected to the linear wirings, and wiring widths of the lower layer wirings being larger than widths of the linear wirings, the peripheral circuit area including a patterns electrically connected to the linear wirings via the lower layer wirings, the boundary area failing to be provided with the linear wirings and a wiring in same layer as the linear wirings.

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Номер записи: 14
14-06-2012 дата публикации

Continuous mesh three dimensional non-volatile storage with vertical select devices

Номер: US20120147644A1
Автор: Roy E. Scheuerlein
Принадлежит: SanDisk 3D LLC

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

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Номер записи: 15
14-06-2012 дата публикации

Three dimensional non-volatile storage with multi block row selection

Номер: US20120147689A1
Автор: Roy E. Scheuerlein, Tianhong Yan
Принадлежит: SanDisk 3D LLC

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

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Номер записи: 16
21-06-2012 дата публикации

Memory Module With Reduced Access Granularity

Номер: US20120159061A1
Автор: Craig E. Hampel, Frederick A. Ware
Принадлежит: RAMBUS INC

A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

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Номер записи: 17
12-07-2012 дата публикации

Method and system for reducing trace length and capacitance in a large memory footprint

Номер: US20120175160A1
Автор: Rachid M. Kadri, Stephen F. Contreras
Принадлежит: Hewlett Packard Development Co LP

A method and system are disclosed to reduce trace length and capacitance in a large memory footprint. When more dual in-line memory module (DIMM) connectors are used per memory channel, the overall bus bandwidth may be affected by trace length and trace capacitance. In order to reduce the overall trace length and trace capacitance, the system and method use a palm tree topology placement, i.e., back-to-back DIMM placement, to place surface mount technology (SMT) DIMM connectors (instead of through-hole connectors) back-to-back in a mirror fashion on each side of a printed circuit board (PCB). The system and method may improve signal propagation time when compared to the commonly used traditional topology placements in which all DIMM connectors are placed on one side of the PCB.

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Номер записи: 18
19-07-2012 дата публикации

Dram device with built-in self-test circuitry

Номер: US20120182776A1
Автор: Ming Li, Scott C. Best
Принадлежит: RAMBUS INC

A dynamic random access memory (DRAM) device includes a first and second integrated circuit (IC) die. The first integrated circuit die has test circuitry to generate redundancy information. The second integrated circuit die is coupled to the first integrated circuit die in a packaged configuration including primary storage cells and redundant storage cells. The second integrated circuit die further includes redundancy circuitry responsive to the redundancy information to substitute one or more of the primary storage cells with one or more redundant storage cells.

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Номер записи: 19
19-07-2012 дата публикации

Semiconductor device including plural chips stacked to each other

Номер: US20120182778A1
Автор: Homare Sato
Принадлежит: Elpida Memory Inc

Such a device is disclosed that includes a first semiconductor chip including a plurality of first terminals, a plurality of second terminals, and a first circuit coupled between the first and second terminals and configured to control combinations of the first terminals to be electrically connected to the second terminals, and a second semiconductor chip including a plurality of third terminals coupled respectively to the second terminals, an internal circuit, and a second circuit coupled between the third terminals and the internal circuit and configured to activate the internal circuit when a combination of signals appearing at the third terminals indicates a chip selection.

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Номер записи: 20
19-07-2012 дата публикации

Memory System with Multi-Level Status Signaling and Method for Operating the Same

Номер: US20120182780A1
Автор: Steven Cheng
Принадлежит: SanDisk Technologies LLC

A memory system includes a status circuit having a common status node electrically connected to a respective status pad of each of a plurality of memory chips. The memory system also includes a plurality of resistors disposed within the status circuit to define a voltage divider network for generating different voltage levels at the common status node. Each of the different voltage levels indicates a particular operational state combination of the plurality of memory chips. Also, each of the plurality of memory chips is either in a first operational state or a second operational state. Additionally, the different voltage levels are distributed within a voltage range extending from a power supply voltage level to a reference ground voltage level.

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Номер записи: 21
02-08-2012 дата публикации

Semiconductor device including plural chips stacked to each other

Номер: US20120195090A1
Автор: Homare Sato, Junichi Hayashi
Принадлежит: Elpida Memory Inc

Such a device is disclosed that includes first and second chips stacked to each other, and a third chip controlling the first and second chips, stacked on the first and second chips, and including first, second and third output circuits. The first output circuit supplies a first command signal to the first chip. The second output circuit supplies the first command signal to the second chip. The third output circuit supplies a second command signal to the first and second chips.

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Номер записи: 22
02-08-2012 дата публикации

Semiconductor device

Номер: US20120195136A1
Автор: Hideyuki Yoko
Принадлежит: Elpida Memory Inc

A semiconductor device according to the present invention includes plural controlled chips CC 0 to CC 7 that hold mutually different layer information, and a control chip IF that supplies in common layer address signals A 13 to A 15 and a command signal ICMD to the controlled chips. Each bit that constitutes the layer address signals A 13 to A 15 is transmitted via at least two through silicon vias that are connected in parallel for each controlled chip out of plural first through silicon vias. Each bit that constitutes the command signal ICMD is transmitted via one corresponding through silicon via that is selected by an output switching circuit and an input switching circuit. With this configuration, the layer address signals A 13 to A 15 reach the controlled chips earlier than the command signal ICMD.

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Номер записи: 23
30-08-2012 дата публикации

Magnetic memory device

Номер: US20120218804A1
Автор: Shota Okayama
Принадлежит: Renesas Electronics Corp

The present invention provides a magnetic memory device capable of providing high-speed access without increasing an array area. Gate word lines are respectively linearly disposed between source impurity regions and drain impurity regions within a memory cell array area. Gate word line protrusions are respectively provided at boundary regions of memory cell forming regions. Contacts relative to the gate word line protrusions are respectively provided at boundary regions of memory cells at adjacent columns. The drain impurity regions are respectively disposed with being shifted from the centers of the memory cell forming regions in such a manner that spaces between the drain impurity regions become large in the regions in which the protrusions are disposed.

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Номер записи: 24
30-08-2012 дата публикации

Embedded processor

Номер: US20120221911A1
Автор: Joe M. Jeddeloh
Принадлежит: Individual

Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

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Номер записи: 25
06-09-2012 дата публикации

Three dimensional memory system with intelligent select circuit

Номер: US20120224410A1
Автор: Tianhong Yan
Принадлежит: SanDisk 3D LLC

A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. Performing memory operation on the non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits that include a storage device, a select circuit connected to the storage device and one or more level shifters providing two or more interfaces to the respective selection circuit.

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Номер записи: 26
06-09-2012 дата публикации

Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit

Номер: US20120226924A1
Автор: David T. Wang, Frederick Daniel Weber, Keith R. Schakel, Michael John Sebastian Smith, Suresh Natarajan Rajan
Принадлежит: Google LLC

A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits.

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Номер записи: 27
13-09-2012 дата публикации

Transmission gate-based spin-transfer torque memory unit

Номер: US20120230093A1
Автор: Hai Li, Hongyue Liu, Yang Li, Yiran Chen, Yong Lu
Принадлежит: SEAGATE TECHNOLOGY LLC

A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.

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Номер записи: 28
13-09-2012 дата публикации

Sense operation in a stacked memory array device

Номер: US20120230116A1
Автор: Akira Goda, Zengtao Liu
Принадлежит: Micron Technology Inc

Methods for sensing and memory devices are disclosed. One such method for sensing includes changing a sense condition of a particular layer responsive to a programming rate of that particular layer (e.g., relative to other layers).

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Номер записи: 29
08-11-2012 дата публикации

Memory module and layout method therefor

Номер: US20120281348A1
Автор: Shiro Harashima, Wataru Tsukada
Принадлежит: Elpida Memory Inc

The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.

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Номер записи: 30
08-11-2012 дата публикации

Raising Programming Currents of Magnetic Tunnel Junctions Using Word Line Overdrive and High-k Metal Gate

Номер: US20120281464A1
Автор: Chun-Jung Lin, Hung-Sen Wang, Shine Chung, Tao-Wen Chung, Yu-Jen Wang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector.

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Номер записи: 31
29-11-2012 дата публикации

Heat management in an above motherboard interposer with peripheral circuits

Номер: US20120300392A1
Автор: Frederick G. Weiss, Morgan Johnson
Принадлежит: Morgan Johnson, Weiss Frederick G

A computing device has a circuit substrate having a socket, a main processor inserted into the socket, an interposer substrate inserted between the socket and the main processor, the circuit substrate, the socket and the interposer substrate being electrically connected, at least one peripheral circuit on the interposer substrate, and a heat sink thermally coupled to the peripheral circuit.

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Номер записи: 32
29-11-2012 дата публикации

Integrated circuit memory device

Номер: US20120300555A1
Автор: Choong-Sun Shin, Joo-Sun Choi
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor memory device includes a plurality of memory regions formed on one chip, each of the memory regions having a plurality of volatile memory cells that are formed with a density or capacity of 2̂K bits, where K is an integer greater than or equal to 0, and a plurality of input/output (I/O) terminals for inputting and outputting data of the volatile memory cells, and at least one peripheral region that controls a write operation for writing data into the memory regions and a read operation for reading data from the memory regions based on a command and an address input from outside. Thus, a total or entire density of the memory regions corresponds to a non-standard (or ‘interim’) density so that the semiconductor memory device may have an interim density.

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Номер записи: 33
03-01-2013 дата публикации

Semiconductor memory device

Номер: US20130003433A1
Автор: Tomoo Hishida, Yoshihisa Iwata
Принадлежит: Toshiba Corp

A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

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Номер записи: 34
17-01-2013 дата публикации

Memory module in a package

Номер: US20130015590A1
Автор: Belgacem Haba, Ilyas Mohammed, Richard DeWitt Crisp, Wael Zohni
Принадлежит: Invensas LLC

A microelectronic package can include a substrate having first and second opposed surfaces, at least two pairs of microelectronic elements, and a plurality of terminals exposed at the second surface. Each pair of microelectronic elements can include an upper microelectronic element and a lower microelectronic element. The pairs of microelectronic elements can be fully spaced apart from one another in a horizontal direction parallel to the first surface of the substrate. Each lower microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. A surface of each of the upper microelectronic elements can at least partially overlie a rear surface of the lower microelectronic element in its pair. The microelectronic package can also include electrical connections extending from at least some of the contacts of each lower microelectronic element to at least some of the terminals.

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Номер записи: 35
31-01-2013 дата публикации

Apparatuses and methods including memory array and data line architecture

Номер: US20130028023A1
Автор: Toru Tanzawa
Принадлежит: Individual

Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between the transistor and the memory cells. Other embodiments including additional apparatus and methods are described.

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Номер записи: 36
28-02-2013 дата публикации

Semiconductor device and semiconductor chip

Номер: US20130049223A1
Автор: Keisuke NOMOTO, Toru Ishikawa
Принадлежит: Elpida Memory Inc

The present invention is applicable to a semiconductor device having a plurality of chips being stacked with a TSV structure in which adjacent ones of the chips are connected to each other via a plurality of through electrodes. Each of the chips includes a plurality of TSV array portions provided so as to correspond to a plurality of channels. The TSV array portions include a TSV array portion that contributes to an input and an output depending upon the number of the chips being stacked, and a pass-through TSV array portion that is not connected to an input/output circuit.

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Номер записи: 37
28-02-2013 дата публикации

Fly-over conductor segments in integrated circuits with successive load devices along a signal path

Номер: US20130051128A1
Автор: Chiting Cheng, Chung-Cheng Chou, Hsiao-Wen Lu, Jonathan Tsung-Yung Chang, Wei-jer Hsieh
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The propagation delay of a signal through multiple load devices coupled sequentially along a conductor is improved by separating a subset of the load devices that is more distant from the signal source, and coupling the more distant subset to the signal through a fly-over conductor that bypasses the subset that is nearer to the signal source. The technique is applicable to subsets of bit cells in a random access memory (SRAM) coupled to a given word line, or to word line decoder gates coupled sequentially to a strobe signal, as well as other circuits wherein load devices selectable as a group can be divided into subsets by proximity to the signal source. In an SRAM layout with multiple levels, different metal deposition layers carry the conductor legs between the load devices versus the fly-over conductor bypassing the nearer subset.

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Номер записи: 38
04-04-2013 дата публикации

MEMORY DEVICE INTERFACE METHODS, APPARATUS, AND SYSTEMS

Номер: US20130083585A1
Автор: Jeddeloh Joe M.
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatus and systems for memory system are provided. In an example, a memory system can include a plurality of memory dice and an interface chip. The memory dice can include a first memory die including a memory array coupled to through wafer interconnects (TWIs) and a second memory die, wherein the first memory die is stacked over the second memory die. In an example, the interface chip can be coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice. In an example, the interface chip can be configured to perform DRAM sequencing. 1. A memory system comprising: a first memory die including a memory array coupled to through wafer interconnects (TWIs);', 'a second memory die, wherein the first memory die is stacked over the second memory die; and, 'a plurality of memory dice includingan interface chip coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice, wherein the interface chip is configured to perform DRAM sequencing.2. The memory system of claim 1 , wherein the second memory die is disposed on the interface chip and the first memory die is disposed on the second memory die.3. The memory system of claim 1 , wherein the TWIs pass through vias within the second memory die to connect with the interface chip.4. The memory system of claim 1 , wherein the second memory die is coupled to the interface chip using connection pins.5. The memory system of claim 1 , including a substrate claim 1 , wherein the interface chip is disposed on the substrate.6. A memory system comprising: a first memory die including a memory array coupled to through wafer interconnects (TWIs);', 'a second memory die, wherein the first memory die is stacked over the second memory die; and, 'a plurality of memory dice includingan interface chip coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of ...

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Номер записи: 39
04-04-2013 дата публикации

Novel semiconductor device and structure

Номер: US20130083589A1
Автор: Brian Cronquist, Deepak Sekar, Paul Lim, Zvi Or-Bach
Принадлежит: Monolithic 3D Inc

A semiconductor device, including: a first semiconductor layer including first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; and a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer, wherein the second mono-crystallized semiconductor layer is less than 100 nm in thickness, and wherein the second transistors include horizontally oriented transistors.

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Номер записи: 40
18-04-2013 дата публикации

CONNECTION OF MULTIPLE SEMICONDUCTOR MEMORY DEVICES WITH CHIP ENABLE FUNCTION

Номер: US20130094271A1
Автор: Schuetz Roland
Принадлежит: MOSAID TECHNOLOGIES INCORPORATED

A system comprising a plurality of memory devices coupled by a common bus to a controller has a single serially coupled enable signal per channel. Each memory device or chip comprises a serial enable input and enable output and a register for storing a device identifier, e.g., chip ID. The memory devices are serially coupled by a serial enable link, for assertion of a single enable signal to all devices. This parallel data and serial enable configuration provides reduced per-channel pin count, relative to conventional systems that require a unique enable signal for each device. In operation, commands on the common bus targeting an individual device are asserted by adding an address field comprising a device identifier to each command string, preferably in an initial identification cycle of the command. Methods are also disclosed for initializing the system, comprising assigning device identifiers and obtaining a device count, prior to normal operation. 1. A system comprising a controller and a plurality of (N) memory devices , N being an integer greater than one , the plurality of memory devices beinginterconnected to the controller on a common bus comprising parallel links, andinterconnected in series by a serial chip enable link from a single enable output of the controller.2. The system of wherein the plurality of memory devices comprises at least first and second memory devices claim 1 , each of the first and second memory devices comprising a serial enable input and a serial enable output claim 1 ,the enable input of the first memory device being coupled to the enable output of the controller, andthe enable output of the first memory device being coupled to a enable input of the second memory device in the series, for providing single enable signal from the controller for enabling or disabling each of the plurality of memory devices.3. The system of whereineach of the plurality of memory devices comprises a serial enable input and a serial enable output, andthe ...

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Номер записи: 41
18-04-2013 дата публикации

3D MEMORY AND DECODING TECHNOLOGIES

Номер: US20130094273A1
Автор: CHIEN WEI-CHIH, LEE MING-HSIU, LUNG HSIANG-LAN
Принадлежит:

A 3D memory device is based on an array of conductive pillars and a plurality of patterned conductor planes including left side and right side conductors adjacent the conductive pillars at left side and right side interface regions. Memory elements in the left side and right side interface regions comprise a programmable transition metal oxide which can be characterized by built-in self-switching behavior, or other programmable resistance material. The conductive pillars can be selected using two-dimensional decoding, and the left side and right side conductors in the plurality of planes can be selected using decoding on a third dimension, combined with left and right side selection. 1. A memory device , comprising:an array of access devices;a plurality of patterned conductor layers, separated from each other and from the array of access devices by insulating layers, the plurality of patterned conductor layers including left side and right side conductors;an array of conductive pillars extending through the plurality of patterned conductor layers, the conductive pillars in the array contacting corresponding access devices in the array of access devices, and defining left side and right side interface regions between the conductive pillars and adjacent left side and right side conductors in corresponding patterned conductor layers in the plurality of patterned conductor layers; andmemory elements in the left side and right side interface regions, each of said memory elements comprising a programmable and erasable memory material.2. The memory device of claim 1 , including:row decoding circuits and column decoding circuits coupled to the array of access devices arranged to select a conductive pillar in the array of conductive pillars; andleft and right plane decoding circuits coupled to the left side and right side conductors in the plurality of patterned conductor layers arranged to turn on current flow in a selected cell in a left side or right side interface region ...

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Номер записи: 42
25-04-2013 дата публикации

Power supply circuit for memory slots

Номер: US20130099568A1
Автор: Ting Ge, Ya-Jun Pan
Принадлежит: Hon Hai Precision Industry Co Ltd, Hongfujin Precision Industry Shenzhen Co Ltd

A power supply circuit for providing a voltage to a memory slot group with one or more memory slots includes a platform controller hub (PCH), a basic input/output system (BIOS), and a control circuit. The PCH detects whether any of the memory slots are occupied, and notifies the BIOS. If there are any memory slots are occupied, the BIOS enables a general purpose input/output (GPIO) terminal of the PCH. The control circuit controls a power supply to provide or not provide power to the memory slot group based on whether the GPIO terminal of the PCH is enabled.

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Номер записи: 43
02-05-2013 дата публикации

Storage device and method for producing the same

Номер: US20130107440A1
Автор: Hung-I Chung, Wei-Hung Lin
Принадлежит: Phison Electronics Corp

A storage device including a circuit board, an electronic device package and a terminal module is provided. The circuit board has a first surface and a second surface opposite to each other, a plurality of via-holes connecting the first surface and the second surface, a plurality of first pads on the first surface, and a plurality of first pads on the second surface. The electronic device package is disposed on the first surface. The terminal module disposed on the first surface has a plurality of first and second contact parts, and each of the first contact parts passes through the corresponding via-hole and is protruded out of the second surface, and each of the second contact parts is electrically connected to the corresponding first pad. An orthogonal projection area of the electronic device package on the first surface is smaller than an area of the first surface.

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Номер записи: 44
16-05-2013 дата публикации

THREE-DIMENSIONAL INTEGRATED CIRCUIT

Номер: US20130121054A1
Автор: Snider Gregory Stuart
Принадлежит:

A three-dimensional integrated circuit comprising a submicroscale integrated-circuit substrate and n nanoscale layers stacked above the submicroscale integrated-circuit substrate, a nanowire-junction memory element in each of which is independently controlled by two submicroscale subcomponents within the submicroscale integrated-circuit substrate, the first submicroscale subcomponent coupled through a first set of switches to each of the n nanowire-junction memory elements and the second submicroscale subcomponent coupled through a second set of switches to each of the n nanowire-junction memory elements, the total number of switches in the first and second sets of switches less than 2n, and n greater than or equal to 2. 1. A three-dimensional integrated circuit comprising:a submicroscale integrated-circuit substrate; andn nanoscale layers stacked above the submicroscale integrated-circuit substrate, a nanowire-junction memory element in each of which is independently controlled by two submicroscale subcomponents within the submicroscale integrated-circuit substrate, the first submicroscale subcomponent coupled through a first set of switches to each of the n nanowire-junction memory elements and the second submicroscale subcomponent coupled through a second set of switches to each of the n nanowire-junction memory elements, the total number of switches in the first and second sets of switches less than 2n, and n greater than or equal to 2.2. The three-dimensional integrated circuit of wherein the n memory elements are memristive nanowire junctions.3. The three-dimensional integrated circuit of wherein the first submicroscale subcomponent is a driver and the second submicroscale subcomponent is a sensor.4. The three-dimensional integrated circuit of wherein claim 3 , to set the data state of a memory element to a first data state claim 3 , logic within the integrated-circuit substrate submicroscale subcomponent:closes a first switch to connect the driver to the ...

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Номер записи: 45
16-05-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130121073A1
Автор: Kimura Daisuke, Kimura Naoki, SUGITA Masato
Принадлежит:

According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate. 1. A semiconductor device comprising:a substrate comprising a multi-layer structure with a wiring pattern, and comprising a substantially rectangular shape in a plan view;a connector to be connectable to a host device;a volatile semiconductor memory element provided on a front surface layer side of the substrate;a first nonvolatile semiconductor memory element provided on the front surface layer side of the substrate;a second nonvolatile semiconductor memory element provided on the front surface layer side of the substrate;a third nonvolatile semiconductor memory element provided on the front surface layer side of the substrate; anda controller provided on the front surface layer side of the substrate to control the volatile semiconductor memory element and the nonvolatile semiconductor memory elements,wherein the wiring pattern includes a signal line formed between the connector and the controller to connect the connector to the controller, andwherein the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element are aligned along the longitudinal direction of the substrate, on the opposite side of the controller to the third nonvolatile semiconductor memory element.2. A semiconductor device comprising:a substrate comprising a multi-layer structure with a wiring pattern, and comprising a substantially rectangular shape in a plan view;a connector provided on a short side of the substrate to be connectable to a ...

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Номер записи: 46
16-05-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130121074A1
Автор: Kimura Daisuke, Kimura Naoki, SUGITA Masato
Принадлежит:

According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate. 1. A semiconductor system comprising:a host device including a CPU; anda semiconductor device; wherein the semiconductor device comprises:a substrate comprising a multi-layer structure with a wiring pattern, and comprising a substantially rectangular shape in a plan view;a connector to be connectable to the host device;a volatile semiconductor memory element provided on a front surface layer side of the substrate;a first nonvolatile semiconductor memory element provided on the front surface layer side of the substrate;a second nonvolatile semiconductor memory element provided on the front surface layer side of the substrate;a third nonvolatile semiconductor memory element provided on the front surface layer side of the substrate; anda controller provided on the front surface layer side of the substrate to control the volatile semiconductor memory element and the nonvolatile semiconductor memory elements,wherein the wiring pattern includes a signal line formed between the connector and the controller to connect the connector to the controller, andwherein the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element are aligned along the longitudinal direction of the substrate, on the opposite side of the controller to the third nonvolatile semiconductor memory element,wherein the CPU writes information on the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element ...

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Номер записи: 47
23-05-2013 дата публикации

DATA PROCESSING DEVICE

Номер: US20130128647A1
Автор: BETSUI Takafumi, FUKUSHIMA Yoshiharu, MATSUI Shigezumi, SUGITA Norihiko, SUWA Motoo, TAOKA Naoto
Принадлежит: RENESAS ELECTRONICS CORPORATION

A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board. 1. A semiconductor chip comprising:a semiconductor board having a surface comprised of a quadrangle in a plan view, the surface having a first side, a second side facing the first side, a third side crossing the first and second sides, and a fourth side facing the third side and crossing the first and second sides;a first memory interface circuit formed on the surface of the semiconductor board, the first memory interface circuit being arranged along the first side of the surface of the semiconductor board in the plan view, the first memory interface circuit being arranged closer to the first side of the surface of the semiconductor board than the second side of the surface of the semiconductor board in the plan view, the first memory interface circuit having a first data unit; anda second memory interface circuit formed on the surface of the semiconductor board, the second memory interface circuit being arranged along the third side of the surface of the semiconductor board in the plan view, the first memory interface circuit being arranged closer to the third side of the surface of the semiconductor board than the fourth side of the surface of the semiconductor board in the plan view, the second memory interface circuit having a second data unit.2. The semiconductor chip ...

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Номер записи: 48
23-05-2013 дата публикации

LAYOUTS FOR MEMORY AND LOGIC CIRCUITS IN A SYSTEM-ON-CHIP

Номер: US20130128648A1
Автор: Anderson Scott B., Greiner Brandon, Holt Joseph, Mader Roy
Принадлежит: MARVELL WORLD TRADE LTD.

An integrated circuit including a plurality of memory circuits and a plurality of logic circuits. The plurality of memory circuits is arranged on a die along a plurality of rows and a plurality of columns. Each memory circuit includes a plurality of memory cells. The plurality of logic circuits is arranged on the die between the plurality of memory circuits along the plurality of rows and the plurality of columns. The plurality of logic circuits is configured to communicate with one or more of the memory circuits. 1. An integrated circuit comprising:a plurality of memory circuits arranged on a die along a plurality of rows and a plurality of columns, wherein each memory circuit includes a plurality of memory cells; anda plurality of logic circuits arranged on the die between the plurality of memory circuits along the plurality of rows and the plurality of columns,wherein the plurality of logic circuits are configured to communicate with one or more of the memory circuits.2. The integrated circuit of claim 1 , wherein the plurality of rows and the plurality of columns are arranged in an area away from a perimeter of the die.3. The integrated circuit of claim 1 , wherein the memory cells include latch-based random access memory cells.4. The integrated circuit of claim 1 , wherein the logic circuits include at least one of combinational and sequential logic circuits.5. The integrated circuit of claim 1 , wherein the memory circuits have a predetermined memory capacity.6. The integrated circuit of claim 1 , wherein at least one of the plurality of memory circuits has a different memory capacity than others of the plurality of memory circuits.7. The integrated circuit of claim 1 , wherein at least one of the logic circuits is configured to:process signals during a read or a write operation of a storage device, wherein the storage device includes a hard disk drive, an optical disc drive, or a solid-state disk; andstore data generated by the processing in one or more of ...

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Номер записи: 49
23-05-2013 дата публикации

Method and apparatus for refresh management of memory modules

Номер: US20130132661A1
Автор: David T. Wang, Keith R. Schakel, Michael John Sebastian Smith, Suresh Natarajan Rajan
Принадлежит: Google LLC, MetaRAM Inc

One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices

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Номер записи: 50
30-05-2013 дата публикации

MEMORY MODULE INCLUDING PLURAL MEMORY DEVICES AND DATA REGISTER BUFFER

Номер: US20130135916A1
Автор: HIRAISHI Atsushi, OSANAI Fumiyuki, SUGANO Toshio
Принадлежит: ELPIDA MEMORY, INC.

Disclosed herein is a memory module that includes a module substrate, data connectors, memory devices, and data register buffers. A first main surface of the module substrate has first and second memory mounting areas. One of the first and second main surfaces of the module substrate has a register mounting area located between the first and second memory mounting areas in a planner view. The memory devices include a plurality of first memory devices that are mounted on the first memory mounting area and a plurality of second memory devices that are mounted on the second memory mounting area. The data register buffers are mounted on the register mounting area. The data register buffers transfers write data supplied from the data connectors to the memory devices, and transfers read data supplied from the memory devices to the data connectors. 1. A memory module comprising:a module substrate having first and second main surfaces opposite to each other, the first main surface having first and second memory mounting areas, one of the first and second main surfaces having a register mounting area located between the first and second memory mounting areas in a planner view;a plurality of data connectors formed on the module substrate;a plurality of memory devices including a plurality of first memory devices that are mounted on the first memory mounting area and a plurality of second memory devices that are mounted on the second memory mounting area; anda plurality of data register buffers mounted on the register mounting area, the data register buffers transferring write data supplied from the data connectors to the memory devices, and transferring read data supplied from the memory devices to the data connectors.2. The memory module as claimed in claim 1 , whereinthe first memory devices are arranged in a first direction in the first memory mounting area,the second memory devices are arranged in the first direction in the second memory mounting area,the data register ...

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Номер записи: 51
30-05-2013 дата публикации

MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE

Номер: US20130135917A1
Автор: CHOI Byoung Jin
Принадлежит: MOSAID TECHNOLOGIES INCORPORATED

A method and apparatus for organizing memory for a computer system including a plurality of memory devices connected to a logic device particularly a memory system having a plurality of stacked memory dice connected to a logic die, with the logic device having capability to analyze and compensate for differing delays to the stacked devices stacking multiple dice divided into partitions serviced by multiple buses connected to a logic die to increase throughput between the devices and logic device allowing large scale integration of memory with self-healing capability. 1. A memory device for use in computer systems comprising: a plurality of semiconductor dies stacked and connected together; and , each of said dies further comprising a plurality of partitions; and , vaults in said dies comprising a grouping of said partitions in a said dies2. A memory device for use in computer systems as in claim 1 , further comprising switch circuits configured to form said vaults.3. A memory device for use in computer systems as in claim 1 , wherein the number of partitions in each vault is as same as the number of stacked memory dies.4. A memory device for use in computer systems as in claim 2 , wherein said switch circuits are located on said dies.5. A memory device for use in computer systems as in claim 1 , further comprising a logic dice connected to each of said dies by at least one wide bus.6. A memory device for use in computer systems as in claim 5 , wherein said logic dice is configured to analyze and compensate for differing delays to said stacked memory dies.7. A memory device for use in computer systems as in claim 5 , further comprising switch circuits configured to form said vaults.8. A memory device for use in computer systems as in claim 5 , wherein each of said dies are further comprising switch circuits connected to said logic dice.9. A method for organizing memory for use in computer systems comprising the steps of; providing a plurality of semiconductor memory ...

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Номер записи: 52
30-05-2013 дата публикации

Semiconductor storage device

Номер: US20130135919A1
Автор: Makoto Hamada
Принадлежит: Individual

According to one embodiment, a semiconductor storage device includes a stripe, a sense amplifier, a global signal line, and a controller. Blocks are in the stripe. The blocks are formed in a first direction. Each of blocks is made a read unit of data and includes a memory cell capable of holding the data provided along a row and a column. The sense amplifier is provided just under each of the blocks, and reads the data. The global signal line is formed so as to penetrate through the stripe in the first direction, and transfers the data read from the block to the sense amplifier. The controller controls a value of a reference current applied to the sense amplifier according to positional relationship between each area in which the sense amplifier is arranged and the block, which is made a read target of the data, out of the blocks.

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Номер записи: 53
30-05-2013 дата публикации

Systems and methods for testing and assembling memory modules

Номер: US20130135951A1
Автор: Eric Sin Kwok CHIU, Lawrence Wai Cheung Ho
Принадлежит: Kingtiger Technology Canada Inc

Embodiments described herein relate to systems and methods for testing and assembling memory modules. In at least one embodiment, the method comprises, for each memory device of a plurality of memory devices, based on testing performed on the memory device, determining whether the memory device has any defective memory locations, and if so, identifying the one or more defective memory locations, and generating data that identifies the one or more defective memory locations on the memory device; and assembling a memory module comprising at least one memory device having one or more defective memory locations; wherein the assembling comprises, for each memory device of the memory module having one or more defective memory locations, storing the data that identifies the one or more defective memory locations on the memory device in a persistent store on the memory module.

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Номер записи: 54
13-06-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20130148399A1
Автор: Murooka Kenichi
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A semiconductor memory device in accordance with an embodiment includes a plurality of first word lines, a plurality of bit lines, a resistance varying material, a plurality of second word lines and an insulating film. The bit lines intersect the first word lines. The resistance varying material is disposed at respective intersections of the first word lines and the bit lines. The second word lines intersect the bit lines. The insulating film is disposed at respective intersections of the second word lines and the bit lines. One of the first word lines and one of the second word lines are disposed so as to sandwich the bit lines. The second word lines, the bit lines, and the insulating film configure a field-effect transistor at respective intersections of the second word lines and the bit lines. The field-effect transistor and the resistance varying material configure one memory cell. 17-. (canceled)8. A semiconductor memory device , comprising:a semiconductor substrate;a plurality of first word lines extending in a stacking direction perpendicular to the semiconductor substrate, the first word lines being arranged having a certain pitch in a first direction parallel to a surface of the semiconductor substrate and being arranged having a certain pitch in a second direction parallel to the surface of the semiconductor substrate and orthogonal to the first direction;a plurality of bit lines extending in the first direction and arranged having a certain pitch in the second direction and the stacking direction, the bit lines being configured to intersect the first word lines such that a first surface of the bit lines faces the first word lines;a resistance varying material disposed at respective intersections of the first word lines and the bit lines;a plurality of second word lines extending in the stacking direction and arranged having a certain pitch in the first direction and the second direction, the second word lines being configured to intersect the bit lines so ...

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Номер записи: 55
13-06-2013 дата публикации

MEMORY SYSTEM HAVING IMPROVED SIGNAL INTEGRITY

Номер: US20130148403A1
Автор: Park Kwang-Soo
Принадлежит: Samsung Electronics Co., Ltd

A memory system having improved signal integrity includes a printed circuit board for use in a memory device, N memory semiconductor packages mounted on the printed circuit board, a first switch mounted on the printed circuit board, a controller mounted on the printed circuit board, N first signal lines connecting the semiconductor packages to the first switch such that the semiconductor packages and the first switch are in an N-to- correspondence, a second signal line connecting the first switch to the controller, and N selection lines connecting the semiconductor packages to the first switch such that the semiconductor packages and the first switch are in an N-to- correspondence. The N selection lines connect the semiconductor packages to the controller and transmit an enable signal. N is a natural number. 1. A semiconductor device , comprising:at least two semiconductor chips;a switch connected to each of the semiconductor chips via at least two first I/O lines, each first I/O line connected to a separate semiconductor chip; anda controller connected to the switch via a single second I/O line and to each of the switch and the at least two semiconductor chips via an enable line,wherein the controller controls the switch to transmit data between only one of the first I/O lines and the second I/O line.2. The semiconductor device according to claim 1 , wherein the at least two semiconductor chips comprise memory semiconductor chips.3. The semiconductor device according to claim 1 , wherein at least one of the semiconductor chips comprises a logic semiconductor chip.4. The semiconductor device according to claim 1 , wherein the switch comprises at least two switches claim 1 , each switch connected to a single semiconductor chip and each semiconductor chip connected to only one switch claim 1 ,the enable line comprises at least two enable lines, andeach semiconductor chip and corresponding switch is connected to a same enable line that is separate from an enable line ...

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Номер записи: 56
20-06-2013 дата публикации

SEMICONDUCTOR STORAGE DEVICE

Номер: US20130155750A1
Автор: MAEJIMA Hiroshi
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A semiconductor storage device includes: a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resistance element connected in series; and a control circuit selectively driving the first and second wirings. The plurality of first wirings that are specified and selectively driven at the same time by one of a plurality of address signals are separately arranged with other first wirings interposed therebetween within the memory cell array when a certain potential difference is applied to a selected memory cell positioned at an intersection between the first and second wirings by the control circuit. 1. A semiconductor storage device comprising:a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a variable resistance element; anda control circuit selectively driving the first and second wirings,in applying, by the control circuit, a certain potential difference to a selected memory cell positioned at an intersection between the first and second wirings,the plurality of first wirings specified and selectively driven at the same time by one of a plurality of address signals being separately arranged with other first wirings interposed therebetween within the memory cell array,the first wirings being arranged such that a first set of the plurality of first wirings specified and selectively driven at the same time by a first address signal are positioned apart from a second set of the plurality of first wirings specified and selectively driven at the same time by the first address signal, with other first wirings interposed between the first and second set in the memory cell array, anda plurality of sets of the first wirings being repeatedly arranged in the memory cell array, each of ...

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Номер записи: 57
20-06-2013 дата публикации

MEMORY DEVICES HAVING BREAK CELLS

Номер: US20130155751A1
Автор: HSU Kuoyuan, TANG Yukit, TAO Derek
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A representative memory device includes a cell array, at least one break cell that subdivides the cell array into bit cell arrays, and one or more power switches that are electrically coupled to the bit cell. In one embodiment, the break cell separates a connectivity of a first voltage and a second voltage between at least two bit cell arrays so that the bit cell arrays can be selectively coupled to either the first voltage or the second voltage using the power switches. The power switches control the connection of each separated bit cell array of the cell array to either the first voltage or second voltage. 1. A semiconductor memory , comprising:a first break cell electrically separating a first subset of bit cells from a second subset of bit cells of a cell array; anda first power switch configured to connect the first subset of bit cells to a first voltage during a first operating mode and to a second voltage that is different from the first voltage during a second operating mode.2. The semiconductor memory of claim 1 , wherein the first operational mode is a data retention mode claim 1 , and the second operational mode is a write mode.3. The semiconductor memory of claim 1 , further comprising a section decoder that is coupled to the first power switch claim 1 , wherein the section decoder instructs the first power switch to connect the first subset of bit cells to either the first voltage or to the second voltage.4. The semiconductor memory of claim 1 , further comprising a second power switch configured to connect the second subset of bit cells to the first voltage during the first operating mode and to the second voltage that is different from the second voltage during the second operating mode claim 1 , wherein the second power switch is configured to operate independently of the first power switch.5. The semiconductor memory of claim 4 , further comprising a section decoder that is coupled to the first and second power switches claim 4 , wherein the section ...

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Номер записи: 58
27-06-2013 дата публикации

SEMICONDUCTOR DEVICE HAVING MULTI-LEVEL WIRING STRUCTURE

Номер: US20130163303A1
Автор: Egawa Hidekazu
Принадлежит: ELPIDA MEMORY, INC.

Disclosed herein is a device that includes a multi-level wiring structure including a first wiring layer and a second wiring layer formed over the first wiring layer; a memory cell array area including a plurality of memory cells, a plurality of sense amplifiers and a plurality of sub amplifiers; a main amplifier area including a plurality of main amplifiers, the memory cell array area and the main amplifier area being arranged in line in a first direction; and a plurality of first I/O lines each connecting an associated one of the sub amplifiers to an associated one of the main amplifiers, each of the first I/O lines including first and second wiring portions that are elongated in the first direction, the first wiring portion being formed as the first wiring layer and the second wiring portion being formed as the second wiring layer. 1. A semiconductor device comprising:a memory mat including a plurality of memory cells;a sense amplifier located in a sense amplifier area and amplifying data supplied from the memory cells to generate first amplified data;a main amplifier that amplifies the first amplified data supplied from the sense amplifier;a main I/O line extends in a first direction to connect the sense amplifier to the main amplifier, the main I/O line including a first section provided over the memory mat as a first wiring layer and the second section provided over the sense amplifier area as a third wiring layer different from the first wiring layer; anda power-supply line provided as the third wiring layer such that the power-supply line overlaps with the first section of the main I/O line.2. The semiconductor device as claimed in claim 1 , wherein the third wiring layer is over the first wiring layer.3. The semiconductor device as claimed in claim 2 , further comprising a local I/O line provided over the sense amplifier area and extending in a second direction crossing the first direction to connect the sense amplifier to the main I/O line claim 2 ,wherein ...

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Номер записи: 59
04-07-2013 дата публикации

Boundary scan chain for stacked memory

Номер: US20130173971A1
Автор: David J. Zimmerman
Принадлежит: Individual

A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.

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Номер записи: 60
11-07-2013 дата публикации

Layout to minimize fet variation in small dimension photolithography

Номер: US20130175631A1
Автор: Daniel M. Nelson, Derick G. Behrends, Michael Launsbach, Todd A. Christensen, Travis R. Hebig
Принадлежит: International Business Machines Corp

A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.

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Номер записи: 61
11-07-2013 дата публикации

STACKED MEMORY WITH REDUNDANCY

Номер: US20130176763A1
Автор: Franzon Paul D., Ware Frederick A.
Принадлежит: RAMBUS INC.

A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and stacked with a second integrated circuit memory chip. A redundant memory is shared by the first and second integrated circuit memory chips and has redundant storage locations that selectively replace corresponding storage locations in the first or second integrated circuit memory chips. The stacked memory also includes a pin interface for coupling to an external integrated circuit memory controller and respective first and second signal paths. The first signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface. The second signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface via the first signal path. 1. A stacked memory comprising:a first integrated circuit memory chip having first storage locations;a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip, the second integrated circuit memory chip having second storage locations;a redundant memory shared by the first and second integrated circuit memory chips, the redundant memory having redundant storage locations that selectively replace corresponding storage locations in the first or second integrated circuit memory chips;a pin interface for coupling to an external memory controller;a first signal path formed through the first and second integrated circuit memory chips and coupled to the redundant memory, the first signal path coupled to the pin interface; anda second signal path formed through the first and second integrated circuit memory chips and coupled to the redundant memory, the second signal path coupled to the pin interface via the first signal path.2. The stacked memory according to wherein the redundant memory comprises a redundant integrated ...

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Номер записи: 62
18-07-2013 дата публикации

Discrete Three-Dimensional Memory Comprising Off-Die Address/Data Translator

Номер: US20130182483A1
Автор: ZHANG Guobiao
Принадлежит:

The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its address-data translator (A/D-translator) is located on a separate peripheral-circuit die. The A/D-translator converts at least an address and/or data between logical space and physical space for the 3D-array die. A single A/D-translator die can support multiple 3D-array dies. 1. A discrete three-dimensional memory (3D-M) , comprising:a first 3D-array die comprising at least a first 3D-M array including a plurality of vertically stacked memory levels;a first peripheral-circuit die comprising an address/data translator for converting at least an address and/or data between logical space and physical space for said first 3D-array die;a second peripheral-circuit die comprising a read/write-voltage generator for providing said first 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply;wherein said first 3D-array die, said first peripheral-circuit die and said second peripheral-circuit die are separate dies.2. The memory according to claim 1 , further comprising a second 3D-array die comprising at least a second 3D-M array including a plurality of vertically stacked memory levels claim 1 , wherein:said address/data translator converts at least an address and/or data between logical space and physical space for said second 3D-array die;said read/write-voltage generator provides said second 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply;said first 3D-array die, said second 3D-array die, said first peripheral-circuit die and said second peripheral-circuit die are separate dies.3. The memory according to claim 1 , wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).4. The memory according to claim 1 , wherein said 3D-M comprises a three-dimensional mask-programmed read- ...

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Номер записи: 63
18-07-2013 дата публикации

Data Storage and Stackable Configurations

Номер: US20130182485A1
Автор: KIM Jin-Ki, OH HakJune, PYEON Hong Beom
Принадлежит:

A first memory device and second memory device have a same input/output layout configuration. To form a stack, the second memory device is secured to the first memory device. To facilitate connectivity, the second memory device is rotationally offset with respect to the first memory device in the stack to align outputs of the first memory device with corresponding inputs of the second memory device. The rotational offset of the second memory device with respect to the first memory device aligns one or more outputs of the first memory device with one or more respective inputs of the second memory device. Based on links between outputs and inputs from one memory device to another in the stack, the stack of memory devices can include paths facilitating one or more series connection configurations through the memory devices. 1. A method comprising:receiving a first memory device;receiving a second memory device, the first memory device and the second memory device having a same input/output layout configuration; andproducing a stack of memory devices in which the first memory device and the second memory device are rotationally offset with respect to each other in the stack to align outputs of the first memory device with inputs of the second memory device.2. The method as in claim 1 , wherein the first memory device includes a facing of input-output pads and the second memory device includes a facing of input-output pads; andwherein producing the stack of memory devices includes orienting the facing of the second memory device in the stack to point in a same direction as the facing of the first memory device in the stack.3. The method as in further comprising:staggering the first memory device with respect to the second memory device in the stack to expose outputs on a plane of the first memory device for electrically connecting to inputs exposed on a plane of the second memory device; andproviding electrical connectivity between the outputs of the first memory device ...

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Номер записи: 64
18-07-2013 дата публикации

Memory device, method of operating the same, and apparatus including the same

Номер: US20130182522A1
Автор: Cheol Kim, Jung Sik Kim, Young-Il Lim, Yun Sang Lee
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of operating a memory device includes masking at least one bank among a plurality of banks in response to a mode register writing command; and performing a refresh operation on a plurality of rows in one of unmasked banks in response to a first per-bank refresh command.

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Номер записи: 65
01-08-2013 дата публикации

MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DATA INTERFACES

Номер: US20130194854A1
Автор: Bansal Akash, Ho Fan, Lai Lawrence, Leibowitz Brian S., Oh Kyung Suk, Richardson Wayne S., Secker David A., Shaeffer Ian
Принадлежит: RAMBUS INC.

A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins. 1. A memory device , comprising:a first and second command-and-address (CA) interface; and select an operational mode, wherein both the first and second CA interfaces are active in a first operational mode, and wherein only one of the first or second CA interface is active in a second operational mode, and', 'select the first or second CA interface as the active CA interface in the second operational mode., 'circuitry to2. The memory device of claim 1 , wherein the memory device is capable of supporting multiple microthreads in the first operational mode claim 1 , and wherein the memory device is capable of supporting only a single microthread in the second operational mode.3. The memory device of claim 1 , wherein the circuitry is capable of selecting the operational mode based on:one or more bits in one or more registers,one or more signals received on one or more pins, ora combination of one or more bits in one or more registers and one or more signals received on one or more pins.4. The memory device of claim 1 , wherein the circuitry is capable of selecting the first or second CA interface as the active ...

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Номер записи: 66
01-08-2013 дата публикации

High current capable access device for three-dimensional solid-state memory

Номер: US20130194855A1
Автор: Luiz M. Franca-Neto
Принадлежит: Individual

The present invention generally relates to three-dimensional arrangement of memory cells and methods of addressing those cells. The memory cells can be arranged in a 3D orientation such that macro cells that are in the middle of the 3D arrangement can be addressed without the need for overhead wiring or by utilizing a minimal amount of overhead wiring. An individual macro cell within a memory cell can be addressed by applying three separate currents to the macro cell. A first current is applied to the memory cell directly. A second current is applied to the source electrode of the MESFET, and a third current is applied to the gate electrode of the MESFET to permit the current to travel through the channel of the MESFET to the drain electrode which is coupled to the memory element.

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Номер записи: 67
08-08-2013 дата публикации

Three-Dimensional Memory Comprising an Integrated Intermediate-Circuit Die

Номер: US20130201743A1
Автор: ZHANG Guobiao
Принадлежит:

The present invention discloses a discrete three-dimensional memory (3D-M). It comprises at least a 3D-array die and at least an integrated intermediate-circuit die comprising both a read/write-voltage generator (V/V-generator) and an address/data translator (A/D-translator). The intermediate-circuit die performs voltage, address and/or data conversion between the 3D-M core region and the host. Discrete 3D-M support multiple 3D-array dies. 1. A discrete three-dimensional memory (3D-M) , comprising:a 3D-array die comprising at least a 3D-M array including a plurality of vertically stacked memory levels;an intermediate-circuit die comprising a read/write-voltage generator and an address/data translator, wherein said read/write-voltage generator provides said 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply, and said address/data translator converts at least an address and/or data of a host to an address/data of said 3D-array die and vice versa;wherein said 3D-array die and said intermediate-circuit die are separate dies.2. The memory according to claim 1 , further comprising another 3D-array die comprising at least a 3D-M array including a plurality of vertically stacked memory levels claim 1 , wherein:said read/write-voltage generator provides said another 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply;said address/data translator converts at least an address and/or data of a host to an address/data of said second 3D-array die and vice versa;both of said 3D-array dies and said intermediate-circuit die are separate dies.3. The memory according to claim 1 , wherein said read/write-voltage generator comprises a DC-to-DC converter.4. The memory according to claim 1 , wherein said address/data translator is an address translator comprising at least one of an address mapping table claim 1 , a faulty block table and a wear management table.5. The memory according to claim 1 , ...

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Номер записи: 68
15-08-2013 дата публикации

MEMORY MODULE FOR HIGH-SPEED OPERATIONS

Номер: US20130208524A1
Автор: Ko Chang-Woo, Lee Jea-Eun, Lee Young-Ho, SUNG MYUNG-HEE
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A memory module includes a plurality of buses. A plurality of memory chips is mounted on a module board and is connected to a first node, a second node, and a plurality of third nodes of the plurality of buses. The first node, the second node, and the third nodes branch off to a first memory chip, a second memory chip, and the third memory chips, respectively. A length of the plurality of buses between the first and second nodes is longer than a length of the plurality of buses between adjacent nodes from among the second node and the third nodes. 1. A memory module comprising:a plurality of buses; anda plurality of memory chips mounted on a module board, and connected to a first node, a second node, and a plurality of third nodes of the plurality of buses, respectively,wherein the first node, the second node, and the third nodes branch off to a first memory chip, a second memory chip, and a plurality of third memory chips, respectively, andwherein a length of the plurality of buses between the first and second nodes is longer than a length of the plurality of buses between adjacent nodes from among the second node and the third nodes.2. The memory module of claim 1 , wherein the lengths of the plurality of buses between adjacent nodes from among the second node and the third nodes are all equal.3. The memory module of claim 1 , further comprising a buffer chip mounted on the module board claim 1 , the buffer chip controlling operations of the plurality of memory chips.4. The memory module of claim 3 , wherein the plurality of memory chips is disposed on an upper surface and a lower surface of the module board in at least one row at both sides of the buffer chip claim 3 , in such a manner that the memory chips on the upper surface of the module board and the memory chips on the lower surface of the module board correspond to each other claim 3 ,wherein the plurality of buses comprise a command/address signal bus having a split fly-by structure, andwherein a command/ ...

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Номер записи: 69
22-08-2013 дата публикации

LOAD REDUCED MEMORY MODULE AND MEMORY SYSTEM INCLUDING THE SAME

Номер: US20130215659A1
Автор: FUJISAWA Hiroki, HIRAISHI Atsushi, Nakamura Masayuki, OSANAI Fumiyuki, SAITO Shunichi, SUGANO Toshio
Принадлежит: ELPIDA MEMORY, INC.

A device includes a printed circuit board, a clock connector provided on the printed circuit board and configured to be supplied with a first clock signal, a first register buffer provided on the printed circuit board, coupled to the clock connector and, including a first clock generator that produces a second clock signal in response to the first clock signal, a plurality of data connectors, provided on the printed circuit board, a plurality of memory chips each provided on the printed circuit board and including a first data terminal, and a plurality of second register buffers each provided on the printed circuit board independently of the first register buffer. 1. A device comprising:a printed circuit board;a clock connector provided on the printed circuit board and configured to be supplied with a first clock signal;a first register buffer provided on the printed circuit board, coupled to the clock connector and including a first clock generator that produces a second clock signal in response to the first clock signal;a plurality of data connectors provided on the printed circuit board;a plurality of memory chips each provided on the printed circuit board and including a first data terminal; anda plurality of second register buffers each provided on the printed circuit board independently of the first register buffer; a clock terminal configured to receive the second crock signal;', 'a second date terminal coupled to the first data terminal of an associated one of the memory chips;', 'a third data terminal coupled to an associated one of the data connectors;', 'a second clock generator configured to produce a third clock signal in response to the second clock signal; and', 'a data transfer circuit coupled between the second and third data terminals and configured to perform a data transfer therebetween in response to the third clock signal., 'wherein each of the second register buffers comprises2. The device as claimed in claim 1 , wherein the first clock ...

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Номер записи: 70
22-08-2013 дата публикации

MEMORY CIRCUIT AND SEMICONDUCTOR DEVICE

Номер: US20130215661A1
Автор: KOYAMA Jun
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Included is a first transistor for controlling rewriting and reading of a first data, a second transistor for controlling rewriting and reading of a second data, a first inverter including an input terminal for the first data, a second inverter including an input terminal for the second data, a third transistor between an output terminal of the second inverter and the input terminal of the first inverter, a fourth transistors between the output of the first inverter and the input terminal of the second inverter, a fifth transistor for controlling rewriting and reading of the first data in the first capacitor, and a sixth transistor for controlling rewriting and reading of the second data in a second capacitor. The first data and the second data are held in the first capacitor and the second capacitor even while power supply is cut off. 1. A memory circuit comprising:a first transistor;a second transistor;a first inverter comprising an input terminal connected to one of a source electrode and a drain electrode of the first transistor, and an output terminal;a second inverter comprising an input terminal connected to one of a source electrode and a drain electrode of the second transistor, and an output terminal;a third transistor comprising one of a source electrode and a drain electrode connected to the input terminal of the first inverter and the one of the source electrode and the drain electrode of the first transistor, and the other of the source electrode and the drain electrode connected to the output terminal of the second inverter;a fourth transistor comprising one of a source electrode and a drain electrode connected to the input terminal of the second inverter and the one of the source electrode and the drain electrode of the second transistor, and the other of the source electrode and the drain electrode connected to the output terminal of the first inverter;a fifth transistor comprising one of a source electrode and a drain electrode connected to the one ...

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Номер записи: 71
29-08-2013 дата публикации

MEMORY MODULE AND ON-DIE TERMINATION SETTING METHOD THEREOF

Номер: US20130223123A1
Автор: Baek Jeonghoon, Kim Bo-Ra, Lee Jaejun
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A memory system includes a plurality of memory devices on a printed circuit board, each of the memory devices including a plurality of external pads; a plurality of connection terminals formed on the printed circuit board, and electrically connected to respective ones of the external pads; and a plurality of signal lines formed on the printed circuit board to connect the connection terminals with the external pads, each of the signal lines between a corresponding connection terminal and a corresponding external pad and having a length. The plurality of memory devices are arranged at different distances from the plurality of connection terminals, and each signal line that connects a connection terminal to an external pad of a memory device either is connected to or does not connect a stub resistor depending on a length of the line. 1. A memory system comprising:a printed circuit board;a plurality of connection terminals formed on the printed circuit board; and the plurality of memory devices comprise: a first set of memory devices arranged in a first row of the printed circuit board; and a second set of memory devices arranged in a second row of the printed circuit board,', 'a first memory device of the first set of memory devices is electrically connected to a first group of connection terminals of the plurality of connection terminals through a first group of signal lines, such that all of the connections between the first memory device of the first set of memory devices and connection terminals on the printed circuit board pass through the first group of signal lines,', 'a first memory device of the second set of memory devices is electrically connected to a second group of connection terminals of the plurality of connection terminals through a second group of signal lines, such that all of the connections between the first memory device of the second set of memory devices and connection terminals on the printed circuit board pass through the second group of ...

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Номер записи: 72
29-08-2013 дата публикации

Semiconductor Device Capable of Rescuing Defective Characteristics Occurring After Packaging

Номер: US20130223171A1
Автор: Jeong-Kyoum Kim, Jung-hwan Choi, Seok-Hun Hyun, Seong-Jin Jang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory device capable of rescuing defective characteristics that occur after packaging includes a memory cell array including a plurality of memory cells and an antifuse circuit unit including at least one antifuse. The antifuse circuit unit stores a defective cell address of the memory cell array in the at least one antifuse and reads the defective cell address to an external source. The antifuse circuit unit stores a defective characteristic code in the at least one antifuse, wherein the defective characteristic code is related to at least one of a timing parameter spec., a refresh spec., an input/output (I/O) trigger voltage spec., and a data training spec. of the memory device, and outputs the defective characteristic code to an external source.

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Номер записи: 73
05-09-2013 дата публикации

Memories with Cylindrical Read/Write Stacks

Номер: US20130229846A1
Автор: Alsmeier Johann, Chien Henry, Lee Yao-Sheng, Samachisa George
Принадлежит: SanDisk 3D LLC

A three-dimensional memory is formed as an array of memory elements across multiple layers positioned at different distances above a semiconductor substrate. Cylindrical stacks of memory elements are formed where a cylindrical opening has read/write material deposited along its wall, and a cylindrical vertical bit line formed along its central axis. Memory elements formed on either side of such a cylinder may include sheet electrodes that extend into the read/write material. 1. A three-dimensional array of read/write elements comprising:a plurality of horizontal line stacks, each horizontal line stack comprising a plurality of electrically-conductive horizontal lines that extend in a first direction and are separated from each other by insulating material, individual stacks separated from adjacent stacks in a second direction that is perpendicular to the first direction;a plurality of cylinders of read/write material located between a first horizontal line stack and a second horizontal line stack so that each cylinder of the plurality of cylinders is in electrical contact with horizontal lines of the first and second horizontal line stacks; anda plurality of vertical lines, each vertical line extending through a corresponding cylinder of read/write material to form read/write elements between the vertical line and horizontal lines of the first and second horizontal line stacks.2. The three-dimensional array of wherein the electrically-conductive horizontal lines of the first and second horizontal line stacks include sheet electrodes that extend towards the vertical lines claim 1 , a sheet electrode having a vertical thickness that is less than the total vertical thickness of a horizontal line.3. The three-dimensional array of wherein the sheet electrode extends into a cylinder of read/write material.4. The three-dimensional array of claim three wherein the sheet electrode is formed of Titanium Nitride (TiN).5. The three-dimensional array of wherein the electrically- ...

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Номер записи: 74
05-09-2013 дата публикации

MEMORY DIES, STACKED MEMORIES, MEMORY DEVICES AND METHODS

Номер: US20130229847A1
Автор: Ito Yutaka, Nakanishi Takuya
Принадлежит: MICRON TECHNOLOGY, INC.

Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node. 1. A memory die configured to be arranged in a stack of memory dies , wherein the stack comprises an external select connection node , the memory die comprising:a plurality of detection circuits, each detection circuit being configured to determine if it is coupled to the external select connection node; anda decoder configured to receive detection signals from at least a portion of the plurality of detection circuits and to output an identification of the memory die responsive to which, if any, of the detection circuits is coupled to the external select connection node using the received ones of the detection signals.2. The memory die of claim 1 , further comprising an input buffer configured to receive a signal from the external select connection node.3. The memory die of claim 2 , further comprising a delay circuit claim 2 , wherein the delay circuit is configured to delay a signal received from the external select connection node responsive to the identification.4. The memory die of claim 1 , wherein the memory die is configured to be coupled to another memory die in the stack via four select related connection nodes claim 1 , wherein the plurality of detection circuits comprise at least three detection circuits claim 1 , wherein each of the at least three detection circuits is configured to be coupled to a respective one of the select related connection nodes when the die is arranged in the stack.5. A method comprising:determining an identification ...

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Номер записи: 75
05-09-2013 дата публикации

MULTI-DIE DRAM BANKS ARRANGEMENT AND WIRING

Номер: US20130229848A1
Автор: Vogelsang Thomas
Принадлежит:

A memory die for use in a multi-die stack having at least one other die. The memory die includes a plurality of contacts arranged in a field and configured to interface to the other dies of the multi-die stack. A first subset of the buffer lines of a number of buffer lines are connected to respective contacts in the field. The memory die also includes a number of buffers and cross-bar lines. The buffers are coupled between respective signal lines and respective buffer lines. The cross-bar lines interconnect respective pairs of buffer lines in a second subset of the buffer lines that is distinct from the first subset of the buffer lines. 1. A memory die for use in a multi-die stack having at least one other die , comprising:a plurality of memory banks, each having a plurality of signal lines;a plurality of contacts arranged in a field, the contacts configured to interface to the at least one other die of the multi-die stack;buffer lines, including a first subset of buffer lines and a second subset of buffer lines, the first subset of buffer lines being connected to respective contacts in the field;a plurality of buffers each coupled between a respective signal line and a respective buffer line; anda plurality of cross-bar lines interconnecting respective pairs of buffer lines in the second subset of buffer lines.2. The memory die of claim 1 , wherein the contacts in the field comprise a plurality of through-silicon vias (TSVs) claim 1 , the TSVs configured to interface to the other die of the multi-die stack.3. The memory die of claim 1 , wherein each buffer of the plurality of buffers claim 1 , when in a first state claim 1 , connects a respective signal line of the plurality of signal lines to a corresponding buffer line.4. The memory die of claim 3 , wherein each buffer of the plurality of buffers claim 3 , when in a second state claim 3 , together with another buffer in the second state claim 3 , connects a respective buffer line in the first subset to a ...

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Номер записи: 76
12-09-2013 дата публикации

MAGNETIC RANDOM ACCESS MEMORY (MRAM)LAYOUT WITH UNIFORM PATTERN

Номер: US20130235639A1
Автор: Kang Seung H., Kim Jung Pill, Kim Taehyun, Lee Kangho, Li Xia
Принадлежит: QUALCOMM INCORPORATED

A large scale memory array includes a. uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects. 1. A memory array , comprising:a pattern of adjacent uniformly sized bit cells; andsignal distribution circuitry occupying an area having a size coinciding with an integer multiple of a size of the uniformly sized bit cells.2. The memory array of claim I. in which the adjacent uniformly sized bit cells comprise a plurality of active bit cells outside of a footprint of the signal distribution circuitry area.3. The memory array of claim 2 , comprising:a resistive memory element configured in each of the active bit cells.4. The memory array of claim 2 , comprising:a magnetic tunnel junction configured in each of the active bit cells.5. The memory array of claim 2 , in which the adjacent uniformly sized bit cells comprise a plurality of dummy bit cells within the footprint of the signal distribution circuitry area.6. The memory array of claim 2 , in which the signal distribution circuitry is coupled to the active bit cells.7. The memory array of claim 1 , in which the signal distribution circuitry comprises:word line strapping extending in a first dimension of the pattern.8. The memory array of claim 1 , in which the signal distribution circuitry comprises:at least one substrate tie extending in a second dimension of the pattern.9. The memory array of claim 1 , further comprising a plurality of edge dummy cells extending ...

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Номер записи: 77
12-09-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130235641A1
Автор: IWAKI Hiroaki
Принадлежит: ELPIDA MEMORY, INC.

Disclosed herein is a semiconductor device including a multi-level wiring structure that includes a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level and upper-level wirings. The device further includes a plurality of bit lines for a plurality of memory cells, and each of the bit lines includes a first portion that is formed as the lower-level wiring and a second portion that is electrically connected in series to the first portion and formed as the upper-level wiring. 1. A semiconductor device comprising:a first memory mat comprising a plurality of first memory cells;a second memory mat comprising a plurality of second memory cells;a first global bit line extending over the first memory mat and the second memory mat; anda multi-level wiring structure comprising a lower-level wiring, an upper-level wiring, and an interlayer insulation film between the lower-level wiring and the upper-level wiring;the first global bit line comprising a first portion over the first memory mat and a second portion over the second memory mat, the first portion being formed as the lower-level wiring, and the second portion being formed as the upper-level wiring.2. The semiconductor device as recited in claim 1 , wherein the first memory mat comprises a first local bit line connected to the plurality of first memory cells and a first switching element connected between the first local bit line and the first global bit line claim 1 , andthe second memory mat comprises a second local bit line connected to the plurality of second memory cells and a second switching element connected between the second local bit line and the first global bit line.3. The semiconductor device as recited in claim 1 , wherein the first global bit line comprises a contact plug penetrating the interlayer insulation film to connect the first portion and the second portion to each other.4. The semiconductor device as recited in claim 1 , wherein:the first memory mat ...

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Номер записи: 78
26-09-2013 дата публикации

MULTI-CHIP PACKAGE AND MEMORY SYSTEM

Номер: US20130250643A1
Автор: MATSUNAGA Naoki
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation. 1. A multi-chip package comprising:a first group of memory chips that includes a first memory chip and a second memory chip;a second group of memory chips that includes at least one memory chip;a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal; anda second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal,wherein the first memory chip and the second memory chip each comprises a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation.2. The multi-chip package according to claim 1 , wherein the first memory chip and the second memory chip each include an initial value-setting module configured to set the address associated with the memory chip to an initial state.3. The multi-chip package according to claim 2 , wherein the first memory chip and the second memory chip ...

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Номер записи: 79
26-09-2013 дата публикации

CONTROL CIRCUIT BOARD, CONTROL SYSTEM, AND COPYING METHOD

Номер: US20130250644A1
Автор: Watanabe Kenichi
Принадлежит: RICOH COMPANY, LIMITED

A control circuit board includes a first storage unit configured to store therein predetermined data; a connecting unit configured to be connected to another control circuit board including a second storage unit; a switching unit configured to switch between a first state and a second state, the first state being a state in which data read from the first storage unit is enabled but data read from the second storage unit is disabled, the second state being a state in which data read from the first storage unit is disabled but data read from the second storage unit is enabled; and a storage control unit configured to write or read data to or from the first storage unit in the first state, and perform a copying operation that reads the data from the second storage unit and stores the read data in the first storage unit in the second state. 1. A control circuit board comprising:a first storage unit configured to store therein predetermined data;a connecting unit configured to be connected to another control circuit board that includes a second storage unit;a switching unit configured to switch between a first state and a second state, the first state being a state in which data read from the first storage unit is enabled but data read from the second storage unit is disabled, the second state being a state in which data read from the first storage unit is disabled but data read from the second storage unit is enabled; and write or read data to or from the first storage unit in the first state, and', 'perform a copying operation that reads the data from the second storage unit and stores the read data in the first storage unit in the second state., 'a storage control unit configured to'}2. The control circuit board according to claim 1 , wherein the switching unit includesa first switching unit configured to switch between a state where data read from the first storage unit is enabled and a state where data read from the first storage unit is disabled, anda second ...

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Номер записи: 80
26-09-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE FOR REDUCING BIT LINE COUPLING NOISE

Номер: US20130250645A1
Автор: Kim Sang-yun, Ko Tai-young
Принадлежит:

A semiconductor memory device including: first and second memory cell arrays each including at least one word line, at least three bit lines, and memory cells; and a sense amplifier area disposed between the first and second memory cell arrays and including a sense amplifier circuit for sensing and amplifying data of the memory cells, wherein the at least three bit lines of the first memory cell array and the at least three bit lines of the second memory cell array extend in a first direction and the at least three bit lines of the first and the second memory cell arrays are respectively connected to data lines disposed in a second direction, and wherein a bit line located between two of the at least three bit lines of each of the first and the second memory cell arrays is connected to an outermost data line of the data lines. 1. A semiconductor memory device , comprising:first and second memory cell arrays each comprising a plurality of word lines, bit lines disposed to intersect the word lines, and a plurality of memory cells disposed at intersections between the word lines and the bit lines; anda sense amplifier area disposed between the first and the second memory cell arrays and comprising sense amplifier circuits for sensing and amplifying data of the memory cells,wherein bit lines of the first memory cell array and bit lines of the second memory cell array extend into the sense amplifier area, and wherein a portion of a first bit line in at least one of the first and the second memory cell arrays has a width greater than a portion of the first bit line in the sense amplifier area.2. The semiconductor memory device of claim 1 , wherein a distance between the portion of the first bit line and a second bit line in the sense amplifier area is greater than a distance between the portion of the first bit line and a third bit line in the at least one of the first and the second memory cell arrays.3. The semiconductor memory device of claim 2 , wherein the second bit ...

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Номер записи: 81
26-09-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20130250646A1
Автор: IIDA Masahisa
Принадлежит: Panasonic Corporation

In a memory device having a hierarchical bit line architecture, a main memory array is divided into two sub-memory arrays. The number of sub bit lines is twice the number of main bit lines, and global data lines are formed in the same metal interconnect layer as the main bit lines, thereby reducing an increase in the number of interconnects used in a memory macro. Furthermore, after charge sharing of the bit lines, the global data lines are kept in a pre-charge state at the time of amplification using sense amplifiers so that the global data lines function as shields of the main bit lines. This largely reduces interference noise between adjacent main bit lines to improve operating characteristics. 1. A semiconductor memory device having a hierarchical bit line architecture , the device comprising:a first sub-memory array including a plurality of memory cells coupled in common to first sub bit lines in a cross-point manner;a second sub-memory array including a plurality of memory cells coupled in common to second sub bit lines in a cross-point manner;main bit lines, each being coupled to one of the first sub bit lines via a first switching transistor, and to one of the second sub bit lines via a second switching transistor; andsense amplifiers coupled to the main bit lines such that the main bit lines are arranged in a folded bit line structure, whereina total number of the first sub bit lines and the second sub bit lines is twice a number of the main bit lines, andeach of the main bit lines extends, as a reference bit line, over the sense amplifiers to another memory array and is twisted at a portion together with another main bit line.2. The semiconductor memory device of claim 1 , whereinthe main bit lines are twisted around centers of the main bit lines in a longitudinal direction.3. The semiconductor memory device of claim 1 , whereinthe main bit lines are twisted in a region above the sense amplifiers.4. The semiconductor memory device of claim 1 , further ...

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Номер записи: 82
03-10-2013 дата публикации

SEMICONDUCTOR DEVICE HAVING MULTIPORT MEMORY

Номер: US20130258741A1
Автор: FUNANE Kiyotada, SHIBATA KEN, SHIMAZAKI Yasuhisa
Принадлежит: RENESAS ELECTRONICS CORPORATION

A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA, WLB, WLB, WLA, WLA. Further, a pitch d between WLA-WLA and between WLB-WLB is made smaller than a pitch d between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d on the other. 1a plurality of word line groups respectively including a first word line for a first port and a second word line for a second port and the first word line and the second word line being disposed in juxtaposition with one another;a plurality of bit line groups respectively extending in a direction orthogonal to an extension direction of the word line groups and including a first bit line for the first port and a second bit line for the second port and the first word line and the second word line being disposed in juxtaposition with one another; anda plurality of memory cells disposed at respective intersections between the word line groups and the bit line groups,wherein the first word line and the second word line included in one of the word line groups are disposed at a first pitch;wherein the first word line included in one of the word line groups is disposed adjacent to the first word line included in a word line group disposed on one neighboring side of the one word line group concerned at a second pitch;wherein the second word line included in one of the word line groups is disposed adjacent to the second word line included in a word line group disposed on the other neighboring side of the one word line group concerned at the second pitch; andwherein a first shield line extending in juxtaposition with the first word line and the ...

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Номер записи: 83
03-10-2013 дата публикации

SEMICONDUCTOR DEVICE HAVING MEMORY CELL ARRAY DIVIDED INTO PLURAL MEMORY MATS

Номер: US20130258742A1
Автор: KOSHIKAWA Yasuji, NODA Hiromasa
Принадлежит:

A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the X direction. The mat selecting circuit activates at least one of the memory mats included in each of the memory mat groups, while maintaining the rest of memory mats inactivated. With this operation, a portion of discontinuity does not occur in the memory mats arranged in the X direction, and thus the necessity of arranging two sub-word driver areas in the portion of discontinuity is eliminated. 1. A semiconductor device comprising:first, second, third, fourth, fifth, sixth, seventh and eighth memory mats that are arranged in line in that order, each of the first to eighth memory mats including a plurality of memory cells; anda selection circuit that is configured to respond to a first bit of a row address including a plurality of bits and to activate the first, second, fifth and sixth memory mats in parallel to one another with deactivating the third, fourth, seventh and eighth memory mats when the first bit of the row address is one of logic-1 and logic-0 and to activate the third, fourth, seventh and eighth memory mats in parallel to one another with deactivating the first, second, fifth and sixth memory mats when the first bit of the row address is the other of logic-1 and logic-0.2. The device as claimed in claim 1 ,wherein each of the first to eighth memory mats further includes a plurality of word lines; andwherein the device further comprises first, second, third and fourth word drivers, the first word driver being between the first and second memory mats to be connected to the word lines of each of the first and second memory mats, the second word driver being between the third and fourth memory mats to ...

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Номер записи: 84
10-10-2013 дата публикации

MAGNETIC RAMDOM ACCESS MEMORY

Номер: US20130265814A1
Автор: SHIN Hyung Soon
Принадлежит: Ewha University - Industry Collaboration Foundation

A magnetic random access memory includes multiple gate lines that are divided into a first gate line group and a second gate line group and arranged to be parallel to one another; multiple magnetic random access memory cells that are bonded to the gate lines in a direction intersected with the gate lines, respectively; multiple source lines that are bonded to one ends of switching devices included in the magnetic random access memory cells and arranged to be parallel to one another; and multiple bit lines that are bonded to one ends of magnetic tunnel junction devices included in the magnetic random access memory cells and arranged to be parallel to one another. 1. A magnetic random access memory comprising:multiple gate lines that are divided into a first gate line group and a second gate line group and arranged to be parallel to one another;multiple magnetic random access memory cells that are bonded to the gate lines in a direction intersected with the gate lines, respectively;multiple source lines that are bonded to one ends of switching devices included in the magnetic random access memory cells and arranged to be parallel to one another; andmultiple bit lines that are bonded to one ends of magnetic tunnel junction devices included in the magnetic random access memory cells and arranged to be parallel to one another,wherein the other ends of the switching devices and the other ends of the magnetic tunnel junction devices are connected to each other in series,the magnetic random access memory cell bonded to the first gate line group is arranged so as not to be adjacent to the magnetic random access memory cell bonded to the second gate line group, andthe source lines and the bit lines are bonded to the magnetic random access memory cell bonded to the gate lines different from each other and the source lines and the bit lines are arranged so as to be intersected with each other.2. The magnetic random access memory of claim 1 ,wherein the bit lines is arranged in ...

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Номер записи: 85
10-10-2013 дата публикации

Semiconductor device having auxiliary power-supply wiring

Номер: US20130265840A1
Автор: Hisayuki Nagamine, Masaki Yoshimura
Принадлежит: Elpida Memory Inc

Disclosed herein is a semiconductor device that includes a signal wiring arranged on a first layer and extending over the circuit block or blocks in the first direction so as to reach the first circuit block and produce a free space above the first circuit block, the signal wiring being electrically connected to the first circuit block, a power-supply wiring arranged on a second layer and extending over the circuit block or blocks in the first direction so as to reach the first circuit block, the power-supply wiring supplying an operating voltage to the first circuit block and an auxiliary power-supply wiring being configured to enhance the operating voltage supplied by the power supply line, and the auxiliary power-supply wiring being formed in the free space produced by the arrangement of the signal wiring.

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Номер записи: 86
17-10-2013 дата публикации

SELF-DISABLING CHIP ENABLE INPUT

Номер: US20130272048A1
Автор: Chu Daniel
Принадлежит:

A multi-die memory package may have separate chip enable inputs for the respective memory dice. Individual chip enable inputs may be separated by other chip connections such as power and ground. The memory dice may include multiple chip enable inputs to allow easy wire bonding of the individual chip enable inputs to a die without requiring any jumpers within the package. Circuitry may be included so that undriven chip enable inputs are masked and driven chip enable inputs may be propagated to the memory die to enable memory accesses while a single chip enable input is only connected to the capacitance of a single bonding pad. 1. A electronic memory comprising:a first chip enable input pad;a second chip enable input pad that is isolated from the first chip enable input pad; andcircuitry coupled to the first chip enable input pad and the second chip enable input pad;wherein the circuitry is configured to determine whether the electronic memory is enabled for access based on an input voltage level asserted on the first chip enable input pad by an external source if the second chip enable input pad is not connected externally.2. The electronic memory of claim 1 , wherein the circuitry is further configured to determine whether the electronic memory is enabled for access based on the input voltage level asserted on the second chip enable input pad by the external source if the first chip enable input pad is not externally connected.3. The electronic memory of claim 1 , further comprising:at least one additional external connection pad positioned between the first chip enable input pad and the second chip enable input pad.4. The electronic memory of claim 3 , further comprising:other external connection pads;wherein the first chip enable input pad, the second chip enable input pad, the at least one additional external connection pad, and the other external connection pads are arranged for compliance with an Open NAND Flash Interface (ONFI) working group specification.5. ...

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Номер записи: 87
17-10-2013 дата публикации

STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS

Номер: US20130272049A1
Автор: HALBERT John, KIM Jin, Morrow Warren, Schaefer Andre, Shoemaker Kenneth, Vogt Pete
Принадлежит: Intel Corporation

Dynamic operations for operations for a stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element. 1. A memory device comprising:a system element for the memory device; anda memory stack coupled with the system element, the memory stack including one or more memory die layers, each memory die layer including first face and a second face, the second face of each memory die layer including an interface for coupling a plurality of data interface pins of the memory die layer with a plurality of data interface pins in a first face of a coupled element;wherein the interface of each memory die layer includes interconnects that provide an offset between each of the plurality of data interface pins of the memory die layer and a corresponding data interface pin of a plurality of data interface pins of the coupled element.2. The memory device of claim 1 , wherein the memory stack includes a plurality of memory die layers claim 1 , the plurality of memory die layers being coupled together in the memory stack.3. The memory device of claim 2 , wherein the memory stack includes a top memory die layer having a first face that is not coupled with another memory die layer.4. The memory device of claim 3 , wherein one or more of the memory die layers includes a plurality of through silicon vias (TSVs) claim 3 , wherein each of the plurality of ...

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Номер записи: 88
17-10-2013 дата публикации

Method and Apparatus for Programming a Spin-Transfer Torque Magnetic Random Access Memory (STTMRAM) Array

Номер: US20130272062A1
Автор: Ebrahim Abedifard, Yuchen Zhou, Zihui Wang
Принадлежит: Avalanche Technology Inc

A spin-transfer torque memory random access memory (STTMRAM) cell is disclosed comprising a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ.

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Номер записи: 89
24-10-2013 дата публикации

VERTICAL NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

Номер: US20130279233A1
Автор: Cho Won-Seok, HWANG Sung-Min, JANG Jae-Hoon, JEONG Jae-Hun, KIM Han-soo, Kim Ki-hyun, SHIM Sun-Il
Принадлежит:

A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines. 1. A vertical non-volatile memory device comprising:a substrate;a plurality of groups of memory cell strings on the substrate, each of the memory cell strings comprising a plurality of memory transistors distributed in a vertical direction, substantially perpendicular to the plane of the substrate, such that each of the memory cell strings extends vertically on the substrate, and a respective array of the memory transistors is disposed on each of several layers above the substrate;stacks of integrated word lines on the substrate, the integrated word lines being coupled to sets of the memory transistors, respectively, the memory transistors of each of said sets being those memory transistors which constitute a respective one only of the groups of the memory cell strings and which are disposed within the same layer above the substrate,wherein for each array of memory transistors on a respective layer above the substrate, there are a plurality of integrated word lines electrically isolated from each other in the layer and connected to sets of the memory transistors, respectively; anda stack of layers each of which has a plurality of coplanar word select lines on the substrate,wherein plural ones of the coplanar word select lines in each of the layers of the stack are connected to plural ones of the integrated word lines, respectively, constituting a respective one of the stacks of ...

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Номер записи: 90
31-10-2013 дата публикации

Memory Modules and Devices Supporting Configurable Data Widths

Номер: US20130286706A1
Автор: Hampel Craig E., Perego Richard E., Stark Donald C., Tsern Ely K., Ware Frederick A.
Принадлежит:

Described are memory apparatus organized in physical banks and including configurable data control circuit to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey configuration value to configurable memory apparatus and support point-to-point data buffers for multiple width configurations. 1. (canceled)2. An integrated-circuit memory device comprising:an input to receive memory-width configuration value;data terminals to exchange data with another device;a plurality of physical banks, each physical bank including columns of memory cells coupled to corresponding sense amplifiers; anda data control circuit coupling the physical banks with the data terminals, the data control circuit supporting first and second width configurations responsive to the configuration value; in the first width configuration, the data control circuit conveys data of a first data width between a first integer number of the physical banks per read operation and the data terminals, and the plurality of physical banks collectively provide a first memory depth, and', 'in the second width configuration, the data control circuit conveys data of a second data width between a second integer number of the physical banks per read operation and the data terminals, the second data width wider than the first data width, the second integer number larger than the first integer number, and the plurality of physical banks collectively provide a second memory depth; and', 'wherein the memory device loads a first page of sense amplifiers in the first number of the physical banks for activate operation in the first width configuration and loads a second page of sense amplifiers in the second number of physical banks for activate operations in the second width configuration, the first page smaller than the second page., 'wherein3 ...

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Номер записи: 91
31-10-2013 дата публикации

STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS

Номер: US20130286707A1
Автор: Crisp Richard Dewitt, Haba Belgacem, Lambrecht Frank, Zohni Wael
Принадлежит:

A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane. 1. A microelectronic structure , comprising:active elements defining a memory storage array;address input contacts for receipt of address information specifying locations within the storage array; anddata contacts configured for transferring data at least one of from the storage array or to the storage array,the structure having a first surface and first and second peripheral edges each extending away from the first surface and being opposite from one another, and the structure having terminals exposed at the first surface, the terminals including first terminals and the structure being configured to provide address information received at the first terminals to the address input contacts, each of at least some of the first terminals having a signal assignment including information to be transferred to one or more of the address input contacts,the first terminals disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein signal assignments of the first terminals disposed on the first side are symmetric about the theoretical plane with the signal assignments of the first terminals disposed ...

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Номер записи: 92
31-10-2013 дата публикации

MEMORY EDGE CELL

Номер: US20130286708A1
Автор: CHEN Jung-Hsuan, CHENG Hong-Chen, LEE Cheng Hung, LEE Ming-Yi, LIAO Hung-Jen, PAN Kuo-Hua, TIEN Li-Chun
Принадлежит:

A column of a memory includes a first edge cell and at least one memory cell. The first edge cell is located at a first edge of the column and includes a first edge cell reference node and a second edge cell reference node. Each of the at least one memory cells includes a first memory reference node. The first edge cell reference node is coupled to respective first memory reference nodes of the at least one memory cell. The second edge cell reference node serves as second memory reference nodes of the at least one memory cell. Front-end layers of the first edge cell are the same as front-end layers of a memory cell of the at least one memory cell. 1. A column of a memory comprising:a first edge cell located at a first edge of the column and including a first edge cell reference node and a second edge cell reference node; andat least one memory cell, each of the at least one memory cells including a first memory reference node,whereinthe first edge cell reference node is coupled to one or more corresponding first memory reference nodes of the at least one memory cell;the second edge cell reference node serves as second memory reference nodes of the at least one memory cell; andfront-end layers of the first edge cell are the same as front-end layers of a memory cell of the at least one memory cell.2. The column of further comprising a second edge cell located at a second edge of the column.3. The column of claim 2 , wherein the first edge cell is different from the second edge cell.4. The column of claim 1 , wherein:a memory cell of the at least one memory cell includes a first memory PMOS transistor, a second memory PMOS transistor, a first memory NMOS transistor, a second memory NMOS transistor, a third memory NMOS transistor, and a fourth memory NMOS transistor;the first edge cell includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;the first memory PMOS ...

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Номер записи: 93
07-11-2013 дата публикации

Interlayer communications for 3d integrated circuit stack

Номер: US20130293292A1
Автор: Andre Schaefer, Guido Droege, Niklas Linkewitsch
Принадлежит: Intel Corp

Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.

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Номер записи: 94
07-11-2013 дата публикации

Memory Arrays

Номер: US20130294132A1
Автор: Zengtao T. Liu
Принадлежит: Micron Technology Inc

Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F 2 .

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Номер записи: 95
07-11-2013 дата публикации

STACKED LAYER TYPE SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME

Номер: US20130294134A1
Автор: LEE HO CHEOL
Принадлежит:

A stacked layer type semiconductor device includes N memories each including at least one main via and (N−1) sub vias, the N memories being sequentially stacked on one-another so that central axes of the N memories face each other crosswise, and a plurality of connection units electrically connecting the N memories. Here, N is a natural number greater than 1. 1. A stacked layer type semiconductor device comprising:a first memory comprising a first main via, a first sub via, and a first buffer electrically connected to the first main via and the first sub via;a second memory stacked on the first memory, and comprising a second main via electrically connected to the first main via, a second sub via electrically connected to the first sub via, and a second buffer electrically connected to the second main via and the second sub via; andat least one selection circuit for applying an access signal received from an external source to the first buffer and the second buffer along different paths at substantially the same time.2. The stacked layer type semiconductor device of claim 1 , wherein the at least one selection circuit selects a first path in which the access signal is input to the second buffer through the first main via and the second main via claim 1 , and at the same time selects a second path in which the access signal is input to the first buffer through the first sub via.3. The stacked layer type semiconductor device of claim 1 , wherein the at least one selection circuit selects a first path in which the access signal is input to the second buffer through the first sub via and the second sub via claim 1 , and at substantially the same time selects a second path in which the access signal is input to the first buffer through the first main via.4. The stacked layer type semiconductor device of claim 1 , wherein the at least one selection circuit may be at least one fuse or at least one MUX.5. A stacked layer type semiconductor device of claim 1 , ...

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Номер записи: 96
07-11-2013 дата публикации

SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES AND SYSTEM INCLUDING THE SAME

Номер: US20130294135A1
Автор: NARUI Seiji
Принадлежит:

A system includes a first circuit, a second circuit including a logic circuit, and a bus interconnecting the first and second circuits to each other so that the second circuit accesses the first circuit to perform a data transfer therebetween, wherein the first circuit includes a first sense amplifier array including a plurality of first sense amplifiers that are arranged in a first direction, each of the first sense amplifiers including first and second nodes; and a plurality of first global bit lines each extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that each of the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers. 1. A system comprising:a first circuit;a second circuit comprising a logic circuit; anda bus interconnecting the first and second circuits to each other so that the second circuit accesses the first circuit to perform a data transfer therebetween;wherein the first circuit comprises:a first sense amplifier array including a plurality of first sense amplifiers that are arranged in a first direction, each of the first sense amplifiers including first and second nodes;a plurality of first global bit lines each extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that each of the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers;a plurality of second global bit lines each extending in the second direction, the second global bit lines being arranged in the first direction on a right side of the first sense amplifier array so that each of the second global bit lines being operatively connected to the second node of the associated one of the first sense amplifiers;a ...

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Номер записи: 97
07-11-2013 дата публикации

GLOBAL BIT LINE PRE-CHARGE CIRCUIT THAT COMPENSATES FOR PROCESS, OPERATING VOLTAGE, AND TEMPERATURE VARIATIONS

Номер: US20130294136A1
Автор: Bateman Bruce Lynn, Siau Chang Hua
Принадлежит:

A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation. 1. A method of operating a cross point memory array comprising a plurality of word lines and a plurality of bit lines , wherein the plurality of bit lines comprises a plurality of local bit lines , each electrically connected to a corresponding one of a plurality of global bit lines by respective corresponding one of a plurality of gain stage transistors , the plurality of gain stage transistors having parameters that vary with respect to at least one of process , voltage , and temperature , the method comprising:precharging a first selected local bit line of the plurality of local bit lines to a first voltage that varies with the transistor parameters of the corresponding gain stage transistor; andafter precharging the first selected local bit line, applying a voltage to a selected word line of the cross point memory array to read a memory cell coupled between the selected local bit line and the selected word line.2. The method of claim 1 , further comprising claim 1 , coincident with precharging the first selected local bit line ...

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Номер записи: 98
07-11-2013 дата публикации

SEMICONDUCTOR DEVICE HAVING BIT LINE HIERARCHICALLY STRUCTURED

Номер: US20130294137A1
Автор: IKEBATA Koji, MOCHIDA Noriaki, NAGATA Kyoichi, Uno Hiroyuki
Принадлежит: ELPIDA MEMORY, INC.

Disclosed herein is a semiconductor device that includes a plurality of memory cells; a local bit line coupled to the memory cells; a global bit line; and a first switch circuit coupled between the global bit line and the local bit line, the first switch circuit electrically connecting the local bit line to the global bit line when at least one of first and second control signals is in an active state, and the first switch circuit electrically disconnecting the local bit line to the global bit line when both of the first and second control signals are in an inactive state. 1. A semiconductor device comprising:a plurality of memory cells;a local bit line coupled to the memory cells;a global bit line; anda first switch circuit coupled between the global bit line and the local bit line, the first switch circuit electrically connecting the local bit line to the global bit line when at least one of first and second control signals is in an active state, and the first switch circuit electrically disconnecting the local bit line to the global bit line when both of the first and second control signals are in an inactive state.2. The semiconductor device as claimed in claim 1 , further comprising first and second switch drivers respectively generating the first and second control signals.3. The semiconductor device as claimed in claim 2 , wherein the first and second switch drivers are commonly controlled based on a third control signal.4. The semiconductor device as claimed in claim 2 , wherein the first switch circuit includes first and second transistors coupled in parallel between the global bit line and the local bit line claim 2 , and the first and second control signals are respectively supplied to control electrodes of the first and second transistors.5. The semiconductor device as claimed in claim 2 , wherein the first switch circuit includes a third transistor coupled between the global bit line and the local bit line claim 2 , and the first and second control ...

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Номер записи: 99
14-11-2013 дата публикации

SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE

Номер: US20130301330A1
Автор: IZAWA Daiki, MATSUMOTO Yasuhiro, MOCHIDA Noriaki, OHGAMI Takeshi
Принадлежит: ELPIDA MEMORY, INC.

A semiconductor device having hierarchical bit lines is disclosed, which comprises: a first global bit line; first and second local bit lines coupled in common to the first global bit line; first and second power lines; a first transistor coupled between the first local bit line and the first power line; a second transistor coupled between the second local bit line and the second power line; a third transistor coupled between the first and second power lines. 1. A device comprising:a first global bit line;first and second local bit lines coupled in common to the first global bit line;first and second power lines;a first transistor coupled between the first local bit line and the first power line;a second transistor coupled between the second local bit line and the second power line; anda third transistor coupled between the first and second power lines.2. The device as claimed in claim 1 , wherein the third transistor receives a test signal at a control electrode thereof.3. The device as claimed in claim 1 , further comprising first and second power generators coupled respectively to the first and second power lines.4. The device as claimed in claim 3 , wherein each of the first and second power generators is supplied with first and second power supply voltages claim 3 , configured to generate a precharge voltage and configured to supply one of the first and second power supply voltages and the precharge voltage to a corresponding one of the first and second power lines.5. The device as claimed in claim 4 , further comprising a reference voltage generator configured to produce a reference voltage and to supply the reference voltage in common to the first and second power generator claim 4 , and wherein each of the power generators generates the precharge voltage in response to the reference voltage.6. The device as claimed in claim 4 , wherein the precharge voltage is substantially half level between the first and second power supply voltages.7. The device as ...

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Номер записи: 100