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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 5159. Отображено 100.
05-01-2012 дата публикации

Methods, structures, and devices for reducing operational energy in phase change memory

Номер: US20120002465A1
Автор: Roy E. Meade
Принадлежит: Micron Technology Inc

Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. Memory devices include a phase change memory cell and a material, structure, or device for applying stress to the phase change material in the memory cell. In some embodiments, a piezoelectric device may be used to apply stress to the phase change material. In additional embodiments, a material having a thermal expansion coefficient greater than that of the phase change material may be positioned to apply stress to the phase change material.

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Номер записи: 1
16-02-2012 дата публикации

Destruction of data stored in phase change memory

Номер: US20120039117A1
Автор: Gary Edward Webb
Принадлежит: Individual

A mechanism and means by which the data information pattern stored in Phase Change Memory PCM ( 21 ) can be quickly destroyed and made unreadable upon the receipt of a destruction stimuli( 11 ) by the application of a targeted thermal heat source generated by an internal integrated thermal heater ( 26 ), a heat source mounted under the PCM ( 28 ), on top of the PCM ( 29 ), within the PCB ( 30 ), or an externally generated heat source ( 27 ). Such an operation is non-destructive and while the stored data is rendered unreadable, the physical PCM device is unharmed and can be used again.

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Номер записи: 2
15-03-2012 дата публикации

Storage element and memory device

Номер: US20120061780A1
Автор: Hiroyuki Ohmori, Hiroyuki Uchida, Kazuhiro Bessho, Kazutaka Yamane, Masanori Hosomi, Yutaka Higo
Принадлежит: Sony Corp

Disclosed herein is a storage element, including: a storage layer which has magnetization vertical to a film surface and in which a direction of the magnetization is changed in correspondence to information; a magnetization fixing layer which has magnetization vertical to a film surface becoming a reference of the information stored in the storage layer, which is composed of plural magnetic layers, and which has a multilayered ferri-pin structure into which the plural magnetic layers are laminated one upon another through a non-magnetic layer(s); and an insulating layer made of a non-magnetic material and provided between the storage layer and the magnetization fixing layer.

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Номер записи: 3
26-07-2012 дата публикации

Timing adjustment circuit for a memory interface and method of adjusting timing for memory interface

Номер: US20120188833A1
Автор: Hideaki Kito, Hiroaki Iijima, Satoshi Ota, Shigehiro Tsuchiya, Yosuke Yamahara
Принадлежит: Toshiba Corp

According to one embodiment, a timing adjustment circuit for a memory interface is presented. The circuit is provided with a gate circuit, an original gate signal generation circuit, a high impedance prevention unit, an impedance control unit and a gate leveling circuit. The gate circuit performs gating of a data strobe signal outputted from a memory. The original gate signal generation circuit generates an original gate signal based on information of a read latency and a burst length. The high impedance prevention unit to prevent the data strobe signal from being in a high impedance state. The impedance control unit controls execution and release of operation of the high impedance prevention unit. The gate leveling circuit outputs a timing adjusted gate signal to the gate circuit based on the original gate signal and the data strobe signal.

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Номер записи: 4
29-11-2012 дата публикации

Advanced memory device having improved performance, reduced power and increased reliability

Номер: US20120300563A1
Автор: Charles A. Kilmer, Daniel M. Dreps, George L. Chiu, Hillery C. Hunter, Kevin C. Gower, Kyu-Hyoun Kim, Paul W. Coteus, Warren E. Maule
Принадлежит: International Business Machines Corp

An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

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Номер записи: 5
14-02-2013 дата публикации

Semiconductor device and semiconductor memory device

Номер: US20130039136A1
Автор: Soichiro Yoshida
Принадлежит: Elpida Memory Inc

A semiconductor device includes a memory cell, a first bit line coupled to the memory cell, a second bit line, a first sense amplifier circuit including first and second transistors, the first transistor including a gate coupled to the first bit line, and the first and second transistors are coupled in series between the second bit line and a first voltage line, a temperature detection circuit configured to detect a temperature of the semiconductor device, and a control circuit configured to receive an output of the temperature detection circuit and supply a control signal to a gate of the second transistor.

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Номер записи: 6
28-02-2013 дата публикации

High speed multiple memory interface i/o cell

Номер: US20130049799A1
Автор: Cheng-Gang Kong, Dharmesh Bhakta, Hong-Him Lim, Todd Randazzo
Принадлежит: LSI Corp

A calibration circuit includes an amplifier, a current steering digital-to-analog converter (DAC), a comparator, a slew calibration network, and an on-die termination (ODT) network. The amplifier generally has a first input, a second input, and an output. The first input generally receives a reference signal. The current steering digital-to-analog converter (DAC) generally has a first input coupled to the output of the amplifier, a first output coupled to the second input of the amplifier, and a second output coupled to a circuit node. The comparator generally has a first input receiving the reference signal, a second input coupled to the circuit node, and an output at which an output of the calibration circuit may be presented. The slew calibration network is generally coupled to the circuit node and configured to adjust a slew rate of the calibration circuit. The on-die termination (ODT) network is generally coupled to the circuit node.

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Номер записи: 7
28-03-2013 дата публикации

Memory storage device, memory controller, and temperature management method

Номер: US20130080680A1
Автор: Chien-Hua Chu
Принадлежит: Phison Electronics Corp

A temperature management method suitable for a memory storage device having a rewritable non-volatile memory module and a memory controller used for controlling the rewritable non-volatile memory module are provided. The temperature management method includes detecting and determining whether the hot-spot temperature of the memory storage device is higher than a predetermined temperature; and when affirmative, making the memory controller execute a cooling process, so as to reduce the hot-spot temperature of the memory storage device. Accordingly, the problem of heat buildup of the (rewritable non-volatile) memory storage device can be mitigated, as well as the problems of data loss and device aging of the (rewritable non-volatile) memory storage device.

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Номер записи: 8
04-04-2013 дата публикации

TEMPERATURE DETECTION CIRCUIT OF SEMICONDUCTOR MEMORY APPARTUS

Номер: US20130083616A1
Автор: Lee Je-Yoon, LEE Jong Chern
Принадлежит: HYNIX SEMICONDUCTOR INC.

A temperature detection circuit of a semiconductor memory apparatus includes a fixed period oscillator, a temperature variable signal generating unit and a counting unit. The oscillator is configured to generate a fixed period oscillator signal when an enable signal is enabled. The temperature variable signal generating unit is configured to generate a temperature variable signal whose enable interval varies based on temperature variations, when the enable signal is enabled. The counting unit is configured to count the oscillator signal during the enable interval of the temperature variable signal to generate a temperature information signal. 1. A temperature detection circuit of a semiconductor memory apparatus comprising:a temperature variable signal generating unit configured to enable a temperature variable signal when an enable signal is enabled, and to charge a capacitor, and to discharge the capacitor when a voltage level of the capacitor is increased to above a reference voltage level, and to disable the temperature variable signal when the voltage level of the capacitor is decreased to below the reference voltage level; anda counting unit configured to count an oscillator signal during an enable interval of the temperature variable signal to generate a temperature information signal.2. The temperature detection circuit of claim 1 , wherein the temperature information signal includes a mufti-bit code.3. The temperature detection circuit of claim 2 , wherein the temperature variable signal generating unit includes:a charging unit configured to apply an external voltage to the capacitor to charge the capacitor when the enable signal is enabled; anda discharging unit configured to discharge the capacitor when the voltage level of the capacitor is increased to above the reference voltage level, andthe temperature variable signal generating unit is configured to enable the temperature variable signal when the enable signal is enabled, and to disable the ...

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Номер записи: 9
18-04-2013 дата публикации

Complementary Reference Method for High Reliability Trap-Type Non-Volatile Memory

Номер: US20130094299A1
Автор: Nori Ogura, Seiki Ogura, Tomoko Ogura
Принадлежит: Halo LSI Inc

Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.

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Номер записи: 10
23-05-2013 дата публикации

Power-up signal generation circuit

Номер: US20130127498A1
Автор: Kyoung Hwan Kwon
Принадлежит: SK hynix Inc

A power-up signal generation circuit includes a fixed level transition voltage generation unit, a variable level transition voltage generation unit, a comparison unit, and a selective output unit. The fixed level transition voltage generation unit is configured to generate a fixed level transition voltage changing at a constant level of an external voltage. The variable level transition voltage generation unit is configured to generate a variable level transition voltage changing at a level of an external voltage which varies depending on temperature. The comparison unit is configured to compare the level of the fixed level transition voltage with the level of the variable level transition voltage, and generate a selection signal. The selective output unit is configured to output the fixed level transition voltage or the variable level transition voltage as a power-up signal in response to the selection signal.

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Номер записи: 11
04-07-2013 дата публикации

Reducing power consumption of memory

Номер: US20130173944A1
Автор: Donald Evans, Richard Stephani, Ross Kohler, Ting Zhou
Принадлежит: LSI Corp

Described embodiments provide for a memory system having a transparent source bias (TSB) circuit. A monitor in the memory system monitors a process, temperature, and/or a leakage current of the memory. The system determines whether at least one of the monitored process, temperature, and leakage current reaches a corresponding threshold. The threshold is set based on a power budget of the memory. If the corresponding threshold is reached, the TSB is disabled and the memory operates at a relatively high speed. If the corresponding threshold is not reached, the TSB is enabled and the memory operates at a relatively law speed.

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Номер записи: 12
22-08-2013 дата публикации

Semiconductor memory device changing refresh interval depending on temperature

Номер: US20130215700A1
Автор: Akinobu Shirota, Kuninori Kawabata
Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit.

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Номер записи: 13
29-08-2013 дата публикации

Oscillator based on a 6T SRAM for measuring the Bias Temperature Instability

Номер: US20130222071A1
Автор: Ching-Te Chuang, Hao-I Yang, Kuen-Di Lee, Ming-Chien Tsai, Ming-Hsien Tu, Nan-Chun Lien, Shyh-Jye Jou, Wei Hwang, Wei-Chiang Shih, Yi-Wei Lin
Принадлежит: National Chiao Tung University NCTU

The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.

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Номер записи: 14
29-08-2013 дата публикации

NONVOLATILE MEMORY DEVICE HAVING ADJUSTABLE PROGRAM PULSE WIDTH

Номер: US20130223143A1
Автор: CHO Yongsung, Choi Kihwan, Park Il Han, SONG KIiwhan, Yoon Sangyong
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A method of programming a nonvolatile memory device comprises determining a temperature condition of the nonvolatile memory device, determining a program pulse period according to the temperature condition, supplying a program voltage to a selected word line using the program pulse period, and supplying a pass voltage to unselected word lines while supplying the program voltage to the selected word line. 1. A method of programming a nonvolatile memory device , comprising:determining a temperature condition of the nonvolatile memory device;determining a program pulse period according to the temperature condition;supplying a program voltage to a selected word line using the program pulse period; andsupplying a pass voltage to unselected word lines while supplying the program voltage to the selected word line.2. The method of claim 1 , further comprising increasing the program pulse period in response to a temperature decrease of the nonvolatile memory.3. The method of claim 1 , further comprising decreasing the program pulse period in response to a temperature increase of the nonvolatile memory device.4. The method of claim 1 , further comprising adjusting the program pulse period according to a physical location of the selected word line.5. The method of claim 4 , wherein a program pulse period determined where the selected word line is an uppermost word line adjacent to a bit line is shorter than a program pulse period determined where the selected word line is not the uppermost word line.6. The method of claim 1 , wherein the program pulse period determined according to a temperature variation becomes relatively shorter after a predetermined number of program loops.7. A nonvolatile memory device comprising:a memory cell array comprising memory cells arranged in word lines and bit lines;an address decoder configured to select one of the word lines of the memory cell array;a temperature code generator circuit configured to detect a current temperature of the ...

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Номер записи: 15
02-01-2014 дата публикации

Memory array with on and off-state wordline voltages having different temperature coefficients

Номер: US20140003164A1
Автор: John A. Fifield, Mark D. Jacunski
Принадлежит: International Business Machines Corp

Disclosed is a memory array structure, where a wordline driver selectively applies a high on-state voltage (VWLH) or a low off-state voltage (VWLL) to a wordline. VWLH has a slightly negative temperature coefficient so that it is regulated as high as the gate dielectric reliability limits allow, whereas VWLL has a substantially neutral temperature coefficient. To accomplish this, the wordline driver is coupled to one or more voltage regulation circuits. In one embodiment, the wordline driver is coupled to a single voltage regulation circuit, which incorporates a single voltage reference circuit having a single output stage that outputs multiple reference voltages. Also disclosed is a voltage reference circuit, which can be incorporated into the voltage regulation circuit of a memory array structure, as described, or, alternatively, into any other integrated circuit structure requiring voltages with different temperature coefficients. Also disclosed is a method of operating a memory array structure.

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Номер записи: 16
09-01-2014 дата публикации

Dynamic memory performance throttling

Номер: US20140013070A1
Автор: Brian Toronyi, Kenneth Shoemaker
Принадлежит: Intel Corp

Dynamic memory performance throttling. An embodiment of a memory device includes a memory stack including coupled memory elements; the memory elements including multiple ranks, the plurality of ranks including a first rank and a second rank, and a logic device including a memory controller. The memory controller is to determine an amount of misalignment between data signals relating to a read request for the first rank and a read request for the second rank, and, upon determining that misaligment between the first rank and the second rank is greater than a threshold, the memory controller is to insert a time shift between a data signal for the first rank and a data signal for the second rank.

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Номер записи: 17
09-01-2014 дата публикации

Dynamically Calibrated DDR Memory Controller

Номер: US20140013149A1
Автор: Jung Lee, Mahesh Goplan
Принадлежит: Uniquify Inc

A method for calibrating a DDR memory controller is described. The method provides an optimum delay for a core clock delay element to produce an optimum capture clock signal. The method issues a sequence of read commands so that a delayed version of a dqs signal toggles continuously. The method delays a core clock signal to sample the delayed dqs signal at different delay increments until a 1 to 0 transition is detected on the delayed dqs signal. This core clock delay is recorded as “A.” The method delays the core clock signal to sample the core clock signal at different delay increments until a 0 to 1 transition is detected on the core clock signal. This core clock delay is recorded as “B.” The optimum delay value is computed from the A and B delay values.

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Номер записи: 18
06-02-2014 дата публикации

Temperature based compensation during verify operations for non-volatile storage

Номер: US20140036601A1
Автор: Fanglin Zhang, Gerrit Jan Hemink, Hao Nguyen, Jong Park, Ken Oowada, Man Lung Mui, Seungpil Lee, Yingda Dong
Принадлежит: SanDisk Technologies LLC

A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.

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Номер записи: 19
13-03-2014 дата публикации

Adjusting bit-line discharge time in memory arrays based on characterized word-line delay and gate delay

Номер: US20140071775A1
Автор: Bijan Kumar Ghosh, Donald Albert Evans, Rasoju Veerabadra Chary, Richard John Stephani, Ronald Brian Steele
Принадлежит: LSI Corp

A memory tracking circuit controls discharge duration of a tracking bit-line based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. The tracking circuit (i) extends the discharge duration when one or more of (a) the propagation delay and (b) the transistor-based gate delay is shorter than an uncontrolled discharge duration of the tracking bit-line, and (ii) does not extend the discharge duration otherwise. Based on the discharge duration, the tracking circuit activates a reset signal that resets a clock-pulse generator to switch the memory from an access operation to a recess state. Controlling the discharge duration, and consequently the reset signal, based on the propagation delay and the gate delay allows the clock-pulse generator to adjust access times to account for the memory array configuration and process, temperature, and voltage conditions.

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Номер записи: 20
13-03-2014 дата публикации

Methods for operating a memory interface circuit including calibration for cas latency compensation in a plurality of byte lanes

Номер: US20140075146A1
Автор: Jung Lee, Mahesh Goplan
Принадлежит: Uniquify Inc

A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.

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Номер записи: 21
04-01-2018 дата публикации

WITHIN-DIE SPECIAL OSCILLATOR FOR TRACKING SRAM MEMORY PERFORMANCE WITH GLOBAL PROCESS VARIATION, VOLTAGE AND TEMPERATURE

Номер: US20180004689A1
Автор: Chen Nan, Hu Shih-Hsin Jason, MARFATIA Percy Tehmul, NARAYANAN Rajagopal
Принадлежит:

An apparatus includes a memory, a timing circuit configured to emulate a first operation of the memory to activate a second operation of the memory, a sensor configured to emulate a portion of the timing circuit, and a controller configured to adjust an operating parameter of the memory based on the sensor emulating the portion of the timing circuit. A method is presented. The method includes at least operating a timing circuit to emulate a first operation of the memory, activating a second operation of the memory based on the emulating the first operation of the memory, emulating, by a sensor, a portion of the timing circuit. Another apparatus is presented. The apparatus includes at least a memory, a timing circuit, and means for tracking a performance of the memory based on the timing circuit tracking a memory operation. 1. An apparatus , comprising:a memory;a timing circuit configured to emulate a first operation of the memory to activate a second operation of the memory;a sensor configured to emulate a portion of the timing circuit; anda controller configured to adjust an operating parameter of the memory based on the sensor emulating the portion of the timing circuit.2. The apparatus of claim 1 , wherein the sensor comprises a ring oscillator claim 1 , and the ring oscillator comprises at least one stage having a dummy bitline.3. The apparatus of claim 2 , wherein the at least one stage further comprises a voltage driver coupled to the dummy bitline.4. The apparatus of claim 3 , wherein the voltage driver comprises a pull-down device to pull down a voltage of the dummy bitline to emulate the timing circuit.5. The apparatus of claim 4 , wherein the voltage driver further comprises a pull-up device to charge the dummy bitline to emulate the timing circuit.6. The apparatus of claim 1 , wherein the sensor comprises a plurality of sensor timing settings claim 1 , and a timing of the sensor is based on the plurality of sensor timing settings.7. The apparatus of claim ...

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Номер записи: 22
04-01-2018 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING SEMICONDUCTOR DEVICE

Номер: US20180005687A1
Автор: Kawabe Yukihito
Принадлежит: FUJITSU LIMITED

A semiconductor device includes an oscillator that oscillates to generate a clock, a circuit that operates based on the clock generated by the oscillator, a temperature detector that detects the temperature of the circuit, a power detector that acquires, as a monitored power value, power consumed by the circuit, and a frequency controller that controls, when the temperature detected by the temperature detector exceeds a temperature threshold, the frequency of the clock of the oscillator so that the monitored power value matches target power that causes the temperature of the circuit to converge to a temperature higher than the temperature threshold. 1. A semiconductor device comprising:an oscillator that oscillates to generate a clock;a circuit that operates based on the clock generated by the oscillator;a temperature detector that detects the temperature of the circuit;a power detector that acquires, as a monitored power value, power consumed by the circuit; anda frequency controller that controls, when the temperature detected by the temperature detector exceeds a temperature threshold, the frequency of the clock of the oscillator so that the monitored power value matches target power that causes the temperature of the circuit to converge to a temperature higher than the temperature threshold.2. The semiconductor device according to claim 1 ,wherein the frequency controller includesa power estimator that estimates, based on the monitored power value, a base power value corresponding to the temperature of the circuit when the temperature detected by the temperature detector matches the temperature threshold, anda frequency determiner that determines the frequency of the clock so that the target power is equal to or higher than the base power value and equal to or lower than the monitored power value acquired when the temperature detected by the temperature detector exceeds the temperature threshold.3. The semiconductor device according to claim 2 ,wherein the ...

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Номер записи: 23
20-01-2022 дата публикации

Semiconductor memory device

Номер: US20220020436A1
Автор: Hyung Jin Choi, Sung Hyun Hwang
Принадлежит: SK hynix Inc

A semiconductor memory device includes a memory cell array, a page buffer, a control logic, and a voltage generator. The memory cell array includes memory cells. The page buffer is connected to the memory cells through a bit line and configure to read data of the memory cells. The control logic generates control signals for controlling the page buffer. The voltage generator generates activation voltages of the control signals. The page buffer includes a first transistor between the bit line and a first node, a second transistor between a power voltage and a second node, a third transistor between the first node and the second node, a fourth transistor between the second node and a third node, and a fifth transistor between the first node and the third node. The voltage generator controls a first control signal controlling the fifth transistor based on temperature of the semiconductor memory device.

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Номер записи: 24
11-01-2018 дата публикации

SEMICONDUCTOR DEVICE HAVING TEMPERATURE SENSOR CIRCUIT THAT DETECTS A TEMPERATURE RANGE UPPER LIMIT VALUE AND A TEMPERATURE RANGE LOWER LIMIT VALUE

Номер: US20180010968A1
Автор: Walker Darryl G.
Принадлежит:

A method can include, in response to a power supply voltage transition, setting a temperature window to a first temperature range by operation of a temperature circuit formed on a semiconductor device. In response to a temperature of the semiconductor device being determined to be outside of the first temperature range, changing the temperature range of the temperature window until the temperature of the semiconductor device is determined to be within the temperature window. 1. A method of operating a semiconductor device , comprising:in response to a power supply voltage transitioning to at least a first potential, setting a temperature window to a first temperature range by operation of a temperature circuit formed on the semiconductor device; andin response to a temperature of the semiconductor device being determined to be outside of the first temperature range, changing the temperature range of the temperature window until the temperature of the semiconductor device is determined to be within the temperature window.2. The method of claim 1 , wherein:the semiconductor device is configured to set the temperature window to any of a plurality of temperature ranges in which the semiconductor device can operate.3. The method of claim 2 , wherein:at least one of the temperature ranges overlaps a portion of another of the temperature ranges.4. The method of claim 3 , wherein:the temperature ranges include a highest temperature range, a lowest temperature range, and a plurality of intermediate temperature ranges, each intermediate temperature range overlapping a portion of an adjacent temperature range.5. The method of claim 2 , wherein:the first temperature range is about midway between the highest and lowest of the plurality of temperature ranges.6. The method of claim 1 , further including:changing the temperature range of the temperature window includes incrementing a count value by operation of a counter circuit.7. The method of claim 1 , wherein:after the ...

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Номер записи: 25
10-01-2019 дата публикации

TEMPERATURE RELATED ERROR MANAGEMENT

Номер: US20190012226A1
Автор: Muchherla Kishore K., Ratnam Sampath K.
Принадлежит:

Apparatuses and methods for temperature related error management are described. One or more apparatuses for temperature related error management can include an array of memory cells and a write temperature indicator appended to at least one predetermined number of bytes of the stored data in the array of memory cells. The apparatuses can include a controller configured to determine a numerical temperature difference between the write temperature indicator and a read temperature indicator and determine, from stored operations, an error management operation for the stored data based, at least in part, on comparison of the numerical temperature difference to a temperature difference threshold. 1. An apparatus , comprising:an array of memory cells;a write temperature indicator appended to at least one predetermined number of bytes of stored data in the array of memory cells; and determine an error rate during a read of data stored in the array of memory cells;', 'determine a temperature difference between the write temperature indicator and a read temperature indicator; and', 'retire a number of memory cells associated with storage of the stored data when the determined error rate is at least equal to a stored retirement error threshold and the determined error rate exceeds an error rate expected at a stored temperature difference threshold., 'a controller configured to2. The apparatus of claim 1 , wherein the apparatus is further configured to include a component to receive an ambient temperature measurement to enable storage of the read temperature indicator in a timeframe associated with a read of stored data.3. The apparatus of claim 1 , wherein the apparatus is further configured to store claim 1 , in the controller claim 1 , a write temperature stamp for the at least one predetermined number of bytes of data claim 1 , wherein the write temperature stamp indicates at least one of:an ambient temperature range in a timeframe in which the data is written for storage; ...

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Номер записи: 26
09-01-2020 дата публикации

MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES

Номер: US20200012332A1
Автор: Fuller Andrew M., Palmer Robert E., Poulton John W., Ware Frederick A.
Принадлежит:

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices. 120-. (canceled)21. A memory controller component comprising:a clock transmitter to transmit a first clock signal to a dynamic random access memory device (DRAM), the DRAM having (i) command/address receive circuitry to receive read commands and write commands, (ii) read-data transmit circuitry to transmit, in response to the read commands, read data using the first clock signal, and (iii) write-data receive circuitry to sample, in response to the write commands, write data using the first clock signal;a command/address transmitter to transmit the read commands and the write commands to the DRAM in response to a second clock signal;a write-data transmitter to transmit the write data to the DRAM in response to a third clock signal;a read-data receiver to sample the read data transmitted by the DRAM in response to a fourth clock signal; and phase control circuitry to independently offset phases of the third and fourth clock signals relative to the first clock signal and', 'circuitry to generate the second clock signal at a lower frequency than the third and fourth clock signals; and', 'clock-pause circuitry to halt transmission of the first clock signal to the DRAM during a first interval to conserve power and to re- ...

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Номер записи: 27
11-01-2018 дата публикации

Semiconductor storage device

Номер: US20180012640A1
Автор: Kosuke Hatsuda, Yoshiaki Osada
Принадлежит: Toshiba Memory Corp

According to one embodiment, a semiconductor storage device includes a memory cell, a bit line connected to the memory cell, and a sense circuit connected to the bit line, wherein the sense circuit includes a first transistor with a first end connected to the bit line, a second transistor with a first end connected to a second end of the first transistor, a third transistor with a first end connected to the bit line, a fourth transistor with a first end connected to a second end of the third transistor, and an amplifier connected to a second end of the second transistor and to a second end of the fourth transistor.

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Номер записи: 28
11-01-2018 дата публикации

MEMORY CONTROLLER

Номер: US20180012644A1
Автор: Hampel Craig E., Perego Richard E., Tsern Ely K., Ware Frederick A.
Принадлежит:

A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM. 120-. (canceled)21. A memory controller component comprising: first circuitry to transmit a write command to a dynamic random access memory device (DRAM), the write command to be sampled by the DRAM in response to a first timing signal; and', 'second circuitry to transmit first write data to the DRAM, the first write data to be sampled by the DRAM in response to a second timing signal; and, 'a signaling interface, includingadjustment circuitry to offset the first and second timing signals from one another at the signaling interface to compensate for skew between their arrival times at the DRAM.22. The memory controller of wherein the adjustment circuitry to offset the first and second timing signals from one another comprises circuitry to offset a phase of the second timing signal from a phase of the first timing signal.23. The memory controller of wherein the adjustment circuitry to offset the first and second timing signals from one another comprises circuitry to offset the first and second timing signals at the signaling interface by a time interval that corresponds to a difference in respective propagation times claim 21 , from the memory controller component to the DRAM claim 21 , of the first and second timing signals.24. The memory controller of wherein the second circuitry to transmit the first write data to the DRAM comprises circuitry to output at least part of the first write data onto an external data signaling link at one or more times indicated by the second timing signal.25. The memory controller of wherein the circuitry to ...

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Номер записи: 29
11-01-2018 дата публикации

Memory including Bi-polar Memristor

Номер: US20180012654A1
Автор: Chia Leong Yap, GE NING, Koh Ser Chia, Wong Wai Mun
Принадлежит: Hewlett-Packard Development Company, L.P.

A memory cell includes an input coupled to a read line, an output coupled to a circuit ground, a bi-polar memristor, and at least one address switch coupled to an address line to select the memory cell. A memory includes the bi-polar memristor and a one-way current conducting device, wherein the one-way current conducting device is positioned between the memristor cell output and the circuit ground, or between the read line and the memristor cell input. 1. A memory circuit including:a memory cell including an input coupled to a read line, an output coupled to a circuit ground, a bi-polar memristor and at least one address switch coupled to an address line to select the memory cell; anda one-way current conducting device to prevent resetting of the bi-polar memristor;wherein the one-way current conducting device is positioned between the memristor cell output and the circuit ground, or between the read line and the memristor cell input.2. The memory circuit of wherein the one-way current conducting device is a diode.3. The memory circuit of wherein a breakdown voltage of the diode is at least 10V.4. The memory circuit of wherein the one-way current conducting device is a transistor including a gate and a drain claim 1 , wherein the gate of the transistor is coupled to the drain of the transistor.5. The memory circuit of wherein the memory circuit includes a plurality of memory cells claim 1 , each memory cell being connected to a common line to a circuit ground and wherein the one-way current conducting device is positioned on the common line to the circuit ground to prevent resetting of the plurality of memory cells.6. The memory circuit of wherein the memory circuit includes a plurality of blocks claim 5 , each block including a plurality of bi-polar memristors claim 5 , each bi-polar memristor associated with a respective column switch and all bi-polar memristors in a block sharing a common row switch;wherein a plurality of row switches connect to a common line to ...

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Номер записи: 30
14-01-2021 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20210012816A1
Автор: Atsumi Tomoaki, Kato Kiyoshi, ONUKI Tatsuya, Yamazaki Shunpei
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

A semiconductor device with a high on-state current and high operating speed is provided. The semiconductor device includes a transistor and a first circuit. The transistor includes a first gate and a second gate, and the first gate and the second gate include a region where they overlap each other with a semiconductor layer therebetween. The first circuit includes a temperature sensor and a voltage control circuit. The temperature sensor has a function of obtaining temperature information and outputting the temperature information to the voltage control circuit. The voltage control circuit has a function of converting the temperature information into a control voltage. The first circuit applies the control voltage to the second gate. 1. A semiconductor device comprising:a transistor and a first circuit,wherein the transistor comprises a first gate and a second gate,wherein the first gate and the second gate overlap each other with a semiconductor layer therebetween,wherein the first circuit comprises a temperature sensor and a voltage control circuit,wherein the temperature sensor is configured to obtain temperature information and output the temperature information to the voltage control circuit,wherein the voltage control circuit is configured to convert the temperature information into a control voltage, andwherein the first circuit applies the control voltage to the second gate.2. The semiconductor device according to claim 1 ,wherein the voltage control circuit is configured to convert the temperature information into the control voltage according to a conversion formula.3. The semiconductor device according to claim 1 ,wherein the voltage control circuit comprises a microcomputer or an amplifier.4. The semiconductor device according to claim 1 ,wherein the semiconductor layer comprises a metal oxide.5. The semiconductor device according to claim 1 , further comprising a second circuit claim 1 ,wherein the second circuit applies a negative voltage to the ...

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Номер записи: 31
14-01-2021 дата публикации

APPARATUSES INCLUDING TEMPERATURE-BASED THRESHOLD VOLTAGE COMPENSATED SENSE AMPLIFIERS AND METHODS FOR COMPENSATING SAME

Номер: US20210012818A1
Автор: Ahmad Galaly, Hawkins Jonathan, Lam Boon Hor, Major Karl L.
Принадлежит: MICRON TECHNOLOGY, INC.

Systems, methods, and apparatuses for temperature-compensated operation of electronic devices are described. For example, an apparatus for performing voltage compensation on a sense amplifier based on temperature may include a sense amplifier control circuit coupled to the sense amplifier to provide a compensation pulse to the sense amplifier, wherein the sense amplifier operates in a voltage compensation phase during the compensation pulse. The apparatus may determine the compensation pulse responsive to a voltage compensation duration signal that is based on the operating temperature of the apparatus. The voltage compensation occurs when there is no activate command immediately before or immediately after so that compensation duration change do not happen during an activate command from the command decoder. 1. An apparatus , comprising:a sense amplifier control circuit coupled to at least one sense amplifier and configured to provide a bit line compensation signal to cause the sense amplifier to perform a voltage compensation for a duration of time, wherein the duration of time is based on an operating temperature of the apparatus.2. The apparatus of claim 1 , wherein the sense amplifier control circuit includes a threshold voltage compensation duration circuit configured to receive the bit line compensation signal at an active logic level and deactivate the bit line compensation signal based on a delay signal.3. The apparatus of claim 2 , wherein the threshold voltage compensation duration circuit comprises a latch circuit.4. The apparatus of further comprising a first switching circuit coupled to the threshold voltage compensation duration circuit and configured to provide the delay signal to the threshold voltage compensation duration circuit from one of a plurality of delay signals responsive to a threshold voltage compensation duration signal.5. The apparatus of further comprising a second switching circuit coupled to the first switch circuit to select one of ...

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Номер записи: 32
03-02-2022 дата публикации

Circuit Device And Real-Time Clock Device

Номер: US20220035398A1
Автор: MATSUZAKI Sho
Принадлежит:

A circuit device includes a first power supply line to which a first power supply voltage is supplied, a second power supply line to which a second power supply voltage is supplied, a third power supply line, a power supply circuit, a predetermined circuit, a first power-on reset circuit, a second power-on reset circuit, and a reset control circuit. When a first power-on reset signal and a second power-on reset signal become a reset release level, the reset control circuit sets a third power-on reset signal output to at least a part of the predetermined circuit to a reset release level. 1. A circuit device comprising:a first power supply line to which a first power supply voltage is supplied;a second power supply line to which a second power supply voltage is supplied;a third power supply line;a power supply circuit that is coupled to the first power supply line and the second power supply line, performs selection of the first power supply voltage or the second power supply voltage, and outputs a third power supply voltage based on the selected power supply voltage to the third power supply line;a predetermined circuit that is operated by the third power supply voltage;a first power-on reset circuit that is coupled to the first power supply line and outputs a first power-on reset signal based on the first power supply voltage;a second power-on reset circuit that is coupled to the third power supply line and outputs a second power-on reset signal based on the third power supply voltage; anda reset control circuit that sets a third power-on reset signal output to at least a part of the predetermined circuit to a reset release level when the first power-on reset signal and the second power-on reset signal become a reset release level.2. The circuit device according to claim 1 , whereinthe predetermined circuit includes a memory and a logic circuit that performs processing based on data from the memory, andthe third power-on reset signal is input to the memory.3. The ...

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Номер записи: 33
21-01-2016 дата публикации

DISTRIBUTED COMPUTING WITH PHASE CHANGE MATERIAL THERMAL MANAGEMENT

Номер: US20160019937A1
Автор: Arora Manish, Jayasena Nuwan, Loh Gabriel H., Schulte Michael J.
Принадлежит:

Various apparatus and methods using phase change materials are disclosed. In one aspect, a method of operating a computing device that has a first semiconductor chip with a first phase change material and a second semiconductor chip with a second phase change material is provided. The method includes determining if the first semiconductor chip phase change material has available thermal capacity. If the first semiconductor chip phase change material has available thermal capacity then the first semiconductor chip is instructed to operate in sprint mode. The first semiconductor chip is instructed to perform a first computing task while in sprint mode.

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Номер записи: 34
17-01-2019 дата публикации

MEMORY THROTTLING

Номер: US20190018474A1
Автор: BACCHUS Reza, BENEDICT Melvin, Pope Eric L
Принадлежит:

An example memory device comprises at least one memory region; and a controller to determine exceeding of a throttling threshold and to throttle processing of access requests for the at least one memory region. 1. A memory device , comprising:at least one memory region; anda controller to determine when a throttling threshold has been exceeded, the con being to throttle processing of access requests for the at least one memory region.2. The memory device of claim 1 , wherein the memory device is a dynamic random access memory (DRAM) device.3. The memory device of claim 1 , wherein the controller is to receive access requests from an external memory controller.4. The memory device of claim 1 , wherein the controller comprises at least one of:a thermal portion to determine if a temperature threshold has been exceeded and to facilitate throttling of access requests for the at least one memory region when the temperature threshold has been exceeded;a quality-of-service (QoS) portion to determine if an access threshold for a first memory region of the at least one memory region has been exceeded and to facilitate throttling of access requests for the first memory region when the access threshold for the first memory region has been exceeded; ora power control portion to determine if a power draw threshold for the memory device has been exceeded and to facilitate throttling of access requests for the at least one memory region when the power draw threshold has been exceeded.5. The memory device of claim 4 , wherein the QoS portion includes a separate counter for each of the at least one memory region.6. The memory device of claim 1 , wherein the controller is at least one of hardware claim 1 , software or firmware.7. A method claim 1 , comprising:receiving, by a memory device, a memory access request from a memory controller for access to at least one memory region of the memory device;determining, by a controller of the memory device, when a throttling threshold ...

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Номер записи: 35
17-01-2019 дата публикации

PRECHARGE CIRCUIT, AND MEMORY DEVICE AND SRAM GLOBAL COUNTER USING PRECHARGE CIRCUIT

Номер: US20190019560A1
Автор: Jeong Hoesam
Принадлежит:

A precharge circuit includes: a precharge time controller suitable for generating a precharge time control signal based on a threshold voltage of a transistor; a precharge control signal generator suitable for generating a precharge control signal activated during a predetermined period based on the precharge time control signal from the precharge time controller; and a precharger suitable for precharging a bit line and a bit line bar during the predetermined period based on the precharge control signal from the precharge control signal generator. 1. A precharge circuit comprising:a precharge time controller suitable for generating a precharge time control signal based on a threshold voltage of a transistor;a precharge control signal generator suitable for generating a precharge control signal activated during a predetermined period based on the precharge time control signal from the precharge time controller; anda precharger suitable for precharging a bit line and a bit line bar during the predetermined period based on the precharge control signal from the precharge control signal generator.2. The precharge circuit according to claim 1 , wherein the precharge time controller comprises:a PVT sensing circuit suitable for sensing at least one of process, voltage, and temperature (PVT) conditions applied to a memory element and generating a PVT condition sensing result signal; anda precharge time control signal generating circuit suitable for generating the precharge time control signal based on the PVT condition sensing result signal from the PVT sensing circuit.3. The precharge circuit according to claim 2 , wherein the PVT sensing circuit comprises:a first NMOS transistor having a drain terminal to which a power supply voltage is applied, a gate terminal to which an enable signal is applied, and a source terminal which is coupled to a first node;a first PMOS transistor having a source terminal which is coupled to the first node, and a gate terminal and a drain ...

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Номер записи: 36
16-01-2020 дата публикации

DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD

Номер: US20200020381A1
Автор: GOPALAN Mahesh, IYER Venkat, WU David
Принадлежит:

In accordance with one embodiment, a computer-implemented method is provided, comprising: configuring code to cause at least part of hardware to operate as a double data rate (DDR) memory controller and to produce one or more capture clocks, where: a timing of at least one of the one or more capture clocks is based on a first clock signal of a first clock, the first clock signal is a core clock signal or a signal derived from at least the core clock signal, the at least one of the one or more capture clocks is used to time a read data path, the at least one of the one or more capture clocks is used to capture read data into a clock domain related to a second clock, the first clock and the second clock being related in timing such that at least one of: the second clock is derived from the first clock, or the first clock is derived from the second clock; and providing access to the code. 1. A computer-implemented method , comprising: a timing of at least one of the one or more capture clocks is based on a first clock signal of a first clock,', 'the first clock signal is a core_clock signal or a signal derived from at least the core_clock signal,', 'the at least one of the one or more capture clocks is used to time a read data path,', 'the at least one of the one or more capture clocks is used to capture read data into a clock domain related to a second clock, the first clock and the second clock being related in timing such that at least one of: the second clock is derived from the first clock, or the first clock is derived from the second clock., 'configuring code to cause at least part of hardware to operate as a double data rate (DDR) memory controller and to produce one or more capture clocks, where2. The method of claim 1 , and comprising further configuring the code claim 1 , where the code causes the at least part of the hardware to operate such that the at least one of the one or more capture clocks is produced by a capture clock generation circuit.3. The ...

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Номер записи: 37
16-01-2020 дата публикации

RRAM VOLTAGE COMPENSATION

Номер: US20200020397A1
Автор: CHIH Yu-Der, CHOU Chung-Cheng, Lai Chien-An
Принадлежит:

A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line. 1. A memory device , comprising:an array of resistive memory cells;a plurality of word lines connected to the array of resistive memory cells;a voltage compensation controller configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines; anda word line driver configured to apply the determined word line voltage to the selected word line.2. The memory device of claim 1 , wherein the voltage compensation controller is configured to determine the word line voltage based on the selected word line.3. The memory device of claim 2 , further comprising:an I/O block connected to the plurality resistive memory cells, wherein the voltage compensation controller varies the determined word line voltage based on a distance of the selected word line from the I/O block.4. The memory device of claim 3 , wherein the determined word line voltage is selected from a predetermined number of word line voltages by segmenting the array of resistive memory cells into a plurality of predetermined segments based on the location from the I/O block claim 3 , wherein a first predetermined word line voltage corresponding to a segment that is farther from the I/O block is lower than a second predetermined word line voltage corresponding to a segment that is closer to the I/O block.5. The memory device of claim 1 , wherein the voltage compensation controller is configured to determine the word line voltage based on a temperature of the array of resistive memory cells.6. The memory device of claim 5 , wherein the voltage compensation controller is configured to ...

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Номер записи: 38
21-01-2021 дата публикации

Non-volatile memory devices and program methods thereof

Номер: US20210020254A1
Автор: Jinwoo Park, Sang-Wan Nam, Seongjin Kim, Wandong Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A program method of a non-volatile memory device, the non-volatile memory device including a cell string having memory cells stacked perpendicular to a surface of a substrate, the method includes performing a first program phase including programming a first memory cell connected to a first word line and applying a first pass voltage to other word lines above or below the first word line, and performing a second program phase including programming a second memory cell after the first memory cell is completely programmed, the second memory cell being connected to a second word line closer to the substrate than the first word line, applying a second pass voltage to a first word line group below the second word line and applying a third pass voltage to a second word line group above the second word line, the second pass voltage being lower than the third pass voltage.

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Номер записи: 39
21-01-2021 дата публикации

NON-VOLATILE MEMORY DEVICES AND PROGRAM METHODS THEREOF

Номер: US20210020256A1
Автор: KIM Seongjin, Kim Wandong, NAM Sang-Wan, PARK Jinwoo
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A program method of a non-volatile memory device, the non-volatile memory device including a peripheral circuit region and a memory cell region including a cell substrate and a cell string having memory cells stacked perpendicular to a surface of a cell substrate, the method includes performing a first program phase including programming a first memory cell connected to a first word line and applying a first pass voltage to other word lines above or below the first word line, and performing a second program phase including programming a second memory cell being connected to a second word line closer to the cell substrate, applying a second pass voltage to a first word line group below the second word line and applying a third pass voltage to a second word line group above the second word line, the second pass voltage being lower than the third pass voltage. 1. A program method of a non-volatile memory device , the non-volatile memory device including a peripheral circuit region and a memory cell region vertically connected to the peripheral circuit region , the peripheral circuit region including at least one first metal pad , the memory cell region including a cell substrate , a cell string , and at least one second metal pad directly connected with the at least one first metal pad , respectively , and the cell string in which a plurality of memory cells are stacked in a direction perpendicular to a surface of a cell substrate , the method comprising:performing a first program phase including programming a first memory cell among the plurality of memory cells, the first memory cell being connected to a first word line among a plurality of word lines of the cell string, the first program phase including applying a first pass voltage from the peripheral circuit region to other word lines among the plurality of word lines above or below the first word line with respect to the cell substrate; andperforming a second program phase including programming a second memory ...

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Номер записи: 40
23-01-2020 дата публикации

Power supply device, power supply control method, and storage device

Номер: US20200025834A1
Автор: Wataru Okamoto
Принадлежит: Toshiba Memory Corp

According to one embodiment, a power supply device includes a power supply circuit including circuit blocks and configured to generate power supply voltages based on an external power supply, detectors that detect failures of the circuit blocks, a nonvolatile memory, and a controller that stops an operation of the power supply circuit when any of the detectors detects the failure of any of the circuit blocks, and writes failure information of the power supply circuit into the nonvolatile memory. The failure information includes information indicating a type of the failure which has occurred and a circuit block among the circuit blocks in which the failure has occurred.

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Номер записи: 41
10-02-2022 дата публикации

DEBUGGING MEMORY DEVICES

Номер: US20220044752A1
Автор: Kim Junam
Принадлежит:

Methods, systems, and devices for debugging memory devices are described. A memory system may be an example of a multichip package (MCP) that includes at least one volatile memory device and at least one non-volatile memory device. In some examples, errors may occur at the volatile memory device, and data associated with the errors may be stored to the non-volatile memory device. To store the data, access operations being performed on the non-volatile memory may be interrupted (e.g., paused) and the data may be stored to the non-volatile memory before the access operations are resumed. The stored data may be accessed (e.g., by a host device) for use during an error correction operation. 1. A system , comprising:a first memory subsystem comprising a set of dynamic random access memory (DRAM) devices having a first memory interface for memory access commands associated with the set of DRAM devices, the first memory subsystem coupled with a first signal path and a second signal path; anda second memory subsystem comprising a controller and a set of NAND devices, the second memory subsystem within a single memory system package with the first memory subsystem, wherein the controller comprises a second memory interface for memory access commands associated with the set of NAND devices and is coupled with the first signal path and the second signal path, the controller configured to receive signaling via the first and second signal paths indicating one or more errors associated with the set of DRAM devices and to store data associated with the one or more errors to the set of NAND devices.2. The system of claim 1 , wherein the controller is configured to:interrupt processing commands associated with the set of NAND devices to obtain the signaling via the second signal path based at least in part on the signaling received via the first signal path.3. The system of claim 2 , wherein the controller is configured to:receive at least one additional memory access command ...

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Номер записи: 42
10-02-2022 дата публикации

Read Model of Memory Cells using Information Generated during Read Operations

Номер: US20220044756A1
Автор: Alhussien AbdelHakim S., Fitzpatrick James, Khayat Patrick Robert, Parthasarathy Sivagnanam
Принадлежит:

A memory sub-system configured to generate or update a model for reading memory cells in a memory device. For example, in response to a processing device of a memory sub-system transmitting to a memory device read commands that are configured to instruct the memory device to retrieve data from a group of memory cells formed on an integrated circuit die in the memory device, the memory device may measure signal and noise characteristics of the group of memory cells during execution of the read commands. Based on the signal and noise characteristics the memory sub-system can generate or update, measured during the execution of the read commands a model of changes relevant to reading data from the group of memory cells. The changes can be a result of damage, charge loss, read disturb, cross-temperature effect, etc. 1. A device , comprising:an integrated circuit die;memory cells formed on the integrated circuit die; and measure signal and noise characteristics of a memory cell group, among the memory cells, to calibrate read voltages of the memory cell group; and', 'generate, based at least in part on the signal and noise characteristics of the memory cell group, a model of changes of the group of memory cells., 'a logic circuit configured to, in response to commands to read data from the memory cells,'}2. The device of claim 1 , comprising:a calibration circuit configured to apply test voltages to the memory cell group to measure the signal and noise characteristics of the memory cell group.3. The device of claim 2 , wherein the logic circuit is configured to generate the model by updating a prior model.4. The device of claim 2 , wherein the logic circuit is configured to generate the model based on a history of the changes reflected at least in part in the signal and noise characteristics of the memory cell group measured during execution of the commands configured to read data from the memory cell groups.5. The device of claim 4 , wherein the logic circuit is ...

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Номер записи: 43
24-01-2019 дата публикации

Storage system and method for die-based data retention recycling

Номер: US20190027193A1
Автор: James M. Higgins, Jeff Whaley, Jingfeng Yuan
Принадлежит: Western Digital Technologies Inc

The subject technology performs the following in a storage system including memory dies, where each memory die includes its own temperature sensor. The subject technology determines a temperature of each of the memory dies based on a temperature reading from each memory die's temperature sensor. The subject technology determines whether data is hot data or cold data, where hot data is more likely to be changed after it is written than cold data. In response to determining that the data is hot data, the subject technology stores the data in a memory die with a relatively higher temperature than another one of the memory dies. Further, in response to determining that the data is cold data, the subject technology stores the data in a memory die with a relatively cooler temperature than another one of the memory dies.

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Номер записи: 44
24-01-2019 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20190027223A1
Автор: YANAGIDAIRA Kosuke
Принадлежит:

A semiconductor memory device includes a first circuit configured to process data received from and transmitted to an external controller, a second circuit configured to execute calibration on the first circuit, and a control circuit configured to control the second circuit to execute the calibration on the first circuit in response to a calibration command received from the external controller. In response to a first calibration command, the control circuit controls the second circuit to execute the calibration on the first circuit. In response to a second calibration command that is received after the first calibration command, the control circuit controls the second circuit to execute the calibration on the first circuit if a first condition is met and to not execute the calibration on the first circuit if the first condition is not met. 1. A semiconductor memory device comprising:a first circuit configured to process data received from and transmitted to an external controller;a second circuit configured to execute calibration on the first circuit; anda control circuit configured to control the second circuit to execute the calibration on the first circuit in response to a calibration command received from the external controller, whereinin response to a first calibration command, the control circuit controls the second circuit to execute the calibration on the first circuit,in response to a second calibration command that is received after the first calibration command, the control circuit controls the second circuit to execute the calibration on the first circuit if a first condition is met and to not execute the calibration on the first circuit if the first condition is not met, the first condition being met when a change in a temperature of the first circuit exceeds a threshold, andthe second circuit includes a temperature measurement circuit that measures a first temperature of the first circuit at a time of the first calibration command and a second ...

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Номер записи: 45
23-01-2020 дата публикации

SELECTABLE TRIM SETTINGS ON A MEMORY DEVICE

Номер: US20200027517A1
Автор: Feeley Peter, Lowrance Daniel L., Thiruvengadam Aswin
Принадлежит:

The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells. 1. An apparatus , comprising:an array of memory cells; and store a number of sets of trim settings, wherein the number of sets of trim settings are each configured to provide particular operational characteristics for the array of memory cells; and', 'select a particular set of trims settings of the number of sets of trim settings including particular trim setting parameters based on desired operational characteristics for the array of memory cells., 'a controller, wherein the controller is coupled to the array of memory cells and includes control circuitry configured to2. The apparatus of claim 1 , wherein the operational characteristics include programming operation speed for the array of memory cells.3. The apparatus of claim 1 , wherein the operational characteristics include life span for the array of memory cells.4. The apparatus of claim 1 , wherein the operational characteristics include data retention characteristics for the array of memory cells.5. The apparatus of claim 1 , wherein the operational characteristics include storage density characteristics for the array of memory cells.6. The apparatus of claim 1 , the particular set of trim settings is selected by a host.7. An apparatus claim 1 , comprising:an array of memory cells; and 'operate the array of memory cells using a particular set of trims settings, including particular trim setting parameters, selected based on desired operational characteristics for the array of memory cells, wherein the particular trim setting parameters include a number of bits per cell.', 'a controller, wherein the controller is coupled to the array of memory cells and includes control ...

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Номер записи: 46
28-01-2021 дата публикации

MEMORY CONTROLLER

Номер: US20210027825A1
Автор: Hampel Craig E., Perego Richard E., Tsern Ely K., Ware Frederick A.
Принадлежит:

A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM. 120-. (canceled)21. A memory controller component comprising: a first timing signal that requires a first time interval to propagate to the memory component;', 'write data to be sampled by the memory component synchronously with respect to the first timing signal;', 'a second timing signal that requires a second time interval to propagate to the DRAM; and', 'a write command, corresponding to the write data, to be sampled by the memory component synchronously with respect to the second timing signal; and, 'transmit circuitry to transmit to a memory componentcontrol circuitry to adjust transmit timing of at least one of the first and second timing signals based on a difference between the first and second time intervals to render phase-aligned arrival of the first and second timing signals at the memory component.22. The memory controller component of wherein the second timing signal is a clock signal and the first timing signal is a strobe signal.23. The memory controller component of wherein the control circuitry to adjust transmit timing of at least one of the first and second timing signals to render phase-aligned arrival of the first and second timing signals at the memory component comprises circuitry to render alignment claim 21 , at the memory component claim 21 , between respective rising edges of the first and second timing signals.24. The memory controller component of wherein the control circuitry to adjust transmit timing of at least one of the first and second timing signals to render phase-aligned arrival of the first and second ...

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Номер записи: 47
28-01-2021 дата публикации

METHODS AND APPARATUS FOR SYNCHRONIZING COMMUNICATION WITH A MEMORY CONTROLLER

Номер: US20210027826A1
Автор: Best Scott C., Lambrecht Frank, Roberts David B., Warmke Richard E.
Принадлежит:

A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals. 1. (canceled)2. A memory controller comprising:an interface circuit to couple to a first memory device and a second memory device, the interface circuit including a first receiver circuit to receive a first read signal of a first phase from the first memory device and second read signal of a second phase from the second memory device;a first register to store a first receive state corresponding to the first memory device, the first receive state derived from the first phase; anda second register to store a second receive state corresponding to the second memory device, the second receive state derived from the second phase.3. The memory controller of claim 2 , wherein the first receive state represents a first offset from a clock signal and the second receive state represents a second offset from the clock signal.4. The memory controller of claim 3 , the interface circuit comprising a delay-locked loop to derive the first offset from and the second offset from the clock signal.5. The memory controller of claim 2 , wherein at least one of the first read signal and the second read signal comprises a strobe signal.6. The memory controller of claim 2 , wherein the interface circuit further includes transmitter circuits for transmitting first write data signals to the first memory device and second write data signals to the second memory device claim 2 , the first register stores a first transmitting timing state for the first write data signals claim 2 , and the second register stores a second transmitting timing ...

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Номер записи: 48
02-02-2017 дата публикации

Semiconductor device that writes temperature data for subsequent data reading

Номер: US20170030777A1
Автор: Daisuke Kimura, Hayato Masubuchi
Принадлежит: Toshiba Corp

A semiconductor device includes a substrate having a connector for connection with a host, a semiconductor memory device mounted on the substrate, a temperature sensor mounted on the substrate, and a controller mounted on the substrate. The controller is configured to write, in the semiconductor memory device, write data received through the connector together with temperature data representing temperature detected by the temperature sensor.

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Номер записи: 49
01-02-2018 дата публикации

RESISTANCE CHANGE MEMORY

Номер: US20180033475A1
Автор: Fujita Katsuyuki
Принадлежит: Toshiba Memory Corporation

A resistance change memory including a memory cell having a resistance change element; a reference voltage generating circuit which generates a reference adjustment voltage; a first transistor which has a source and a drain, the drain providing a reference current in accordance with the reference adjustment voltage; and a sense amplifier which compares a cell current flowing through the memory cell with the reference current flowing through the first transistor. The reference voltage generating circuit includes a second transistor having a gate coupled to a gate of the first transistor, the reference adjustment voltage changing in accordance with a temperature, and the first transistor is an n-channel MOS transistor, and operates in a linear region which changes in a current value in accordance with the reference adjustment voltage. 1. A resistance change memory comprising:a memory cell comprising a resistance change element;a reference voltage generating circuit which generates a reference adjustment voltage;a first transistor which has a source and a drain, the drain providing a reference current in accordance with the reference adjustment voltage; anda sense amplifier which compares a cell current flowing through the memory cell with the reference current flowing through the first transistor,wherein:the reference voltage generating circuit includes a second transistor having a gate coupled to a gate of the first transistor,the reference adjustment voltage changes in accordance with a temperature, andthe first transistor is an n-channel MOS transistor, and operates in a linear region which changes in a current value in accordance with the reference adjustment voltage.2. The resistance change memory according to claim 1 , wherein the reference voltage generating circuit increases the reference adjustment voltage as the temperature rises.3. The resistance change memory according to claim 1 , wherein the reference voltage generating circuit decreases the reference ...

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Номер записи: 50
31-01-2019 дата публикации

CACHE POLICY RESPONSIVE TO TEMPERATURE CHANGES

Номер: US20190033933A1
Автор: Anagani Chandra Sekhar, Bhat Santosh, Hur Ho Young, Kenchanpura Rohit S., Koppana Venkat Rohit, Pandya Nisarg, Sathappan Swaminathan
Принадлежит:

Embodiments of the present disclosure are directed towards a computer system with cache policy that may be modified in response to temperature changes. In some embodiments, the system may include a memory storage having a first storage device with a first response time, and a second storage device with a second response time that may be higher than the first response time. The system may include a cache policy module to facilitate execution of I/O requests to access the memory storage. The cache policy module may be configured to restrict access to at least a portion of the first storage device and provide access to the second storage device, in response to an increase of temperature of the first storage device above a threshold. Other embodiments may be described and/or claimed. 1. A computer system , comprising:a first storage device having a first response time, and a second storage device coupled with the first storage device, and having a second response time that is higher than the first response time; anda cache policy module to facilitate execution of input-output (I/O) requests to access the memory storage of the computer system, wherein the cache policy module is to restrict access to at least a portion of the first storage device and provide access to the second storage device, in response to an increase of temperature of the first storage device above a threshold.2. The computer system of claim 1 , wherein the first storage device comprises a cache of the second storage device.3. The computer system of claim 2 , wherein the second storage device comprises at least one of: a Serial Advanced Technology Attachment (SATA) hard disk drive (HDD) claim 2 , SATA solid state drive (SSD) claim 2 , Non-Volatile Memory express (NVMe) SSD claim 2 , Embedded Multimedia Card (eMMC) claim 2 , or Universal Flash Storage (UFS).4. The computer system of claim 2 , wherein the first storage device comprises a solid state drive (SSD) or a hard disk drive (HDD).5. The computer ...

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Номер записи: 51
30-01-2020 дата публикации

Storage device and control method

Номер: US20200034068A1
Автор: Hayato Masubuchi
Принадлежит: Toshiba Memory Corp

According to one embodiment, a controller acquires temperature data periodically while receiving a first mode designating signal, writes the temperature data into a nonvolatile storage while or after the first mode designating signal, acquires temperature data after a lapse of a predetermined time from designation of the second mode, writes the temperature data into the nonvolatile storage while or after a lapse of a predetermined time since the designation of the second mode, acquires temperature data at a timing of changing from the second mode to the first mode, and write the acquired temperature data into the nonvolatile storage at or after the timing of changing from the second mode to the first mode.

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Номер записи: 52
31-01-2019 дата публикации

CONTROLLER AND OPERATING METHOD THEREOF

Номер: US20190035443A1
Автор: PARK Byoung Jun, PARK Seong Jo
Принадлежит: SK HYNIX INC.

A controller controls an operation of a semiconductor memory device including a plurality of memory blocks. The controller includes a temperature sensing unit, a period storage unit, and a command generating unit. The temperature sensing unit generates temperature information by sensing a temperature of the semiconductor memory device. The period storage unit updates an output period of a dummy read command that allows the semiconductor memory device to perform a dummy read operation, based on the temperature information. The command generating unit generates the dummy read command, based on the output period. 1. A controller that controls an operation of a semiconductor memory device including a plurality of memory blocks , the controller comprising:a temperature sensing unit configured to generate temperature information by sensing a temperature of the semiconductor memory device;a period storage unit configured to update an output period of a dummy read command that allows the semiconductor memory device to perform a dummy read operation, based on the temperature information; anda command generating unit configured to generate the dummy read command, based on the output period.2. The controller of claim 1 , wherein the period storage unit includes a lookup table that includes an output period corresponding to each temperature range claim 1 ,wherein the period storage unit updates a currently applied output period with reference to the lookup table.3. The controller of claim 1 , wherein claim 1 , as the temperature measured by the temperature sensing unit increases claim 1 , the period storage unit updates a shorter period as the output period.4. The controller of claim 1 , wherein the command generating unit generates the dummy read command by comparing an output reference time with the output period claim 1 , where the output reference time indicates a period between a time when a preceding dummy read command was generated and a current time.5. The controller of ...

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Номер записи: 53
17-02-2022 дата публикации

COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS

Номер: US20220052802A1
Автор: Hampel Craig E., Perego Richard E., Ware Frederick A.
Принадлежит:

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component. 1. (canceled)2. A controller to control a memory component , the controller comprising:interface circuitry to transfer information with the memory component, via at least one link, wherein the interface circuitry is to time the transfer the information according to edges of a clock signal; andphase adjustment circuitry to vary a phase of the edges of the clock signal;wherein the phase adjustment circuitry is to establish an operating value of the phase during a calibration operation, the operating value to be applied to the transfer of the information, and wherein the phase adjustment circuitry is to from-time-to-time adjust the operating value in response to drift between the operating value and a timing point for transfer of the information used by the memory device, the drift being detected subsequent to establishment of the operating value.3. The controller of wherein the interface circuitry comprises a transmitter and wherein the information is to be transmitted by the transmitter to the memory device according to the edges of the clock signal.4. The controller ...

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Номер записи: 54
30-01-2020 дата публикации

MULTISTAGE SET PROCEDURE FOR PHASE CHANGE MEMORY

Номер: US20200035300A1
Автор: Gajera Nevil N., Liu Lu, Pangal Kiran, Rangan Sanjay, RAO SUBBU Gayathri
Принадлежит:

Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.

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Номер записи: 55
30-01-2020 дата публикации

Non-volatile memory with countermeasure for select gate disturb

Номер: US20200035312A1
Автор: Deepanshu Dutta, Dengtao Zhao
Принадлежит: SanDisk Technologies LLC

Program disturb is a condition that includes the unintended programming while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a dummy word line to another side of the dummy word line and redirected into a select gate. To prevent such program disturb, it is proposed to open the channel from one side of the dummy word line to the other side of the dummy word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied. For example, the channel can be opened up by applying a voltage to the dummy word line prior to pre-charging unselected memory cells.

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Номер записи: 56
08-02-2018 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20180039295A1
Автор: LEE Myung Hwan
Принадлежит: SK HYNIX INC.

A semiconductor device may be provided. The semiconductor device may include a reference voltage generation circuit suitable for controlling a level of a reference voltage depending on an internal resistance value, and controlling the level of the reference voltage depending on the internal resistance value. 1. A semiconductor device comprising:a reference voltage generation circuit suitable for controlling a level of a reference voltage depending on an internal resistance value controlled based on first code signals and second code signals at a first temperature, and controlling the level of the reference voltage depending on the internal resistance value controlled based on the first code signals and the second code signals at a second temperature.2. The semiconductor device according to claim 1 , wherein the reference voltage generation circuit comprises:an internal reference voltage generation circuit suitable for controlling the internal resistance value depending on the first code signals based on a power-up signal, and generating an internal reference voltage, a level of the internal reference voltage is controllable by the internal resistance value; anda voltage control circuit suitable for controlling the level of the internal reference voltage depending on the first code signals and the second code signals, and generating the reference voltage.3. The semiconductor device according to claim 2 , wherein the internal reference voltage generation circuit comprises:a driving signal generation circuit suitable for generating a driving voltage which is enabled in response to the power-up signal;a first reference current generation circuit suitable for generating a first control voltage, a level of which is controllable based on the driving voltage, and a first reference current which has a constant current value; anda second reference current generation circuit suitable for generating a second reference current which has the same current value as the first ...

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Номер записи: 57
12-02-2015 дата публикации

Memory module

Номер: US20150043290A1
Автор: Craig E. Hampel, Ely K. Tsern, Frederick A. Ware, Richard E. Perego
Принадлежит: RAMBUS INC

A memory module having integrated circuit (IC) components, a termination structure, an address/control signal path, a clock signal path, multiple data signal paths and multiple strobe signal paths. The strobe signal paths and data signal paths are coupled to respective IC components, and the address/control signal path and clock signal path are coupled in common to all the IC components. The address/control signal path extends along the IC components to the termination structure such that control signals propagating toward the termination structure arrive at address/control inputs of respective IC components at progressively later times corresponding to relative positions of the IC components.

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Номер записи: 58
12-02-2015 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20150043293A1
Автор: HUR Young-Do, KWON Tae-Woo, SONG Choung-Ki
Принадлежит: SK HYNIX INC.

A semiconductor memory device includes a plurality of banks; a counting block suitable for counting the activation number of the respective banks, and selecting a bank of which the activation number is larger than or equal to a given number; and a refresh control block suitable for performing a normal refresh operation on the banks in response to a refresh command, and performing an additional refresh operation N times on the selected bank, N being a positive integer. 1. A semiconductor memory device comprising:a plurality of banks;a counting block suitable for counting the activation number of the respective banks, and selecting a bank of which the activation number is larger than or equal to a given number; anda refresh control block suitable for performing a normal refresh operation on the banks in response to a refresh command, and performing an additional refresh operation N times on the selected bank, N being a positive integer.2. The semiconductor memory device according to claim 1 , wherein the counting block comprises:an active pulse generation unit suitable for generating a plurality of active pulses, each of which is toggled in response to an active command for the respective banks;a plurality of pulse counters suitable for counting the toggling number of the respective active pulses; anda plurality of activation detecting sections suitable for detecting the counting number of the respective pulse counters, and generating a plurality of determination signals indicating whether or not the activation number of the respective banks exceeds the given number.3. The semiconductor memory device according to claim 2 , wherein the refresh control block comprises:a normal refresh control circuit suitable for performing the normal refresh operation on the banks in response to the refresh command; andan additional refresh control circuit suitable for performing the additional refresh operation on the selected bank N times in response to the determination signals ...

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Номер записи: 59
08-02-2018 дата публикации

MULTIPLE TEMPERATURE TESTING OF NON-VOLATILE MEMORY DATA RETENTION TIME

Номер: US20180040384A1
Автор: Lazarov Kalin V., Petersen Michael D., ROHRER Timothy D.
Принадлежит:

The data retention time of a non-volatile memory array containing multiple non-volatile memory cells, each cell having a floating gate, may be tested. The method may include: baking the non-volatile memory array at a first temperature for a first duration and at a second temperature that is materially different than the first temperature for a second duration; testing the non-volatile memory array before and after each baking; and deciding whether to use or sell the tested non-volatile memory array based on results of the testing before and after each baking. 1. A method of testing the data retention time of a non-volatile memory array containing multiple non-volatile memory cells , each cell having a floating gate , comprising in the order recited:charging the floating gate of each memory cell;measuring the charge on the floating gate of each memory cell a first time;storing information indicative of the first-time measured charge on the floating gate of each memory cell;baking the non-volatile memory array at a first temperature for a first duration;measuring the charge on the floating gate of each memory cell a second time;storing information indicative of the second-time measured charge on the floating gate of each memory cell;baking the non-volatile memory array at a second temperature that is materially different than the first temperature for a second duration;measuring the charge on the floating gate of each memory cell a third time; andestimating the data retention time of each memory cell based on the first-time, second-time, and third-time measured charge on the floating gate of each memory cell.2. The method of further comprising claim 1 , between the baking at the first and the second temperature claim 1 , in the order recited:charging the floating gate of each memory cell a second time;measuring the charge on the floating gate of each memory cell after the second-time charging; andstoring information indicative of the measured charge on the floating ...

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Номер записи: 60
24-02-2022 дата публикации

MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE

Номер: US20220059141A1
Автор: HONG Yong Hwan, KIM Byung Ryul
Принадлежит: SK HYNIX INC.

A storage device including: a peripheral circuit configured to perform a plurality of internal operations corresponding to a plurality of internal operation commands input from the memory controller, a temperature information controller configured to generate a first temperature code corresponding to an internal temperature at a time at which an internal operation corresponding to a first internal operation command among the plurality of internal operation commands is performed and temperature code generation information representing information that the first temperature code has been generated during a set period and a operation controller configured to control the peripheral circuit to perform an internal operation corresponding to a second internal operation command input after the first internal operation command among the plurality of internal operation commands is input, based on the first temperature code and the temperature code generation information, in response to the second internal operation command. 1. A memory device comprising:a peripheral circuit configured to perform a plurality of internal operations corresponding to a plurality of internal operation commands input from the memory controller;a temperature information controller configured to generate a first temperature code corresponding to an internal temperature at a time at which an internal operation corresponding to a first internal operation command among the plurality of internal operation commands is performed and temperature code generation information representing information that the first temperature code has been generated during a set period; andan operation controller configured to control the peripheral circuit to perform an internal operation corresponding to a second internal operation command input after the first internal operation command among the plurality of internal operation commands is input, based on the first temperature code and the temperature code generation ...

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Номер записи: 61
18-02-2021 дата публикации

Clock Generation for Timing Communications with Ranks of Memory Devices

Номер: US20210049118A1
Автор: Eble John, Shaeffer Ian P., Zerbe Jared L.
Принадлежит:

A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device. 1. (canceled)2. A memory controller to control the operation of a first memory device and a second memory device , the memory controller comprising:a first register to store a first phase value for receiving data from the first memory device;a second register to store a second phase value for receiving data from the second memory device;a timing circuit to derive the first phase value based on first calibration data associated with the first memory device, wherein the first calibration data is to be established based on a strobe signal received from the first memory device via a respective strobe signal line, and to derive the second phase value based on second calibration data associated with the second memory device, wherein the second calibration data is to be established based on a strobe signal received from the second memory device via a respective strobe signal line; anda sampling circuit, coupled to the timing circuit and at least one signal line, to receive data based on the first phase value and the second phase value.3. The memory controller of claim 2 , wherein the timing circuit includes edge tracking circuitry coupled to the first register and second register to generate first timing adjustment data associated with the first memory device and second timing adjustment data associated with ...

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Номер записи: 62
19-02-2015 дата публикации

MEMORY AND MEMORY SYSTEM INCLUDING THE SAME

Номер: US20150049566A1
Автор: LEE Doo-Chan, SONG Choung-Ki
Принадлежит: SK HYNIX INC.

A memory including a first cell block comprising a plurality of first word line groups, and one or more first redundancy word line groups each corresponding to one hit signal of a plurality of hit signals; a second cell block comprising a plurality of second word line groups, and one or more second redundancy word line groups each corresponding to one hit signal of the plurality of hit signals; and a control unit suitable for selecting a cell block and a word line in response to a first input address and refreshing a selected word line based on an input address inputted after the first input address, while refreshing one or more adjacent word lines adjacent to a first selected word line, which is selected by the first input address, in response to the first input address and the hit signals when the first selected word line is adjacent to a redundancy word line, wherein the first input address is first inputted in a target refresh section. 1. A memory comprising:a first cell block comprising a plurality of first word line groups each having two or more first word lines, and one or more first redundancy word line groups each having two or more first redundancy word lines and corresponding to one hit signal of a plurality of hit signals;a second cell block comprising a plurality of second word line groups each having two or more second word lines, and one or more second redundancy word line groups each having two or more second redundancy word lines and corresponding to one hit signal of the plurality of hit signals; anda control unit suitable for selecting a cell block and a word line in response to a first input address and refreshing a selected word line based on an input address inputted after the first input address, while refreshing, one or more adjacent word lines adjacent to a first selected word line, which is selected by the first input address, in response to the first input address and the hit signals when the first selected word line is adjacent to a ...

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Номер записи: 63
06-02-2020 дата публикации

TEMPERATURE SENSITIVE NAND PROGRAMMING

Номер: US20200043555A1
Автор: Hoei Jung Sheng, Huang Jianmin, Luo Ting, Luo Xiangang, Singidi Harish Reddy, Vashi Ankit Vinod
Принадлежит:

Devices and techniques temperature sensitive NAND programming are disclosed herein. A device controller can receive a command to write data to a component of the device. A temperature can be obtained in response to the command, and the temperature can be combined with a temperature compensation value to calculate a verification level. The command can then be executed in accordance with the verification level. 1. A memory device for temperature sensitive programming , the memory device comprising:an array of memory components; and obtaining a temperature for a memory component in the array of memory components during a write to the memory component;', 'calculating a verification read voltage for a write verification from the temperature; and', 'controlling repeated application of a program pulse to the memory component to perform the write until the memory component can be read using the verification read voltage., 'a controller configured to perform operations comprising2. The memory device of comprising a machine readable medium that includes instructions that claim 1 , when executed by the controller claim 1 , configure the controller to perform the operations.3. The memory device of claim 1 , wherein obtaining the temperature includes obtaining the temperature from a thermometer in response to receiving the command.4. The memory device of claim 1 , wherein calculating the read voltage from the temperature includes performing a quantification of the temperature into one range of a set of temperature ranges.5. The memory device of claim 4 , wherein calculating the read voltage from the temperature includes selecting a temperature compensation value using the one range; andwherein controlling repeated application of the program pulse includes modifying the program pulse to use the temperature compensation value.6. The memory device of claim 5 , wherein selecting the temperature compensation value includes:identifying an intermediate temperature compensation value ...

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Номер записи: 64
06-02-2020 дата публикации

MANAGED NAND PERFORMANCE THROTTLING

Номер: US20200043559A1
Автор: Blodgett Greg A., Jean Sebastien Andre
Принадлежит:

Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments. 1. (canceled)2. A method implemented on a host , the method comprising:sending by an initiator executing on the host, over a host interface to a memory device, an access request for a protected memory region of a non-volatile memory array, the access request including an identifier of the initiator, the protected memory region requiring a secret value derived from a key and a write counter to access the protected memory region;receiving a result from the memory device through the host interface; anddetermining that the result includes a second identifier different from the identifier of the initiator; andresponsive to determining that the result includes the second identifier, determining that the result is not responsive to the access request and sending a second access request for the protected memory region.3. The method of claim 2 , wherein the result includes a write counter status and an operation status.4. The method of claim 3 , wherein the write counter status is located in a first region of the result claim 3 , the operation status is located in a second region of the result claim 3 , and the identifier of the initiator is located in a third region of the result.5 ...

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Номер записи: 65
16-02-2017 дата публикации

Read distribution in a three-dimensional stacked memory based on thermal profiles

Номер: US20170046079A1
Автор: Diyanesh B. Chinnakkonda Vidyapoornachary, Kenneth L. Wright, Saravanan Sethuraman
Принадлежит: International Business Machines Corp

A memory controller may receive a plurality of thermal profiles from a plurality of three-dimensional (3D)-stacked memory chips, where the plurality of thermal profiles include thermal profile data for the memory chips, where the thermal profile data includes a memory chip usage data and a location data for each of the memory chips, and where the memory chips include a first memory chip and a second memory chip. The memory controller may generate a first predicted memory chip usage data and location data by analyzing the usage data and location data of the thermal profile data. A second predicted memory chip usage data and location data may be generated. Based on the predicted memory chip, fractional memory chip read propensity data may be generated. The memory controller may distribute, according the first fractional memory chip read propensity distribution, memory chip read operations.

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Номер записи: 66
16-02-2017 дата публикации

METHOD AND APPARATUS FOR ADJUSTMENT OF CURRENT THROUGH A MAGNETORESISTIVE TUNNEL JUNCTION (MTJ) BASED ON TEMPERATURE FLUCTUATIONS

Номер: US20170047104A1
Автор: Abedifard Ebrahim, Keshtbod Parviz
Принадлежит:

A non-volatile memory system includes a first circuit and a second circuit both coupled to a magnetoresistance tunnel junction (MTJ) cell to substantially reduce the level of current flowing through the MTJ with rise in temperature, as experienced by the MTJ. The first circuit is operable to adjust a slope of a curve representing current as a function of temperature and the second circuit is operable to adjust a value of the current level through the MTJ to maintain current constant or to reduce current when the temperature increases. This way sufficient current is provided for the MTJ at different temperatures, to prevent write failure, over programming, MTJ damage and waste of current. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. (canceled)6. A circuit comprising:a first device operable to measure a temperature of an MTJ;a second device coupled to the first device and operable to generate a write current according to the temperature of the MTJ, the write current being used to program the MTJ,wherein the first device is a diode circuit located on a chip onto which the MTJ is formed.7. (canceled)8. (canceled)9. (canceled)10. A circuit comprising:a first device operable to measure a temperature of an MTJ,a second device coupled to the first device and operable to generate a write current according to the temperature of the MTJ, the write current being used to program the MTJ,wherein the first device is a temperature sensitive resistor located on a chip onto which the MTJ is formed.11. The circuit of claim 6 , wherein the second device is a current source controlled by the first device.12. The circuit of claim 11 , wherein the current source is operable to determine a slope defined by a change in the write current through the MTJ versus a change in the temperature of the MTJ claim 11 , the current source further operable to use the slope to adjust the write current.13. The circuit of claim 11 , wherein the current source is operable to measure a change in a ...

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Номер записи: 67
15-02-2018 дата публикации

Methods and apparatus for synchronizing communication with a memory controller

Номер: US20180047437A1
Автор: David B. Roberts, Frank Lambrecht, Richard E. Warmke, Scott C. Best
Принадлежит: RAMBUS INC

A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

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Номер записи: 68
03-03-2022 дата публикации

METHOD AND SYSTEM FOR REGULATING MEMORY, AND SEMICONDUCTOR DEVICE

Номер: US20220068320A1
Автор: NING Shu-Liang
Принадлежит: CHANGXIN MEMORY TECHNOLOGIES, INC.

A method for regulating the memory includes operations as follows. A mapping relationship among temperatures of a transistor, body bias voltages of the transistor, and data writing time of the memory is acquired, a current temperature of the transistor is acquired, the body bias voltage is regulated based on the current temperature and the mapping relationship, to enable the data writing time corresponding to the regulated body bias voltage to be within a preset writing time.

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Номер записи: 69
03-03-2022 дата публикации

Method and system for adjusting memory, and semiconductor device

Номер: US20220068321A1
Автор: Jie Liu, Jun He, Shu-Liang NING, Zhan Ying
Принадлежит: Changxin Memory Technologies Inc

Embodiments of the disclosure, there is provided a method, a system for adjusting the memory, and a semiconductor device. The method for adjusting the memory includes: acquiring a mapping relationship between a temperature of a transistor, an equivalent width-length ratio of a sense amplifier transistor in a sense amplifier and an actual time at which the data is written into the memory; acquiring a current temperature of the transistor; and adjusting the equivalent width-length ratio, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted equivalent width-length ratio is within a preset writing time.

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Номер записи: 70
03-03-2022 дата публикации

MEMORY DEVICE

Номер: US20220068395A1
Автор: "MANFRE Davide", AURICCHIO Chantal, CALVETTI Emanuela, CAPECCHI Laura, CARISSIMI Marcella, DISEGNI Fabio Enrico Carlo, TORTI Cesare, ZANCHI Stefano
Принадлежит: STMICROELECTRONICS S.R.L.

A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.

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Номер записи: 71
03-03-2022 дата публикации

Circuit and method for process and temperature compensated read voltage for non-volatile memory

Номер: US20220068400A1
Автор: Abhishek Mittal, Dario Livornesi, Marco Pasotti, Roberto Bregoli, Vikas RANA
Принадлежит: STMicroelectronics International NV, STMicroelectronics International NV Switzerland, STMICROELECTRONICS SRL

An integrated circuit includes a memory array and a read voltage regulator that generates read voltages from the memory array. The read voltage regulator includes a replica memory cell and the replica bitline current path. The replica memory cell is a replica of memory cells of the memory array. The replica bitline current path is a replica of current paths associated with deadlines of the memory array. The read voltage regulator generates a read voltage based on the current passed through the replica bitline current path. This read voltage is then supplied to the wordlines of the memory array during a read operation.

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Номер записи: 72
26-02-2015 дата публикации

Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory

Номер: US20150055425A1
Автор: Chang Hua Siau, Christophe Chevallier, Seow Fong Lim
Принадлежит: Unity Semiconductor Corp

Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

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Номер записи: 73
25-02-2016 дата публикации

Semiconductor device including temperature ranges having temperature thresholds and method of determining therefor

Номер: US20160054374A1
Автор: Darryl G. Walker
Принадлежит: Darryl G. Walker

A method of determining temperature ranges and setting performance parameters in a semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. The performance parameters may be set to improve speed parameters and/or decrease current consumption over a wide range of temperature ranges.

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Номер записи: 74
25-02-2016 дата публикации

Testing and setting performance parameters in a semiconductor device and method therefor

Номер: US20160054379A1
Автор: Darryl G. Walker
Принадлежит: Darryl G. Walker

A method of determining temperature ranges and setting performance parameters in a semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. The performance parameters may be set to improve speed parameters and/or decrease current consumption over a wide range of temperature ranges.

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Номер записи: 75
14-02-2019 дата публикации

ROUTING DATA BLOCKS DURING THERMAL THROTTLING

Номер: US20190050153A1
Автор: KAMILA Varuna, Yang Nian Niles
Принадлежит:

Embodiments of a SSD include a controller coupled to one or more flash dies, one or more temperature sensors proximate to the one or more flash dies, and data storing instructions. The one or more flash dies includes a plurality of TLC (triple level cell) blocks. The controller when executing the data storing instructions cause the controller to periodically fetch a temperature reading from the one or more temperature sensors and limit operations to the one or more flash dies when the temperature reading is above a start throttling threshold. In certain embodiments, TLC blocks are written to in a SLC mode when the temperature reading is above the start throttling threshold. In other embodiments, one or more spare SLC blocks are written to with non-system data during throttling. 1. A solid state drive , comprising:a controller;one or more flash dies comprising a plurality of triple level cell (TLC) blocks;one or more temperature sensors proximate to the one or more flash dies; and periodically fetch a temperature reading from the one or more temperature sensors;', 'limit operations to the one or more flash dies when the temperature reading is above a start throttling threshold; and', 'write to the TLC blocks in a SLC mode when the temperature reading is above the start throttling threshold., 'a non-transitory computer readable storage medium containing data storing instructions that, when executed by the controller, cause the controller to2. The solid state drive of claim 1 , further comprising an assignment table wherein the data storing instructions further cause the controller to flag in the assignment table the TLC blocks written in the SLC mode.3. The solid state drive of claim 1 , wherein the data storing instructions further cause the controller to fold the TLC blocks written in the SLC mode into TLC blocks in a TLC mode when the temperature reading is below a stop throttling threshold.4. The solid state drive of claim 3 , wherein the data storing instructions ...

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Номер записи: 76
14-02-2019 дата публикации

MANAGEMENT SYSTEM FOR MEMORY DEVICE AND MANAGEMENT METHOD FOR THE SAME

Номер: US20190050156A1
Автор: Chang Hung-Sheng, Chang Yuan-hao, Kuo Tei-Wei, Li Hsiang-Pang
Принадлежит:

Disclosed is a management system for managing a memory device having sub-chips each having a container area and a data area. A CPU selects a target sub-chip according to respective temperature of the sub-chips. When the CPU intends to access a first original data in one of the data areas, a hot date tracking device acquires a first original address of the first original data from the CPU. When the first original address is recorded in one of a plurality of tracking layers, the CPU is indicated to access a first copied data corresponding to the first original data in the container area of the target sub-chip according to a current tracking layer recording the first original address. When the first original address is not recorded in the tracking layers, the CPU accesses the first original data in the data area according to the first original address. 1. A management system for managing a memory device , the memory device having a plurality of sub-chips , each of the sub-chips comprising a container area and a data area , the management system comprising:a central processing unit (CPU) coupled to the memory device, the CPU selecting a target sub-chip among the sub-chips according to respective temperature of the sub-chips;a hot data tracking device coupled to the CPU, the hot data tracking device comprising a plurality of tracking layers,wherein, when the CPU intends to access a first original data stored in one of the data areas,the hot date tracking device acquires a first original address of the first original data from the CPU;when the hot data tracking device determines that the first original address is recorded in one of the tracking layers, the hot data tracking device indicates the CPU to access a first copied data corresponding to the first original data from the container area of the target sub-chip according to a current tracking layer of the tracking layers recording the first original address; andwhen the hot data tracking device determines that the ...

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Номер записи: 77
03-03-2022 дата публикации

SIGNALING SYSTEM WITH ADAPTIVE TIMING CALIBRATION

Номер: US20220069975A1
Автор: Hampel Craig E., Stott Bret G., Ware Frederick A.
Принадлежит:

A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

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Номер записи: 78
25-02-2016 дата публикации

Memory system and driving method thereof

Номер: US20160055914A1
Автор: Kitae Park, Kuihan KO, Sang-Wan Nam, Yang-Lo AHN
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A driving method of a nonvolatile memory device includes receiving a program command and an address. The method includes changing a number of adjacent zones of a plurality of zones formed of unselected word lines according to a location of a selected word line corresponding to the received address. The method further includes applying different zone voltages to the number of adjacent zones and remaining zones. The nonvolatile memory device includes a plurality of strings formed to penetrate word lines stacked on a substrate in a plate shape.

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Номер записи: 79
14-02-2019 дата публикации

STROBE-OFFSET CONTROL CIRCUIT

Номер: US20190051345A1
Автор: Best Scott C.
Принадлежит:

A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal. 1. (canceled)2. A method of operation in a memory controller , the method comprising:configuring each of multiple receiver circuits for operation in one of a calibration mode or an input sampler mode; and receiving a read data signal at a data input and receiving an accompanying strobe signal,', 'selecting a delayed version of the strobe signal from a selection of strobe signals,', 'adjusting the delayed version of the strobe signal by an offset to generate an adjusted strobe signal, the offset determined during the calibration mode., 'wherein operation in the input sampler mode comprises'}3. The method according to claim 2 , further comprising:determining the offset during the calibration mode on a per-bit basis.4. The method according to claim 3 , wherein:the offset for each of the multiple receiver circuits is different.5. The method according to claim 2 , wherein:the selection of strobe signals includes the delayed strobe signal and the strobe signal.6. The method according to claim 2 , further comprising:applying a predetermined delay to the strobe signal along a strobe delay path to generate the delayed version of the strobe signal.7. The method according to claim 6 , further comprising:applying the predetermined delay to the read data signal along a read data path.8. The method according to claim 2 , wherein adjusting the delayed ...

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Номер записи: 80
22-02-2018 дата публикации

Semiconductor device, test program, and test method

Номер: US20180053546A1
Автор: Atsushi Miyanishi, Yoshisato Yokoyama, Yuichiro Ishii
Принадлежит: Renesas Electronics Corp

When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of defects due to local variation is suppressed. An SRAM including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (VDD) potential and drive the other bit line at an intermediate potential (VSS+several tens mV to one handled and several tens mV) a little higher than a low level (VSS) potential for normal writing when writing data into the memory cell.

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Номер записи: 81
10-03-2022 дата публикации

Memory device for adjusting delay on data clock path, memory system including the memory device, and operating method of the memory system

Номер: US20220075564A1
Автор: Byongmo Moon, Jihye Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory system includes a memory device configured to monitor a first oscillator count value for a write data strobe signal for sampling a data signal at a first temperature and a second oscillator count value for the write data strobe signal for sampling the data signal at a second temperature, and a memory controller configured to determine a weight based on the first oscillator count value and the second oscillator count value, wherein the memory device is configured to sample the data signal by adjusting a delay on a transfer path of the write data strobe signal according to a change in temperature of the memory device based on the weight.

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Номер записи: 82
05-03-2015 дата публикации

MEMORY TIMING CIRCUIT

Номер: US20150063046A1
Автор: CHABA Ritu, GULATI Chirag, Sinha Rakesh Kumar, Yoon Sei Seung
Принадлежит: QUALCOMM INCORPORATED

Disclosed are various apparatuses and methods for a memory with a multiple word line design. A memory timing circuit may include a dummy word line including a first portion and a second portion and further including capacitative loading that is lumped in the second portion of the dummy word line, a first transistor connected to the first portion of the dummy word line and configured to charge the dummy word line, and a second transistor connected to the second portion of the dummy word line and configured to discharge the dummy word line. A method may include charging a dummy word line using a first transistor, and discharging the dummy word line using a second transistor, wherein the dummy word line includes a first portion and a second portion and further includes capacitative loading that is lumped in the second portion of the dummy word line. 1. A memory timing circuit comprising:a dummy word line comprising a first portion and a second portion and comprising capacitative loading that is lumped in the second portion of the dummy word line;a first transistor connected to the first portion of the dummy word line and configured to charge the dummy word line; anda second transistor connected to the second portion of the dummy word line and configured to discharge the dummy word line.2. The memory timing circuit of claim 1 , wherein the first transistor is a p-type transistor and the second transistor is an n-type transistor.3. The memory timing circuit of claim 1 , further comprising a tripping transistor having a source connected to the second portion of the dummy word line and a drain connected to an output node of the memory timing circuit.4. The memory timing circuit of claim 3 , wherein the tripping transistor is a p-type transistor.5. The memory timing circuit of claim 3 , wherein a gate of the tripping transistor is tied to ground.6. The memory timing circuit of claim 3 , wherein the source of the tripping transistor is connected to a drain of the second ...

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Номер записи: 83
01-03-2018 дата публикации

SEMICONDUCTOR DEVICE HAVING TEMPERATURE CIRCUIT THAT SETS TEMPERATURE RANGES AND IS DISABLED UPON POWER SUPPLY TRANSITION

Номер: US20180058944A1
Автор: Walker Darryl G.
Принадлежит:

A device can include a temperature circuit that can selectively set one of a plurality of temperature ranges. Each temperature range can have a temperature range upper limit value and a temperature range lower limit value. The temperature circuit can be disabled in response to a detection of a transition in a power supply voltage. In some embodiments, the temperature circuit can also be enabled a predetermined time period after the detection of the transition in the power supply voltage. 1. A device , comprising:a temperature circuit, the temperature circuit configured to selectively set one of a plurality of temperature ranges, each temperature range having a temperature range upper limit value and a temperature range lower limit value;wherein the temperature circuit configured to be disabled in response to a detection of a transition in a power supply voltage.2. The device of claim 1 , wherein:the temperature circuit is configured to be enabled a predetermined time period after the detection of the transition in the power supply voltage.3. The device of claim 2 , further including:a power up circuit configured to detect the transition in the power supply voltage, the power up circuit configured to provide a power up signal and the temperature circuit is configured to be disabled in response to the power up signal having a first power up logic level.4. The device of claim 3 , wherein:the temperature circuit is configured to be enabled in response to the power up signal having a second power up logic level.5. The device of claim 1 , further including:a value providing circuit, the value providing circuit configured to provide a value, the value selectively sets the one of the plurality of temperature windows, wherein the value is set to a first value in response to the detection of the transition in the power supply voltage.6. The device of claim 5 , wherein:the temperature circuit is configured to be enabled a predetermined first time period after the detection of ...

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Номер записи: 84
10-03-2022 дата публикации

TIMING SIGNAL DELAY COMPENSATION IN A MEMORY DEVICE

Номер: US20220076720A1
Автор: Chu Wei Lu, Huang Zhi Qi, Pan Dong
Принадлежит:

Methods, systems, and devices for timing signal delay compensation in a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. In accordance with examples as disclosed herein, a memory device may include delay components having a variable and configurable impedance, where the configurable impedance may be based at least in part on a configuration signal generated at the memory device. A configuration signal may be generated based on fabrication characteristics of the memory device, or based on operating conditions of the memory device, or various combinations thereof. 1. A method , comprising:receiving, at a delay component of a memory device, a first timing signal and an impedance configuration signal;configuring an impedance of the delay component based at least in part on the impedance configuration signal; andgenerating a second timing signal based at least in part on the first timing signal and the impedance configuration signal, wherein the second timing signal is delayed relative to the first timing signal based at least in part on the configured impedance of the delay component.2. The method of claim 1 , wherein configuring the impedance of the delay component comprises:configuring a resistance between a source of a transistor and a drain of the transistor based at least in part on biasing a gate of the transistor with the impedance configuration signal.3. The method of claim 1 , wherein generating the second timing signal comprises:generating the second timing signal with a rising edge that is delayed, relative to a rising edge of the first timing signal, with a delay that is based at least in part on configuring the impedance of the delay component.4. The method of ...

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Номер записи: 85
10-03-2022 дата публикации

Selection of read offset values in a memory sub-system

Номер: US20220076765A1
Автор: Kishore Kumar Muchherla, Larry J. Koudele, Vamsi Pavan Rayaprolu
Принадлежит: Micron Technology Inc

An example memory sub-system to receive a request to execute a read operation associated with data of a memory unit of a memory sub-system. A time after program associated with the data is determined. The time after program is compared to a threshold time level to determine if a first condition is satisfied or a second condition is satisfied. The memory sub-system selects one of a first set of read offset values based on the time after program in response to satisfying the first condition, or a second set of read offset values based on a data state metric measurement in response to satisfying the second condition.

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Номер записи: 86
03-03-2016 дата публикации

Power up of semiconductor device having a temperature circuit and method therefor

Номер: US20160064064A1
Автор: Darryl G. Walker
Принадлежит: Darryl G. Walker

A semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at other operating temperatures. The temperature sensing circuit may provide a plurality of temperature ranges for setting the operational parameters. Each temperature range can include a temperature range upper limit value and a temperature range lower limit value and adjacent temperature ranges may overlap. The temperature ranges may be set in accordance with a count value that can incrementally change in response to the at least one temperature sensing circuit.

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Номер записи: 87
01-03-2018 дата публикации

Semiconductor memory device

Номер: US20180061462A1
Автор: Hiroki Murakami, Makoto SENO
Принадлежит: Winbond Electronics Corp

A semiconductor memory device which is capable of high-speed operation in synchronization with external control signals is provided. The semiconductor memory device has a data input portion, a memory array, a data output portion, and a control portion. The data input portion receives command and address input data in response to the external control signals. The memory array has a plurality of memory elements. The data output portion outputs data read from the memory array in response to the external control signals. The control portion has the function of delay-compensation. During the time interval for receiving the input data, the function of delay-compensation estimates the delay time of the internal circuits, stores the estimated delay-time in a memory unit, and adjusts the output timing of the data output portion.

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Номер записи: 88
01-03-2018 дата публикации

Semiconductor memory device

Номер: US20180061496A1
Автор: Makoto Senoo, Naoaki Sudo
Принадлежит: Winbond Electronics Corp

A semiconductor memory device improving a high-temperature data retention is provided. Here, a flash memory includes an erasing element erasing a selected storage cell in a storage cell array. The erasing element further includes an applying element, a verifying element, and a decision element. The applying element applies a monitoring erasing pulse to a monitoring storage cell before starting an erasing operation for selecting the storage cell. The verifying element performs a verification of the monitoring storage cell to which the monitoring erasing pulse is applied. The decision element detennines ISPE conditions based on a verification result of the verifying element. The erasing element erases the storage cell according to the determined ISPE conditions.

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Номер записи: 89
01-03-2018 дата публикации

TEMPERATURE COMPENSATION IN MEMORY SENSING

Номер: US20180061497A1
Автор: Kavalipurau Kalyan C., Park Jae-Kwan, Vu Luyen, Yu Erwin E.
Принадлежит: MICRON TECHNOLOGY, INC.

Sense circuits and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation. 1. A sense circuit , comprising:a sense node selectively connected to a data line that is selectively connected to a memory cell;a first transistor connected between a voltage node and an output of the sense circuit and having a control gate connected to the sense node; anda second transistor connected between the sense node and the output of the sense circuit and having a control gate configured to receive a control signal, a first source/drain connected to the sense node, and a second source/drain connected to a first source/drain of the first transistor.2. The sense circuit of claim 1 , further comprising:a third transistor connected to the first transistor and having a control gate configured to receive a second control signal;wherein the third transistor is configured to facilitate isolation of the output of the sense circuit from the voltage node regardless of activation of the first transistor.3. The sense circuit of claim 2 , wherein the third transistor is connected between the first transistor and the voltage node claim 2 , and further comprising:a latch connected between the output of the sense circuit and the first transistor;wherein the third transistor has a first source/drain connected to the voltage node and a second source/drain connected to a second source/drain of the first transistor.4. The sense circuit of claim 2 , wherein the third transistor is connected between the first transistor and the output of the sense circuit claim 2 , and further comprising:a latch connected between the output of the sense circuit and the third transistor;wherein the first transistor has a second source/drain ...

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Номер записи: 90
01-03-2018 дата публикации

CIRCUIT AND METHOD FOR BIASING NONVOLATILE MEMORY CELLS

Номер: US20180061499A1
Автор: Castagna Giuseppe, DISEGNI Fabio Enrico Carlo, Perroni Maurizio Francesco
Принадлежит:

A circuit for biasing non-volatile memory cells includes a dummy decoding path between a global bias line and a biasing node, a reference current generator coupled to the dummy decoding path and configured to supply a reference current, a biasing stage configured to set a cell bias voltage on the biasing node, and a compensation stage configured to compensate a current absorption of the biasing stage at the biasing node so that the reference current will flow through the dummy decoding path. 1. A circuit , comprising:a dummy decoding path having a first terminal tied to a global bias line and a second terminal tied to a cell bias node, the dummy decoding path having a structure identical to a conductive path of a column decoder coupled between the global bias line and a bit line of a memory cell;a first enable transistor coupled between the cell bias node and a current adder node;a reference current generator coupled between the current adder node and a ground line, the reference current generator being configured to supply a reference current flowing through the dummy decoding path;a bias circuit comprising a bias resistive divider path having a first portion and a second portion separated by a bias regulation node, the second portion of the bias resistive divider path coupled between the cell bias node and the bias regulation node, the bias circuit being configured to set a cell bias voltage on the cell bias node;a second enable transistor coupled between the cell bias node and an output of the bias circuit; anda compensation circuit configured to generate a compensation current that is injected into the current adder node, the compensation current being configured to compensate a current absorption of the bias circuit at the cell bias node.2. The circuit of claim 1 , wherein the reference current is equal to an average current flowing in the memory cell during a programming operation.3. The circuit of claim 1 , wherein the first enable transistor and the second ...

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Номер записи: 91
20-02-2020 дата публикации

NAND CELL ENCODING TO IMPROVE DATA INTEGRITY

Номер: US20200058327A1
Автор: Bueb Christopher, Huang Jianmin, Singidi Harish Reddy, Stichka Tyson M., Stoller Scott Anthony, Tanpairoj Kulachet, Thomson Preston Allen
Принадлежит:

Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modified encoding in response to the high-temperature indicator. The modified encoding includes a reduced number of voltage distribution positions from an unmodified encoding without changing voltage distribution widths, where each voltage distribution corresponds to a discrete set of states an encoding. 1. (canceled)2. A non-transitory machine-readable medium including instructions for temperature-sensitive cell encoding , the instructions , when executed by circuitry on a device to program a NAND cell , cause the circuitry to perform operations comprising:obtaining a temperature;selecting a NAND cell encoding from a base encoding based on the temperature; andprogramming the NAND cell with the encoding, wherein the selected encoding differs from the base encoding by using fewer than all voltage distributions in the base encoding.3. The machine-readable medium of claim 2 , wherein the NAND cell is read using the base encoding.4. The machine-readable medium of claim 2 , wherein the voltage distributions used in the selected encoding increase a read margin between two symbols compared to that of the base encoding.5. The machine-readable medium of claim 2 , wherein the base encoding has eight discrete states claim 2 , and wherein the selected encoding has four discrete states.6. The machine-readable medium of claim 2 , wherein multiple programming passes are used to program the NAND cell claim 2 , and wherein the first pass operates in accordance with a first programming pass of the base encoding claim 2 , one or more subsequent programming passes enacting the selected encoding.7. The machine-readable medium of claim 5 , wherein the four discrete states correspond to states zero claim 5 , three claim 5 , four claim 5 , and seven from the ...

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Номер записи: 92
22-05-2014 дата публикации

Three-Dimensional Flash Memory System

Номер: US20140140138A1
Автор: Hieu Van Tran, Hung Quoc Nguyen, Mark REITEN
Принадлежит: Silicon Storage Technology Inc

A three-dimensional flash memory system is disclosed.

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Номер записи: 93
08-03-2018 дата публикации

SIGNALING INTERFACE WITH PHASE AND FRAMING CALIBRATION

Номер: US20180067538A1
Автор: Fuller Andrew M., Palmer Robert E., Poulton John W., Ware Frederick A.
Принадлежит:

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices. 120-. (canceled)21. A method of operation within a memory controller , the method comprising:outputting a first timing signal to a memory device to time transmission of a data signal from the memory device to the memory controller;sampling the data signal in response to a second timing signal during first and second calibration intervals to generate respective first and second calibration data sequences;adjusting a phase of the first timing signal, based at least in part on whether the first calibration data sequence matches a first expected data pattern, to phase-adjust the data signal relative to the second timing signal; andadjusting a first control value that defines framing boundaries between respective multi-bit values conveyed in the data signal based at least on whether the second calibration data sequence matches a second expected data pattern.22. The method of wherein each bit conveyed in the data signal is valid at an input of the controller for a respective bit interval claim 21 , and wherein adjusting the phase of the first timing signal comprises adjusting a phase of the data signal within a phase range corresponding to the respective bit interval.23. The method of wherein the first calibration data ...

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Номер записи: 94
17-03-2022 дата публикации

MEMORY DEVICE AND CONTROL METHOD THEREOF

Номер: US20220084563A1
Автор: Shin Hoyoung
Принадлежит:

Disclosed is a memory device, which includes a memory cell, a bit line connected to the memory cell, a controller that generates at least one current control code, a first current generator that generates a first current having a proportional to absolute temperature (PTAT) characteristic, based on the at least one current control code from the controller, a second current generator that generates a second current having a complementary to absolute temperature (CTAT) characteristic, based on the at least one current control code from the controller, a subtractor that generates a third current by subtracting the second current from the first current, and a sense amplifier that controls a load current to be supplied to the bit line based on the third current, and generates a bit line compensation current for compensating for a leakage current of the bit line. 1. A memory device comprising:a memory cell;a bit line connected to the memory cell;a controller configured to generate at least one current control code;a first current generator configured to generate a first current having a proportional to absolute temperature (PTAT) characteristic, based on the at least one current control code from the controller;a second current generator configured to generate a second current having a complementary to absolute temperature (CTAT) characteristic, based on the at least one current control code from the controller;a subtractor configured to generate a third current by subtracting the second current from the first current; anda sense amplifier configured to control, based on the third current, a load current to be supplied to the bit line, and to generate a bit line compensation current for compensating for a leakage current of the bit line.2. The memory device of claim 1 , further comprising:a pulse signal generator configured to output a pre-charge pulse signal to the sense amplifier,wherein the pulse signal generator generates the pre-charge pulse signal based on a ...

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Номер записи: 95
17-03-2022 дата публикации

SEMICONDUCTOR STORAGE DEVICE

Номер: US20220084566A1
Автор: IWAI Makoto
Принадлежит: Kioxia Corporation

A semiconductor storage device of embodiments is a semiconductor storage device including a memory cell array including a plurality of non-volatile memory cells, a sequencer configured to control a sequence based on read operation of reading data from the memory cell array, and a column decoder, the sequencer controlling the sequence of changing a ready/busy signal from ready to busy after receiving a read command and an address signal, reading data from the memory cell array using a sense amplifier after changing the ready/busy signal to the busy, changing the ready/busy signal from the busy to the ready after storing data in the data latch circuit, receiving a data output command after changing the ready/busy signal to the ready, and, in a case where a first condition occurs, writing log data including the data stored in the data latch circuit in a memory area of the memory cell array. 1. A semiconductor storage device comprising:a memory cell array including a plurality of blocks and configured to be able to store first data;a sequencer configured to control a sequence based on read operation of reading the first data from the memory cell array on a basis of a read command received from a memory controller; anda column decoder comprising a sense amplifier configured to perform sense operation necessary for reading the first data from the memory cell array, and a data latch circuit configured to store the first data,at least one block among the plurality of blocks comprising first and second select transistors and a plurality of non-volatile memory cells connected in series between the first and second select transistors,the sequencer controlling the sequence ofreceiving the read command and an address signal;changing a ready/busy signal from ready to busy after receiving the read command and the address signal;reading the first data from the memory cell array using the sense amplifier after changing the ready/busy signal to the busy, and storing the first data in ...

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Номер записи: 96
17-03-2022 дата публикации

Memory system

Номер: US20220084567A1
Автор: Prashob Ramachandran Nair
Принадлежит: Kioxia Corp

According to one embodiment, a memory system includes a non-volatile semiconductor memory with a plurality of dies and a memory controller. A temperature sensor is provided for each of the dies. The temperature sensors measures a temperature of each die. The memory controller schedules execution of access commands for each of the dies based on the measured die temperature, a predetermined limit temperature for each of the dies, and the type of access command that has been received by the memory controller.

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Номер записи: 97
17-03-2022 дата публикации

Resistive memory device for writing data and operating method thereof

Номер: US20220084591A1
Автор: Chankyung Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A resistive memory device includes a resistive cell connected between a first bit line and a first source line, a reference cell including a reference resistor and connected between a second bit line and a second source line, and a write driver connected to the first bit line or the first source line, connected to the second bit line or the second source line. The write driver includes a comparator configured to compare previous data written in the resistive cell with the target data by comparing a voltage of the first source line with a voltage of the second source line or comparing a voltage of the first bit line with a voltage of the second bit line, and determine whether the target data is written in the resistive cell after comparing the previous data with the target data.

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Номер записи: 98
28-02-2019 дата публикации

NAND CELL ENCODING TO IMPROVE DATA INTEGRITY

Номер: US20190066736A1
Автор: Bueb Christopher, Huang Jianmin, Singidi Harish, Stichka Tyson M., Stoller Scott Anthony, Tanpairoj Kulachet, Thomson Preston
Принадлежит:

Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modified encoding in response to the high-temperature indicator. The modified encoding includes a reduced number of voltage distribution positions from an unmodified encoding without changing voltage distribution widths, where each voltage distribution corresponds to a discrete set of states an encoding. 1. A NAND device for NAND cell encoding , the NAND device comprising:a NAND cell; and obtain a high-temperature indicator;', 'receive a write operation; and', 'perform the write operation on a NAND cell using a modified encoding in response to the high-temperature indicator, the modified encoding including a reduced number of voltage distribution positions from an unmodified encoding without changing voltage distribution widths, the position of a voltage distribution is defined as a central tendency of a range of voltages bounded by values within half of a width of the central tendency, each voltage distribution corresponding to a discrete set of states an encoding., 'a controller to2. The NAND device of claim 1 , wherein the modified encoding includes a different voltage distribution position from a first position in the unmodified encoding to a second position in the modified encoding.3. The NAND device of claim 2 , wherein the second position is within a defined range of voltages.4. The NAND device of claim 2 , wherein the range of voltages is set defined by a read voltage for a state in the discrete set of states for the unmodified encoding that corresponds to the voltage distribution position.5. The NAND device of claim 2 , wherein the second position increases a read margin for the voltage distribution.6. The NAND device of claim 1 , wherein the unmodified encoding has eight discrete states.7. The NAND device of claim 6 , wherein the ...

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Номер записи: 99
11-03-2021 дата публикации

AUTOMATIC VENT FOR SSD COOLING ENHANCEMENT

Номер: US20210072806A1
Автор: Gong Haifeng, LIANG Xiaoguo, Sun Yanbing, Zhang Ming
Принадлежит:

Provided are devices and methods relating to temperature control in a solid state drive (SSD). A SSD () including a housing () including a plurality of sides surrounding an interior region. The SSD () includes at least one vent () on the housing (), the at least one vent () configured to be opened and closed in response to a signal. The SSD () also includes a temperature sensor and a controller, the controller configured to send a signal to open the at least one vent () when a temperature sensed inside the interior region reaches a first temperature, and the controller configured to close the at least one vent () when a temperature sensed inside the interior region reaches a second temperature, wherein the first temperature is greater than the second temperature. 1. A solid state drive (SSD) comprising:a housing including a plurality of sides surrounding an interior region;a temperature sensor; andat least one vent in the housing, the at least one vent configured to be opened and closed based on temperature data sensed by the temperature sensor.2. The solid state drive of claim 1 , the housing including a first side opposite a second side claim 1 , the at least one vent comprising a plurality of vents on the first side and a plurality of vents on the second side.3. The solid state drive of claim 1 , the at least one vent comprising a plurality of vents configured in two rows on at least one side of the housing.4. The solid state drive of claim 1 , further comprising a controller that is programmed to open the at least one vent when a first temperature is reached in the housing claim 1 , and programmed to close the at least one vent when a second temperature is reached in the housing claim 1 , the first temperature being greater than the second temperature.5. The solid state drive of claim 1 , wherein the at least one vent comprises an opening in the housing and a structure configured to impede a flow of gas into the interior region when in a closed position and to ...

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Номер записи: 100