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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 5428. Отображено 100.
02-02-2012 дата публикации

Semiconductor memory apparatus having sense amplifier

Номер: US20120026773A1
Автор: Myoung Jin LEE
Принадлежит: Hynix Semiconductor Inc

Disclosed is a semiconductor memory apparatus comprising an upper mat and a lower mat with a sense amplifier array region in between, where the sense amplifier array region includes a plurality of sense amplifiers. There is also a plurality of bit lines configured to extend toward the sense amplifier array region from the upper mat, and a plurality of complementary bit lines configured to extend toward the sense amplifier array region from the lower mat. Bit lines of the upper mat and complementary bit lines of the lower mat are configured to be alternately disposed at a predetermined interval in the sense amplifier array region, and the sense amplifier is configured to be formed between a bit line and a corresponding complementary bit line.

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Номер записи: 1
15-03-2012 дата публикации

Pre-charge sensing scheme for non-volatile memory (nvm)

Номер: US20120063238A1
Автор: Avri Harush, Oleg Dadashev, Yaal Horesh, Yoram Betser
Принадлежит: Individual

The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.

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Номер записи: 2
19-04-2012 дата публикации

Memory devices and memory systems including discharge lines and methods of forming

Номер: US20120092946A1
Автор: Jae Hee OH, Ji-Hyun Jeong, Jin-Young Kim, Ki Whan SONG
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A non-volatile memory device can include a word line that is operatively coupled to a non-volatile memory cell. A local bit line can be operatively coupled to the non-volatile memory cell. A discharge line that is associated with the local bit line can be configured to discharge the local bit line and a discharge diode can be electrically coupled between the local bit line and the discharge line.

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Номер записи: 3
07-06-2012 дата публикации

Write circuitry for hierarchical memory architectures

Номер: US20120140582A1
Автор: Anand Mishra, Nitin Jain, Siddharth Gupta
Принадлежит: STMICROELECTRONICS PVT LTD

A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

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Номер записи: 4
14-06-2012 дата публикации

Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines

Номер: US20120146132A1
Автор: Leonard Forbes
Принадлежит: Micron Technology Inc

A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration.

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Номер записи: 5
15-11-2012 дата публикации

Gain cell semiconductor memory device and driving method thereof

Номер: US20120287700A1
Автор: Yasuhiko Takemura
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A memory cell including two transistors and one capacitor, which is known as a gain cell, is improved. One electrode of the capacitor is connected to a bit line, and the other electrode thereof is connected to a drain of a write transistor. A source of the write transistor is connected to a source line. As a result, for example, in the case where a stacked capacitor is used, the one electrode of the capacitor can be part of the bit line. Only one specific write transistor is turned on when a potential of the source line and a potential of the write bit line are set; thus, only one memory cell can be rewritten.

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Номер записи: 6
29-11-2012 дата публикации

Field side sub-bitline nor flash array and method of fabricating the same

Номер: US20120299079A1
Автор: Lee Wang
Принадлежит: Individual

Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density.

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Номер записи: 7
27-12-2012 дата публикации

Semiconductor memory apparatus and bit line equalizing circuit

Номер: US20120327731A1
Автор: Mi Hyeon JO
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory apparatus comprise s bit line sense amplifier unit, and a pair of precharge elements coupled in series between a first bit line and a second bit line and having an asymmetrical contact resistance ratio.

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Номер записи: 8
03-01-2013 дата публикации

Semiconductor memory device

Номер: US20130003433A1
Автор: Tomoo Hishida, Yoshihisa Iwata
Принадлежит: Toshiba Corp

A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

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Номер записи: 9
03-01-2013 дата публикации

Semiconductor memory cell array and semiconductor memory device having the same

Номер: US20130003479A1
Автор: Sang-woong Shin, Seong-Jin Jang
Принадлежит: Individual

A semiconductor memory cell array includes a plurality of bit-lines, a plurality of word-lines, a plurality of memory cells, a plurality of dummy memory cells, a plurality of dummy bit-lines, and a plurality of dummy word-lines. The dummy bit-lines are in outer regions of the bit-lines. The dummy word-lines are in outer regions of the word-lines. The dummy bit-lines are maintained in a floating state. The dummy word-lines retain a turn-off voltage

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Номер записи: 10
14-02-2013 дата публикации

Line driver circuits, methods, and apparatuses

Номер: US20130039132A1
Автор: Howard C. Kirsch, Mingshiang Wang, Tae H. Kim, Todd A. Merritt, Yu-Wen Huang
Принадлежит: Individual

Described embodiments are directed to line drivers, such as those for providing reduced gate induced drain leakage in a memory array. Corresponding methods of operation of line drivers are also disclosed.

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Номер записи: 11
28-02-2013 дата публикации

Semiconductor memory device

Номер: US20130051170A1
Автор: Naoki Kuroda
Принадлежит: Panasonic Corp

In a static random access memory (SRAM) device having a hierarchical bit line architecture, a local sense amplifier (SA) circuit includes P-channel transistors which precharge local bit lines connected to memory cells, P-channel transistors each having a gate connected to a corresponding one of the local bit lines and a drain connected to a corresponding one of global bit lines, and N-channel transistors each having a gate connected to a corresponding one of the global bit lines and a drain connected to a corresponding one of the local bit lines. As a result, restore operation to a non-selected memory cell during write operation can be achieved without the need of a fine timing control, the speed of read operation by a feedback function can be increased, and the area can be reduced.

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Номер записи: 12
04-04-2013 дата публикации

Semiconductor device with complementary global bit lines, operating method, and memory system

Номер: US20130083592A1
Автор: Byung-ho Kang, Yong Jin Yoon, Young Jae Son
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory device includes sections arranged between a global bit line and a complementary global bit line, and having a section control unit disposed between first and second memory cell groups and connected between the global bit line and the complementary global bit line to provide a first read signal and a second read signal. A signal converter receives the first and second read signals and generates a stable controlled read signal indicative of a data value stored in the memory cell. A latch unit receives and latches the controlled read signal provided by the signal converter to generate a latched read signal.

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Номер записи: 13
18-04-2013 дата публикации

Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines

Номер: US20130095645A1
Автор: Leonard Forbes
Принадлежит: Micron Technology Inc

A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration.

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Номер записи: 14
06-06-2013 дата публикации

Semiconductor memory device

Номер: US20130141959A1
Автор: Atsushi Kawasumi
Принадлежит: Toshiba Corp

A semiconductor memory device according to an embodiment comprises: a plurality of memory cells arranged in a first direction and a second direction; local bit lines connected to group of the memory cells; a global bit line to be commonly connected to a plurality of the local bit lines; and switch circuits connected between the local bit lines and the global bit line. The switch circuits connect the global bit line to one of the local bit lines, the one of the local bit lines being electrically connected to the memory cells of the group located at a position specified by select information of the first direction and the second direction.

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Номер записи: 15
01-08-2013 дата публикации

High current capable access device for three-dimensional solid-state memory

Номер: US20130194855A1
Автор: Luiz M. Franca-Neto
Принадлежит: Individual

The present invention generally relates to three-dimensional arrangement of memory cells and methods of addressing those cells. The memory cells can be arranged in a 3D orientation such that macro cells that are in the middle of the 3D arrangement can be addressed without the need for overhead wiring or by utilizing a minimal amount of overhead wiring. An individual macro cell within a memory cell can be addressed by applying three separate currents to the macro cell. A first current is applied to the memory cell directly. A second current is applied to the source electrode of the MESFET, and a third current is applied to the gate electrode of the MESFET to permit the current to travel through the channel of the MESFET to the drain electrode which is coupled to the memory element.

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Номер записи: 16
29-08-2013 дата публикации

Memory and method of operating the same

Номер: US20130223122A1
Автор: Binghan Li, HONG Jiang, Jun Xiao, Weiran Kong, Yi Xu
Принадлежит: Grace Semiconductor Manufacturing Corp

The disclosure discloses a memory and a method of operating the same. The memory includes an array of memory cells including a plurality of memory cells with a common source, wherein each of the plurality of memory cells with a common source includes two sub-memory cells, each of the sub-memory cells corresponds to a bit line, and the respective bits are electrically independent. Each of the sub-memory cells in the memory according to the disclosure corresponds to a bit line, and the respective bit lines are electrically independent, thereby effectively avoiding interference to other memory cells which will not be programmed during a program operation.

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Номер записи: 17
29-08-2013 дата публикации

Refresh request queuing circuitry

Номер: US20130227212A1
Автор: Robert J. Proebsting
Принадлежит: Intellectual Ventures I LLC

An apparatus and system associated with memory are disclosed herein. In various embodiments, an apparatus may include first circuitry to determine a number of queued pending refresh requests for a memory bank based on a comparison of a count from a refresh-request counter to a count from a refresh-address counter; and second circuitry to set a refresh flag in response to a determination that the number of queued pending refresh requests exceeds a predetermined number. Other embodiments may be disclosed and/or claimed.

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Номер записи: 18
10-10-2013 дата публикации

Apparatuses and methods for improved memory operation times

Номер: US20130265834A1
Автор: Gary Howe, John Winegard, Vijayakrishna J. Vankayala, Vipul Surlekar
Принадлежит: Micron Technology Inc

Apparatuses and methods for improved memory cycle times are disclosed. An example apparatus may include first and second lines and a sense amplifier. The sense amplifier is directly coupled to the first and second lines. The sense amplifier may sense a differential signal between the first and second lines and amplify the same. An example method may include accessing a first memory cell coupled to a first line of a pair of lines and accessing a second memory cell coupled to a second line of the pair of lines. A differential is sensed between the pair of lines with a sense amplifier coupled directly to the pair of lines, and the sensed differential is amplified. The sense amplifier is coupled to an input/output bus to provide the amplified sensed differential to the input/output bus.

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Номер записи: 19
17-10-2013 дата публикации

Memory device from which dummy edge memory block is removed

Номер: US20130272047A1
Автор: Chul-woo Yi, Jin-seok Kwak, Joung-yeal Kim, Jung-Bae Lee, Sang-Kyun Park, Sang-Yun Kim, Seong-Jin Jang, Tai-Young Ko
Принадлежит: Individual

A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

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Номер записи: 20
07-11-2013 дата публикации

Memory Arrays

Номер: US20130294132A1
Автор: Zengtao T. Liu
Принадлежит: Micron Technology Inc

Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F 2 .

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Номер записи: 21
21-11-2013 дата публикации

Three dimensional non-volatile storage with interleaved vertical select devices above and below vertical bit lines

Номер: US20130308363A1
Автор: Chang SIAU, Roy E. Scheuerlein
Принадлежит: SanDisk 3D LLC

A three-dimensional array of memory elements reversibly change a level of electrical conductance/resistance in response to one or more voltage differences being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Local bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. Vertically oriented select devices are used to connect the local bit lines to global bit lines. A first subset of the vertically oriented select devices are positioned above the vertically oriented bit lines and a second subset of the vertically oriented select devices (interleaved with the first subset of the vertically oriented select devices) are positioned below the vertically oriented bit lines.

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Номер записи: 22
19-12-2013 дата публикации

3d memory with vertical bit lines and staircase word lines and vertical switches and methods thereof

Номер: US20130339571A1
Автор: Raul Adrian Cernea, Roy E. Scheuerlein
Принадлежит: SanDisk 3D LLC

A 3D memory with vertical local bit lines global bit lines has an in-line vertical switch in the form of a thin film transistor (TFT) formed as a vertical structure, to switch a local bit line to a global bit line. The TFT is implemented to switch a maximum of current carried by the local bit line by a strongly coupled select gate which must be fitted within the space around the local bit line. Maximum thickness of the select gate is implemented with the select gate exclusively occupying the space along the x-direction from both sides of the local bit line. The switches for odd and even bit lines of the row are staggered and offset in the z-direction so that the select gates of even and odd local bit lines are not coincident along the x-direction. The switching is further enhanced with a wrap-around select gate.

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Номер записи: 23
26-12-2013 дата публикации

Bitline for Memory

Номер: US20130343140A1
Автор: Raed Sabbah
Принадлежит: Micron Technology Inc

Subject matter disclosed herein relates to accessing memory, and more particularly to operation of a partitioned bitline.

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Номер записи: 24
02-01-2014 дата публикации

SEMICONDUCTOR DEVICE HAVING OPEN BITLINE STRUCTURE

Номер: US20140003113A1
Автор: SENO Masaki, Yamamoto Akiyoshi
Принадлежит:

Disclosed herein is a semiconductor device that includes: a plurality of memory arrays disposed in a first direction and a second direction that crosses the first direction; a plurality of row decoders disposed along a first side of the memory arrays; a plurality of first column decoders each disposed along a second side that does not face the first side of an associated one of the memory arrays; and a plurality of second column decoders each disposed along a third side that faces the second side of an associated one of the memory arrays. Each of the memory arrays is sandwiched between a corresponding one of the first column decoders and a corresponding one of the second column decoders. 1. A semiconductor device comprising:a plurality of memory mats arranged in a first direction and selected based on a mat address, the plurality of memory mats including a first memory mat disposed in one end portion of the first direction, a second memory mat disposed in the other end portion of the first direction, and a third memory mat positioned between the first and second memory mats; anda plurality of sense amplifier areas each arranged between two of the memory mats that are adjacent to each other in the first direction, each of the sense amplifier areas including a plurality of sense amplifiers, whereineach of the memory mats includes a plurality of bit lines extending in the first direction, a plurality of word lines extending in a second direction that crosses the first direction, and a plurality of memory cells disposed at intersections of the bit lines and word lines,each of the sense amplifiers is connected to an associated one of the bit lines included in an adjacent one of the memory mats on one side of the first direction, and to an associated one of the bit lines included in an adjacent one of the memory mats on the other side of the first direction,the first and third memory mats are selected when the mat address indicates a first value, andthe second and third ...

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Номер записи: 25
20-02-2014 дата публикации

Bit line sense amplifier and layout method therefor

Номер: US20140050040A1
Автор: Hyoun Mi YU
Принадлежит: SK hynix Inc

A bit line sense amplifier and a layout method therefor which can reduce coupling capacitance. The bit line sense amplifier is disposed between a first memory cell block and a second memory cell block adjacent to the first memory cell block and configured to include first and third switching elements substantially symmetrically formed in a first direction so that the drain terminals of the first and third switching elements face each other, second and fourth switching elements substantially symmetrically formed in the first direction so that the drain terminals of the second and fourth switching elements face each other, a first line configured to electrically couple the gate terminal of the first switching element and the drain terminal of the second switching element, and a second line configured to electrically couple the gate terminal of the third switching element and the drain terminal of the fourth switching element.

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Номер записи: 26
27-02-2014 дата публикации

Nonvolatile semiconductor memory device

Номер: US20140056048A1
Автор: Masayuki Ichige
Принадлежит: Toshiba Corp

This nonvolatile semiconductor memory device comprises a memory cell array configured having a plurality of memory mats arranged therein, each of the memory mats having a memory cell disposed therein at an intersection of a first line and a second line, the memory cell including a first variable resistance element. A third line extends through a plurality of the memory mats. A second variable resistance element is connected between the third line and the second line of each of the plurality of memory mats.

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Номер записи: 27
06-03-2014 дата публикации

Sram local evaluation logic for column selection

Номер: US20140063916A1
Автор: Peter T. Freiburger, Travis R. Hebig
Принадлежит: International Business Machines Corp

An SRAM includes a first SRAM column having first SRAM cells and a first local evaluation logic coupled to a global bit line and a second SRAM column having second SRAM cells and a second local evaluation logic coupled to the same global bit line. The first SRAM column is selected with a first column select line and the second SRAM column is selected with a second column select line.

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Номер записи: 28
10-04-2014 дата публикации

Volatile memory access via shared bitlines

Номер: US20140098590A1
Автор: Bao G Truong, Michael Ju Hyeok Lee
Принадлежит: International Business Machines Corp

A memory includes an array of memory cells that form rows and columns. The rows of the array include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. The two memory cells of a memory cell pair share a common intra-pair bitline. Adjacent memory cell pairs share a common inter-pair bitline. To perform a data read operation on a particular memory cell in a memory cell pair in the rows and columns of the array, wordline drive circuitry transmits wordline activate signals to select both the row for the data read operation and a particular one of the pair of memory cells for the data read operation.

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Номер записи: 29
06-01-2022 дата публикации

Two-Bit Memory Cell and Circuit Structure Calculated in Memory Thereof

Номер: US20220005525A1
Автор: CONG Wei, Lim Seow Fong
Принадлежит:

The invention relates to a two-bit memory cell structure, and an array architecture and a circuit structure thereof in an in-memory computing chip. The double-bit storage unit comprises three transistors which are connected in series, a selection transistor in the middle is used as a switch, and two charge storage transistors are symmetrically arranged on the two sides of the double-bit storage unit. A storage array formed by the double-bit storage unit is used for storing the weight of the neural network, and multiplication and accumulation operation of the neural network is carried out in a two-step current detection mode. According to the invention, leakage current can be effectively controlled, higher weight storage density and higher reliability are realized, and neural network operation with more practical significance is further realized. 1. A circuit structure of a two-bit memory cell for in-memory computing , comprising:a memory cell array consisting of two-bit memory cell structures and used for storing a weight matrix of a neural network, and the two-bit memory cell comprises: three transistors connected in series, in which the middle transistor is a select transistor used as a switch, and a first charge storage transistor and a second charge storage transistor are symmetrically placed on two sides of the select transistor; the gate electrode of the select transistor is connected to a word line, the gate electrodes of the first charge storage transistor and the second charge storage transistor are connected to respective word lines, and the drain side of the first charge storage transistor and the source side of the second charge storage transistor are respectively connected to the cell bit line and the cell source line while the source side of the first charge storage transistor and the drain side of the second charge storage transistor are respectively connected to the drain side and the source side of the select transistor; wherein the first charge ...

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Номер записи: 30
07-01-2021 дата публикации

SRAM WITH LOCAL BIT LINE, INPUT/OUTPUT CIRCUIT, AND GLOBAL BIT LINE

Номер: US20210005232A1
Автор: KATOCH Atul, Taghvaei Ali
Принадлежит:

A memory device Input/Output includes a memory cell having a local bit line. A first IO circuit is coupled to the local bit line and is configured to output a local IO signal to a global bit line. A second IO circuit is coupled to the global bit line and is configured to output a global IO signal. A latch circuit is configured to latch the local IO signal in response to a data signal on the local bit line. 1. An SRAM memory device , comprising:a memory array including an SRAM memory cell and a local bit line;a local IO circuit having a sense amplifier coupled to the local bit line and configured to generate a local IO signal based on a data signal received on the local bit line, and output a global bit line signal based on the local IO signal to a global bit line, the local IO including a latch circuit having an input terminal connected to the global bit line, wherein the latch circuit is configured to latch the global bit line signal in response to the local IO signal;a global IO circuit coupled to the global bit line and configured to receive the latched global bit line signal and output a global IO signal.2. The SRAM memory device of claim 1 , wherein the sense amplifier is configured to output the local IO signal to a latch enable terminal of the latch circuit in response to a sense amplifier enable signal.3. The SRAM memory device of claim 1 , wherein the sense amplifier is configured to output first and second complementary local IO signals claim 1 , the first and second complementary local IO signals including the local IO signal.4. The SRAM memory device of claim 3 , wherein the latch circuit includes first and second enable terminals claim 3 , which include the latch enable terminal claim 3 , coupled to receive the first and second complementary local IO signals claim 3 , respectively.5. The SRAM memory device of claim 1 , wherein the local IO circuit includes a first transistor configured to pull the global bit line signal to a first predetermined voltage ...

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Номер записи: 31
02-01-2020 дата публикации

High-Speed Memory Architecture

Номер: US20200005836A1
Автор: Bohra Fakhruddin Ali, Dasani Jitendra, Dwivedi Shri Sagar, Gupta Lalit, Nautiyal Vivek, Singla Gaurav Rattan
Принадлежит:

Various implementations described herein refer to an integrated circuit having memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays. The first pair of bank arrays may have a first number of rows, and the second pair of bank arrays have a second number of rows that is different than the first number of rows. The integrated circuit may include bank multiplexer circuitry that is coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel. The bank multiplexer circuitry may provide an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal. 1. An integrated circuit , comprising:memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays, wherein the first pair of bank arrays have a first number of rows, and wherein the second pair of bank arrays have a second number of rows that is different than the first number of rows; andbank multiplexer circuitry coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel, wherein the bank multiplexer circuitry provides an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal.2. The integrated circuit of claim 1 , wherein the second number of rows has a sum of rows that is asymmetrically balanced with a sum of rows of the first number of rows.3. The integrated circuit of claim 2 , wherein the asymmetrical balancing of the second number of rows with respect to the first number of rows provides a resistive-capacitive (RC) balancing between the multiple banks of bitcell arrays.4. The integrated circuit of claim 1 , wherein the second number of rows is less than the first number of rows.5. ...

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Номер записи: 32
02-01-2020 дата публикации

Sram input/output

Номер: US20200005837A1
Автор: Ali Taghvaei, Atul Katoch
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A memory device Input/Output includes a memory cell having a local bit line. A first IO circuit is coupled to the local bit line and is configured to output a local IO signal to a global bit line. A second IO circuit is coupled to the global bit line and is configured to output a global IO signal. A latch circuit is configured to latch the local IO signal in response to a data signal on the local bit line.

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Номер записи: 33
02-01-2020 дата публикации

MEMORY CIRCUIT AND METHOD OF OPERATING SAME

Номер: US20200005841A1
Автор: LEE Cheng Hung, LU Shih-Lien Linus, TSAI Jui-Che
Принадлежит:

A memory circuit includes a first memory cell, a second memory cell, a pre-charge circuit and a sense amplifier. The pre-charge circuit is coupled to a first bit line and a second bit line. The pre-charge circuit is configured to charge the first bit line and the second bit line to a pre-charge voltage level responsive to a first signal. The sense amplifier is coupled to the first memory cell by the first bit line, and coupled to the second memory cell by the second bit line. The sense amplifier is responsive to a second signal and a third signal. The second signal and the third signal being different from the first signal. 1. A memory circuit comprising:a first memory cell coupled to a first bit line;a second memory cell coupled to a second bit line;a pre-charge circuit coupled to the first bit line and the second bit line, the pre-charge circuit configured to charge the first bit line and the second bit line to a pre-charge voltage level responsive to a first signal; anda sense amplifier coupled to the first memory cell by the first bit line, and coupled to the second memory cell by the second bit line, the sense amplifier being responsive to a second signal and a third signal, the second signal and the third signal being different from the first signal, the sense amplifier comprising:a header switch coupled to a first supply voltage, and configured to provide the first supply voltage to the sense amplifier responsive to the second signal.2. The memory circuit of claim 1 , further comprising:a latch coupled to the sense amplifier by the first bit line, and being configured to output a random set of data based on data stored in the first memory cell and the second memory cell.3. The memory circuit of claim 1 , wherein the pre-charge circuit comprises: a first terminal of the first transistor being configured to receive the first signal;', 'a second terminal of the first transistor being coupled to the first bit line; and', 'a third terminal of the first transistor ...

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Номер записи: 34
07-01-2021 дата публикации

NONVOLATILE MEMORY DEVICE

Номер: US20210005622A1
Автор: CHO Min Kuck, LEE SEUNG HOON
Принадлежит: KEY FOUNDRY CO., LTD.

A nonvolatile memory device includes a cell array formed on a substrate, and a control gate pickup structure, wherein the cell array comprises floating gates, and a control gate surrounding the floating gates, wherein the control gate pickup structure comprises a floating gate polysilicon layer, a control gate polysilicon layer surrounding the floating gate polysilicon layer and connected to the control gate, and at least one contact plug formed on the control gate polysilicon layer. 1. A nonvolatile memory device , comprising:a cell array formed on a substrate; anda control gate pickup structure, floating gates, and', 'a control gate surrounding the floating gates,, 'wherein the cell array comprises'} a floating gate polysilicon layer,', 'a control gate polysilicon layer surrounding the floating gate polysilicon layer and connected to the control gate, and', 'at least one contact plug formed on the control gate polysilicon layer., 'wherein the control gate pickup structure comprises'}2. The nonvolatile memory device of claim 1 , wherein the control gate pickup structure further comprises a dielectric film formed between the floating gate polysilicon layer and the control gate polysilicon layer.3. The nonvolatile memory device of claim 1 , wherein the floating gates each has a long axis and a short axis claim 1 , and a direction of the long axis has a shape tilted with respect to an X-axial direction.4. The nonvolatile memory device of claim 1 , wherein the cell array further comprises:a bit line;a word line;a source line;a bit line contact formed in a first active region of the substrate; anda source line contact formed in a second active region of the substrate, whereinthe word line is connected to the at least one contact plug formed on the control gate polysilicon layer.5. The nonvolatile memory device of claim 1 , wherein the cell array comprises odd rows and even rows claim 1 , and the floating gates in the odd rows and the floating gates in the even rows have ...

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Номер записи: 35
07-01-2021 дата публикации

Three-dimensional semiconductor memory device

Номер: US20210005629A1
Автор: Bongsoon LIM, Hongsoo Jeon, Sang-Wan Nam, Sang-Won Park, Sang-Won Shim, Yonghyuk Choi
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.

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Номер записи: 36
02-01-2020 дата публикации

WORD LINE WITH AIR-GAP FOR NON-VOLATILE MEMORIES

Номер: US20200006433A1
Автор: Doyle Brian, Karpov Elijah V., Majhi Prashant, Pillarisetty Ravi, Sharma Abhishek
Принадлежит: Intel Corporation

Integrated circuits including 3D memory structures are disclosed. Air-gaps are purposefully introduced between word lines. The word lines may be horizontal or vertical. 1. An integrated circuit , comprising:a plurality of word lines (WLs), wherein said WLs are arranged in a stacked configuration with respect to one another;one or more air-gaps arranged between at least some of said WLs;a plurality of bit lines (BLs), wherein one or more said BLs intersects one or more said WLs; andan array of memory cells, at least some of the memory cells being addressable by corresponding ones of said WLs and BLs.2. The integrated circuit according to claim 1 , wherein the array of memory cells includes an RRAM (“Resistance Random Access Memory) memory configuration.3. The integrated circuit according to claim 1 , wherein the array of memory cells includes a FeFET (“Ferroelectric Field Effect Transistor”) memory configuration.4. The integrated circuit according to claim 1 , wherein said WLs are arranged parallel to an underlying wafer surface or substrate surface.5. The integrated circuit according to claim 1 , wherein said WLs are arranged perpendicular to an underlying wafer surface or substrate surface.6. The integrated circuit according to claim 1 , wherein each memory cell comprises a selector claim 1 , a metal electrode claim 1 , and an RRAM switching layer.7. The integrated circuit according to claim 6 , wherein said RRAM switching layer comprises oxygen and one or more of hafnium claim 6 , tantalum claim 6 , silicon claim 6 , and tungsten.8. The integrated circuit according to claim 1 , wherein said integrated circuit is a processor or a communication chip.9. The integrated circuit according to claim 1 , wherein said integrated circuit is part of a mobile computing device.10. An integrated circuit claim 1 , comprising:a first word line (WL) and a second WL;an air-gap between the first WL and second WL; a switching layer including an oxide material,', 'a selector layer, for ...

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Номер записи: 37
27-01-2022 дата публикации

TSV Check Circuit With Replica Path

Номер: US20220028749A1
Автор: Harutaka Makabe
Принадлежит: Micron Technology Inc

Disclosed herein is an apparatus that includes a first semiconductor chip, first and second TSVs penetrating the first semiconductor chip, a first path including the first TSV, a second path including the second TSV, a first charge circuit configured to charge the first path, a second charge circuit configured to charge the second path, a first discharge circuit configured to discharge the first path, a second discharge circuit configured to discharge the second path, and a comparator circuit configured to compare a potential of the first path with a potential of the second path.

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Номер записи: 38
27-01-2022 дата публикации

NAND FLASH MEMORY AND MANUFACTURING METHOD THEREOF

Номер: US20220028880A1
Автор: Shirota Riichiro
Принадлежит: WINBOND ELECTRONICS CORP.

A NAND flash memory capable of reducing the planar size of a memory cell is provided. The three-dimensional NAND flash memory includes a substrate, an insulating layer, a lower conductive layer (a source), a three-dimensional memory cell structure, and a bit line. The memory cell structure includes a plurality of strip-shaped gate stacks including stacks of insulators and conductors stacked along a vertical direction from the substrate; and a plurality of channel stacks separately arranged along one side of the gate stack. An upper end of the channel stack is electrically connected to the orthogonal bit line, and a lower end of the channel stack is electrically connected to the lower conductive layer. 1. A three-dimensional NAND flash memory , comprising:a substrate;a lower conductive layer formed in or on the substrate;a plurality of stacks extending along a first direction on the lower conductive layer and respectively comprising stacks of insulators and conductors stacked along a vertical direction from the substrate;a plurality of channel stacks separately arranged along one side of the plurality of stacks and respectively comprising an insulating layer comprising a charge storage layer and a channel film, the insulating layer and the channel film extending along a vertical direction from the substrate, and a lower end of the channel film being electrically connected to the lower conductive layer; anda plurality of upper conductive layers extending along a second direction orthogonal to the first direction, respectively arranged on the plurality of channel stacks, and electrically connected to an upper end of the crossed channel film.2. The flash memory according to claim 1 , whereinthe plurality of channel stacks are arranged at a first interval along the first direction, and one NAND string comprises one of the channel stacks.3. The flash memory according to claim 2 , whereinthe plurality of stacks are arranged at a second interval along the second direction, ...

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Номер записи: 39
11-01-2018 дата публикации

Memory Circuit with Leakage Compensation

Номер: US20180012668A1
Автор: Heinrich-Barna Stephen Keith, Rao Raviprakash Suryanarayana
Принадлежит:

A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line. 1. A memory array , comprising the steps of:a word line;a bit line;a plurality of memory cells, wherein each memory cell has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal;a first memory cell of the plurality of memory cells having the second terminal coupled to receive a first supply voltage when selected by the word line; anda second memory cell of the plurality of memory cells having the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.2. The memory array of claim 1 , wherein the voltage different from the first supply voltage is substantially equally to a second supply voltage less a transistor threshold voltage.3. The memory array of claim 1 , wherein the memory cells are flash electrically programmable erasable memory cells.4. The memory array of claim 1 , wherein the memory cells are read only memory (ROM) cells. This continuation application claims priority to U.S. patent application Ser. No. 15/050,678, filed Feb. 23, 2016, which application is hereby incorporated herein by reference.The present embodiments relate to a memory circuit with leakage compensation of unselected memory cells.Shrinking semiconductor integrated circuit feature sizes have placed increasing challenges on semiconductor ...

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Номер записи: 40
09-01-2020 дата публикации

ADJUSTABLE ACCESS ENERGY AND ACCESS LATENCY MEMORY SYSTEM AND DEVICES

Номер: US20200012429A1
Автор: Linstadt John Eric, Ware Frederick A.
Принадлежит:

Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed. 1. (canceled)2. A method of operating a memory controller , comprising:transmitting a plurality of commands, to a memory device, the plurality of commands to access, utilizing at least a first plurality and a second plurality of memory array tiles, respective blocks of data having a first size, the respective blocks of data being stored in different formats, the first plurality and the second plurality to be different numbers of memory array tiles.3. The method of claim 2 , wherein the second plurality of memory array tiles includes at least twice the number of memory array tiles as the first plurality of memory array tiles.4. The method of claim 2 , wherein the first plurality and second plurality of memory array tiles include sense amplifiers claim 2 , and accessing the memory array tiles includes a row access that places data stored by a sub-row of storage cells into sense amplifiers of a utilized memory array tile claim 2 , and accessing the memory array tiles also includes a column access operation that moves data between the sense amplifiers and an interface.5. The method of claim 4 , wherein accessing utilizing the first plurality of memory array tiles comprises at least twice the number of column ...

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Номер записи: 41
11-01-2018 дата публикации

ELECTRONIC DEVICE

Номер: US20180012936A1
Автор: Kang Hee-Sung
Принадлежит:

An electronic device is provided to comprise a semiconductor memory unit that comprises: a substrate including active regions, which are extended in a second direction and disposed from each other in a first direction; a plurality of gates extended in the first direction and across with the active regions; a lower contact disposed in both sides of gates and coupling the active regions in the first direction; an upper contact of the lower contact overlapping with the active region out of the active regions in a side of each gate, and overlapping with the active regions in the other side of each gate; and first and second interconnection lines coupled to the upper contact, extended in the second direction, and being alternately disposed from each other in the first direction, wherein the upper contact of a side of the gates has a zigzag shape in a first oblique direction. 120-. (canceled)21. An electronic device comprising a semiconductor memory unit that comprises:a plurality of memory cells;a mat region having N number of first interconnection lines coupled to terminals of the plurality of memory cells; anda switching region for controlling a coupling between each of the N number of first interconnection lines and an external region,wherein the switching region comprises:a substrate having N number of second active regions, which are extended in a second direction and are disposed from each other in a first direction across the second direction;N number of second gates extended in the first direction and across the N number of second active regions;a second lower contact disposed in both sides of each of the N number of second gates and coupling the N number of second active regions in the first direction;a second upper contact overlapping with a corresponding second active region out of the N number of second active regions in a side of each of the N number second gates, and disposed to have a zigzag shape in a first oblique direction;a third upper contact ...

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Номер записи: 42
10-01-2019 дата публикации

Semiconductor device and method for fabricating the same

Номер: US20190013357A1
Автор: Jeong Hee Park, Jong Uk Kim, Jung Moo Lee, Seong Geon PARK, Soon Oh PARK
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a first memory cell, a second memory cell, a first capping film, and a second capping film. The first memory cell includes a first ovonic threshold switch (OTS) on a first phase change memory. The second memory cell includes a second OTS on a second phase change memory. The first capping film is on side surfaces of the first and second memory cells. The second capping film is on the first capping film and fills a space between the first and second memory cells.

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Номер записи: 43
09-01-2020 дата публикации

Semiconductor memory device

Номер: US20200013435A1
Автор: Jumpei Sato
Принадлежит: Toshiba Memory Corp

A semiconductor memory device includes n interconnect layers above a substrate; and a first interconnect region between an end of a control circuit and an end of the substrate in a direction of a first axis beside a first pad region in a direction of a second axis. The n interconnect layers are located at different levels from the substrate. Each of the n interconnect layers includes an interconnect. The first interconnect region includes no transistor, and no contact coupled to the substrate. The first interconnect region includes an interconnect extending along the second axis in m (m is a natural number equal to or larger than 3, larger than n/2, and equal to or smaller than n) interconnect layers of the n interconnect layers.

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Номер записи: 44
09-01-2020 дата публикации

HIGH SPEED INTERLEAVER/DEINTERLEAVER DEVICE SUPPORTING LINE RATE, AND METHOD THEREOF

Номер: US20200014490A1
Автор: Bhat Sri, LIU Yanlai, Subramaniam Bala
Принадлежит: HUGHES NETWORK SYSTEMS, LLC

A deinterleaver device, a method for deinterleaving, an interleaver device, and a method for interleaving are disclosed. The method for deinterleaving includes: providing a memory and a stream count for a frame; virtually dividing the memory into equal sections, wherein a section count equals the stream count; calculating a write address for a sample of the samples based on a location of the sample in the frame and a correspondence of the location to one of the sections; receiving the sample; and writing the received sample to the write address, wherein the calculating and the write address corresponds to a correct deinterleaving location in one of the sections for the sample. 121-. (canceled)22. A method for interleaving soft decisions for a frame , the method comprising:providing a memory and a stream count selected from n-different supported stream counts;virtually dividing the memory into x-rows, y-columns and the y-columns into equal sections, wherein y is calculated as a common denominator of a majority of the n-different counts, x is at least a length of samples divided by y, and the y-columns are subdivided into equal sections wherein a section count equals the stream count;collecting soft decisions sequentially, wherein the soft decisions number less than or equal to a frame size of the frame;calculating, for each respective soft decision, a write address comprising a row of the x-rows and a column of the y-columns based on a location of the respective soft decision, wherein a next column of the y-columns is set as the column every x soft decisions; andwriting the respective soft decision to a respective write address of the memory.23. The method of claim 22 , wherein a frame length of the soft-decisions in the frame is variable.24. The method of claim 22 , wherein the frame comprises 64 claim 22 ,800 soft-decisions claim 22 , each soft decision of the soft decisions is 6-bits claim 22 , the frame is modulated using a modulation type having 1 claim 22 , 2 ...

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Номер записи: 45
19-01-2017 дата публикации

CIRCUITS FOR DRIVING DATA LINES

Номер: US20170018303A1
Автор: HUANG Chia-En, LEE Cheng Hung, Lin Geng-Cing, YANG Hao-I, YANG Jung-Ping
Принадлежит:

A circuit includes: a first data line; a second data line; a write driver including first and second transistors; a first switch connected in series with the first transistor to form a first series-connected pair; a second switch in series with the second transistor to form a second series-connected pair; and a level shifter which includes the first and second transistors. The first series-connected pair is coupled between a first voltage node and the first data line. The second series-connected pair is coupled between the first voltage node and the second data line. Gate terminals of the first and second transistors are correspondingly cross-coupled with the second and first data lines. 1. A circuit comprising:a first data line;a second data line;a write driver including first and second transistors;a first switch connected in series with the first transistor to form a first series-connected pair;a second switch in series with the second transistor to form a second series-connected pair; anda level shifter which includes the first and second transistors; the first series-connected pair is coupled between a first voltage node and the first data line;', 'the second series-connected pair is coupled between the first voltage node and the second data line; and', 'gate terminals of the first and second transistors are correspondingly cross-coupled with the second and first data lines., 'wherein2. The circuit of claim 1 , wherein: a first terminal of the first transistor is coupled to the first voltage node;', 'a second terminal of the first transistor is coupled to a first terminal of the first switch; and', 'a second terminal of the first switch is coupled to the first data line; and', 'for the second series-connected pair:', 'a first terminal of the second transistor is coupled to the first voltage node;', 'a second terminal of the second transistor is coupled to a first terminal of the second switch; and', 'a second terminal of the second switch is coupled to the ...

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Номер записи: 46
21-01-2016 дата публикации

Semiconductor device

Номер: US20160020217A1
Автор: Jae Kwan Kwon
Принадлежит: SK hynix Inc

A semiconductor device includes a first vertical memory string connected to a common source line, a second vertical memory string connected to a bit line, a pipe transistor suitable for selectively connecting the first and second vertical memory strings based on a block selection signal, and a plurality of transistors suitable for selectively connecting local lines of the first and second vertical memory strings to corresponding global lines based on the block selection signal.

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Номер записи: 47
17-01-2019 дата публикации

Non-volatile (nv) memory (nvm) matrix circuits employing nvm matrix circuits for performing matrix computations

Номер: US20190019538A1
Автор: Bin Yang, Gengming Tao, Xia Li
Принадлежит: Qualcomm Inc

Non-volatile (NV) memory (NVM) matrix circuits employing NVM circuits for performing matrix computations are disclosed. In exemplary aspects disclosed herein, an NVM matrix circuit is provided that has a plurality of NVM storage string circuits each comprising a plurality of NVM bit cell circuits each configured to store a memory state. Each NVM bit cell circuit has a stored memory state represented by a resistance, and includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector of 1×m size for example. Activation of the gate of a given NVM bit cell circuit controls whether its resistance is contributed to a respective source line. This causes a summation current to be generated on each source line based on the weighted summed contribution of each NVM bit cell circuit's resistance to its respective source line.

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Номер записи: 48
17-01-2019 дата публикации

MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20190019542A1
Автор: Chang Wei-Che, TANAKA Yoshinori
Принадлежит: WINBOND ELECTRONICS CORP.

Provided is a memory device including a substrate, isolation structures, conductive pillars, and bit-line structures. The substrate includes active areas. The active areas are arranged as a first array. The isolation structures are located in the substrate and extending along a Y direction. Each of the isolation structures is arranged between the active areas in adjacent two columns. The conductive pillars are located on the substrate and arranged as a second array. The conductive pillars in adjacent two rows are in contact with the active areas arranged as the same column, to form a first contact region and a second contact region. The bit-line structures are arranged on the substrate in parallel along a X direction. Each of the bit-line structures is in contact with the active areas arranged as the same column, to form a third contact region between the first and second regions. 1. A manufacturing method of a memory device , comprising:forming a plurality of first isolation structures in a substrate, wherein the first isolation structures separate the substrate into a plurality of strip patterns, and the strip patterns are bent or straight;forming a plurality of word line sets in the substrate, wherein the word line sets are extended along a Y direction and pass through the first isolation structures and the strip patterns to divide the substrate into a plurality of first regions and a plurality of second regions, and the first regions and the second regions are alternately arranged along an X direction and the word line sets are located in the first regions;forming a first dielectric pattern on the substrate, wherein the first dielectric pattern covers the word line sets and exposes a surface of the substrate of the second regions;forming a conductive layer on the substrate of the second regions, wherein a top surface of the conductive layer is lower than a top surface of the first dielectric pattern;forming a plurality of second isolation structures in the ...

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Номер записи: 49
17-01-2019 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

Номер: US20190019555A1
Автор: CHO Byeong Kyu, LEE Hee Youl
Принадлежит:

Disclosed are a semiconductor memory device and an operating method thereof. The semiconductor memory device includes: a memory cell array including a plurality of memory blocks sharing one or more drain select lines; a peripheral circuit configured to perform a program operation on the memory cell array; and a control logic configured to control the peripheral circuit to coding-program one or more drain select transistors included in each of the plurality of memory blocks. 1. A semiconductor memory device , comprising:a memory cell array including a plurality of memory blocks sharing one or more drain select lines;a peripheral circuit configured to perform a program operation on the memory cell array; anda control logic configured to control the peripheral circuit to coding-program one or more drain select transistors included in each of the plurality of memory blocks.2. The semiconductor memory device of claim 1 , wherein the peripheral circuit performs the program operation so that the one or more drain select transistors included in each of the plurality of memory blocks have different coding data claim 1 , respectively.3. The semiconductor memory device of claim 1 , wherein each of the plurality of memory blocks includes one or more connection control transistors serially connected between a bit line and a common source line claim 1 , the one or more drain select transistors claim 1 , a plurality of memory cells claim 1 , and a source select transistor.4. The semiconductor memory device of claim 3 , wherein the plurality of memory blocks shares a connection control line connected to the one or more connection control transistors claim 3 , the one or more drain select lines connected to the one or more drain select transistors claim 3 , and a plurality of word lines connected to the memory cells.5. The semiconductor memory device of claim 3 , wherein the source select transistors included in the plurality of memory blocks are connected to the electrically ...

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Номер записи: 50
22-01-2015 дата публикации

Memory device and read operation method thereof

Номер: US20150023120A1
Автор: Chia-Jung Chen, Chin-Hung Chang, Ken-Hui Chen, Kuen-Long Chang, Su-Chueh Lo
Принадлежит: Macronix International Co Ltd

A read operation for a memory device is provided. A selected word line, first and second global bit line groups and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit line groups are kept precharged.

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Номер записи: 51
16-01-2020 дата публикации

Balanced Coupling Structure for Physically Unclonable Function (PUF) Application

Номер: US20200020364A1
Автор: Cheng Hung Lee, Jui-che Tsai, Shih-Lien Linus Lu, Yi-Ju Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A memory storage device is fabricated using a semiconductor fabrication process. Often times, manufacturing variations and/or misalignment tolerances present within the semiconductor fabrication process can cause the memory storage device to differ from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process. For example, uncontrollable random physical processes in the semiconductor fabrication process can cause small differences, such as differences in doping concentrations, oxide thicknesses, channel lengths, structural widths, and/or parasitics to provide some examples, between these memory storage devices. These small differences can cause bitlines within the memory storage device to be physically unique with no two bitlines being identical. As a result, the uncontrollable random physical processes in the semiconductor fabrication process can cause electronic data read from the memory storage device to propagate along the bitlines at different rates. This physical uniqueness of the bitlines can be utilized to implement a physical unclonable function (PUF) allowing the memory storage device to be differentiated from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process.

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Номер записи: 52
16-01-2020 дата публикации

DATA DEPENDENT KEEPER ON GLOBAL DATA LINES

Номер: US20200020370A1
Автор: IQBAL Md Nadeem, SREENIVASULA REDDY Dhani Reddy
Принадлежит:

The present disclosure relates to a structure which includes at least one keeper circuit which is configured to hold data to a precharged state during a first operation and be disabled during a second operation. 1. A structure comprising at least one keeper circuit which is configured to hold data to a precharged state during a first operation and be disabled during a second operation ,wherein the at least one keeper circuit comprises a first transistor which is directly gated by a sense amplifier enable signal and a second transistor which is gated by an inverted digital line true signal, and further comprising:a third transistor which has a drain connected to a drain of the second transistor, a source directly connected to ground, and is gated by the inverted digital line true signal.2. (canceled)3. The structure of claim 1 , wherein the first transistor is between a power supply signal and a source of the second transistor and the second transistor is between the first transistor and the drain of the third transistor.4. The structure of claim 3 , wherein the first transistor and the second transistor are PMOS transistors and the third transistor is a NMOS transistor.5. The structure of claim 4 , wherein the drain of the second transistor is connected to a read global data line signal.6. The structure of claim 5 , further comprising a RC component connected to the read global data line signal.7. (canceled)8. The structure of claim 1 , further comprising a sense amplifier circuit which is connected to the at least one keeper circuit.9. The structure of claim 8 , wherein the at least one keeper circuit is configured to hold data to the precharged state when the sense amplifier circuit is fired.10. A circuit claim 8 , comprising:a sense amplifier circuit comprising at least one keeper circuit which is clocked with a sense amplifier enable signal, holds data to a precharged state during a precharge operation, and is disabled during an evaluating operation; anda ...

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Номер записи: 53
16-01-2020 дата публикации

VERTICAL MEMORY CELLS AND MEMORY DEVICES USING THE SAME

Номер: US20200020377A1
Автор: KUO Shih-Chi, Mo Chun-Chieh
Принадлежит:

Vertical memory cells and memory devices using the same are disclosed. In one example, a memory cell formed on a backend layer over a substrate is disclosed. The memory cell includes: a first electrode, a second electrode and a magnetic tunnel junction. The first electrode has sidewalls and a bottom surface disposed over the backend layer. The second electrode has sidewalls and a bottom surface in contact with the backend layer. The magnetic tunnel junction is formed between the first electrode and the second electrode. The magnetic tunnel junction is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode. 1. A method for fainting a memory cell on a backend layer , comprising:forming a first electrode with sidewalls and a bottom surface over the backend layer;fainting a magnetic tunnel junction layer over the first electrode;forming, over the magnetic tunnel junction layer, a second electrode with sidewalls and a bottom surface in contact with the backend layer, wherein the magnetic tunnel junction is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode; andforming a first conductive line that extends along a first direction over the backend layer and electrically connects the first electrode with an electrode of a first neighbor memory cell on the backend layer.2. The method of claim 1 , wherein:the backend layer extends in a second direction; andthe magnetic tunnel junction extends in a third direction substantially perpendicular to the second direction.3. The method of claim 1 , further comprising:forming a second conductive line that extends along a second direction through the backend layer and electrically connects the second electrode with an electrode of a second neighbor memory cell under the backend layer.4. The method of claim 3 , wherein:one of the first and second conductive lines is a bit line; andthe other one of the first and second conductive lines is a word line.5. ...

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Номер записи: 54
21-01-2021 дата публикации

Implementations to store fuse data in memory devices

Номер: US20210020218A1
Автор: Anna Maria Conti, Innocenzo Tortorelli, Mario Allegra, Mattia Boniardi, Mattia Robustelli
Принадлежит: Micron Technology Inc

Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.

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Номер записи: 55
21-01-2021 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20210020655A1
Автор: NAKATSUKA Keisuke, YOSHIMURA Naoya
Принадлежит: Kioxia Corporation

A semiconductor memory device according to an embodiment includes a substrate, first to eleventh conductive layers, first and second pillars, and first to fourth insulating regions. The first insulating regions are provided between the third and fifth conductive layers and between the fourth and sixth conductive layers. The second insulating regions are provided between the eighth and tenth conductive layers and between the ninth and eleventh conductive layers. The third insulating region is provided between the third to sixth conductive layers and the eighth to eleventh conductive layers. The fourth insulating region is provided between the second and seventh conductive layers. The fourth insulating region is separated from the third insulating region in a planar view. 1. A semiconductor memory device comprising:a substrate;a first conductive layer provided above the substrate;a second conductive layer provided above the first conductive layer;a third conductive layer and a fourth conductive layer provided above the second conductive layer, the third conductive layer and the fourth conductive layer being separated from each other in a first direction;a fifth conductive layer provided in the same level of a layered structure as the third conductive layer above the second conductive layer, the fifth conductive layer being separated from the third conductive layer;a sixth conductive layer provided in the same level of the layered structure as the fourth conductive layer above the second conductive layer, the sixth conductive layer being separated from the fourth conductive layer;a plurality of first insulating regions provided between the third conductive layer and the fifth conductive layer and between the fourth conductive layer and the sixth conductive layer, along a second direction intersecting the first direction;a first pillar provided between the first insulating regions and penetrating the second conductive layer along the first direction, the first pillar ...

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Номер записи: 56
10-02-2022 дата публикации

SEMICONDUCTOR MEMORY DEVICES

Номер: US20220045094A1
Автор: HONG Jaeho, KIM Hyuncheol, Kim Yongseok, LEE Kyunghwan, SEO Hyeoungwon, YOO Sungwon
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor memory device includes a word line extending in a vertical direction on a substrate, a channel layer surrounding the word line to configure a cell transistor and having a horizontal ring shape with a predetermined horizontal width, a bit line disposed at one end of the channel layer in a first horizontal direction and extending in a second horizontal direction perpendicular to the first horizontal direction, and a cell capacitor disposed at other end of the channel layer in the first horizontal direction, the cell capacitor including an upper electrode layer extending in the vertical direction, a lower electrode layer surrounding the upper electrode layer, and a capacitor dielectric layer disposed between the upper electrode layer and the lower electrode layer. 1. A semiconductor memory device comprising:a word line extending in a vertical direction on a substrate;a channel layer surrounding the word line to configure a cell transistor and having a horizontal ring shape with a predetermined horizontal width;a bit line disposed at one end of the channel layer in a first horizontal direction and extending in a second horizontal direction perpendicular to the first horizontal direction; anda cell capacitor disposed at other end of the channel layer in the first horizontal direction, the cell capacitor including an upper electrode layer extending in the vertical direction, a lower electrode layer surrounding the upper electrode layer, and a capacitor dielectric layer disposed between the upper electrode layer and the lower electrode layer.2. The semiconductor memory device of claim 1 , wherein an inner surface of the lower electrode layer comprises an electrode hole extending along a perimeter of the upper electrode layer and having a concave shape.3. The semiconductor memory device of claim 1 , wherein the lower electrode layer comprises a vertical cross-sectional surface having a U-shape rotated by 90 degrees.4. The semiconductor memory device of claim ...

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Номер записи: 57
23-01-2020 дата публикации

STACKED MEMORY DEVICES, MEMORY SYSTEMS AND METHODS OF OPERATING STACKED MEMORY DEVICES

Номер: US20200027521A1
Автор: Choi Ahn
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A stacked memory device includes a buffer die, a plurality of memory dies stacked on the buffer die and a plurality of through silicon vias (TSVs). The buffer die communicates with an external device. The TSVs extend through the plurality of memory dies to connect to the buffer die. Each of memory dies includes a memory cell array which includes a plurality of dynamic memory cells coupled to a plurality of word-lines and a plurality of bit-lines. The buffer die includes a test circuit, and the test circuit, in a test mode, performs a test on the dynamic memory cells of a target memory die corresponding to one of the memory dies and store, an address of a memory cell row including at least one defective cell, in at least one column decoder of other memory dies of except the target memory die. 1. A stacked memory device comprising:a buffer die configured to communicate with at least one external device, the buffer die including a test circuit;a plurality of memory dies stacked on the buffer die, each of the plurality of memory dies including a memory cell array, the memory cell array including a plurality of dynamic memory cells coupled to a plurality of word-lines and a plurality of bit-lines;a plurality of through silicon vias (TSVs) extending through the plurality of memory dies and connected to the buffer die; and perform a test on the dynamic memory cells of a target memory die corresponding to at least one of the plurality of memory dies, the test to detect at least one defective cell of the target memory die, and', 'store, as fail address information, an address of a memory cell row including the at least one defective cell detected through the test, in at least one column decoder of another memory die of the plurality of memory dies, the another memory die not being the target memory die., 'the test circuit, during a test mode of the stacked memory device, is configured to,'}2. The stacked memory device of claim 1 , wherein each of the plurality of memory dies ...

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Номер записи: 58
28-01-2021 дата публикации

DATA PROCESSING SYSTEM AND METHOD FOR GENERATING A DIGITAL CODE WITH A PHYSICALLY UNCLONABLE FUNCTION

Номер: US20210027814A1
Автор: Garni Brad John, Hoefler Alexander, Mahatme Nihaar N.
Принадлежит:

A data processing system and method for generating a digital code for use as a physically unclonable function (PUF) response is provided. The method includes activating a plurality of word lines for a read operation. A first bit line is coupled to a first input of a comparator during the read operation. A second bit line is coupled to a second input of the comparator during the read operation. A current is generated on each of the first and second bit lines. The currents on the first and second bit lines are converted to voltages. The voltage on the first bit line is compared to the voltage on the second bit line. A logic bit is output from the comparator as part of the digital code, a logic state of the logic bit is determined in response to the comparison. By selecting multiple word lines to determine a PUF response, noise immunity is improved. 1. A method for generating a digital code , the method comprising:activating a plurality of word lines at the same time in a memory array for a read operation of a single logic bit, wherein the memory array includes a plurality of bit lines intersecting with the plurality of word lines, a bit cell of a plurality of bit cells being located at each intersection of the plurality of word lines and the plurality of bit lines;coupling a first bit line of the memory array to a first input of a comparator during the read operation;coupling a second bit line of the memory array to a second input of the comparator during the read operation, the second bit line is coupled to different bit cells than the first bit line;coupling a third bit line to the first bit line and coupling a fourth bit line to the second bit line during the read operation of the single logic bit;generating a signal on each of the first, second, third, and fourth bit lines;comparing the signal on the first bit line and third bit line to the signal on the second bit line and fourth bit line; andoutputting the single logic bit from the comparator as part of the ...

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Номер записи: 59
28-01-2021 дата публикации

PROCESSING ARRAY DEVICE THAT PERFORMS ONE CYCLE FULL ADDER OPERATION AND BIT LINE READ/WRITE LOGIC FEATURES

Номер: US20210027815A1
Автор: Chang Chao-Hung, HAIG Bob, SHU Lee-Lean
Принадлежит: GSI Technology, Inc.

A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed. 1. A method , comprising:providing a processing array having two read bit lines, an array of memory cells having a plurality of rows of memory cells and a plurality of columns of memory cells, each memory cell having a storage cell, each read bit line connecting to a particular one or more columns of memory cells in the memory cell array and a column of memory cells in the array being connected to the two read bit lines and bit line read/write circuitry connected to the two read bit lines that are connected to the column of memory cells and having a latch;isolating, by an isolation circuit in each memory cell, the storage cell in the memory cell from the signals on the two read bit lines; andperforming, using the bit line read/write circuitry connected to the two read bit lines that are connected to the column of memory cells and the latch, a full adder operation in a single clock cycle.2. The method of further comprising storing claim 1 , on a first read bit line of the two read bit lines claim 1 , a first input of the full adder operation and storing claim 1 , a second read bit line of the two read bit lines an inverted second input of the full adder operation and storing claim 1 , by the latch claim 1 , a carry input of the full adder operation.3. The method of further comprising combining claim 2 , by an exclusive OR gate that is part of the bit line read/write circuitry claim 2 , the first input of the full adder operation and the carry input of the full adder operation to generate a Y1 output claim 2 , inverting the inverted second input of the full adder operation to generate a second input of the full adder operation claim 2 , logically ANDing the Y1 output and the inverted second input of the full adder operation to generate a first output and logically ANDing the Y1 signal and ...

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Номер записи: 60
28-01-2021 дата публикации

SEMICONDUCTOR DEVICES

Номер: US20210028109A1
Автор: Cho Uk Rae, Choi Kyu Won, Jung Woo Jin, Lee Chan Ho, Youn Suk
Принадлежит:

A semiconductor device includes a substrate including a first cell region, a second cell region adjacent to the first cell region in a first direction, and a comparison region adjacent the first and second cell regions in a second direction, a bit line in a first metal level on the substrate and extending in the first direction, and a first ground rail in a second metal level different from the first metal level. The first ground rail comprises a first sub-ground rail extending in the second direction on the first cell region, a second sub-ground rail extending in the second direction on the second cell region, a third sub-ground rail connecting the first sub-ground rail to the second sub-ground rail on the first and second cell regions, and a fourth sub-ground rail that branches off from the third sub-ground rail and extends in the second direction. 1. A semiconductor device comprising:a substrate comprising a first cell region, a second cell region that is adjacent the first cell region in a first direction, and a comparison region that is adjacent the first and second cell regions in a second direction different from the first direction;a bit line in a first metal level on the substrate, the bit line extending in the first direction; anda first ground rail in a second metal level different from the first metal level,wherein the first ground rail comprises a first sub-ground rail extending in the second direction on the first cell region,a second sub-ground rail extending in the second direction on the second cell region,a third sub-ground rail connecting the first sub-ground rail to the second sub-ground rail on the first and second cell regions, anda fourth sub-ground rail that branches off from the third sub-ground rail and extends in the second direction.2. The semiconductor device of claim 1 , wherein the third sub-ground rail extends in the first direction.3. The semiconductor device of claim 1 , wherein the third sub-ground rail comprises:a first portion ...

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Номер записи: 61
04-02-2016 дата публикации

Low power consumption memory device

Номер: US20160034220A1
Автор: Chih-Cheng Hsiao
Принадлежит: Individual

A memory device includes a plurality of memory modules and a plurality of control lines. Each memory module includes a plurality of memory units. Each memory unit includes: a plurality of memory cell groups, each of which includes at least one memory cell; a plurality of first bit lines, each of which is coupled to the at least one memory cell of a respective memory cell group; a second bit line; and a plurality of controllable circuits, each of which has an input terminal coupled to a respective first bit line, an output terminal coupled to the second bit line, and a control terminal. Each control line is coupled to the control terminal of a corresponding controllable circuit of each of at least one memory unit of each memory module. The memory device consumes relatively small power.

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Номер записи: 62
05-02-2015 дата публикации

Nonvolatile semiconductor memory device including memory cell array with pseudo separate source line structure

Номер: US20150035032A1
Автор: Chan-kyung Kim, Dong-seok Kang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory cell array of a nonvolatile semiconductor memory device is provided which includes a first memory cell including a first variable resistance element and a first access transistor connected to each other, and having a first node connected to a first bit line and one end of the first variable resistance element and a second node connected to a second bit line and one end of the first access transistor; and a second memory cell including a second variable resistance element and a second access transistor connected to each other, and having a first node connected to the second bit line and one end of the second variable resistance element and a second node connected to one end of the second access transistor, wherein the first and second access transistors are connected to first and second word lines, respectively.

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Номер записи: 63
01-05-2014 дата публикации

Semiconductor device, control method thereof and data processing system

Номер: US20140119143A1
Автор: Kyoichi Nagata
Принадлежит: Longitude Semiconductor SARL

Disclosed herein is a semiconductor device comprising a global bit line, a first local bit line coupled to normal memory cells, a second local bit line coupled to redundant memory cells first and second hierarchical switches, a precharge circuit precharging the global bit line, a redundancy determination circuit determining whether or not an accessed address matches a defective address, and a control circuit. In a standby state, the global bit line and the second local bit line are precharged through the second hierarchical switch. In an active state, the first local bit line is precharged through the first hierarchical switch, subsequently when the redundancy determination circuit determines that the addresses do not match, the second hierarchical switch is inactivated to access the normal memory cells, and when the redundancy determination circuit determines that the addresses match each other, the first hierarchical switch is inactivated to access the redundant memory cells.

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Номер записи: 64
17-02-2022 дата публикации

Three-Dimensional Memory Device and Method

Номер: US20220052060A1
Автор: Chia Han-Jong, Lin Yu-Ming, Wang Sheng-Chen, Yeong Sai-Hooi, Young Bo-Feng
Принадлежит:

In an embodiment, a device includes: a first dielectric layer having a first sidewall; a second dielectric layer having a second sidewall; a word line between the first dielectric layer and the second dielectric layer, the word line having an outer sidewall and an inner sidewall, the inner sidewall recessed from the outer sidewall, the first sidewall, and the second sidewall; a memory layer extending along the outer sidewall of the word line, the inner sidewall of the word line, the first sidewall of the first dielectric layer, and the second sidewall of the second dielectric layer; and a semiconductor layer extending along the memory layer. 1. A device comprising:a first dielectric layer having a first sidewall;a second dielectric layer having a second sidewall;a word line between the first dielectric layer and the second dielectric layer, the word line having an outer sidewall and an inner sidewall, the inner sidewall recessed from the outer sidewall, the first sidewall, and the second sidewall;a memory layer extending along the outer sidewall of the word line, the inner sidewall of the word line, the first sidewall of the first dielectric layer, and the second sidewall of the second dielectric layer; anda semiconductor layer extending along the memory layer.2. The device of claim 1 , wherein the word line has a connecting surface extending between the outer sidewall and the inner sidewall claim 1 , the connecting surface and the inner sidewall forming a right angle.3. The device of claim 1 , wherein the word line has a connecting surface extending between the outer sidewall and the inner sidewall claim 1 , the connecting surface and the inner sidewall forming an obtuse angle.4. The device of claim 1 , wherein the word line has a connecting surface extending between the outer sidewall and the inner sidewall claim 1 , the connecting surface and the inner sidewall forming a sharp corner.5. The device of claim 1 , wherein the word line has a connecting surface ...

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Номер записи: 65
17-02-2022 дата публикации

RESISTIVE RANDOM ACCESS MEMORY DEVICES

Номер: US20220052114A1
Автор: Loy Desmond Jia Jun, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a first electrode, a dielectric cap above the first electrode, a second electrode laterally adjacent to the first electrode, in which an upper surface of the second electrode is substantially coplanar with an upper surface of the dielectric cap, and a resistive layer between the first electrode and the second electrode. An edge of the first electrode is electrically coupled to an edge of the second electrode by at least the resistive layer. 1. A memory device comprising:a first electrode;a dielectric cap above the first electrode;a second electrode laterally adjacent to the first electrode, wherein an upper surface of the second electrode is substantially coplanar with an upper surface of the dielectric cap; anda resistive layer between the first electrode and the second electrode;wherein an edge of the first electrode is electrically coupled to an edge of the second electrode by at least the resistive layer .2. The device of claim 1 , wherein the resistive layer includes a conductive path configured to form between the edge of the first electrode and the edge of the second electrode in response to a change in an electric signal.3. The device of claim 1 , wherein the resistive layer conforms to sidewalls and a lower surface of the second electrode.4. The device of claim 3 , wherein the lower surface of the second electrode is positioned between an upper surface and a lower surface of the first electrode.5. The device of claim 3 , wherein the lower surface of the second electrode is substantially coplanar with an upper surface of the first electrode.6. The device of claim 1 , further comprising an oxygen scavenging layer between the first electrode and the second electrode claim 1 , wherein the oxygen scavenging layer is ...

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Номер записи: 66
04-02-2021 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20210036005A1
Автор: OH Sung Lae
Принадлежит:

A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a source plate defined with a cell area and a connection area in a first direction; a vertical channel passing through the electrode structure in the cell area; a hard mask pattern disposed on the electrode structure in the connection area, and having a plurality of opening holes; a plurality of contact holes defined in the electrode structure under the opening holes, and exposing pad areas of the electrode layers; and a slit dividing the hard mask pattern into units smaller than the electrode structure in the connection area. 1. A semiconductor memory device comprising:an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a source plate defined with a cell area and a connection area in a first direction;a vertical channel passing through the electrode structure in the cell area;a hard mask pattern disposed on the electrode structure in the connection area, and having a plurality of opening holes;a plurality of contact holes defined in the electrode structure under the opening holes, and exposing pad areas of the electrode layers; anda slit dividing the hard mask pattern into units smaller than the electrode structure in the connection area.2. The semiconductor memory device according to claim 1 , wherein the electrode structure has a line shape extending in a first direction claim 1 , and one or more units of the hard mask pattern are arranged in the first direction.3. The semiconductor memory device according to claim 2 , further comprising:a bit line coupled to the vertical channel and disposed on the hard mask pattern,wherein the bit line extends in a second direction, which intersects with the first direction to form a plane substantially parallel to a surface of the electrode structure or ...

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Номер записи: 67
04-02-2021 дата публикации

SEMICONDUCTOR DEVICES AND METHODS OF OPERATING THE SAME

Номер: US20210036011A1
Автор: HAN Jeehoon, KANG SEOGOO, SON YOUNGHWAN
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor device is disclosed. The semiconductor device includes a channel structure on a substrate and extending in a first direction perpendicular to a top surface of the substrate; a plurality of gate electrodes on the substrate and spaced apart from one another in the first direction on a sidewall of the channel structure; and a gate insulating layer between each of the plurality of gate electrodes and the channel structure, wherein the channel structure includes a body gate layer extending in the first direction; a charge storage structure surrounding a sidewall of the body gate layer; and a channel layer surrounding sidewall of the charge storage structure. 1. A semiconductor device comprising: a body gate layer extending in the first direction;', 'a charge storage structure surrounding a sidewall of the body gate layer; and', 'a channel layer surrounding a sidewall of the charge storage structure;', 'a plurality of gate electrodes on the substrate and spaced apart from one another in the first direction on a sidewall of the channel structure; and', 'a gate insulating layer between each of the plurality of gate electrodes and the channel structure., 'a channel structure on a substrate and extending in a first direction perpendicular to a top surface of the substrate, the channel structure comprising'}2. The semiconductor device of claim 1 , whereinthe charge storage structure is between the body gate layer and the channel layer, andthe charge storage structure is in contact with an inner wall of the channel layer.3. The semiconductor device of claim 1 , whereinthe channel layer is on an inner wall of a channel hole penetrating the plurality of gate electrodes and extending in the first direction,the charge storage structure is conformally along the inner wall of the channel hole on the channel layer, andthe body gate layer fills in the channel hole on the charge storage structure.4. The semiconductor device of claim 1 , wherein the charge storage ...

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Номер записи: 68
09-02-2017 дата публикации

3D Memory Having Vertical Switches with Surround Gates and Method Thereof

Номер: US20170040381A1
Автор: Cernea Raul Adrian, Chen Yung-Tin, Radigan Steven J., Scheuerlein Roy E.
Принадлежит:

A vertical switching layer of a 3D memory device serves to switch a set of vertical local bit lines to a corresponding set of global bit lines, the vertical switching layer being a 2D array of TFT channels of vertical thin-film transistors (TFTs) aligned to connect to an array of local bit lines, each TFT switching a local bit line to a corresponding global bit line. The TFTs in the array have a separation of lengths Lx and Ly along the x- and y-axis respectively such that a gate material layer forms a surround gate around each TFT in an x-y plane and has a thickness that merges to form a row select line along the x-axis while maintaining a separation of length Ls between individual row select lines. The surround gate improves the switching capacity of the TFTs. 1. A method , comprising: providing in the multi-plane memory layer a 2-D array in an x-y plane of conductive pillars as bit line pillars elongated in the z-direction through the plurality of planes, the 2-D array of bit line pillars being spaced apart in the x-direction and the y-direction by a spacing Lx and a spacing Ly respectively and a difference between Ly and Lx given by a spacing Ls;', 'forming a slab of a vertical switch layer on top of the multi-plane memory layer by forming a 2D array of isolated TFT channels in the x-y plane of the slab, each TFT channel being in-line with and having a first end connected to one end of one of the bit line pillars along the z-direction;', 'depositing a layer of gate oxide on the slab;', 'forming a select gate surrounding and wrapped around each TFT channel in a plane defined by the x-direction and the y-direction by depositing a layer of gate material on top of the layer of gate oxide, said layer of gate material having a thickness that fills a space between adjacent TFT channels in the x-direction to form a select gate line along the x-direction, thereby leaving a select gate with at least half of said thickness surrounding each TFT channel while leaving a space ...

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Номер записи: 69
24-02-2022 дата публикации

Memory controller and method of operating the same

Номер: US20220057953A1
Автор: Ji Hoon Lee
Принадлежит: SK hynix Inc

A memory controller includes a meta data memory configured to store mapping information of data stored in a plurality of memory blocks included in a memory device and valid data information indicating whether the data stored in the plurality of memory blocks is valid data, and a migration controller configured to control the memory device to perform a migration operation of moving a plurality of valid data stored in a source memory block among the plurality of memory blocks from the source memory block to a target memory block based on the mapping information and the valid data information.

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Номер записи: 70
07-02-2019 дата публикации

READ ONLY MEMORY

Номер: US20190043587A1
Автор: Chen Chung-Hao, Hsu Chi-Hsiu, Lu Hsin-Pang, Mou Ya-Nan, Tsai Chung-Cheng
Принадлежит:

A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact. 1. A read only memory (ROM) , comprising:a plurality of bit lines extending in a first direction;a plurality of source lines extending in parallel to the plurality of bit lines; anda plurality of word lines extending in a second direction perpendicular to the first direction;wherein each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.2. The read only memory of claim 1 , wherein the plurality of bit lines and the plurality of source lines are in interlaced arrangement in the second direction.3. The read only memory of claim 1 , wherein each of the active area is crossed over by two of the plurality of word lines.4. The read only memory of claim 1 , wherein each of the active area is crossed over by one of the plurality of source lines.5. The read only memory of claim 1 , wherein each of the active area is crossed over by one of the plurality of bit lines.6. The read only memory of claim 1 , wherein each of the active area comprises two bit line contacts at most.7. The read only memory of claim 6 , wherein one of the bit line contact and one of the source line contact in the active area are disposed at opposite sides of one of the word lines respectively. The present invention relates generally to a read only memory (ROM), and more specifically, relates to a read only memory with each two ROM cells sharing a common source line and an active area.Read-only memory (ROM) is a type of memory that persistently stores content or data. ...

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Номер записи: 71
07-02-2019 дата публикации

METAL-NITRIDE-FREE VIA IN STACKED MEMORY

Номер: US20190043807A1
Автор: Bohra Mihir, ECONOMY D. Ross, Redaelli Andrea
Принадлежит:

A nonvolatile memory device includes a metal silicon nitride layer on a three-dimensional (3D) crosspoint architecture, where the metal silicon nitride layer is in the memory array processing. The metal silicon nitride layer is patterned in accordance with the memory array structure, rather than being an underlying layer for a metal layer. The metal layer provides bitline or wordline select paths, and can connect to a via in parallel with the memory array stack. The metal silicon nitride layer is between the metal layer and the memory array, and is not present over the via. 1. An apparatus comprising:a memory stack structure including multiple memory cells, the memory stack structure including a crosspoint architecture;a via in parallel with the memory stack structure to provide a current path to select at least one of the memory cells;a metal layer to couple to the via and to a top electrode of the memory stack structure; anda metal silicon nitride layer to couple the metal layer to the top electrode, wherein the metal silicon nitride layer to be part of the memory stack structure, to be between individual pillars of the crosspoint architecture and the metal layer, and not be between the metal layer and the via.2. The apparatus of claim 1 , wherein the via is to provide a current path to a bitline.3. The apparatus of claim 1 , wherein the via is to provide a current path to a wordline.4. The apparatus of claim 1 , wherein the metal layer comprises tungsten (W) and the metal silicon nitride layer comprises tungsten silicon nitride (WSiN).5. The apparatus of claim 4 , further comprising a layer of tungsten silicide (WSix) as a seed layer for the tungsten metal layer.6. The apparatus of claim 1 , wherein the memory stack structure further comprises a layer of carbon as the top electrode.7. The apparatus of claim 1 , wherein the crosspoint architecture comprises a three dimensional (3D) crosspoint (3DXP) nonvolatile memory architecture.8. A system comprising:a ...

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Номер записи: 72
18-02-2021 дата публикации

Semiconductor memory apparatus for preventing disturbance

Номер: US20210050058A1
Автор: Jin Su Park
Принадлежит: SK hynix Inc

A semiconductor memory apparatus includes an access line control circuit. The access line control circuit applies a selected bias voltage to a selected access line coupled with a target memory cell and applies a first unselected bias voltage to an unselected access line adjacent to the selected access line. A second unselected bias voltage is applied to an unselected access line not adjacent to the selected access line.

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Номер записи: 73
06-02-2020 дата публикации

Semiconductor memory device

Номер: US20200043941A1
Автор: Hui-jung Kim, Keunnam Kim, Kiseok LEE, Yoosang Hwang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device may include a stack structure that includes a plurality of layers vertically stacked on a substrate, and a plurality of gate electrodes that vertically extend to penetrate the stack structure. Each of the plurality of layers may include a plurality of semiconductor patterns that extend in parallel along a first direction, a bit line that is electrically connected to the semiconductor patterns and extends in a second direction intersecting the first direction, a first air gap on the bit line, and a data storage element that is electrically connected to a corresponding one of the semiconductor patterns. The first air gap is interposed between the bit line of a first layer of the plurality of layers and the bit line of a second layer of the plurality of layers.

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Номер записи: 74
16-02-2017 дата публикации

Design structure for reducing pre-charge voltage for static random-access memory arrays

Номер: US20170046465A1
Автор: Alexander Fritsch, Amira Rozenfeld, Dieter Wendel, Rolf Sautter
Принадлежит: International Business Machines Corp

A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.

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Номер записи: 75
03-03-2022 дата публикации

Power network for providing power supply to memory device

Номер: US20220068346A1
Автор: Andy Wangkun CHEN, Ayush Kulshrestha, Ettore Amirante, Sony, Sriram Thyagarajan, Yew Keong Chong
Принадлежит: ARM LTD

Various implementations described herein are related to a device having memory circuitry with a bitcell array. The device may include a frontside power network that is coupled to the bitcell array, and the device may include a backside power network that provides power to the bitcell array. The device may include transition vias that couple the backside power network to the frontside power network, and the backside power network may provide power to the bitcell array by way of the transition vias being coupled to the frontside power network.

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Номер записи: 76
03-03-2022 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND A MANUFACTURING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE

Номер: US20220068963A1
Автор: LEE Nam Jae
Принадлежит: SK HYNIX INC.

A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes: a bit line overlapping with a peripheral circuit layer; interlayer insulating layers and conductive patterns alternately stacked in a first direction on the bit line; vertical channels connected to the bit line, the vertical channels penetrating the interlayer insulating layers and the conductive patterns, the vertical channels protruding farther in the first direction than the stacked interlayer insulating layers and the conductive patterns; a connection pattern in contact with a portion of each of the vertical channels that protrudes farther in the first direction than the stacked interlayer insulating layers and the conductive patterns, the connection pattern connecting the vertical channels; a source channel in contact with the connection pattern, the source channel extending in the first direction; and a source select line surrounding the source channel.

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Номер записи: 77
14-02-2019 дата публикации

SEMICONDUCTOR STORAGE DEVICE

Номер: US20190050169A1
Автор: KOMAI Hiromitsu
Принадлежит:

A semiconductor storage device includes a hookup circuit including first and second circuits connected respectively to first and second bit lines, a first circuit group including a first sense amplifier circuit connected to the first circuit and a first data register connected to the first sense amplifier circuit, a second circuit group including a second sense amplifier circuit connected to the second circuit and a second data register connected to the second sense amplifier circuit, and a memory cell array that is above the hookup circuit and the first and second circuit groups and includes a first memory cell connected to the first bit line and a second memory cell connected to the second bit line. The first circuit group, the hookup circuit, and the second circuit group are arranged in sequence along a first direction that is parallel to a surface of the semiconductor substrate. 1. A semiconductor storage device comprising:a hookup circuit that is above a semiconductor substrate and includes a first circuit connected to a first bit line and a second circuit connected to a second bit line;a first circuit group that includes a first sense amplifier circuit connected to the first circuit and a first data register connected to the first sense amplifier circuit via a first data bus;a second circuit group that includes a second sense amplifier circuit connected to the second circuit and a second data register connected to the second sense amplifier circuit via a second data bus; anda memory cell array that is above the hookup circuit and the first and second circuit groups and includes a first memory cell connected to the first bit line and a second memory cell connected to the second bit line,wherein the first circuit group, the hookup circuit, and the second circuit group are arranged in sequence along a first direction that is parallel to a surface of the semiconductor substrate.2. The semiconductor storage device according to claim 1 ,wherein the first data ...

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Номер записи: 78
22-02-2018 дата публикации

MEMORY DEVICE AND CENTRAL PROCESSING UNIT

Номер: US20180053535A1
Автор: SON Jong-Pil
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A memory device includes a first memory cell array connected to a first internal data line; a second memory cell array connected to a second internal data line; and a line swap circuit configured to connect the first and second internal data lines with first and second external data lines based on an externally received driving signal. The line swap circuit is configured such that, when the driving signal has a first logic level, the line swap circuit connects the first and second internal data lines with the first and second external data lines, respectively, and when the driving signal has a second, different logic level, the line swap circuit swaps the first and second external data lines so that the first internal data line is connected to the second external data line and the second internal data line is connected to the first external data line. 1. A memory device comprising:a first memory cell array connected to a first internal data line;a second memory cell array connected to a second internal data line; anda line swap circuit configured to connect the first internal data line and the second internal data line with a first external data line and a second external data line based on a driving signal received from the outside, when the driving signal has a first logic level, the line swap circuit connects the first internal data line and the second internal data line with the first external data line and the second external data line, respectively, and', 'when the driving signal has a second logic level different from the first logic level, the line swap circuit swaps the first external data line and the second external data line so that the first internal data line is connected to the second external data line and the second internal data line is connected to the first external data line., 'the line swap circuit being configured such that,'}2. The memory device of claim 1 ,wherein the line swap circuit is configured to operate in response to the driving ...

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Номер записи: 79
22-02-2018 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF OPERATING AND CONTROLLING A SEMICONDUCTOR DEVICE

Номер: US20180053539A1
Автор: OH TAE YOUNG, SHIN SEUNGJUN
Принадлежит:

An exemplary embodiment includes a method of controlling a semiconductor device. The semiconductor device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, a row decoder for receiving a row address and selecting a word line corresponding to the row address, a column decoder for receiving a column address and selecting a bit line corresponding to the column address, a sense amplifier for reading data stored in a memory cell connected to the selected word line and the selected bit line, and a data output driver. The method includes setting a calibration code for a driver control code, to control an initial current strength of the data output driver, and changing the calibration code to change the driver control code during a read or write operation for the memory cell array. 1. A method of controlling a semiconductor device , the semiconductor device comprising:a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines;a row decoder for receiving a row address and selecting a word line corresponding to the row address;a column decoder for receiving a column address and selecting a bit line corresponding to the column address;a sense amplifier for reading data stored in a memory cell connected to the selected word line and the selected bit line; anda data output driver including a first driver including a plurality of first transistors having different sizes from each other and a second driver including a plurality of second transistors having the same size as each other, the first driver and the second driver outputting the data to an output pad and driven to provide impedance to the output pad, the method comprising:at a first time, outputting a first calibration code for the first driver and a second calibration code for the second driver to control the impedance provided to the output pad; andat a second ...

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Номер записи: 80
22-02-2018 дата публикации

SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHODS OF OPERATING THE SAME

Номер: US20180053545A1
Автор: SON Jong-Pil
Принадлежит:

A semiconductor memory device includes a memory cell array, a control logic circuit, an internal processing circuit, and an error correction circuit. The control logic circuit generates an internal processing mode signal in response to a command from a memory controller. The internal processing circuit selectively performs the internal processing operation on a first set of data read from the memory cell array to output a processing result data, in response to the internal processing mode signal. The error correction circuit performs an error correction code (ECC) encoding on the processing result data to generate a second parity data and stores the processing result data and the second parity data in the memory cell array. The error correction circuit generates the second parity data by selecting the same ECC of a plurality of ECCs as a first ECC. 1. A semiconductor memory device , comprising:a memory cell array including a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines;a control logic circuit configured to generate an internal processing mode signal designating whether to perform an internal processing operation in response to a command received from a memory controller;an internal processing circuit configured to output a processing result data by selectively performing the internal processing operation on a first set of data read from the memory cell array, in response to the internal processing mode signal, the first set of data including a main data and a first parity data; andan error correction circuit configured to generate a second parity data by performing an error correction code (ECC) encoding on the processing result data and configured to store the processing result data and the second parity data in the memory cell array,wherein the error correction circuit is configured to generate the second parity data by selecting the same ECC of a plurality of ECCs as a first ECC which is used for generating the first ...

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Номер записи: 81
22-02-2018 дата публикации

SEMICONDUCTOR DEVICE INCLUDING NONVOLATILE MEMORY CONFIGURED TO SWITCH BETWEEN A REFERENCE CURRENT READING SYSTEM AND A COMPLIMENTARY READING SYSTEM

Номер: US20180053557A1
Автор: KATO Tamiyu, Suzuki Takanobu
Принадлежит:

The present invention provides a semiconductor device including a nonvolatile memory of which the memory size of a data area and the memory size of a code area can be freely changed. The semiconductor device according to one embodiment includes a nonvolatile memory which can switch between a reference current reading system which performs data read by comparing a current flowing through a first memory cell as a read target and the reference current and a complementary reading system which performs data read by comparing currents flowing through a first memory cell and a second memory cell storing complementary data, as a read target. 1. A semiconductor device comprising:a first memory array including a plurality of memory cells arranged in a matrix, a plurality of bit lines respectively corresponding to columns of the memory cells, and a plurality of word lines respectively corresponding to rows of the memory cells;a sense amplifier configured to amplify the difference of currents flowing through a first and a second output signal lines; anda coupling switch unit configured to switch coupling between the first and second output signal lines and the bit lines of the first memory array based on specified modes including first and second modes, the first mode performing data read by comparing a current flowing through a memory cell as a read target and the second mode performing data read by comparing currents flowing through first and second memory cells as a read target storing complementary data,wherein, in the first mode, the coupling switch unit couples a bit line of the first memory array corresponding to the memory cell as the read target to the first output signal line and couples a reference current source to the second output signal line,wherein, in the second mode, the coupling switch unit couples the first and second bit lines of the first memory array corresponding to the first and second memory cells as the read target to the first and second output ...

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Номер записи: 82
13-02-2020 дата публикации

Memory Bypass Function For A Memory

Номер: US20200051658A1
Автор: Barth, Gorman Kevin W., JR. John Edward, Pilo Harold
Принадлежит:

A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit and the read/write activation circuit. The write data input circuit is coupled to a write driver of the memory device for providing write data. 1. A memory bypass circuit for a memory device , comprising:a word line disable circuit; anda read and write activation circuit;wherein the word line disable circuit is coupled to a word line of the memory device, andwherein the read and write activation circuit is coupled to the memory device for concurrent activation of writing and reading functions of the memory device during a testing mode.2. The memory bypass circuit of further comprising an internal clock generator and a write data input circuit claim 1 , wherein the internal clock generator is coupled to the word line disable circuit and the read/write activation circuit claim 1 , and wherein the write data input circuit is coupled to a write driver of the memory device for providing test data.3. The memory bypass circuit of wherein the word line disable circuit comprises:a latch,an inverter,a first AND gate for generating a word line deactivation signal A_C, anda second AND gate for generating a word line deactivation signal A_T,wherein inputs of the first AND gate are coupled to an output of the inverter, a negated logic test signal, and an internal clock signal, andwherein inputs of the second AND gate are coupled to the negated logic test signal, the internal clock signal, and an output of the latch.4. The memory bypass circuit of wherein an input of the latch is coupled to an ...

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Номер записи: 83
13-02-2020 дата публикации

MULTI-DIVISION 3D NAND MEMORY DEVICE

Номер: US20200051983A1
Автор: LI Yan Ni, Zhang Zhong
Принадлежит: Yangtze Memory Technologies Co., Ltd.

Disclosed is a method for forming a staircase structure of 3D memory. The method includes providing a substrate, forming an alternating layer stack over the substrate, forming a plurality of block regions over a surface of the alternating layer stack, forming a first plurality of staircase structures to expose a portion of a first number of top-most layer stacks at each of the block regions and removing the first number of the layer stacks at a second plurality of staircase structures at each of the block regions. 1. A semiconductor structure , comprising:a substrate;a first plurality of layer stacks disposed over the substrate, wherein the first plurality of layer stacks has a first number of layer stacks;a second plurality of layer stack disposed over the first plurality of layer stack, wherein the second plurality of layer stacks has the first number of layer stacks; a second number of steps in a first horizontal direction;', 'and', 'a third number of steps in a second horizontal direction;, 'a first staircase structure disposed over the substrate, wherein a step of the first staircase structure exposes a portion of a layer stack of the first plurality of layer stacks, the first staircase structure comprisinganda second staircase structure horizontally abutting the first staircase structure, wherein a step of the second staircase structure exposes a portion of a layer stack of the second plurality of layer stacks.2. The semiconductor structure of claim 1 , wherein the second staircase structure further comprises the second number of steps in the first horizontal direction and the third number of steps in the second horizontal direction.3. The semiconductor structure of claim 1 , wherein a top step of the first staircase structure is at least the first number of levels lower than that of the second staircase structure.4. The semiconductor structure of claim 1 , wherein the first number is equal to the product of the second and the third number.5. The semiconductor ...

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Номер записи: 84
10-03-2022 дата публикации

SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME

Номер: US20220077167A1
Автор: KANG MINJUN, LIM Geunwon, PARK BYUNGGON, SHIN Joongshik
Принадлежит:

A semiconductor includes a lower structure and a stack structure having interlayer insulating layers and horizontal layers alternately stacked on the lower structure. A first dam vertical structure penetrates the stack structure. The first dam vertical structure divides the stack structure into a gate stack region and an insulator stack region. The horizontal layers include gate horizontal layers in the gate stack region and insulating horizontal layers in the insulator stack region. A memory vertical structure and a supporter vertical structure penetrate the gate stack region. Separation structures penetrate the gate stack region. One separation structure includes a first side surface, a second side surface not perpendicular to the first side surface, and a connection side surface extending from the first side surface to the second side surface. The connection side surface is higher than an uppermost gate horizontal layer of the gate horizontal layers. 1. A semiconductor device comprising:a lower structure including a peripheral circuit;a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, wherein the stack structure is disposed in a memory cell region and a staircase region adjacent to the memory cell region, and the stack structure has a staircase shape in the staircase region;a capping insulating structure covering the stack structure on the lower structure;a first dam vertical structure penetrating the stack structure in the staircase region and extending into the capping insulating structure, wherein the first dam vertical structure divides the stack structure into a gate stack region and an insulator stack region, and among the horizontal layers, horizontal layers disposed in the gate stack region are gate horizontal layers, and horizontal layers disposed in the insulator stack region are insulating horizontal layers;a memory vertical structure penetrating the gate stack region in the memory ...

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Номер записи: 85
21-02-2019 дата публикации

Semiconductor storage device

Номер: US20190057746A1
Автор: Hiromitsu Komai
Принадлежит: Toshiba Memory Corp

A semiconductor storage device includes a plurality of memory cells, bit lines respectively connected to the third memory cells, sense circuits respectively connected to the bit lines, latch circuits respectively connected to the sense circuits, and an input and output circuit connected to a first set of latch circuits via a first data line, a second set of latch circuit via a second data line, and a third set of latch circuits via a third data line. The bit lines are disposed in sequence in a first direction and a group of the sense circuits is disposed in sequence in a second direction crossing the first direction, and two bit lines that are not adjacent in the first direction are connected respectively to two sense circuits in the group that are adjacent in the second direction.

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Номер записи: 86
03-03-2016 дата публикации

Memory with local-/global bit line architecture and additional capacitance for global bit line discharge in reading

Номер: US20160064044A1
Автор: Anthony Stansfield
Принадлежит: Surecore Ltd

There is provided a memory unit comprising one or more global bit lines connected to a sense amplifier, and a plurality of memory cells that are grouped into a plurality of memory cell groups, each memory cell group having one or more local bit lines operatively connected to each of the memory cells in the memory cell group. Each memory cell group is configured such that, when a memory cell of the memory cell group is being read, the one or more local bit lines of the memory cell group are provided as inputs to a logic circuit and are not connected to the global bit lines, the logic circuit being configured to cause a capacitance element to be connected to one of the one or more global bit lines in dependence upon the states of the one or more local bit lines of the memory cell group.

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Номер записи: 87
03-03-2016 дата публикации

Semiconductor memory devices and memory systems including the same

Номер: US20160064056A1
Автор: Chul-woo Park, Dae-Jeong Kim, Dae-sun Kim, Jae-Youn Youn, Kwang-II Park, Su-a Kim, Sung-Min RYU, Young-Soo Sohn
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.

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Номер записи: 88
03-03-2016 дата публикации

Semiconductor device

Номер: US20160064095A1
Автор: Takanobu Suzuki, Tamiyu Kato
Принадлежит: Renesas Electronics Corp

The present invention provides a semiconductor device including a nonvolatile memory of which the memory size of a data area and the memory size of a code area can be freely changed. The semiconductor device according to one embodiment includes a nonvolatile memory which can switch between a reference current reading system which performs data read by comparing a current flowing through a first memory cell as a read target and the reference current and a complementary reading system which performs data read by comparing currents flowing through a first memory cell and a second memory cell storing complementary data, as a read target.

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Номер записи: 89
01-03-2018 дата публикации

BIT LINE SENSE AMPLIFIER

Номер: US20180061461A1
Автор: Seo Young-Hun
Принадлежит:

A bit line sense amplifier with an enhanced sensing margin is provided. The bit line sense amplifier includes a sensing amplification circuit connected to a bit line and a complementary bit line and configured to sense a voltage change of the bit line and adjust voltages of a sensing bit line. Also provided is a complementary sensing bit line based on the sensed voltage change, wherein the sensing amplification circuit includes a first transistor connected between the complementary sensing bit line and a first high-voltage node and controlled by the voltage change of the bit line. A second transistor is connected between the sensing bit line and a second high-voltage node and controlled by a voltage change of the complementary bit line. 1. A bit line sense amplifier comprising:a sensing amplification circuit respectively connected to a bit line and to a complementary bit line, and the sensing amplification circuit is configured to sense a voltage change of the bit line and adjust voltages of a sensing bit line and a complementary sensing bit line based on the sensed voltage change of the bit line;an isolation switching circuit including a first isolation switch connected to the bit line and the sensing bit line and controlled by an isolation switch control signal, and a second isolation switch connected between the complementary bit line and the complementary sensing bit line and controlled by the isolation switch control signal; andan offset cancellation circuit including a first offset cancellation switch connected between the bit line and the complementary sensing bit line and controlled by an offset cancellation control signal, and a second offset cancellation switch connected between the complementary bit line and the sensing bit line and controlled by the offset cancellation control signal,wherein the sensing amplification circuit comprises:a first transistor connected between the complementary sensing bit line and a first high-voltage node, and the first ...

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Номер записи: 90
01-03-2018 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND READING METHOD THEREOF

Номер: US20180061464A1
Автор: YAMAUCHI Kazuki
Принадлежит: WINBOND ELECTRONICS CORP.

The invention provides a semiconductor memory device and a reading method thereof, which are capable of suppressing a peak current when pre-charging a bit line are provided. The reading method of a flash memory of the present invention includes steps of: pre-charging a selected bit line; and reading a voltage or a current of the pre-charged selected bit line. The step of pre-charging is performed by pre-charging a sense node SNS to Vcc−Vth at a time t pre-charging a node TOBL to VCLAMP at a time t pre-charging the node TOBL to VCLAMP at a time t and pre-charging the sense node SNS to Vcc at a time t 1. A reading method of a semiconductor storage device , comprising steps of:pre-charging a selected bit line; andreading a voltage or a current of the pre-charged selected bit line,wherein the step of pre-charging the selected bit line comprises steps of:pre-charging a sense node to a first voltage;for a bit line node between the sense node and a bit line, pre-charging the bit line node to a first clamp voltage based on the first voltage of the sense node;pre-charging the bit line node to a second clamp voltage greater than the first clamp voltage after pre-charging the selected bit line by the first clamp voltage; andpre-charging the sense node to a second voltage greater than the first voltage.2. The reading method as recited in claim 1 , whereinthe sense node is pre-charged by a first transistor, and the bit line node is pre-charged by a second transistor.3. The reading method as recited in claim 2 , whereinthe first voltage is pre-charged to the sense node by applying a first signal voltage to a gate of the first transistor, the second voltage is pre-charged to the sense node by applying a second signal voltage to the gate of the first transistor, and the second signal voltage is greater than the first signal voltage.4. The reading method as recited in claim 2 , whereinthe bit line node is pre-charged to the first clamp voltage by applying the first clamp voltage to ...

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Номер записи: 91
01-03-2018 дата публикации

APPARATUSES AND METHODS INCLUDING TWO TRANSISTOR-ONE CAPACITOR MEMORY AND FOR ACCESSING SAME

Номер: US20180061477A1
Автор: Derner Scott J., KAWAMURA CHRISTOPHER J.
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage. 1. An apparatus , comprising:a capacitor having a first plate and a second plate;a first digit line supplied operatively with a reference voltage;a first selection component configured to couple the first plate to the first digit line responsive to activating the first selection component;a second digit line;a second selection component configured to couple the second plate to the second digit line responsive to activating the second selection component; anda sense amplifier coupled to the second digit line and configured to amplify a voltage difference between a voltage on the second digit line and the reference voltage.2. The apparatus of wherein the first selection component is coupled to a first word line and is configured to be activated responsive to activation of the first word line and wherein the second selection component is coupled to a second word line and is configured to be activated responsive to activation of the second word line.3. The apparatus of wherein the first selection component is coupled between the first digit line and the first plate of the capacitor and wherein the second selection component is coupled between the second digit line and the second plate of the capacitor.4. An apparatus claim 1 , comprising:a memory cell including first and second selection ...

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Номер записи: 92
20-02-2020 дата публикации

MEMORY CIRCUIT AND METHOD OF MANUFACTURING THE SAME

Номер: US20200058328A1
Автор: Chang Meng-Sheng, WU Min-Shin, YANG Yao-Jen
Принадлежит:

A memory circuit array includes a first read device and a first program device. The first read device is coupled to a first bit line. The first read device includes a first transistor coupled to a first word line, and a second transistor coupled to the first word line. The first program device is coupled to the first read device. The first program device includes a third transistor coupled to a second word line, and a fourth transistor coupled to the second word line. 1. A memory circuit comprising: a first transistor coupled to a first word line; and', 'a second transistor coupled to the first word line; and, 'a first read device coupled to a first bit line, the first read device comprising a third transistor coupled to a second word line; and', 'a fourth transistor coupled to the second word line., 'a first program device coupled to the first read device, the first program device comprising2. The memory circuit of claim 1 , wherein the second transistor is coupled in parallel with the first transistor claim 1 , and the fourth transistor is coupled in parallel with the third transistor.3. (canceled)3. The memory circuit of claim 1 , whereinthe first transistor comprises a first terminal, a second terminal and a third terminal; and the first terminal of the first transistor, the first terminal of the second transistor and the first word line are coupled to each other,', 'the second terminal of the first transistor is coupled to the second terminal of the second transistor, and', 'the third terminal of the first transistor is coupled to at least the third terminal of the second transistor., 'the second transistor comprises a first terminal, a second terminal and a third terminal,'}4. The memory circuit of claim 3 , whereinthe third transistor comprises a first terminal, a second terminal and a third terminal; and the first terminal of the third transistor, the first terminal of the fourth transistor and the second word line are coupled to each other,', 'the second ...

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Номер записи: 93
04-03-2021 дата публикации

MEMORY DEVICE

Номер: US20210065751A1
Автор: BYEON Daeseok, KIM CHANHO, PARK Jooyong
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A memory device includes a first semiconductor chip including a memory cell array disposed on a first substrate, and a first bonding metal on a first uppermost metal layer of the first semiconductor chip, and a second semiconductor chip including circuit devices disposed on a second substrate and a second bonding metal on a second uppermost metal layer of the second semiconductor chip, the circuit devices providing a peripheral circuit operating the memory cell array. The first and second semiconductor chips are electrically connected to each other by the first bonding metal and the second bonding metal in a bonding area. A routing wire electrically connected to the peripheral circuit is disposed in one or both of the first and second uppermost metal layers and is disposed in a non-bonding area in which the first and second semiconductor chips are not electrically connected to each other. 1. A memory device comprising:a first semiconductor chip including a memory cell array disposed on a first substrate, and a first bonding metal on a first uppermost metal layer of the first semiconductor chip; anda second semiconductor chip including circuit devices disposed on a second substrate, and a second bonding metal on a second uppermost metal layer of the second semiconductor chip, the circuit devices providing a peripheral circuit operating the memory cell array,wherein the first semiconductor chip and the second semiconductor chip are electrically connected to each other by the first bonding metal and the second bonding metal in a bonding area, anda routing wire electrically connected to the peripheral circuit is disposed in at least one of the first uppermost metal layer or the second uppermost metal layer and is disposed in a non-bonding area in which the first semiconductor chip and the second semiconductor chip are not electrically connected to each other.2. (canceled)3. The memory device of claim 1 , wherein the second semiconductor chip comprises a first metal ...

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Номер записи: 94
17-03-2022 дата публикации

Semiconductor device

Номер: US20220084859A1
Автор: Bong Soon LIM, Dae Seok Byeon, Jae Ick Son
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a first semiconductor chip including bitlines, wordlines, common source line, first bonding pads, second bonding pads, third bonding pads and memory cells, the memory cells being electrically connected to the bitlines, the wordlines, and the common source line, the first bonding pads being electrically connected to the bitlines, the second bonding pads being electrically connected to the wordlines, and the third bonding pads being electrically connected to the common source line; a second semiconductor chip including fourth bonding pads, fifth bonding pads, sixth bonding pads and an input/output circuit, the fourth bonding pads being electrically connected to the first bonding pads, the fifth bonding pads being electrically connected to the second bonding pads, the sixth bonding pads being electrically connected to the third bonding pads and the input/output circuit being configured to write data to the memory cells via the fourth bonding pads and the fifth bonding pads; a sensing line extending along an edge portion of the first semiconductor chip, an edge portion of the second semiconductor chip, or the edge portion of the first semiconductor chip and the edge portion of the second semiconductor chip; and a detecting circuit in the second semiconductor chip, the detecting circuit being configured to detect defects from the first semiconductor chip, the second semiconductor chip, or both the first semiconductor chip and the second semiconductor chip using the sensing line.

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Номер записи: 95
17-03-2022 дата публикации

SEMICONDUCTOR STORAGE DEVICE

Номер: US20220085058A1
Автор: Arayashiki Yusuke, Ishikawa Takayuki, MOMO Nobuyuki, Murakami Yosuke, Nagashima Satoshi
Принадлежит:

A semiconductor storage device includes a substrate, a first wiring, a second wiring, a third wiring, a fourth wiring, a charge storage unit. The first wiring extends in a first direction along a surface of the substrate. The second wiring is aligned with the first wiring in a second direction intersecting with the first direction and extends in the first direction. The third wiring is in contact with the first wiring and the second wiring and includes a semiconductor. The fourth wiring is located between the first wiring and the second wiring, extends in a third direction intersecting with the first direction and the second direction, and is aligned with the third wiring in at least the first direction. The charge storage unit is located between the third wiring and the fourth wiring. 1. A semiconductor storage device comprising:a substrate having a surface;a first source line extending in a first direction along the surface;a first drain line aligned with the first source line in a second direction and extending in the first direction, the second direction intersecting with the first direction;a first channel portion in contact with the first source line and the first drain line, the first channel portion including a semiconductor;a first gate wiring located between the first source line and the first drain line, the first gate wiring extending in a third direction intersecting with the first direction and the second direction, the first gate wiring aligned with the first channel portion in the first direction; anda first charge storage located between the first channel portion and the first gate wiring.2. The semiconductor storage device according to claim 1 , wherein the first channel portion includes a first portion aligned with the first gate wiring in the first direction claim 1 , and a second portion located on an opposite side to the first portion with respect to the first gate wiring in the first direction claim 1 , andthe first charge storage including (i ...

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Номер записи: 96
28-02-2019 дата публикации

SEMICONDUCTOR STORAGE DEVICE

Номер: US20190066744A1
Автор: NIKI Yusuke
Принадлежит: Toshiba Memory Corporation

A device includes a memory-cell array and a sense-amplifier. A decoder connects a first BL to the sense amplifier. The decoder includes first and second multiplexers. The first multiplexer includes a first n-type transistor and a first p-type transistor. The first n-type transistor is connected to the first BL and capable of applying a first voltage for writing a first logic or a non-select voltage for not writing data to the first BL. The first p-type transistor is connected to the first BL and capable of applying a second voltage for writing a second logic or the non-select voltage to the first BL. The second multiplexer is connected between the first multiplexer and the sense amplifier and transmits the first voltage or the non-select voltage to the first n-type transistor and transmits the second voltage or the non-select voltage to the first p-type transistor. 1. A semiconductor storage device comprising:a memory cell array;a plurality of bit lines connected to the memory cell array;a plurality of word lines connected to the memory cell array;a sense amplifier configured to read data from memory cells in the memory cell array or write data to the memory cells via the bit lines; anda decoder configured to connect a first bit line selected from the bit lines to the sense amplifier, wherein the decoder includesa first multiplexer comprising a first n-type transistor connected to the first bit line among the bit lines and configured to apply a first voltage for writing a first logic or a non-select voltage for not writing data to the first bit line, and a first p-type transistor connected to the first bit line and configured to apply a second voltage for writing a second logic or the non-select voltage to the first bit line, anda second multiplexer connected between the first multiplexer and the sense amplifier and configured to transmit the first voltage or the non-select voltage to the first n-type transistor and transmit the second voltage or the non-select ...

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Номер записи: 97
28-02-2019 дата публикации

Memory devices and methods of operating the same

Номер: US20190066773A1
Автор: In-Hak Lee, Jae-Seung Choi, Sung-Hyun Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory device includes a memory cell, a word line connected to the memory cell, a bit line connected to the memory cell, a complementary bit line connected to the memory cell, an auxiliary bit line, an auxiliary complementary bit line, and a switch circuit. The memory cell stores a single bit. The switch circuit electrically connects one of the bit line and the complementary bit line to one of the auxiliary bit line and the auxiliary complementary bit line, in response to a logic level of a data bit to be written in the memory cell during a write operation, by using at least one or more transistors of at least one dummy cell as a switch, and the at least one dummy cell does not store a data bit.

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Номер записи: 98
08-03-2018 дата публикации

Memory architecture with multi-bank memory cell array accessed by local drive circuit within memory bank

Номер: US20180068700A1
Автор: Gyh-Bin Wang, Ming-Hung Wang, Tah-Kang Joseph Ting
Принадлежит: PieceMakers Tech Inc

A memory architecture includes K first control lines, M groups of second control lines and a memory cell array. K and M are positive integers. Each group of second control lines includes at least one second control line. The memory cell array includes M memory banks. Each memory bank is coupled to the K first control lines. The M memory banks are selected according to M bank select signals respectively so as to receive a shared set of first control signals through the K first control lines. The M memory banks are coupled to the M groups of second control lines respectively, and receive independent M sets of second control signals through the M groups of second control lines respectively. Each memory bank performs one of a column select operation and a sense amplification operation according to the set of first control signals and a set of second control signals.

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Номер записи: 99
08-03-2018 дата публикации

Semiconductor device

Номер: US20180068708A1
Автор: Koji Nii
Принадлежит: Renesas Electronics Corp

A semiconductor device includes: a first cell; a second cell; a first match line and a second match line; a first search line pair, first data being transmitted through the first search line pair; a second search line pair, second data being transmitted through the second search line pair; a first logical operation cell connected to the first search line pair and the first match line, and configured to drive the first match line based on a result of comparison between information held by the first and second cells and the first data; and a second logical operation cell connected to the second search line pair and the second match line, and configured to drive the second match line based on a result of comparison between information held by the first and second cells and the second data.

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Номер записи: 100