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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 12665. Отображено 100.
23-01-2017 дата публикации

Центрифуга

Номер: RU0000168186U1

Полезная модель относится к области производства оптических и оптико-электронных элементов и устройств и может быть использована преимущественно для финишной очистки поверхностей оптических деталей, например поверхностей подложек с нанесенными на них зеркалами лазерных гироскопов. Сущность полезной модели - она содержит корпус цилиндрической формы и опорный механизм, выполненный с возможностью установки и удержания оптической детали, а также подачи на ее поверхность моющего раствора и деионизованной воды, причем в верхней части корпуса имеется выемка, в центре которой установлен опорный механизм для удержания оптической детали, выполненный с возможностью вращения вокруг вертикальной оси в виде пружинящей разрезной втулки с упругими вертикально ориентированными пружинящими элементами, предназначенными для закрепления и удержания оптической детали, при этом внутренняя стенка выемки в верхней части корпуса выполнена из капиллярно-пористого материала с V-образным вырезом у верхнего края, а дно выемки выполнено с возможностью слива моющего раствора и деионизованной воды. Технический результат заключается в упрощении устройства и повышении качества очистки. 1 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 168 186 U1 (51) МПК B08B 3/10 (2006.01) B08B 3/02 (2006.01) B08B 11/02 (2006.01) H01L 21/08 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ФОРМУЛА ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ РОССИЙСКОЙ ФЕДЕРАЦИИ (21)(22) Заявка: 2016127895, 12.07.2016 (24) Дата начала отсчета срока действия патента: 12.07.2016 (72) Автор(ы): Ищенко Петр Иванович (RU) Дата регистрации: 23.01.2017 Приоритет(ы): (22) Дата подачи заявки: 12.07.2016 Адрес для переписки: 117405, Москва, Варшавское ш., 143, корп. 1, кв. 110, Борисову Э.В. 1 6 8 1 8 6 R U (57) Формула полезной модели Центрифуга, содержащая корпус цилиндрической формы и опорный механизм, выполненный с возможностью установки и удержания оптической детали, а также подачи на ее поверхность моющего раствора и деионизованной воды, ...

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09-02-2012 дата публикации

Substrate processing apparatus and producing method of semiconductor device

Номер: US20120034788A1
Принадлежит: Hirohisa Yamazaki, Masanori Sakai, Toru Kagaya

A substrate treatment apparatus includes a reaction tube and a heater heating a silicon wafer. Trimethyl aluminum (TMA) and ozone (O 3 ) are alternately fed into the reaction tubeto generate Al 2 O 3 film on the surface of the wafer. The apparatus also includes supply tubes and for flowing the ozone and TMA and a nozzle supplying gas into the reaction tube. The two supply tubes are connected to the nozzle disposed inside the heater in a zone inside the reaction tube where a temperature is lower than a temperature near the wafer, and the ozone and TMA are supplied into the reaction tube through the nozzle.

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16-02-2012 дата публикации

Method for manufacturing porous structure and method for forming pattern

Номер: US20120037594A1
Принадлежит: Individual

A pattern forming material contains a block copolymer or graft copolymer and forms a structure having micro polymer phases, in which, with respect to at least two polymer chains among polymer chains constituting the block copolymer or graft copolymer, the ratio between N/(Nc−No) values of monomer units constituting respective polymer chains is 1.4 or more, where N represents total number of atoms in the monomer unit, Nc represents the number of carbon atoms in the monomer unit, No represents the number of oxygen atoms in the monomer unit.

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15-03-2012 дата публикации

Producing method of semiconductor device and substrate processing apparatus

Номер: US20120064730A1
Принадлежит: Individual

Disclosed is a method for manufacturing a semiconductor device which comprises a step for carrying a plurality of substrates ( 1 ) in a process chamber ( 4 ), a step for supplying an oxygen-containing gas from the upstream side of the substrates ( 1 ) carried in the process chamber ( 4 ), a step for supplying a hydrogen-containing gas from at least one location corresponding to a position within the region where substrates ( 1 ) are placed in the process chamber ( 4 ), a step for oxidizing the substrates ( 1 ) by reacting the oxygen-containing gas with the hydrogen-containing gas in the process chamber ( 4 ), and a step for carrying the thus-processed substrates ( 1 ) out of the process chamber ( 4 ).

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29-03-2012 дата публикации

Method of and apparatus for active energy assist baking

Номер: US20120077339A1

A method of and apparatus for forming interconnects on a substrate includes etching patterns in ultra-low k dielectric and removing moisture from the ultra-low k dielectric using active energy assist baking. During active energy assist baking, the ultra-low k dielectric is heated and exposed to light having only wavelengths greater than 400 nm for about 1 to about 20 minutes at a temperature of about 300 to about 400 degrees Celsius. The active energy assist baking is performed after wet-cleaning or after chemical mechanical polishing, or both.

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03-05-2012 дата публикации

Methods Of Forming Doped Regions In Semiconductor Substrates

Номер: US20120108042A1
Принадлежит: Micron Technology Inc

Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.

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31-05-2012 дата публикации

Doping of planar or three-dimensional structures at elevated temperatures

Номер: US20120135578A1

An improved method of doping a workpiece is disclosed. In this method, a film comprising the species to be implanted is introduced to the surface of a planar or three-dimensional workpiece. This film can be grown using CVD, a bath or other means. The workpiece with the film is then subjected to ion bombardment to help drive the dopant into the workpiece. This ion bombardment is performed at elevated temperatures to reduce crystal damage and create a more abrupt doped region.

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31-05-2012 дата публикации

Method of manufacturing porous insulating film

Номер: US20120135611A1
Принадлежит: Renesas Electronics Corp

A method includes forming an insulating film over a substrate by introducing a cyclic siloxane compound having a cyclic siloxane as a skeleton and having at least one volatile hydrocarbon group bonded to a side chain, and a silicon-containing compound into a plasma, and converting the insulating film to a porous insulating film by adding energy to the insulating film. The silicon-containing compound is decomposed using less energy as compared with the skeleton of the cyclic siloxane compound, the volatile hydrocarbon group, and the bond between the cyclic siloxane compound and the volatile hydrocarbon group.

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28-06-2012 дата публикации

Substrate processing method

Номер: US20120164839A1
Автор: Eiichi Nishimura
Принадлежит: Tokyo Electron Ltd

There is provided a substrate processing method capable of increasing an etching rate of a copper member without using a halogen gas. A Cu layer 40 having a smoothened surface 50 is obtained, and then, a processing gas produced by adding a methane gas to a hydrogen gas is introduced into an inner space of a processing chamber 15 . Plasma is generated from this processing gas. In the inner space of the processing chamber 15 , there exist oxygen radicals 52 generated when an oxide layer 42 is etched, and carbon radicals 53 generated from methane. The oxygen radicals 52 and the carbon radicals 53 are compounded to generate an organic acid, and the organic acid makes a reaction with copper atoms of the Cu layer 40 . As a result, a complex of the organic acid having the copper atoms is generated, and the generated organic acid complex is vaporized.

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13-09-2012 дата публикации

Memory Cell Constructions, and Methods for Fabricating Memory Cell Constructions

Номер: US20120228573A1
Автор: JIAN Li, Jun Liu
Принадлежит: Micron Technology Inc

Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals.

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04-10-2012 дата публикации

Silicon oxycarbide, growth method of silicon oxycarbide layer, semiconductor device and manufacture method for semiconductor device

Номер: US20120252227A1
Принадлежит: Fujitsu Semiconductor Ltd

A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O 2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.

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11-10-2012 дата публикации

Formation of a Masking Layer on a Dielectric Region to Facilitate Formation of a Capping Layer on Electrically Conductive Regions Separated by the Dielectric Region

Номер: US20120258595A1
Принадлежит: Intermolecular Inc

A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions the masking layer inhibits formation of capping layer material on the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive, a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

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17-01-2013 дата публикации

Method for manufacturing diode, and diode

Номер: US20130015469A1
Автор: Hideki Hayashi
Принадлежит: Sumitomo Electric Industries Ltd

A semiconductor substrate having a first side and a second side made of single crystal silicon carbide is prepared. A mask layer having a plurality of openings and made of silicon oxide is formed on the second side. The plurality of openings expose a plurality of regions included in the second side, respectively. A plurality of diamond portions are formed by epitaxial growth on the plurality of regions, respectively. The epitaxial growth is stopped before the plurality of diamond portions come into contact with each other. A Schottky electrode is formed on each of the plurality of diamond portions. An ohmic electrode is formed on the first side.

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07-02-2013 дата публикации

Silicon carbide semiconductor device

Номер: US20130032823A1
Автор: Hideki Hayashi
Принадлежит: Sumitomo Electric Industries Ltd

A first layer has a first conductivity type. A second layer is provided on the first layer such that a part of the first layer is exposed, and it has a second conductivity type. First to third impurity regions penetrate the second layer and reach the first layer. Each of the first and second impurity regions has the first conductivity type. The third impurity region is arranged between the first and second impurity regions and it has the second conductivity type. First to third electrodes are provided on the first to third impurity regions, respectively. A Schottky electrode is provided on the part of the first layer and electrically connected to the first electrode.

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07-03-2013 дата публикации

Method for forming a capacitor dielectric and method for manufacturing a capacitor using the capacitor dielectric

Номер: US20130058007A1
Автор: Jong-Bum Park
Принадлежит: Hynix Semiconductor Inc

A method for forming a capacitor dielectric includes depositing a zirconium oxide layer, performing a post-treatment on the zirconium oxide layer such that the zirconium oxide layer has a tetragonal phase, and depositing a tantalum oxide layer over the zirconium oxide layer such that the tantalum oxide layer has a tetragonal phase.

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28-03-2013 дата публикации

THIN-FILM SEMICONDUCTOR DEVICE, DISPLAY APPARATUS, AND METHOD FOR MANUFACTURING THIN-FILM SEMICONDUCTOR DEVICE

Номер: US20130075745A1
Принадлежит: Panasonic Corporation

A thin-film semiconductor device includes: a first gate line; a metal line; a first gate electrode extending from the first gate line; a second gate electrode on the first gate electrode; an insulating layer provided in a crossing area where the first gate line and the metal line cross; and a second gate line formed in the same layer as the second gate electrode, and on the first gate line in other than the crossing area, wherein the metal line is on the insulating layer, the second gate line and the second gate electrode are thicker than the first gate line and the first gate electrode, and an interface between the metal line and the insulating layer is positioned above a top surface of the second gate electrode, in a cross section in a direction in which the first and second gate lines extend. 1. A thin-film semiconductor device having a thin-film semiconductor element for driving a display device , the thin-film semiconductor device comprising:a substrate;a first gate line disposed on the substrate, through which a control signal is applied to the thin-film semiconductor element;a metal line above the substrate, the metal line crossing the first gate line;a first gate electrode of the thin-film semiconductor element, the first gate electrode extending from the first gate line;a second gate electrode on the first gate electrode;a gate insulating film on the second gate electrode;a semiconductor layer on the gate insulating film;a metal electrode on the semiconductor layer, the metal electrode extending from the metal line;an insulating layer provided, between the first gate line and the metal line, in a crossing area in which the first gate line and the metal line cross, to secure a distance between the first gate line and the metal line, the insulating layer being different from the gate insulating film; and wherein the metal line is on the insulating layer,', 'the second gate line and the second gate electrode are thicker than the first gate line and the first ...

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18-04-2013 дата публикации

Reusable substrates for electronic device fabrication and methods thereof

Номер: US20130095640A1
Автор: Baoguo Zhang
Принадлежит: Lux Material Co Ltd

Substrates for electronic device fabrication and methods thereof. A reusable substrate with at least a plurality of grooves for electronic device fabrication includes a substrate body made of one or more substrate materials and including a top planar surface, the top planar surface being divided into a plurality of planer regions by the plurality of grooves, the plurality of grooves including a plurality of bottom planar surfaces. Each of the plurality of grooves includes a bottom planar surface and two side surfaces, the bottom planar surface being selected from the plurality of bottom planar surfaces, the two side surfaces being in contact with the top surface and the bottom surface. The bottom planar surface is associated with a groove width from one of the two side surfaces to the other of the two side surfaces, the groove width ranging from 0.1 μm to 5 mm.

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25-04-2013 дата публикации

2DEG SCHOTTKY DIODE FORMED IN NITRIDE MATERIAL WITH A COMPOSITE SCHOTTKY/OHMIC ELECTRODE STRUCTURE AND METHOD OF MAKING THE SAME

Номер: US20130102135A1
Принадлежит: SAMSUNG ELECTRO-MECHANICS CO., LTD.

A method for manufacturing a semiconductor device includes preparing a base substrate; forming a semiconductor layer on the base substrate; forming an ohmic electrode part having ohmic electrode lines, on the semiconductor layer; and forming a Schottky electrode part, which is disposed on the semiconductor layer to be spaced apart from the ohmic electrode lines and has Schottky electrode lines parallel to the ohmic electrode lines, wherein forming the ohmic electrode part further comprises forming an ohmic electrode plate connected to one end of the ohmic electrode lines, forming the Schottky electrode part further comprises forming a Schottky electrode plate connected one end of the Schottky electrode lines, and one line of the Schottky electrode lines is disposed between two of the ohmic electrode lines to thereby achieve an interdigited configuration in which the ohmic electrode part and the Schottky electrode part are formed. 1. A method for manufacturing a semiconductor device comprising:preparing a base substrate;forming a semiconductor layer on the base substrate;forming an ohmic electrode part having ohmic electrode lines, on the semiconductor layer; andforming a Schottky electrode part, which is disposed on the semiconductor layer to be spaced apart from the ohmic electrode lines and has Schottky electrode lines parallel to the ohmic electrode lines,wherein forming the ohmic electrode part further comprises forming an ohmic electrode plate connected to one end of the ohmic electrode lines,forming the Schottky electrode part further comprises forming a Schottky electrode plate connected one end of the Schottky electrode lines,one line of the Schottky electrode lines is disposed between two of the ohmic electrode lines to thereby achieve an interdigited configuration in which the ohmic electrode part and the Schottky electrode part are formed,forming the ohmic electrode lines and the ohmic electrode plate is made through an in-situ scheme, andforming the ...

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02-05-2013 дата публикации

Indium Phosphide Substrate Manufacturing Method and Epitaxial Wafer Manufacturing Method

Номер: US20130109156A1
Автор: Okita Kyoko
Принадлежит: Sumitomo Electric Industries, Ltd.

The present invention affords methods of manufacturing InP substrates, methods of manufacturing epitaxial wafers, InP substrates, and epitaxial wafers whereby deterioration of the electrical characteristics can be kept under control, and at the same time, deterioration of the PL characteristics can be kept under control. An InP substrate manufacturing method of the present invention is provided with the following steps. An InP substrate is prepared (Steps S through S). The InP substrate is washed with sulfuric acid/hydrogen peroxide (Step S). After the step of washing with sulfuric acid/hydrogen peroxide (Step S), the InP substrate is washed with phosphoric acid (Step S). 1. An indium phosphide substrate manufacturing method comprising:a step of preparing an indium phosphide substrate;a step of washing the indium phosphide substrate with sulfuric acid/hydrogen peroxide; anda step, following said step of washing with sulfuric acid/hydrogen peroxide, of washing the indium phosphide substrate with phosphoric acid.2. The indium phosphide substrate manufacturing method set forth in claim 1 , wherein in said step of washing with phosphoric acid claim 1 , a aqueous phosphoric acid solution having a concentration of from 1% to 30% claim 1 , inclusive claim 1 , is utilized.3. The indium phosphide substrate manufacturing method set forth in claim 1 , wherein in said preparation step an indium phosphide substrate containing a dopant consisting of at least one substance selected from the group composed of iron claim 1 , sulfur claim 1 , tin claim 1 , and zinc is prepared.4. An epitaxial wafer manufacturing method comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a step of manufacturing an indium phosphide substrate according to the indium phosphide substrate manufacturing method set forth in any one of ; and'}a step of forming an epitaxial layer onto the indium phosphide substrate. 1. Technical FieldThe present invention relates to methods of manufacturing indium ...

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16-05-2013 дата публикации

Pattern forming method and manufacturing method of semiconductor device

Номер: US20130122429A1
Принадлежит: Tokyo Electron Ltd

A disclosed manufacturing method of a semiconductor device includes laminating a substrate, an etched film, an anti-reflective coating film, and a resist film; forming a pattern made of the resist film using a photolithographic technique; forming the third mask pattern array by a mask pattern forming method; and a seventh step of forming a fourth mask pattern array by processing the etched film using the third mask pattern array.

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23-05-2013 дата публикации

INSULATING FILM, FORMATION METHOD THEREOF, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF

Номер: US20130126861A1

An amorphous region with low density is formed in an oxide insulating film containing zirconium. The amount of oxygen released from such an oxide insulating film containing zirconium by heating is large and a temperature at which oxygen is released is higher in the oxide insulating film than in a conventional oxide film (e.g., a silicon oxide film). When the insulating film is formed using a sputtering target containing zirconium in an oxygen atmosphere, the temperature of a surface on which the insulating film is formed may be controlled to be lower than a temperature at which a film to be formed starts to crystallize. 1. A method for forming an insulating film , the method comprising the step of:forming the insulating film in an atmosphere comprising oxygen by a sputtering method,wherein a target used in the sputtering method comprises zirconium,wherein a first temperature of a surface on which the insulating film is formed is controlled to be lower than a second temperature at which the insulating film is completely crystallized, andwherein the insulating film is formed so that an amorphous region comprising oxygen in excess of a stoichiometric composition in a crystalline state is formed in a part of the insulating film.2. The method for forming an insulating film claim 1 , according to claim 1 , wherein the target further comprises yttrium.3. The method for forming an insulating film claim 1 , according to claim 1 , wherein the first temperature is higher than or equal to 20° C. and lower than or equal to 100° C.4. The method for forming an insulating film claim 1 , according to claim 1 , wherein a partial pressure of oxygen in the atmosphere comprising oxygen is greater than or equal to 25% and less than or equal to 100%.5. A method for manufacturing a semiconductor device claim 1 , the method comprising the steps of:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'forming a first insulating film by the method for forming an insulating film, according to ;'} ...

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23-05-2013 дата публикации

CIRCUITS WITH LINEAR FINFET STRUCTURES

Номер: US20130126978A1
Принадлежит:

A first transistor has source and drain regions within a first diffusion fin. The first diffusion fin projects from a surface of a substrate. The first diffusion fin extends lengthwise in a first direction from a first end to a second end of the first diffusion fin. A second transistor has source and drain regions within a second diffusion fin. The second diffusion fin projects from the surface of the substrate. The second diffusion fin extends lengthwise in the first direction from a first end to a second end of the second diffusion fin. The second diffusion fin is positioned next to and spaced apart from the first diffusion fin. Either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin. 1. A semiconductor device , comprising:a substrate;a first transistor having a source region and a drain region within a first diffusion fin, the first diffusion fin structured to project from a surface of the substrate, the first diffusion fin structured to extend lengthwise in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin;a second transistor having a source region and a drain region within a second diffusion fin, the second diffusion fin structured to project from the surface of the substrate, the second diffusion fin structured to extend lengthwise in the first direction from a first end of the second diffusion fin to a second end of the second diffusion fin, the second diffusion fin positioned next to and spaced apart from the first diffusion fin,wherein either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin.2. A semiconductor device as recited in claim 1 , wherein the first and second transistors are located at different positions in the second direction.3. A semiconductor device as recited ...

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30-05-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20130134412A1

To reduce oxygen vacancies in an oxide semiconductor film and the vicinity of the oxide semiconductor film and to improve electric characteristics of a transistor including the oxide semiconductor film. A semiconductor device includes a gate electrode whose Gibbs free energy for oxidation is higher than that of a gate insulating film. In a region where the gate electrode is in contact with the gate insulating film, oxygen moves from the gate electrode to the gate insulating film, which is caused because the gate electrode has higher Gibbs free energy for oxidation than the gate insulating film. The oxygen passes through the gate insulating film and is supplied to the oxide semiconductor film in contact with the gate insulating film, whereby oxygen vacancies in the oxide semiconductor film and the vicinity of the oxide semiconductor film can be reduced. 1. A semiconductor device comprising:an oxide semiconductor film;a gate electrode overlapping with the oxide semiconductor film; anda gate insulating film provided between the oxide semiconductor film and the gate electrode,wherein the gate electrode comprises a first region and a second region,wherein the first region is closer to the gate insulating film than the second region, andwherein an oxygen concentration of the first region is lower than an oxygen concentration of the second region.2. The semiconductor device according to claim 1 , wherein the gate electrode includes one or more elements selected from silver claim 1 , copper claim 1 , ruthenium claim 1 , iridium claim 1 , platinum claim 1 , and gold.3. The semiconductor device according to claim 1 , wherein the gate electrode includes ruthenium.4. The semiconductor device according to claim 1 , wherein the gate electrode includes a substance having higher Gibbs free energy for oxidation than a substance of the gate insulating film.5. The semiconductor device according to claim 1 , wherein the gate insulating film has an oxygen-transmitting property.6. The ...

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06-06-2013 дата публикации

Thin and Flexible Gallium Nitride and Method of Making the Same

Номер: US20130140517A1
Принадлежит: PURDUE RESEARCH FOUNDATION

A material for use in electronic circuits. The material includes a thin layer of gallium nitride (GaN), the thin layer of GaN produced in a high-volume production setting without mechanical planarization having a thickness of as low as 10 nm and a defect density as low as 10per cm. 1. A material for use in electronic circuits , comprising:{'sup': 5', '2, 'a thin layer of gallium nitride (GaN), the thin layer of GaN produced in a high-volume production setting without mechanical planarization having a thickness of as low as 10 nm and a defect density as low as 10per cm.'}2. The material for use in electronic circuits of claim 1 , the thin layer of GaN is configured to be separated from a support structure claim 1 , the support structure is decomposed prior to the separation claim 1 , and the support structure includes at least one layer containing indium.3. The material for use in electronic circuits of claim 2 , the separated thin layer of GaN is configured to be flexible.4. The material for use in electronic circuits of claim 1 , the thin layer of GaN is configured to be sheared from a support structure claim 1 , the support structure is an epitaxial GaN structure claim 1 , the epitaxial GaN structure has an adjustable and controllable thickness claim 1 , and the thickness of the epitaxial GaN structure is as low as 50 nm.5. The material for use in electronic circuits of claim 4 , the epitaxial GaN structure includes a plurality of nanorods claim 4 , the thickness of nanorods and the spacing between the nanorods is adjustable and controllable claim 4 , the thickness of the nanorods is as low as 5 nm claim 4 , and the spacing between the nanorods is as low as 5 nm.6. The material for use in electronic circuits of claim 4 , the shearing of epitaxial GaN structure is performed by one of mechanical disruption claim 4 , optical disruption claim 4 , thermal disruption claim 4 , and chemical disruption.7. The material for use in electronic circuits of claim 4 , the ...

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06-06-2013 дата публикации

Localized carrier lifetime reduction

Номер: US20130140667A1

A semiconductor structure includes a substrate, a first power device and a second power device in the substrate, at least one isolation feature between the first and second power device, and a trapping feature adjoining the at least one isolation feature in the substrate.

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13-06-2013 дата публикации

n- and p-Channel Field Effect Transistors with Single Quantum Well for Complementary Circuits

Номер: US20130149845A1

A complementary metal oxide semiconductor (CMOS) device in which a single InGaSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InGaSb layer is part of a heterostructure that includes a Te-delta doped AlGaSb layer above the InGaSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlGaSb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlGaSb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InGaSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure. 1. A method for forming a complementary semiconductor device having a single quantum well layer serving as a transport channel for both holes and electrons , comprising:forming a heterostructure comprising a single quantum well layer and a doped barrier layer; andremoving the doped bather layer from a portion of the heterostructure;wherein the portion of the heterostructure where the doped barrier layer is removed forms a p-FET and the portion of the heterostructure where the doped barrier layer is not removed forms an n-FET, the p-FET and the n-FET forming a complementary device; andwherein the single quantum well layer serves as a hole transport channel for the p-FET and as an electron transport channel for the n-FET in the complementary semiconductor device.2. A method for forming a complementary semiconductor device having a single quantum well layer serving as a transport channel for both holes and electrons , comprising:forming a heterostructure comprising a single quantum well layer and a doped barrier layer, the doped bather layer being formed on only a portion of the hetero structure;wherein the portion of the heterostructure on which the doped bather layer is formed ...

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20-06-2013 дата публикации

PIEZOELECTRIC DEVICES AND METHODS FOR THEIR PREPARATION AND USE

Номер: US20130153924A1
Принадлежит: INDIAN INSTITUTE OF TECHNOLOGY MADRAS

Methods for fabricating a piezoelectric device are provided. The methods can include providing a substrate and forming a nanocrystalline diamond layer on a first surface of the substrate. The methods can also include depositing a piezoelectric layer on a first surface of the nanocrystalline diamond layer. 1. A method for fabricating a piezoelectric device , the method comprising:providing a substrate;forming a nanocrystalline diamond (NCD) layer on a first surface of the substrate; anddepositing a piezoelectric layer on a first surface of the nanocrystalline diamond layer.2. The method of claim 1 , wherein the substrate comprises silicon.3. The method of claim 1 , wherein the piezoelectric layer has a perovskite structure.4. The method of claim 1 , wherein the forming a nanocrystalline diamond (NCD) layer comprises using a chemical vapor deposition (CVD) technique.56.-. (canceled)7. The method of claim 1 , wherein the depositing a piezoelectric layer comprises using a pulsed laser deposition (PLD) technique.8. The method of claim 1 , wherein the piezoelectric layer comprises lead zirconate titanate (PZT).9. The method of claim 1 , wherein the piezoelectric layer comprises lead lanthanum zirconate titanate (PLZT).10. The method of claim 1 , wherein depositing the piezoelectric layer comprises exposing a piezoelectric target placed within a pulsed laser deposition (PLD) chamber to a laser source.11. The method of claim 10 , further comprising annealing the deposited piezoelectric layer.12. The method of claim 10 , wherein a deposition temperature within the PLD chamber is about 525° C. to about 600° C.13. The method of claim 12 , wherein the deposition temperature is about 550° C.14. The method of claim 10 , wherein a deposition pressure within the PLD chamber is about 0.4 mbar to about 0.6 mbar.15. A method for fabricating a piezoelectric device claim 10 , the method comprising:providing a diamond substrate; anddepositing a lead zirconate titanate (PZT) layer on a ...

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20-06-2013 дата публикации

Memory Cell Constructions, and Methods for Fabricating Memory Cell Constructions

Номер: US20130157410A1
Автор: Li Jian, Liu Jun
Принадлежит: MICRON TECHNOLOGY, INC.

Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals. 1. A method for fabricating a memory cell construction , comprising:forming a memory cell to comprise a programmable material directly against another material; said other material having a different coefficient of expansion than the programmable material;forming a retaining shell adjacent the programmable material;exposing the memory cell to thermal processing to increase a temperature of the materials of the memory cell by at least about 200° C.; the exposure to said thermal processing creating a first stress due to the different rates of thermal expansion of the programmable material and the other material; the retaining shell providing a second stress which is at least about equal to the first stress to substantially balance the first stress.2. The method of wherein the retaining shell comprises one or more of metal claim 1 , carbon claim 1 , silicon nitride and silicon dioxide.3. The method of wherein the programmable material comprises germanium claim 1 , antimony and tellurium; and wherein the retaining shell comprises silicon nitride having an ...

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27-06-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20130161611A1

Release of oxygen at a side surface of an island-shaped oxide semiconductor film is controlled and decrease in resistance is prevented. A semiconductor device includes an island-shaped oxide semiconductor film at least partly including a crystal, a first gate insulating film provided to cover at least a side surface of the island-shaped oxide semiconductor film, and a second gate insulating film provided to cover at least the island-shaped oxide semiconductor film and the first gate insulating film. The first gate insulating film is an insulating film that supplies oxygen to the island-shaped oxide semiconductor film, and the second gate insulating film is an insulating film which has a low oxygen-transmitting property 1. A semiconductor device comprising:an island-shaped oxide semiconductor film;a first gate insulating film covering at least side faces of the island-shaped oxide semiconductor film; anda second gate insulating film covering the island-shaped oxide semiconductor film and the first gate insulating film,wherein the second gate insulating film has a lower oxygen-transmitting property than that of the first gate insulating film.2. The semiconductor device according to claim 1 ,wherein at least one kind of metal contained in the island-shaped oxide semiconductor film, andwherein atoms of the metal is arranged in a layered manner parallel to a surface where the island-shaped oxide semiconductor film is formed.3. The semiconductor device according to claim 2 , wherein the metal is indium.4. The semiconductor device according to claim 1 ,wherein the island-shaped oxide semiconductor film has a layered structure of at least two layers, each of a lower layer and an upper layer of the layered structure comprising at least a metal.5. The semiconductor device according to claim 4 , wherein each of the lower layer and the upper layer comprises gallium claim 4 , zinc claim 4 , and indium.6. The semiconductor device according to claim 5 ,wherein in the lower layer, ...

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27-06-2013 дата публикации

METHODS OF FORMING DILUTE NITRIDE MATERIALS FOR USE IN PHOTOACTIVE DEVICES AND RELATED STRUCTURES

Номер: US20130164874A1
Принадлежит: SOITEC

Atomic layer deposition (ALD) or ALD-like deposition processes are used to fabricate dilute nitride III-V semiconductor materials. A first composition of process gases may be caused to flow into a deposition chamber, and a group V element other than nitrogen and one or more group III elements may be adsorbed over the substrate (in atomic or molecular form). Afterward, a second composition of process gases may be caused to flow into the deposition chamber, and N and one or more group III elements may be adsorbed over the substrate in the deposition chamber. An epitaxial layer of dilute nitride III-V semiconductor material may be formed over the substrate in the deposition chamber from the sequentially adsorbed elements. 1. A method of fabricating a dilute nitride III-V semiconductor material , comprising:flowing a first plurality of process gases into a deposition chamber, the first plurality of process gases including an arsenic-containing precursor gas;depositing a first layer comprising As and one or more of B, Al, Ga, In, and Ti over a substrate in the deposition chamber from the first plurality of process gases, the first layer being at least substantially free of N;after depositing the first layer, flowing a second plurality of process gases into the deposition chamber, the second plurality of process gases including a nitrogen-containing precursor gas;depositing a second layer comprising N and one or more of B, Al, Ga, In, and Ti over the substrate in the deposition chamber from the second plurality of process gases; andepitaxially growing a dilute nitride III-V semiconductor material over the substrate in the deposition chamber using the first layer and the second layer.2. The method of claim 1 , wherein the first plurality of process gases is at least substantially free of nitrogen-containing precursor gas.3. The method of claim 1 , wherein the second plurality of process gases is at least substantially free of arsenic-containing precursor gas.4. The method ...

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27-06-2013 дата публикации

METHODS OF FORMING A THIN FILM AND METHODS OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING USING THE SAME

Номер: US20130164907A1
Автор: Lee Dongkak
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Provided are methods of forming a thin film and methods of fabricating a semiconductor device including the same. The thin film forming methods may include supplying an organic silicon source to form a silicon seed layer on a lower layer, the silicon seed layer including silicon seed particles adsorbed on the lower layer, and supplying an inorganic silicon source to deposit a silicon film on the lower layer adsorbed with the silicon atoms. 1. A method of forming a thin film , comprising:supplying an organic silicon source to form a silicon seed layer on a lower layer on a substrate, the silicon seed layer including silicon seed particles adsorbed on the lower layer; andsupplying an inorganic silicon source to deposit a silicon film on the lower layer adsorbed with the silicon seed particles.2. The method of claim 1 , wherein the silicon film is formed to have a thickness ranging from about 1 nm to 10 nm.3. The method of claim 1 , wherein the silicon seed layer is formed to have a thickness ranging from about 0.1 nm to 1.0 nm.4. The method of claim 1 , wherein the organic silicon source is a silicon compound comprising an amino group or a hydrocarbyl group.5. The method of claim 1 , wherein the organic silicon source is one of BisTertButylAminoSilane (BTBAS) claim 1 , DilsoPropylAminoSilane (DIPAS) claim 1 , BisDiEthylAminoSilane (BDEAS) claim 1 , BisEthylMethylAminoSilane (BEMAS) claim 1 , DiPropylAminoSilane (DPAS) claim 1 , DiEthylAminoSilane (DEAS) claim 1 , DiMethylAminoSilane (DMAS) claim 1 , BisDimethylAminoSilane (BDMAS) claim 1 , TrisDimethylAminoSilane (3DMAS) claim 1 , and tetrakis(DimethylAminoSilane) (4DMAS).6. The method of claim 1 , wherein the inorganic silicon source is one of SiH claim 1 , SiH claim 1 , SiH claim 1 , SiCl claim 1 , SiCl claim 1 , SiClH claim 1 , and DCS(SiClH).7. The method of claim 1 , wherein the silicon film is formed to have a poly-crystalline structure.8. The method of claim 1 , wherein forming the silicon seed layer is ...

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04-07-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Номер: US20130171809A1
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor device has a substrate that includes a cell array region and a dummy pattern region surrounding the cell array region. The cell array region includes a cell structure having a plurality of cell active pillars extending in a vertical direction from the cell array region of the substrate and includes cell gate patterns and cell gate interlayer insulating patterns alternately stacked on the substrate. The cell gate patterns and cell gate interlayer insulating patterns have sides facing the cell active pillars. The dummy pattern region includes a damp-proof structure. 114.-. (canceled)15. A method of fabricating a semiconductor device , the method comprising:preparing a substrate including a cell array region and a dummy pattern region surrounding the cell array region; andforming a cell structure and a damp-proof structure on the cell array region and the dummy pattern region, respectively,wherein the cell structure includes a plurality of cell active pillars extending in a vertical direction from the substrate; and cell gate patterns and cell gate interlayer insulating patterns are alternately stacked on the substrate and have sides facing the cell active pillars.16. The method as claimed in claim 15 , further comprising:forming an outer interlayer insulating layer filling a gap between the cell structure and the damp-proof structure; andforming a damp-proof layer covering upper surfaces of the cell structure, the damp-proof structure, and the outer interlayer insulating layer.17. The method as claimed in claim 15 , wherein the damp-proof structure is formed so as to surround the cell structure.18. The method as claimed in claim 15 , wherein forming the cell structure and the damp-proof structure at the cell array region and the dummy pattern region claim 15 , respectively claim 15 , includes:alternately stacking sacrificial layers and interlayer insulating layers on an entire surface of the substrate to form a stacked structure;forming the plurality ...

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11-07-2013 дата публикации

High strength bonding and coating mixture and method

Номер: US20130174980A1
Автор: Sang In LEE
Принадлежит: Ferrotec USA Corp

A method of using a high-strength bonding and coating mixture is disclosed. The mixture includes a silicon compound having a polycarbosilane backbone and a powder having a plurality of individual powder grains. Each of the powder grains has a diameter substantially between 0.05 micrometers and 50 micrometers. The mixture is applied to one or more work pieces and the work piece(s) is (are) heated in either an inert or reduction environment to a temperature sufficient to decompose the silicon compound into gaseous atoms and radicals of silicon and carbon.

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11-07-2013 дата публикации

Nonvolatile semiconductor memory device and method of manufacturing the same

Номер: US20130175490A1
Принадлежит: Individual

According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure.

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11-07-2013 дата публикации

Diamond Semiconductor System and Method

Номер: US20130175546A1
Автор: Khan Adam
Принадлежит: AKHAN Technologies, Inc.

Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein at least 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm/Vs to the diamond lattice at 100 kPa and 300K. 1. A method of fabricating a monolithically integrated diamond semiconductor , the method including the steps of:seeding the surface of a substrate material;forming a diamond layer upon the surface of the substrate material; andforming a semiconductor layer within the diamond layer,{'sup': '2', 'wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein at least 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm/Vs to the diamond lattice at 100 kPa and 300K.'}2. The method of fabricating a monolithically integrated diamond semiconductor of claim 1 , wherein the substrate material is selected from the group consisting of silicon claim 1 , silicon oxide claim 1 , refractory metal claim 1 , glass claim 1 , and wide band gap semiconductor material.3. The method of fabricating a monolithically integrated diamond semiconductor of claim 1 , wherein the diamond layer is formed using chemical vapor deposition.4. The method of fabricating a monolithically integrated diamond semiconductor of claim 1 , wherein the diamond layer is formed at or below 450 degrees Celsius.5. A monolithically integrated diamond semiconductor device formed according to the method of .6. The monolithically integrated diamond semiconductor device of claim 5 , wherein the device is one of a group consisting of an LED claim 5 , ...

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11-07-2013 дата публикации

THERMAL OXIDE FILM FORMATION METHOD FOR SILICON SINGLE CRYSTAL WAFER

Номер: US20130178071A1
Принадлежит: SHIN-ETSU HANDOTAI CO., LTD.

Disclosed is a method of forming a thermal oxide film on a silicon single crystal wafer, which includes throwing the silicon single wafer into a heat treatment furnace; elevating temperature of the heat treatment furnace up to a temperature T1 where a thermal oxide film is formed to form a thermal oxide film having a thickness d1; subsequently lowering the temperature of the heat treatment furnace down to a temperature lower than the temperature T1; and thereafter elevating the temperature of the heat treatment furnace up to a temperature T2 higher than the temperature T1 to additionally form a thermal oxide film having a thickness d2 thicker than the thickness d1. Thus, there is provided a thermal oxide film formation method to suppress occurrence of slip dislocation and/or crack of the silicon single wafer during formation of the thermal oxide film. 18-. (canceled)9. A method of forming a thermal oxide film on a silicon single crystal wafer , at least comprising:throwing the silicon single crystal wafer into a heat treatment furnace;elevating temperature of the heat treatment furnace up to a temperature T1 where a thermal oxide film is formed to form a thermal oxide film having a thickness d1;subsequently lowering the temperature of the heat treatment furnace down to a temperature lower than the temperature T1; and thereafterelevating the temperature of the heat treatment furnace up to a temperature T2 higher than the temperature T1 to additionally form a thermal oxide film having a thickness d2 thicker than the thickness d1.10. The method of forming a thermal oxide film on a silicon single crystal wafer according to claim 9 , whereinthe temperature of the heat treatment furnace is elevated up to the temperature T2 higher than the temperature T1 without taking out the silicon single crystal wafer from the heat treatment furnace to additionally form a thermal oxide film having the thickness d2 thicker than the thickness d1 after the temperature of the heat ...

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25-07-2013 дата публикации

Profile Engineered Thin Film Devices and Structures

Номер: US20130189823A1
Принадлежит:

The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch. 1. A method of making an electrically active device , comprising:a) printing a first ink composition comprising one or more first semiconductor and/or metal precursors onto a substrate, the first ink having one or more predetermined properties;b) curing the first precursor(s) to form a first electrically active layer having a smooth, dome-shaped profile; andc) forming a second electrically active layer conformally covering the first electrically active layer.2. The method of claim 1 , wherein the one or more first precursors are present in an amount of from 1 to 40% by weight of the first ink composition.3. The method of claim 2 , wherein the one or more first precursors are selected from the group consisting of (poly)silanes claim 2 , (poly)germanes claim 2 , (poly)germasilanes claim 2 , and nanoparticles of silicon and/or germanium.4. The method of claim 3 , wherein said (poly)silanes claim 3 , ( ...

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01-08-2013 дата публикации

PRODUCTION OF AN INTEGRATED CIRCUIT INCLUDING ELECTRICAL CONTACT ON SiC

Номер: US20130193449A1
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on an SiC substrate.

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01-08-2013 дата публикации

Display Device With Touch Panel

Номер: US20130194233A1
Автор: Masahiro Teramoto
Принадлежит: Individual

A touch panel includes a substrate having a plurality of first electrodes extending in a first direction on the substrate, and a plurality of second electrodes three-dimensionally intersecting the plurality of first electrodes. Each of the plurality of first electrodes includes a first portion formed on a layer different from a layer of the plurality of second electrodes to three-dimensionally intersect one of the plurality of second electrodes, and a second portion formed on the same layer as the layer of the plurality of second electrodes to be separated from the plurality of second electrodes. An insulating film made of negative resist is formed between the first portion and the second portion, and the first portion is electrically connected to the second portion via a contact portion formed through the insulating film.

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01-08-2013 дата публикации

METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR CRYSTAL LAYER

Номер: US20130196487A1
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a method is disclosed for manufacturing a nitride semiconductor crystal layer. The method can include forming the nitride semiconductor crystal layer having a first thickness on a silicon crystal layer. The silicon crystal layer is provided on a base body. The silicon crystal layer has a second thickness before the forming the nitride semiconductor crystal layer. The second thickness is thinner than the first thickness. The forming the nitride semiconductor crystal layer includes making at least a portion of the silicon crystal layer incorporated into the nitride semiconductor crystal layer to reduce a thickness of the silicon crystal layer from the second thickness. 1. A method for manufacturing a nitride semiconductor crystal layer comprising:forming the nitride semiconductor crystal layer having a first thickness on a silicon crystal layer, the silicon crystal layer being provided on a base body,the silicon crystal layer having a second thickness before the forming the nitride semiconductor crystal layer, the second thickness being thinner than the first thickness,the forming the nitride semiconductor crystal layer including making the silicon crystal layer incorporated into the nitride semiconductor crystal layer to reduce a thickness of the silicon crystal layer from the second thickness and to cause disappearance of the silicon crystal layer.2. The method according to claim 1 , whereinthe base body includes a substrate,the forming the nitride semiconductor crystal layer further includes: the substrate, and', 'the nitride semiconductor crystal layer provided on the substrate, and silicon included in the silicon crystal layer is introduced in the nitride semiconductor crystal layer., 'forming a structure including'}3. The method according to claim 2 , wherein the base body has a crystal profile which differs from a crystal profile of the silicon crystal layer.4. The method according to claim 2 , wherein a melt back etching of the ...

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08-08-2013 дата публикации

COMPOUND SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME

Номер: US20130200424A1
Принадлежит:

According to the present invention, a method for manufacturing a compound semiconductor comprises: forming a graphene-derived material layer on either a first selected substrate or a first selected compound semiconductor layer; forming a second compound semiconductor layer of at least one layer on at least said graphene-derived material layer, and changing the graphene-derived material layer so as to separate said second compound semiconductor layer of at least one layer. 1. A method for manufacturing a compound semiconductor , the method comprising:forming a graphene-derived material layer on one of a first substrate and a first compound semiconductor layer;forming at least one layer of second compound semiconductor layers on the graphene-derived material layer; andtransforming the graphene-derived material layer to separate at least one layer of the second compound semiconductor layers.2. The method of claim 1 , wherein the graphene-derived material layer is a graphene layer.3. The method of claim 2 , wherein the graphene layer is transformed into a graphene oxide layer by one method among a chemical treatment method claim 2 , a heat treatment method and a photo treatment method.4. The method of claim 1 , wherein the graphene-derived material layer is a graphene layer claim 1 , and the transformed material layer from the graphene-derived material layer is a graphene oxide layer claim 1 ,a thickness of the graphene oxide layer being greater than that of the graphene layer, and at least one layer of the second compound semiconductor layers being lifted up.5. The method of claim 1 , wherein the graphene-derived material layer is a graphene oxide layer.6. The method of claim 5 , wherein the graphene layer is transformed by one method among a chemical treatment method claim 5 , a heat treatment method and a photo treatment method.7. The method of claim 6 , wherein the graphene oxide layer is transformed into a transformed graphene oxide layer having a greater thickness ...

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08-08-2013 дата публикации

SEMICONDUCTOR COMPONENT, SUBSTRATE AND METHOD FOR PRODUCING A SEMICONDUCTOR LAYER SEQUENCE

Номер: US20130200432A1
Принадлежит: OSRAM Opto Semiconductors GmbH

A semiconductor component includes a semiconductor body based on a nitride compound semiconductor material, and a substrate on which the semiconductor body is arranged, wherein impurities are formed in the substrate in a targeted manner. 1. A semiconductor component comprising:a semiconductor body based on a nitridic compound semiconductor material, anda substrate on which the semiconductor body is arranged, wherein impurities are formed in the substrate in a targeted manner.2. The semiconductor component according to claim 1 , wherein the impurities are provided to increase an upper yield point of the substrate.3. The semiconductor component according to claim 1 , wherein the substrate has a silicon surface.4. The semiconductor component according to claim 3 , wherein the surface is a (111) plane.5. The semiconductor component according to claim 1 , wherein the substrate is a silicon bulk substrate.6. The semiconductor component according to claim 1 , wherein the impurities are formed with a concentration of 1*10cmto 1*10cmin the substrate.7. The semiconductor component according to claim 1 , wherein the impurities contain at least one of carbon claim 1 , nitrogen claim 1 , boron or oxygen.8. The semiconductor component according to claim 1 , wherein the semiconductor body has an active region provided to generate and/or receive radiation.9. The semiconductor component according to claim 1 , which is an electronic semiconductor component.10. A substrate for deposition of nitridic compound semiconductor material claim 1 , wherein impurities that increase its upper yield point are formed in a targeted manner in the substrate.11. (canceled)124. A method for producing a semiconductor layer sequence based on a nitridic compound semiconductor material comprising depositing the semiconductor layer sequence on a substrate claim 1 , in which impurities () are formed in a targeted manner.13. The method according to claim 12 , wherein the substrate is removed or thinned at ...

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08-08-2013 дата публикации

High-k heterostructure

Номер: US20130200440A1

A method for preparing a multilayer substrate includes the step of deposing an epitaxial γ-Al 2 O 3 Miller index (001) layer on a Si Miller index (001) substrate.

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08-08-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20130200485A1
Автор: Naruse Hiroaki
Принадлежит: CANON KABUSHIKI KAISHA

A method for manufacturing a semiconductor device, the method comprising, forming an opening in an insulating layer, which is formed on a semiconductor substrate, using a photoresist pattern formed on the insulating layer as a mask, forming a first element isolation portion in the semiconductor substrate by implanting an ion into the semiconductor substrate using the photoresist pattern as a mask, forming a second element isolation portion, in the semiconductor substrate, whose outer edge is outside an outer edge of the opening, by implanting an ion into the semiconductor substrate through the opening, and forming a third element isolation portion, which is inside the outer edge of the second element isolation portion, by embedding an insulating member in the opening and removing the insulating layer. 1. A method for manufacturing a semiconductor device , the method comprising:forming an opening in an insulating layer, which is formed on a semiconductor substrate, using a photoresist pattern formed on the insulating layer as a mask;forming a first element isolation portion in the semiconductor substrate by implanting an ion into the semiconductor substrate using the photoresist pattern as a mask;forming a second element isolation portion, in the semiconductor substrate, whose outer edge is outside an outer edge of the opening, by implanting an ion into the semiconductor substrate through the opening; andforming a third element isolation portion, which is inside the outer edge of the second element isolation portion, by embedding an insulating member in the opening and removing the insulating layer.2. The method according to claim 1 , wherein the forming the second element isolation portion is performed after the forming the first element isolation portion.3. The method according to claim 2 , further comprising:removing the photoresist pattern after the forming the first element isolation portion and before the forming the second element isolation portion.4. The ...

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08-08-2013 дата публикации

OPTICAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING OPTICAL SEMICONDUCTOR DEVICE

Номер: US20130202248A1
Принадлежит:

An optical semiconductor device includes: a waveguide unit which is formed on a semiconductor substrate including a (100) plane and includes a core layer which propagates light; a spot size converting unit which is formed on the semiconductor substrate, is optically connected to the waveguide unit, and converts diameter of light propagated; and a pair of terraces which are formed on the semiconductor substrate and are opposed to each other while sandwiching the spot size converting unit. Interval between opposed units which are opposed to each other while sandwiching the spot size converting unit in the pair of terraces changes, and each of the opposed units includes a part whose orientation tilts to a [0-11] direction with respect to a [011] direction, and position of an upper end of the spot size converting unit is higher than that of an upper end of the waveguide unit. 1. An optical semiconductor device comprising:a waveguide unit which is formed on a semiconductor substrate having a (100) plane and includes a core layer which propagates light;a spot size converting unit which is formed on the semiconductor substrate, is optically connected to the waveguide unit, and converts diameter of light propagated; anda pair of terraces which are formed on the semiconductor substrate and opposed to each other while sandwiching the spot size converting unit,wherein interval between opposed units which are opposed to each other while sandwiching the spot size converting unit in the pair of terraces changes, and each of the opposed units includes a part whose orientation tilts to a [0-11] direction with respect to a [011] direction, andposition of an upper end of the spot size converting unit is higher than position of an upper end of the waveguide unit.2. The optical semiconductor device according to claim 1 , wherein the interval of the pair of terraces repeats enlargement and reduction.3. The optical semiconductor device according to claim 1 , wherein a part higher than ...

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08-08-2013 дата публикации

METHODS FOR ENHANCING P-TYPE DOPING IN III-V SEMICONDUCTOR FILMS

Номер: US20130203243A1
Принадлежит: The University of Utah

Methods of doping a semiconductor film are provided. The methods comprise epitaxially growing the III-V semiconductor film in the presence of a dopant, a surfactant capable of acting as an electron reservoir, and hydrogen, under conditions that promote the formation of a III-V semiconductor film doped with the p-type dopant. In some embodiments of the methods, the epitaxial growth of the doped III-V semiconductor film is initiated at a first hydrogen partial pressure which is increased to a second hydrogen partial pressure during the epitaxial growth process. 1. A method of doping a III-V semiconductor film , the method comprising:presenting a p-type dopant to an epitaxial growth process;presenting a surfactant capable of acting as an electron reservoir to the epitaxial growth process;presenting hydrogen to the epitaxial growth process; andgrowing a III-V semiconductor film under conditions that promote the formation of a p-type doped III-V semiconductor film.2. The method recited in claim 1 , wherein the presenting a p-type dopant to an epitaxial growth process comprises presenting magnesium.3. The method recited in claim 1 , wherein the presenting a p-type dopant to an epitaxial growth process comprises presenting beryllium.4. The method recited in claim 1 , wherein the presenting a p-type dopant to an epitaxial growth process comprises presenting cadmium.5. The method recited in claim 1 , wherein the presenting a surfactant capable of acting as an electron reservoir to the epitaxial growth process comprises presenting Sb.6. The method recited in claim 1 , wherein the presenting a surfactant capable of acting as an electron reservoir to the epitaxial growth process comprises presenting Bi.7. The method recited in claim 1 , wherein the presenting hydrogen to the epitaxial growth process comprises:presenting hydrogen at a first hydrogen partial pressure; andincreasing the hydrogen partial pressure from the first hydrogen partial pressure to a second hydrogen partial ...

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12-09-2013 дата публикации

Composite target sputtering for forming doped phase change materials

Номер: US20130234093A1

A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition.

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12-09-2013 дата публикации

Moisture and/or electrically conductive remains detection for wafers after rinse / dry process

Номер: US20130236274A1
Принадлежит: Globalfoundries Inc

A method, device, and apparatus is provided for detecting moisture and/or electrically conductive remains on a wafer after the wafer is removed from a drying chamber of a processing tool that includes wet clean processing. Embodiments include fixing a wafer to an endeffector between a processing chamber and a FOUP, moving the wafer from the processing chamber toward the FOUP, detecting moisture and/or electrically conductive remains on the wafer, and delivering the wafer to the FOUP, if no moisture and/or electrically conductive remains are detected, or delivering the wafer to a buffer station, if moisture and/or electrically conductive remains are detected.

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19-09-2013 дата публикации

Process for production of functional device, process for production of ferroelectric material layer, process for production of field effect transistor, thin film transistor, field effect transistor, and piezoelectric inkjet head

Номер: US20130240871A1
Принадлежит: JAPAN SCIENCE AND TECHNOLOGY AGENCY

A method of producing a functional device according to the present invention includes, in this order: the functional solid material precursor layer formation step of applying a functional liquid material onto a base material to form a precursor layer of a functional solid material; the drying step of heating the precursor layer to a first temperature in a range from 80° C. to 250° C. to preliminarily decrease fluidity of the precursor layer; the imprinting step of imprinting the precursor layer that is heated to a second temperature in a range from 80° C. to 300° C. to form an imprinted structure on the precursor layer; and the functional solid material layer formation step of heat treating the precursor layer at a third temperature higher than the second temperature to transform the precursor layer into a functional solid material layer.

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26-09-2013 дата публикации

METHOD OF MANUFACTURING PHOTONIC CRYSTAL AND METHOD OF MANUFACTURING SURFACE-EMITTING LASER

Номер: US20130252360A1
Автор: Hoshino Katsuyuki
Принадлежит: CANON KABUSHIKI KAISHA

Provided is a method of manufacturing a photonic crystal, including: a first step of forming, on a surface of a substrate, a protective mask for selective growth, the protective mask having an opening pattern opened therein; a second step of selectively growing a columnar semiconductor from an exposed portion of the surface of the substrate not having the mask formed thereon, laterally overgrowing the semiconductor layer on the mask, and embedding the mask; a third step of forming a photonic crystal in the semiconductor layer so that openings in the opening pattern and the one of pores and grooves which form the photonic crystal are at least partly overlapped each other when seen from a direction perpendicular to the surface of the substrate; a fourth step of removing at least part of the columnar semiconductor; and a fifth step of removing at least part of the mask. 1. A method of manufacturing a photonic crystal formed by periodically arranging media having different refractive indices , the media including a semiconductor layer and one of pores and grooves , the method comprising:a first step of forming, on a surface of a substrate, a protective mask for selective growth, the protective mask having an opening pattern opened therein;a second step of selectively growing a columnar semiconductor from an exposed portion of the surface of the substrate not having the protective mask formed thereon, laterally overgrowing the semiconductor layer on the protective mask, and embedding the protective mask;a third step of forming a photonic crystal in the semiconductor layer so that openings in the opening pattern and the one of pores and grooves which form the photonic crystal are at least partly overlapped each other when seen from a direction perpendicular to the surface of the substrate;a fourth step of removing at least part of the columnar semiconductor; anda fifth step of removing at least part of the protective mask.2. The method of manufacturing a photonic crystal ...

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03-10-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20130256686A1
Автор: KANAMURA MASAHITO
Принадлежит: FUJITSU LIMITED

A semiconductor device includes: a first semiconductor layer formed over a substrate; a second semiconductor layer formed over the first semiconductor layer; an insulating film including a first insulating film formed over the second semiconductor layer, a second insulating film, and a third insulating film stacked sequentially over the first insulating film, and an electrode formed over the insulating film, wherein, in the first insulating film, a region containing halogen ions is formed under a region provided with the electrode, and the third insulating film contains a halogen. 1. A semiconductor device comprising:a first semiconductor layer formed over a substrate;a second semiconductor layer formed over the first semiconductor layer;an insulating film including a first insulating film formed over the second semiconductor layer, a second insulating film, and a third insulating film stacked sequentially over the first insulating film, andan electrode formed over the insulating film,wherein, in the first insulating film, a region containing halogen ions is formed under a region provided with the electrode, andthe third insulating film contains a halogen.2. The semiconductor device according to claim 1 , further comprising:a recess is formed in the third insulating film in the region, in which the electrode is provided, by removing part of the third insulating film.3. The semiconductor device according to claim 1 , whereinthe halogen is chlorine or fluorine.4. The semiconductor device according to claim 1 , whereinthe insulating film contains any one of an oxide, a nitride, and an oxynitride.5. The semiconductor device according to claim 1 ,{'sub': 2', '3', '2', '2', '2', '5', '2, 'wherein, the insulating film contains at least one material of AlO, SiO, HfO, TaO, ZrO, MgO, SiN, AlN, SiON, and AlON.'}6. The semiconductor device according to claim 1 , whereinthe insulating film contains aluminum oxide.7. The semiconductor device according to claim 1 , whereinthe ...

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17-10-2013 дата публикации

METHODS OF FORMING A POLYSILICON LAYER AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

Номер: US20130273704A1
Принадлежит:

A method of forming a polysilicon layer includes providing a silicon precursor onto an object loaded in a process chamber to form a seed layer. The silicon precursor includes a nitrogen containing silicon precursor and a chlorine containing silicon precursor. The method further includes providing a silicon source on the seed layer. 1. A method of forming a polysilicon layer , comprising:providing a silicon precursor onto an object loaded in a process chamber to form a seed layer, wherein the silicon precursor includes a nitrogen containing silicon precursor and a chlorine containing silicon precursor; andproviding a silicon source on the seed layer.2. The method of claim 1 , wherein the nitrogen containing silicon precursor includes at least one selected from the group consisting of Bis(ethlymethylamino)silane (BEMAS) claim 1 , Bis(diethylamino)silane (BDEAS) claim 1 , Bis(dimethylamino)silane (BDMAS) claim 1 , tris(dimethylamino)silane (Tris-DMAS) claim 1 , tetrakis(dimethylamino)silane (TDMAS) claim 1 , tris(ethlymethylamino)silane (Tris-EMAS) claim 1 , Diethylaminosiliane (DEAS) claim 1 , Bis(tertybutylamino)silane (BTBAS) and Di-Isopropyl-Amino-Silane (DIPAS).3. The method of claim 1 , wherein the chlorine containing silicon precursor includes at least one selected from the group consisting of dichlorosilane (SiClH) claim 1 , trichlorosilane (SiClH) claim 1 , tetrachlorosilane (SiCl) and hexachlorodisilane (SiCl).4. The method of claim 1 , wherein the silicon source includes at least one selected from the group consisting of silane (SiH) claim 1 , disilane (SiH) and trisilane (SiH).5. The method of claim 1 , wherein the process chamber includes an atomic layer deposition (ALD) process chamber.6. The method of claim 1 , wherein the providing of the silicon precursor onto the object loaded in the process chamber to form the seed layer comprises:providing the nitrogen containing silicon precursor onto the object loaded in the process chamber to form a preliminary ...

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31-10-2013 дата публикации

Method for making epitaxial structure

Номер: US20130288457A1
Автор: Shou-Shan Fan, Yang Wei
Принадлежит: Individual

A method for making epitaxial structure is provided. The method includes providing a substrate having an epitaxial growth surface, placing a graphene layer on the epitaxial growth surface, and epitaxially growing an epitaxial layer on the epitaxial growth surface. The graphene layer includes a number of apertures to expose a part of the epitaxial growth surface. The epitaxial layer is grown from the exposed part of the epitaxial growth surface and through the aperture.

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31-10-2013 дата публикации

Methods of Forming Doped Regions in Semiconductor Substrates

Номер: US20130288466A1
Принадлежит: Micron Technology Inc

Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.

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14-11-2013 дата публикации

Semiconductor device and manufacturing method

Номер: US20130299875A1
Автор: ZHONGSHAN Hong

A fabrication process of a semiconductor device is disclosed. The method includes providing a semiconductor substrate with a first insulation layer formed on the semiconductor substrate and a fin formed on the surface of the first insulation layer, and forming a fully-depleted semiconductor layer on sidewalls of the fin, and the fully-depleted semiconductor layer having a material different from that of the fin. The method also includes forming a second insulation layer covering the fully-depleted semiconductor layer, and removing the fin to form an opening exposing sidewalls of the fully-depleted semiconductor layer. Further, the method includes forming a gate dielectric layer on part of the sidewalls of the fully-depleted semiconductor layer such that the part of the sidewalls of the fully-depleted semiconductor layer form channel regions of the semiconductor device, and forming a gate electrode layer covering the gate dielectric layer.

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21-11-2013 дата публикации

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

Номер: US20130309877A1
Принадлежит:

A silicon carbide semiconductor device (), includes: 1) a silicon carbide substrate (); 2) a gate electrode () made of polycrystalline silicon; and 3) an ONO insulating film () sandwiched between the silicon carbide substrate () and the gate electrode () to thereby form a gate structure, the ONO insulating film () including the followings formed sequentially from the silicon carbide substrate (): a) a first oxide silicon film (O) (), b) an SiN film (N) (), and c) an SiN thermally-oxidized film (O) (). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) () and in a vicinity of the silicon carbide substrate (), and ii) in an interface between the silicon carbide substrate () and the first oxide silicon film (O) (). 132-. (canceled)33. A method for producing a silicon carbide semiconductor device , a silicon carbide substrate;', 'a gate electrode made of polycrystalline silicon; and', 'an ONO insulating film sandwiched between the silicon carbide substrate and the gate electrode to thereby form a gate structure, the ONO insulating film including the followings formed sequentially from the silicon carbide substrate:', 'a first oxide silicon film (O),', 'an SiN film (N), and', 'an SiN thermally-oxidized film (O),, 'the silicon carbide semiconductor device comprisingthe method comprising forming the first oxide silicon film (O) by thermally oxidizing a surface of the silicon carbide substrate in an oxidized nitrogen (NOx) gas atmosphere.34. The method for producing the silicon carbide semiconductor device as claimed in claim 33 , wherein the oxidized nitrogen (NOx) gas atmosphere is formed by supplying any one of the following gases:{'sub': '2', 'i) NO (nitrous oxide),'}ii) NO (nitrogen monoxide),{'sub': '2', 'iii) NO(nitrogen dioxide),'}iv) a mixture of at least two of i) to iii),v) a diluted gas of any of i) to iii), andvi) a diluted gas of the mixture in iv).35. The method for producing the silicon carbide semiconductor ...

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05-12-2013 дата публикации

METHOD FOR FORMING SEMICONDUCTOR DEVICE

Номер: US20130323911A1
Автор: Cho Young Man
Принадлежит: SK HYNIX INC.

A method for forming a semiconductor device is disclosed. In the semiconductor device, a gate is formed to enclose a fin structure in a 6Fsaddle fin gate structure transistor, so that the size of a channel region increases. In accordance with an aspect of the present invention, a method for forming a semiconductor device includes: defining an active region by forming a device isolation film over a semiconductor substrate; forming a first recess extending to a first level in the active region; forming a sacrificial film at a lower portion of the first recess; forming a fin structure over the sacrificial film; separating the fin structure from the semiconductor substrate in the active region by removing the sacrificial film and forming a hole between the fin structure and the active region; and forming a gate to enclose the fin structure. 1. A method for forming a semiconductor device comprising:defining an active region by forming a device isolation film over a semiconductor substrate;forming a first recess extending to a first level in the active region;forming a sacrificial film at a lower portion of the first recess;forming a fin structure over the sacrificial film;separating the fin structure from the semiconductor substrate in the active region by removing the sacrificial film and forming a hole between the fin structure and the active region; andforming a gate to enclose the fin structure.2. The method according to claim 1 , wherein the forming the fin structure includes:forming an epitaxial growth layer over the sacrificial film; andforming a second recess by partially etching the silicon epitaxial growth layer and the device isolation film, andforming the remaining silicon epitaxial growth layer as the fin structure.3. The method according to claim 2 , wherein the forming the gate to enclose the fin structure includes:depositing a polysilicon material to fill the hole and the second recess; andforming the gate by etching back the polysilicon material.4. The ...

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23-01-2014 дата публикации

Method of Making a Multicomponent Film

Номер: US20140024173A1
Принадлежит:

Described herein is a method and liquid-based precursor composition for depositing a multicomponent film. In one embodiment, the method and compositions described herein are used to deposit Germanium Tellurium (GeTe), Antimony Tellurium (SbTe), Antimony Germanium (SbGe), Germanium Antimony Tellurium (GST), Indium Antimony Tellurium (IST), Silver Indium Antimony Tellurium (AIST), Cadmium Telluride (CdTe), Cadmium Selenide (CdSe), Zinc Telluride (ZnTe), Zinc Selenide (ZnSe), Copper indium gallium selenide (CIGS) films or other tellurium and selenium based metal compounds for phase change memory and photovoltaic devices. 19-. (canceled)10. A method of depositing a multicomponent film on a substrate comprising steps of:(a) contacting the substrate with an In precursor or a precursor solution comprising the In precursor to react with the substrate to provide a first coating layer comprising In;(b) rinsing at least a portion of the first coating layer with a rinse solution to remove any unreacted In precursor;(c) contacting the first coating layer comprising In with a Te precursor or a precursor solution comprising the Te precursor, wherein at least a portion of the Te precursor reacts with the In comprised therein to provide a second coating layer comprising In and Te;(d) rinsing at least a portion of the second coating layer with rinse solution to remove any unreacted Te precursor;(e) contacting the second coating layer comprising In and Te with a Sb precursor or a precursor solution comprising the Sb precursor, wherein at least a portion of the Sb precursor reacts with at least a portion of the In and Te comprised therein to provide a third coating layer comprising In, Sb, and Te;(f) rinsing at least a portion of the third coating layer with rinse solution to remove any unreacted Sb precursor,(g) contacting the third coating layer comprising In, Te, and Sb with a Te precursor or a precursor solution comprising the Te precursor to provide a fourth coating layer ...

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06-02-2014 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20140035030A1
Принадлежит:

According to one embodiment, in a semiconductor device, a semiconductor laminated body includes a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type provided on the first semiconductor region and having a higher concentration of impurities than that of the first semiconductor region. A third semiconductor region includes a side surface and a lower end, the side surface and the lower end are surrounded by the semiconductor laminated body. A fourth semiconductor region of a second conductivity type is provided between the semiconductor laminated body and the third semiconductor region. A fifth semiconductor region of the first conductivity type is in contact with an outside surface of the semiconductor laminated body opposite to an inside surface of the semiconductor laminated body, the inside surface is in contact with the fourth semiconductor region. 1. A semiconductor device , comprising:a semiconductor laminated body including a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type provided on the first semiconductor region and having a higher concentration of impurities than that of the first semiconductor region, the semiconductor laminated body including an inside surface and an outside surface opposed to the inside surface, the first semiconductor region including an upper surface and a lower surface;a third semiconductor region including a side surface and a lower end, the side surface and the lower end being surrounded by the semiconductor laminated body;a fourth semiconductor region of a second conductivity type provided between the semiconductor laminated body and the third semiconductor region, the fourth semiconductor region being in contact with the inside surface of the semiconductor laminated body, and including an upper end and a lower end;a fifth semiconductor region of the first conductivity type being in contact ...

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06-02-2014 дата публикации

Transistor having replacement metal gate and process for fabricating the same

Номер: US20140035068A1
Принадлежит: International Business Machines Corp

A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the mask layer and on a top surface of the doped region. A layer adapted to reduce a threshold voltage of the transistor and/or reduce a thickness of an inversion layer of the transistor is deposited on the interfacial layer. The layer includes metal, such as aluminum or lanthanum, which diffuses into the interfacial layer, and also includes oxide, such as hafnium oxide. A conductive plug, such as a metal plug, is formed within the hole of the mask layer. The interfacial layer, the layer on the interfacial layer, and the conductive plug are a replacement gate of the transistor.

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27-02-2014 дата публикации

Memory Cells, Memory Arrays, Methods Of Forming Memory Cells, And Methods Of Forming A Shared Doped Semiconductor Region Of A Vertically Oriented Thyristor And A Vertically Oriented Access Transistor

Номер: US20140057398A1
Автор: Tang Sanh D.
Принадлежит: MICRON TECHNOLOGY, INC.

A memory cell includes a thyristor having a plurality of alternately doped, vertically superposed semiconductor regions; a vertically oriented access transistor having an access gate; and a control gate operatively laterally adjacent one of the alternately doped, vertically superposed semiconductor regions. The control gate is spaced laterally of the access gate. Other embodiments are disclosed, including methods of forming memory cells and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor. 139-. (canceled)40. A method of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor , the method comprising:forming a general U-shape of semiconductor material in lateral cross section, the general U-shape having a pair of vertical stems having a base extending laterally there-between in the lateral cross section; anddoping the base between the stems with a conductivity modifying impurity of at least one of n type and p type and forming the shared doped semiconductor region there-from.41. The method of wherein laterally inner facing sidewalls of the stems are masked from such doping during the doping.42. The method of wherein forming the shared doped semiconductor region there-from comprises annealing to diffuse the conductivity modifying impurity laterally outward into the stems.43. The method of wherein the diffusing is to laterally outermost surfaces of the stems.44. A method of forming a memory cell comprising a vertically oriented thyristor and a control gate operatively laterally adjacent thereto claim 42 , the memory cell comprising a vertically oriented access transistor which shares a doped semiconductor region with the thyristor claim 42 , the method comprising:forming a block of semiconductor material relative to a substrate;etching into the block to form a general U-shape of the semiconductor material in lateral ...

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06-03-2014 дата публикации

Semiconductor fin on local oxide

Номер: US20140061862A1
Принадлежит: International Business Machines Corp

A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins. The first semiconductor material can be selected from materials more easily oxidized relative to the second semiconductor material to provide a uniform height for the semiconductor fins after formation of the localized oxide layer.

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27-03-2014 дата публикации

Contact Structure Of Semiconductor Device

Номер: US20140084340A1

The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and a metal layer filling a coated opening of the dielectric layer.

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27-03-2014 дата публикации

TIN PRECURSORS FOR VAPOR DEPOSITION AND DEPOSITION PROCESSES

Номер: US20140087544A1
Автор: Tolle John
Принадлежит: ASM AMERICA, INC.

Sn-containing precursors for deposition of Sn-containing films and methods of using are provided herein. In some embodiments, Sn-containing precursors are methylated and/or hydrogenated and/or deuteriated. In some embodiments, methods of chemical vapor deposition are provided. 1. A CVD method for forming an epitaxial film comprising Sn on a substrate within a reaction chamber , the method comprising:providing a substrate disposed within a reaction chamber; and [{'br': None, 'sub': 3', '4-n', 'n, 'Sn(CH)X, in which X═H, D, Cl or Br, and n=0, 1, 2, or 3; \u2003\u2003Formula (I)'}, {'br': None, 'sub': 3', '3-n', 'n, 'ZSn(CH)X, in which Z═H or D, X═Cl or Br, and n═0, 1, or 2; \u2003\u2003Formula (II)'}, {'br': None, 'sub': 2', '3', '2-n', 'n, 'ZSn(CH)X, in which Z═H or D, X═Cl or Br, and n=0, or 1; or \u2003\u2003Formula (III)'}, {'br': None, 'sub': '4', 'SnBr; and \u2003\u2003(IV)'}], 'contacting an epitaxial surface of the substrate with a Sn precursor comprisinga second precursor comprising at least one of Si or Ge, thereby forming an epitaxial film comprising Sn.2. The method of claim 1 , wherein the epitaxial surface of the substrate comprises Si.3. The method of claim 1 , wherein the film comprising Sn comprises about 20% Sn or less.4. The method of claim 1 , wherein the film comprising Sn comprises about 5% Sn or less.5. The method of claim 1 , wherein the second precursor comprises a Group III claim 1 , Group IV claim 1 , or Group V element.6. The method of claim 1 , wherein the second precursor comprises a Group IV element.7. The method of claim 1 , wherein the second precursor comprises Ge.8. The method of claim 1 , further comprising contacting the epitaxial surface of the substrate with a dopant precursor.9. The method of claim 8 , wherein the dopant precursor comprises at least one of B claim 8 , Ga claim 8 , In claim 8 , As claim 8 , P claim 8 , or Sb.10. The method of claim 2 , wherein the film comprising Sn comprises a buffer layer for integration of ...

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01-01-2015 дата публикации

METHOD OF STRIPPING ORGANIC MASK WITH REDUCED DAMAGE TO LOW-K FILM

Номер: US20150004797A1
Принадлежит:

A method for stripping an organic mask above a porous low-k dielectric film is provided. A steady state flow of a stripping gas, comprising COand CHis provided. The stripping gas is formed into a plasma, wherein the plasma strips at least half the organic mask and protects the porous low-k dielectric film, for a duration of providing the steady state flow of the stripping gas. 1. A method for stripping an amorphous carbon mask above a porous low-k dielectric film , comprising:{'sub': 2', '4, 'providing a steady state flow of a stripping gas, comprising COand CH; and'}forming the stripping gas into a plasma, wherein the plasma strips at least half the amorphous carbon mask and protects the porous low-k dielectric film, for a duration of providing the steady state flow of the stripping gas.2. The method claim 1 , as recited in claim 1 , wherein the stripping gas is fluorine free.3. A method for processing an amorphous carbon mask above a hardmask layer above a porous low-k dielectric film claim 1 , comprising:etching features into the hardmask layer through the amorphous carbon mask; providing a steady state flow of a stripping gas, comprising a stripping component and a hydrocarbon or fluorocarbon; and', 'forming the stripping gas into a plasma, wherein the plasma strips the amorphous carbon mask and protects the low-k dielectric film;, 'stripping the amorphous carbon mask after etching features into the hardmask layer, comprisingetching features into the porous low-k dielectric film through the hardmask layer after stripping the amorphous carbon mask.4. The method claim 3 , as recited in claim 3 , wherein more than half of the amorphous carbon mask is stripped during a duration of the steady state flow of the stripping gas.5. The method claim 4 , as recited in claim 4 , wherein the stripping component comprises an oxidizing component or reducing component.6. The method claim 5 , as recited in claim 5 , wherein the hydrocarbon or fluorocarbon is a hydrocarbon claim 5 ...

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13-01-2022 дата публикации

METHOD FOR PRODUCING PLASTIC ELEMENT PROVIDED WITH FINE SURFACE ROUGHNESS

Номер: US20220013369A1
Принадлежит: NALUX CO., LTD.

A method for producing a plastic element provided with fine surface roughness is provided. In the method, etching of a surface of the plastic element is performed separately in a first step and in a second step, in the first step, fine roughness having a predetermined average value of pitch in the range from 0.05 to 1 micrometer is generated on the surface through reactive ion etching in an atmosphere of a first gas; and in the second step, an average value of depth of the fine roughness generated in the first step is adjusted to a predetermined value in the range from 0.15 to 1.5 micrometers while the predetermined average value of pitch is substantially maintained through reactive ion etching in an atmosphere of a second gas, reactivity to the plastic element of the second gas being lower than reactivity to the plastic element of the first gas. 1. A method for producing a plastic element provided with fine surface roughness , comprising:etching of a surface of the plastic element separately in a first step that is an early stage and in a second step that is a stage following the early stage, whereinin the first step, fine roughness having a predetermined average value of pitch in the range from 0.05 micrometers to 1 micrometer is generated on a surface of the plastic element through reactive ion etching in an atmosphere of a first gas; and whereinin the second step, an average value of depth of the fine roughness generated in the first step is adjusted to a predetermined value in the range from 0.15 micrometers to 1.5 micrometers while the predetermined average value of pitch of the fine roughness is substantially maintained through reactive ion etching in an atmosphere of a second gas, reactivity to the plastic element of the second gas being lower than reactivity to the plastic element of the first gas.2. The method for producing a plastic element provided with fine surface roughness according to claim 1 , wherein the first gas is sulfur hexafluoride (SF) claim ...

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13-01-2022 дата публикации

SUBSTRATE CARRIER LATCHING STRUCTURE

Номер: US20220013391A1
Принадлежит:

The invention discloses a substrate carrier latching structure, which mainly comprises a top portion, a cover and a detachable module. The top portion is disposed on the enclosure of a substrate carrier, and the cover is connected to the top portion via a detachable module. As such, the excessive stress on the substrate carrier is avoided to maintain the integrity of substrates stored in the inner portion of the substrate carrier. 1. A substrate carrier latching structure , comprising:a top portion, disposed on an enclosure;a cover, connected to the top portion via a detachable module, wherein the detachable module comprising:at least one first fastener, configured on the top portion or the cover, wherein a shield is disposed in a horizontal extension part of the at least one first fastener;at least one second fastener, configured on the top portion or the cover corresponding to the at least one first fastener, wherein the at least one second fastener is matched with the at least one first fastener;a positioning post, configured on the top portion or the cover; andan alignment member, configured on the top portion or the cover corresponding to the positioning post, wherein the alignment member matches with the positioning post.2. The substrate carrier latching structure as claimed in claim 1 , wherein at least one first latch portion and at least one second latch portion are installed on the top portion and the cover respectively claim 1 , and the at least one first latch portion and the at least one second latch portion are connected with the top portion and the cover respectively.3. The substrate carrier latching structure as claimed in claim 2 , wherein the at least one second latch portion matches with the at least one first latch portion.4. The substrate carrier latching structure as claimed in claim 1 , wherein the at least one first fastener is arranged in a ring-shape.5. The substrate carrier latching structure as claimed in claim 1 , wherein the at least ...

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04-01-2018 дата публикации

Method of Reducing an Impurity Concentration in a Semiconductor Body

Номер: US20180005831A1
Принадлежит:

A method includes kicking out impurity atoms from substitutional sites of a crystal lattice of a semiconductor body by implanting particles via a first surface into the semiconductor body, reducing a thickness of the semiconductor body by removing semiconductor material of the semiconductor body, and annealing the semiconductor body in a first annealing process at a temperature of between 300° C. and 450° C. to diffuse impurity atoms out of the semiconductor body. 1. A method , comprising:kicking out impurity atoms from substitutional sites of a crystal lattice of a semiconductor body by implanting particles via a first surface into the semiconductor body;reducing a thickness of the semiconductor body by removing semiconductor material of the semiconductor body; andannealing the semiconductor body in a first annealing process at a temperature of between 300° C. and 450° C. to diffuse impurity atoms out of the semiconductor body.2. The method of claim 1 , wherein a duration of the first annealing process is between 30 minutes and 80 hours.3. The method of claim 1 , wherein the temperature in the first annealing process is between 350° C. and 400° C. claim 1 , and wherein a duration of the first annealing process is between 30 minutes and 10 hours.4. The method of claim 3 , wherein the duration of the first annealing process is between 2 hours and 4 hours.5. The method of claim 2 , wherein the temperature in the first annealing process is between 300° C. and 350° C. claim 2 , and wherein the duration of the first annealing process is between 2 hours and 80 hours.6. The method of claim 1 , wherein reducing the thickness of the semiconductor body comprises removing semiconductor material of the semiconductor body at a second surface opposite the first surface.7. The method of claim 6 , wherein implanting the particles into the semiconductor body comprises implanting the particles into an end-of-range region spaced apart from the first surface claim 6 , and wherein ...

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04-01-2018 дата публикации

Through-silicon via with injection molded fill

Номер: US20180005887A1
Принадлежит: International Business Machines Corp

Embodiments are directed to a method of forming a conductive via. The method includes forming an opening in a substrate and forming a conductive material along sidewall regions of the opening, wherein the conductive material occupies a first portion of an area within the opening. The method further includes forming a conductive fill in a second portion of the area within the opening, wherein at least one surface of the conductive material and at least one surface of the conductive fill are substantially coplanar with a front surface of the substrate.

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07-01-2021 дата публикации

SiC FREESTANDING FILM STRUCTURE

Номер: US20210005469A1
Автор: Satoshi Kawamoto
Принадлежит: Admap Inc

A SiC Freestanding Film Structure capable of preventing a functional surface of a SiC Freestanding Film Structure from being affected by a film thickness and improving strength by increasing the film thickness, the SiC Freestanding Film Structure is formed by depositing a SiC layer through a vapor deposition type film formation method. The SiC layer is deposited with respect to a first SiC layer serving as a functional surface in the SiC Freestanding Film Structure. Focusing on the functional surface and a non-functional surface positioned on front and back sides of any particular portion, the functional surface has smoothness higher than that of the non-functional surface.

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07-01-2021 дата публикации

SiC FILM STRUCTURE

Номер: US20210005491A1
Автор: Satoshi Kawamoto
Принадлежит: Admap Inc

A SiC film structure for obtaining a three-dimensional SiC film by forming the SiC film in an outer circumference of a substrate using a vapor deposition type film formation method and removing the substrate, the SiC film structure including: a main body having a three-dimensional shape formed of a SiC film and having an opening for removing the substrate; a lid configured to cover the opening; and a SiC coat layer configured to cover at least a contact portion between the main body and an outer edge portion of the lid and join the main body and the lid.

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02-01-2020 дата публикации

GERMANIUM NANOSHEETS AND METHODS OF FORMING THE SAME

Номер: US20200006067A1
Автор: Cheng Hung-Hsiang
Принадлежит:

Devices comprising germanium nanosheets are described herein. Methods of forming such germanium nanosheets and devices including such germanium nanosheets are also described. 1. A method , comprising:receiving a wafer comprising a stack of alternating semiconductor layers on a substrate, the stack of alternating semiconductor layers comprising alternating layers of a group IV semiconductor and layers of germanium;shaping the stack of alternating semiconductor layers to have a first pad, a second pad, and a narrow portion between the first and second pads;forming a plurality of germanium nanosheets by removing the narrow portion of the layers of the group IV semiconductor; anddepositing a dielectric material that surrounds at least a portion of each of the plurality of germanium nanosheets.2. The method of claim 1 , further comprising forming a layer of insulator on the stack of alternating semiconductor layers before shaping the stack of alternating semiconductor layers.3. The method of claim 2 , wherein the layer of insulator is silicon dioxide (SiO).4. The method of claim 3 , wherein shaping the stack of alternating semiconductor layers comprises:forming a pattern on the layer of insulator; andremoving portions of the stack of alternating semiconductor layers around the pattern by reactive-ion etching.5. The method of claim 4 , further comprising removing any remaining portions of the layer of insulator after shaping the stack of alternating semiconductor layers.6. The method of claim 1 , wherein removing the narrow portion of the layers of the group IV semiconductor comprises selective wet etching.7. The method of claim 1 , wherein the group IV semiconductor is silicon-germanium-tin (SiGeSn) or silicon-tin (SiSn).8. A method claim 1 , comprising: a first layer of a group IV semiconductor on a substrate;', 'a second layer of germanium on the first layer;', 'a third layer of the group IV semiconductor on the second layer; and', 'a fourth layer of germanium on the ...

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02-01-2020 дата публикации

Semiconductor die carrier structure

Номер: US20200006105A1

An apparatus having a first portion including first front wall, first rear wall, and bottom wall integrally coupled to the first front wall and the first rear wall, and pivotal pin structures integrally coupled to and extending from the first rear wall. The apparatus includes a second portion having second front wall, second rear wall, and top wall integrally coupled to the second front wall and the second rear wall, and pin holders integrally coupled to and extending from the second rear wall and at an offset angle with reference to the top wall. The pivotal pin structure includes a base support connected to the first rear wall and a shaft connected to the base support, and the pin holder defines an opening sized and shaped to accept the shaft. The first and second portions are sized and shaped to be pivotally movable between an open and closed configurations.

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02-01-2020 дата публикации

NANOSHEET SUBSTRATE ISOLATION SCHEME BY LATTICE MATCHED WIDE BANDGAP SEMICONDUCTOR

Номер: US20200006569A1
Принадлежит:

A thin layer of lattice matched wide bandgap semiconductor material having semi-insulating properties is employed as an isolation layer between the substrate and a vertical stack of suspended semiconductor channel material nanosheets. The presence of such an isolation layer eliminates the parasitic leakage path between the source region and the drain region that typically occurs through the substrate, while not interfering with the CMOS device that is formed around the semiconductor channel material nanosheets. 1. A method of forming a semiconductor structure , the method comprising:forming a nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet on an isolation layer that is disposed on a substrate, wherein a sacrificial gate structure and a dielectric spacer material layer straddle over the nanosheet stack, and wherein the substrate is composed of a first semiconductor material having a first bandgap, and the isolation layer is composed of a second semiconductor material having a second bandgap that is larger than the first bandgap, and further wherein the second semiconductor material is lattice matched to the first semiconductor material and is doped such that the second semiconductor material has semi-insulating properties;recessing end portions of each of the sacrificial semiconductor material nanosheets to provide a gap between each of the semiconductor channel material nanosheets;forming an inner spacer in each gap;forming a source/drain (S/D) region by epitaxial growth of a semiconductor material on physically exposed sidewalls of each semiconductor channel material nanosheet;removing the sacrificial gate structure and each recessed sacrificial semiconductor material nanosheet; andforming a functional gate structure around exposed surfaces of each semiconductor channel material nanosheet.2. The method of claim 1 , wherein the first semiconductor material is composed of Si ...

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27-01-2022 дата публикации

METHOD OF PRODUCING A TWO-DIMENSIONAL MATERIAL

Номер: US20220028683A1
Принадлежит: Paragraf Ltd.

A method of producing graphene or other two-dimensional material such as graphene including heating the substrate held within a reaction chamber to a temperature that is within a decomposition range of a precursor, and that allows two-dimensional crystalline material formation from a species released from the decomposed precursor; establishing a steep temperature gradient (preferably >1000° C. per meter) that extends away from the substrate surface towards an inlet for the precursor; and introducing precursor through the relatively cool inlet and across the temperature gradient towards the substrate surface. The steep temperature gradient ensures that the precursor remains substantially cool until it is proximate the substrate surface thus minimizing decomposition or other reaction of the precursor before it is proximate the substrate surface. The separation between the precursor inlet and the substrate is less than 100 mm. 1. A method of producing a two-dimensional crystalline material , the method comprising:providing a substrate having nucleation sites within a reaction chamber;introducing at a precursor entry point a precursor into the reaction chamber, the precursor being in a gas phase and/or suspended in a gas;heating the substrate to a temperature that is within a decomposition range of the precursor, and that allows two-dimensional crystalline material formation from a species released from the decomposed precursor; andcooling the precursor entry point;wherein the reaction chamber is a close coupled reaction chamber such that a separation between the substrate surface upon which the two-dimensional crystalline material is formed and the point at which the precursor enters the reaction chamber is sufficiently small, and a thermal gradient between the substrate surface and the point at which the precursor enters the chamber is sufficiently steep, such that the fraction of precursor that reacts in the gas phase within the reaction chamber is low enough to ...

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27-01-2022 дата публикации

PROCESS FOR PREPARING EPITAXY WAFER AND EPITAXY WAFER THEREFROM

Номер: US20220028732A1
Принадлежит: Zing Semiconductor Corporation

The present application provides a process for preparing an epitaxy wafer, and an epitaxy wafer prepared therefrom. The process comprises: step S: providing a semiconductor substrate wafer, conducting an epitaxy process and forming an epitaxy layer on the wafer; and step S: conducting a thermal treatment to the wafer to eliminate the haze pattern of the epitaxy layer. According to the process, the thermal treatment after the epitaxy process can facilitate the orientation of atoms on the wafer surface toward the lowest energy orientation, so that the atoms of the epitaxy layer arrange and accumulate uniformly. Therefore, the haze pattern on the wafer surface can be eliminated. 1. A process for preparing an epitaxy wafer comprising:{'b': '1', 'step S: providing a semiconductor substrate wafer, conducting an epitaxy process and forming an epitaxy layer on the wafer; and'}{'b': '2', 'step S: conducting a thermal treatment to the wafer to eliminate the haze pattern of the epitaxy layer.'}22. The process of claim 1 , wherein the thermal treatment in the step S is a rapid thermal treatment to rapidly increases the wafer temperature to the desired temperature of the thermal treatment to anneal.3. The process of claim 2 , wherein the desired temperature of the thermal treatment is 1000° C. to 1200° C.4. The process of claim 2 , wherein the thermal treatment is conducted for 1 minute (min) to 10 min.51. The process of claim 1 , wherein claim 1 , in the step S claim 1 , the substrate wafer is provided via blowing wand for the epitaxy process.6122. The process of further comprising claim 1 , conducting a metrology test to the substrate wafer for determination of morphology on the wafer surface after the step S claim 1 , before the step S claim 1 , and/or after the step S.72. The process of claim 1 , wherein claim 1 , in the step S claim 1 , the substrate wafer is grabbed by mechanical means.82. The process of claim 1 , wherein claim 1 , in the step S claim 1 , the thermal ...

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10-01-2019 дата публикации

BIDIRECTIONAL GATE VALVE

Номер: US20190011061A1
Принадлежит: PRESYS.CO., LTD

The present invention is characterized by including: a blade () installed in a valve housing () having first and second passage holes () to open/close the first and second passage holes (); a shaft () coupled to a lower portion of the blade (); a first driving block () including: a first cylinder () which is provided under the valve housing () and into which the shaft () is inserted; a first piston () installed inside the first cylinder () and coupled to a lower portion of the shaft () to vertically move the shaft () according to pressure change inside the first cylinder (); and horizontal movement guide rollers () respectively provided on both outer sides thereof to guide the horizontal movement of the blade a second driving block which is coupled to a lower portion of the first guiding block so as to be vertically movable and which guides the horizontal movement of the blade according to the vertical movement thereof such that the horizontal movement guide rollers () are respectively inserted into both inner side surfaces the second driving block a third driving block () provided under the second driving block and having therein: first and second mounting parts () provided as respective independent spaces; a second piston () provided to the first mounting part and coupled to the second driving block to vertically move the second driving block according to pressure change inside the first mounting part (); and a movement restricting member () which is installed to the second mounting part () so as to be vertically movable and restricts a downward movement of the second piston (); and a main body bracket () provided under the valve housing () to accommodate the first, second, and third driving blocks (). 11. A bidirectional gate valve () comprising:{'b': 200', '100', '110', '120', '110', '120, 'a blade () installed inside a valve housing () having first and second passage holes (, ), which respectively have an open front surface and an open rear surface, and ...

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12-01-2017 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM

Номер: US20170011908A1
Принадлежит: HITACHI KOKUSAI ELECTRIC INC.

A method of manufacturing a semiconductor device includes forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing: supplying a precursor containing a predetermined element to the substrate in a process chamber, removing the precursor from the process chamber, supplying a first reactant containing nitrogen, carbon and hydrogen to the substrate, removing the first reactant from the process chamber, supplying a second reactant containing oxygen to the substrate, and removing the second reactant from the process chamber. A time period of the act of removing the precursor is set to be longer than a time period of the act of removing the first reactant, or a time period of the act of removing the second reactant is set to be longer than the time period of the act of removing the first reactant. 1. A method of manufacturing a semiconductor device , comprising forming a film on a substrate by performing a cycle a predetermined number of times , the cycle including non-simultaneously performing:supplying a precursor containing a predetermined element to the substrate in a process chamber;removing the precursor from the process chamber;supplying a first reactant containing nitrogen, carbon and hydrogen to the substrate in the process chamber;removing the first reactant from the process chamber;supplying a second reactant containing oxygen to the substrate in the process chamber; andremoving the second reactant from the process chamber,wherein a time period of the act of removing the precursor is set to be longer than a time period of the act of removing the first reactant, or a time period of the act of removing the second reactant is set to be longer than the time period of the act of removing the first reactant.2. The method of claim 1 , wherein the time period of the act of removing the precursor is set to be longer than the time period of the act of removing the first reactant claim 1 , and the ...

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12-01-2017 дата публикации

SILICON-ON-INSULATOR DEVICE AND INTERMETALLIC DIELECTRIC LAYER STRUCTURE THEREOF AND MANUFACTURING METHOD

Номер: US20170011957A1
Принадлежит:

Provided is an intermetallic dielectric layer structure of a silicon-on-insulator device, comprising a silicon-rich oxide layer () covering a metal interconnect, a fluorine-silicon glass layer on the silicon-rich oxide layer, and a non-doped silicate glass layer on the fluorine-silicon glass layer; the thickness of the silicon-rich oxide layer () is 700 angstroms ±10%; the silicon-rich oxide layer having a greater thickness captures movable ions on an unsaturated bond, such that it is difficult for the movable ions to pass through the silicon-rich oxide layer, thus blocking the movable ions. The present invention has good performance in an integrity evaluation of the gate oxide layer, and avoids damage to the device caused by the aggregation of movable ions at an interface. Also provided are a silicon-on-insulator device and a method of manufacturing the intermetallic dielectric layer of the silicon-on-insulator device. 1. An intermetallic dielectric layer structure of a silicon-on-insulator device , comprising: a Si-rich oxide layer covering a metal interconnection , a fluorine-silicon glass layer formed on the Si-rich oxide layer , and an undoped silicate glass layer formed on the fluorine-silicon glass layer; wherein a thickness of the Si-rich oxide layer is 700 angstroms ±10%.2. The intermetallic dielectric layer structure of the silicon-on-insulator device of claim 1 , characterized in that claim 1 , the Si-rich oxide layer is an in-situ Si-rich oxide layer.3. The intermetallic dielectric layer structure of the silicon-on-insulator device of claim 1 , characterized in that claim 1 , a thickness of the undoped silicate glass layer is 2000 angstroms ±10%.4. The intermetallic dielectric layer structure of the silicon-on-insulator device of claim 1 , further comprising a silicon nitride layer provided between the metal interconnection and the fluorine-silicon glass layer.5. A silicon-on-insulator device claim 1 , comprising a substrate claim 1 , a buried oxide ...

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15-01-2015 дата публикации

METHODS FOR COATING SEMICONDUCTOR NANOCRYSTALS

Номер: US20150014629A1
Автор: Breen Craig, Liu Wenhao
Принадлежит:

A coated quantum dot and methods of making coated quantum dots are provided. 1. A method of making quantum dots having a coating thereon comprisingproviding a reaction mixture including core quantum dots, one or more metal carboxylates and one or more chalcogenide sources at a temperature of greater than 240° C. to form ; a first coating on the core quantum dots from the metal carboxylate and chalcogenide source to form first coated quantum dots, wherein the metal and chalcogenide of the first coating are the same or different from elements included in the core;combining one or more metal precursors and one or more chalcogen precursors with the first coated quantum dots to form a second coating on the first coated quantum dots from the one or more metals and one or more chalcogens included in the precursors, wherein the one or more metals and one or more chalcogens included in the second coating comprises a composition that is different from the composition of at least one of the core or the first coating.2. The method of wherein the one or more metal precursors for the second coating comprise one or more metal carboxylates and the precursors for the second coating are reacted at a second temperature >280° C.3. The method of wherein the core quantum dots include group II-VI elements.4. The method of wherein the first coating includes group II-VI elements.5. The method of wherein the second coating includes group II-VI elements.6. The method of wherein the second coating is CdZnS.7. The method of wherein the core quantum dots are CdSe quantum dots.8. The method of wherein unbound phosphonic acid or unbound metal phosphonate species are substantially removed from the core quantum dots prior to the core quantum dots receiving a first coating.9. The method of wherein any unbound phosphonic acid or unbound metal phosphonate species are substantially removed from the core quantum dots by placing the quantum dots in a fluid causing precipitation of the phosphonic acid or ...

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10-01-2019 дата публикации

High-Density Volatile Random Access Memory Cell Array and Methods of Fabrication

Номер: US20190013317A1
Принадлежит:

Thyristor memory cell arrays and their fabrication have improved features. Assist-gates between thyristor memory cells in an array operate on both sides of an assist-gate. The assist-gates can be arranged in various ways for optimized performance and the materials of the assist-gate are selected to control the bias voltage of the assist-gate in operation. The PNPN (or NPNP) thyristor layers of the memory cell can be fabricated in different process flows according to manufacturing concerns and the dopant concentrations of the layers are selected to reduce temperature sensitivity of the memory cell. 1. An integrated circuit array of thyristor memory cells comprising:a set of cathode lines;a set of anode lines;a plurality of thyristor memory cells arranged in an array, each thyristor memory cell having a cathode region connected to a cathode line and an anode region connected to an anode line and at least one base region between the cathode region and anode region; anda set of assist-gate electrodes, each assist-gate electrode located between pairs of thyristor memory cells, a portion of the assist-gate electrode adjacent to, but displaced from, the at least one base region of each of the thyristor memory cell pair to form an electrical coupling with the each of the thyristor memory cell pair.2. The integrated circuit array of further comprising a semiconductor substrate wherein the plurality of thyristor memory cells are arranged over the substrate and each of the thyristor memory cells comprises a layered structure of alternating electrical conductivities claim 1 , the layered structure arranged perpendicular to the substrate.3. The integrated circuit array of wherein the set of assist-gate electrodes are between the set of cathode lies and the set of anode lines located4. The integrated circuit array of wherein the set of assist-gate electrodes comprises a conductive material selected to control a bias voltage for a thyristor memory cell claim 1 , the bias voltage ...

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10-01-2019 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20190013391A1
Принадлежит:

Disclosed is a semiconductor device including a bottom electrode, a dielectric layer, and a top electrode that are sequentially disposed on a substrate. The dielectric layer includes a hafnium oxide layer including hafnium oxide having a tetragonal crystal structure, and an oxidation seed layer including an oxidation seed material. The oxidation seed material has a lattice constant having a lattice mismatch of 6% or less with one of a horizontal lattice constant and a vertical lattice constant of the hafnium oxide having the tetragonal crystal structure. 1. A semiconductor device , comprising:a bottom electrode disposed on a substrate;a top electrode disposed on the bottom electrode; and a hafnium oxide layer including hafnium oxide having a tetragonal crystal structure having a vertical lattice constant and a horizontal lattice constant; and', 'an oxidation seed layer including an oxidation seed material,, 'a dielectric layer includingwherein the oxidation seed material has a lattice constant having a lattice mismatch of 6% or less with one of the horizontal lattice constant and the vertical lattice constant of the hafnium oxide.2. The semiconductor device of claim 1 ,wherein the oxidation seed material has a band gap energy of 3.0 eV or more.3. The semiconductor device of claim 1 ,wherein the oxidation seed material comprises zirconium oxide, niobium oxide, germanium oxide, tin oxide, molybdenum oxide, or titanium oxide.4. The semiconductor device of claim 1 ,wherein the oxidation seed layer further comprises nitrogen.5. The semiconductor device of claim 1 ,wherein the oxidation seed layer and the hafnium oxide layer are in contact with each other.6. The semiconductor device of claim 1 ,wherein the oxidation seed layer is disposed between the hafnium oxide layer and the top electrode.7. The semiconductor device of claim 6 , further comprising:a conductive seed layer between the bottom electrode and the hafnium oxide layer,wherein the conductive seed layer ...

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10-01-2019 дата публикации

HIGH POWER COMPOUND SEMICONDUCTOR FIELD EFFECT TRANSISTOR DEVICES WITH LOW DOPED DRAIN

Номер: US20190013398A1
Принадлежит:

A compound semiconductor field effect transistor may include a channel layer. The compound semiconductor transistor may also include a multi-layer epitaxial barrier layer on the channel layer. The channel layer may be on a doped buffer layer or on a first un-doped buffer layer. The compound semiconductor field effect transistor may further include a gate. The gate may be on a first tier of the multi-layer epitaxial barrier layer, and through a space between portions of a second tier of the multi-layer epitaxial barrier layer. 1. A compound semiconductor field effect transistor , comprising:a multi-layer epitaxial barrier layer on a channel layer, the channel layer on a doped buffer layer or on a first un-doped buffer layer; anda gate on a first tier of the multi-layer epitaxial barrier layer, and through a space between portions of a second tier of the multi-layer epitaxial barrier layer.2. The compound semiconductor field effect transistor of claim 1 , further comprising a body contact electrically coupled to the doped buffer layer or the first un-doped buffer layer.3. The compound semiconductor field effect transistor of claim 1 , in which the doped buffer layer comprises a P-type doped buffer layer.4. The compound semiconductor field effect transistor of claim 1 , further comprising an etch stop layer on the doped buffer layer or on the first un-doped buffer layer.5. The compound semiconductor field effect transistor of claim 1 , in which a thickness of the multi-layer epitaxial barrier layer increases in steps as a distance from the gate increases.6. The compound semiconductor field effect transistor of claim 1 , in which a distance between the gate and a source region is less than a distance between the gate and a drain region.7. The compound semiconductor field effect transistor of claim 1 , in which the multi-layer epitaxial barrier layer comprises a third tier and an etch stop layer between each of the first tier claim 1 , the second tier claim 1 , and the ...

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14-01-2021 дата публикации

Wafer level sequencing flow cell fabrication

Номер: US20210013025A1
Принадлежит: MGI Tech Co Ltd

A method for forming sequencing flow cells can include providing a semiconductor wafer covered with a dielectric layer, and forming a patterned layer on the dielectric layer. The patterned layer has a differential surface that includes alternating first surface regions and second surface regions. The method can also include attaching a cover wafer to the semiconductor wafer to form a composite wafer structure including a plurality of flow cells. The composite wafer structure can then be singulated to form a plurality of dies. Each die forms a sequencing flow cell. The sequencing flow cell can include a flow channel between a portion of the patterned layer and a portion of the cover wafer, an inlet, and an outlet. Further, the method can include functionalizing the sequencing flow cell to create differential surfaces.

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14-01-2021 дата публикации

Semiconductor device including capacitor

Номер: US20210013319A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Disclosed is a semiconductor device including a bottom electrode, a dielectric layer, and a top electrode that are sequentially disposed on a substrate. The dielectric layer includes a hafnium oxide layer including hafnium oxide having a tetragonal crystal structure, and an oxidation seed layer including an oxidation seed material. The oxidation seed material has a lattice constant having a lattice mismatch of 6% or less with one of a horizontal lattice constant and a vertical lattice constant of the hafnium oxide having the tetragonal crystal structure.

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09-01-2020 дата публикации

Array Of Gated Devices And Methods Of Forming An Array Of Gated Devices

Номер: US20200013669A1
Принадлежит: MICRON TECHNOLOGY, INC.

An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed. 121-. (cancelled)22. An array of gated devices , comprising:a plurality of gated devices arranged in rows and columns and individually comprising an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region;a plurality of access lines that individually are laterally proximate the mid regions along individual of the rows;a plurality of data/sense lines that individually are elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns; anda plurality of metal lines that individually longitudinally extend along and between immediately adjacent of the rows elevationally inward of the access lines, the individual metal lines being directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows, the metal lines being electrically isolated from the data/sense lines ...

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18-01-2018 дата публикации

SIC EPITAXIAL WAFER AND METHOD FOR MANUFACTURING SIC EPITAXIAL WAFER

Номер: US20180016706A1
Принадлежит: SHOWA DENKO K.K.

An SiC epitaxial wafer having an SiC epitaxial layer formed on an SiC single crystal substrate having an offset angle of 4 degrees or less in a <11-20> direction from a (0001) plane. A trapezoidal defect included in the SiC epitaxial wafer includes an inverted trapezoidal defect in which a length of a lower base on a downstream side of a step flow is equal to or less than a length of an upper base on an upstream side of the step flow. Also disclosed is a method for manufacturing the SiC epitaxial wafer. 1. An SiC epitaxial wafer comprising an SiC epitaxial layer formed on an SiC single crystal substrate having an offset angle of 4 degrees or less in a <11-20> direction from a (0001) plane ,wherein a trapezoidal defect included in the SiC epitaxial wafer comprises an inverted trapezoidal defect in which a length of a lower base on a downstream side of a step flow is equal to or less than a length of an upper base on an upstream side of the step flow.2. The SiC epitaxial wafer according to claim 1 , wherein a ratio of the inverted trapezoidal defect in the trapezoidal defect is 50% or more.3. The SiC epitaxial wafer according to claim 1 , wherein the inverted trapezoidal defect comprises an inverted trapezoidal defect having a length of the lower base on the downstream side of the step flow of 0 and a triangular shape.4. A method for manufacturing an SiC epitaxial wafer which is a method for manufacturing the SiC epitaxial wafer according to claim 1 , the method comprising:an etching step for etching an SiC single crystal substrate; andan epitaxial growth step for growing an epitaxial layer on the SiC single crystal substrate after etching,wherein in the epitaxial growth step, a concentration ratio C/Si of a Si-based source gas and a C-based source gas is set to 1.0 or less.5. The method for manufacturing an SiC epitaxial wafer according to claim 4 , wherein a temperature in the epitaxial growth step is set to 1 claim 4 ,630° C. or less.6. The method for manufacturing ...

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18-01-2018 дата публикации

REPRODUCIBLE AND MANUFACTURABLE NANOGAPS FOR EMBEDDED TRANSVERSE ELECTRODE PAIRS IN NANOCHANNELS

Номер: US20180017524A1
Принадлежит:

A method for forming a nanogap includes forming a knockoff feature on a dielectric layer and forming a trench in the dielectric layer on opposite sides of the knockoff feature. A noble metal is deposited in the trenches and over the knockoff feature. A top surface is polished to level the noble metal in the trenches with a top of the dielectric layer to form electrodes in the trenches and to remove the noble metal from the knockoff feature. A nanochannel is etched into the dielectric layer such that the knockoff feature is positioned within the nanochannel. The knockoff feature is removed to form a nanogap between the electrodes. 1. A method for forming a nanogap , comprising:forming a knockoff feature on a dielectric layer;forming a trench in the dielectric layer on opposite sides of the knockoff feature;depositing a noble metal in the trenches and over the knockoff feature;polishing a top surface to remove the noble metal in field regions and the knockoff feature, leaving the noble metal in the trenches level with a top of the dielectric layer to form electrodes embedded in the trenches;etching a nanochannel in the dielectric layer such that the knockoff feature is positioned within the nanochannel; andremoving the knockoff feature to form a nanogap between the electrodes.2. The method as recited in claim 1 , wherein forming the knockoff feature includes:depositing a negative electron beam (ebeam) resist;exposing a line in the resist with an ebeam at a position of the nanogap to provide the knockout feature; anddeveloping away the resist to leave the knockout feature.3. The method as recited in claim 1 , wherein forming the trench includes:depositing a resist layer;patterning the resist layer to open up electrode and nanoelectrode shapes adjacent to the nanogap; andetching the trenches in accordance with a resist pattern.4. The method as recited in claim 1 , wherein depositing the noble metal includes depositing the noble metal by electron beam evaporation.5. The ...

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17-01-2019 дата публикации

PASSIVATION AGAINST VAPOR DEPOSITION

Номер: US20190017170A1
Автор: Sharma Varun, Tois Eva
Принадлежит:

Passivation layers to inhibit vapor deposition can be used on reactor surfaces to minimize deposits while depositing on a substrate housed therein, or on particular substrate surfaces, such as metallic surfaces on semiconductor substrates to facilitate selective deposition on adjacent dielectric surfaces. Passivation agents that are smaller than typical self-assembled monolayer precursors can have hydrophobic or non-reactive ends and facilitate more dense passivation layers more quickly than self-assembled monolayers, particularly over complex three-dimensional structures. 1. A method for vapor-phase coating , the method comprising:passivating a conductive surface against vapor-phase deposition, wherein passivating comprises exposing the conductive surface to a vapor-phase passivating agent to form a passivated conductive surface; andselectively depositing a layer on a dielectric surface relative to the passivated conductive surface by exposing both the passivated conductive surface and the dielectric surface to vapor-phase deposition reactants.2. The method of claim 1 , wherein the passivating agent comprises a molecule smaller than a self-assembled monolayer (SAM) precursor having a carbon chain greater than five (5) carbon atoms.3. The method of claim 2 , wherein the passivating agent comprises halogen terminations.4. The method of claim 2 , wherein the passivated conductive surface comprises hydrophobic terminations or terminations that are inert to the selective deposition of the vapor phase deposition reactants.5. The method of claim 1 , wherein the passivating agent comprises a compound with one or more alkyl chains claim 1 , wherein the alkyl chains each have fewer than 5 carbon atoms.6. The method of claim 1 , wherein the passivating agent comprises a compound having a molecular mass of less than or equal to 330 g/mol.7. The method of claim 1 , wherein the passivating agent comprises a haloalkane of the formulae CHX claim 1 , CHX claim 1 , RRCX or RRCX ...

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19-01-2017 дата публикации

METAL REMOVAL WITH REDUCED SURFACE ROUGHNESS

Номер: US20170018439A1
Принадлежит: Applied Materials, Inc.

Methods are described for etching metal layers that are difficult to volatize, such as cobalt, nickel, and platinum to form an etched metal layer with reduced surface roughness. The methods include pretreating the metal layer with a local plasma formed from a hydrogen-containing precursor. The pretreated metal layer is then reacted with a halogen-containing precursor to form a halogenated metal layer having a halogenated etch product. A carbon-and-nitrogen-containing precursor reacts with the halogenated etch product to form a volatile etch product that can be removed in the gas phase from the etched surface of the metal layer. The surface roughness may be reduced by performing one or more plasma treatments on the etching metal layer after a plurality of etching sequences. Surface roughness is also reduced by controlling the temperature and length of time the metal layer is reacting with the etchant precursors. 1. A method of etching a metal layer on a semiconductor substrate , the method comprising:contacting the semiconductor substrate with a pre-treatment plasma, wherein the pre-treatment plasma is formed from a hydrogen-containing precursor; (i) reducing metal oxide formed on the metal layer to additional metal, and', '(ii) bombarding the metal layer to disorder crystalline regions on the metal layer;, 'treating the metal layer with the pre-treatment plasma to form a pre-treated metal layer, wherein the treating of the metal layer includesreacting the pre-treated metal layer with a halogen-containing precursor, wherein the halogen-containing precursor reacts with the pre-treated metal layer to form a halogenated metal layer comprising a halogenated etch product;removing the halogen-containing precursor from the semiconductor substrate;reacting the halogenated etch product on the halogenated metal layer with a carbon-and-nitrogen-containing precursor to form one or more volatile etch products; andremoving the carbon-and-nitrogen-containing precursor and the ...

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03-02-2022 дата публикации

LOW-K ALD GAP-FILL METHODS AND MATERIAL

Номер: US20220037146A1
Принадлежит:

Various embodiments include methods to produce low dielectric-constant (low-k) films. In one embodiment, alternating ALD cycles and dopant materials are used to generate a new family of silicon low-k materials. Specifically, these materials were developed to fill high-aspect-ratio structures with re-entrant features. However, such films are also useful in blanket applications where conformal nanolaminates are applicable. Various embodiments also disclose SiOF as well as SiOCF, SiONF, GeOCF, and GeOF. Analogous films may include halide derivatives with iodine and bromine (e.g., replace “F” with “I” or “Br”). Other methods, chemistries, and techniques are disclosed. 1. A method of forming low dielectric-constant (low-κ) films , the method comprising:depositing, by atomic-layer deposition (ALD) techniques, a film-deposition layer;doping the deposited film layer with fluorine;depositing, by atomic-layer deposition techniques, a subsequent film-deposition layer; andrepeating the deposition operations and the doping operations as needed to obtain a final film thickness of a film having a low dielectric constant.2. The method of claim 1 , where the formed low-κ films are silicon-based materials.3. The method of claim 2 , further comprising selecting a silane precursor.4. The method of claim 1 , wherein the low-κ films comprise at least one material selected from materials including fluorine-doped silicon oxide (SiOF) claim 1 , carbonofluoridoylsilicon (SiOCF) claim 1 , and fluorinated silicon oxynitride (SiONF).5. The method of claim 1 , further comprising selecting a density of the fluorine dopant is within a range of about 1×10atoms per cmto about 1×10atoms per cm.6. The method of claim 5 , wherein the stated range of the density of the fluorine dopant is within a silicon oxide (SiO) matrix.7. The method of claim 1 , further comprising selecting at least one variable from variables comprising a level of fluorine doping and a deposited film thickness per deposition layer. ...

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03-02-2022 дата публикации

PACKAGING UNIT FOR SUBSTRATES

Номер: US20220037179A1
Принадлежит:

The invention relates to a packaging unit for substrates, a packaging stack having packaging units of this type and a method for packaging substrates. The packaging unit for substrates comprises a first substrate, a spacer and a second substrate. The spacer is placed on the first substrate and the second substrate is placed on the spacer. A respective metal deposit is applied to a surface of the first substrate and to a surface of the second substrate and a respective adhesive point is arranged on the two metal deposits. The spacer is placed on the first substrate in such a way that the spacer is only in contact with the first substrate outside of the adhesive point. The spacer is bridge-shaped. At least the first substrate comprises a plurality of individual substrates arranged next to one another and the spacer borders the individual substrates. 1. A packaging unit for substrates , comprising:a first substrate,a spacer, anda second substrate,wherein the spacer is placed onto the first substrate and the second substrate is placed onto the spacer,wherein a first metal deposit is placed onto a surface of the first substrate and a second metal deposit is placed onto a surface of the second substrate in each case and one adhesive dot is arranged on each of the two metal deposits, andwherein the spacer is placed onto the first substrate in such a manner that the spacer is only in contact with the first substrate outside of the adhesive dot,wherein the spacer is web-like, andwherein at least the first substrate comprises a multiplicity of individual substrates arranged next to one another and the spacer edges the individual substrates.2. The packaging unit according to claim 1 , wherein the first substrate is a first metal-ceramic substrate and the second substrate is a second metal-ceramic substrate.3. The packaging unit according to claim 2 , wherein the first and the second metal-ceramic substrate comprise a ceramic layer and at least one metallization layer in each ...

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18-01-2018 дата публикации

Display driver semiconductor device and manufacturing method thereof

Номер: US20180019262A1
Принадлежит: MagnaChip Semiconductor Ltd

A display driver semiconductor device includes a high voltage well region being formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer. The first insulating layer may be formed using a chemical vapor deposition (CVD) process and the second insulating layer is formed using a thermal oxide process.

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18-01-2018 дата публикации

THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND DISPLAY DEVICE HAVING THE SAME, AND METHOD OF MANUFACTURING THEREOF

Номер: US20180019344A1
Автор: YAN Liangchen
Принадлежит: BOE Technology Group Co., Ltd.

The disclosure provides a method of manufacturing a thin film transistor on a base substrate by patterning an active layer comprising a metal oxynitride, and treating the active layer with a plasma comprising oxygen. 114-. (canceled)15. A thin film transistor comprising an active layer comprising a metal oxynitride , a source electrode , and a drain electrode;wherein the active layer is partially covered by an etching stop layer on top of the active layer;the active layer has a first region contacting the etching stop layer, a second region contacting the source electrode, and a third region contacting the drain electrode; andthe first region has an oxygen content lower than that of at least one of the second region and the third region.16. The thin film transistor of claim 15 , having one or more of the following characteristics:a ratio of oxygen content in at least one of the second region and the third region to oxygen content in the first region is approximately 1.005 to approximately 1.2;{'sup': 2', '2, 'a mobility rate ranging from approximately 50 cm/Vs to approximately 100 cm/Vs;'}{'sup': '−12', 'a turn-off current less than approximately 1×10A; and'}a turn-on voltage larger than approximately −10V.17. The thin film transistor of claim 15 , wherein the active layer comprises Zinc Oxynitride.18. The thin film transistor of claim 17 , wherein the active layer further comprises an element X in the Zinc Oxynitride claim 17 , the element X is selected from the group consisting of the following or combination thereof: boron claim 17 , aluminum claim 17 , gallium claim 17 , indium claim 17 , tin claim 17 , titanium claim 17 , zirconium claim 17 , hafnium claim 17 , silicon claim 17 , fluorine claim 17 , chlorine claim 17 , bromine claim 17 , iodine claim 17 , sulfur claim 17 , and selenium.19. An array substrate comprising the thin film transistor according to .20. A display apparatus claim 19 , comprising the array substrate of .21. The thin film transistor of ...

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22-01-2015 дата публикации

METHODS FOR COATING SEMICONDUCTOR NANOCRYSTALS

Номер: US20150021551A1
Автор: Breen Craig, Liu Wenhao
Принадлежит: QD VISION, INC.

A coated quantum dot and methods of making coated quantum dots are provided. Products including quantum dots described herein are also disclosed. 136-. (canceled)37. A method of making quantum dots having a coating thereon comprising:providing a first reaction mixture comprising core quantum dots, a zinc carboxylate and a chalcogen source at a temperature of greater than 240° C. in the substantial absence of an amine species;forming a first coating on the core quantum dots from the zinc carboxylate and chalcogen source to form first coated quantum dots;providing a second reaction mixture comprising one or more metal carboxylates and one or more chalcogenide sources with the first coated quantum dots at a temperature of greater than 240° C. in the substantial absence of an amine species; andforming a second coating on the first coated quantum dots from the one or metal carboxylates and the one or more chalcogenide sources.38. A method in accordance with wherein the temperature of the first reaction mixture is greater than 280° C.39. A method in accordance with wherein the temperature of the second reaction mixture is greater than 280° C.40. The method of wherein the core quantum dots comprise a Group II-VI semiconductor material.41. The method of wherein a first coating comprising one or more zinc chalcogenides is formed on the core quantum dots in the absence of amine species.42. The method of wherein the second coating comprises CdZnS wherein 0 Подробнее

17-01-2019 дата публикации

NON-HALOGEN ETCHING OF SILICON-CONTAINING MATERIALS

Номер: US20190019690A1
Принадлежит: Applied Materials, Inc.

Processing methods may be performed to limit damage of features of a substrate, such as missing fin damage. The methods may include forming a plasma of an inert precursor within a processing region of a processing chamber. Effluents of the plasma of the inert precursor may be utilized to passivate an exposed region of an oxygen-containing material that extends about a feature formed on a semiconductor substrate. A plasma of a hydrogen-containing precursor may also be formed within the processing region. Effluents of the plasma of the hydrogen-containing precursor may be directed, with DC bias, towards an exposed silicon-containing material on the semiconductor substrate. The methods may also include anisotropically etching the exposed silicon-containing material with the plasma effluents of the hydrogen-containing precursor, where the plasma effluents of the hydrogen-containing precursor selectively etch silicon relative to silicon oxide. 1. An etching method comprising:forming a plasma of an inert precursor within a processing region of a semiconductor processing chamber;passivating, with plasma effluents of the inert precursor, an exposed region of an oxygen-containing material, wherein the oxygen-containing material extends about a feature formed on a semiconductor substrate contained within the processing region to limit exposure of the feature to the plasma effluents;forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber;directing plasma effluents of the hydrogen-containing precursor towards an exposed silicon-containing material on the semiconductor substrate, wherein the plasma effluents of the hydrogen-containing precursor are directed with a DC bias; andanisotropically etching the exposed silicon-containing material with the plasma effluents of the hydrogen-containing precursor, wherein the plasma effluents selectively etch silicon relative to the oxygen-containing material.2. The etching ...

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17-01-2019 дата публикации

Passivation scheme for pad openings and trenches

Номер: US20190019770A1

An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

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21-01-2021 дата публикации

Semiconductor arrangement and method for manufacturing the same

Номер: US20210020521A1
Автор: Huilong Zhu
Принадлежит: Institute of Microelectronics of CAS

Provided are a semiconductor arrangement and a method for manufacturing the same. An example arrangement may comprise: a bulk semiconductor substrate; a fin formed on the substrate; a first FinFET and a second FinFET formed on the substrate, wherein the first FinFET comprises a first gate stack intersecting the fin and a first gate spacer disposed on sidewalls of the first gate stack, the second FinFET comprises a second gate stack intersecting the fin and a second gate spacer disposed on sidewalls of the second gate stack; a dummy gate spacer formed between the first FinFET and the second FinFET and intersecting the fin; a first isolation section self-aligned to a space defined by the dummy gate spacer, wherein the isolation section electrically isolates the first FinFET from the second FinFET; and a second isolation layer disposed under a bottom surface of the first isolation section.

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26-01-2017 дата публикации

SHALLOW TRENCH ISOLATION REGIONS MADE FROM CRYSTALLINE OXIDES

Номер: US20170025305A1
Принадлежит:

A method of manufacturing a semiconductor device that involves etching a trench in a semiconductor substrate, epitaxially growing a crystalline structure in the trench and forming semiconductor structures on either side of the crystalline structure. Crystalline oxides may include rare earth oxides, aluminum oxides or Perovskites. 1. A method of forming a semiconductor structure , the method comprising:etching a trench into a semiconductor substrate;forming a crystalline oxide layer in the trench, wherein the crystalline oxide fills an entire volume of the trench to form an epitaxial oxide structure, wherein said epitaxial oxide structure does not extend above a topmost planar surface of said semiconductor substrate; andforming a first semiconductor structure and a second semiconductor structure on the semiconductor substrate, wherein the epitaxial oxide structure is located between the first semiconductor structure and the second semiconductor structure, and wherein the epitaxial oxide structure substantially electrically isolates the first and the second semiconductor structure.2. The method of claim 1 , wherein the crystalline oxide comprises rare earth oxides.3. The method of claim 2 , wherein the rare earth oxide is selected from the group consisting of cerium oxide (CeO) claim 2 , lanthanum oxide (LaO) claim 2 , yttrium oxide (YO) claim 2 , gadolinium oxide (GdO) claim 2 , europium oxide (EuO) claim 2 , and terbium oxide (TbO).4. The method of claim 1 , wherein the crystalline oxide comprises a combination of rare earth oxides.5. The method of claim 4 , wherein the combination of rare earth oxides is a binary oxide having the chemical formula ABO claim 4 , wherein A is a rare earth metal atom and B is a different rare earth metal atom.6. The method of claim 1 , wherein the crystalline oxide comprises a perovskite material.7. The method of claim 6 , wherein the perovskite material is selected from the group consisting of strontium titanate (SrTiO) and barium ...

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24-04-2014 дата публикации

Graphene-based composite structure and method for making the same

Номер: US20140110662A1
Принадлежит: Individual

A graphene-based composite structure is disclosed. The graphene-based composite structure includes a graphene layer, a transition metal layer, and a substrate. The graphene layer, transition metal layer, and substrate are stacked together in series to form a sandwich structure. The graphene layer and the transition metal layer are coupled by d-p orbitals hybridization. The transition metal layer and the substrate are also coupled by d-p orbitals hybridization. A method for making graphene-based composite structure is also disclosed.

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