Method for Manufacturing a Si-Based High-Mobility CMOS Device With Stacked Channel Layers, and Resulting Devices

A device and method for manufacturing a Si-based high-mobility CMOS device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a III-V semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with III-V semiconductor material by etching via holes in the first oxide layer followed by selective area growth; (iii) manufacturing a second insulation layer above the III-V semiconductor channel layer and uncovering the trench; (iv) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by depositing a second dummy layer of a sacrificial material, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching via holes in the second oxide layer followed by selective area growth.

High-K heterostructure

A method for preparing a multilayer substrate includes the step of deposing an epitaxial -Al2O3 Miller index (001) layer on a Si Miller index (001) substrate.

Method for manufacturing an III-V engineered substrate and the III-V engineered substrate thereof

Manufacturing an III-V engineered substrate involves providing a base substrate comprising an upper layer made of a first III-V compound with a <110> or a <111> crystal orientation, forming an intermediate layer comprising at least a buffer layer of a second III-V compound, wherein the intermediate layer is overlying and in contact with the upper layer of the base substrate. Then a pseudomorphic passivation layer made of a group IV semiconductor material is grown so as to be overlying and in contact with the intermediate layer. This can enable an unpinned interface. The substrate surface can be smoother, implying fewer problems from surface stress. It can be used in electronic devices such as metal-oxide-semiconductor field effect transistors (MOSFETs), high electron mobility transistors (HEMTs), tunneling field effect transistors (TFETs), and optoelectronic devices.

Method for manufacturing a low defect interface between a dielectric and a III-V compound

The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.

GATE-ALL-AROUND SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure. 1. A method of fabricating a semiconductor device , the method comprising:providing a semiconductor substrate formed of a first crystalline semiconductor material;forming a plurality of shallow trench isolation (STI) regions in the semiconductor substrate;forming a plurality of semiconductor fins interposed between a pair of adjacent STI regions and extending in a first lateral direction, each of the semiconductor fins comprising a second crystalline semiconductor material lattice mismatched to the first crystalline semiconductor material, each semiconductor fin being separated from an adjacent fin by one of the STI regions;providing at least one nanostructure formed of a third crystalline semiconductor material on the second crystalline semiconductor material of each semiconductor fin, the at least one nanostructure extending in the first lateral direction;providing a sacrificial gate on the at least one nanostructure;providing on the at least one nanostructure a source region and a drain region separated in the first lateral direction from the source region by the sacrificial gate;removing the sacrificial gate and further removing the second crystalline semiconductor material, thereby suspending the at least one nanostructure being anchored by the source and drain region; andproviding a final gate stack surrounding the at least one nanostructure after removing the second crystalline ...

Method for Reducing Contact Resistance in MOS

A method for growing a III-V semiconductor structure on a SiGesubstrate, wherein n is from 0 to 1 is provided. The method includes the steps of: (a) bringing a SiGesubstrate to a high temperature; (b) exposing the area to a group V precursor in a carrier gas for from 5 to 30 min, thereby forming a doped region at said area; (c) bringing the SiGesubstrate to a low temperature; (d) exposing the doped region to a group III precursor in a carrier gas and to a group V precursor in a carrier gas until a nucleation layer of III-V material of from 5 to 15 nm is formed on the nucleation layer; (e) bringing the SiGesubstrate to an intermediate temperature; and (f) exposing the nucleation layer to a group III precursor in a carrier gas and to a group V precursor in a carrier gas. 1. A method for growing a III-V semiconductor structure on an area of a SiGesubstrate , wherein n is from 0 to 1 , comprising the steps of:{'sub': n', '1-n, '(a) setting the temperature of a SiGesubstrate between 550° C. and 750° C. if n<0.5 and between 760 and 950° C. if n≧0.5;'}{'sub': n', '1-n, 'b': '9', '(b) exposing an area of the SiGesubstrate to a group V precursor in a carrier gas for from 5 to 30 min, thereby forming a doped region () at said area;'}{'sub': n', '1-n, '(c) setting the temperature of the SiGesubstrate between 325° C. and 375° C.;'}(d) exposing the doped region to a group III precursor in a carrier gas and to a group V precursor in a carrier gas until a nucleation layer of III-V material of from 5 to 15 nm is formed on the doped region;{'sub': n', '1-n, '(e) setting the temperature of the SiGesubstrate between 450° C. and 550° C.; and'}(f) exposing the nucleation layer to a group III precursor in a carrier gas and to a group V precursor in a carrier gas, thereby forming a III-V semiconductor structure.2. The method according to claim 1 , wherein the III-V semiconductor structure is InAs.3. The method according to claim 1 , wherein the III-V semiconductor structure forms at least ...

Method for manufacturing a low defect interface between a dielectric and a III-V compound

The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.

Method for Manufacturing a Low Defect Interface Between a Dielectric and a III-V Compound

The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.

METHOD FOR FORMING A TRANSITION METAL DICHALCOGENIDE - GROUP III-V HETEROSTRUCTURE AND A TUNNELING FIELD EFFECT TRANSISTOR

A method for forming a Transition Metal Dichalcogenide (TMD)—Group III-V semiconductor heterostructure comprises forming an insulating layer on an upper surface of a substrate, wherein the upper surface of the substrate is formed by a (111)-surface of a group IV semiconductor, forming a first aperture in the insulating layer, the aperture exposing a portion of the upper surface of the substrate, forming in a first epitaxial growth process, a semiconductor structure formed by a group III-V semiconductor comprising a pillar extending through the first aperture and a micro disc extending horizontally along a first portion of the upper surface of the insulating layer, and forming in a second epitaxial growth process, a TMD layer on an upper surface of the micro disc. 1. A method for forming a transition metal dichalcogenide—group III-V semiconductor heterostructure , comprising:forming an insulating layer on an upper surface of a substrate, wherein the upper surface of the substrate is a (111)-surface of a group IV semiconductor;forming a first aperture in the insulating layer, the aperture exposing a portion of the upper surface of the substrate;forming, in a first epitaxial growth process, a semiconductor structure of a group III-V semiconductor comprising a pillar extending through the first aperture and a micro disc extending horizontally along a first portion of an upper surface of the insulating layer; andforming, in a second epitaxial growth process, a transition metal dichalcogenide layer on an upper surface of the micro disc, whereby a transition metal dichalcogenide—group III-V semiconductor heterostructure is obtained.2. The method of claim 1 , further comprising claim 1 , prior to the second epitaxial growth process:forming a first layer on a second portion of the upper surface of the insulating layer, whereby a side surface of the micro disc is covered.3. The method of claim 2 , further comprising claim 2 , prior to the second epitaxial growth process: ...

Perovskite oxides with a-axis orientation

A structure is provided and includes (i) a substrate having a surface, the surface comprising a ternary or quaternary oxide having a first lattice parameter, the first lattice parameter being a lattice parameter of the ternary or quaternary oxide as it is present at the surface; and (ii) a layer of a perovskite oxide on the ternary or quaternary oxide, the perovskite oxide having a second lattice parameter, the second lattice parameter being a native lattice parameter of the perovskite oxide, wherein the first lattice parameter is larger than the second lattice parameter. A method for forming a perovskite oxide with an a-axis orientation is also provided.

Self-aligned nanostructures for semiconductor devices

A method for forming a semiconductor device is disclosed. The method includes providing a semiconductor substrate. The method also includes epitaxially growing on the semiconductor substrate a first part of a III-V semiconductor nanostructure. The method further includes covering the first part of the III-V semiconductor nanostructure with a layer of a first material. Additionally, the method includes removing a top portion of the layer of the first material. Still further, the method includes epitaxially growing on the first part of the III-V semiconductor nanostructure a second part of the III-V semiconductor nanostructure. The method additionally includes covering the second part of the III-V semiconductor nanostructure with a layer of a second material. The second material is different from the first material. Even further, the method includes removing a top portion of the layer of the second material.

III-V device and method for manufacturing thereof

The disclosure relates to a method for manufacturing a III-V device and the III-V device obtained therefrom. The method comprises providing a semiconductor substrate including at least a recess area and forming a buffer layer overlying the semiconductor substrate in the recess area. The buffer layer includes a binary III-V compound formed at a first growth temperature by selective epitaxial growth from a group III precursor and a group V precursor in the presence of a carrier gas. The first growth temperature is equal or slightly higher than a cracking temperature of each of the group III precursor and of the group V precursor.

Method for Formation of a Transition Metal Dichalcogenide (TMDC) Material Layer

A method for formation of a transition metal dichalcogenide (TMDC) material layer on a substrate arranged in a process chamber of a molecular beam epitaxy tool is provided. The method includes evaporating metal from a solid metal source, forming a chalcogen-including gas-plasma, and introducing the evaporated metal and the chalcogen-including gas-plasma into the process chamber thereby forming a TMDC material layer on the substrate.

GATE-ALL-AROUND SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure. 1. A semiconductor device comprising:a semiconductor substrate comprising a crystalline semiconductor material;at least one suspended nanostructure extending in a first direction and formed at least partially above and between a pair of adjacent STI regions, the at least one suspended nanostructure being electrically connected to and mechanically supported by a source region and a drain region formed at opposite ends of the at least one suspended nanostructure in the first direction, wherein the at least one suspended nanostructure comprises a crystalline semiconductor material that is different from the crystalline semiconductor material of the semiconductor substrate;a cavity formed vertically between the at least one suspended nanostructure and the semiconductor substrate and laterally between sidewalls of the STI regions facing each other; anda gate stack surrounding the suspended nanostructure, wherein the gate stack extends to cover a top surface and the sidewalls of the STI regions and an exposed surface of the semiconductor substrate in the cavity.2. The semiconductor device of claim 1 , wherein the at least one nanostructure includes only one suspended nanostructure with a width substantially equal to the width of the cavity.3. The semiconductor device of claim 1 , wherein the at least one nanostructure includes two suspended nanostructures at a distance D from each other claim 1 , ...

Method for Manufacturing a Si-Based High-Mobility CMOS Device With Stacked Channel Layers, and Resulting Devices

A device and method for manufacturing a Si-based high-mobility CMOS device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a III-V semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with III-V semiconductor material by etching via holes in the first oxide layer followed by selective area growth; (iii) manufacturing a second insulation layer above the III-V semiconductor channel layer and uncovering the trench; (iv) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by depositing a second dummy layer of a sacrificial material, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching via holes in the second oxide layer followed by selective area growth. 1. A method for manufacturing a Si-based high-mobility CMOS device , wherein a Ge or SiGechannel layer and a III-V semiconductor channel layer are co-integrated on a silicon substrate , the method comprising the steps of:a) providing a silicon substrate having a first insulation layer on top and a trench extending through the insulation layer and into the silicon;b) manufacturing a III-V semiconductor channel layer above the first insulation layer by means of, in sequence, depositing a first dummy layer of a sacrificial material above the first insulation layer and in the trench, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with III-V semiconductor material by etching the sacrificial material via first holes made in the first oxide layer followed by selective area growth with the III-V semiconductor material;c) manufacturing a second insulation layer above the III ...

Method for reducing contact resistance in MOS

A method for growing a III-V semiconductor structure on a SinGe1-n substrate, wherein n is from 0 to 1 is provided. The method includes the steps of: (a) bringing a SinGe1-n substrate to a high temperature; (b) exposing the area to a group V precursor in a carrier gas for from 5 to 30 min, thereby forming a doped region at said area; (c) bringing the SinGe1-n substrate to a low temperature; (d) exposing the doped region to a group III precursor in a carrier gas and to a group V precursor in a carrier gas until a nucleation layer of III-V material of from 5 to 15 nm is formed on the nucleation layer; (e) bringing the SinGe1-n substrate to an intermediate temperature; and (f) exposing the nucleation layer to a group III precursor in a carrier gas and to a group V precursor in a carrier gas.

Method for Manufacturing a Si-Based High-Mobility CMOS Device With Stacked Channel Layers, and Resulting Devices

A device and method for manufacturing a Si-based high-mobility CMOS device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a III-V semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with III-V semiconductor material by etching via holes in the first oxide layer followed by selective area growth; (iii) manufacturing a second insulation layer above the III-V semiconductor channel layer and uncovering the trench; (iv) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by depositing a second dummy layer of a sacrificial material, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching via holes in the second oxide layer followed by selective area growth.

Method for manufacturing a Si-based high-mobility CMOS device with stacked channel layers, and resulting devices

A device and method for manufacturing a Si-based high-mobility CMOS device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a III-V semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with III-V semiconductor material by etching via holes in the first oxide layer followed by selective area growth; (iii) manufacturing a second insulation layer above the III-V semiconductor channel layer and uncovering the trench; (iv) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by depositing a second dummy layer of a sacrificial material, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching ...

Gate-all-around semiconductor device and method of fabricating the same

The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.

III-V Device and Method for Manufacturing Thereof

The disclosure relates to a method for manufacturing a III-V device and the III-V device obtained therefrom. The method comprises providing a semiconductor substrate including at least a recess area and forming a buffer layer overlying the semiconductor substrate in the recess area. The buffer layer includes a binary III-V compound formed at a first growth temperature by selective epitaxial growth from a group III precursor and a group V precursor in the presence of a carrier gas. The first growth temperature is equal or slightly higher than a cracking temperature of each of the group III precursor and of the group V precursor.

PEROVSKITE OXIDES WITH A-AXIS ORIENTATION

A structure is provided and includes (i) a substrate having a surface, the surface comprising a ternary or quaternary oxide having a first lattice parameter, the first lattice parameter being a lattice parameter of the ternary or quaternary oxide as it is present at the surface; and (ii) a layer of a perovskite oxide on the ternary or quaternary oxide, the perovskite oxide having a second lattice parameter, the second lattice parameter being a native lattice parameter of the perovskite oxide, wherein the first lattice parameter is larger than the second lattice parameter. A method for forming a perovskite oxide with an a-axis orientation is also provided. 1. A structure comprising:(i) a substrate having a surface, the surface comprising a ternary or quaternary oxide having a first lattice parameter, the first lattice parameter being a lattice parameter of the ternary or quaternary oxide as it is present at the surface, and(ii) a layer of a perovskite oxide on the ternary or quaternary oxide, the perovskite oxide having an a-axis orientation and being selected from perovskite oxides having a second lattice parameter, being a native lattice parameter, and being smaller than the first lattice parameter.2. The structure according to claim 1 , wherein the first lattice parameter is from 0.05% to 3% larger than the second lattice parameter.3. The structure according to claim 1 , wherein the first lattice parameter is from 0.1% to 1.5% larger than the second lattice parameter.4. The structure according to claim 1 , wherein the ternary oxide has a general chemical formula ABOwherein A is selected from the group consisting of Ba claim 1 , Sr claim 1 , and Ca claim 1 , and B is selected from the group consisting of Ti claim 1 , Zr claim 1 , and Hf.5. The structure according to claim 1 , wherein the quaternary oxide has a general chemical formula ABB′Owherein 0 Подробнее

Vertical nanowire semiconductor structures

An example semiconductor structure comprises a first surface and at least one nanowire, the at least one nanowire being perpendicular to the first surface, wherein the first surface is defect-poor and is made of a doped III-V semiconductor material, wherein the at least one nanowire is defect-poor and made of an undoped III-V semiconductor material having a lattice mismatch with the material of the first surface of from about 0% to 1%.

Method for Manufacturing a Low Defect Interface Between a Dielectric and a III-V Compound

The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.

Method of Producing a Pre-Patterned Structure for Growing Vertical Nanostructures

A method of producing a pre-patterned structure comprising at least one cavity for growing a vertical nanostructure is disclosed. The method includes providing at least one protruding structure that extends upwardly from a main surface of a substrate. The at least one protruding structure has a main portion of a first height and an upper portion on the main portion. The method also includes embedding the at least one protruding structure in a dielectric material. Further, the method includes removing at least an excess portion of the dielectric material, thereby exposing a top surface of the upper portion and forming a flattened surface of the top surface of the upper portion and the dielectric material. In addition, the method includes forming at least one cavity of a first depth by removing the upper portion, thereby exposing a top surface of the main portion of the at least one protruding structure. 1. A method of producing a pre-patterned structure comprising at least one cavity for growing a vertical nanostructure , the method comprising:providing at least one protruding structure that extends upwardly from a main surface of a substrate, wherein the at least one protruding structure has a main portion of a first height and an upper portion on the main portion, and wherein at least the main portion comprises a monocrystalline semiconductor material;embedding the at least one protruding structure in a dielectric material;removing at least an excess portion of the dielectric material by performing a surface flattening process, thereby exposing a top surface of the upper portion and forming a flattened surface of the top surface of the upper portion and the dielectric material; andforming at least one cavity of a first depth by removing the upper portion, thereby exposing a top surface of the main portion of the at least one protruding structure.2. The method according to claim 1 , wherein claim 1 , the first depth is less than the first height.3. The method ...

Laser Devices

An electrically-operated semiconductor laser device and method for forming the laser device are provided. The laser device includes a fin structure to which a waveguide is optically coupled. The waveguide is optically coupled to passive waveguides at either end thereof. The fin structure includes an array of fin elements, each fin element comprising Group III-V materials.

Gate-all-around semiconductor device and method of fabricating the same

The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.

Laser devices

An electrically-operated semiconductor laser device and method for forming the laser device are provided. The laser device includes a fin structure to which a waveguide is optically coupled. The waveguide is optically coupled to passive waveguides at either end thereof. The fin structure includes an array of fin elements, each fin element comprising Group III-V materials.

Method for forming a qubit device

The disclosed technology is directed to a method of forming a qubit device. In one aspect, the method comprises: forming a gate electrode embedded in an insulating layer formed on a substrate, wherein an upper surface of the substrate is formed from a group IV semiconductor material and the gate electrode extends along the substrate in a first horizontal direction; forming an aperture in the insulating layer, the aperture exposing a portion of the substrate; forming, in an epitaxial growth process, a semiconductor structure comprising a group III-V semiconductor substrate contact part and a group III-V semiconductor disc part, the substrate contact part having a bottom portion abutting the portion of the substrate and an upper portion protruding from the aperture above an upper surface of the insulating layer, the semiconductor disc part extending from the upper portion of the substrate contact part, horizontally along the upper surface of the insulating layer to overlap a portion of the gate electrode; forming a mask covering a portion of the disc part, the portion of the disc part extending across the portion of the gate electrode in a second horizontal direction; etching regions of the semiconductor structure exposed by the mask such that the masked portion of the disc part remains to form a channel structure extending across the portion of the gate electrode; and forming a superconductor source contact and a superconductor drain contact on the channel structure at opposite sides of the portion of the gate electrode.

Si-based high-mobility CMOS device with stacked channel layers and resulting devices

A device and method for manufacturing a Si-based high-mobility CMOS device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a III-V semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with III-V semiconductor material by etching via holes in the first oxide layer followed by selective area growth; (iii) manufacturing a second insulation layer above the III-V semiconductor channel layer and uncovering the trench; (iv) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by depositing a second dummy layer of a sacrificial material, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching ...

Method for formation of a transition metal dichalcogenide (TMDC) material layer

A method for formation of a transition metal dichalcogenide (TMDC) material layer on a substrate arranged in a process chamber of a molecular beam epitaxy tool is provided. The method includes evaporating metal from a solid metal source, forming a chalcogen-including gas-plasma, and introducing the evaporated metal and the chalcogen-including gas-plasma into the process chamber thereby forming a TMDC material layer on the substrate.

HIGH-K HETEROSTRUCTURE

A method for preparing a multilayer substrate includes the step of deposing an epitaxial γ-Al 2 O 3 Miller index (001) layer on a Si Miller index (001) substrate.

Self-Aligned Nanostructures for Semiconductor Devices

A method for forming a semiconductor device is disclosed. The method includes providing a semiconductor substrate. The method also includes epitaxially growing on the semiconductor substrate a first part of a III-V semiconductor nanostructure. The method further includes covering the first part of the III-V semiconductor nanostructure with a layer of a first material. Additionally, the method includes removing a top portion of the layer of the first material. Still further, the method include epitaxially growing on the first part of the III-V semiconductor nanostructure a second part of the III-V semiconductor nanostructure. The method additionally includes covering the second part of the III-V semiconductor nanostructure with a layer of a second material. The second material is different from the first material. Even further, the method includes removing a top portion of the layer of the second material. 1. A method for forming a semiconductor device , comprising:providing a semiconductor surface;epitaxially growing on, and perpendicular to, the semiconductor surface a first part of a III-V semiconductor nanostructure, wherein the first part comprises a top surface;covering the first part of the III-V semiconductor nanostructure with a layer of a first material;removing a top portion of the layer of the first material such that a top surface of the layer of the first material is co-planar with the top surface of the first part of the III-V semiconductor nanostructure, thereby exposing the top surface of the first part of the III-V semiconductor nanostructure;epitaxially growing on the first part of the III-V semiconductor nanostructure a second part of the III-V semiconductor nanostructure, wherein the second part comprises a top surface;covering the second part of the III-V semiconductor nanostructure with a layer of a second material, wherein the second material is different from the first material; andremoving a top portion of the layer of the second material ...

Method for Manufacturing an III-V Engineered Substrate and the III-V Engineered Substrate Thereof

Manufacturing an III-V engineered substrate involves providing a base substrate comprising an upper layer made of a first III-V compound with a <110> or a <111> crystal orientation, forming an intermediate layer comprising at least a buffer layer of a second III-V compound, wherein the intermediate layer is overlying and in contact with the upper layer of the base substrate. Then a pseudomorphic passivation layer made of a group IV semiconductor material is grown so as to be overlying and in contact with the intermediate layer. This can enable an unpinned interface. The substrate surface can be smoother, implying fewer problems from surface stress. It can be used in electronic devices such as metal-oxide-semiconductor field effect transistors (MOSFETs), high electron mobility transistors (HEMTs), tunneling field effect transistors (TFETs), and optoelectronic devices.

METHOD FOR FORMING A QUBIT DEVICE

The disclosed technology is directed to a method of forming a qubit device. In one aspect, the method comprises: forming a gate electrode embedded in an insulating layer formed on a substrate, wherein an upper surface of the substrate is formed from a group IV semiconductor material and the gate electrode extends along the substrate in a first horizontal direction; forming an aperture in the insulating layer, the aperture exposing a portion of the substrate; forming, in an epitaxial growth process, a semiconductor structure comprising a group III-V semiconductor substrate contact part and a group III-V semiconductor disc part, the substrate contact part having a bottom portion abutting the portion of the substrate and an upper portion protruding from the aperture above an upper surface of the insulating layer, the semiconductor disc part extending from the upper portion of the substrate contact part, horizontally along the upper surface of the insulating layer to overlap a portion of the gate electrode; forming a mask covering a portion of the disc part, the portion of the disc part extending across the portion of the gate electrode in a second horizontal direction; etching regions of the semiconductor structure exposed by the mask such that the masked portion of the disc part remains to form a channel structure extending across the portion of the gate electrode; and forming a superconductor source contact and a superconductor drain contact on the channel structure at opposite sides of the portion of the gate electrode. 1. A method of forming a qubit device , the method comprising:forming a gate electrode embedded in an insulating layer formed on a substrate, wherein an upper surface of the substrate is formed from a group IV semiconductor material and the gate electrode extends along the substrate in a first horizontal direction;forming an aperture in the insulating layer, the aperture exposing a portion of the substrate;forming, in an epitaxial growth process, a ...

Vertical Nanowire Semiconductor Structures

An example semiconductor structure comprises a first surface and at least one nanowire, the at least one nanowire being perpendicular to the first surface, wherein the first surface is defect-poor and is made of a doped III-V semiconductor material, wherein the at least one nanowire is defect-poor and made of an undoped III-V semiconductor material having a lattice mismatch with the material of the first surface of from about 0% to 1%.

Passivated III-V or Ge fin-shaped field effect transistor

A semiconductor device includes a semiconductor substrate having a top surface, and at least one coated fin protruding perpendicularly from the surface and having a height h and side walls. The at least one coated fin further includes a core of one or more layers selected from the group consisting of (a) III-V compound layers and (b) a Ge layer, and a coating overlaying the core. The coating includes one or more metal oxide layers, at least one of which is aluminium. The device also includes a recess surrounding the at least one coated fin and being defined between two coated fins when more than one fin is present. The recess is filled up with a dielectric material so as to cover the coating on the side walls of the at least one fin up to a certain height h′, which is less than the height h. The present disclosure also relates to a method for producing the semiconductor device.

Passivated III-V or Ge Fin-Shaped Field Effect Transistor

A semiconductor device includes a semiconductor substrate having a top surface, and at least one coated fin protruding perpendicularly from the surface and having a height h and side walls. The at least one coated fin further includes a core of one or more layers selected from the group consisting of (a) III-V compound layers and (b) a Ge layer, and a coating overlaying the core. The coating includes one or more metal oxide layers, at least one of which is aluminium. The device also includes a recess surrounding the at least one coated fin and being defined between two coated fins when more than one fin is present. The recess is filled up with a dielectric material so as to cover the coating on the side walls of the at least one fin up to a certain height h′, which is less than the height h. The present disclosure also relates to a method for producing the semiconductor device.

Method for manufacturing a iii-v gate all around semiconductor device

A gate-all-around semiconductor device and a method for manufacturing a gate-all-around (GAA) semiconductor device are disclosed. The method comprises providing on a semiconductor substrate (100) in between STI regions (101) at least one suspended nanostructure (105) anchored by a source (121) and a drain region (122), the suspended nanostructure comprising a crystalline semiconductor material which is different from the semiconductor substrate. A gate stack (117) is provided around the at least one suspended nanostructure.

A method for forming a qubit device

Method for manufacturing a low defect interface between a dielectric and a III/V compound

Method for reducing contact resistance in a transistor

Method for manufacturing an III-V material substrate and the substrate thereof

An integrated electro-optical absorption modulator

The present disclosure is related to an integrated electro-optical absorption modulator. A two-dimensional (2D) material is employed for forming electrodes of the modulator, and a material with a non-zero off-diagonal electro-optic tensor coefficient may be employed for forming a waveguide core of the modulator. The modulator comprises a cladding, a waveguide core arranged at least partly in the cladding to guide light, and a first electrode and a second electrode arranged on opposite sides of the waveguide core. Each electrode is formed of the 2D material on a surface of the cladding or in the cladding, and extends into the waveguide core. The electrodes are configured to apply an electric field across a modulation region of the waveguide core, and thereby to convert at least a part of the energy of the light in the modulation region between two orthogonal modes, wherein one of the two orthogonal modes is polarized perpendicular to the plane of the 2D material.

High-k heterostructure

A method for preparing a multilayer substrate includes the step of deposing an epitaxial γ-Al 2 O 3 Miller index (001) layer on a Si Miller index (001) substrate.

High-k heterostructure

A method for preparing a multilayer substrate, comprising the step of deposing an epitaxial Y-AI2O3 Miller indice (001) layer (22) on a Si Miller indice (001) substrate (20).

High-k heterostructure

High-k heterostructure

A method for preparing a multilayer substrate, comprising the step of deposing an epitaxial Y-AI2O3 Miller indice (001) layer (22) on a Si Miller indice (001) substrate (20).

An integrated electro-optical absorption modulator

This disclosure is related to an integrated electro-optical absorption modulator. A two-dimensional (2D) material is employed for forming electrodes, and a material with a non-zero off-diagonal electro-optic tensor coefficient may be employed for forming a waveguide core. The modulator comprises a cladding, a waveguide core arranged at least partly in the cladding, and a first and a second electrode arranged on opposite sides of the waveguide core. Each electrode is formed of the 2D material on a surface of the cladding or in the cladding, and extends into the waveguide core. The electrodes are configured to apply an electric field across a modulation region of the waveguide core, and thereby to convert at least a part of the energy of the light in the modulation region between two orthogonal modes, wherein one of the two orthogonal modes is polarized perpendicular to the plane of the 2D material.

不動態化したＩＩＩ−Ｖ族またはＧｅフィン形状電界効果トランジスタ

【課題】低いソース−ドレイン漏れを有するＩＩＩ−Ｖ族及び／又はＧｅのＦｉｎＦＥＴを提供する。 【解決手段】半導体デバイスは、上面を有する半導体基板（２）と；（ａ）ＩＩＩ−Ｖ族化合物層および（ｂ）Ｇｅ層からなるグループから選択された１つ以上の層を含むコア（５）、および前記コア（５）を覆うコーティング（６）であって、１つ以上の金属酸化物層を含み、そのうち少なくとも１つはアルミニウムを含むようにしたコーティング（６）を備え、前記上面から垂直に突出し、高さｈおよび側壁を有する少なくとも１つのコート付フィン（５）と；前記少なくとも１つのコート付フィン（５）を包囲し、１つより多くのフィン（５）が存在する場合は前記コート付フィン（５）の間にある凹部（９）であって、該少なくとも１つのフィン（５）の側壁の上にある該コーティングをｈより低い特定の高さｈ’まで覆うように、誘電体材料で充填された前記凹部（９）と；を備える。 【選択図】図４

Method for etching a silicon containing surface

A Method for etching a silicon-containing surface of a substrate or a layer deposited on a substrate without forming solid adducts, wherein the method comprising: Flowing NF3 and H2 into an activation zone of a cleaning system or chamber, activating NF3 and H2 in the activation zone by forming H-radicals, forming gaseous HF in a first reaction of the H-radicals with NF3 and reaction products of NF3, flowing the gaseous HF to the surface and forming gaseous SiF4 in a second reaction of HF with SiO2 of the surface. The flow ratio of R=(NF3)/(NF3+H2) is less than 0.3 or is between 0.2 and 0.3. The substrate is maintained at a temperature between room temperature and 1050°C during the etching operation. The first reaction comprises first subsequent reactions of NF2 with H-radicals and NF with H-radicals. The first reaction comprises second subsequent reactions forming NH3. The first reaction comprises third subsequent reactions forming molecules comprising NH and F and F-radicals.

Method for manufacturing a Si-based high-mobility CMOS device with stacked channel layers, and resulting devices

A device and method for manufacturing a Si-based high-mobility CMOS device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a III-V semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with III-V semiconductor material by etching via holes in the first oxide layer followed by selective area growth; (iii) manufacturing a second insulation layer above the III-V semiconductor channel layer and uncovering the trench; (iv) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by depositing a second dummy layer of a sacrificial material, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching via holes in the second oxide layer followed by selective area growth.