Способ изготовления последовательности фотогальванических слоев методом печати при комнатной температуре и последовательность фотогальванических слоев, полученная данным способом

Verfahren zur Herstellung eines porösen halbleitenden Films

Verfahren zur Herstellung einer porösen halbleitenden Struktur, dadurch gekennzeichnet, dass A. dotierte Halbmetallpartikel erzeugt werden, und anschließend B. aus den nach Schritt A erhaltenen Halbmetallpartikeln eine Dispersion erzeugt wird, und anschließend C. ein Substrat mit der nach Schritt B erhaltenen Dispersion beschichtet wird, und anschließend D. die nach Schritt C erhaltene Schicht durch eine Lösung von Fluorwasserstoff in Wasser behandelt wird, und anschließend E. die nach Schritt D erhaltene Schicht thermisch behandelt wird, wobei eine poröse halbleitende Struktur erhalten wird.

ZnO Nanomaterials and gas sensors made using said nanomaterials

PROCEDURE FOR THE PRODUCTION OF GROUP III-METAL NITRIDE MATERIALS

Method and apparatus for producing M^IIIN columns and M^IIIN materials grown thereon

Manufacturing method of two-dimensional material structure and two-dimensional material device

Nitride semiconductor structure and method for producing the same

FOLDABLE HYBRID CIRCUIT COMPRISING ANISOTROPIC CONDUCTIVE CARBON FILM AND METHOD OF PREPARING THE SAME

Semiconductor device and method for manufacturing semiconductor device

A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. An oxide semiconductor film which can have a first crystal structure by heat treatment and an oxide semiconductor film which can have a second crystal structure by heat treatment are formed so as to be stacked, and then heat treatment is performed; accordingly, crystal growth occurs with the use of an oxide semiconductor film having the second crystal structure as a seed, so that an oxide semiconductor film having the first crystal structure is formed. An oxide semiconductor film formed in this manner is used for an active layer of the transistor.

Support for a semiconductor structure

The invention relates to a support (1) for a semiconductor structure comprising a charge-trapping layer (2) on a base substrate (3). The trapping layer (2) consists of a polycrystalline main layer (2a) and, interposed in the main layer (2a) or between the main layer (2a) and the base substrate (3), at least one intermediate polycrystalline layer (2b) composed of a silicon and carbon alloy or carbon, the intermediate layer (2b) having a resistivity greater than 1000 ohm. cm.

HIGH EFFECIENCY ULTRAVIOLET LIGHT EMITTING DIODE WITH BAND STRUCTURE POTENTIAL FLUCTUATIONS

A method of growing an AlGaN semiconductor material utilizes an excess of Ga above the stoichiometric amount typically used. The excess Ga results in the formation of band structure potential fluctuations that improve the efficiency of radiative recombination and increase light generation of optoelectronic devices, in particular ultraviolet light emitting diodes, made using the method. Several improvements in UV LED design and performance are also provided for use together with the excess Ga growth method. Devices made with the method can be used for water purification, surface sterilization, communications, and data storage and retrieval.

OPTOELECTRONIC DEVICE HAVING SEMI-CONDUCTIVE MICROWIRES OR NANOWIRES AND METHOD FOR PRODUCING SAME

The invention concerns an optoelectrical device (10) comprising microwires or nanowires (24) on a support (14, 20 and 22), each microwire or nanowire comprising at least one portion (26) predominantly comprising a III-V compound in contact with the substrate, in which the III-V compound is made from a first element from group V and a second element from group III, in which one face (23) of the substrate comprises first areas (20) made from a first material promoting the growth of the III-V compound according to the polarity of the first element distributed in a second area (22) made from a second material promoting the growth of the compound according to the polarity of the second element, the microwires or nanowires (24) being positioned on the first areas, in which the edge of said portion (26) is covered with a layer (36) made from a dielectric material from the substrate along a part of the total height of said portion.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. An oxide semiconductor film which can have a first crystal structure by heat treatment and an oxide semiconductor film which can have a second crystal structure by heat treatment are formed so as to be stacked, and then heat treatment is performed; accordingly, crystal growth occurs with the use of an oxide semiconductor film having the second crystal structure as a seed, so that an oxide semiconductor film having the first crystal structure is formed. An oxide semiconductor film formed in this manner is used for an active layer of the transistor.

Process for forming homoepitaxial tunnel barriers with hydrogenated graphene-on-graphene for room temperature electronic device applications

A homoepitaxial, ultrathin tunnel barrier-based electronic device in which the tunnel barrier and transport channel are made of the same material—graphene.

GROUP III NITRIDE COMPOSITE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR DEVICE

Provided are a group III nitride composite substrate having a low sheet resistance and produced with a high yield, and a method for manufacturing the same, as well as a method for manufacturing a group III nitride semiconductor device using the group III nitride composite substrate. A group III nitride composite substrate includes a group III nitride film and a support substrate formed from a material different in chemical composition from the group III nitride film. The group III nitride film is joined to the support substrate in one of a direct manner and an indirect manner. The group III nitride film has a thickness of 10 μm or more. A sheet resistance of a group III-nitride-film-side main surface is 200 Ω/sq or less.

Light-emitting diode and method of manufacturing the same

A light-emitting diode and a method of manufacturing the light-emitting diode are provide, the light-emitting diode including a lower electrode on a substrate, a template layer on the lower electrode. The template layer may have a plurality of open regions. A plurality of nano-dashes may be formed in the plurality of open regions of the template layer. A transparent insulating layer may be formed between the nano-dashes. A transparent upper electrode may be formed on the nano-dashes and the transparent insulating layer.

SEMICONDUCTOR MATERIAL INCLUDING DIFFERENT CRYSTALLINE ORIENTATION ZONES AND RELATED PRODUCTION PROCESS

The invention relates to a manufacturing process of semiconductor material of element III nitride from a starting substrate, the process comprising: the formation of an intermediate layer based on silicon on a starting substrate, said intermediate layer comprising at least two adjacent zones of different crystalline orientations, especially a monocrystalline zone and an amorphous or poly-crystalline zone, growth via epitaxy of a layer of element III nitride on said intermediate layer, the intermediate layer being intended to be vaporised spontaneously during the step consisting of growing the layer of element III nitride via epitaxy.

Composition and Method for Making Picocrystalline Artificial Borane Atoms

Materials containing picocrystalline quantum dots that form artificial atoms are disclosed. The picocrystalline quantum dots (in the form of boron icosahedra with a nearly-symmetrical nuclear configuration) can replace corner silicon atoms in a structure that demonstrates both short range and long-range order as determined by x-ray diffraction of actual samples. A novel class of boron-rich compositions that self-assemble from boron, silicon, hydrogen and, optionally, oxygen is also disclosed. The preferred stoichiometric range for the compositions is (B12Hw)xSiyOz with 3≦w≦5, 2≦x≦4, 2≦y≦5 and 0≦z≦3. By varying oxygen content and the presence or absence of a significant impurity such as gold, unique electrical devices can be constructed that improve upon and are compatible with current semiconductor technology.

METHODS OF FORMING FIN-ON-NANOSHEET TRANSISTOR STACKS

Methods of forming a plurality of transistor stacks are provided. A method of forming a plurality of transistor stacks includes etching a plurality of nanosheets, using a plurality of spacers that are on sidewalls of a plurality of semiconductor fins as an etch mask, to provide a plurality of spaced-apart nanosheet stacks that each have at least one of the semiconductor fins thereon.

TRANSISTORS WITH REDUCED EPITAXIAL SOURCE/DRAIN SPAN VIA ETCH-BACK FOR IMPROVED CELL SCALING

Methods, transistors, and systems are discussed related to anisotropically etching back deposited epitaxial source and drain semiconductor materials for reduced lateral source and drain spans in the fabricated transistors. Such lateral width reduction of the source and drain materials enables improved transistor scaling and perturbation reduction in the resultant source and drain semiconductor materials.

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

A method for forming a semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure also includes a first bottom layer formed adjacent to the first nanostructures, and a first dielectric liner layer formed over the first bottom layer and adjacent to the first nanostructures. The semiconductor device structure further includes a first source/drain (S/D) structure formed over the first dielectric liner layer, and the first S/D structure is isolated from the first bottom layer by the first dielectric liner layer.

MANUFACTURING APPARATUS AND MANUFACTURING METHOD FOR QUANTUM DOT MATERIAL

A manufacturing apparatus and a manufacturing method for a quantum dot material. The manufacturing apparatus (10) adds an optical device (120) capable of generating an interference pattern in an existing epitaxial apparatus (110), so that a substrate (200) applies an interference pattern on an epitaxial layer while performing epitaxial growth. By means of the interference pattern, a regularly distributed temperature field is formed on the epitaxial layer, so that on the epitaxial layer, an atom aggregation phenomenon is formed at dot positions with higher temperature, but no atoms are aggregated on areas having relatively lower temperature. Therefore, according to the temperature distribution on the surface of the epitaxial layer, positions where quantum dots generate can be controlled manually without introducing defects, thereby achieving a defect-free and long-range ordered quantum dot manufacturing.

Способ выращивания в вертикальном реакторе многослойных наногетероэпитаксиальных структур с массивами идеальных квантовых точек

Stempelreplikationsvorrichtung und Verfahren zum Herstellen einer Halteeinrichtung für eine Stempelreplikationsvorrichtung sowie eines Stempels

Eine Stempelreplikationsvorrichtung (10) zur Herstellung von Stempeln für die Herstellung von mikro- und/oder nanostrukturierten Bauteilen hat eine Plattform (14), einen auf die Plattform (14) aufsetzbaren Deckel (12) und eine Halteeinrichtung (32) für einen Stempelträger (28), wobei die Halteeinrichtung (32) am Deckel (12) oder an der Plattform (14) ausgebildet ist und einen Träger (33) sowie eine mikrostrukturierte Vakuumfläche (34) auf dem Träger (33) zur Halterung des Stempelträgers (28) aufweist. Des Weiteren wird ein Verfahren zur Herstellung eine Halteeinrichtung (32) für eine Stempelreplikationsvorrichtung (10) und ein Verfahren zur Herstellung eines Stempels angegeben.

Mikromechanische Struktur mit Kupfer-Leiterbahn

Die Erfindung geht aus von einer mikromechanischen Struktur mit einer Verankerung (30), einer Siliziumfeder (10) und einem beweglichen Teil (40), wobei die Siliziumfeder (10) an einem ersten Ende (13) mit der Verankerung (30) und an einem zweiten Ende (14) mit dem beweglichen Teil (40) verbunden ist, wobei an der Siliziumfeder (10) wenigstens eine Kupfer-Leiterbahn (20) angeordnet ist, welche sich wenigstens vom ersten Ende (13) zum zweiten Ende (14) erstreckt. Der Kern der Erfindung besteht darin, dass die Kupfer-Leiterbahn (20) eine Schichtstruktur mit mehreren aneinandergrenzenden Kupferschichten (21) aufweist.Die Erfindung betrifft auch ein Verfahren zur Herstellung einer mikromechanischen Struktur mit einer Siliziumfeder (10) mit einer Kupfer-Leiterbahn (20) mit einer Schichtstruktur mit mehreren aneinandergrenzenden Kupferschichten (21).

METHOD OF FORMING QUANTUM DOTS FOR EXTENDED WAVELENGTH OPERATION

METHOD FOR PRODUCTION OF A LAYERED STRUCTURE WITH NANOCRYSTALS IN A DIELECTRIC LAYER

LED AND FABRICATION METHOD THEREOF

METHOD FOR REALIZATION Of STACKINGS Of MATERIAL SEMI-CONDUCTEURENCAPSULES SMALL ISLANDS IN ANOTHER SEMICONDUCTOR MATERIAL

L'invention concerne la réalisation d'une structure empilée de plans d'îlots d'un premier matériau semiconducteur encapsulés dans un deuxième matériau semiconducteur, sur un substrat, comprenant le dépôt alterné de plans d'îlots de premier matériau semiconducteur et de couches d'encapsulation de deuxième matériau semiconducteur, les plans d'îlots de premier matériau semiconducteur étant réalisés à une température de croissance optimale et sous une pression partielle de gaz précurseur optimale pour obtenir une structure empilée dont les propriétés optiques permettent la réalisation de composants optoélectroniques pour interconnecter optiquement des circuits intégrés. La structure empilée est réalisée sur un plan d'îlots de troisième matériau semiconducteur, dit plan sacrificiel, encapsulé dans un quatrième matériau semiconducteur, les îlots du plan sacrificiel étant réalisés dans des conditions de croissance permettant d'obtenir de fortes densités d'îlots de faible taille, c'est-à-dire à ...

PROCESS OF SELECTIVE GROWTH ON A STRUCTURE SEMICONDUCTRICE

Selon ce procédé, qui s'applique notamment en électronique, on forme une structure semiconductrice (12) à partir de premiers flux gazeux ou moléculaires ; en même temps ou de façon décalée, on ajoute à ceux-ci au moins un deuxième flux gazeux ou moléculaire, pour faire croître sélectivement et in situ une couche diélectrique (14) sur la structure ; puis on fait croître sur celle-ci une autre structure semiconductrice (16) à partir de troisièmes flux gazeux ou moléculaires.

Method for modifying the properties of a thin layer of a substrate for applications in making electronic and optoelectronic components

L'invention concerne un procédé pour modifier les propriétés d'une couche mince réalisée en surface d'un support formant un substrat utilisé dans le domaine de la micro-, nano-électronique ou de la micro-, nano-technologie, consistant : - à réaliser sur un support nanostructuré à surface spécifique élevée, au moins une couche mince, - et à traiter le support nanostructuré pour générer des contraintes internes dans le support entraînant sa déformation au moins dans le plan de la couche mince de manière à assurer une déformation correspondante de la couche mince pour en modifier ses propriétés.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

ELECTRONIC DEVICE HAVING TWO-DIMENSIONAL MATERIAL LAYER AND METHOD OF MANUFACTURING ELECTRONIC DEVICE USING INKJET PRINTING

Disclosed are an electronic device having a two-dimensional material layer and a method of manufacturing an electronic device using inkjet printing. The electronic device includes a first and a second electrode which are separated from each other, a two-dimensional material layer which connects the first and the second electrode. Here, the two-dimensional material layer includes two-dimensional nano material layers of which one or more parts are overlapped with each other. So, the electronic device can be manufactured by a simple process. COPYRIGHT KIPO 2016 ...

Methods of forming semiconductor device structures including two-dimensional material structures, and related semiconductor device structures and electronic systems

A method of forming a semiconductor device structure comprises forming at least one 2D material over a substrate. The at least one 2D material is treated with at least one laser beam having a frequency of electromagnetic radiation corresponding to a resonant frequency of crystalline defects within the at least one 2D material to selectively energize and remove the crystalline defects from the at least one 2D material. Additional methods of forming a semiconductor device structure, and related semiconductor device structures, semiconductor devices, and electronic systems are also described.

A METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE HAVING QUANTUM WIRES AND A SEMICONDUCTOR DEVICE INCLUDING SUCH STRUCTURE

MIXED BISMUTH AND COPPER OXIDES AND SULPHIDES FOR PHOTOVOLTAIC USE

The present invention relates to the use of a material comprising at least one compound of formula (I): BiCu1-zOaSbSecTed (I), where 0 ≤ z ≤ 0.2; 0 ≤ a ≤ 2; 0 ≤ b ≤ 2; 0 ≤ c ≤ 2; 0 ≤ d ≤ 2; and a + b + c + d = 2, as a p‑type semiconductor, for providing a photocurrent. The invention also relates to the photovoltaic devices using these semiconductors.

METHOD FOR THE ORGANISED GROWTH OF NANOSTRUCTURES

The invention relates to a method of forming nanostructures, comprising: the formation of nucleation sites (4) by irradiating a substrate using a silicon or germanium ion beam, and the growth of nanostructures (8) on the nucleation sites thus formed.

Group III-nitride structure having successively reduced crystallographic dislocation density regions

A structure having: a nucleation layer; and a Group III-Nitride structure disposed on a surface of the nucleation layer, the Group III-Nitride structure comprising a plurality of pairs of stacked Group III-Nitride layers, each one of the pairs of layers having a lower layer having a 3D growth structure and each one of the upper one of the pairs of layers having a 2D growth structure. Each one of the lower layers at completion has a surface roughness greater than a surface roughness at completion of an upper one of the pair of layers. Interfaces between each one of the upper layers and each one of the lower layers of the plurality of pairs of stacked Group III-Nitride layers have crystallographic dislocation combinations and/or annihilations therein.

INORGANIC METALLIC OXIDE THIN FILM WITH COMPOSITE CRYSTAL FORM AND MANUFACTURING METHOD THEREOF

Disclosed is an inorganic metal oxide thin film with an embedded crystal morphology, wherein the embedded crystal morphology is composed of crystalline grains and an amorphous matrix, the crystalline grains are embedded in the amorphous matrix, and the grain size ranges from 0.5 nm to 10 nm. Also provided is a manufacturing method of the inorganic metal oxide thin film with the embedded crystal morphology.

Epitaxial Features

The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor according one embodiment of the present disclosure include a plurality of channel members disposed over a substrate, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a source/drain feature. The source/drain feature includes a first epitaxial layer in contact with the substrate and the plurality of channel members, and a second epitaxial layer in contact with the first epitaxial layer and the plurality of inner spacer features. The first epitaxial layer and the second epitaxial layer include silicon germanium. A germanium content of the second epitaxial layer is greater than a germanium content of the first epitaxial layer.

METHOD FOR PREPARING A NANOSHEET AND A MULTILAYER STRUCTURE

The present invention relates to a method for preparing a nanosheet including the steps of: depositing a solution onto a substrate to form a first layer, wherein the substrate is rotatable relative to the depositing solution; depositing and condensing target material onto the first layer to form a second layer; and separating the second layer from the first layer and the substrate to form a nanosheet. Also disclosed a multilayer structure including: a substrate; a first layer arranged to deposit onto the substrate, wherein the substrate is rotatable relative to the depositing of the first layer; and a second layer arranged to deposit onto the first layer and separable from the first layer to form a nanosheet.

ELECTRONICS DEVICE HAVING TWO-DIMENSIONAL (2D) MATERIAL LAYER AND METHOD OF MANUFACTURING THE ELECTRONIC DEVICE BY INKJET PRINTING

An electronic device includes first and second electrodes that are spaced apart from each other and a 2D material layer. The 2D material layer connects the first and second electrodes. The 2D material layer includes a plurality of 2D nanomaterials. At least some of the 2D nanomaterials overlap one another.

Methods for the synthesis of arrays of thin crystal grains of layered semiconductors SnS2 and SnS at designed locations

Methods of producing arrays of thin crystal grains of layered semiconductors, including the creation of stable atomic-layer-thick to micron-thick membranes of crystalline semiconductors by chemical vapor deposition.

GROWTH OF SEMICONDUCTORS ON HETERO-SUBSTRATES USING GRAPHENE AS AN INTERFACIAL LAYER

Graphene is used as an interfacial layer to grow Si and other semiconductors or crystalline materials including two-dimensional Si and other structures on any foreign substrate that can withstand the growth temperature without the limitation matching condition typically required for epitaxial growth.

METHOD OF FORMING INTERNAL DIELECTRIC SPACERS FOR HORIZONTAL NANOSHEET FET ARCHITECTURES

A method to form a nanosheet stack for a semiconductor device includes forming a stack of a plurality of sacrificial layers and at least one channel layer on an underlayer in which a sacrificial layer is in contact with the underlayer, each channel layer being in contact with at least one sacrificial layer, the sacrificial layers are formed from SiGe and the at least one channel layer is formed from Si; forming at least one source/drain trench region in the stack to expose surfaces of the SiGe sacrificial layers and a surface of the at least one Si channel layer; and oxidizing the exposed surfaces of the SiGe sacrificial layers and the exposed surface of the at least one Si layer in an environment of wet oxygen, or ozone and UV.

Semiconductor device and method of manufacturing the same

There are contained the steps of forming an undoped or low impurity concentration amorphous silicon film to project from an upper surface of a first insulating film, introducing selectively impurity into an uppermost surface of the amorphous silicon film to form the uppermost surface of the amorphous silicon film as a high concentration impurity region, forming hemispherical grained silicon on the uppermost surface of the amorphous silicon film at a first density and on a side surface at a second density higher than the first density by exposing the amorphous silicon film to a silicon compound gas and then annealing the amorphous silicon film in a low pressure atmosphere, and introducing the impurity into the hemispherical grained silicon and the amorphous silicon film. Accordingly, a semiconductor device having a capacitor, in which a cylindrical storage electrode from an upper surface of which silicon projections are difficult to come off is formed, can be provided.

SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

A semiconductor device includes a logic cell on a substrate and a first metal layer on the logic cell. The first metal layer includes first and second power lines that extend in a first direction, and first, second, and third lower interconnection lines, which are respectively disposed on first, second, and third interconnection tracks defined between the first and second power lines that extend in the first direction parallel to each other. The first lower interconnection line includes first and second interconnection lines spaced apart from each other by a first distance, and the third lower interconnection line includes third and fourth interconnection lines spaced apart from each other by a second distance. The first and third interconnection lines have first and second ends, respectively, which face the second and fourth interconnection lines, respectively, and have different curvatures.

Raumtemperatur-Druckverfahren zur Herstellung einer PV-Schichtfolge und verfahrensgemäß erhaltene PV-Schichtfolge

Nachteilig ist bei etablierten PV-Schichtfolgen und entsprechenden Herstellungsverfahren, dass diese verfahrenstechnisch aufwändig sind und teure, reine Ausgangsstoffe erfordern, um zuverlässig die PV-Aktivität bereitstellen zu können. Aufgabe war es daher, die Nachteile zu überwinden und ein Verfahren und eine verfahrensgemäße PV-Schichtfolge bereitzustellen, welche trotz niedrigster Herstellungskosten zuverlässig und langlebig eine PV-Funktion bereitstellen kann. Die Lösung erfolgt durch eine reaktive Konditionierung anorganischer Partikel im Rahmen eines Raumtemperatur-Druckverfahrens; die oberflächliche, reaktive Konditionierung stellt die PV-Aktivität präzise ein, liefert ein kinetisch kontrolliertes Reaktionsprodukt und kann selbst bei technisch reinen Ausgangsstoffen mit Reinheiten um 97% die angestrebte PV-Aktivität gewährleisten. In konkreter Ausführungsform sind auf einen Träger 300 Partikel 100 im Verbund in Teilabschnitten aufgedruckt, wobei jeder Teilabschnitt seinerseits einen ...

PROCEDURE FOR THE PRODUCTION QUANTITY DOTS FOR LONG-WAVE ENTERPRISE

PROCEDURE FOR THE PRODUCTION OF STACKED ISLAND STRUCTURES FROM A SEMICONDUCTOR MATERIAL IN ANOTHER SEMICONDUCTOR MATERIAL

Stamp-repelling device and method for manufacturing a holding device for a stamp-repelling device and a punch

Eine Stempelreplikationsvorrichtung (10) zur Herstellung von Stempeln für die Herstellung von mikro- und/oder nanostrukturierten Bauteilen hat eine Plattform (14), einen auf die Plattform (14) aufsetzbaren Deckel (12) und eine Halteeinrichtung (32) für einen Stempelträger (28), wobei die Halteeinrichtung (32) am Deckel (12) oder an der Plattform (14) ausgebildet ist und einen Träger (33) sowie eine mikrostrukturierte Vakuumfläche (34) auf dem Träger (33) zur Halterung des Stempelträgers (28) aufweist. Des Weiteren wird ein Verfahren zur Herstellung eine Halteeinrichtung (32) für eine Stempelreplikationsvorrichtung (10) und ein Verfahren zur Herstellung eines Stempels angegeben.

Graphene-based thin film laminate and method for manufacturing the same

Production of semiconductor nanostructures on dielectric substrate comprises chemical vapor phase deposition onto stable semiconductor seeds, e.g. for floating gate and other memory cells

L'invention concerne un procédé de réalisation de nano-structures de matériau semi-conducteur sur un substrat de matériau diélectrique par dépôt chimique en phase vapeur (CVD). Ce procédé comprend les étapes suivantes : - une étape de formation sur le substrat (12) de germes stables (14) d'un premier matériau semi-conducteur sous forme d'îlots, par dépôt CVD à partir d'un précurseur (11) du premier matériau semi-conducteur choisi pour que le matériau diélectrique (12) accepte la formation desdits germes (14), - une étape de formation de nano-structures (16A, 16B) d'un deuxième matériau semi-conducteur à partir des germes stables (14) du premier matériau semi-conducteur, par dépôt CVD à partir d'un précurseur (21) choisi pour engendrer un dépôt sélectif du deuxième matériau semi-conducteur uniquement sur lesdits germes (14). L'invention concerne également les nano-structures réalisées selon l'un de ces procédés ainsi que les dispositifs comportant lesdites nano-structures.

METHOD OF FORMING NANOCRYSTALS

Nanocrystals (20) are formed in a semiconductor, such as for example, in a memory having a floating gate. A dielectric (18) overlies a substrate (12) and is placed in a chemical vapor deposition chamber (34). A first precursor gas, such as disilane (36), is flowed into the chemical vapor deposition chamber during a first phase to nucleate the nanocrystals (20) on the dielectric with first predetermined processing conditions existing within the chemical vapor deposition chamber for a first time period. A second precursor gas, such as silane, is flowed into the chemical vapor deposition chamber during a second phase subsequent to the first phase to grow the nanocrystals under second predetermined processing conditions existing within the chemical vapor deposition chamber for a second time period. © KIPO & WIPO 2007 ...

2차원 반도체의 도핑 방법

... 본 발명은 2차원 반도체의 도핑 방법에 관한 것으로서, 본 발명의 일 실시예에 따른 발명은 2차원 반도체의 도핑 방법은, 기판 상에 감광 입자가 포함된 절연층을 형성하는 단계; 열처리 공정을 통해, 절연층에 포함된 감광 입자를 절연층의 표면으로 이동시키는 단계; 절연층 상에, 2차원 반도체층을 형성하는 단계; 및 절연층에 포함된 감광 입자의 흡수 파장에 대응하는 빛을 노광시켜, 2차원 반도체층에 포함된 2차원 반도체 물질을 도핑시키는 단계를 포함한다.

Group iii-nitride structure having successively reduced crystallographic dislocation density regions

NON-PLANAR SEMICONDUCTOR DEVICE WITH ASPECT RATIO TRAPPING

As disclosed herein, a semiconductor device with aspect ratio trapping including, a bulk substrate, a plurality of isolation pillars formed on the bulk substrate, wherein one or more gaps are formed between the isolation pillars, an oxide layer formed by epitaxy on the bulk substrate, between the isolation pillars, wherein the oxide layer partially fills the gaps between the isolation pillars, one or more fins formed over the oxide layer between the isolation pillars, such that the one or more fins fill the gaps between the isolation pillars, wherein the oxide layer electrically isolates the one or more fins from the bulk substrate. The size of the gaps between the isolation pillars is selected to statistically eliminate defects caused by a lattice mismatch between the bulk substrate and the oxide layer. The semiconductor device may also contain an aspect-ratio trapping layer between the bulk substrate and oxide layer.

Non-planar semiconductor device with multiple-head epitaxial structure on fin

A non-planar semiconductor structure includes raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon naturally growing into a diamond shape. The surface area of the epitaxial structure may be increased by removing portion(s) thereof. The removal may create a multi-head (e.g., dual-head) epitaxial structure, together with the neck of the raised structure resembling a Y-shape. Raised structures that are not intended to include an epitaxial structure will be masked during epitaxial structure creation and modification. In addition, in order to have a uniform height, the filler material surrounding the raised structures is recessed around those to receive epitaxial structures.

LAYERED GaAs, METHOD OF PREPARING SAME, AND GaAs NANOSHEET EXFOLIATED FROM SAME

The present invention relates to: layered gallium arsenide (GaAs), which is more particularly layered GaAs, which, unlike the conventional bulk GaAs, has a two-dimensional crystal structure, has the ability to be easily exfoliated into nanosheets, and exhibits excellent electrical properties by having a structure that enables easy charge transport in the in-plane direction; a method of preparing the same; and a GaAs nanosheet exfoliated from the same.

Laser processing unit, laser processing method, and method for manufacturing semiconductor device

Objects of the present invention is to reduce a number of scanning a linear laser, to shorten the amount of time for laser annealing, and to reduce a manufacturing process, a manufacturing time, and manufacturing cost of a semiconductor device. In this invention, a gas at high temperature is locally blown so as to overlap at an irradiation surface of linear laser light. The linear laser light can be obtained by injecting laser light radiated from a laser oscillator into a lens. The gas at high temperature can be obtained by heating a gas which is compressed using a gas compressor, by a nozzle type heater. The heated has is sprayed so as to overlap with the irradiation surface of the linear laser light.

Semiconductor Devices With Modified Source/Drain Feature And Methods Thereof

A method includes providing a semiconductor structure including a fin protruding from a substrate, where the fin includes first semiconductor layers and second semiconductor layers, recessing the fin to form a source/drain (S/D) recess, forming an S/D feature in the S/D recess, trimming the S/D feature, depositing a dielectric layer to cover the S/D feature, forming a contact hole in the dielectric layer to expose the S/D feature, and forming a metal contact in the contact hole.

Co-integration of gate-all-around FET, FINFET and passive devices on bulk substrate

An apparatus that includes a substrate divided into a plurality of different regions, where the substrate remains physically together. A first device located in a first region of the plurality of different regions, where the first device has a first height. A second device located in a second region of the plurality of different regions. The second device has a second height and the second device is a different device from the first device. A third device located in a third region of the plurality of different regions. The third device has a third height and the third device is a different device from the first device and the second device. The second height is smaller than the first height.

3D SINGLE CRYSTAL SILICON NANO SHEETS INTEGRATED WITH 2D MATERIAL CHANNEL AND S/D DIODE ENHANCEMENT

Methods for the manufacture of semiconductor devices constructed with three-dimensional (3D) single crystal silicon nano sheets integrated with two-dimensional (2D) materials are disclosed. A device may include a semiconductor material and having a first end and a second end doped with a first polarity; a seed material wrapping around the semiconductor material; a two-dimensional (2D) material around the seed material; an active gate around the 2D material; and a source/drain structure in contact with the first end and the second end of the semiconductor material and in contact with the 2D material, wherein the source/drain structure is doped with a second polarity opposite to the first polarity.

DIRECT FORMATION OF HEXAGONAL BORON NITRIDE ON SILICON

A method of forming a multilayer structure, the method comprising: providing a silicon wafer, the silicon wafer comprising two major, generally parallel surfaces, one of which is a front surface of the silicon wafer and the other of which is a back surface of the silicon wafer, a circumferential edge joining the front and back surfaces of the silicon wafer, a central plane between the front surface and the back surface of the silicon wafer, and a bulk region between the front and back surfaces of the silicon wafer, contacting the front surface of the silicon wafer with (i) a boron-containing gas or a boron-containing vapor and (ii) a nitrogen-containing gas or a nitrogen-containing vapor at a temperature sufficient to directly deposit a layer comprising hexagonal boron nitride in interfacial contact with the front surface of the silicon wafer, and after the direct deposition of the hexagonal boron nitride layer, forming a metal film on the layer comprising hexagonal boron nitride, wherein ...

III-V compound semiconductor quantum dot production

In the production of quantum dots of III-V compound semiconductor in the Stranski-Krastanow growth mode by MOCVD, the novelty is that, after epitaxy of the quantum dots during growth interruption by switching off the group III component, the group V component process gas is also switched off. Preferably, the quantum dots consist of two InxGa1-xAs layers, the first having an In concentration (x) of 0.3-1.0 and the second having the same or lower In concentration, and, after deposition of the second layer, a second growth interruption is provided before epitaxy of further cover layers.

A low temperture method for the production of polycrystalline silicon, aligned silicon columns and silicon nanowires

A method of making a graphene transistor and devices

Method for producing a doped graphene transistor, comprising; i) providing a substrate on a heated susceptor in a reaction chamber, the chamber having a plurality of cooled inlets arranged so that, in use, the inlets are distributed across the substrate and have a constant separation from the substrate; ii) supplying a flow comprising a precursor compound through the inlets and into the reaction chamber to thereby decompose the precursor compound and form a plurality of graphene layers on the substrate, wherein the inlets are cooled to less than 100°C and the susceptor is heated to a temperature of at least 50°C in excess of a decomposition temperature of the precursor, wherein the flow comprising the precursor compound comprises a source of an N-type dopant or a source of P-type dopant; and iii) selectively counter-doping a portion of the graphene on the substrate with a dopant of an opposite type to the dopant present in the flow comprising the precursor compound. Second and third aspects ...

A low temperture method for the production of polycrystalline silicon, aligned silicon columns and silicon nanowires

Electrochemical method for the direct nanostructured deposition of material onto a substrate, and semiconductor component produced according to said method

Insulating gate-type silicon carbide semiconductor device and method for manufacturing same

MIXED OXIDES AND SULPHIDES OF BISMUTH AND COPPER PHOTOVOLTAIC

METHOD OF SELECTIVE GROWTH ON A SEMICONDUCTOR STRUCTURE

SUPPORT FOR A SEMICONDUCTOR STRUCTURE

PARTICLE AND METHOD FOR MANUFACTURING SAME

The present application relates to a method for manufacturing particles and the particles manufactured thereby, the manufacturing method comprising the following steps: inserting an auxiliary body into a receiving groove on a first substrate which allows for a first surface of the auxiliary body to be received by the receiving groove and a second surface of the auxiliary body to be exposed to the outside; forming a first coating layer on the second surface; attaching a second substrate to the auxiliary body which is provided with the first coating layer; separating the first substrate from the auxiliary body which is provided with the first coating layer and is attached to the second substrate, and exposing to the outside the first surface of the auxiliary body which is provided with the first coating layer; forming a second coating layer on the first surface; and separating the second substrate from auxiliary body which is provided with the first coating layer and the second coating layer ...

Method for processing oxide semiconductor layer

A method for processing an oxide semiconductor containing indium, gallium, and zinc is provided. In the method, the oxide semiconductor layer comprises a plurity of excess oxygen, a first oxygen vacancy that is close to first indium and captures first hydrogen, and a second oxygen vacancy that is close to second indium and captures second hydrogen, the first hydrogen captured by the first oxygen vacancy is bonded to one of a plurality of excess oxygen to so that a hydroxyl is formed; the hydroxyl is bonded to the second hydrogen captured by the second oxygen vacancy to release as water; and then, the first oxygen vacancy captures one of excess oxygen and the second oxygen vacancy captures one of excess oxygen.

HIGH RATE ELECTRIC FIELD DRIVEN NANOELEMENT ASSEMBLY ON AN INSULATED SURFACE

A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.

LARGE-AREA, FREE-STANDING METAL OXIDE FILMS AND TRANSISTORS MADE THEREFROM

The present invention provides continuous, free-standing metal oxide films and methods for making said films. The methods are able to produce large-area, flexible, thin films having one or more continuous, single-crystalline metal oxide domains. The methods include the steps of forming a surfactant monolayer at the surface of an aqueous solution, wherein the headgroups of the surfactant molecules provide a metal oxide film growth template. When metal ions in the aqueous solution are exposed to the metal oxide film growth template in the presence of hydroxide ions under suitable conditions, a continuous, free-standing metal oxide film can be grown from the film growth template downward into the aqueous solution.

Method for fabricating multiple thickness insulator layers

The present invention discloses a method for fabricating multiple-thickness insulator layers via strain field generated by stress. The strain field is used for alternating a develop mechanism of insulator layers on the quantum dots. By forming the multiple-thickness insulator layers at various developing rates, not only leakage current is prevented, but also components are kept isolated in the nano-electronics components. In nano-electronics manufacturing, the method for fabricating multiple-thickness insulator layers results in both better product reliability and the yield rate. It is potential for integral circuit manufacturing.

Methods of forming nanocrystals

Methods of selectively forming nanocrystals on semiconductor devices are disclosed. Regions of a workpiece are masked with a masking material, and the nanocrystals are formed on the unmasked regions. The nanocrystals may be formed by exposing the masked workpiece to a first substance, and exposing the workpiece to at least one second substance either before or after the masking material is removed.

Methods of forming nanocrystals

Methods of selectively forming nanocrystals on semiconductor devices are disclosed. Regions of a workpiece are masked with a masking material, and the nanocrystals are formed on the unmasked regions. The nanocrystals may be formed by exposing the masked workpiece to a first substance, and exposing the workpiece to at least one second substance either before or after the masking material is removed.

SYSTEMS AND METHODS FOR FABRICATING LONGITUDINALLY-SHAPED STRUCTURES

The present invention relates, in some aspects, to systems and methods for fabricating longitudinally-shaped structures such as nanobelt semiconductor structures. In some embodiments, the method comprises: a) providing a substrate selected to promote epitaxial growth thereon a selected growth orientation, b) depositing a crystalline sacrificial layer on the substrate for epitaxially growing along the selected growth orientation, c) forming a film over the sacrificial layer, the film having a crystal lattice structure grown substantially along the selected growth orientation, and d) removing at least part of the sacrificial layer, thereby producing the longitudinally shaped structures from the film by strain redistribution through the crystal lattice structure of the film to crack the film along a selected in-plane axis of the selected growth orientation.

FORMING NS GATES WITH IMPROVED MECHANICAL STABILITY

A semiconductor device includes a first gate stack disposed over an active region and a second gate stack disposed over a shallow trench isolation (STI) region such that the first gate stack is taller than the second gate stack. The second gate stack includes a plurality of gates formed over a non-active region. The nanosheet stacks in the active region include first inner spacers and second inner spacers. The first inner spacers are vertically aligned with the second inner spacers. Further, the first inner spacers directly contact lower sidewalls of a source/drain epitaxial region to isolate the second gate stack from the STI region.

Isolation Structures

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes receiving a fin-shaped structure comprising a first channel region and a second channel region, a first and a second dummy gate structures disposed over the first and the second channel regions, respectively. The method also includes removing a portion of the first dummy gate structure, a portion of the first channel region and a portion of the substrate under the first dummy gate structure to form a trench, forming a hybrid dielectric feature in the trench, removing a portion of the hybrid dielectric feature to form an air gap, sealing the air gap, and replacing the second dummy gate structure with a gate stack after sealing the air gap.

SOURCE/DRAIN REGIONS AND METHODS OF FORMING SAME

A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.

FORMING OF SEMICONDUCTOR FILM

PURPOSE: To obtain a semiconductor film without a heater or a control device by adhering semiconductor particles on a substrate by means of electrostatic force and dissolving the particles with the help of light or electronic beam. CONSTITUTION: An electricity is charged on the surface of an SiO2 substrate 1 having a matrix-shaped unevenness as a positive electric charge, using a corona electric discharging head C. Next, silicon powder is blown out of a nozzle N and silicon particles electrically charged as a negative electric charge are adhered on the substrate 1 at room temperature by means of electrostatic force. Following this process, silicon particles 2 are dissolved by scanning with high energy generated by a leaser beam, etc. to form a single crystal silicon film 4. To complete a substrate for a film semiconductor device, an impurity is introduced into a layer 4. In this fashion, it is possible to process a large quantity of semiconductor films and form the said film on a substrate ...

Способ выращивания в вертикальном реакторе многослойных наногетероэпитаксиальных структур с массивами идеальных квантовых точек

Изобретение относится к нанотехнологии, а именно к способу выращивания многослойных наногетероэпитаксиальных структур с массивами идеальных квантовых точек (НГЭС ИКТ). Способ основан на процессах растворения и кристаллизации полупроводниковых и металлических материалов из растворов-расплавов легкоплавких металлов. Способ выращивания в вертикальном реакторе многослойных наногетероэпитаксиальных структур с массивами идеальных квантовых точек методом жидкофазной эпитаксии в потоке водорода или форминг-газа включает нагрев емкостей с различными растворами кристаллизуемых материалов в расплавах легкоплавких металлов до температуры их насыщения и монокристаллической подложки до такой же температуры, при этом подложка плотно прикреплена тыльной поверхностью к нижнему основанию цилиндра за счет создания вакуума, последовательное приведение растворов-расплавов в контакт с лицевой поверхностью подложки при многократном переносе теплопоглотителем в виде пластины импульсов «холода» на тыльную поверхность ...

Amorphous and polycrystalline growing method for galllium nitride based compound semiconductor

Quantum dots for extended wavelength operation

A method of forming quantum dots having a ground state emission at a wavelength greater that 1350 nm at 273 K. First a layer of strained InAs quantum dots are formed on a GaAs based layer or substrate. A spacer layer is formed on these dots, the strain from the underlying dots extends to the surface of this layer. Then a layer of active of quantum dots is formed on the spacer layer, these tend to form on the strained areas of the spacer layer, aligning with the underlying dots. These dots are substantially strain relaxed, which increases their emission wavelength and gives a narrower emission spectrum. A capping layer is formed on the active layer to preserve the strain relaxed state. The active quantum dots are formed at a lower temperature that the first layer to minimise intermixing.

Method of manufacturing an electrically conductive or semiconductive structure and electronic device comprising the same

Mesoporous single crystal semiconductore

FIELD EFFECT SENSORS

Apparatus and methods are disclosed for single molecule field effect sensors having conductive channels functionalized with a single active moiety. A region of a nanostructure (e.g., such as a silicon nanowire or a carbon nanotube) provide the conductive channel. Trapped state density of the nanostructure is modified for a portion of the nanostructure in proximity with a location where the active moiety is linked to the nanostructure. In one example, the semiconductor device includes a source, a drain, a channel including a nanostructure having a modified portion with an increased trap state density, the modified portion being further functionalized with an active moiety. A gate terminal is in electrical communication with the nanostructure. As a varying electrical signal is applied to an ionic solution in contact with the nanostructure channel, changes in current observed from the semiconductor device can be used to identify composition of the analyte.

Thin film transistor

Method and device for forming silicon dot, and method and device for forming substrate with insulating film and silicon dot

A silicon dot is formed with good controllability of particle size and good reproducibility between substrates by suppressing generation or clustering of defects in the silicon dot, or plasma damage under a relatively low temperature. A silicon dot and an insulating film are formed with good controllability of silicon dot particle size and insulating film thickness, and good reproducibility between substrates under a relatively low temperature. A method and a device (1) for forming a silicon dot (method and device A for forming a silicon dot and a substrate with an insulating film), in which inductively coupled plasma is generated from gas for forming a silicon dot (gas for forming an insulating film) by a low inductance internal antenna 12(22), a silicon dot SiD (insulating film F) is formed on a substrate S under the inductively coupled plasma, and the substrate S is kept unexposed to an unstable plasma when plasma is in unstable state, but the substrate S is made to face a stabilized ...

OPTO-ELECTRIC DEVICE OR SEMICONDUCTOR NANOWIRES MICRO-WIRES AND METHOD OF MAKING SAME

METHOD FOR REALIZATION Of STACKINGS Of MATERIAL SEMI-CONDUCTEURENCAPSULES SMALL ISLANDS IN ANOTHER SEMICONDUCTOR MATERIAL

Manufacturing a semiconductor solar absorbing material of e.g. copper indium gallium selenide type, in a photovoltaic cell, comprises mixing metal elements, dry grinding the mixture, and suspending the powder in an organic solvent

Procédé de fabrication d'un matériau semi-conducteur absorbant le rayonnement solaire au sein d'une cellule photovoltaïque, ledit matériau comprenant du soufre ou du sélénium ou un mélange de soufre et de sélénium et au moins deux éléments métalliques choisis dans le groupe constitué par Cu, In, Ga, Zn, Sn, ledit procédé comprenant au moins les étapes de mélange desdits métaux élémentaires, de cobroyage à sec dudit mélange jusqu'à l'obtention d'alliages desdits métaux, de mise en suspension des particules d'alliage dans un solvant organique de type polyalcool dont la chaîne carbonée présente au moins 2 carbones, de dépôt de la suspension sur un support, d'élimination du solvant, et de sulfuration et/ou sélénisation de la couche de particules d'alliages par traitement thermique sous atmosphère de soufre et/ou de sélénium, jusqu'à l'obtention de la couche du matériau semi-conducteur.

SEMICONDUCTOR MATERIAL INCLUDING AREAS OF DIFFERENT CRYSTAL ORIENTATIONS AND METHOD FOR THE PRODUCTION THEREOF

L'invention concerne un procédé de fabrication d'un matériau semi-conducteur de nitrure d'élément III à partir d'un substrat de départ, le procédé comprenant : - la formation (500) une couche intermédiaire à base de silicium (30) sur un substrat de départ, ladite couche intermédiaire comportant au moins deux zones adjacentes d'orientations cristallines différentes (31, 32), notamment une zone monocristalline (32) et une zone amorphe ou poly-cristalline (31), - la croissance par épitaxie d'une couche de nitrure d'élément III sur ladite couche intermédiaire, la couche intermédiaire étant destinée à être vaporisée spontanément lors de l'étape consistant à faire croître par épitaxie la couche de nitrure d'élément III.

Method for forming silicon film having microcrystal structure

A method for forming a silicon film having a microcrystal structure is provided. The method includes following steps. A plasma-enhanced chemical vapor deposition system having a reaction chamber, a top electrode and a bottom electrode is provided. The top electrode and the bottom electrode are opposite and disposed in the reaction chamber. A substrate is disposed on the bottom electrode. A silane gas is applied into the reaction chamber. A silicon film having a microcrystal structure is formed by simultaneously irradiating the silane gas in the reaction chamber by a carbon dioxide laser and performing a plasma-enhanced chemical vapor deposition step.

Semiconductor device and manufacturing method thereof

A semiconductor device having high operating performance and reliability, and a manufacturing method thereof are provided. An LDD region 207 provided in an n-channel TFT 302 forming a driving circuit enhances the tolerance for hot carrier injection. LDD regions 217 - 220 provided in an n-channel TFT (pixel TFT) 304 forming a pixel portion greatly contribute to the decrease in the OFF current value. Here, the LDD region of the n-channel TFT of the driving circuit is formed such that the concentration of the n-type impurity element becomes higher as the distance from an adjoining drain region decreases.

Semiconductor film, semiconductor element, semiconductor device, and method for manufacturing the same

One of objects is to provide a semiconductor film having stable characteristics. Further, one of objects is to provide a semiconductor element having stable characteristics. Further, one of objects is to provide a semiconductor device having stable characteristics. Specifically, a structure which includes a seed crystal layer (seed layer) including crystals each having a first crystal structure, one of surfaces of which is in contact with an insulating surface, and an oxide semiconductor film including crystals growing anisotropically, which is on the other surface of the seed crystal layer (seed layer) may be provided. With such a heterostructure, electric characteristics of the semiconductor film can be stabilized.

Trap Rich Layer for Semiconductor Devices

An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

Method of Fabricating Silicon Quantum Dot Layer and Device Manufactured Using the Same

Disclosed are a method of fabricating a silicon quantum dot layer and a device manufactured using the same. A first capping layer is formed on a substrate, and a silicon-containing precursor layer is formed on the first capping layer. A second capping layer is formed on the silicon-containing precursor layer. The first capping layer, the silicon-containing precursor layer, and the second capping layer are irradiated to convert the silicon-containing precursor layer into a stack including a first poly-crystalline silicon layer, a silicon quantum dot layer on the first poly-crystalline silicon layer, and a second poly-crystalline silicon layer on the silicon quantum dot layer.

Hybrid Silicon Wafer

A hybrid silicon wafer which is a silicon wafer having a structure wherein monocrystalline silicon is embedded in polycrystalline silicon that is prepared by the unidirectional solidification/melting method. The longitudinal plane of crystal grains of the polycrystalline portion prepared by the unidirectional solidification/melting method is used as the wafer plane, and the monocrystalline silicon is embedded so that the longitudinal direction of the crystal grains of the polycrystalline portion forms an angle of 120° to 150° relative to the cleaved surface of the monocrystalline silicon. Thus provided is a hybrid silicon wafer comprising the functions of both a polycrystalline silicon wafer and a monocrystalline wafer.

Semiconductor device and method for manufacturing same

A method for fabricating a semiconductor device according to the present invention includes the steps of: (a) providing a substrate ( 11 a ) in a chamber ( 26 ); (b) supplying a microwave into the chamber ( 26 ) through a dielectric plate ( 24 ), of which one surface that faces the chamber is made of alumina, thereby depositing a microcrystalline silicon film ( 14 ) with an aluminum concentration of 1.0×10 16 atoms/cm 3 or less on the substrate ( 11 a ) by high-density plasma CVD process; and (c) making a thin-film transistor that uses the microcrystalline silicon film as its active layer. As a result, a semiconductor device including a TFT that uses a microcrystalline silicon film with a mobility of more than 0.5 cm 2 /Vs as its active layer is obtained.

Device and method for forming low-temperature polysilicon film

Provided is a forming device and method making it possible to obtain a low-temperature polysilicon film in which the size of crystal grains fluctuates minimally, and is uniform. A mask has laser-light-blocking areas and laser-light-transmission areas arranged in the form of a grid such that the light-blocking areas and transmission areas are not adjacent to one another. Laser light is directed by the microlenses through the masks to planned channel-area-formation areas. The laser light transmitted by the transmission areas is directed onto an a-Si:H film, annealing and polycrystallzing the irradiated parts thereof. The mask is then removed, and when the entire planned channel-area-formation area is irradiated with laser light, the already-polycrystallized area, having a higher melting point, does not melt, while the area in an amorphous state melts and solidifies, leading to polycrystallization. The grain size of the polysilicon film obtained is regulated by the light-blocking areas and transmission areas and is thus controlled to a predetermined range.

Method of manufacturing semiconductor device

A highly reliable transistor which includes an oxide semiconductor and has high field-effect mobility and in which a variation in threshold voltage is small is provided. By using the transistor, a high-performance semiconductor device, which has been difficult to realize, is provided. The transistor includes an oxide semiconductor film which contains two or more kinds, preferably three or more kinds of elements selected from indium, tin, zinc, and aluminum. The oxide semiconductor film is formed in a state where a substrate is heated. Further, oxygen is supplied to the oxide semiconductor film with an adjacent insulating film and/or by ion implantation in a manufacturing process of the transistor, so that oxygen deficiency which generates a carrier is reduced as much as possible. In addition, the oxide semiconductor film is highly purified in the manufacturing process of the transistor, so that the concentration of hydrogen is made extremely low.

Amorphous oxide thin film, thin film transistor using the same, and method for manufacturing the same

A thin film transistor using an amorphous oxide thin film for an active layer, wherein: the amorphous oxide thin film includes, as main components, indium (In), oxygen (O), and a metal element (M) selected from the group consisting of silicon (Si), aluminum (Al), germanium (Ge), tantalum (Ta), magnesium (Mg) and titanium (Ti); an atomic ratio of M to In in this amorphous oxide thin film is 0.1 or more and 0.4 or less; and carrier density in the amorphous oxide thin film is 1×10 15 cm −3 or more and 1×10 19 cm −1 or less.

Plasma Deposition of Amorphous Semiconductors at Microwave Frequencies

Apparatus and method for plasma deposition of thin film photovoltaic materials at microwave frequencies. The apparatus avoids deposition on windows that couple microwave energy to deposition species. The apparatus includes a microwave applicator with one or more conduits that carry deposition species. The applicator transfers microwave energy to the deposition species to energize them to a reactive state. The conduits physically isolate deposition species that would react or otherwise combine to form a thin film material at the point of microwave power transfer and deliver the microwave-excited species to a deposition chamber. Supplemental material streams may be delivered to the deposition chamber without passing through the microwave applicator and may combine with deposition species exiting the conduits to form a thin film material. Precursors for the microwave-excited deposition species include fluorinated forms of silicon. Precursors for supplemental material streams include hydrogenated forms of silicon.

Deposition methods for the formation of iii/v semiconductor materials, and related structures

Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.

Ge QUANTUM DOTS FOR DISLOCATION ENGINEERING OF III-N ON SILICON

A virtual substrate structure includes a crystalline silicon substrate with a first layer of III-N grown on the silicon substrate. Ge clusters or quantum dots are grown on the first layer of III-N and a second layer of III-N is grown on the Ge clusters or quantum dots and any portions of the first layer of III-N exposed between the Ge clusters or quantum dots. Additional alternating Ge clusters or quantum dots and layers of III-N are grown on the second layer of III-N forming an upper surface of III-N. Generally, the additional alternating layers of Ge clusters or quantum dots and layers of III-N are continued until dislocations in the III-N adjacent the upper surface are substantially eliminated.

Method for forming nanocrystalline silicon film

Provided is a method for forming a nanocrystalline silicon film that can be deposited on a substrate while maintaining a high degree of crystallinity at low temperatures. The method includes performing plasma treatment on a substrate, and forming a nanocrystalline silicon film by depositing the nanocrystalline silicon film on the substrate.

Method of forming silicon oxide film

A method of forming a silicon oxide film includes forming a seed layer on a base, forming a silicon film on the seed layer, and forming the silicon oxide film on the base by oxidizing the silicon film and the seed layer.

STABLE AMORPHOUS METAL OXIDE SEMICONDUCTOR

A thin film semiconductor device has a semiconductor layer including a mixture of an amorphous semiconductor ionic metal oxide and an amorphous insulating covalent metal oxide. A pair of terminals is positioned in communication with the semiconductor layer and define a conductive channel, and a gate terminal is positioned in communication with the conductive channel and further positioned to control conduction of the channel. The invention further includes a method of depositing the mixture including using nitrogen during the deposition process to control the carrier concentration in the resulting semiconductor layer. 121-. (canceled)22. A method of forming a layer of stable amorphous metal oxide material for use as a semiconductor in semiconductor devices , the method comprising the steps of:depositing a mixture of an amorphous semiconductor ionic metal oxide and an amorphous insulating covalent metal oxide on a substrate; andcontrolling carrier concentration of the mixture using one of oxygen and nitrogen during the deposition.23. A method as claimed in wherein the step of depositing includes depositing a greater amount of the amorphous semiconductor ionic metal oxide than the amount of amorphous insulating covalent metal oxide.24. A method as claimed in wherein the step of depositing an amorphous semiconductor ionic metal oxide includes depositing an amount greater than approximately 17% of the mixture.25. A method as claimed in wherein the step of depositing includes depositing an amount of amorphous insulating covalent metal oxide sufficient to prevent the amorphous semiconductor ionic metal oxide from becoming poly crystalline at high temperatures.26. A method as claimed in wherein the step of depositing includes depositing an amount of amorphous insulating covalent metal oxide sufficient to prevent the amorphous semiconductor ionic metal oxide from becoming poly crystalline at temperatures in a range of approximately 250° C. to approximately 700° C.27. A ...

PRODUCTION OF AN INTEGRATED CIRCUIT INCLUDING ELECTRICAL CONTACT ON SiC

Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on an SiC substrate.

GALLIUM NITRIDE BASED STRUCTURES WITH EMBEDDED VOIDS AND METHODS FOR THEIR FABRICATION

A gallium nitride-based structure includes a substrate, a first layer of gallium nitride disposed on a growth surface of the substrate, and a second gallium nitride layer disposed on the first gallium nitride layer. The first layer includes a region in which a plurality of voids is dispersed. The second layer has a lower defect density than the gallium nitride of the interfacial region. The gallium nitride-based structure is fabricated by depositing GaN on the growth surface to form the first layer, forming a plurality of gallium nitride nanowires by removing gallium nitride from the first layer, and growing additional GaN from facets of the nanowires. Gallium nitride crystals growing from neighboring facets coalesce to form a continuous second layer, below which the voids are dispersed in the first layer. The voids serve as sinks or traps for crystallographic defects, and also as expansion joints that ameliorate thermal mismatch between the Ga.N and the underlying substrate. The voids also provide improved light transmission properties in optoelectronic applications. 1. A gallium nitride-based structure , comprising:a substrate comprising a growth surface;a first layer of gallium nitride disposed on the growth surface, the first gallium nitride layer comprising an interfacial region proximate to the growth surface and a plurality of voids dispersed in the interfacial region; anda second gallium nitride layer disposed on the first gallium nitride layer and having a defect density lower than a defect density of the gallium nitride of the interfacial region.23.-. (canceled)4. The gallium nitride-based structure of claim 1 , comprising a buffer layer disposed on the growth surface claim 1 , wherein the first gallium nitride layer is disposed on the buffer layer.5. The gallium nitride-based structure of claim 4 , wherein the buffer layer has a composition selected from the group consisting of aluminum nitride and gallium nitride.6. (canceled)7. The gallium nitride-based ...

Method of forming a laminated semiconductor film

According to some embodiments of the present disclosures, a method of forming a laminated semiconductor film is constituted by alternately laminating first and second semiconductor films on an underlying film of each of a plurality of substrates to be processed. The method includes performing a first operation of forming the first semiconductor film and a second operation of forming the second semiconductor film until a predetermined number of laminated films are obtained. In the method, a film forming temperature in the first operation and a film forming temperature in the second operation are set to be equal to each other, and temperatures between the first and second operations are set to be constant.

Manufacturing method of semiconductor device

It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.

UNIT FOR LIQUID PHASE EPITAXIAL GROWTH OF MONOCRYSTALLINE SILICON CARBIDE, AND METHOD FOR LIQUID PHASE EPITAXIAL GROWTH OF MONOCRYSTALLINE SILICON CARBIDE

The cost of liquid phase epitaxial growth of a monocrystalline silicon carbide is reduced. A feed material is such that when a surface layer thereof containing a polycrystalline silicon carbide with a 3C crystal polymorph is subjected to X-ray diffraction, a diffraction peak corresponding to a (111) crystal plane and a diffraction peak other than the diffraction peak corresponding to the (111) crystal plane are observed as diffraction peaks corresponding to the polycrystalline silicon carbide with a 3C crystal polymorph. A seed material is such that when a surface layer thereof containing a polycrystalline silicon carbide with a 3C crystal polymorph is subjected to X-ray diffraction, a first-order diffraction peak corresponding to a (111) crystal plane is observed as a diffraction peak corresponding to the polycrystalline silicon carbide with a 3C crystal polymorph but no other first-order diffraction peak having a diffraction intensity of 10% or more of the diffraction intensity of the first-order diffraction peak corresponding to the (111) crystal plane is observed. 1. A unit for liquid phase epitaxial growth of a monocrystalline silicon carbide , the unit being used in a method for liquid phase epitaxial growth of a monocrystalline silicon carbide and including a seed material and a feed material , whereinthe feed material includes a surface layer containing a polycrystalline silicon carbide with a 3C crystal polymorph and is such that upon X-ray diffraction of the surface layer a diffraction peak corresponding to a (111) crystal plane and a diffraction peak other than the diffraction peak corresponding to the (111) crystal plane are observed as diffraction peaks corresponding to the polycrystalline silicon carbide with a 3C crystal polymorph, andthe seed material includes a surface layer containing a polycrystalline silicon carbide with a 3C crystal polymorph and is such that upon X-ray diffraction of the surface layer a first-order diffraction peak ...

PASSIVATION OF SILICON SURFACES USING INTERMEDIATE ULTRA-THIN SILICON OXIDE LAYER AND OUTER PASSIVATING DIELECTRIC LAYER

Methods, structures and devices are provided in which a crystalline silicon surface is passivated by an ultra-thin silicon oxide layer and an outer passivating dielectric layer, where the ultra-thin silicon oxide layer has a thickness on an Angstrom scale. In some embodiments, both layers are formed by low temperature processes. The outer passivating layer may be formed according to a PECVD process that employs hydrogen-containing precursor gases, such that hydrogen is incorporated into one or both of the silicon oxide layer and the passivating dielectric layer. The present methods may be employed for the passivation of a wide variety of structures and devices, including photovoltaic cells, MOSFET devices, flash memory devices, and thin-film silicon substrates that may contain such devices. 1. A method of passivating a crystalline silicon surface , the method comprising:cleaning the silicon surface and removing a pre-existing native oxide layer;performing a low temperature oxide growth process to form an ultra-thin silicon oxide layer on the silicon surface; andperforming a low temperature depositing process to deposit a passivating dielectric layer on the ultra-thin silicon oxide layer.2. The method according to wherein the ultra-thin silicon oxide layer has a thickness less than approximately 100 Angstroms.3. The method according to wherein the ultra-thin silicon oxide layer has a thickness less than approximately 15 Angstroms.4. The method according to wherein the ultra-thin silicon oxide layer has a thickness less than approximately 10 Angstroms.5. The method according to wherein the low temperature depositing process and the low temperature oxide growth process are performed at temperatures below approximately 500 degrees Celsius.6. The method according to wherein the low temperature oxide growth process is performed under ambient conditions such that the ultra-thin silicon oxide layer is a native oxide layer.7. The method according to wherein the native oxide ...

Sonos ono stack scaling

A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.

HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS

Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. An interfacial intrinsic non-crystalline semiconductor material layer is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. The presence of the interfacial intrinsic non-crystalline semiconductor material layer improves the surface passivation of the crystalline semiconductor material by reducing the interface defect density at the heterojunction. 1. A heterojunction bipolar transistor comprising:a crystalline semiconductor material; andat least one contact in direct physical contact with a surface portion of the crystalline semiconductor material, wherein said at least one contact comprises an interfacial intrinsic non-crystalline semiconductor material in direct contact with the surface portion of the crystalline semiconductor material and a doped non-crystalline semiconductor material located on a surface of the interfacial intrinsic non-crystalline semiconductor material.2. The heterojunction bipolar transistor of claim 1 , wherein said interfacial intrinsic non-crystalline semiconductor material is hydrogenated claim 1 , and said doped non-crystalline semiconductor material is hydrogenated.3. The heterojunction bipolar transistor of claim 1 , wherein said interfacial intrinsic non-crystalline semiconductor material is hydrogenated claim 1 , and said doped non-crystalline semiconductor material is non-hydrogenated.4. The heterojunction bipolar transistor of claim 1 , wherein said interfacial intrinsic non-crystalline semiconductor material is non-hydrogenated claim 1 , and said doped non-crystalline semiconductor material is hydrogenated.5. The heterojunction bipolar transistor of claim 1 , wherein said interfacial intrinsic non- ...

HETEROJUNCTION BIPOLAR TRANSISTORS WITH THIN EPITAXIAL CONTACTS

Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, and/or emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. A highly doped epitaxial semiconductor layer comprising a highly doped hydrogenated crystalline semiconductor material layer portion is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. Minority carriers within the highly doped epitaxial semiconductor layer have a diffusion length that is larger than a thickness of the highly doped epitaxial semiconductor layer. 1. A heterojunction bipolar transistor comprising:a crystalline semiconductor material; andat least one contact in direct physical contact with a surface portion of the crystalline semiconductor material, wherein said at least one contact comprises a doped hydrogenated crystalline semiconductor material layer portion in direct contact with the surface portion of the crystalline semiconductor material, and a doped non-crystalline semiconductor material located on a surface of the doped hydrogenated crystalline semiconductor material layer portion.2. The heterojunction bipolar transistor of claim 1 , wherein said doped non-crystalline semiconductor material is hydrogenated.3. The heterojunction bipolar transistor of claim 1 , wherein said doped non-crystalline semiconductor material is non-hydrogenated.4. The heterojunction bipolar transistor of claim 1 , further comprising another doped non-crystalline semiconductor material located on a surface of said doped non-crystalline semiconductor material claim 1 , wherein said another doped non-crystalline semiconductor material has a lower band gap than the doped non-crystalline semiconductor material.5. The heterojunction bipolar transistor of claim 1 , wherein said doped non-crystalline semiconductor material comprises a ...

Method of forming thin film poly silicon layer

A method of forming a thin film poly silicon layer includes following steps. Firstly, a substrate is provided. The substrate has a first surface. A heating treatment is then performed. A thin film poly silicon layer is then directly formed on the first surface of the substrate by a silicon thin film deposition process.

High voltage three-dimensional devices having dielectric liners

High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric composed of a first dielectric layer disposed on the first fin active region, and a second, different, dielectric layer disposed on the first dielectric layer. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric composed of the second dielectric layer disposed on the second fin active region.

LASER IRRADIATION METHOD, LASER IRRADIATION APPARATUS, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

In the present invention, each laser light emitted from a plurality of lasers is divided, and laser light including at least one laser light that is emitted from a different laser and that has different energy distribution is synthesized with another such laser light, or laser light including at least one laser light that has different energy distribution is synthesized with another such laser light through a convex lens that is set at an angle to the direction each laser light travels, to form laser light having excellent uniformity in energy distribution. 1. (canceled)2. A method of manufacturing a semiconductor device comprising the steps of:forming an amorphous semiconductor film over a substrate;emitting a first laser beam from a first laser;dividing the first laser beam into at least two divided first laser beams;emitting a second laser beam from a second laser;dividing the second laser beam into at least two divided second laser beams;synthesizing one of the at least two divided first laser beams and one of the at least two divided second laser beams to form a synthesized laser beam; andirradiating the amorphous semiconductor film with the synthesized laser beam to crystallize the amorphous semiconductor film;patterning the crystallized semiconductor film to form a semiconductor layer including a channel formation region of a thin film transistor.3. The method according to claim 2 , wherein the amorphous semiconductor film comprises silicon.4. The method according to claim 2 , wherein each of the first laser beam and the second laser beam is selected from the group consisting of a continuous wave or pulse oscillation YAG laser claim 2 , YVOlaser claim 2 , YLF laser claim 2 , YAlOlaser claim 2 , YOlaser claim 2 , glass laser claim 2 , ruby laser claim 2 , alexandrite laser claim 2 , and Ti:sapphire laser.5. The method according to claim 2 , wherein each of the first laser beam and the second laser beam is selected from the group consisting of an Ar laser claim ...

FORMATION METHOD OF OXIDE SEMICONDUCTOR FILM

An oxide semiconductor film with high crystallinity is formed. An ion is made to collide with a sputtering target including a polycrystalline oxide containing a plurality of crystal grains to separate parts of the plurality of crystal grains and obtain flat plate-like sputtered particles, and the flat plate-like sputtered particles are deposited on a substrate having an insulating surface, which is heated at a temperature higher than 400° C. and lower than or equal to 500° C., to form an oxide semiconductor film including a crystal part over the substrate. Since the substrate which is a deposition surface is heated at a high temperature, the flat plate-like sputtered particles are rearranged and thus the oxide semiconductor film has a high film density. 1. A method for forming an oxide semiconductor film , comprising the steps of:making an ion collide with a sputtering target including a polycrystalline oxide containing crystal grains to separate parts of the crystal grains and obtain flat plate-like sputtered particles; anddepositing the flat plate-like sputtered particles on a substrate having an insulating surface, which is heated at a temperature higher than 400° C. and lower than or equal to 500° C. to form an oxide semiconductor film including a crystal part over the substrate,wherein a diameter of a plane of the sputtered particle which is parallel to an a-b plane of a crystal is greater than or equal to 3 nm and less than or equal to 10 nm.2. The method for forming an oxide semiconductor film according to claim 1 ,wherein the polycrystalline oxide comprises indium, zinc, and a metal other than indium and zinc.3. The method for forming an oxide semiconductor film according to claim 2 ,wherein the metal other than indium and zinc is gallium.4. The method for forming an oxide semiconductor film according to claim 1 ,wherein c-axes of crystals of the deposited sputtered particles are aligned in a direction perpendicular to a deposition surface of the substrate.5 ...

Optoelectric Integrated Circuit

A semiconductor device includes a substrate supporting a plurality of layers that include at least one modulation doped quantum well (QW) structure offset from a quantum dot in quantum well (QD-in-QW) structure. The modulation doped QW structure includes a charge sheet spaced from at least one QW by a spacer layer. The QD-in-QW structure has QDs embedded in one or more QWs. The QD-in-QW structure can include at least one template/emission substructure pair separated by a barrier layer, the template substructure having smaller size QDs than the emission substructure. A plurality of QD-in-QW structures can be provided to support the processing (emission, absorption, amplification) of electromagnetic radiation of different characteristic wavelengths (such as optical wavelengths in range from 1300 nm to 1550 nm). The device can realize an integrated circuit including a wide variety of devices that process electromagnetic radiation at a characteristic wavelength(s) supported by the QDs of the QD-in-QW structure(s). Other semiconductor devices are also described and claimed.

THIN FILM SEMICONDUCTOR DEVICE COMPRISING A POLYCRYSTALLINE SEMICONDUCTOR LAYER FORMED ON AN INSULATION LAYER HAVING DIFFERENT THICKNESS

In an organic light emitting diode (OLED) display and a manufacturing method thereof, the OLED display includes a substrate main body; an insulation layer pattern formed on the substrate main body, and including a first thickness layer and a second thickness layer thinner than the first thickness layer; a metal catalyst that is scattered on the first thickness layer of the insulation layer pattern; and a polycrystalline semiconductor layer formed on the insulation layer pattern, and divided into a first crystal area corresponding to the first thickness layer and to a portion of the second thickness layer adjacent to the first thickness layer and a second crystal area corresponding to the remaining part of the second thickness layer. The first crystal area of the polycrystalline semiconductor layer is crystallized through the metal catalyst, and the second crystal area of the polycrystalline semiconductor layer is solid phase crystallized. 1. A method for manufacturing an organic light emitting diode (OLED) display , comprising:providing a substrate main body;forming an insulation layer on the substrate main body;scattering a metal catalyst on the insulation layer;forming an insulation layer pattern including a first thickness layer and a second thickness layer that is thinner than the first thickness layer by patterning the insulation layer on which the metal catalyst is scattered through a photolithography process;forming an amorphous silicon layer on the insulation layer pattern; andforming a polycrystalline semiconductor layer that is divided into a first crystal area that is crystallized through the metal catalyst by crystallizing the amorphous silicon layer and a second crystal area that is formed through solid phase crystallization (SPC).2. The method of claim 1 , wherein the metal catalyst includes at least one of nickel (Ni) claim 1 , palladium (Pd) claim 1 , titanium (Ti) claim 1 , silver (Ag) claim 1 , gold (Au) claim 1 , tin (Sn) claim 1 , antimony (Sb) ...

Semiconductive micro- and nano-wire array manufacturing

The disclosure provides methods of manufacturing semiconductive structures using stamping and VLS techniques.

METHOD FOR FORMING LOW TEMPERATURE POLYSILICON THIN FILM

Embodiments of the present invention provide a method for forming a low temperature polysilicon thin film. The method for forming the low temperature polysilicon thin film can comprise: depositing a buffer layer and an amorphous silicon layer on a substrate in this order; heating the amorphous silicon layer; performing an excimer laser annealing process on the amorphous silicon layer to form a polysilicon layer; oxidizing partially the polysilicon layer so as to form an oxidation portion at an upper portion of the polysilicon layer; and removing the oxidation portion of the polysilicon layer to form a polysilicon thin film. 1. A method for forming a low temperature polysilicon thin film comprising:depositing a buffer layer and an amorphous silicon layer sequentially on a substrate;heating the amorphous silicon layer;performing an excimer laser annealing process on the amorphous silicon layer to form a polysilicon layer;oxidizing partially the polysilicon layer so as to form an oxidation portion at an upper portion of the polysilicon layer; andremoving the oxidation portion of the polysilicon layer to form a polysilicon thin film.2. The method for forming the low temperature polysilicon thin film according to claim 1 , wherein depositing the buffer layer comprises depositing a silicon nitride layer having a thickness from 50 to 150 nm and a silicon dioxide layer having a thickness from 100 nm to 350 nm sequentially.3. The method for forming the low temperature polysilicon thin film according to claim 1 , wherein the amorphous silicon layer has a thickness from 30 to 100 nm.4. The method for forming the low temperature polysilicon thin film according to claim 1 , wherein heating the amorphous silicon layer comprises heating the amorphous silicon layer at a temperature from 400 to 500° C. for 0.5 to 3 hours.5. The method for forming the low temperature polysilicon thin film according to claim 1 , wherein performing the excimer laser annealing (ELA) process on the ...

PROCESS FOR PRODUCING A POLYCRYSTALLINE LAYER

A process is provided for producing a polycrystalline layer. This process includes the steps of: applying to a substrate a layer sequence comprising at least one amorphous starting layer provided with impurities, a metallic activator layer, and a cleaning layer based on titanium or titanium oxide arranged between the starting layer and the activator layer for withdrawing the impurities from the starting layer; and carrying out a heat treatment after the layer sequence has been applied for forming a polycrystalline end layer. 113.-. (canceled)14. A process for producing a polycrystalline layer , the process comprising the steps of:applying to a substrate a layer sequence comprising at least: a metallic activator layer, and', 'a cleaning layer based on titanium or titanium oxide arranged between the starting', 'layer and the activator layer and serving for withdrawing the impurities from the starting layer; and, 'an amorphous starting layer provided with impurities,'}carrying out a thermal treatment after applying the layer sequence to form a polycrystalline end layer.15. The process as claimed in claim 14 , wherein the impurities are boron impurities.16. The process as claimed in claim 14 , wherein the amorphous starting layer is applied by physical vapor deposition (PVD).17. The process as claimed in claim 14 , wherein the cleaning layer has a layer thickness in a range of between 2 nm and 10 nm.18. The process as claimed in claim 17 , wherein the cleaning layer has a layer thickness in a range of between 2 nm and 4 nm.19. The process as claimed claim 14 , wherein the thermal treatment takes place at a temperature in a range of between 600° C. and 800° C.20. The process as claimed in claim 14 , wherein the substrate is single-pane safety glass.21. The process as claimed in claim 14 , wherein the amorphous starting layer comprises at least one semiconductor material.22. The process as claimed in claim 21 , wherein the at least one semiconductor material comprises at ...

METHOD FOR FABRICATING WELL-ALIGNED ZINC OXIDE MICRORODS AND NANORODS AND APPLICATION THEREOF

The present invention relates to a method for fabricating well-aligned zinc oxide microrods and nanorods and application thereof and particularly relates to a method for fabricating well-aligned zinc oxide microrods and nanorods on a general substrate by hydrothermal method and application thereof. 1. A method for fabricating well-aligned zinc oxide microrods/nanorods , comprising:(1) providing a substrate;(2) forming a zinc oxide thin film on said substrate;(3) baking said zinc oxide thin film with temperature control;(4) forming a suppressing layer on said zinc oxide thin film, and then, annealing said zinc oxide thin film and said substrate with high temperature;(5) removing said suppressing layer after annealing; and(6) forming zinc oxide microrods/nanorods on said zinc oxide thin film by hydrothermal method.2. The method of claim 1 , wherein said substrate is a metal substrate claim 1 , a silicon substrate claim 1 , a quartz substrate claim 1 , a glass substrate claim 1 , a sapphire substrate claim 1 , or a flexible plastic substrate.3. The method of claim 1 , wherein in said step (2) claim 1 , said zinc oxide thin film is formed by sol-gel method.4. The method of claim 3 , wherein a chemical solution used in said sol-gel method is a mixed solution composed of monoethanolamine claim 3 , zinc acetate claim 3 , and ethylene glycol monoethyl ether claim 3 , or a mixed solution which can precipitate zinc oxide by chemical reactions.5. The method of claim 4 , wherein said chemical solution is coated on said substrate by spin coating.6. The method of claim 1 , wherein said step (3) is performed to flatten surfaces of said zinc oxide thin film for preventing generation of wrinkles or grains on said zinc oxide thin film.7. The method of claim 1 , wherein said temperature control in said step (3) is performed at 100° C. to 300° C.8. The method of claim 1 , wherein speed of temperature variation of said temperature control in said step (3) is at a range of 5° C. per ...

METHOD FOR MANUFACTURING FINFET

Designs and fabrication of a FinFET are provided. In one implementation, the fabrication can include forming a dielectric stripe on a substrate; implanting ions to the substrate by using the dielectric stripe as a mask so as to convert a surface layer of the substrate to an amorphous layer; forming an amorphous semiconductor layer on the substrate covering the dielectric stripe and recrystallizing each of the amorphous layer and the amorphous semiconductor layer to be a monocrystalline layer; processing regions beside two ends of the dielectric stripe to form a protective layer, the regions being predesigned as source and drain regions; forming recrystallized semiconductor spacers at two sides of the dielectric stripe uncovered by the protective layer, and forming recrystallized semiconductor blocks on regions covered by the protective layer; removing the dielectric stripe between the spacers so that the spacers can be formed as Fin bodies. 1. A method for manufacturing a FinFET , comprising:forming a dielectric stripe on a substrate;implanting ions to the substrate by using the dielectric stripe as a mask so as to convert a surface layer of the substrate from a monocrystalline material to an amorphous layer;forming an amorphous semiconductor layer on the substrate, which covers the dielectric stripe, and then recrystallizing each of the amorphous layer and the amorphous semiconductor layer to be a monocrystalline layer by thermal annealing;processing regions beside two ends of the dielectric stripe to form a protective layer, the regions being predesigned as source and drain regions;forming recrystallized semiconductor spacers at two sides of the dielectric stripe uncovered by the protective layer, and forming recrystallized semiconductor blocks on regions covered by the protective layer;removing the dielectric stripe between the spacers so that the spacers can be formed as Fin bodies, the semiconductor blocks being support blocks on two sides of the Fin bodies and ...

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING APPARATUS

According to one embodiment, a manufacturing method of a semiconductor device includes forming a crystal film on a semiconductor substrate by irradiating the semiconductor substrate with a first microwave, obtained by providing frequency modulation or phase modulation of a first carrier wave which is a sine wave with a first frequency, using a first signal wave which is a sine wave or a pulse wave with a third frequency lower than a first frequency, and irradiating the semiconductor substrate with a second microwave, obtained by providing frequency modulation or phase modulation of a second carrier wave, which is a sine wave with a second frequency higher than the first frequency, using a second signal wave which is a sine wave or a pulse wave with a fourth frequency lower than the second frequency. 1. A manufacturing method of a semiconductor device , comprising:forming a crystal film on a semiconductor substrate by irradiating a first microwave energy at a first frequency and a second microwave energy at a second frequency higher than the first frequency.2. The manufacturing method according to claim 1 , whereinthe semiconductor substrate is cooled during irradiation of the first microwave.3. The manufacturing method according to claim 1 , whereinthe semiconductor substrate is rotated during irradiation of the first microwave.4. The manufacturing method according to claim 1 , whereinthe semiconductor substrate is rotated during irradiation of the second microwave.5. The manufacturing method according to claim 1 , whereinthe first microwave energy includes a first carrier wave that is frequency modulated or phase modulated.6. The manufacturing method according to claim 5 , whereinthe first carrier wave is a sine wave having a first frequency.7. The manufacturing method according to claim 6 , whereinthe second microwave energy includes a second carrier wave that is frequency modulated or phase modulated.8. The manufacturing method according to claim 6 , whereinthe ...

ELECTRONIC DEVICES INCLUDING BARIUM STRONTIUM TITANIUM OXIDE FILMS

Apparatus and methods of forming the apparatus include a dielectric layer containing barium strontium titanium oxide layer, an erbium-doped barium strontium titanium oxide layer, or a combination thereof. Embodiments of methods of fabricating such dielectric layers provide dielectric layers for use in a variety of devices. Embodiments include forming barium strontium titanium oxide film using atomic layer deposition. Embodiments include forming erbium-doped barium strontium titanium oxide film using atomic layer deposition. 1. A method comprising:forming a layer of strontium titanium oxide by atomic layer deposition;forming a layer of barium titanium oxide by atomic layer deposition; andannealing the layers of strontium titanium oxide and barium titanium oxide to form a layer of barium strontium titanium oxide.2. The method of claim 1 , wherein the method includes doping the barium strontium titanium oxide with erbium.3. The method of claim 1 , wherein the method includes forming alternating layers of SrTiOand BaTiObefore annealing.4. The method of claim 1 , wherein the method includes forming an amorphous barium strontium titanium oxide layer.5. The method of claim 1 , wherein the method includes forming a BaSrTiOlayer.6. The method of claim 1 , wherein forming the layer of barium strontium titanium oxide includes forming the layer of barium strontium titanium oxide as a capacitor dielectric in a capacitor in an integrated circuit.7. The method of claim 1 , wherein forming the layer of barium strontium titanium oxide includes forming the layer of barium strontium titanium oxide as a dielectric layer in a memory.8. The method of claim 1 , wherein forming the layer of barium strontium titanium oxide includes forming the layer of barium strontium titanium oxide as a gate insulator in a transistor.9. The method of claim 1 , wherein forming the layer of barium strontium titanium oxide includes forming the layer of barium strontium titanium oxide as a gate insulator in a ...

Optoelectric device with semiconductor microwires or nanowires and method for manufacturing the same

An optoelectric device including microwires or nanowires on a support, each microwire or nanowire including at least one portion mainly containing a III-V compound in contact with the support, wherein the III-V compound is based on a first group-V element and on a second group-III element, wherein a surface of the support includes first areas of a first material promoting the growth of the III-V compound according to the polarity of the first element distributed in a second area of a second material promoting the growth of the compound according to the polarity of the second element, the microwires or nanowires being located on the first areas. 1. A device comprising microwires or nanowires on a support , each microwire or nanowire comprising at least one portion mainly containing a III-V compound in contact with the support , wherein the III-V compound is based on a first group-V element and on a second group-III element , wherein a surface of the support comprises first areas of a first material promoting the growth of the III-V compound according to the polarity of the first element distributed in a second area of a second material promoting the growth of the compound according to the polarity of the second element , the microwires or nanowires being located on the first areas , wherein the periphery of said portion is covered with a layer of a dielectric material from the support up to part of the total height of said portion.2. The optoelectric device of claim 1 , wherein the dielectric material layer has a thickness ranging between one atomic monolayer and 5 nm.3. The device of claim 1 , wherein the first material comprises magnesium nitride or magnesium and gallium nitride.4. The device of claim 1 , wherein the second material comprises aluminum nitride.5. The device of claim 1 , wherein blocks are located on the second area claim 1 , the blocks comprising said compound and having a thickness ranging between 50 nm and 5 μm and smaller than the height of the ...

Method for Manufacturing a Semiconductor Structure

According to an embodiment, a method for manufacturing a semiconductor structure includes providing a first monocrystalline semiconductor portion having a first lattice constant in a reference direction and forming a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion. 1. A method for manufacturing a semiconductor structure , the method comprising:providing a first monocrystalline semiconductor portion having a first lattice constant in a reference direction; andforming a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion.2. The method of claim 1 , wherein the first monocrystalline semiconductor portion and the second monocrystalline semiconductor portion are made of the same semiconductor material.3. The method of claim 1 , wherein the second monocrystalline semiconductor portion is formed in direct contact with the first monocrystalline semiconductor portion.4. The method of claim 1 , further comprising:forming a semiconductor layer, selected from the group consisting of micro-crystalline semiconductor layer, partially micro-crystalline semiconductor layer, amorphous semiconductor layer and partially amorphous semiconductor layer, on or at a surface of the first monocrystalline semiconductor portion; andannealing the semiconductor layer at an elevated temperature to cause the semiconductor layer to crystallise or re-crystallise to form the second Monocrystalline semiconductor portion on and in contact with the first monocrystalline semiconductor portion.5. The method of claim 4 , wherein the annealing is carried out at a temperature equal to or higher than 800° C.6. The method of claim 4 , wherein the annealing is carried out in a temperature range between ...

Polysilicon Thin Film And Manufacturing Method Thereof, Array Substrate And Display Device

A polysilicon thin film and a manufacturing method thereof, an array substrate and a display device are disclosed. The manufacturing method of the polysilicon thin film comprises the following steps: forming a graphene layer and an amorphous silicon layer which are adjacent; forming polysilicon by way of crystallizing amorphous silicon so as to obtain the polysilicon thin film. The polysilicon thin film manufactured by the method possesses good characteristics. 1. A manufacturing method of a polysilicon thin film , comprising the following steps:(A) forming a graphene layer and an amorphous silicon layer which are adjacent;(B) forming polysilicon by way of crystallizing amorphous silicon so as to obtain the polysilicon thin film.2. The manufacturing method of the polysilicon thin film of claim 1 , wherein claim 1 , the step (A) comprises:forming the amorphous silicon layer on a base layer, and then forming the graphene layer on the amorphous silicon layer.3. The manufacturing method of the polysilicon thin film of claim 2 , further comprising a step (C) following the step (B):removing the graphene layer through an ashing process.4. The manufacturing method of the polysilicon thin film of claim 3 , wherein the ashing process in the step (C) ashes the graphene layer by dry etching with oxygen gas.5. The manufacturing method of the polysilicon thin film of claim 1 , wherein claim 1 , the step (A) comprises:forming the graphene layer on a base layer, and then forming the amorphous silicon layer on the graphene layer.6. The manufacturing method of the polysilicon thin film of claim 1 , wherein the graphene layer formed in the step (A) is a p-type graphene layer.7. The manufacturing method of the polysilicon thin film of claim 2 , wherein the graphene layer formed in the step (A) is a p-type graphene layer.8. The manufacturing method of the polysilicon thin film of claim 5 , wherein the graphene layer formed in the step (A) is a p-type graphene layer.9. The manufacturing ...

Method for making epitaxial structure

A method for making an epitaxial structure is provided. The method includes the following steps. A substrate having an epitaxial growth surface is provided. A buffer layer is formed on the epitaxial growth surface. A carbon nanotube layer is placed on the buffer layer. An epitaxial layer is epitaxially grown on the buffer layer. The substrate and the carbon nanotube layer are removed.

Laser Doping of Crystalline Semiconductors Using a Dopant-Containing Amorphous Silicon Stack For Dopant Source and Passivation

Techniques and structures for laser doping of crystalline semiconductors using a dopant-containing amorphous silicon stack for dopant source and passivation. A structure includes a crystalline semiconductor having at least one surface, a doped crystalline region disposed in at least one selected area of the semiconductor surface, and a dopant-containing amorphous silicon layer stack containing a same dopant as present in the doped crystalline region on at least a portion of the semiconductor surface outside the selected area, wherein the dopant-containing amorphous silicon layer stack passivates the portion of the semiconductor surface on which it is disposed.

BEAM HOMOGENIZER, LASER IRRADIATION APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

The energy distribution of the beam spot on the irradiated surface changes due to the change in the oscillation condition of the laser or before and after the maintenance. The present invention provides an optical system for forming a rectangular beam spot on an irradiated surface including a beam homogenizer for homogenizing the energy distribution of the rectangular beam spot on the irradiated surface in a direction of its long or short side. The beam homogenizer includes an optical element having a pair of reflection planes provided oppositely for reflecting the laser beam in the direction where the energy distribution is homogenized and having a curved shape in its entrance surface. The entrance surface of the optical element means a surface of the optical element where the laser beam is incident first. 1. (canceled)2. A method for manufacturing a semiconductor device comprising:forming a non-single crystal semiconductor film over a substrate,emitting a laser beam from a laser oscillator,forming a beam spot on the non-single crystal semiconductor film by an optical system comprising a beam homogenizer, andforming a crystalline semiconductor film by irradiating the non-single crystal semiconductor film with the beam spot while moving a position of the beam spot relative to the substrate,wherein the optical system comprises a pair of mirrors, andwherein the optical system comprises a concave lens between the pair of mirrors.3. The method for manufacturing a semiconductor device according to claim 2 , wherein the optical system comprises a light pipe.4. The method for manufacturing a semiconductor device according to claim 2 , wherein the optical system comprises an optical waveguide.5. The method for manufacturing a semiconductor device according to claim 2 , further comprising a cylindrical lens facing a curved surface of the concave lens.6. The method for manufacturing a semiconductor device according to claim 2 , wherein the concave lens is a concave ...

Memory transistor with multiple charge storing layers and a high work function gate electrode

Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ONO) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ONO stack. Preferably, the gate electrode comprises a doped polysilicon layer, and the ONO stack comprises multi-layer charge storing layer including at least a substantially trap free bottom oxynitride layer and a charge trapping top oxynitride layer. More preferably, the device also includes a metal oxide semiconductor (MOS) logic transistor formed on the same substrate, the logic transistor including a gate oxide and a high work function gate electrode. In certain embodiments, the dopant is a P+ dopant and the memory transistor comprises N-type (NMOS) silicon-oxide-nitride-oxide-silicon (SONOS) transistor while the logic transistor a P-type (PMOS) transistor. Other embodiments are also disclosed.

SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF

A semiconductor device and a forming method thereof are provided. The semiconductor device includes a substrate, a fin located on the substrate, and a gate structure located on the substrate and across the fin. The fin includes a first region, and the fin of the first region includes a gate groove and a channel layer located between adjacent gate grooves. The gate structure covers a sidewall and a top of the fin of the first region, fills the gate groove and surrounds the channel layer. A width of the gate structure located in the gate groove is smaller than a width of the gate structure located on the top of the fin of the first region. 1. A semiconductor device , comprising:a substrate;a fin, located on the substrate; anda gate structure, located on the substrate and across the fin, the fin includes a first region, and the fin of the first region includes a gate groove and a channel layer located between adjacent gate grooves;', 'the gate structure covers a sidewall and a top of the fin of the first region, fills the gate groove and surrounds the channel layer; and', 'a width of the gate structure located in the gate groove is smaller than a width of the gate structure located on the top of the fin of the first region., 'wherein2. The device according to claim 1 , further comprising a sidewall spacer claim 1 , wherein:the sidewall spacer is located on a sidewall of the gate structure; and the first sidewall spacer is located on a sidewall of the gate structure; and', 'the second sidewall spacer is located on a sidewall of the first sidewall spacer., 'the sidewall spacer includes a stacked structure including a first sidewall spacer and a second sidewall spacer, wherein3. The device according to claim 2 , further comprising a barrier layer claim 2 , wherein:the barrier layer is located on a sidewall of the gate structure in the gate groove.4. The device according to claim 3 , wherein:a sidewall of the barrier layer is located between the sidewall of the first ...

Method for heat treatment of silicon single crystal wafer

The present invention is a method for a heat treatment of a silicon single crystal wafer in an oxidizing ambient, including: performing the heat treatment based on a condition determined by a tripartite correlation between a heat treatment temperature during the heat treatment, an oxygen concentration in the silicon single crystal wafer before the heat treatment, and a void size in the silicon single crystal wafer before the heat treatment. This provides a method for a heat treatment of a silicon single crystal wafer which can annihilate void defects or micro oxide precipitate nuclei in a silicon single crystal wafer with low cost, efficiently, and securely by a heat treatment in an oxidizing ambient.

METHOD OF FABRICATING THIN FILM TRANSISTOR ARRAY SUBSTRATE

A thin film transistor array substrate includes a substrate, a plurality of poly-silicon islands and a plurality of gates. The substrate has a display region, a gate driver region and a source driver region. Each poly-silicon island disposed on the substrate has a source region, a drain region and a channel region disposed therebetween. The poly-silicon islands include several first poly-silicon islands and several second poly-silicon islands. The first poly-silicon islands having main grain boundaries and sub grain boundaries are only disposed within the display region and the gate driver region. The main grain boundaries of the first poly-silicon islands are only disposed within the source regions and/or the drain regions. The second poly-silicon islands are disposed in the source driver region. Grain sizes of the first poly-silicon islands are substantially different from those of the second poly-silicon islands. Gates corresponding to the channel regions are disposed on the substrate. 1. A method of fabricating a thin film transistor array substrate , comprising:providing a substrate, the substrate comprising a display region, a gate driver region, and a source driver region;forming an amorphous silicon layer on the substrate;using a laser beam to irradiate the amorphous silicon layer to form a poly-silicon layer, wherein the poly-silicon layer comprises a plurality of main grain boundaries and a plurality of sub grain boundaries, and grain sizes of the poly-silicon layer disposed in the display region and the gate driver region are different from grain sizes of the poly-silicon layer disposed in the source driver region;patterning the poly-silicon layer to form a plurality of poly-silicon islands, wherein the poly-silicon islands disposed in the display region and the gate driver region constitute a plurality of first poly-silicon islands, and the poly-silicon islands disposed in the source driver region constitute a plurality of second poly-silicon islands; ...

SEMICONDUCTOR NANOCRYSTALS, METHODS FOR PREPARING SEMICONDUCTOR NANOCRYSTALS, AND PRODUCTS INCLUDING SAME

Disclosed is a method for preparing a semiconductor nanocrystal, comprising: forming a reaction mixture comprising injecting one or more first semiconductor nanocrystal precursors including one or more Group V elements and one or more Group VI elements into a mixture including one or more second semiconductor nanocrystal precursors including one or more Group II elements and one or more Group III elements at a first temperature; and reacting the first and second semiconductor nanocrystal precursors in the reaction mixture at a second temperature for a period time sufficient to form a semiconductor nanocrystal core comprising at least a portion of the one or more Group II elements, one or more Group III elements, one or more Group V elements, and one or more Group VI elements included in the first and second semiconductor nanocrystal precursors, wherein the second temperature is greater than the first temperature. 1. A method for preparing a semiconductor nanocrystal , comprising:forming a reaction mixture comprising injecting one or more first semiconductor nanocrystal precursors including one or more Group V elements and one or more Group VI elements into a mixture including one or more second semiconductor nanocrystal precursors including one or more Group II elements and one or more Group III elements at a first temperature; andreacting the first and second semiconductor nanocrystal precursors in the reaction mixture at a second temperature for a period time sufficient to form a semiconductor nanocrystal core comprising at least a portion of the one or more Group II elements, one or more Group III elements, one or more Group V elements, and one or more Group VI elements included in the first and second semiconductor nanocrystal precursors, wherein the second temperature is greater than the first temperature.2. A method in accordance with wherein the first temperature is greater than about 170° C.3. A method in accordance with wherein the second temperature is at ...

POLYSILICON LAYER PREPARING METHOD

The present disclosure discloses a method of preparing the polysilicon layer, wherein by the depositions of the amorphous silicon thin film in batches for many times and the implementation of the excimer laser process after each deposition, it can not only convert the amorphous silicon thin film into the polysilicon thin film completely, but also control the uniformity of the polysilicon thin film, thereby gaining the polysilicon layer of good uniformity which composed of the polysilicon thin films stacked in sequence, improving the performance of the product while effectively avoiding the chromatism problems of the display device, and significantly improving the yield of products. 1. A polysilicon layer preparing method comprising the steps of:forming a plurality of polysilicon thin films on a substrate by polysilicon deposition and transformation process;wherein, the polysilicon layer is formed by stacking a plurality of the polysilicon thin films in sequence.2. The method as claimed in claim 1 , wherein the substrate comprises a baseplate claim 1 , a silicon nitride layer and a silicon oxide layer;wherein, an upper surface of the baseplate is covered by the silicon nitride layer; an upper surface of the silicon nitride layer is covered by the silicon oxide layer; and an upper surface of the silicon oxide layer is covered by the polysilicon layer.3. The method as claimed in claim 2 , wherein the baseplate is made of glass or plastic.4. The method as claimed in claim 1 , wherein the polysilicon deposition and transformation process comprises:depositing an amorphous silicon thin film on the baseplate; andtransforming the amorphous silicon thin film into the polysilicon thin film.5. The method as claimed in claim 4 , wherein the amorphous silicon thin film is formed by chemical vapor deposition claim 4 , physical vapor deposition claim 4 , plasma enhancing chemical vapor deposition claim 4 , low pressure chemical vapor deposition or atomic layer deposition.6. The ...

METHODS OF FORMING VERTICAL CELL SEMICONDUCTOR DEVICES WITH SINGLE-CRYSTALLINE CHANNEL STRUCTURES

Methods of fabricating a vertical cell semiconductor device including forming a hole passing through a stacked structure of alternating insulating and sacrificial layers on a substrate, forming an amorphous silicon layer conforming to an inner wall of the hole, forming a silicon region on the amorphous silicon layer, and metal induced crystallizing the amorphous silicon layer via the silicon region to form a single-crystalline channel structure in the hole. 1. A method of fabricating a semiconductor device , the method comprising:forming alternating interlayer insulating layers and sacrificial layers on a substrate;forming a first capping layer on the interlayer insulating layers and the sacrificial layers;forming a channel hole passing through the first capping layer, the interlayer insulating layers and the sacrificial layers to expose a first portion of the substrate;forming a dielectric pattern conforming to a wall of the channel hole;forming an amorphous channel active pattern conforming to the dielectric pattern and the exposed first portion of the substrate;forming a channel core pattern in a space defined by the amorphous channel active pattern;forming an amorphous silicon layer on the first capping layer and the amorphous channel active pattern;forming a metal catalytic layer on the amorphous silicon layer; andannealing to change the amorphous silicon layer and the amorphous channel active pattern into a single-crystalline silicon layer and a single-crystalline channel active pattern, respectively.2. The method of claim 1 , wherein forming a metal catalytic layer on the amorphous silicon layer is preceded by forming an insulating barrier layer on the amorphous silicon layer and wherein forming a metal catalytic layer on the amorphous silicon layer comprises forming the metal catalytic layer on the insulating barrier layer.3. The method of claim 2 , wherein forming the insulating barrier layer on the amorphous silicon layer is preceded by forming a mask ...

METHOD OF MANUFACTURING LOW TEMPERATURE POLYCRYSTALLINE SILICON THIN FILM AND THIN FILM TRANSISTOR, THIN FILM TRANSISTOR, DISPLAY PANEL AND DISPLAY DEVICE

A method of manufacturing a low temperature polycrystalline silicon thin film and a thin film transistor, a thin film transistor, a display panel and a display device are provided. The method includes: forming an amorphous silicon thin film () on a substrate (); forming a pattern of a silicon oxide thin film () covering the amorphous silicon thin film (), a thickness of the silicon oxide thin film () located at a preset region being larger than that of the silicon oxide thin film () located at other regions; and irradiating the silicon oxide thin film () by using excimer laser to allow the amorphous silicon thin film () forming an initial polycrystalline silicon thin film (), the initial polycrystalline silicon thin film () located at the preset region being a target low temperature polycrystalline silicon thin film (). The polycrystalline silicon thin film has more uniform crystal size. 1. A method of manufacturing a low temperature polycrystalline silicon thin film , comprising:forming an amorphous silicon thin film on a substrate;forming a pattern of a silicon oxide thin film covering the amorphous silicon thin film, wherein a thickness of the silicon oxide thin film located at a preset region is larger than that of the silicon oxide thin film located at other regions other than the preset region; andirradiating the silicon oxide thin film by using excimer laser to allow the amorphous silicon thin film forming an initial polycrystalline silicon thin film, wherein the initial polycrystalline silicon thin film located at the preset region is a target low temperature polycrystalline silicon thin film.2. The manufacturing method according to claim 1 , further comprising: after forming the initial polycrystalline silicon thin film by using the amorphous silicon thin film claim 1 ,removing the silicon oxide thin film on the initial polycrystalline silicon thin film;hydrotreating the initial polycrystalline silicon thin film; andpatterning the hydrotreated initial ...

Method for manufacturing semiconductor device

The invention relates to a method for forming a uniform silicide film using a crystalline semiconductor film in which orientation of crystal planes is controlled, and a method for manufacturing a thin film transistor with less variation in electric characteristics, which is formed over an insulating substrate using the silicide film. A semiconductor film over which a cap film is formed is irradiated with a laser to be crystallized under the predetermined condition, so that a crystalline semiconductor film including large grain crystals in which orientation of crystal planes is controlled in one direction is formed. The crystalline semiconductor film is used for silicide, whereby a uniform silicide film can be formed. 1. (canceled)2. A method of manufacturing a semiconductor device comprising:forming a semiconductor film comprising amorphous silicon over a substrate;emitting a first laser beam having a length along a first direction and a width along a second direction, the first laser beam including TEM00 mode; modifying the first laser beam along the first direction by using a first cylindrical lens; and', 'modifying the first laser beam along the second direction by using a second cylindrical lens, and, 'shaping the first laser beam to a second laser beam having a linear shape, wherein the step of shaping includesirradiating the semiconductor film with the second laser beam to crystallize the semiconductor film,wherein the semiconductor film comprises a crystal region of which crystal plane orientation in a direction perpendicular to a surface of the semiconductor film is {100}.3. The method according to claim 2 , wherein the crystal region occupies 40% or more of the semiconductor film.4. The method according to claim 2 , wherein the semiconductor film has a thickness of greater than or equal to 10 nm and less than or equal to 100 nm.5. The method according to claim 2 , wherein the semiconductor film is formed on an insulating film having a thickness of 50 to 150 ...

GENERATION OF LOCALIZED STRAIN IN A SOI SUBSTRATE

Method to strain a channel zone of a transistor of the semiconductor on insulator type transistor that makes use of an SMT stress memorisation technique in which regions located under the insulation layer of the substrate (FIG. ) are amorphised, before the transistor gate is made. 1. Method for making a transistor with a strained channel on a semiconductor on insulator type substrate comprising a support layer , a surface semiconducting layer and an insulating layer separating the support layer and the surface semiconducting layer , the method comprising steps consisting of:a) forming a stencil on the surface semiconducting layer provided with a plurality of openings, at least two openings in the stencil and at least one stencil block located between the two openings being arranged facing a first zone in the surface semiconducting layer in which a transistor channel is provided,{'b': 10', '10, 'i': 'a', 'b) making regions in the support layer that are not protected by the stencil and are facing the openings and the first zone of the surface semiconducting layer amorphous, so as to keep at least one non-amorphised crystalline portion of the support layer facing the first zone, between two amorphous regions,'}c) recrystallising regions made amorphous in the support layer, recrystallisation being made such that a mechanical strain is applied on the substrate during this recrystallisation through a stressor layer deposited on the substrate,d) removing the stencil and the stressor layer,e) forming a gate for the transistor on the first zone of the surface layer.2. Method according to claim 1 , wherein the stressor layer is deposited after the stencil has been formed and before recrystallisation.3. Method according to claim 1 , wherein the stencil is based on a strained material claim 1 , the stencil forming the stressor layer during step c).4. Method according to claim 1 , wherein at least one opening in the stencil exposes a second zone of the surface layer in which or ...

ELECTRONIC DEVICES COMPRISING CRYSTALLINE MATERIALS AND RELATED MEMORY DEVICES AND SYSTEMS

A method includes forming a first amorphous material, forming a second amorphous material over and in contact with the first material, removing a portion of the second material and the first material to form pillars, and exposing the materials to a temperature between a crystallization temperature of the first material and a crystallization temperature of the second material. The first material and the second material each comprise at least one element selected from the group consisting of silicon and germanium. The second material exhibits a crystallization temperature different than a crystallization temperature of the first material. Semiconductor structures, memory devices, and systems are also disclosed. 1. An electronic device , comprising:crystalline pillars, each crystalline pillar comprising a portion of a first material and a portion of a second material over and in contact with the portion of the first material, wherein each of the first material and the second material comprise at least one element selected from the group consisting of silicon and germanium, and wherein the second material exhibits a composition different than a composition of the first material;wherein each crystalline pillar is laterally isolated from each adjacent crystalline pillar, and wherein the portion of the first material in each pillar is in single crystalline form.2. The electronic device of claim 1 , further comprising a blocking material between the crystalline pillars.3. The electronic device of claim 2 , wherein the blocking material comprises a material selected from the group consisting of an oxide claim 2 , a nitride claim 2 , and a carbon-containing material.4. The electronic device of claim 1 , further comprising a dopant in at least one material selected from the group consisting of the first material and the second material.5. The electronic device of claim 4 , wherein the dopant comprises an element selected from the group consisting of boron claim 4 , arsenic ...

METHOD FOR MANUFACTURING SINGLE-GRAINED NANOWIRE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE EMPLOYING SAME SINGLE-GRAINED NANOWIRE

A method of manufacturing a semiconductor nanowire semiconductor device is described. The method includes forming an amorphous channel material layer on a substrate, patterning the channel material layer to form semiconductor nanowires extending in a lateral direction on the substrate, and forming a cover layer covering an upper of the semiconductor nanowire. The cover layer and the nanowire are patterned to form a trench exposing a side surface of an one end of the semiconductor nanowire and a catalyst material layer is formed in contact with a side surface of the semiconductor nanowire, and metal induced crystallization (MIC) by heat treatment is performed to crystallize the semiconductor nanowire in a length direction of the nanowire from the one end of the semiconductor nanowire in contact with the catalyst material. 1. A method of manufacturing a semiconductor nanowire , the method comprising:forming an amorphous channel material layer on a substrate;patterning the channel material layer to form semiconductor nanowires extending in a lateral direction on the substrate;forming a cover layer covering an upper of the semiconductor nanowire;patterning the cover layer and the nanowire to form a trench exposing a side surface of an one end of the semiconductor nanowire;forming a catalyst material layer in contact with the side surface of the semiconductor nanowire; andperforming metal induced crystallization (MIC) by heat treatment to crystallize the semiconductor nanowire in a length direction of the nanowire from one end of the semiconductor nanowire in contact with the catalyst material.2. The method of claim 1 , wherein the channel material layer is formed of any one selected from the group consisting of Si claim 1 , SiGe claim 1 , and Ge.3. The method of claim 2 , wherein the catalyst material layer is formed of at least one material selected from the group consisting of Ni claim 2 , NiOx claim 2 , NiCxOy claim 2 , NiNxOy claim 2 , NiCxNyOz claim 2 , NiCxOy:H ...

FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REDUCED DIMENSIONAL VARIATIONS

A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins. 1. A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations , comprising:forming two dummy fin trenches in a substrate, wherein each of the two dummy fin trenches is on opposite sides of a portion of the substrate;forming a dummy fin fill in each of the two dummy fin trenches;forming a first dummy fin from one of the dummy fin fills, a second dummy fin from the other of the two dummy fin fills, and a vertical fin from the portion of the substrate between the two dummy fin trenches, wherein the first dummy fin and second dummy fin are border fins and the vertical fin is an interior fin; andremoving the border fins.2. The method of claim 1 , wherein the border fins and interior fin have a width in the range of about 4 nm to about 20 nm.3. The method of claim 1 , wherein the dummy fin fill and the border fins are made of amorphous silicon (a-Si) claim 1 , poly-crystalline silicon (p-Si) claim 1 , amorphous silicon-germanium (a-SiGe) claim 1 , or poly-crystalline silicon-germanium (p-SiGe).4. The method of claim 3 , wherein the vertical fin is single crystal silicon claim 3 , and the border fins are removed by a selective HCl etch.5. The method of claim 1 , wherein the width of each of the two dummy fin trenches is in the range of about 30 nm to about 30 nm.6. ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, and a second insulating film provided between the first electrode and the second electrode. The second electrode includes a thin sheet portion disposed on the first electrode side, and a thick sheet portion disposed on the semiconductor pillar side. A length in the first direction of the thick sheet portion is longer than a length in the first direction of the thin sheet portion. 1. A semiconductor memory device , comprising:a semiconductor pillar extending in a first direction;a first electrode extending in a second direction crossing the first direction;a second electrode provided between the semiconductor pillar and the first electrode;a first insulating film provided between the semiconductor pillar and the second electrode; anda second insulating film provided between the first electrode and the second electrode, a thin sheet portion disposed on the first electrode side, and', 'a thick sheet portion disposed on the semiconductor pillar side, a length in the first direction of the thick sheet portion being longer than a length in the first direction of the thin sheet portion., 'the second electrode including'}2. The device according to claim 1 , wherein a first layer disposed between the thin sheet portion and the first electrode and on two first-direction sides of the thin sheet portion; and', 'a second layer disposed between the first layer and the first electrode and on two first-direction sides of the first electrode., 'the second insulating film includes3. The device according to claim 2 , wherein a portion of the second layer is disposed on two first-direction sides of the first ...

SEMICONDUCTOR STRUCTURE AND METHODS FOR CRYSTALLIZING METAL OXIDE SEMICONDUCTOR LAYER

The present invention provides two methods for crystallizing a metal oxide semiconductor layer and a semiconductor structure. The first crystallization method is treating an amorphous metal oxide semiconductor layer including indium with oxygen at a pressure of about 550 mtorr to about 5000 mtorr and at a temperature of about 200° C. to about 750° C. The second crystallization method is, firstly, sequentially forming a first amorphous metal oxide semiconductor layer, an aluminum layer, and a second amorphous metal oxide semiconductor layer on a substrate, and, secondly, treating the first amorphous metal oxide semiconductor layer, the aluminum layer, and the second amorphous metal oxide semiconductor layer with an inert gas at a temperature of about 350° C. to about 650° C. 1. A method for crystallizing a metal oxide semiconductor layer , comprising:forming an amorphous metal oxide semiconductor layer on a substrate, the amorphous metal oxide semiconductor layer comprising indium; andtreating the amorphous metal oxide semiconductor layer with oxygen at a pressure of about 550 mtorr to about 5000 mtorr at a temperature of about 200° C. to about 750° C., and changing a part of the amorphous metal oxide semiconductor layer into an indium oxide crystallization layer.2. The method according to claim 1 , further comprising: heating the indium oxide crystallization layer.3. The method according to claim 2 , wherein the heating the indium oxide crystallization layer is performed at a temperature of about 200° C. to about 800° C.4. The method according to claim 1 , wherein a radio-frequency power source is further comprised claim 1 , and when the amorphous metal oxide semiconductor layer is being treated with oxygen claim 1 , an output power of the radio-frequency power source is 0.5. The method according to claim 1 , wherein a radio-frequency power source is further comprised claim 1 , and when the amorphous metal oxide semiconductor layer is being treated with oxygen claim ...

LOW TEMPERATURE POLYCRYSTALLINE SEMICONDUCTOR DEVICE AMD MANUFACTURING METHOD THEREOF

Provided is a method of manufacturing a semiconductor device, the method including: forming a buffer layer of an insulating layer on a substrate; a seed layer formation operation of forming, on the buffer layer, a seed layer of at least one selected from the group consisting of NiCxOy, NiNxOy, NiCxNyOz, NiCxOy:H, NiNxOy:H, NiCxNyOz:H, NixSiy, and NixGey; a silicon layer formation operation of forming an amorphous silicon layer on the seed layer; and a crystallization operation of crystallizing the amorphous silicon layer by a catalytic action of Ni by thermally treating the amorphous silicon layer. 1. A method of manufacturing a semiconductor device , the method comprising:forming a buffer layer of an insulating material on a substrate;a seed layer formation operation of forming, on the buffer layer, a seed layer of at least one selected from the group consisting of NiCxOy, NiNxOy, NiCxNyOz, NiCxOy:H, NiNxOy:H, NiCxNyOz:H, NixSiy, and NixGey;a silicon layer formation operation of forming an amorphous silicon layer on the seed layer; anda crystallization operation of crystallizing the amorphous silicon layer by a catalytic action of Ni by thermally treating the amorphous silicon layer.2. The method of claim 1 , further comprising:forming a catalytic reaction control layer between the seed layer formation operation and the silicon layer formation operation.3. The method of claim 1 , wherein the silicon layer formation operation comprises:forming, on the buffer layer, an amorphous intrinsic silicon layer for forming a channel;forming, on the amorphous intrinsic silicon layer, a non-intrinsic silicon layer for forming a source and/or drain; andforming a metal layer on the non-intrinsic silicon layer.4. The method of claim 3 , wherein the non-intrinsic silicon layer is formed so that a first non-intrinsic silicon layer claim 3 , in contact with an amorphous silicon layer for forming a semiconductor channel claim 3 , has a lower doping concentration than a second non- ...

LASER IRRADIATION APPARATUS, LASER IRRADIATION METHOD, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A laser irradiation apparatus includes a laser generation device, a levitation unit to levitate an object to which the laser light is applied, and a conveyance unit to convey the levitated object. The conveyance unit includes a holding mechanism for holding the object by absorption, and a moving mechanism for moving the holding mechanism in a conveyance direction. The holding mechanism includes a base including a plurality of through holes, a plurality of pipes respectively connected to the through holes, a vacuum generation device configured to evacuate air from the f pipes, and a plurality of absorption assistance valves each disposed in the middle of a respective one of the pipes, each of the plurality of absorption assistance valves being configured to be closed when a flow rate of a gas flowing into the pipe through the through hole becomes equal to or higher than a threshold. 1. A laser irradiation apparatus comprising:a laser generation device configured to generate laser light;a levitation unit configured to levitate an object to be processed to which the laser light is applied; anda conveyance unit configured to convey the levitated object to be processed, whereinthe conveyance unit comprises:a holding mechanism for holding the object to be processed by absorbing the object to be processed; anda moving mechanism for moving the holding mechanism in a conveyance direction, andthe holding mechanism comprises:a base including: a first surface serving as an absorption surface on which the object to be processed is absorbed; a second surface opposite to the first surface; and a plurality of through holes extending from the first surface to the second surface;a plurality of pipes each of which is connected to a respective one of the plurality of through holes on the second surface of the base;an evacuation mechanism for evacuating air from the plurality of pipes; anda plurality of absorption assistance valves each of which is disposed in the middle of a respective ...

Three-dimensional Vertical NOR Flash Thin-Film Transistor Strings

A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings. 1. A memory structure , comprising:a storage transistor having a gate terminal, a first drain or source terminal, and a second drain or source terminal, the storage transistor having a variable threshold voltage representative of data stored therein;a word line connected to the gate terminal to provide a control voltage during a read operation;a bit line connecting the first drain or source terminal to data detection circuitry; anda source line connected to the second drain or source terminal to provide a capacitance sufficient to sustain at least a predetermined voltage difference between the second drain or source terminal and the gate terminal during the read operation.2. The memory structure of claim 1 , further comprising a pre-charge transistor for charging the capacitance to a predetermined voltage prior to the ...

Package-on-package structure and method of manufacturing package

A package-on-package (PoP) structure includes a first package and a second package stacked on the first package. The first package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes an amorphous layer located on the rear surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is on the active surface of the die and is electrically connected to the conductive structures and the die.

Method of Manufacturing a Semiconductor Device Having an Integrated pn Diode Temperature Sensor

A method of manufacturing a semiconductor device includes: forming one or more transistor cells in a first region of a semiconductor substrate, the semiconductor substrate having a second region that is devoid of transistor cells; forming a first dielectric material over the first and second regions; forming a second dielectric material over the first dielectric material; forming a pn diode in the first dielectric material over the second region; etching first contact grooves into a p-type region of the pn diode, second contact grooves into an n-type region of the pn diode, and third contact grooves into the first region of the semiconductor substrate at the same time using a common contact formation process; and filling the first contact grooves, the second contact grooves and the third contact grooves with an electrically conductive material. 1. A method of manufacturing a semiconductor device , the method comprising:forming one or more transistor cells in a first region of a semiconductor substrate, the semiconductor substrate having a second region that is devoid of transistor cells;forming a first dielectric material over the first region and the second region of the semiconductor substrate;forming a second dielectric material over the first dielectric material;forming a pn diode in the first dielectric material over the second region of the semiconductor substrate;etching first contact grooves into a p-type region of the pn diode, second contact grooves into an n-type region of the pn diode, and third contact grooves into the first region of the semiconductor substrate, the first contact grooves, the second contact grooves and the third contact grooves being etched at the same time using a common contact formation process; andfilling the first contact grooves, the second contact grooves and the third contact grooves with an electrically conductive material.2. The method of claim 1 , further comprising:photolithographically focusing the common contact formation ...

FZ SILICON AND METHOD TO PREPARE FZ SILICON

FZ silicon which shows no degradation of its minority carrier lifetime after any processing steps at a processing temperature of less than 900° C. is prepared by annealing FZ silicon at an annealing temperature of greater than or equal to 900° C. and processing the annealed FZ silicon at a processing temperature of less than 900° C. 114.-. (canceled)15. A method for preparing FZ silicon with improved minority carrier lifetime , comprising:annealing FZ silicon at an annealing temperature of ≥900° C., and further processing the annealed FZ silicon at processing temperatures of less than 900° C.16. The method of claim 15 , further comprising mechanically forming a plurality of FZ silicon wafers from an FZ pulled ingot claim 15 , prior to annealing at ≥900° C.17. The method of claim 15 , comprising annealing an FZ pulled ingot at an annealing temperature of ≥900° C. claim 15 , and then mechanically forming a plurality of FZ wafers.18. The method of claim 15 , wherein the FZ silicon is annealed in an oxygen-containing ambient.19. The method of claim 16 , wherein at least one FZ wafer formed from the FZ silicon is further processed at a processing temperature of less than 900° C.20. The method of claim 17 , wherein at least one FZ wafer formed from the FZ silicon is further processed at a processing temperature of less than 900° C.21. The method of claim 15 , wherein the annealing step is performed in a rapid thermal processing chamber.22. The method of claim 15 , wherein processing the annealed FZ silicon at a processing temperature of less than 900° C. comprises a step of deposition of polycrystalline silicon on a surface of an FZ wafer.23. The method of claim 15 , wherein the FZ silicon is doped with nitrogen.24. FZ silicon which shows no degradation of minority carrier lifetime after any processing steps at processing temperatures of less than 900° C.25. The FZ silicon of claim 24 , doped with nitrogen.26. The FZ silicon of claim 24 , comprising a wafer with a nominal ...

SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE COMPRISING A TRAP-RICH LAYER WITH SMALL GRAIN SIZES

Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate comprising a trap-rich layer with small grain sizes, as well as the resulting SOI substrate. In some embodiments, an amorphous silicon layer is deposited on a high-resistivity substrate. A rapid thermal anneal (RTA) is performed to crystallize the amorphous silicon layer into a trap-rich layer of polysilicon in which a majority of grains are equiaxed. An insulating layer is formed over the trap-rich layer. A device layer is formed over the insulating layer and comprises a semiconductor material. Equiaxed grains are smaller than other grains (e.g., columnar grains). Since a majority of grains in the trap-rich layer are equiaxed, the trap-rich layer has a high grain boundary area and a high density of carrier traps. The high density of carrier traps may, for example, reduce the effects of parasitic surface conduction (PSC). 1. A method for forming a semiconductor-on-insulator (SOI) substrate , the method comprising:depositing an amorphous silicon layer on a high-resistivity substrate;performing a rapid thermal anneal (RTA) to crystallize the amorphous silicon layer into a trap-rich layer of polysilicon in which a majority of grains are equiaxed;forming an insulating layer over the trap-rich layer; andforming a device layer over the insulating layer, wherein the device layer comprises a semiconductor material.2. The method according to claim 1 , wherein the performing of the RTA comprises:ramping up heating of the amorphous silicon layer at a ramp-up rate above about 75 degrees Celsius per second until a high temperature above about 600 degrees Celsius is reached.3. The method according to claim 2 , wherein the performing of the RTA comprises:ramping down heating of the amorphous silicon layer after heating the amorphous silicon layer for a short period of time less than about 10 seconds.4. The method according to claim 1 , wherein the ...

SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME

A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode. 1. A semiconductor memory comprising:a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate;a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate;a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate; andwherein the layers are patterned in self-alignment with each other,intersections of the active areas and the first gate electrode form a plurality of memory cells, andthe plurality of memory cells in an intersecting plane share the first gate electrode.2. The memory according to claim 1 , wherein the first and second gate electrodes are formed by one layer.3. The memory according to claim 1 , wherein the first and second gate electrodes are connected to interconnections and driven independently of each other.4. The memory according to claim 1 , wherein the second gate electrode is formed parallel to the active areas claim 1 , and shared by the plurality of memory cells in a plane parallel to the active areas and perpendicular to the substrate.5. The memory according to claim 1 , wherein a ...

Layered structure, semiconductor device including layered structure, and semiconductor system including semiconductor device

In a first aspect of a present inventive subject matter, a layered structure includes a first semiconductor layer including an ε-phase crystalline oxide semiconductor with a first composition, and a second semiconductor layer including an ε-phase crystalline oxide semiconductor with a second composition that is different from the first composition of the first semiconductor layer, and the second semiconductor layer is layered on the first semiconductor layer.

THIN FILM TRANSISTOR AND METHOD FOR FABRICATING THE SAME, DISPLAY DEVICE, EXPOSURE DEVICE

A thin film transistor, a method for fabricating the same, a display device, and an exposure device are disclosed. The method comprises: patterning a source and drain layer by using a single slit mask and an exposure machine, to form a source, a drain, and an active region of the thin film transistor; wherein a pattern resolution of the single slit mask is not larger than a resolution of the exposure machine to form a groove shaped exposure pattern, wherein the groove shaped exposure pattern corresponds to the active region. 1. A method for fabricating a thin film transistor , comprising:patterning a source and drain layer by using a single slit mask and an exposure machine, to form a source, a drain, and an active region of the thin film transistor;wherein a pattern resolution of the single slit mask is not larger than a resolution of the exposure machine to form a groove shaped exposure pattern, wherein the groove shaped exposure pattern corresponds to the active region.2. The method of claim 1 , wherein the step of patterning the source and drain layer by using the single slit mask and the exposure machine claim 1 , to form the source claim 1 , the drain claim 1 , and the active region of the thin film transistor comprises:coating a first photoresist on the source and drain layer;exposing and developing the first photoresist by using the single slit mask and the exposure machine according to a size of the source and the drain, so that the resulting first photoresist on the source and drain layer forms a groove shaped exposure pattern;ashing the first photoresist at a bottom of the groove shaped exposure pattern, to reveal the source and drain layer;wet etching the source and drain layer to form the source and the drain, and to reveal an active layer at a position to which the groove shaped exposure pattern corresponds to form the active region of the thin film transistor; andremoving the remaining first photoresist.3. The method of claim 2 , wherein the ashing is ...

MANUFACTURING METHOD OF POLYSILICON SEMICONDUCTOR LAYER,THIN FILM TRANSISTOR AND MANUFACTURING METHOD

A method for manufacturing a polysilicon semiconductor layer, a thin film transistor, and a manufacturing method are provided. The method for manufacturing a polysilicon semiconductor layer includes the following steps. A predetermined gas is dissociated, and a low amount of first ions and a high amount of second ions are screened out. A heavily doped region is doped with the second ions. A lightly doped region is doped with the first ions. Annealing is further performed, so that a polysilicon semiconductor layer is formed from an amorphous silicon layer. 1. A method for manufacturing a polysilicon semiconductor layer , comprising:{'b': '10', 'step S, dissociating a predetermined gas containing ions for use in ion-implantation, and screening dissociated ions for implantation to obtain a low amount of first ions and a high amount of second ions;'}{'b': '11', 'step S, doping a heavily doped region of an amorphous silicon layer with the second ions;'}{'b': '12', 'step S, doping a lightly doped region of the amorphous silicon layer with the first ions; and'}{'b': '13', 'step S, annealing the amorphous silicon layer so that the polysilicon semiconductor layer is formed from the amorphous silicon layer doped with the first ions and the second ions.'}2. The manufacturing method as claimed in claim 1 , further comprising:{'b': '101', 'sub': '3', 'sup': 2+', '3+', '+, 'step S, dissociating a gas containing BF, and screening out B/B ions and B ions;'}{'b': '111', 'sup': '+', 'step S, doping the heavily doped region of the amorphous silicon layer with B ions;'}{'b': '121', 'sup': 2+', '3+, 'step S, doping the lightly doped region of the amorphous silicon layer with B/B ions;'}{'b': '131', 'step S, annealing the amorphous silicon layer so that the polysilicon semiconductor layer is formed from the amorphous silicon layer.'}3. The manufacturing method as claimed in claim 1 , wherein the step of doping the amorphous silicon layer comprises bombarding a surface of the amorphous ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

An object is to provide a high reliability thin film transistor using an oxide semiconductor layer which has stable electric characteristics. In the thin film transistor in which an oxide semiconductor layer is used, the amount of change in threshold voltage of the thin film transistor before and after a BT test is made to be 2 V or less, preferably 1.5 V or less, more preferably 1 V or less, whereby the semiconductor device which has high reliability and stable electric characteristics can be manufactured. In particular, in a display device which is one embodiment of the semiconductor device, a malfunction such as display unevenness due to change in threshold voltage can be reduced. 1. (canceled)2. A method for manufacturing a semiconductor device , comprising:forming a gate electrode;forming a gate insulating layer over the gate electrode;forming an oxide semiconductor layer containing an In—Ga—Zn—O-based oxide semiconductor over the gate insulating layer,performing first heat treatment on the oxide semiconductor layer in an inert gas atmosphere to dehydrate or dehydrogenate the oxide semiconductor layer;forming source and drain electrodes over the oxide semiconductor layer;forming an inorganic insulating layer over the oxide semiconductor layer and the source and drain electrodes; andperforming second heat treatment on the inorganic insulating layer,wherein:in the In—Ga—Zn—O-based oxide semiconductor, a content of In is larger than or equal to a content of Ga, and a content of Zn is smaller than a sum of the content of In and the content of Ga.3. The method according to claim 2 , wherein the inert gas atmosphere is a nitrogen atmosphere or a rare gas atmosphere.4. The method according to claim 2 , wherein the first heat treatment is performed in a range of 350° C. and 750° C. claim 2 , inclusive.5. The method according to claim 2 , wherein the second heat treatment is performed in an air atmosphere claim 2 , an oxygen atmosphere claim 2 , a nitrogen atmosphere ...

Devices Having a Semiconductor Material That Is Semimetal in Bulk and Methods of Forming the Same

Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

HYDROGEN MANAGEMENT IN PLASMA DEPOSITED FILMS

Exemplary methods of semiconductor processing may include flowing a silicon-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region, and the substrate may be maintained at a temperature below or about 450° C. The methods may include striking a plasma of the silicon-containing precursor. The methods may include forming a layer of amorphous silicon on a semiconductor substrate. The layer of amorphous silicon may be characterized by less than or about 3% hydrogen incorporation. 1. A semiconductor processing method comprising:flowing a silicon-containing precursor into a processing region of a semiconductor processing chamber, wherein a substrate is housed within the processing region, and wherein the substrate is maintained at a temperature below or about 450° C.;striking a plasma of the silicon-containing precursor; andforming a layer of amorphous silicon on a semiconductor substrate, wherein the layer of amorphous silicon is characterized by less than or about 3% hydrogen incorporation.2. The semiconductor processing method of claim 1 , further comprising:flowing hydrogen into the processing region of the semiconductor processing chamber with the silicon-containing precursor.3. The semiconductor processing method of claim 2 , wherein the hydrogen is flowed at a flow rate of at least twice the flow rate of the silicon-containing precursor.4. The semiconductor processing method of claim 1 , further comprising:flowing a boron-containing precursor or a phosphorus-containing precursor into the processing region of the semiconductor processing chamber with the silicon-containing precursor.5. The semiconductor processing method of claim 1 , wherein the plasma is pulsed at a frequency of less than or about 10 kHz during the semiconductor processing method claim 1 , and wherein a duty cycle of plasma pulsing is less than or about 50%.6. The semiconductor processing method of claim 1 , further ...

Semiconductor assemblies with flexible substrates

Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a polycrystalline semiconductor material, and a polycrystalline dielectric disposed between and adjacent to the flexible substrate and the polycrystalline semiconductor material. The polycrystalline semiconductor material. The polycrystalline semiconductor material may include a polycrystalline III-V material, a polycrystalline II-VI material or polycrystalline germanium. Other embodiments may be disclosed and/or claimed.

Array Substrate and Manufacturing Method Thereof, Display Panel and Display Device

An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate, an active layer, and a first polarization structure. The active layer is disposed on the base substrate; the first polarization structure is disposed on a side of the active layer facing the base substrate, and an orthographic projection of the first polarization structure on the base substrate is at least partially overlapped with an orthographic projection of the active layer on the base substrate. 1. An array substrate , comprising:a base substrate;an active layer, disposed on the base substrate;a first polarization structure, disposed on a side of the active layer facing the base substrate, and an orthographic projection of the first polarization structure on the base substrate being at least partially overlapped with an orthographic projection of the active layer on the base substrate;a second polarization structure, laminated on the base substrate, and disposed on the side of the active layer facing the base substrate,wherein a polarization direction of the first polarization structure is substantially perpendicular to a polarization direction of the second polarization structure, and both of the orthographic projections of the active layer and the first polarization structure on the base substrate fall within an orthographic projection of the second polarization structure on the base substrate.2. The array substrate of claim 1 , wherein the first polarization structure is provided between the base substrate and the active layer.3. The array substrate of claim 1 , wherein the orthographic projection of the active layer on the base substrate falls within the orthographic projection of the first polarization structure on the base substrate.4. The array substrate of claim 3 , wherein the orthographic projection of the active layer on the base substrate substantially coincides with the orthographic projection of the first ...

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS

A method of manufacturing a polysilicon (poly-Si) layer, a method of manufacturing an organic light-emitting display apparatus using the method, and an organic light-emitting display apparatus manufactured by using the method. The method includes forming an amorphous silicon (a-Si) layer on a substrate having first and second areas, thermally treating the a-Si layer to partially crystallize the a-Si layer into a partially crystallized Si layer, removing a thermal oxide layer through a thermal treatment, selectively irradiating the first areas with laser beams to crystallize the partially crystallized Si layer. 1. A method of manufacturing a polysilicon (poly-Si) layer , the method comprising:forming an amorphous silicon (a-Si) layer on a substrate, the substrate having a first area and a second area;thermally treating the a-Si layer to convert the a-Si layer into a partially crystallized Si layer;removing a thermal oxide layer formed by the thermally treating of the a-Si layer; andselectively irradiating the first area with laser beams to crystallize the partially crystallized Si layer.2. The method of claim 1 , further comprising:forming a buffer layer on the substrate before the forming of the a-Si layer.3. The method of claim 1 , wherein the substrate has a plurality of first areas comprising the first area claim 1 , and a plurality of second areas comprising the second area claim 1 , and the plurality of first areas and the plurality of second areas alternate with each other and are spaced apart.4. The method of claim 1 , wherein a crystallinity of the partially crystallized Si layer is in a range between 65% and 80%.5. The method of claim 1 , wherein the thermally treating of the a-Si layer comprises:thermally treating the a-Si at a temperature between 650° C. and 780° C.;partially crystallizing the a-Si layer into the partially crystallized Si layer; andforming the thermal oxide layer on the partially crystallized Si layer.6. The method of claim 5 , wherein ...

METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING VARIABLE WIDTH FLOATING GATES

A semiconductor device includes a substrate including an active region defined by a device isolation pattern and a floating gate on the active region. The floating gate includes an upper portion, a lower portion having a width greater than a width of the upper portion, and a step-difference portion between the upper portion and the lower portion. A dielectric pattern is on the floating gate, and a control gate is on the dielectric pattern. The lower portion of the floating gate has a height of about 4 nm or more. 1. A method of manufacturing a semiconductor device , the method comprising:forming a poly-silicon layer on a substrate;successively patterning the poly-silicon layer and the substrate to form a poly-silicon pattern and a trench;forming a device isolation pattern in the trench and extending on a sidewall of a lower portion of the poly-silicon pattern;performing a thermal treatment process on the poly-silicon pattern exposed by the device isolation pattern under an atmosphere of a reaction gas including first dopants of a p-type and an etching material;sequentially forming a dielectric layer and a conductive layer on the poly-silicon pattern and the device isolation pattern; andsuccessively patterning the conductive layer, the dielectric layer, and the poly-silicon pattern to form a control gate, a dielectric pattern, and a floating gate.2. The method of claim 1 , wherein the poly-silicon layer formed on the substrate includes poly-silicon doped with second dopants of the p-type.3. The method of claim 2 , wherein the first and the second dopants are boron (B).4. The method of claim 1 , wherein the reaction gas includes chlorine (Cl) or fluorine (F).5. The method of claim 1 , wherein the reaction gas includes BClor BF.6. The method of claim 1 , wherein the reaction gas further includes nitrogen (N) gas.7. The method of claim 1 , wherein the thermal treatment process is performed on the poly-silicon pattern at a temperature of about 500 degrees Celsius or more ...

SEMICONDUCTOR STRUCTURES AND FABRICATION METHOD THEREOF

A method is provided for fabricating a semiconductor structure. The method includes providing a substrate having an upper surface and a bottom surface; and forming a deep hole in the substrate from the upper surface. The method also includes forming an amorphous silicon layer on a side surface and a bottom surface of the deep hole to promote a preferred crystal orientation in subsequently formed layers. Further, the method includes forming a barrier layer having a preferred orientation along the (111) crystal face on the barrier layer. Further, the method also includes forming a metal layer having a preferred orientation along the (111) crystal face on the barrier layer to fill the through hole. 1. A method for fabricating a semiconductor structure , comprising:providing a substrate having an upper surface and a bottom surface;forming a deep hole in the substrate from the upper surface;forming an amorphous silicon layer on a side surface and a bottom surface of the deep hole to promote a preferred crystal orientation in subsequently formed layers;forming a barrier layer having a preferred orientation along a (111) crystal face; andforming a metal layer having a preferred orientation along the (111) crystal face on the barrier layer to fill the deep hole.2. The method according to claim 1 , wherein:the barrier layer is made of TiN, TaN, or Ta.3. The method according to claim 2 , wherein:the barrier layer is formed by a chemical vapor deposition process.4. The method according to claim 3 , wherein:the barrier layer is made of TiN;{'sub': '2', 'a reaction gas of the chemical vapor deposition process for forming the barrier layer includes a titanium source gas, a nitrogen source gas and H;'}{'sub': '4', 'the titanium source gas is TiCl;'}{'sub': '2', 'the nitrogen source gas is N;'}a flow rate of the titanium source gas is in a range of approximately 20 sccm˜200 sccm;a flow rate of the nitrogen source gas is in a range of approximately 20 sccm˜200 sccm;{'sub': '2', 'a ...

SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE

A method for manufacturing a semiconductor device may include the following steps: providing a semiconductor substrate structure; providing a substrate-connecting barrier layer on the semiconductor substrate structure; performing one or more iterations of a composite-layer formation process to provide a gate-connecting barrier layer, wherein the composite-layer formation process comprises: applying a silicon-containing compound set to an outmost existing barrier layer to form an amorphous silicon layer, and forming an overlying barrier layer on the amorphous silicon layer, wherein the substrate-connecting barrier layer is the outmost existing barrier layer for a first iteration of the one or more iterations, and wherein the gate-connecting barrier layer is the overlying barrier layer resulted from a last iteration of the one or more iterations; and providing a conductive gate layer on the gate-connecting barrier layer. 1. A method for manufacturing a semiconductor device , the method comprising:providing a semiconductor substrate structure;providing a substrate-connecting barrier layer on the semiconductor substrate structure;performing one or more iterations of a composite-layer formation process to provide a gate-connecting barrier layer, wherein the composite-layer formation process comprises: applying a silicon-containing compound set to an outmost existing barrier layer to form an amorphous silicon layer, and forming an overlying barrier layer on the amorphous silicon layer, wherein the substrate-connecting barrier layer is the outmost existing barrier layer for a first iteration of the one or more iterations, and wherein the gate-connecting barrier layer is the overlying barrier layer resulted from a last iteration of the one or more iterations; andproviding a conductive gate layer on the gate-connecting barrier layer.2. The method of claim 1 , wherein a material of the substrate-connecting barrier layer is same as a material of the gate-connecting barrier ...

Integration of air-sensitive two-dimensional materials on arbitrary substrates for the manufacturing of electronic devices

A field-effect transistor and method for fabricating such a field-effect transistor that utilizes an air-sensitive two-dimensional material (e.g., silicene). A film of air-sensitive two-dimensional material is deposited on a crystalized metallic (e.g., Ag) thin film on a substrate (e.g., mica substrate). A capping layer of insulating material (e.g., aluminum oxide) is deposited on the air-sensitive two-dimensional material. The substrate is detached from the metallic thin film/air-sensitive two-dimensional material/insulating material stack structure. The metallic thin film/air-sensitive two-dimensional material/insulating material stack structure is then flipped. The flipped metallic thin film/air-sensitive two-dimensional material/insulating material stack structure is attached to a device substrate followed by having the metallic thin film etched to form contact electrodes. In this manner, the pristine properties of air-sensitive two-dimensional materials are preserved from degradation when exposed to air. Furthermore, this new technique allows safe transfer and device fabrication of air-sensitive two-dimensional materials with a low material and process cost.

Manufacturing method of array substrate, array substrate and display device

A manufacturing method of an array substrate, an array substrate and a display device are provided. The method includes: forming a first electrode; forming a first insulation layer on the first electrode; forming a first via hole in the first insulation layer; forming an active layer on the first insulation layer, which is electrically connected with the first electrode through the first via hole; forming a gate insulation layer on the active layer; forming a first gate electrode on the gate insulation layer, which overlaps with at least part of the active layer; forming a second insulation layer on the first gate electrode and the gate insulation layer, forming a second via hole in the second insulation layer and the gate insulation layer; forming a pixel electrode on the second insulation layer, which is electrically connected with the active layer through the second via hole.

METHOD AND SYSTEM FOR FABRICATING A SEMICONDUCTOR DEVICE

The present disclosure provides a method and system for fabricating a semiconductor device. The method and system of the present disclosure, after obtaining the polysilicon layer, first form the protective oxide layer on the surface of the polysilicon layer, and then etch the protective oxide layer and the protrusions on the surface of the polysilicon layer with the buffered oxide etchant based on controllability of the buffered oxide etchant, thereby reducing the protrusions on the surface of the polysilicon layer, while well protecting the surface of the polysilicon layer. Therefore, the technical problem of surface roughness in the existing polysilicon layers is solved. 1. A method for fabricating a semiconductor device , comprising:depositing a polysilicon layer on a device layer;forming an oxide layer on a surface of the polysilicon layer, the oxide layer covering protrusions on the surface of the polysilicon layer;etching the oxide layer with a buffered oxide etchant; andforming a functional layer on the surface of the polysilicon layer obtained by etching to obtain the semiconductor device.2. The method according to claim 1 , wherein the forming the oxide layer on the surface of the polysilicon layer comprises: depositing an oxide on the surface of the polysilicon layer by chemical vapor deposition to form the oxide layer.3. The method according to claim 2 , wherein the depositing the oxide on the surface of the polysilicon layer comprises: depositing silicon oxide on the surface of the polysilicon layer.4. The method according to claim 1 , wherein the depositing the polysilicon layer on the device layer comprises: forming an amorphous silicon layer on the device layer claim 1 , and processing the amorphous silicon layer by excimer laser annealing to form the polysilicon layer.5. The method according to claim 4 , wherein the forming the oxide layer on the surface of the polysilicon layer comprises: forming an oxide layer having a thickness of 20 nm on the ...

Method of preparing an isolation region in a high resistivity silicon-on-insulator substrate

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

THIN FILM TRANSISTOR, DISPLAY APPARATUS INCLUDING THE SAME, AND MANUFACTURING METHODS THEREOF

A method of manufacturing a thin film transistor includes: removing an oxide film on a surface of an amorphous silicon layer by performing a surface cleaning; and forming an active layer by performing a heat treatment on the amorphous silicon layer, where the amorphous silicon layer is changed into crystalline silicon by the heat treatment. 1. A method of manufacturing a thin film transistor , the method comprising:providing an amorphous silicon layer over a substrate;removing an oxide film on a surface of the amorphous silicon layer by performing a surface cleaning; andforming an active layer by performing a heat treatment on the amorphous silicon layer, wherein the amorphous silicon layer is changed into crystalline silicon by the heat treatment.2. The method of claim 1 , wherein the removing the oxide film on the surface of the amorphous silicon layer by performing the surface cleaning comprises spraying a hydrogen fluoride solution onto the surface of the amorphous silicon layer.3. The method of claim 2 , wherein the hydrogen fluoride solution comprises about 0.5 vol % of hydrogen fluoride.4. The method of claim 2 , wherein the removing the oxide film on the surface of the amorphous silicon layer by performing the surface cleaning further comprisesperforming a first rinse cleaning including supplying hydrogen water to the surface of the amorphous silicon layer in a free fall manner.5. The method of claim 4 , wherein the removing the oxide film on the surface of the amorphous silicon layer by performing the surface cleaning further comprisesperforming a second rinse cleaning including supplying hydrogen water to the surface of the amorphous silicon layer in a free fall manner while applying vibration to the hydrogen water with megasonic waves.6. The method of claim 1 , wherein the forming the active layer comprises:radiating a laser beam onto the amorphous silicon layer arranged over the substrate, wherein the laser beam has long sides and short sides in a first ...

GROUP 13 ELEMENT NITRIDE LAYER, FREE-STANDING SUBSTRATE, FUNCTIONAL ELEMENT, AND METHOD OF PRODUCING GROUP 13 ELEMENT NITRIDE LAYER

A group 13 nitride layer is composed of a polycrystalline group 13 nitride and is constituted by a plurality of monocrystalline particles having a particular crystal orientation approximately in a normal direction. The group 13 nitride comprises gallium nitride, aluminum nitride, indium nitride or the mixed crystal thereof. The group 13 nitride layer includes an upper surface and a bottom surface, and a full width at half maximum of a (1000) plane reflection of X-ray rocking curve on the upper surface is 20000 seconds or less and 1500 seconds or more. 1. A group 13 nitride layer comprising a polycrystalline group 13 nitride ,said group 13 nitride layer comprising a plurality of monocrystalline particles having a particular crystal orientation approximately in a normal direction,wherein said group 13 nitride comprises gallium nitride, aluminum nitride, indium nitride or the mixed crystal thereof,wherein said group 13 nitride layer comprises an upper surface and a bottom surface, andwherein a full width at half maximum of a (1000) plane reflection of an X-ray rocking curve on said upper surface is 20000 seconds or more and 1500 seconds or less.2. The group 13 nitride layer of claim 1 ,wherein said monocrystalline particles exposed to said upper surface of said group 13 nitride layer is communicated with said bottom surface of said group 13 nitride layer without intervening a particle boundary, andwherein a ratio DT/DB of an average cross-sectional diameter DT at outermost surfaces of said monocrystalline particles exposed to said upper surface of said group 13 nitride layer with respect to an average cross-sectional diameter DB at outermost surfaces of said monocrystalline particles exposed to said bottom surface of said group 13 nitride layer exceeds 1.0.3. The group 13 nitride layer of claim 2 , wherein said average cross-sectional diameter DT at said outermost surfaces of said monocrystalline particles exposed to said upper surface is 10 μm or larger.4. The group ...

HYBRID THIN FILM TRANSISTOR STRUCTURE, DISPLAY DEVICE, AND METHOD OF MAKING THE SAME

A display device, and method for manufacture, having a substrate; a first thin film transistor (TFT) on the substrate, the first TFT having a first active layer, a first gate insulator, and a first gate electrode; a second TFT on the substrate, the second TFT having a second active layer, a second gate insulator and a second gate electrode. The first gate insulator is disposed between the first gate electrode and the first active layer, and the first gate insulator is in contact with the first active layer. The second gate insulator is disposed between the second gate electrode and the second active layer, and the second gate insulator is in contact with the second active layer. The first active layer is a different material than said second active layer, and a hydrogen concentration of the second gate insulator is less than a hydrogen concentration of the first gate insulator. 1. A method for making a display , comprising the steps of:forming a first active layer over a substrate;forming a first gate insulator over said first active layer;forming a second active layer over said substrate;forming a first gate electrode and a second gate electrode over said first gate insulator;forming a second gate insulator over said second active layer;forming a first source electrode and a first drain electrode over said first active layer; andforming a second source electrode and a second drain electrode over said second active layer,wherein said first active layer, said first source electrode, said first drain electrode, and said first gate electrode form a first thin film transistor, and said second active layer, said second source electrode, said second drain electrode, and said second gate electrode form a second thin film transistor,wherein a material of said first active layer is different from a material of said second active layer.2. The method for making a display as claimed in claim 1 , wherein said first gate electrode and said second gate electrode are formed by the ...

MEMORY TRANSISTOR WITH MULTIPLE CHARGE STORING LAYERS AND A HIGH WORK FUNCTION GATE ELECTRODE

An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride. 1. (canceled)2. A semiconductor device comprising: a tunnel dielectric layer over a channel region formed from a silicon containing layer projecting from a surface of a substrate, and comprising silicon oxynitride;', 'a channel region electrically connecting a source region and a drain region, the channel region comprising polysilicon;', an oxygen-rich first nitride layer of which silicon and nitrogen content increases toward a second nitride layer interface side within the oxygen-rich first nitride layer; and', 'an oxygen-lean second nitride layer disposed abutting the oxygen-rich first nitride layer of which a content of nitrogen is greater than the oxygen-rich first nitride layer; and, 'a multi stack charge trap layer comprising an oxide-nitride-nitride-oxide (ONNO) stack disposed above the channel region, the ONNO stack comprising a multi-layer charge-trapping region including, 'a blocking dielectric layer disposed abutting the second nitride layer interface side, and comprising a multi stack layer including a silicon containing layer and a high K dielectric layer; and', 'a high work function gate electrode formed over a surface of the ONNO stack; and, 'a memory transistor includinga metal oxide semiconductor (MOS) logic transistor on the substrate, wherein the MOS logic transistor comprises a gate oxide ...

SEMICONDUCTOR STRUCTURE AND METHODS FOR CRYSTALLIZING METAL OXIDE SEMICONDUCTOR LAYER

The present invention provides two methods for crystallizing a metal oxide semiconductor layer and a semiconductor structure. The first crystallization method is treating an amorphous metal oxide semiconductor layer including indium with oxygen at a pressure of about 550 mtorr to about 5000 mtorr and at a temperature of about 200° C. to about 750° C. The second crystallization method is, firstly, sequentially forming a first amorphous metal oxide semiconductor layer, an aluminum layer, and a second amorphous metal oxide semiconductor layer on a substrate, and, secondly, treating the first amorphous metal oxide semiconductor layer, the aluminum layer, and the second amorphous metal oxide semiconductor layer with an inert gas at a temperature of about 350° C. to about 650° C. 1. A method for crystallizing a metal oxide semiconductor layer , comprising:forming a first amorphous metal oxide semiconductor layer on a substrate;forming an aluminum layer on the first amorphous metal oxide semiconductor layer;forming a second amorphous metal oxide semiconductor layer on the aluminum layer; andtreating the first amorphous metal oxide semiconductor layer, the aluminum layer, and the second amorphous metal oxide semiconductor layer with an inert gas at a temperature of about 350° C. to about 650° C.2. The method according to claim 1 , wherein the inert gas comprises nitrogen gas claim 1 , helium gas claim 1 , neon gas claim 1 , argon gas claim 1 , krypton gas claim 1 , xenon gas claim 1 , radon gas or a combination thereof.3. The method according to claim 1 , wherein the first amorphous metal oxide semiconductor layer and the second amorphous metal oxide semiconductor layer independently comprise indium gallium zinc oxide claim 1 , indium tin zinc oxide claim 1 , hafnium indium zinc oxide or indium zinc oxide.4. A semiconductor structure claim 1 , comprising:a substrate;a gate, configured on the substrate;a gate insulation layer, located on the gate;a first crystallized metal ...

Wafer producing method

A hexagonal single crystal wafer is produced from a hexagonal single crystal ingot. The depth of the focal point of a laser beam is gradually changed from a shallow position not reaching the depth corresponding to the desired thickness of the wafer to a deep position corresponding to the desired thickness of the wafer in such a manner that a parabola is described by the path of the focal point. When the spot area of the laser beam on the upper surface of the ingot becomes a predetermined maximum value, the deep position of the focal point is maintained.

EPITAXIAL GROWTH OF DOPED FILM FOR SOURCE AND DRAIN REGIONS

Embodiments of mechanisms for epitaxially growing one or more doped silicon-containing materials to form source and drain regions of finFET devices are provided in this disclosure. The dopants in the one or more doped silicon-containing materials can be driven into the neighboring lightly-doped-drain (LDD) regions by thermal anneal to dope the regions. The epitaxially growing process uses a cyclical deposition/deposition/etch (CDDE) process. In each cycle of the CDDE process, a first and a second doped materials are formed and a following etch removes most of the second doped material. The first doped material has a higher dopant concentration than the second material and is protected from the etching process by the second doped material. The CDDE process enables forming a highly doped silicon-containing material. 1. A method comprising:providing a semiconductor substrate with fins and gate structures;forming spacers on each of the gate structures;etching portions of the fins not covered by the gate structures to form recesses in the fins below exposed surfaces of isolation structures between the fins, wherein the recesses are below surfaces of isolation structures neighboring the fins; andforming doped source and drain regions for the gate structures by epitaxially growing at least one silicon-containing material from the recesses, wherein a cyclic deposition-deposition-etch (CDDE) process is used for the epitaxially growing, and wherein each cycle of the CDDE process forms a first doped epitaxial material during a first deposition step and a second doped epitaxial material during a second deposition step subsequent to the first deposition step, a first dopant concentration of the first doped epitaxial material being different from a second dopant concentration of the second doped epitaxial material, wherein a portion of the second doped epitaxial material is removed an etch process in each cycle of the CDDE process.2. The method of claim 1 , further comprising ...

METHOD AND APPARATUS TO REDUCE CONTAMINATION OF PARTICLES IN A FLUIDIZED BED REACTOR

A method and fluidized bed reactor for reducing or eliminating contamination of silicon-coated particles are disclosed. The metal surface of one or more fluidized bed reactor components is at least partially coated with a hard protective layer comprising a material having an ultimate tensile strength of at least 700 MPa at 650° C. 1. A method of reducing or eliminating contamination of silicon-coated particles due to contact with a surface in a fluidized bed reactor , the method comprising:providing, in a fluidized bed reactor, a fluidized bed reactor component having a surface facing silicon-coated particles during operation of the fluidized bed reactor, wherein the surface comprises metal that is at least partially coated with a protective layer comprising a material having an ultimate tensile strength of at least 700 MPa at 650° C.; andoperating the fluidized bed reactor to make silicon-coated particles.2. The method of claim 1 , wherein at least 95% of the surface is coated with the protective layer.3. The method of claim 1 , wherein the metal has a thermal coefficient of expansion claim 1 , TCE-1 claim 1 , and the protective layer has a thermal coefficient of expansion claim 1 , TCE-2 claim 1 , wherein TCE-2 and TCE-1 differ by ≦30%.4. The method of claim 3 , wherein an intermediate coating having a thermal coefficient of expansion claim 3 , TCE-3 claim 3 , between TCE-1 and TCE-2 is disposed between the metal and the protective layer.5. The method of claim 1 , wherein the protective layer has a minimum average thickness of 0.1 mm.6. The method of claim 5 , wherein the protective layer has a thickness that varies across a width and/or along a length of the surface.7. The method of claim 1 , wherein the protective layer comprises a cobalt-based alloy claim 1 , a nickel-based alloy claim 1 , or a combination thereof.8. The method of claim 7 , wherein the protective layer is a cobalt-based alloy comprising 25-35% Cr claim 7 , ≦10% W claim 7 , ≦10% Ni claim 7 , ≦5% ...

Method for making silicon-germanium absorbers for thermal sensors

A system and method for growing polycrystalline silicon-germanium film that includes mixing a GeH 4 gas and a SiH 4 gas to coat and grow polycrystalline silicon-germanium film on a silicon wafer. The GeH 4 gas and the SiH 4 gas are also heated and the pressure around the wafer is reduced to at least 2.5*10 −3 mBar to produce the polycrystalline silicon-germanium film. The polycrystalline silicon-germanium film is then annealed to improve its resistivity.

PROCESS FOR FORMING SILICON-FILLED OPENINGS WITH A REDUCED OCCURRENCE OF VOIDS

In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated.

PROCESS FOR FORMING SILICON-FILLED OPENINGS WITH A REDUCED OCCURRENCE OF VOIDS

In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated.

METAL-INDUCED CRYSTALLIZATION OF AMORPHOUS SILICON IN AN OXIDIZING ATMOSPHERE

Techniques are provided for forming thin film transistors having a polycrystalline silicon active layer formed by metal-induced crystallization (MIC) of amorphous silicon in an oxidizing atmosphere. In an aspect, a transistor device, is provided that includes a source region and a drain region formed on a substrate, and an active channel region formed on the substrate and electrically connecting the source region and the drain region. The active channel region is formed with a polycrystalline silicon layer having resulted from annealing an amorphous silicon layer formed on the substrate and having a metal layer formed thereon, wherein the annealing of the amorphous silicon layer was at least partially performed in an oxidizing ambience, thereby resulting in crystallization of the amorphous silicon layer to form the polycrystalline silicon layer.

Manufacture Method Of Low Temperature Poly Silicon, Manufacturing Method Of TFT Substrate Utilizing The Method, And TFT Substrate Structure

The present invention provides a manufacture method of Low Temperature Poly Silicon, a manufacture method of a TFT substrate utilizing the method and a TFT substrate structure. The manufacture method of Low Temperature Poly Silicon comprises steps of: step 1, providing a substrate ( 1 ); step 2, depositing a buffer layer ( 2 ) on the substrate ( 1 ); step 3, patterning the buffer layer ( 2 ) to form a convex part ( 21 ) and a concave part ( 23 ) having different thicknesses; step 4, depositing an amorphous silicon layer ( 3 ) on the buffer layer ( 2 ) comprising the convex part ( 21 ) and the concave part ( 23 ); step 5, implementing a pretreatment of an excimer laser anneal to the amorphous silicon layer ( 3 ); step 6, implementing the excimer laser anneal to the amorphous silicon layer ( 3 ), and a laser beam scans an entire surface of the amorphous silicon layer ( 3 ) to melt the amorphous silicon layer ( 3 ) to recrystallize as a poly silicon layer ( 4 ). The method is capable of effectively controlling the locations and the directions of the recrystallization.

LITHOGRAPHY USING INTERFACE REACTION

A method of forming a semiconductor structure by; forming a first mask trench in a first mask, where the first mask is on a substrate; forming a second mask in the first mask trench; and forming a third mask between the first mask and the second mask by reacting the first mask with the second mask, where the first mask, the second mask, and the third mask all have different etching properties. 1. A method of forming a semiconductor structure comprising:forming a first mask trench in a first mask, wherein the first mask is on a substrate;forming a second mask in the first mask trench; andforming a third mask at a vertical interface between the first mask and the second mask using a diffusion process, wherein the third mask extends into a portion of the first mask and into a portion of the second mask.2. The method of claim 1 , wherein the first mask trench exposes the substrate.3. The method of claim 1 , further comprising:polishing the second mask exposing the first mask.4. The method of claim 1 , wherein the diffusion process includes an annealing process.5. The method of claim 1 , wherein the diffusion process includes a plasma reaction.6. The method of claim 1 , wherein the first mask is poly silicon claim 1 , the second mask is poly germanium claim 1 , and the third mask is poly silicon germanium.7. The method of claim 1 , further comprising: forming a first pattern by removing a portion of the first mask selective to the second mask and the third mask;', 'forming a second pattern by removing a portion of the second mask selective to the first mask and the third mask; and', 'transferring the transfer pattern from the post-reaction layer into the substrate, wherein the transfer pattern includes the first pattern and the second pattern., 'forming a transfer pattern in a post-reaction layer, the post-reaction layer comprising the first mask, the second mask, and the third mask, and forming the transfer pattern further comprising8. A method of forming a ...

SEMICONDUCTOR SUBSTRATES AND METHODS FOR PROCESSING SEMICONDUCTOR SUBSTRATES

Semiconductor substrates and methods for fabricating integrated circuits are provided. A method for fabricating an integrated circuit includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region. The semiconductor substrate also has an upper surface. The method includes forming an amorphous material over the upper surface of the semiconductor substrate in the peripheral region. Also, the method includes irradiating the upper surface of the semiconductor substrate, wherein the amorphous material inhibits cracking at the outer edge of the semiconductor substrate. 1. A method for processing a semiconductor substrate , the method comprising:providing the semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region, wherein the semiconductor substrate has an upper surface;forming an amorphous material directly on the upper surface of the semiconductor substrate in the peripheral region;irradiating the upper surface of the semiconductor substrate; andinhibiting cracking at the outer edge of the semiconductor substrate with the amorphous material.2. The method of wherein providing the semiconductor substrate comprises providing the semiconductor substrate with the upper surface formed entirely by a semiconductor material claim 1 , wherein forming the amorphous material directly on the upper surface of the semiconductor substrate in the peripheral region comprises forming the amorphous material only on the semiconductor material.3. The method of further comprising implanting dopant ions into the upper surface of the semiconductor substrate including into the central region and peripheral region of the semiconductor substrate before forming the amorphous material directly on the upper surface.4. (canceled)5. The method of wherein forming the amorphous material directly on the upper surface of the semiconductor ...

FABRICATION METHOD FOR A 3-DIMENSIONAL NOR MEMORY ARRAY

A process for manufacturing a 3-dimensional memory structure includes: (a) providing one or more active layers over a planar surface of a semiconductor substrate, each active layer comprising (i) first and second semiconductor layers of a first conductivity; (ii) a dielectric layer separating the first and second semiconductor layer; and (ii) one or more sacrificial layers, at least one of sacrificial layers being adjacent the first semiconductor layer; (b) etching the active layers to create a plurality of active stacks and a first set of trenches each separating and exposing sidewalls of adjacent active stacks; (c) filling the first set of trenches by a silicon oxide; (d) patterning and etching the silicon oxide to create silicon oxide columns each abutting adjacent active stacks and to expose portions of one or more sidewalls of the active stacks; (e) removing the sacrificial layers from exposed portions of the sidewalls by isotropic etching through the exposed portions of the sidewalls of the active stacks to create corresponding cavities in the active layers; (f) filling the cavities in the active stacks by a metallic or conductor material; (g) recessing the dielectric layer from the exposed sidewalls of the active stacks; and (h) filling recesses in the dielectric layer by a third semiconductor layer of a second conductivity opposite the first conductivity. 1. A process for forming a memory structure over a planar surface of a semiconductor substrate , comprising:forming above the semiconductor substrate a plurality of active stacks placed substantially at predetermined positions along a first direction that is substantially parallel to the planar surface, separated one from another by a first electrically insulative material, each active stack extending lengthwise along a second direction that is (i) substantially parallel to the planar surface and (ii) substantially orthogonal the first direction, wherein (i) each active stack comprises a plurality of active ...

Transistor Gate Structures and Methods of Forming the Same

In an embodiment, a device includes: an isolation region; nanostructures protruding above a top surface of the isolation region; a gate structure wrapped around the nanostructures, the gate structure having a bottom surface contacting the isolation region, the bottom surface of the gate structure extending away from the nanostructures a first distance, the gate structure having a sidewall disposed a second distance from the nanostructures, the first distance less than or equal to the second distance; and a hybrid fin on the sidewall of the gate structure. 1. A device comprising:an isolation region;nanostructures protruding above a top surface of the isolation region;a gate structure wrapped around the nanostructures, the gate structure having a bottom surface contacting the isolation region, the bottom surface of the gate structure extending away from the nanostructures a first distance, the gate structure having a sidewall disposed a second distance from the nanostructures, the first distance less than or equal to the second distance; anda hybrid fin on the sidewall of the gate structure.2. The device of claim 1 , wherein the first distance is less than the second distance.3. The device of claim 2 , wherein the hybrid fin extends into a sidewall recess of the gate structure.4. The device of claim 1 , wherein the first distance is equal to the second distance.5. The device of claim 1 , wherein the first distance and the second distance are each in a range of 0.5 nm to 30 nm.6. The device of further comprising:a protective layer disposed between the hybrid fin and the gate structure, the protective layer covering an upper portion of the sidewall of the gate structure, a lower portion of the sidewall of the gate structure uncovered by the protective layer.7. A device comprising:an isolation region;a semiconductor fin protruding above a top surface of the isolation region;nanostructures over the semiconductor fin;a gate structure wrapped around the nanostructures; anda ...