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24-01-2017 дата публикации

Backside illuminated image sensor

Номер: US0009553122B2

Автор: Jaroslav Hynecek, Leonard Forbes, Homayoon Haddad, Thomas Joy, HYNECEK JAROSLAV, FORBES LEONARD, HADDAD HOMAYOON, JOY THOMAS, Hynecek Jaroslav, Forbes Leonard, Haddad Homayoon, Joy Thomas

Принадлежит: INTELLECTUAL VENTURES II LLC, Intellectual Ventures II LLC

A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer disposed on the backside passivation layer.

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Номер записи: 1

15-11-2016 дата публикации

Process module for increasing the response of backside illuminated photosensitive imagers and associated methods

Номер: US0009496308B2

Автор: Homayoon Haddad, Jeffrey McKee, Jutao Jiang, Drake Miller, Chintamani Palsule, Leonard Forbes, HADDAD HOMAYOON, MCKEE JEFFREY, JIANG JUTAO, MILLER DRAKE, PALSULE CHINTAMANI, FORBES LEONARD, Haddad Homayoon, McKee Jeffrey, Jiang Jutao, Miller Drake, Palsule Chintamani, Forbes Leonard

Принадлежит: SiOnyx, LLC, HADDAD HOMAYOON, MCKEE JEFFREY, JIANG JUTAO, MILLER DRAKE, PALSULE CHINTAMANI, FORBES LEONARD, SIONYX LLC, Haddad Homayoon, McKee Jeffrey, Jiang Jutao, Miller Drake, Palsule Chintamani, Forbes Leonard

Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation where the textured region includes surface features sized and positioned to facilitate tuning to a preselected wavelength of light, and a dielectric region positioned between the textured region and the at least one junction. The dielectric region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction.

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Номер записи: 2

08-08-2012 дата публикации

Photosensitive imaging devices and associated methods

Номер: CN102630341A

Автор: Haddad Homayoon, Jiang Jutao, Mckee Jeffrey, Miller Drake, Forbes Leonard, Palsule Chintamani

Принадлежит:

Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor substrate having multiple doped regions forming at least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and an electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least one junction. In one aspect, the textured region is operable to facilitate generation of an electrical signal from the detection of infrared electromagnetic radiation. In another aspect, interacting with electromagnetic radiation further includes increasing the semiconductor substrate's effective absorption wavelength as compared to a semiconductor substrate lacking a textured region.

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Номер записи: 3

14-09-2017 дата публикации

PROCESS MODULE FOR INCREASING THE RESPONSE OF BACKSIDE ILLUMINATED PHOTOSENSITIVE IMAGERS AND ASSOCIATED METHODS

Номер: US20170263671A1

Автор: Homayoon Haddad, Jeffrey McKee, Jutao Jiang, Drake Miller, Chintamani Palsule, Leonard Forbes, HADDAD HOMAYOON, MCKEE JEFFREY, JIANG JUTAO, MILLER DRAKE, PALSULE CHINTAMANI, FORBES LEONARD, Haddad Homayoon, McKee Jeffrey, Jiang Jutao, Miller Drake, Palsule Chintamani, Forbes Leonard

Принадлежит: SiOnyx LLC

Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation where the textured region includes surface features sized and positioned to facilitate tuning to a preselected wavelength of light, and a dielectric region positioned between the textured region and the at least one junction. The dielectric region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction.

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Номер записи: 4

26-01-2017 дата публикации

PROCESS MODULE FOR INCREASING THE RESPONSE OF BACKSIDE ILLUMINATED PHOTOSENSITIVE IMAGERS AND ASSOCIATED METHODS

Номер: US20170025467A1

Автор: Homayoon Haddad, Jeffrey McKee, Jutao Jiang, Drake Miller, Chintamani Palsule, Leonard Forbes, HADDAD HOMAYOON, MCKEE JEFFREY, JIANG JUTAO, MILLER DRAKE, PALSULE CHINTAMANI, FORBES LEONARD, Haddad Homayoon, McKee Jeffrey, Jiang Jutao, Miller Drake, Palsule Chintamani, Forbes Leonard

Принадлежит:

Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation where the textured region includes surface features sized and positioned to facilitate tuning to a preselected wavelength of light, and a dielectric region positioned between the textured region and the at least one junction. The dielectric region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction. 116-. (canceled)17. A method of making a backside-illuminated photosensitive imager device , comprising:forming at least one junction at a surface of a semiconductor substrate;forming a dielectric region over the at least one junction;forming a textured region over the dielectric region, wherein the textured region includes surface features sized and positioned to facilitate tuning to a preselected wavelength of light, wherein the dielectric region isolates the at least one junction from the textured region, and wherein the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region; andcoupling an electrical transfer element to the semiconductor substrate such that the electrical transfer element is operable to transfer an electrical signal from the at least one junction.18. The method of ...

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Номер записи: 5

21-09-2017 дата публикации

PHOTOSENSITIVE IMAGING DEVICES AND ASSOCIATED METHODS

Номер: US20170271391A1

Автор: Homayoon Haddad, Jeffrey McKee, Jutao Jiang, Chintamani Palsule, Leonard Forbes, HADDAD HOMAYOON, MCKEE JEFFREY, JIANG JUTAO, PALSULE CHINTAMANI, FORBES LEONARD, Haddad Homayoon, McKee Jeffrey, Jiang Jutao, Palsule Chintamani, Forbes Leonard

Принадлежит: Siony LLC, SiOnyx LLC

Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and a passivation region positioned between the textured region and the at least one junction. The passivation region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation to passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction.

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Номер записи: 6

22-11-2016 дата публикации

ZrAION films

Номер: US0009502256B2

Автор: Kie Y. Ahn, Leonard Forbes, AHN KIE Y, FORBES LEONARD, Ahn Kie Y., Forbes Leonard

Принадлежит: Micron Technology, Inc., MICRON TECHNOLOGY INC

Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. The dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric, and a tunnel gate insulator in flash memories.

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Номер записи: 7

28-02-2017 дата публикации

Gallium lanthanide oxide films

Номер: US0009583334B2

Автор: Kie Y. Ahn, Leonard Forbes, AHN KIE Y, FORBES LEONARD, Ahn Kie Y., Forbes Leonard

Принадлежит: Micron Technology, Inc., MICRON TECHNOLOGY INC

Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The gallium lanthanide oxide film may be structured as one or more monolayers. The gallium lanthanide oxide film may be formed using atomic layer deposition.

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Номер записи: 8

24-01-2017 дата публикации

Vertically base-connected bipolar transistor

Номер: US0009553177B2

Автор: Badih El-Kareh, Leonard Forbes, Kie Y. Ahn, EL-KAREH BADIH, FORBES LEONARD, AHN KIE Y, El-Kareh Badih, Forbes Leonard, Ahn Kie Y.

Принадлежит: Micron Technology, Inc., MICRON TECHNOLOGY INC

Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor.

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Номер записи: 9

30-05-2017 дата публикации

Process module for increasing the response of backside illuminated photosensitive imagers and associated methods

Номер: US0009666636B2

Автор: Homayoon Haddad, Jeffrey McKee, Jutao Jiang, Drake Miller, Chintamani Palsule, Leonard Forbes, HADDAD HOMAYOON, MCKEE JEFFREY, JIANG JUTAO, MILLER DRAKE, PALSULE CHINTAMANI, FORBES LEONARD, Haddad Homayoon, McKee Jeffrey, Jiang Jutao, Miller Drake, Palsule Chintamani, Forbes Leonard

Принадлежит: SiOnyx, LLC, SIONYX LLC

Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation where the textured region includes surface features sized and positioned to facilitate tuning to a preselected wavelength of light, and a dielectric region positioned between the textured region and the at least one junction. The dielectric region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction.

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Номер записи: 10

01-09-2016 дата публикации

METHODS OF FORMING MEMORY DEVICES WITH ISOLATION STRUCTURES

Номер: US20160254270A1

Автор: Badih El-Kareh, Leonard Forbes, EL-KAREH BADIH, FORBES LEONARD, El-Kareh Badih, Forbes Leonard

Принадлежит: MICRON TECHNOLOGY, INC.

A first conductive region having a second conductivity type is formed in a first semiconductor over a first dielectric isolation region and having a first conductivity type. A second semiconductor having the first conductivity type is formed over the first conductive region and the first semiconductor. Isolation structures are formed extending through the second semiconductor and the first semiconductor to the first dielectric isolation region, thereby defining a first well of the second semiconductor contained within the isolation structures and a second well of the first conductive region contained within the isolation structures. A charge-storage node is formed over the first well. Source/drain regions having the second conductivity type are formed in the first well adjacent the charge-storage node. A control gate is formed over the charge-storage node. A first contact is formed to the first well. A second contact is formed to the second well through the first well.

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Номер записи: 11

10-04-2018 дата публикации

Three dimensional imaging utilizing stacked imager devices and associated methods

Номер: US0009939251B2

Автор: Homayoon Haddad, Chen Feng, Leonard Forbes, HADDAD HOMAYOON, FENG CHEN, FORBES LEONARD, Haddad Homayoon, Feng Chen, Forbes Leonard

Принадлежит: SiOnyx, LLC, SIONYX INC, SIONYX LLC, SiOnyx, Inc.

Stacked imager devices that can determine distance and generate three dimensional representations of a subject and associated methods are provided. In one aspect, an imaging system can include a first imager array having a first light incident surface and a second imager array having a second light incident surface. The second imager array can be coupled to the first imager array at a surface that is opposite the first light incident surface, with the second light incident surface being oriented toward the first imager array and at least substantially uniformly spaced. The system can also include a system lens positioned to direct incident light along an optical pathway onto the first light incident surface. The first imager array is operable to detect a first portion of the light passing along the optical pathway and to pass through a second portion of the light, where the second imager array is operable to detect at least a part of the second portion of light.

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Номер записи: 12

27-03-2018 дата публикации

Process of manufacturing an open pattern inductor

Номер: US9929229B2

Автор: AHN KIE Y, FORBES LEONARD, Ahn Kie Y., Forbes Leonard

Принадлежит: AHN KIE Y, FORBES LEONARD, MICRON TECHNOLOGY INC, Ahn Kie Y., Forbes Leonard, Micron Technology, Inc.

Various embodiments includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of parallel open conducting patterns embedded in a magnetic oxide or in an insulator and a magnetic material. A layer of magnetic material may be located above the inductor and below the inductor to confine electronic noise generated in the stacked open pattern inductor to the area occupied by the inductor. The stacked open pattern inductor may include a magnetic material directly contacts one of the conducting patterns and the substrate. The stacked open pattern inductor may be fabricated using conventional integrated circuit manufacturing processes, and the inductor may be used in connection with computer systems.

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Номер записи: 13

28-07-2016 дата публикации

Clamped Avalanche Photodiode

Номер: US20160218236A1

Автор: Vinit DHULLA, Drake Miller, Leonard Forbes, DHULLA VINIT, MILLER DRAKE, FORBES LEONARD, DHULLA Vinit, Miller Drake, Forbes Leonard

Принадлежит: Voxtel, Inc.

An avalanche photodiode device operated in Geiger-mode, the device comprising a P-N junction formed on a substrate with a first semiconductor region and a second semiconductor region with an anode and cathode. The device further comprising a third semiconductor region, the third semiconductor region in physical contact with the second region, not in physical contact with the first region, and being the same semiconductor-type as the first semiconductor region. Additionally comprising a diode on the second semiconductor region and having a turn-on voltage than the P-N junction.

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Номер записи: 14

06-06-2017 дата публикации

Photosensitive imaging devices and associated methods

Номер: US0009673243B2

Автор: Homayoon Haddad, Jeffrey McKee, Jutao Jiang, Drake Miller, Chintamani Palsule, Leonard Forbes, HADDAD HOMAYOON, MCKEE JEFFREY, JIANG JUTAO, MILLER DRAKE, PALSULE CHINTAMANI, FORBES LEONARD, Haddad Homayoon, McKee Jeffrey, Jiang Jutao, Miller Drake, Palsule Chintamani, Forbes Leonard

Принадлежит: SiOnyx, LLC, SIONYX LLC

Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and a passivation region positioned between the textured region and the at least one junction. The passivation region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction.

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Номер записи: 15

20-11-2013 дата публикации

Backside illuminated image sensor

Номер: CN103400844A

Автор: Hynecek Jaroslav, Forbes Leonard, Haddad Homayoon, Joy Thomas

Принадлежит:

A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer disposed on the backside passivation layer.

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Номер записи: 16

06-03-2018 дата публикации

Photosensitive imaging devices and associated methods

Номер: US0009911781B2

Автор: Homayoon Haddad, Jutao Jiang, Jeffrey McKee, Drake Miller, Leonard Forbes, Chintamani Palsule, HADDAD HOMAYOON, JIANG JUTAO, MCKEE JEFFREY, MILLER DRAKE, FORBES LEONARD, PALSULE CHINTAMANI, Haddad Homayoon, Jiang Jutao, McKee Jeffrey, Miller Drake, Forbes Leonard, Palsule Chintamani

Принадлежит: SiOnyx, LLC, SIONYX LLC

Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor substrate having multiple doped regions forming at least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and an electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least one junction. In one aspect, the textured region is operable to facilitate generation of an electrical signal from the detection of infrared electromagnetic radiation. In another aspect, interacting with electromagnetic radiation further includes increasing the semiconductor substrate's effective absorption wavelength as compared to a semiconductor substrate lacking a textured region.

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Номер записи: 17

13-02-2018 дата публикации

DRAM with nanofin transistors

Номер: US0009893072B2

Автор: Leonard Forbes, FORBES LEONARD, Forbes Leonard

Принадлежит: Micron Technology, Inc., MICRON TECHNOLOGY INC

One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein.

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Номер записи: 18

19-01-2012 дата публикации

High-k gate dielectric oxide

Номер: US20120015488A1

Автор: Kie Y. Ahn, Leonard Forbes

Принадлежит: Individual

A dielectric such as a gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.

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Номер записи: 19

22-03-2012 дата публикации

Conductive layers for hafnium silicon oxynitride

Номер: US20120068272A1

Автор: Kie Y. Ahn, Leonard Forbes

Принадлежит: Individual

Electronic apparatus and methods of forming the electronic apparatus include HfSiON for use in a variety of electronic systems. In various embodiments, conductive material is coupled to a dielectric containing HfSiON, where such conductive material may include one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum.

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Номер записи: 20

29-03-2012 дата публикации

Method of forming lutetium and lanthanum dielectric structures

Номер: US20120074480A1

Автор: Kie Y. Ahn, Leonard Forbes

Принадлежит: Individual

Methods of forming dielectric structures are shown. Methods of forming dielectric structures are shown that include lutetium oxide and lanthanum aluminum oxide crystals embedded within the lutetium oxide. Specific methods shown include monolayer deposition which yields process improvements such as chemistry control, step coverage, crystallinity/microstructure control.

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Номер записи: 21

29-03-2012 дата публикации

APPARATUS CONTAINING COBALT TITANIUM OXIDE

Номер: US20120074487A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит:

Electronic apparatus and methods of forming the electronic apparatus include cobalt titanium oxide on a substrate for use in a variety of electronic systems. The cobalt titanium oxide may be structured as one or more monolayers. The cobalt titanium oxide may be formed by a monolayer by monolayer sequencing process such as atomic layer deposition. 1. An electronic device comprising:a dielectric in a circuit on a substrate, the dielectric containing a cobalt titanium oxide, the cobalt titanium oxide structured as an arrangement of one or more monolayers.2. The electronic device of claim 1 , wherein the dielectric is configured substantially as the cobalt titanium oxide.3. The electronic device of claim 1 , wherein the electronic device includes a hemispherical grained polysilicon region on which the dielectric is disposed.4. The electronic device of claim 3 , wherein the dielectric includes an insulative nitride between the hemispherical grained polysilicon region and the cobalt titanium oxide.5. The electronic device of claim 1 , wherein the cobalt titanium oxide has a ratio of cobalt to titanium ranging from about 0.8 to about 1.2.6. The electronic device of claim 1 , wherein the cobalt titanium oxide is structured substantially as CoTiO.7. The electronic device of claim 1 , wherein the electronic device includes a transistor of a CMOS device claim 1 , having the dielectric as a gate insulator.8. The electronic device of claim 1 , wherein the electronic device includes a capacitor having the dielectric as a capacitor dielectric.9. The electronic device of claim 1 , wherein the dielectric includes a nanolaminate.10. The electronic device of claim 1 , wherein the electronic device includes a memory device having the dielectric as a memory cell component.11. The electronic device of claim 1 , wherein the electronic device includes a conductive path to a conductive material disposed on and contacting the dielectric to provide a signal to the conductive material to ...

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Номер записи: 22

05-04-2012 дата публикации

Backside nanoscale texturing to improve IR response of silicon solar cells and photodetectors

Номер: US20120080676A1

Автор: Leonard Forbes

Принадлежит: SiOnyx LLC

The absorption coefficient of silicon for infrared light is very low and most solar cells absorb very little of the infrared light energy in sunlight. Very thick cells of crystalline silicon can be used to increase the absorption of infrared light energy but the cost of thick crystalline cells is prohibitive. The present invention relates to the use of less expensive microcrystalline silicon solar cells and the use of backside texturing with diffusive scattering to give a very large increase in the absorption of infrared light. Backside texturing with diffusive scattering and with a smooth front surface of the solar cell results in multiple internal reflections, light trapping, and a large enhancement of the absorption of infrared solar energy.

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Номер записи: 23

05-04-2012 дата публикации

CHARGE TRAPPING DIELECTRIC STRUCTURES

Номер: US20120080740A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит:

A dielectric structure may be arranged having a thin nitrided surface of an insulator with a charge blocking insulator over the nitrided surface. The insulator may be formed of a number of different insulating materials such as a metal oxide, a metal oxycarbide, a semiconductor oxide, or oxycarbide. In an embodiment, the dielectric structure may be formed by nitridation of a surface of an insulator using ammonia and deposition of a blocking insulator having a larger band gap than the insulator. The dielectric structure may form part of a memory device, as well as other devices and systems. 1. An electronic apparatus comprising:a semiconductive substrate;a first insulator material disposed on a portion of the semiconductive substrate having a first band gap value;a second insulator material disposed on the first insulator material having a charge trapping interface with the first insulator material;a third insulator material disposed on the second insulator material having a second band gap value; anda conductive material disposed on the third insulator material.2. The electronic apparatus of claim 1 , wherein the first band gap value is lower than the second band gap value.3. The electronic apparatus of claim 1 , wherein the second insulator material comprises a silicon nitride material.4. The electronic apparatus of claim 3 , wherein the second insulator material comprises a nitrided portion of the first insulator material and has a thickness of less than 1 nm.5. The electronic apparatus of claim 1 , wherein the electronic apparatus includes a nonvolatile memory.6. The electronic apparatus of claim 1 , wherein the first insulator material includes at least one of silicon carbide claim 1 , silicon oxycarbide claim 1 , germanium carbide claim 1 , germanium oxycarbide claim 1 , germanium silicon carbide claim 1 , germanium silicon oxycarbide claim 1 , aluminum oxide claim 1 , hafnium oxide claim 1 , zirconium oxide claim 1 , lanthanum oxide claim 1 , ruthenium oxide ...

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Номер записи: 24

12-04-2012 дата публикации

METHODS OF FORMING TITANIUM SILICON OXIDE

Номер: US20120088373A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит:

A dielectric containing a titanium silicon oxide film and a method of fabricating such a dielectric provide a dielectric for use in a variety of electronic devices. Embodiments may include a dielectric containing a titanium silicon oxide film arranged as one or more monolayers. Embodiments may include structures for capacitors, transistors, memory devices, and electronic systems with dielectrics containing a titanium silicon oxide film, and methods for forming such structures. 1. A method comprising:forming a film of titanium silicon oxide by a monolayer or partial monolayer sequencing process; andincorporating an amount of oxygen in the film of titanium silicon oxide to set a specified characteristic for the film of titanium silicon oxide.2. The method of claim 1 , wherein the monolayer or partial monolayer process sequencing process is a self-limiting process.3. The method of claim 1 , wherein incorporating the amount of oxygen in the film of titanium silicon oxide includes regulating the amount of oxygen such that the film of titanium silicon oxide has a specified leakage current characteristic.4. The method of claim 1 , wherein incorporating the amount of oxygen in the film of titanium silicon oxide includes regulating the amount of oxygen to a level to control oxygen vacancies in the film of titanium silicon oxide.5. The method of claim 1 , wherein incorporating the amount of oxygen in the film of titanium silicon oxide includes controlling distribution of oxygen vacancies in the film.6. The method of claim 1 , wherein incorporating the amount of oxygen in the film of titanium silicon oxide includes controlling pulsing sequences of precursors containing titanium and precursors containing silicon claim 1 , controlling pulse time of an oxygen containing precursor claim 1 , and controlling an environment of the substrate on which the film of titanium silicon oxide is being formed to regulate the amount of oxygen in the film of titanium silicon oxide.7. The method ...

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Номер записи: 25

19-04-2012 дата публикации

HAFNIUM TANTALUM OXYNITRIDE DIELECTRIC

Номер: US20120094477A1

Автор: Ahn Kie Y., Bhattacharyya Arup, Forbes Leonard

Принадлежит:

Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film. 1. A method of making a memory device comprising:forming a silicon-based conductive region supported by a substrate;forming a refractory metal-based dielectric with a stoichiometric composition, the refractory metal-based dielectric supported by the silicon-based conductive region; andforming a conductive layer, wherein the conductive layer is supported by the refractory metal-based dielectric.2. The method of claim 1 , wherein forming includes patterning the silicon-based conductive region.3. The method of claim 1 , wherein forming a refractory metal-based dielectric includes forming a refractory metal-based oxynitride dielectric.4. The method of claim 1 , wherein forming a refractory metal-based dielectric includes forming a refractory metal-based dielectric with a stoichiometric composition using one or more layers with a non-stoichiometric composition5. The method of claim 1 , wherein forming a refractory metal-based dielectric includes forming two or more layers comprising at least one of a transition metal and a refractory metal.6. The method of claim 5 , wherein forming includes mixing two or more layers comprising at least one of an oxide claim 5 , a nitride and an oxynitride.7. The method of claim 5 , wherein forming includes mixing two or more layers comprising at least one of a transition metal and a refractory metal.8. The method of claim 7 , wherein mixing includes mixing two or more layers comprising at least one of an oxide claim 7 , a nitride and an oxynitride.9. The method of claim 1 , wherein forming a refractory metal-based dielectric includes forming a ...

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Номер записи: 26

03-05-2012 дата публикации

ELECTRONIC APPARATUS CONTAINING LANTHANIDE YTTRIUM ALUMINUM OXIDE

Номер: US20120108052A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит:

Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The lanthanide yttrium aluminum oxide film may be structured as one or more monolayers. The lanthanide yttrium aluminum oxide film may be formed by a monolayer or partial monolayer sequencing process such as using atomic layer deposition. 1. A method comprising:forming an electronic apparatus;forming lanthanide yttrium aluminum oxide as a portion of the electronic apparatus; andforming the lanthanide yttrium aluminum oxide by a monolayer or partial monolayer sequencing process.2. The method of claim 1 , wherein forming the lanthanide yttrium aluminum oxide using the monolayer or partial monolayer sequencing process includes forming the lanthanide yttrium aluminum oxide using a self-limiting monolayer or partial monolayer sequencing process.3. The method of claim 1 , wherein forming the lanthanide yttrium aluminum oxide includes forming a yttrium-rich lanthanide yttrium aluminum oxide film or a lanthanide-rich lanthanide yttrium aluminum oxide film.4. The method of claim 1 , wherein using the monolayer or partial monolayer sequencing process includes forming lanthanum yttrium aluminum oxide using a CHNLaSiprecursor.5. The method of claim 1 , wherein using the monolayer or partial monolayer sequencing process includes using one or more of a Y(thd)precursor claim 1 , a Y(thd)(2 claim 1 ,2′-bipyridyl) precursor claim 1 , or a Y(thd)(1 claim 1 ,10-phenanthroline) precursor.6. The method of claim 1 , wherein forming the lanthanide yttrium aluminum oxide includes forming LaYAlO claim 1 , where 0.2 Подробнее

Номер записи: 27

31-05-2012 дата публикации

DIELECTRICS CONTAINING AT LEAST ONE OF A REFRACTORY METAL OR A NON-REFRACTORY METAL

Номер: US20120133428A1

Автор: Ahn Kie Y., Bhattacharyya Arup, Forbes Leonard

Принадлежит:

Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory metal for use in a variety of electronic systems and devices. Embodiments can include electronic apparatus and methods of forming the electronic apparatus having a tantalum aluminum oxynitride film. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film. 1. A method comprising:propagating a voltage signal along a conductive path, at least a portion of the conductive path being adjacent to one or more insulators, wherein at least a portion of the one or more insulators comprise a mixture of a refractory metal and a non-refractory metal;generating a charge field associated with the voltage signal across a region of the mixture between a section of the conductive path and one or more electrodes;retaining the charge field between the section of the conductive path and the one or more electrodes based on a first specified signal; andremoving at least a portion of the charge field based on a second specified signal.2. The method of claim 1 , wherein generating includes establishing a charge field across a region including one or more TaAlONamorphous regions claim 1 , where y claim 1 , z claim 1 , x claim 1 , w are integer values claim 1 , and where y is 1 or 2 claim 1 , z is 1 or 2 claim 1 , x is 0 claim 1 , 1 claim 1 , 3 or 5 claim 1 , and w is 0 or 1.3. The method of claim 1 , wherein generating includes coupling electric charge across a region including TaAlON claim 1 , where y claim 1 , z claim 1 , x claim 1 , w are relative mole fractions.4. The method of claim 1 , wherein retaining includes transferring charge across a region including TaAlON.5. The method of claim 1 , wherein generating a charge field ...

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Номер записи: 28

14-06-2012 дата публикации

Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines

Номер: US20120146132A1

Автор: Leonard Forbes

Принадлежит: Micron Technology Inc

A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration.

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Номер записи: 29

02-08-2012 дата публикации

Methods of forming an insulating metal oxide

Номер: US20120196448A1

Автор: Kie Y. Ahn, Leonard Forbes

Принадлежит: Individual

A dielectric containing an insulating metal oxide film having multiple metal components and a method of fabricating such a dielectric produce a reliable dielectric for use in a variety of electronic devices. Embodiments include a titanium aluminum oxide film structured as one or more monolayers. Embodiments also include structures for capacitors, transistors, memory devices, and electronic systems with dielectrics containing a titanium aluminum oxide film.

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Номер записи: 30

16-08-2012 дата публикации

TANTALUM SILICON OXYNITRIDE HIGH-K DIELECTRICS AND METAL GATES

Номер: US20120205720A1

Автор: Ahn Kie Y., Bhattacharyya Arup, Forbes Leonard

Принадлежит:

Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic systems. The tantalum silicon oxynitride film may be structured as one or more monolayers. The tantalum silicon oxynitride film may be formed using a monolayer or partial monolayer sequencing process. Metal electrodes may be disposed on a dielectric containing a tantalum silicon oxynitride film. 1. An electronic device comprising:a substrate;{'sub': x', 'y', 'z', 'r, 'a dielectric disposed on the substrate, the dielectric including TaSiON(x, y, z, r>0) structured as an arrangement of one or more monolayers; and'}a metal on and contacting the dielectric.2. The electronic device of claim 1 , wherein the dielectric consists essentially of the TaSiON.3. The electronic device of claim 1 , wherein the electronic device includes contacts to couple the electronic device to other apparatus of a system.4. The electronic device of claim 1 , wherein the metal includes one or more of aluminum claim 1 , tungsten claim 1 , molybdenum claim 1 , gold claim 1 , silver claim 1 , a gold alloy claim 1 , a silver alloy claim 1 , copper claim 1 , platinum claim 1 , rhenium claim 1 , ruthenium claim 1 , rhodium claim 1 , nickel claim 1 , osmium claim 1 , palladium claim 1 , iridium claim 1 , cobalt claim 1 , germanium claim 1 , WN claim 1 , TiN claim 1 , TaN claim 1 , or a metal nitride other than WN claim 1 , TiN claim 1 , and TaN.5. The electronic device of claim 1 , wherein the tantalum silicon oxynitride is structured as a film doped with elements or compounds other than silicon claim 1 , tantalum claim 1 , oxygen claim 1 , and nitrogen.6. The electronic device of claim 1 , wherein the dielectric includes one or more of SiO claim 1 , SiN claim 1 , TaO claim 1 , TaN claim 1 , SiON claim 1 , or TaON(a claim 1 , b claim 1 , c claim 1 , d claim 1 , e claim 1 , f claim 1 , g claim 1 , h claim 1 , k claim 1 , l claim 1 , m claim 1 , ...

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Номер записи: 31

20-09-2012 дата публикации

BARRIER-METAL-FREE COPPER DAMASCENE TECHNOLOGY USING ENHANCED REFLOW

Номер: US20120235295A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит: MOSAID TECHNOLOGIES, INCORPORATED

A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated circuits such as memory devices and microprocessor. 1. A method of forming a contact in an opening in an insulative material , comprising:forming a non-metal barrier material over the insulative material within the opening;depositing a conductive material over the non-metal barrier material to fill the opening; andreflowing the conductive material in an atmosphere selected to allow formation of a substantially void-free layer of conductive material at a temperature of less than about 400° C.2. The method of claim 1 , wherein said atmosphere includes hydrogen and an inert gas.3. The method of claim 2 , wherein said atmosphere is subjected to a plasma formation process.4. The method of claim 3 , wherein said plasma formation process includes microwave excitation.5. The method of claim 4 , wherein said microwave excitation is performed at a pressure of about 1 Torr and a temperature of about 400° C.6. The method of claim 2 , wherein the mixing ratio of hydrogen to inert gas is between 3% and 5%.7. The method of claim 6 , wherein the inert gas is krypton.8. The method of claim 1 , wherein said depositing step is selected from the group consisting of ionized sputtering and evaporation.9. The method of claim 1 , wherein said reflow step is performed at a temperature between 300° C. and 350° C.10. The method of claim 9 , wherein said reflow step is performed at a temperature of about 320° C.11. A contact in an opening in an insulative material claim 9 , produced by the process of:forming a non-metal barrier material over the insulative material within the opening;depositing a conductive material over the non-metal barrier material to fill the opening; andreflowing the conductive material in an atmosphere selected ...

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Номер записи: 32

01-11-2012 дата публикации

Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines

Номер: US20120276699A1

Автор: Leonard Forbes

Принадлежит: Micron Technology Inc

A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure.

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Номер записи: 33

15-11-2012 дата публикации

LOCALIZED COMPRESSIVE STRAINED SEMICONDUCTOR

Номер: US20120289016A1

Автор: Forbes Leonard

Принадлежит:

One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline semiconductor bridge is formed over a substrate. The bridge has a first portion bonded to the substrate, a second portion bonded to the substrate, and a middle portion between the first and second portions separated from the substrate. The middle portion of the bridge is bonded to the substrate to provide a compressed crystalline semiconductor layer on the substrate. Other aspects are provided herein. 1. A method for forming a strained semiconductor film at desired locations over a substrate , the method comprising:forming an oxidized structure on the substrate, the oxidized structure comprising a first side and a second side on opposite sides of the desired locations, and wherein a thickness of oxidized structure at the desired locations is greater than a thickness of the oxidized structure at the first and second sides;etching the oxidized structure to provide an etched oxidized structure with exposed portions of the substrate on the opposite sides of each of the desired locations and with oxide remaining over the desired locations;depositing amorphous semiconductor over the etched oxidized structure;crystallizing the amorphous semiconductor to provide crystallized semiconductor over the etched oxidized structure, wherein the crystallized semiconductor is bonded to the exposed portions of the substrate on opposite sides of each of the desired locations; andremoving the oxide remaining over the desired locations to allow the crystallized semiconductor to bond to the substrate and to be compressively strained at the desired locations when bonded to the substrate.2. The method of claim 1 , wherein forming an oxidized structure on the substrate includes masking the substrate to create a masked substrate and define and cover the desired locations.3. The method of claim 2 , wherein forming the oxidized structure on ...

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Номер записи: 34

22-11-2012 дата публикации

BACKSIDE TEXTURING BY CUSPS TO IMPROVE IR RESPONSE OF SILICON SOLAR CELLS AND PHOTODETECTORS

Номер: US20120292619A1

Автор: Forbes Leonard

Принадлежит:

The absorption coefficient of silicon for infrared light is very low and most solar cells absorb very little of the infrared light energy in sunlight. Very thick cells of crystalline silicon can be used to increase the absorption of infrared light energy but the cost of thick crystalline cells is prohibitive. The present invention relates to the use of less expensive microcrystalline silicon solar cells and the use of backside texturing with diffusive scattering to give a very large increase in the absorption of infrared light. Backside texturing comprises a plurality of cusped features providing diffusive scattering. Constructing the solar cell with a smooth front surface results in multiple internal reflections, light trapping, and a large enhancement of the absorption of infrared solar energy. 129-. (canceled)30. A semiconductor solar cell or photodetector having improved incident radiation absorption of visible and infrared light wavelengths , comprising:a silicon substrate having a first surface available to the incident radiation being textured to provide internal Lambertian diffusive reflective scattering at least of the infrared light wavelengths and having a second surface;a first layer disposed at said first surface, said first layer being transparent to the visible light and infrared light wavelengths of the incident radiation; anda reflecting layer disposed adjacent said second surface, whereby said infrared light wavelengths are returned by the reflecting layer toward said textured first surface and into said silicon substrate.31. The semiconductor solar cell or photodetector of wherein said first layer is antireflective to visible and infrared light of the incident radiation.32. The semiconductor solar cell or photodetector of wherein said silicon substrate further comprises single crystalline silicon or multi-crystalline silicon substrate having a thickness in a range of 5 micrometers to 500 micrometers.33. The semiconductor solar cell or ...

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Номер записи: 35

13-12-2012 дата публикации

Process Module for Increasing the Response of Backside Illuminated Photosensitive Imagers and Associated Methods

Номер: US20120313204A1

Автор: Chintamani Palsule, Drake Miller, Homayoon Haddad, Jeffrey McKee, Jutao Jiang, Leonard Forbes

Принадлежит: SiOnyx LLC

Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation where the textured region includes surface features sized and positioned to facilitate tuning to a preselected wavelength of light, and a dielectric region positioned between the textured region and the at least one junction. The dielectric region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction.

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Номер записи: 36

13-12-2012 дата публикации

Photosensitive Imagers Having Defined Textures for Light Trapping and Associated Methods

Номер: US20120313205A1

Автор: Forbes Leonard, Haddad Homayoon, Jiang Jutao, McKee Jeffrey, Miller Drake, Palsule Chintamani

Принадлежит:

Photosensitive devices and associated methods are provided. In one aspect, for example, a frontside-illuminated photosensitive imager devices can include a semiconductor substrate having multiple doped regions forming a least one junction and a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation on an opposite side of the semiconductor substrate from the multiple doped regions. The textured region can include surface features sized and positioned to facilitate tuning to a preselected wavelength of light. The device can also include an electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least one junction. 1. A front-side illuminated photosensitive imager device , comprising:a semiconductor substrate having multiple doped regions forming a least one junction;a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation on an opposite side of the semiconductor substrate from the multiple doped regions, wherein the textured region includes surface features sized and positioned to facilitate tuning to a preselected wavelength of light; andan electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least one junction.2. The device of claim 1 , wherein the surface features have an average center-to-center distance distribution of one half wavelength of the preselected wavelength of light claim 1 , multiples of one half wavelength of the preselected wavelength of light claim 1 , at least one half wavelength of the preselected wavelength of light.3. The device of claim 2 , wherein the center-to-center distance distribution is a substantially uniform distance distribution.4. The device of claim 1 , wherein the surface features have an average height of about a multiple of a quarter wavelength of the preselected wavelength of ...

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Номер записи: 37

03-01-2013 дата публикации

TITANIUM-DOPED INDIUM OXIDE FILMS

Номер: US20130000544A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит: MICRON TECHNOLOGY, INC.

An apparatus and methods of forming the apparatus include a film of transparent conductive titanium-doped indium oxide for use in a variety of configurations and systems. The film of transparent conductive titanium-doped indium oxide may be structured as one or more monolayers. The film of transparent conductive titanium-doped indium oxide may be formed using atomic layer deposition. 1. A method comprising:forming indium oxide by a monolayer or partial monolayer sequencing processing; anddoping the indium oxide with titanium, forming a transparent conductive titanium-doped indium oxide.2. The method of claim 1 , wherein forming the transparent conductive titanium-doped indium oxide includes forming the transparent conductive titanium-doped indium oxide with a titanium atomic concentration less than or equal to 7%.3. The method of claim 1 , wherein forming the transparent conductive titanium-doped indium oxide includes forming the transparent conductive titanium-doped indium oxide with an atomic concentration of titanium ranging from 1% to 3%.4. The method of claim 1 , wherein the method includes forming the conductive titanium-doped indium oxide in a flat-panel display.5. The method of claim 1 , wherein the method includes forming the transparent conductive titanium-doped indium oxide in a photovoltaic cell.6. The method of claim 1 , wherein the method includes forming the transparent conductive titanium-doped indium oxide in a smart window.7. The method of claim 1 , wherein the method includes forming the transparent conductive titanium-doped indium oxide in a light emitting diode array.8. The method of claim 1 , wherein the method includes forming the transparent conductive titanium-doped indium oxide in an optical waveguide.9. The method of claim 1 , wherein the doping the indium oxide with titanium includes using a titanium precursor that contains oxygen.10. A method comprising:forming indium oxide by a monolayer or partial monolayer sequencing process; ...

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Номер записи: 38

03-01-2013 дата публикации

METHODS FOR STRESSING TRANSISTOR CHANNELS OF A SEMICONDUCTOR DEVICE STRUCTURE, AND A RELATED SEMICONDUCTOR DEVICE STRUCTURE

Номер: US20130001575A1

Автор: Bhattacharyya Arup, Farrar Paul A., Forbes Leonard

Принадлежит: MICRON TECHNOLOGY, INC.

The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed. 1. A method for stressing transistor channels of a semiconductor device structure , comprising:forming a source and a drain in a substrate on opposing sides of a gate, a transistor channel positioned between the source and the drain;forming nanocavities in opposing regions of a semiconductor material adjacent the opposing sides of the gate;implanting conductivity dopants into the substrate through the nanocavities to form a source extension between the transistor channel and the source, and a drain extension between transistor channel and the drain;activating the conductivity dopants;introducing stress inducing elements into the source extension and the drain extension;treating at least the stress inducing elements to generate stress in the transistor channel.2. The method of claim 1 , further comprising forming an oxide film on the opposing regions of the semiconductor material before forming the nanocavities in the opposing regions of the semiconductor material.3. The method of claim 1 , further comprising forming the opposing regions of the semiconductor material to each have a base located about 500 Å beneath a surface of the substrate and to have a thickness of less than or ...

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Номер записи: 39

10-01-2013 дата публикации

SILICON ON GERMANIUM

Номер: US20130012005A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит: MICRON TECHNOLOGY, INC.

A monolayer or partial monolayer sequencing processing, such as atomic layer deposition (ALD), can be used to form a semiconductor structure of a silicon film on a germanium substrate. Such structures may be useful in high performance electronic devices. A structure may be formed by deposition of a thin silicon layer on a germanium substrate surface, forming a hafnium oxide dielectric layer, and forming a tantalum nitride electrode. The properties of the dielectric may be varied by replacing the hafnium oxide with another dielectric such as zirconium oxide or titanium oxide. 1. A method comprising:forming silicon on a germanium-containing material by a monolayer or partial monolayer sequencing processing;forming a dielectric on the silicon; andforming a conductive material on the dielectric.2. The method of claim 1 , wherein the germanium-containing material is a germanium layer on a silicon substrate.3. The method of claim 1 , wherein the germanium-containing material is a germanium substrate.4. The method of claim 1 , wherein the method includes forming a diffusion barrier between the dielectric and the silicon.5. The method of claim 1 , wherein forming the dielectric includes forming a graded dielectric material.6. The method of claim 1 , wherein forming the dielectric includes forming a dielectric material having a dielectric constant of more than 10.7. The method of claim 6 , wherein forming the dielectric material includes forming one or more of hafnium oxide claim 6 , zirconium oxide claim 6 , titanium oxide claim 6 , STO claim 6 , BTO claim 6 , barium oxide claim 6 , or strontium oxide.8. The method of claim 1 , wherein forming the dielectric includes forming a dielectric nanolaminate.9. The method of claim 8 , wherein forming the dielectric nanolaminate includes forming a nanolaminate of hafnium oxide and zirconium oxide.10. The method of claim 8 , wherein forming the dielectric nanolaminate includes forming the nanolaminate dielectric in a flash memory.11. ...

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Номер записи: 40

10-01-2013 дата публикации

ZIRCONIUM-DOPED TANTALUM OXIDE FILMS

Номер: US20130012034A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит:

Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer can be formed of one or more monolayers of tantalum oxide doped with zirconium, provide an insulating layer in a variety of structures for use in a wide range of electronic devices. 1. A method comprising:forming tantalum oxide on a substrate using a self-limiting deposition process;doping the tantalum oxide with zirconium at different times during the self-limiting deposition process such that a zirconium-doped tantalum oxide is formed; andcontrolling the doping with zirconium to an amount such that the zirconium-doped tantalum oxide has a structure that does not differ significantly from an undoped tantalum oxide structure.2. The method of claim 1 , wherein doping the tantalum oxide with zirconium includes doping as elemental zirconium.3. The method of claim 1 , wherein doping the tantalum oxide with zirconium includes doping as zirconium oxide.4. The method of claim 1 , wherein forming zirconium-doped tantalum oxide includes forming an amorphous zirconium-doped tantalum oxide.5. The method of claim 1 , wherein forming the tantalum oxide including doping the tantalum oxide with zirconium is conducted at temperatures between about 250° C. and about 325° C.6. The method of claim 1 , wherein forming tantalum oxide on a substrate includes forming the tantalum oxide on a silicon substrate.7. The method of claim 6 , wherein forming the tantalum oxide including doping the tantalum oxide with zirconium is conducted at temperatures such that a silicon oxide interface is formed between the zirconium-doped tantalum oxide and the silicon substrate.8. The method of claim 1 , wherein the method includes providing a tantalum containing precursor directed to the substrate and providing a zirconium containing precursor directed to the substrate such that these precursors are directed to the substrate at non-overlapping periods.9. The method of claim 8 , wherein the ...

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Номер записи: 41

21-02-2013 дата публикации

DEVICES AND METHODS TO IMPROVE CARRIER MOBILITY

Номер: US20130045578A1

Автор: Bhattacharyya Arup, Forbes Leonard

Принадлежит: MICRON TECHNOLOGY, INC.

Electronic apparatus and methods of forming the electronic apparatus include a silicon oxynitride layer on a semiconductor device for use in a variety of electronic systems. The silicon oxynitride layer may be structured to control strain in a silicon channel of the semiconductor device to modify carrier mobility in the silicon channel, where the silicon channel is configured to conduct current under appropriate operating conditions of the semiconductor device. 1. A method comprising:forming a source and a drain of a transistor, the source and drain separated by a silicon channel;forming a gate stack on the silicon channel; andforming a first silicon oxynitride layer as part of a first spacer by chemical vapor deposition at a temperature greater than 750° C., the first spacer disposed adjacent the gate stack and on a portion of the drain; andforming a second silicon oxynitride layer as part of a second spacer by chemical vapor deposition at a temperature greater than 750° C., the second spacer disposed adjacent the gate stack and on a portion of the source, the first and second silicon oxynitride layers structured to control strain in the silicon channel.2. The method of claim 1 , wherein the method includes forming the first spacer substantially as the first silicon oxynitride layer and forming the second spacer substantially as the second silicon oxynitride layer.3. The method of claim 1 , wherein forming a gate stack includes forming a gate dielectric on the silicon channel and forming a gate on the gate dielectric.4. The method of claim 1 , wherein forming a gate stack includes:forming a gate dielectric on the silicon channel;forming a floating gate on the gate dielectric;forming an intergate dielectric on the floating gate; andforming a control gate on the intergate dielectric.5. The method of claim 1 , wherein forming a gate stack includes forming a multiple layer dielectric on the silicon channel claim 1 , the multiple layer dielectric having a layer ...

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Номер записи: 42

18-04-2013 дата публикации

Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines

Номер: US20130095645A1

Автор: Leonard Forbes

Принадлежит: Micron Technology Inc

A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration.

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Номер записи: 43

09-05-2013 дата публикации

METHOD FOR FORMING NANOFIN TRANSISTORS

Номер: US20130112982A1

Автор: Forbes Leonard

Принадлежит: MICRON TECHNOLOGY, INC.

One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin is formed from a crystalline substrate. A first source/drain region is formed in the substrate beneath the fin. A surrounding gate insulator is formed around the fin. A surrounding gate is formed around the fin and separated from the fin by the surrounding gate insulator. A second source/drain region is formed in a top portion of the fin. Various embodiments etch a hole in a layer over the substrate, form sidewall spacers in the hole, form a fin pattern from the sidewall spacers, and etch into the crystalline substrate to form the fin from the substrate using a mask corresponding to the fin pattern. Other aspects are provided herein. 1. A semiconductor structure , comprising: a first source/drain region in the crystalline substrate at a bottom of the fin, and a second source/drain region in a top portion of the fin to define a vertically-oriented channel region in the fin between the first and second source/drain regions;', 'a gate insulator formed around the fin; and', 'a surrounding gate formed around and separated from the fin by the gate insulator; and, 'a crystalline substrate, with trenches etched therein to form at least three crystalline semiconductor fins from the substrate, wherein for each of the at least three crystalline semiconductor fins the respective fin has a cross-sectional dimension that is less than a minimum feature size and includesthe at least three crystalline semiconductor fins including a first fin, a second fin, and a third fin, wherein the second fin is between the first and third fins, the first and second fins have a center-to-center spacing of the minimum feature length (F) less the cross-sectional dimension of the fins (ΔT), and the second fin and the third fin have a center-to center spacing of the minimum feature length (F) plus the cross-sectional dimension of the fin (ΔT).2. The structure of claim 1 , wherein ...

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Номер записи: 44

16-05-2013 дата публикации

Zr-SUBSTITUTED BaTiO3 FILMS

Номер: US20130122609A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит: MICRON TECHNOLOGY, INC.

The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition (ALD), to form a zirconium substituted layer of barium titanium oxide, produces a reliable ferroelectric structure for use in a variety of electronic devices such as a dielectric in nonvolatile random access memories (NVRAM), tunable dielectrics for multi layer ceramic capacitors (MLCC), infrared sensors and electro-optic modulators. In various embodiments, structures can be formed by depositing alternating layers of barium titanate and barium zirconate by ALD on a substrate surface using precursor chemicals, and repeating to form a sequentially deposited interleaved structure of desired thickness and composition. The properties of the dielectric may be tuned by adjusting the percentage of zirconium to titanium to optimize properties such as a dielectric constant, Curie point, film polarization, ferroelectric property and a desired relaxor response. 1. A method comprising: forming a plurality of barium titanate monolayers on the substrate;', 'forming a plurality of barium zirconate monolayers on the substrate; and', 'repeating the forming of pluralities of barium titanate and barium zirconate monolayers on the substrate until a final thickness is obtained; and, 'forming a ferroelectric on a substrate by a monolayer or partial monolayer sequencing process, includingannealing the ferroelectric at least once in one of a non-oxidizing ambient or an oxidizing ambient.2. The method of claim 1 , further including forming an electrically conductive material on the ferroelectric.3. The method of claim 1 , wherein the barium titanate monolayer is formed by exposing an activated substrate surface at a preselected temperature to a first precursor material for a preselected time period and a preselected flow volume of the first precursor material to saturate the substrate surface with the first precursor material;exposing the substrate surface to a preselected volume of a purge ...

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Номер записи: 45

20-06-2013 дата публикации

STRUCTURES INCLUDING PASSIVATED GERMANIUM

Номер: US20130153902A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит: ROUND ROCK RESEARCH, LLC

A passivated germanium surface that is a germanium carbide material formed on and in contact with the germanium material. A semiconductor device structure having the passivated germanium having germanium carbide material on the substrate surface is also disclosed. 1. A semiconductor device structure , comprising:{'sub': x', '1-x, 'a substrate having, at least formed on its top surface, a germanium material and an amorphous germanium carbide material having the composition GeC:H, where 0 is less than x and x is less than 1, wherein the amorphous germanium carbide material is in contact with at least a portion of the germanium material and wherein the germanium material and the amorphous germanium carbide material are formed on the top surface of the substrate;'}a source region formed in the germanium material;a drain region formed in the germanium material; wherein the source and drain regions are separated by a channel region; anda gate region formed over the amorphous germanium carbide material over which is formed a conductive layer.2. The semiconductor device structure of claim 1 , wherein the germanium material comprises a germanium substrate or a substrate comprising at least one other material and having a germanium material on a surface thereof.3. The semiconductor device of wherein the substrate is selected from the group consisting of a silicon wafer claim 1 , a silicon on insulator substrate claim 1 , a silicon on glass substrate claim 1 , a silicon on sapphire substrate claim 1 , an epitaxial layer of silicon on a base semiconductor foundation claim 1 , a silicon-germanium substrate claim 1 , a gallium arsenide substrate claim 1 , and an indium phosphide substrate.4. The semiconductor device structure of claim 1 , wherein the amorphous germanium carbide material comprises approximately equal amounts of germanium and carbon.5. The semiconductor device structure of claim 1 , wherein x is about 0.5.6. The semiconductor device structure of claim 1 , wherein ...

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Номер записи: 46

20-06-2013 дата публикации

HIGH-K DIELECTRICS WITH GOLD NANO-PARTICLES

Номер: US20130153986A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит: MICRON TECHNOLOGY, INC.

A metal oxide semiconductor (MOS) structure having a high dielectric constant gate insulator layer containing gold (Au) nano-particles is presented with methods for forming the layer with high step coverage of underlying topography, high surface smoothness, and uniform thickness. The transistor may form part of a logic device, a memory device, a persistent memory device, a capacitor, as well as other devices and systems. The insulator layer may be formed using atomic layer deposition (ALD) to reduce the overall device thermal exposure. The insulator layer may be formed of a metal oxide, a metal oxycarbide, a semiconductor oxide, or semiconductor oxide oxycarbide, and the gold nano-particles in insulator layer increase the work function of the insulator layer and affect the tunneling current and the threshold voltage of the transistor. 1. A device comprising:a semiconductive substrate with a dielectric layer comprising;a first layer of an insulator material disposed on a portion of the semiconductive substrate having a first thickness;a second layer of a material disposed on the first insulator material having a second thickness and a work function higher than 5.0 eV, and;a third layer of an insulator material disposed on the second layer having a third thickness; anda conductive material disposed on the third layer of insulator material.2. The device of claim 1 , wherein the first thickness is less than 1.0 nm.3. The device of claim 1 , wherein the second material comprises gold having a second thickness less than 1.0 nm.4. The device of claim 1 , wherein the third material comprises hafnium oxide having a dielectric constant of greater than 22 claim 1 , and an equivalent silicon dioxide thickness of less than 1.0 nm.5. The device of claim 1 , wherein the device includes a non-volatile memory cell.6. The device of claim 1 , wherein the second layer includes a plurality of nano-particles of gold at an interface between the first and third layers claim 1 , having an ...

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Номер записи: 47

04-07-2013 дата публикации

Three Dimensional Architecture Semiconductor Devices and Associated Methods

Номер: US20130168792A1

Автор: Forbes Leonard, Haddad Homayoon

Принадлежит: SiOnyx, Inc.

Semiconductor devices having three dimensional (3D) architectures and methods form making such devices are provided. In one aspect, for example, a method for making a semiconductor device can include forming a device layer on a front side of a semiconductor layer that is substantially defect free, bonding a carrier substrate to the device layer, processing the semiconductor layer on a back side opposite the device layer to form a processed surface, and bonding a smart substrate to the processed surface. In some aspects, the method can also include removing the carrier substrate from the semiconductor layer to expose the device layer. 1. A method for making a semiconductor device , comprising:forming a device layer on a front side of a semiconductor layer, wherein the semiconductor layer is at least substantially defect free;bonding a carrier substrate to the device layer;processing the semiconductor layer on a back side opposite the device layer to form a processed surface; andbonding a smart substrate to the processed surface.2. The method of claim 1 , further comprising removing the carrier substrate to expose the device layer.3. The method of claim 1 , wherein processing the semiconductor layer on the back side to form the processed surface further includes exposing contact pads associated with the device layer for bonding to the smart substrate.4. The method of claim 1 , wherein forming the device layer further includes forming optoelectronic circuitry on the front side of the semiconductor layer.5. The method of claim 1 , wherein forming the device layer further includes forming on the front side of the semiconductor layer a member selected from the group consisting of CMOS circuitry claim 1 , imaging devices claim 1 , RF circuitry claim 1 , photovoltaic circuitry claim 1 , or a combination thereof.6. The method of claim 1 , wherein the semiconductor layer includes a silicon material.7. The method of claim 5 , wherein the silicon material is a single crystal ...

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Номер записи: 48

04-07-2013 дата публикации

Semiconductor-On-Insulator Devices and Associated Methods

Номер: US20130168803A1

Автор: Forbes Leonard, Haddad Homayoon

Принадлежит: SiOnyx, Inc.

Semiconductor-on-insulator (SOI) devices and associated methods are provided. In one aspect, for example, a method for making a SOI device can include forming a device layer on a front side of a semiconductor layer, bonding a first substrate to the front side of the device layer, processing the semiconductor layer on a back side opposite the device layer to form a processed surface, and bonding a second substrate to the processed surface. In some aspects, the method can further include removing the first substrate from the front side to expose the device layer. In one aspect, forming the device layer can include forming optoelectronic circuitry at the front side of the semiconductor layer. 1. A method for making a semiconductor-on-insulator device , comprising:forming a device layer on a front side of a semiconductor layer;bonding a first substrate to the front side of the device layer;processing the semiconductor layer on a back side opposite the device layer to form a processed surface;bonding a second substrate to the processed surface; andremoving the first substrate from the front side to expose the device layer.2. The method of claim 1 , wherein forming the device layer further includes forming optoelectronic circuitry at the front side of the semiconductor layer.3. The method of claim 1 , wherein forming the device layer further includes forming on the front side of the semiconductor layer a member selected from the group consisting of CMOS circuitry claim 1 , imaging devices claim 1 , RF circuitry claim 1 , photovoltaic circuitry claim 1 , or a combination thereof.4. The method of claim 1 , wherein the semiconductor layer includes a silicon material.5. The method of claim 4 , wherein the silicon material is a single crystal silicon wafer.6. The method of claim 1 , wherein processing the semiconductor layer on the back side further includes thinning the semiconductor layer from the back side to expose the device layer.7. The method of claim 1 , wherein ...

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Номер записи: 49

15-08-2013 дата публикации

Integrated Visible and Infrared Imager Devices and Associated Methods

Номер: US20130207214A1

Автор: Forbes Leonard, Haddad Homayoon

Принадлежит: SiOnyx, Inc.

Semiconductor devices having three dimensional (3D) architectures and methods form making such devices are provided. In one aspect, for example, a method for making a semiconductor device can include forming a device layer on a front side of a semiconductor layer that is substantially defect free, bonding a carrier substrate to the device layer, processing the semiconductor layer on a back side opposite the device layer to form a processed surface, and bonding a smart substrate to the processed surface. In some aspects, the method can also include removing the carrier substrate from the semiconductor layer to expose the device layer. 1. A method for making a semiconductor device , comprising:forming a device layer on a front side of a semiconductor layer, wherein the semiconductor layer is at least substantially defect free;bonding a carrier substrate to the device layer;processing the semiconductor layer on a back side opposite the device layer to form a processed surface; andcoupling a bolometer to the processed surface.2. The method of claim 1 , further comprising removing the carrier substrate to expose the device layer.3. The method of claim 1 , wherein processing the semiconductor layer on the back side to form the processed surface further includes exposing contact pads associated with the device layer.4. The method of claim 1 , wherein forming the device layer further includes forming optoelectronic circuitry on the front side of the semiconductor layer.5. The method of claim 1 , wherein forming the device layer further includes forming on the front side of the semiconductor layer a member selected from the group consisting of CMOS circuitry claim 1 , imaging devices claim 1 , RF circuitry claim 1 , photovoltaic circuitry claim 1 , or a combination thereof.6. The method of claim 1 , wherein forming the device layer further includes forming a CMOS imager.7. The method of claim 1 , wherein the semiconductor layer includes a silicon material.8. The method of ...

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Номер записи: 50

22-08-2013 дата публикации

VERTICALLY BASE-CONNECTED BIPOLAR TRANSISTOR

Номер: US20130214847A1

Автор: Ahn Kie Y., El-Kareh Badih, Forbes Leonard

Принадлежит: MICRON TECHNOLOGY, INC.

Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor. 1. A bipolar transistor , comprising:a collector on a semiconductor substrate;a vertically grown single crystalline silicon pillar;an emitter formed from a polysilicon material and a vertically grown single crystal material formed separated from the collector by oxide nitride; anda vertical base contact with an intrinsic base region formed in the single crystalline silicon pillar and base links formed with dopants driven from an extrinsic base region.2. The transistor of claim 1 , wherein the transistor is in a npn configuration.3. The transistor of claim 1 , wherein the intrinsic base region is silicon germanium (SiGe).4. The transistor of claim 1 , wherein the intrinsic base region is silicon germanium carbon (SiGe:C).5. The transistor of claim 1 , wherein the extrinsic base region is polysilicon.6. The transistor of claim 1 , wherein the vertical base contact includes a base link formed in a thermal cycle that connects the intrinsic and extrinsic regions of the base link.7. The transistor of claim 1 , wherein the transistor is in a pnp configuration.8. A bipolar circuit claim 1 , comprising:an array of complementary vertically oriented base-connected bipolar transistors; a collector on a semiconductor substrate;', 'a vertically grown single crystalline silicon pillar;', 'an emitter formed from a polysilicon material and a vertically grown single crystal material formed separated from the collector by oxide nitride; and', 'a vertical base contact with an intrinsic base region formed in the single crystalline silicon pillar with a dopant driven from the emitter and an extrinsic base region; and, ' ...

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Номер записи: 51

29-08-2013 дата публикации

HAFNIUM TANTALUM TITANIUM OXIDE FILMS

Номер: US20130224916A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит: MICRON TECHNOLOGY, INC.

Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in a transistor. An embodiment may include forming a hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as reaction sequence atomic layer deposition. 1. A method for forming a transistor , the method comprising:forming a source region in a substrate;forming a drain region in the substrate;forming a dielectric on the substrate, with a reaction sequence atomic layer deposition process, the dielectric including a hafnium tantalum titanium oxide, a hafnium oxide, a tantalum oxide, and a titanium oxide as separate entities; andforming a gate above the dielectric.2. The transistor of claim 1 , wherein forming the dielectric includes a dielectric nitride.3. The transistor of claim 1 , wherein forming the dielectric includes forming an insulating metal oxide layer claim 1 , whose metal is different from hafnium claim 1 , tantalum and titanium.4. The transistor of claim 1 , further comprising forming an interfacial material between the substrate and the dielectric.5. The transistor of claim 4 , wherein forming the interfacial material comprises forming the interfacial layer to a thickness that is less than the dielectric.6. The transistor of claim 1 , wherein forming the dielectric comprises forming a tunnel oxide contacting a channel and a floating gate in the transistor.7. The transistor of claim 1 , wherein forming the dielectric comprises forming a floating gate dielectric contacting a floating gate and the gate in the transistor.8. A method for forming a transistor claim 1 , the method comprising:forming a source region in a substrate;forming a drain region in the substrate;forming a dielectric on the substrate with a reaction sequence atomic layer deposition process, the process including doping a hafnium tantalum titanium oxide with a metal or a compound of two or ...

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Номер записи: 52

12-09-2013 дата публикации

Backside Illuminated Image Sensor

Номер: US20130237004A1

Автор: Forbes Leonard, Haddad Homayoon, Hynecek Jaroslav, Joy Thomas

Принадлежит:

A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer disposed on the backside passivation layer. 1. A method for manufacturing a backside illuminated image sensor , the method comprising:forming a light-receiving element in a substrate;forming a patterned conductive layer over the substrate, wherein the patterned conductive layer includes an interconnection layer and an interlayer insulation layer;forming an align key spaced apart from the light-receiving element and passing through the interlayer insulation layer and the substrate, wherein the patterned conductive layer is electrically coupled to the align key;forming a backside passivation layer over the substrate; andforming a transparent conductive layer over the backside passivation layer proximate the light-receiving element, wherein the transparent conductive layer is electrically coupled to the align key.2. The method of claim 1 , further comprising forming both a color filter and a microlens over the transparent conductive layer proximate the light-receiving element.3. The method of claim 1 , further comprising:forming a front side passivation layer over a front side of the patterned conductive layer; andforming a further substrate over the front side passivation layer.4. The method of claim 3 , wherein said forming a further substrate over the front side passivation layer comprises bonding a silicon-on-insulator substrate over the front side passivation layer.5. The method of claim 1 , wherein said forming a backside passivation layer comprises forming a backside passivation layer having a multi-layered structure including layers with different refractive indexes.6. The method of claim 1 , wherein said forming a backside passivation layer comprises forming a backside passivation layer including a layer having a lower refractive index than the substrate.7. The method of claim 1 , wherein said forming ...

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Номер записи: 53

03-10-2013 дата публикации

VERTICAL TRANSISTOR, MEMORY CELL, DEVICE, SYSTEM AND METHOD OF FORMING SAME

Номер: US20130258756A1

Автор: Forbes Leonard

Принадлежит:

A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are disclosed. A first source/drain region is fowled in the substrate and a body region and a second source/drain region are formed within the pillar. A first gate is coupled to a first side of the pillar for coupling the first and second source/drain regions together when activated. The vertical memory cell also includes a storage capacitor formed on an extended end of the semiconducting pillar and electrically coupled to the second source/drain region. 1. A semiconductor device , comprising:a pillar of semiconductor material extending from a substrate and including a body region over the substrate and a second source/drain region over the body region;a bit line formed in the substrate and at least partially offset from the pillar in a direction lateral to the bit line; anda first source/drain region coupled to the bit line and at least partially under the body region, wherein the first source/drain region, the body region and the second source/drain region comprise elements of an access transistor.2. The semiconductor device of claim 1 , further comprising one or more gates of the access transistor disposed on one or more sides of the pillar.3. The semiconductor device of claim 2 , wherein the one or more gates comprise a first gate formed on a first side of the pillar and a second gate formed on a second side claim 2 , of the pillar opposing the first side.4. The semiconductor device of claim 3 , wherein the first gate and the second gate are operably coupled to a word line configured to control the access transistor to access a storage element.5. The semiconductor device of claim 1 , further comprising a storage capacitor formed over and operably coupled to the second source/drain region.6. The semiconductor device of claim 1 , further comprising one or more isolation trenches ...

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Номер записи: 54

10-10-2013 дата публикации

COBALT TITANIUM OXIDE DIELECTRIC FILMS

Номер: US20130264625A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит:

Electronic apparatus and methods of forming the electronic apparatus include cobalt titanium oxide on a substrate for use in a variety of electronic systems. The cobalt titanium oxide may be structured as one or more monolayers. The cobalt titanium oxide may be formed by a monolayer by monolayer sequencing process such as atomic layer deposition. 120-. (canceled)21. A method comprising: pulsing a cobalt-containing precursor;', 'pulsing a titanium-containing precursor; and', 'performing a removal process between pulsing the cobalt-containing precursor and pulsing the titanium-containing precursor such that a gas containing cobalt is not present when pulsing the titanium-containing precursor and a gas containing titanium is not present when pulsing the cobalt-containing precursor., 'forming cobalt titanium oxide by a monolayer or partial monolayer sequencing process including22. The method of claim 21 , wherein forming the cobalt titanium oxide includes forming a dielectric stack including the cobalt titanium oxide.23. The method of claim 22 , wherein forming the dielectric stack includes forming an insulating nitride claim 22 , an insulating metal oxide claim 22 , or a combination of an insulating nitride and an insulating metal oxide.24. The method of claim 22 , wherein forming the dielectric stack includes forming silicon oxide.25. The method of claim 24 , wherein forming the silicon oxide includes arranging the silicon oxide in the dielectric stack such that the silicon oxide operatively provides a charge storage region.26. The method of claim 22 , wherein forming the dielectric stack includes forming the dielectric stack structured as a nanolaminate.27. The method of claim 21 , wherein the method includes doping the cobalt titanium oxide with an element or a compound other than cobalt claim 21 , titanium claim 21 , and oxygen.28. The method of claim 21 , wherein forming the cobalt titanium oxide includes forming the cobalt titanium oxide on a substrate with the ...

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Номер записи: 55

24-10-2013 дата публикации

HAFNIUM TANTALUM OXYNITRIDE DIELECTRIC

Номер: US20130279259A1

Автор: Ahn Kie Y., Bhattacharyya Arup, Forbes Leonard

Принадлежит:

Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film. 1. A method comprising:transmitting a voltage to an electrode, the electrode electrically coupled to an insulator and further electrically coupled to a conductive region, the conductive region forming at least a part of a conductive path, the insulator comprising at least one of a transition metal and a refractory metal; andstoring a charge based on the voltage.2. The method of claim 1 , wherein storing includes storing using the insulator.3. The method of claim 1 , wherein transmitting includes transmitting using the insulator.4. The method of claim 1 , wherein transmitting includes transmitting using an insulator comprising HfTaON.5. A method comprising:receiving a signal using a circuit device including a dielectric portion located between two or more conductive regions, the dielectric comprising a transition metal and a refractory metal; andcoupling the signal to provide an electric field, the electric field strength based on the dielectric portion.6. The method of claim 5 , including:transmitting the signal using circuitry associated with at least one of a mixed signal circuit, a radio frequency device, a transceiver, and an optical transmitter.7. The method of claim 5 , wherein receiving includes receiving using a circuit associated with a portable wireless device.8. The method of claim 5 , wherein receiving includes receiving using a circuit associated with at least one of a processor claim 5 , a controller claim 5 , and a memory.9. The method of claim 5 , wherein receiving includes receiving using a circuit including a dielectric portion comprising HfTaON.10. The ...

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Номер записи: 56

07-11-2013 дата публикации

MEMORY DEVICE HAVING A DIELECTRIC CONTAINING DYSPROSIUM DOPED HAFNIUM OXIDE

Номер: US20130292782A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит:

The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition, to form a dielectric layer of hafnium oxide doped with dysprosium and a method of fabricating such a combination produces a reliable structure for use in a variety of electronic devices. The dielectric structure can include hafnium oxide on a substrate surface followed by dysprosium oxide, and repeating to form a thin laminate structure. A dielectric layer of dysprosium doped hafnium oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memories, or as a dielectric in NROM devices. 1. A memory device comprising:a substrate;a dielectric over the substrate, the dielectric comprising hafnium oxide and dysprosium; anda gate over the dielectric.2. The memory device of wherein the dielectric comprises a plurality of hafnium oxide layers interleaved with at least one dysprosium oxide layer.3. The memory device of wherein the dielectric comprises the dysprosium oxide layer between the plurality of hafnium oxide layers.4. The memory device of wherein the substrate comprises one of silicon claim 1 , germanium claim 1 , gallium arsenide claim 1 , or silicon-on-sapphire.5. The memory device of wherein the dielectric comprises the hafnium oxide doped with the dysprosium.6. The memory device of wherein the dielectric comprises the hafnium oxide doped with dysprosium oxide.7. The memory device of wherein the substrate comprises a hydrogen terminated surface.8. The memory device of wherein the hydrogen terminated surface comprises a hydrogen terminated surface without a native silicon oxide layer.9. The memory device of wherein the dielectric comprises nine hafnium oxide layers doped with the dysprosium.10. The memory device of wherein the dielectric comprises a single alloyed hafnium oxide layer doped with dysprosium.11. The memory device of wherein the dielectric comprises a nanolaminate film having layers of ...

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Номер записи: 57

28-11-2013 дата публикации

FIN-JFET

Номер: US20130313618A1

Автор: El-Kareh Badih, Forbes Leonard

Принадлежит: MICRON TECHNOLOGY, INC.

Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate. 1. A system on a chip , comprising:at least one analog circuit component having a Fin-JFET;digital circuit components including a processor and a memory device coupled to the processor; andwherein at least one digital circuit component has a Fin-MOSFET, and the Fin-JFET and the Fin-MOSFET are formed on a common substrate according to a CMOS process.2. The system on a chip of claim 1 , wherein the at least one Fin-JFET and the at least one Fin-MOSFET have a quasi-planar topography.3. The system on a chip of claim of claim 2 , wherein the quasi-planar topography includes:a gate conductive material contact landing pad recessed to a height not exceeding a source and drain height; andareas between semiconductor structures filled with spacer dielectric.4. The system on a chip of claim of claim 1 , wherein:Fin-MOSFET source and drain extensions are formed on a semiconductor Fin surface located furthest away from the substrate, adjacent to a gate dielectric material so as to reduce series resistance; andsource and drain contacts are formed on the semiconductor Fin surface located furthest away from the substrate.5. The system on a chip of claim 1 , wherein a Fin structure associated with the Fin-JFET has a width different than a width of a Fin structure associated with the Fin-MOSFET.6. The system on a chip of claim 1 , wherein fin structures for the Fin-JFET and the Fin-MOSFET are formed to substantially a same height out of a same semiconductor material.7. A system on a chip claim 1 , comprising:at least one analog circuit component having a number of Fin-JFETs formed on a substrate; andat least one digital circuit component having a number of Fin-MOSFETs formed on the substrate,wherein a Fin structure associated with the number of Fin-JFETs has a width different ...

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Номер записи: 58

06-02-2014 дата публикации

DIELECTRICS CONTAINING AT LEAST ONE OF A REFRACTORY METAL OR A NON-REFRACTORY METAL

Номер: US20140035101A1

Автор: Ahn Kie Y., Bhattacharyya Arup, Forbes Leonard

Принадлежит: MICRON TECHNOLOGY, INC.

Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory metal for use in a variety of electronic systems and devices. Embodiments can include electronic apparatus and methods of forming the electronic apparatus having a tantalum aluminum oxynitride film. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film. 1. A storage capacitor comprising:two or more electrode layers; andone or more dielectric layers, at least one of the one or more dielectric layers including at least one refractory metal oxynitride layer, wherein at least a portion of the at least one refractory metal oxynitride layer is interposed between the two or more electrode layers.2. The storage capacitor of claim 1 , wherein the refractory metal oxynitride layer includes TaAlON.3. The storage capacitor of claim 1 , wherein the one or more dielectric layers includes a TaAlON tunnel layer.4. The storage capacitor of claim 1 , wherein the one or more dielectric layers includes a nanolaminate composite.5. The storage capacitor of claim 4 , wherein the nanolaminate structure includes at least one of a Ta2O5/Al2O3 claim 4 , a TaON/AlON claim 4 , a Ta2O5/AlN claim 4 , a TaN/Al2O3 claim 4 , and a TaN/AlN structure.6. The storage capacitor of claim 4 , wherein the two or more electrodes are configured to form at least a portion of a flash memory. This application is a divisional of U.S. application Ser. No. 13/368,206, filed Feb. 7, 2012, which is a divisional of U.S. application Ser. No. 12/838,983, filed Jul. 19, 2010, now issued as U.S. Pat. No. 8,114,763, which is a divisional of U.S. application Ser. No. 11/514,655, filed on Aug. 31, 2006, now issued as U.S. Pat. No. 7,759,747, all of which are hereby ...

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Номер записи: 59

06-03-2014 дата публикации

ELECTRONIC DEVICES INCLUDING BARIUM STRONTIUM TITANIUM OXIDE FILMS

Номер: US20140065806A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит: MICRON TECHNOLOGY, INC.

Apparatus and methods of forming the apparatus include a dielectric layer containing barium strontium titanium oxide layer, an erbium-doped barium strontium titanium oxide layer, or a combination thereof. Embodiments of methods of fabricating such dielectric layers provide dielectric layers for use in a variety of devices. Embodiments include forming barium strontium titanium oxide film using atomic layer deposition. Embodiments include forming erbium-doped barium strontium titanium oxide film using atomic layer deposition. 1. A method comprising:forming a layer of strontium titanium oxide by atomic layer deposition;forming a layer of barium titanium oxide by atomic layer deposition; andannealing the layers of strontium titanium oxide and barium titanium oxide to form a layer of barium strontium titanium oxide.2. The method of claim 1 , wherein the method includes doping the barium strontium titanium oxide with erbium.3. The method of claim 1 , wherein the method includes forming alternating layers of SrTiOand BaTiObefore annealing.4. The method of claim 1 , wherein the method includes forming an amorphous barium strontium titanium oxide layer.5. The method of claim 1 , wherein the method includes forming a BaSrTiOlayer.6. The method of claim 1 , wherein forming the layer of barium strontium titanium oxide includes forming the layer of barium strontium titanium oxide as a capacitor dielectric in a capacitor in an integrated circuit.7. The method of claim 1 , wherein forming the layer of barium strontium titanium oxide includes forming the layer of barium strontium titanium oxide as a dielectric layer in a memory.8. The method of claim 1 , wherein forming the layer of barium strontium titanium oxide includes forming the layer of barium strontium titanium oxide as a gate insulator in a transistor.9. The method of claim 1 , wherein forming the layer of barium strontium titanium oxide includes forming the layer of barium strontium titanium oxide as a gate insulator in a ...

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Номер записи: 60

27-03-2014 дата публикации

APPARATUS HAVING A DIELECTRIC CONTAINING SCANDIUM AND GADOLINIUM

Номер: US20140084355A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит: MICRON TECHNOLOGY, INC.

Apparatus having a dielectric containing scandium and gadolinium can provide a reliable structure with a high dielectric constant (high k). In an embodiment, a monolayer or partial monolayer sequence process, such as for example atomic layer deposition (ALD), can be used to form a dielectric containing gadolinium oxide and scandium oxide. In an embodiment, a dielectric structure can be formed by depositing gadolinium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing scandium oxide onto the substrate using precursor chemicals, and repeating to form a thin laminate structure. A dielectric containing scandium and gadolinium may be used as gate insulator of a MOSFET, a capacitor dielectric in a DRAM, as tunnel gate insulators in flash memories, as a NROM dielectric, or as a dielectric in other electronic devices, because the high dielectric constant (high k) of the film provides the functionality of a much thinner silicon dioxide film. 1. A memory device comprising:a substrate comprising a plurality of diffusions;{'sub': X', 'Y', '3, 'a dielectric layer formed on the substrate between the plurality of diffusions, the dielectric layer comprising GdScO; and'}a gate electrode formed on the dielectric layer.2. The memory device of wherein the dielectric layer is configured to comprise a tunnel gate insulator and a floating gate dielectric.3. The memory device of wherein the dielectric layer is configured to comprise a floating gate and a control gate oxide.4. The memory device of wherein the dielectric layer comprises interleaved layers of scandium oxide and gadolinium oxide.5. The memory device of wherein a ratio of thicknesses of the interleaved layers is not equal.6. The memory device of wherein the layers of scandium oxide and the gadolinium oxide are configured such that the scandium oxide and the gadolinium oxide together have a dielectric constant equal to that of GdScO.7. The memory device of wherein a first ...

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Номер записи: 61

21-01-2016 дата публикации

METHODS OF FORMING STRAINED SEMICONDUCTOR CHANNELS

Номер: US20160020322A1

Автор: Bhattacharyya Arup, Farrar Paul A., Forbes Leonard

Принадлежит:

In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region has a channel region and the isolation regions have strain-inducing regions laterally adjacent to the channel regions. The channel region is strained with a desired strain for carrier mobility enhancement, where at least one ion type is implanted with an energy resulting in a peak implant in the strain-inducing regions of the isolation regions. Other aspects and embodiments are provided herein. 1. (canceled)2. A semiconductor structure , comprising:a semiconductor substrate including a device region in the substrate and isolation regions in the substrate adjacent to the device region, wherein a deepest part of the isolation regions is at an isolation region depth;the device region including a first source/drain region in the substrate, a second source/drain region in the substrate, and a channel region in the substrate between the first source/drain region and the second source drain region, wherein a deepest part of the first and second source/drain regions is at a source/drain region depth;the isolation regions being formed in isolation trenches having inner trench walls proximate to the device region and an opposing outer trench walls, wherein an oxide is on the outer trench walls and is not on the inner trench walls;the isolation regions having strain-inducing regions laterally adjacent to the channel region, wherein portions of the isolation regions have adjusted volumes laterally adjusting an inner extent of the strain inducing regions with respect to the inner trench walls to strain the channel region, and wherein a deepest part of the strain-inducing regions is at a strain-inducing depth, both the isolation region depth and the source/drain region depth being deeper than the strain-inducing region depth; andthe channel region including a strain induced by the strain-inducing regions in the isolation ...

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Номер записи: 62

05-02-2015 дата публикации

Charge trapping dielectric structures

Номер: US20150035043A1

Автор: Kie Y. Ahn, Leonard Forbes

Принадлежит: Micron Technology Inc

A dielectric structure may be arranged having a thin nitrided surface of an insulator with a charge blocking insulator over the nitrided surface. The insulator may be formed of a number of different insulating materials such as a metal oxide, a metal oxycarbide, a semiconductor oxide, or oxycarbide. In an embodiment, the dielectric structure may be formed by nitridation of a surface of an insulator using ammonia and deposition of a blocking insulator having a larger band gap than the insulator. The dielectric structure may form part of a memory device, as well as other devices and systems.

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Номер записи: 63

05-02-2015 дата публикации

Capacitors and methods with praseodymium oxide insulators

Номер: US20150035119A1

Автор: Arup Bhattacharyya, Kie Y. Ahn, Leonard Forbes

Принадлежит: Micron Technology Inc

Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.

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Номер записи: 64

17-02-2022 дата публикации

PHOTOSENSITIVE IMAGING DEVICES AND ASSOCIATED METHODS

Номер: US20220052102A1

Автор: Forbes Leonard, Haddad Homayoon, Jiang Jutao, McKee Jeffrey, Miller Drake, Palsule Chintamani

Принадлежит:

Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor substrate having multiple doped regions forming at least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and an electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least one junction. In one aspect, the textured region is operable to facilitate generation of an electrical signal from the detection of infrared electromagnetic radiation. In another aspect, interacting with electromagnetic radiation further includes increasing the semiconductor substrate's effective absorption wavelength as compared to a semiconductor substrate lacking a textured region. 1. A photosensitive imager device , comprising:a semiconductor substrate having multiple doped regions forming a least one junction;a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, wherein said textured region is configured to selectively filter at least a portion of electromagnetic radiation incident thereon; andan electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least one junction.228-. (canceled) This application is a continuation of U.S. patent application Ser. No. 15/898,357, filed on Feb. 16, 2018, which is a continuation of U.S. patent application Ser. No. 14/223,938, filed on Mar. 24, 2014, now issued as U.S. Pat. No. 9,911,781, which is a continuation of U.S. patent application Ser. No. 12/885,158, filed on Sep. 17, 2010, now issued as U.S. Pat. No. 8,680,591, which claims the benefit of U.S. Provisional Patent Application Ser. No. 61/243,434, filed on Sep. 17, 2009, U.S. Provisional Patent Application Ser. No. 61/311,004 filed on Mar. 5, 2010, and U.S. Provisional Patent ...

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Номер записи: 65

11-02-2016 дата публикации

LOW-POWER NONVOLATILE MEMORY CELLS WITH SELECT GATES

Номер: US20160042793A1

Автор: Forbes Leonard

Принадлежит:

Technologies are generally described for low-power nonvolatile memory cells configured with select gates. A nonvolatile memory cell may have a transistor body, a select gate and a floating gate both coupled to the body, and a control gate coupled to the floating gate. Charge stored on the floating gate may indicate the data stored on the memory cell, and the control gate may be configured to adjust the charge stored on the floating gate. The select gate may be used to adjust the state of the transistor body to facilitate the adjustment of charge on the floating gate, and may also be used to render the memory cell unresponsive to the control gate. 1. A method to adjust a nonvolatile memory cell having a transistor body , a select gate coupled to the transistor body , a floating gate coupled to the transistor body , and a control gate coupled to the floating gate , the method comprising:determining a memory operation to be performed on the nonvolatile memory cell;selecting the nonvolatile memory cell from a plurality of nonvolatile memory cells based on the determined memory operation to be performed;determining a cell operation to be performed on the nonvolatile memory cell based on the determined memory operation to be performed for the nonvolatile memory cell;selecting a potential from a plurality of potentials based on the determined cell operation to be performed, wherein each potential in the plurality of potentials corresponds to a respective body state of the transistor body;applying the selected potential to the select gate; andadjusting a number of electrons stored on the floating gate of the nonvolatile memory cell responsive to the control gate of the nonvolatile memory cell based on the determined cell operation and the body state that corresponds to the selected potential applied to the select gate of the nonvolatile memory cell.2. The method of claim 1 , wherein determining the operation to be performed comprises determining the operation as one of a ...

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Номер записи: 66

22-05-2014 дата публикации

CAPACITORS AND METHODS WITH PRASEODYMIUM OXIDE INSULATORS

Номер: US20140138795A1

Автор: Ahn Kie Y., Bhattacharyya Arup, Forbes Leonard

Принадлежит: MICRON TECHNOLOGY, INC.

Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties. 1. A method of forming a capacitor , comprising:forming a horizontal first electrode on a semiconductor substrate; forming at least one chemically adhered monolayer that includes praseodymium; and', 'oxidizing the at least one chemically adhered monolayer to form a praseodymium oxide monolayer;', 'forming a second horizontal metal electrode over the dielectric; and, 'forming a dielectric over a portion of the horizontal first electrode, includingforming interfacial layers between the dielectric and the electrodes.2. The method of claim 1 , wherein forming interfacial layers includes forming at least one Pr—O—N interfacial layer.3. The method of claim 2 , wherein forming Pr—O—N interfacial layers includes forming layers including approximately 40 atomic percent praseodymium claim 2 , approximately 20 atomic percent oxygen claim 2 , and approximately 40 atomic percent nitrogen.4. The method of claim 1 , wherein forming interfacial layers includes forming at least one TiN interfacial layer.5. The method of claim 1 , wherein forming interfacial layers includes forming at least one Ti—Si—N interfacial layer.6. The method of claim 1 , wherein forming interfacial layers includes forming at least one Pr—Si—O interfacial ...

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Номер записи: 67

10-03-2016 дата публикации

Backside Illuminated Image Sensor

Номер: US20160071900A1

Автор: Forbes Leonard, Haddad Homayoon, Hynecek Jaroslav, Joy Thomas

Принадлежит:

A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer disposed on the backside passivation layer. 1. A method for manufacturing a backside illuminated image sensor , the method comprising:forming a light-receiving element in a substrate;forming a patterned conductive layer over the substrate, wherein the patterned conductive layer includes an interconnection layer and an interlayer insulation layer;forming an align key spaced apart from the light-receiving element and passing through the interlayer insulation layer and the substrate, wherein the patterned conductive layer is electrically coupled to the align key;forming a backside passivation layer over the substrate; andforming a transparent conductive layer over the backside passivation layer proximate the light-receiving element, wherein the transparent conductive layer is electrically coupled to the align key.2. The method of claim 1 , further comprising forming both a color filter and a microlens over the transparent conductive layer proximate the light-receiving element.3. The method of claim 1 , further comprising:forming a front side passivation layer over a front side of the patterned conductive layer; andforming a further substrate over the front side passivation layer.4. The method of claim 3 , wherein said forming a further substrate over the front side passivation layer comprises bonding a silicon-on-insulator substrate over the front side passivation layer.5. The method of claim 1 , wherein said forming a backside passivation layer comprises forming a backside passivation layer having a multi-layered structure including layers with different refractive indexes.6. The method of claim 1 , wherein said forming a backside passivation layer comprises forming a backside passivation layer including a layer having a lower refractive index than the substrate.7. The method of claim 1 , wherein said forming ...

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Номер записи: 68

19-06-2014 дата публикации

SEMICONDUCTOR DEVICE STRUCTURES INCLUDING STRAINED TRANSISTOR CHANNELS

Номер: US20140167186A1

Автор: Bhattacharyya Arup, Farrar Paul A., Forbes Leonard

Принадлежит: MICRON TECHNOLOGY, INC.

The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed. 1. A semiconductor device structure , comprising: a source and a drain in a substrate on opposing sides of a transistor gate, a strained transistor channel positioned between the source and the drain;', 'opposing regions of a semiconductor material each comprising a plurality of nanocavities, a first of the opposing regions of the semiconductor material located between the strained transistor channel and the source, and a second of the opposing regions of the semiconductor material located between the strained transistor channel and the drain;', 'a source extension at least partially underlying the first of the opposing regions of the semiconductor material and located between the strained transistor channel and the source; and', 'a drain extension at least partially underlying the second of the opposing regions of the semiconductor material and located between the strained transistor channel and the drain., 'at least one transistor comprising2. The semiconductor device structure of claim 1 , wherein each of the opposing regions of the semiconductor material has a base located about 500 Å beneath a surface of the substrate and a thickness of less than or equal to about 1 claim 1 ...

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Номер записи: 69

19-06-2014 дата публикации

METHODS OF FORMING AND PROGRAMMING MEMORY DEVICES WITH ISOLATION STRUCTURES

Номер: US20140169103A1

Автор: El-Kareh Badih, Forbes Leonard

Принадлежит: MICRON TECHNOLOGY, INC.

Methods of programming and forming memory devices. Methods of programming include biasing a control gate of a selected memory cell of the memory device to a first voltage, the control gate being over a first conductive region having a first conductivity type and the first conductive region being over a second conductive region having a second conductivity type different than the first conductivity type; biasing the second conductive region to a second voltage to forward bias the junction from the second conductive region to the first conductive region; and injecting electrons into a charge-storage node of the selected memory cell from the second conductive region. The first conductive region and the second conductive region are contained within a dielectric isolation structure in which at least the selected memory cell is contained. 1. A method of programming a memory device , comprising:biasing a control gate of a selected memory cell of the memory device to a first voltage, the control gate being over a first conductive region having a first conductivity type and the first conductive region being over a second conductive region having a second conductivity type different than the first conductivity type;biasing the second conductive region to a second voltage to forward bias the junction from the second conductive region to the first conductive region; andinjecting electrons into a charge-storage node of the selected memory cell from the second conductive region;wherein the first conductive region and the second conductive region are contained within a dielectric isolation structure in which at least the selected memory cell is contained.2. The method of claim 1 , further comprising:floating the first conductive region while biasing the second conductive region to the second voltage.3. The method of claim 1 , further comprising:biasing the control gate of the selected memory cell to a positive voltage while biasing the second conductive region to a negative ...

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Номер записи: 70

02-04-2020 дата публикации

Process module for increasing the response of backside illuminated photosensitive imagers and associated methods

Номер: US20200105822A1

Автор: Chintamani Palsule, Drake Miller, Homayoon Haddad, Jeffrey McKee, Jutao Jiang, Leonard Forbes

Принадлежит: SiOnyx LLC

Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation where the textured region includes surface features sized and positioned to facilitate tuning to a preselected wavelength of light, and a dielectric region positioned between the textured region and the at least one junction. The dielectric region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction.

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Номер записи: 71

28-04-2016 дата публикации

ZrAlON FILMS

Номер: US20160118259A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит:

Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. The dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric, and a tunnel gate insulator in flash memories. 1. A method comprising:forming zirconium aluminum oxynitride by forming an insulating zirconium compound and an insulating aluminum compound using a monolayer by monolayer sequencing technique and processing the formed insulating zirconium compound and the formed insulating aluminum compound into zirconium aluminum oxynitride; andforming an electrically conductive material adjacent the zirconium aluminum oxynitride.2. The method of claim 1 , wherein forming the insulating zirconium compound includes forming ZrN.3. The method of claim 1 , wherein processing the formed insulating zirconium compound and the insulating aluminum compound into zirconium aluminum oxynitride includes converting the formed insulating zirconium compound and the insulating aluminum compound into zirconium aluminum oxynitride by rapid thermal annealing.4. The method of claim 3 , wherein converting by rapid thermal annealing includes depositing interleaved layers of ZrNand AlOand rapid thermal annealing the interleaved layers of ZrNand AlOto form the zirconium aluminum oxynitride.5. The method of claim 1 , wherein forming the insulating zirconium compound and the insulating aluminum compound includes forming a zirconium oxide compound and an aluminum nitride compound.6. The method of claim 5 , wherein forming the zirconium oxide compound and the aluminum nitride compound includes forming a series of interleaved layers of ZrOand AlN.7. The method of claim 6 , wherein processing the series of interleaved ...

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Номер записи: 72

17-07-2014 дата публикации

PHOTOSENSITIVE IMAGING DEVICES AND ASSOCIATED METHODS

Номер: US20140197509A1

Автор: Forbes Leonard, Haddad Homayoon, Jiang Jutao, McKee Jeffrey, Miller Drake, Palsule Chintamani

Принадлежит: SiOnyx, Inc.

Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and a passivation region positioned between the textured region and the at least one junction. The passivation region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction. 1. A photosensitive imager device , comprising:a plurality of semiconductor devices including semiconductor substrates having a light incident side and multiple doped regions forming at least one junction;a textured region coupled to the light incident side of the semiconductor substrate and positioned to interact with electromagnetic radiation; andat least one isolation feature operable to isolate the plurality of semiconductor devices from each other.2. The device of claim 1 , wherein the at least one isolation feature operable to electrically isolate the plurality of semiconductor devices from each other.3. The device of claim 1 , wherein the at least one isolation feature operable to optically isolate the plurality of semiconductor devices from each other.4. The device of claim 1 , wherein the at least one isolation feature is a deep trench isolation feature.5. The device of claim 1 , wherein the at least one isolation feature is a shallow trench isolation feature.6. The device of claim 1 , wherein the at least one isolation feature includes a ...

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Номер записи: 73

04-09-2014 дата публикации

GROWN NANOFIN TRANSISTORS

Номер: US20140246651A1

Автор: Forbes Leonard

Принадлежит: MICRON TECHNOLOGY, INC.

One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy (SPE) process is performed to crystallise the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The fin has a cross-sectional thickness in at least one direction less than a minimum feature size. The transistor body is formed in the crystallised semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein. 1. A transistor , comprising:a crystalline substrate;a crystalline semiconductor fin on the substrate, the semiconductor fin having a cross-sectional dimension that is less than a minimum feature size, wherein the fin provides a vertically-oriented channel between a lower source/drain region and an upper source/drain region;a gate insulator formed around the fin; anda surrounding gate formed around and separated from the fin by the gate insulator.2. The transistor of claim 1 , wherein the crystalline substrate is a silicon wafer.3. The transistor of claim 1 , wherein the gate insulator includes silicon oxide.4. The transistor of claim 1 , wherein the gate includes polysilicon.5. The transistor of claim 1 , wherein the gate includes metal.6. A transistor claim 1 , comprising:a crystalline silicon substrate;a first source/drain region formed in the crystalline silicon substrate;a crystalline silicon fin on the substrate and over the first source/drain region, the silicon fin having a cross-sectional dimension that is less than a minimum feature size;a second source/drain region formed in a top portion of the fin to define a vertically-oriented channel ...

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Номер записи: 74

18-06-2015 дата публикации

BONDED STRAINED SEMICONDUCTOR WITH A DESIRED SURFACE ORIENTATION AND CONDUCTANCE DIRECTION

Номер: US20150171165A1

Автор: Forbes Leonard

Принадлежит:

According to various method embodiments, a semiconductor layer is oriented to a substrate. The semiconductor layer has a surface orientation and is oriented to the substrate to provide a desired direction of conductance for the surface orientation. The oriented semiconductor layer is bonded to the substrate to strain the semiconductor layer. Various embodiments provide a tensile strain, and various embodiments provide a compressive strain. Other aspects and embodiments are provided herein. 1. A structure , comprising:a substrate;a crystalline semiconductor layer bonded to the substrate, the semiconductor layer having a surface orientation and a desired channel conductance direction for the surface orientation, the crystalline semiconductor layer having a local strained region; anda gate oxide over the local strained region, a gate over the gate oxide, and first and second source/drain regions to provide a channel region with the desired channel conductance direction within in the local strained region.2. The structure of claim 1 , wherein the local strained region includes a uniaxial tensile strain.3. The structure of claim 1 , wherein the local strained region includes a uniaxial compressive strain.4. The structure of claim 1 , wherein the crystalline semiconductor layer includes a silicon layer with a (100) crystalline orientation and the desired channel conductance direction is a <110> direction with respect to the crystalline orientation.5. The structure of claim 1 , wherein the crystalline semiconductor layer includes a silicon layer with a (110) crystalline orientation and the desired channel conductance direction is a <100> direction with respect to the crystalline orientation.6. The structure of claim 1 , wherein the crystalline semiconductor layer includes a silicon layer with a (111) crystalline orientation and the desired channel conductance direction is a <110> direction with respect to the crystalline orientation.7. The structure of claim 1 , wherein ...

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Номер записи: 75

18-09-2014 дата публикации

SILICON ON GERMANIUM

Номер: US20140264555A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит: MICRON TECHNOLOGY, INC.

A monolayer or partial monolayer sequencing processing, such as atomic layer deposition (ALD), can be used to form a semiconductor structure of a silicon film on a germanium substrate. Such structures may be useful in high performance electronic devices. A structure may be formed by deposition of a thin silicon layer on a germanium substrate surface, forming a hafnium oxide dielectric layer, and forming a tantalum nitride electrode. The properties of the dielectric may be varied by replacing the hafnium oxide with another dielectric such as zirconium oxide or titanium oxide. 1at least one transistor containing an atomic layer deposited layer of silicon, an atomic layer deposited layer of a metal oxide in an integrated circuit; anda conductive layer contacting the dielectric layer.. An electronic device comprising: This application is a Continuation of U.S. application Ser. No. 13/617,211, filed 14 Sep. 2012, which is a Continuation of U.S. application Ser. No. 12/829,099, filed 1 Jul. 2010, now issued as U.S. Pat. No. 8,269,254, which is a Divisional of U.S. application Ser. No. 11/498,576, filed 3 Aug. 2006, now issued as U.S. Pat. No. 7,749,879, all of which are incorporated herein by reference in their entirety.This application relates generally to semiconductor devices and device fabrication and, more particularly to semiconductor structures formed on germanium substrates.The semiconductor device industry has a continuous market driven need to improve the operational speed of electronic devices. Previously improved operational speed has been obtained by scaling the devices to reduce the transistor size. Smaller transistors result in improved operational speed and clock rate, and reduced power requirements in both standby and operational modes. To reduce transistor size, the thickness of the silicon dioxide (SiO) gate dielectric is reduced in proportion to the shrinkage of the silicon gate length. For example, a metal-oxide-semiconductor field effect transistor ( ...

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Номер записи: 76

21-06-2018 дата публикации

PHOTOSENSITIVE IMAGING DEVICES AND ASSOCIATED METHODS

Номер: US20180175093A1

Автор: Forbes Leonard, Haddad Homayoon, Jiang Jutao, McKee Jeffrey, Miller Drake, Palsule Chintamani

Принадлежит:

Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor substrate having multiple doped regions forming at least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and an electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least one junction. In one aspect, the textured region is operable to facilitate generation of an electrical signal from the detection of infrared electromagnetic radiation. In another aspect, interacting with electromagnetic radiation further includes increasing the semiconductor substrate's effective absorption wavelength as compared to a semiconductor substrate lacking a textured region. 128-. (canceled)29. A photosensitive imager pixel , comprising:a semiconductor substrate having a radiation-receiving surface for receiving incident electromagnetic radiation and multiple doped regions forming at least one junction,a textured region associated with the semiconductor substrate and positioned to receive at least a portion of the incident electromagnetic radiation and interact with said received electromagnetic radiation to cause at least a portion of said electromagnetic radiation to experience multiple passes within said semiconductor substrate so as to enhance quantum efficiency of said imager device, andan electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal generated in response to absorption of the electromagnetic radiation within said semiconductor substrate.30. The photosensitive imager pixel of claim 29 , wherein said semiconductor substrate comprises said textured region.31. The photosensitive imager pixel of claim 29 , wherein said textured region is coupled to a surface opposite the radiation-receiving surface.32. The photosensitive ...

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Номер записи: 77

09-07-2015 дата публикации

ZrA1ON FILMS

Номер: US20150194299A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит:

Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. The dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric, and a tunnel gate insulator in flash memories. 1. A method comprising:forming a dielectric layer on a substrate containing at least one aluminum oxide layer and at least one zirconium nitride layer using an atomic layer deposition; andforming an electrically conductive layer on the dielectric layer.2. The method of claim 1 , wherein forming the dielectric layer includes forming an amorphous dielectric.3. The method of claim 1 , wherein the substrate includes at least one conductive layer disposed below the dielectric layer.4. The method of claim 1 , wherein the substrate includes at least two diffused regions having a first conductivity type claim 1 , separated by a region of a second conductivity type disposed below the dielectric layer and metal layer.5. The method of claim 1 , wherein a ratio of zirconium to aluminum is about 1.6. The method of claim 1 , wherein a dielectric constant of the dielectric layer is about 18.7. The method of claim 1 , wherein the aluminum oxide layer comprises a plurality of individually deposited aluminum oxide layers claim 1 , and each individual one of the layers is less than or equal to two monolayers in thickness.8. The method of claim 7 , wherein each individual one of the aluminum oxide layers has a thickness of about 1.3 to 1.5 Angstroms.9. The method of claim 1 , wherein the dielectric layer has a root mean square surface roughness that is less than one tenth of the layer thickness.10. The method of claim 1 , wherein the dielectric film is separated from the substrate by a diffusion ...

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Номер записи: 78

16-10-2014 дата публикации

BACKSIDE NANOSCALE TEXTURING TO IMPROVE IR RESPONSE OF SILICON SOLAR CELLS AND PHOTODETECTORS

Номер: US20140306307A1

Автор: Forbes Leonard

Принадлежит:

The absorption coefficient of silicon for infrared light is very low and most solar cells absorb very little of the infrared light energy in sunlight. Very thick cells of crystalline silicon can be used to increase the absorption of infrared light energy but the cost of thick crystalline cells is prohibitive. The present invention relates to the use of less expensive microcrystalline silicon solar cells and the use of backside texturing with diffusive scattering to give a very large increase in the absorption of infrared light. Backside texturing with diffusive scattering and with a smooth front surface of the solar cell results in multiple internal reflections, light trapping, and a large enhancement of the absorption of infrared solar energy. 1. A semiconductor imager capable of absorbing infrared light , comprising: a semiconductor substrate having a substantially planar first surface available to receive incident radiation and a second surface opposite the first surface; and', 'a light diffusing region optically coupled to the second surface wherein the light diffusing region is configured to scatter light in a substantially Lambertian scattering pattern., 'a plurality of photodetectors each comprising2. The semiconductor imager of claim 1 , further comprising a reflecting layer coupled to the light diffusing region.3. The semiconductor imager of claim 1 , wherein the reflecting layer is comprised of a material selected from the group consisting of: oxide claim 1 , silicon oxide claim 1 , transparent conductive oxide claim 1 , metals claim 1 , and any combinations thereof.4. The semiconductor imager of claim 1 , wherein the semiconductor substrate is comprised of silicon.5. The semiconductor imager of claim 1 , wherein the semiconductor substrate has a thickness in the range of about 1 micrometers to about 10 micrometers.6. The semiconductor imager of claim 1 , wherein the light diffusing region includes features being formed on or within the light diffusing ...

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Номер записи: 79

16-10-2014 дата публикации

THREE DIMENSIONAL IMAGING UTILIZING STACKED IMAGER DEVICES AND ASSOCIATED METHODS

Номер: US20140307059A1

Автор: FENG CHEN, Forbes Leonard, Haddad Homayoon

Принадлежит:

Stacked imager devices that can determine distance and generate three dimensional representations of a subject and associated methods are provided. In one aspect, an imaging system can include a first imager array having a first light incident surface and a second imager array having a second light incident surface. The second imager array can be coupled to the first imager array at a surface that is opposite the first light incident surface, with the second light incident surface being oriented toward the first imager array and at least substantially uniformly spaced. The system can also include a system lens positioned to direct incident light along an optical pathway onto the first light incident surface. The first imager array is operable to detect a first portion of the light passing along the optical pathway and to pass through a second portion of the light, where the second imager array is operable to detect at least a part of the second portion of light. 1. An imaging system capable of deriving three dimensional information from a three dimensional subject , comprising:a first imager array having a first light incident surface;a second imager array having a second light incident surface, the second imager array being coupled to the first imager array at a surface that is opposite the first light incident surface, the second light incident surface being oriented toward the first imager array and at least substantially uniformly spaced at a distance of from about 2 microns to about 150 microns from the first light incident surface; anda system lens positioned to direct incident light along an optical pathway onto the first light incident surface, wherein the first imager array is operable to detect a first portion of the light passing along the optical pathway and to pass through a second portion of the light, wherein the second imager array is operable to detect at least a part of the second portion of light, and wherein the first portion of light and the ...

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Номер записи: 80

02-08-2018 дата публикации

Three dimensional imaging utilizing stacked imager devices and associated methods

Номер: US20180216928A1

Автор: Chen Feng, Homayoon Haddad, Leonard Forbes

Принадлежит: SiOnyx LLC

Stacked imager devices that can determine distance and generate three dimensional representations of a subject and associated methods are provided. In one aspect, an imaging system can include a first imager array having a first light incident surface and a second imager array having a second light incident surface. The second imager array can be coupled to the first imager array at a surface that is opposite the first light incident surface, with the second light incident surface being oriented toward the first imager array and at least substantially uniformly spaced. The system can also include a system lens positioned to direct incident light along an optical pathway onto the first light incident surface. The first imager array is operable to detect a first portion of the light passing along the optical pathway and to pass through a second portion of the light, where the second imager array is operable to detect at least a part of the second portion of light.

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Номер записи: 81

30-10-2014 дата публикации

DIELECTRICS CONTAINING AT LEAST ONE OF A REFRACTORY METAL OR A NON-REFRACTORY METAL

Номер: US20140322923A1

Автор: Ahn Kie Y., Bhattacharyya Arup, Forbes Leonard

Принадлежит:

Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory metal for use in a variety of electronic systems and devices. Embodiments can include electronic apparatus and methods of forming the electronic apparatus having a tantalum aluminum oxynitride film. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film. 1. A method of making an integrated circuit device , the method comprising:forming a compound of aluminum including oxygen or nitrogen using the monolayer sequencing process; andprocessing the compound of tantalum and the compound of aluminum together forming tantalum aluminum oxynitride.2. The method of claim 1 , wherein processing the compound of tantalum and the compound of aluminum together includes:forming tantalum aluminum oxide; andperforming a nitridization of the tantalum aluminum oxide.3. The method of claim 2 , wherein performing the nitridization includes introducing nitrogen using a microwave plasma or introducing nitrogen using a NHanneal.4. The method of claim 1 , wherein forming the compound of tantalum includes forming tantalum nitride; forming the compound of aluminum includes forming aluminum nitride; and processing the compound of tantalum and the compound of aluminum together includes annealing and oxidizing the tantalum nitride and the aluminum nitride together.5. The method of claim 4 , wherein oxidizing the tantalum nitride and aluminum nitride includes oxidizing by a rapid thermal oxidation.6. The method of claim 1 , wherein forming the compound of tantalum includes forming tantalum oxynitride; forming the compound of aluminum includes forming aluminum oxynitride; processing the compound of tantalum and the compound of aluminum ...

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Номер записи: 82

06-11-2014 дата публикации

CONDUCTIVE LAYERS FOR HAFNIUM SILICON OXYNITRIDE FILMS

Номер: US20140327065A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит:

Electronic apparatus and methods of forming the electronic apparatus include HfSiON for use in a variety of electronic systems. In various embodiments, conductive material is coupled to a dielectric containing HfSiON, where such conductive material may include one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum. 1. An electronic device comprising:a dielectric including hafnium silicon oxynitride, the hafnium silicon oxynitride doped with elements or compounds other than hafnium or silicon; anda conductive material coupled to the dielectric.2. The electronic device of claim 1 , wherein the dielectric is structured as a stack of dielectrics.3. The electronic device of claim 1 , wherein the electronic device includes:tantalum as the conductive material coupled to the hafnium silicon oxynitride such that the tantalum is disposed as a gate with the hafnium silicon oxynitride as a gate insulator in a PMOS transistor of a CMOS structure; anda titanium nitride as a gate on another region of hafnium silicon oxynitride in a NMOS transistor of the CMOS structure such that the NMOS transistor and the PMOS transistor have substantially symmetrical threshold voltages.4. The electronic device of claim 1 , wherein the electronic device includes a memory device structured with the hafnium silicon oxynitride disposed in a nanolaminate containing silicon oxide as a charge storage region of the nanolaminate. This application is a divisional of U.S. application Ser. No. 13/305,338, filed Nov. 28, 2011, which is a continuation of U.S. application Ser. No. 12/772,473, filed May 3, 2010, now issued as U.S. Pat. No. 8,067,794, which is a divisional of U.S. application Ser. No. 11/355,490 filed Feb. 16, 2006, now issued as U.S. Pat. No. 7,709,402, all of which are incorporated herein by reference in their entirety.This application is related to the commonly assigned application U.S. application Ser. No. 10/229,903, filed on 28 Aug. 2002, now ...

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Номер записи: 83

17-09-2015 дата публикации

VERTICAL TRANSISTOR, MEMORY CELL, DEVICE, SYSTEM AND METHOD OF FORMING SAME

Номер: US20150262643A1

Автор: Forbes Leonard

Принадлежит:

A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are disclosed. A first source/drain region is formed in the semiconductor substrate and a body region and a second source/drain region are formed within the semiconductor pillar. A first gate is coupled to a first side of the semiconductor pillar for coupling the first and second source/drain regions together when activated. The vertical memory cell also includes a storage capacitor formed on an extended end of the semiconducting pillar and electrically coupled to the second source/drain region. 1. A method of using a semiconductor device , the method comprising:controlling conductive characteristics of an access transistor with a first signal applied to a first gate of the access transistor disposed on a first side of a pillar configured as a vertical transistor with a first source/drain region coupled to a bit line in a substrate, a body region over the first source/drain region, and a second source/drain region above the body region; andmodifying the conductive characteristics of the access transistor with a second signal applied to a second gate of the access transistor disposed on a second side of the pillar.2. The method of claim 1 , wherein the first signal and the second signal are asynchronously asserted.3. The method of claim 1 , wherein the first signal and the second signal are asynchronously negated.4. The method of claim 1 , wherein the first signal and the second signal are synchronously applied.5. The method of claim 4 , wherein the first signal and the second signal are applied with different activation voltages.6. The method of claim 1 , wherein the first signal and the second signal are applied with different activation voltages.7. The method of claim 1 , wherein the first signal and the second signal are applied with different activation voltages.8. A method of ...

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Номер записи: 84

24-09-2015 дата публикации

PHOTOSENSITIVE IMAGING DEVICES AND ASSOCIATED METHODS

Номер: US20150270306A1

Автор: Forbes Leonard, Haddad Homayoon, Jiang Jutao, McKee Jeffrey, Miller Drake, Palsule Chintamani

Принадлежит: SiOnyx, Inc.

Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor substrate having multiple doped regions forming at least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and an electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least one junction. In one aspect, the textured region is operable to facilitate generation of an electrical signal from the detection of infrared electromagnetic radiation. In another aspect, interacting with electromagnetic radiation further includes increasing the semiconductor substrate's effective absorption wavelength as compared to a semiconductor substrate lacking a textured region. 1. A photosensitive imager device , comprising:a semiconductor substrate having multiple doped regions forming a least one junction;a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation; andan electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least one junction.2. The device of claim 1 , wherein the textured region is operable to facilitate generation of an electrical signal from the detection of infrared electromagnetic radiation.3. The device of claim 1 , wherein interacting with electromagnetic radiation further includes increasing the semiconductor substrate's effective absorption length as compared to a semiconductor substrate lacking a textured region.4. The device of claim 1 , wherein the transfer element is selected from the group consisting of a transistor claim 1 , a sensing node claim 1 , a transfer gate claim 1 , and combinations thereof.5. The device of claim 1 , further comprising a reflective layer coupled to the semiconductor substrate and positioned to maintain the ...

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Номер записи: 85

08-10-2015 дата публикации

Vertically base-connected bipolar transistor

Номер: US20150287815A1

Автор: Badih El-Kareh, Kie Y. Ahn, Leonard Forbes

Принадлежит: Micron Technology Inc

Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor.

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Номер записи: 86

19-09-2019 дата публикации

PROCESS MODULE FOR INCREASING THE RESPONSE OF BACKSIDE ILLUMINATED PHOTOSENSITIVE IMAGERS AND ASSOCIATED METHODS

Номер: US20190289451A1

Автор: Forbes Leonard, Haddad Homayoon, Jiang Jutao, McKee Jeffrey, Miller Drake, Palsule Chintamani

Принадлежит:

Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation where the textured region includes surface features sized and positioned to facilitate tuning to a preselected wavelength of light, and a dielectric region positioned between the textured region and the at least one junction. The dielectric region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction. 1. A backside-illuminated photosensitive imager device , comprising:a semiconductor substrate having multiple doped regions forming a least one junction;a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, wherein the textured region includes surface features sized and positioned to facilitate tuning to a preselected wavelength of light;a dielectric region positioned between the textured region and the at least one junction, the dielectric region being positioned to isolate the at least one junction from the textured region, wherein the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region; andan electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least ...

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Номер записи: 87

26-10-2017 дата публикации

PHOTOSENSITIVE IMAGING DEVICES AND ASSOCIATED METHODS

Номер: US20170309669A9

Автор: Forbes Leonard, Haddad Homayoon, Jiang Jutao, McKee Jeffrey, Miller Drake, Palsule Chintamani

Принадлежит: SiOnyx, Inc.

Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor substrate having multiple doped regions forming at least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and an electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least one junction. In one aspect, the textured region is operable to facilitate generation of an electrical signal from the detection of infrared electromagnetic radiation. In another aspect, interacting with electromagnetic radiation further includes increasing the semiconductor substrate's effective absorption wavelength as compared to a semiconductor substrate lacking a textured region. 1. A photosensitive imager device , comprising:a semiconductor substrate having multiple doped regions forming a least one junction;a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation; andan electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least one junction.2. The device of claim 1 , wherein the textured region is operable to facilitate generation of an electrical signal from the detection of infrared electromagnetic radiation.3. The device of claim 1 , wherein interacting with electromagnetic radiation further includes increasing the semiconductor substrate's effective absorption length as compared to a semiconductor substrate lacking a textured region.4. The device of claim 1 , wherein the transfer element is selected from the group consisting of a transistor claim 1 , a sensing node claim 1 , a transfer gate claim 1 , and combinations thereof.5. The device of claim 1 , further comprising a reflective layer coupled to the semiconductor substrate and positioned to maintain the ...

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Номер записи: 88

12-11-2015 дата публикации

Dram with nanofin transistors

Номер: US20150325579A1

Автор: Leonard Forbes

Принадлежит: Micron Technology Inc

One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein.

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Номер записи: 89

31-12-2015 дата публикации

GALLIUM LANTHANIDE OXIDE FILMS

Номер: US20150380240A1

Автор: Ahn Kie Y., Forbes Leonard

Принадлежит:

Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The gallium lanthanide oxide film may be structured as one or more monolayers. The gallium lanthanide oxide film may be formed using atomic layer deposition. 1. A method for forming a capacitor comprising:forming a first electrode on a substrate;forming a dielectric layer containing a gallium gadolinium oxide film, the dielectric layer disposed on and contacting the first electrode, including forming the gallium gadolinium oxide film by atomic layer deposition; andforming a second electrode on and contacting the dielectric layer.2. The method of claim 1 , wherein forming the gallium gadolinium oxide film includes forming GaO(GdO) by atomic layer deposition.3. The method of claim 1 , wherein forming a dielectric layer includes forming the gallium gadolinium oxide film as the dielectric layer.4. The method of claim 1 , wherein the method includes forming a dynamic random access memory having the first electrode claim 1 , the dielectric layer claim 1 , and the second electrode as a capacitor in the dynamic random access memory.5. The method of claim 1 , wherein the method includes forming an analog integrated circuit having the first electrode claim 1 , the dielectric layer claim 1 , and the second electrode as a capacitor in the analog integrated circuit.6. The method of claim 1 , wherein the method includes forming a radio frequency integrated circuit having the first electrode claim 1 , the dielectric layer claim 1 , and the second electrode as a capacitor in the radio frequency integrated circuit.7. The method of claim 1 , wherein the method includes forming a mixed signal integrated circuit having the first electrode claim 1 , the dielectric layer claim 1 , and the second electrode as a capacitor in the mixed signal integrated circuit.8. The method of claim 1 , wherein forming a dielectric layer includes forming ...

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Номер записи: 90

07-03-2006 дата публикации

Silicon oxycarbide substrates for bonded silicon on insulator

Номер: US7008854B2

Автор: Leonard Forbes

Принадлежит: Micron Technology Inc

A method for forming a semiconductor on insulator structure includes forming a semiconductor layer on an insulating substrate, where the substrate is a different material than the semiconductor layer, and has a coefficient of thermal expansion substantially equal to that of the semiconductor layer. The semiconductor layer can also be formed having a thickness such that, it does not yield due to temperature-induced strain at device processing temperatures. A silicon layer bonded to a silicon oxycarbide glass substrate provides a silicon on insulator wafer in which circuitry for electronic devices is fabricated.

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Номер записи: 91

17-06-2004 дата публикации

Programmable fuse and antifuse and method therefor

Номер: US20040114433A1

Автор: Leonard Forbes

Принадлежит: Micron Technology Inc

P-channel MOSFET devices are used as reprogrammable fuse or antifuse elements in a memory decode circuit by utilizing anomalous hole generation. An applied negative gate bias voltage is sufficiently large to cause tunnel electrons to gain enough energy to exceed the band gap energy of the oxide. This causes energetic hole-electron pairs to be generated in the silicon substrate. The holes are then injected from the substrate into the oxide, where they remain trapped. A large shift in the threshold voltage of the p-channel MOSFET results. The device can subsequently be reset by applying a positive gate bias voltage. Various circuits incorporating such fuse or antifuse elements are also disclosed.

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Номер записи: 92

14-06-2005 дата публикации

Vertical NROM having a storage density of 1 bit per 1F2

Номер: US6906953B2

Автор: Leonard Forbes

Принадлежит: Micron Technology Inc

The multiple bit, vertical memory cell includes a vertical metal oxide semiconductor field effect transistor (MOSFET) extending horizontally outward from a substrate. The MOSFET has a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator. The gate insulator may be a composite of oxide-nitride-aluminum oxide. The MOSFET is operated with either the first source/drain region or the second source/drain region serving as the source region, depending on the voltages applied to these regions. A negative substrate bias is applied during programming and erasing operations to enhance hot carrier injection.

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Номер записи: 93

21-06-2005 дата публикации

Programmable memory cell using charge trapping in a gate oxide

Номер: US6909635B2

Автор: Eugene H. Cloud, Leonard Forbes, Wendell P. Noble

Принадлежит: Micron Technology Inc

An illustrative embodiment of the present invention includes a non-volatile, reprogrammable circuit switch. The circuit switch includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a source region, a drain region, a channel region between the source and drain regions, and a gate separated from the channel region by a gate oxide. According to the teachings of the present invention, the MOSFET is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region such that the channel region has a first voltage threshold region (Vt 1 ) and a second voltage threshold region (Vt 2 ).

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Номер записи: 94

25-07-2006 дата публикации

Lanthanide oxide dielectric layer

Номер: US7081421B2

Автор: Kie Y. Ahn, Leonard Forbes

Принадлежит: Micron Technology Inc

A ruthenium gate for a lanthanide oxide dielectric layer and a method of fabricating such a combination gate and dielectric layer produce a reliable structure for use in a variety of electronic devices. The lanthanide oxide dielectric layer is formed by depositing lanthanum by atomic layer deposition onto a substrate surface using a trisethylcyclopentadionatolanthanum precursor or a trisdipyvaloylmethanatolanthanum precursor. A ruthenium or a conductive ruthenium oxide gate may be formed on the lanthanide oxide dielectric layer. A ruthenium gate on a lanthanide oxide dielectric layer provides a gate structure that effectively prevents a reaction between the gate and the lanthanide oxide dielectric layer.

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Номер записи: 95

16-02-2010 дата публикации

Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer

Номер: US7662729B2

Автор: Kie Y. Ahn, Leonard Forbes

Принадлежит: Micron Technology Inc

Electronic apparatus and methods of forming the electronic apparatus include a conductive layer having a layer of ruthenium in contact with a lanthanide oxide dielectric layer for use in a variety of electronic systems. The lanthanide oxide dielectric layer and the layer of ruthenium may be structured as one or more monolayers. The lanthanide oxide dielectric layer and the layer of ruthenium may be formed by atomic layer deposition.

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Номер записи: 96

11-08-2009 дата публикации

Hafnium titanium oxide films

Номер: US7572695B2

Автор: Kie Y. Ahn, Leonard Forbes

Принадлежит: Micron Technology Inc

Embodiments of a dielectric layer containing a hafnium titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices.

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Номер записи: 97

29-06-2004 дата публикации

Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals

Номер: US6756298B2

Автор: Kie Y. Ahn, Leonard Forbes

Принадлежит: Micron Technology Inc

In recent years, copper wiring has emerged as a promising substitute for the aluminum wiring in integrated circuits, because copper offers lower electrical resistance and better reliability at smaller dimensions than aluminum. However, use of copper typically requires forming a diffusion barrier to prevent contamination of other parts of an integrated circuit and forming a seed layer to facilitate copper plating steps. Unfortunately, conventional methods of forming the diffusion barriers and seed layers require use of separate wafer-processing chambers, giving rise to transport delays and the introduction of defect-causing particles. Accordingly, the inventors devised unique wafer-processing chambers and methods of forming barrier and seed layers. One embodiment of the wafer-processing chamber includes equipment for physical vapor deposition and equipment for chemical vapor deposition to facilitate formation of diffusion barriers and seed layers within one chamber, thereby promoting fabrication efficiency and reducing defects.

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Номер записи: 98

10-01-2006 дата публикации

Methods for making copper and other metal interconnections in integrated circuits

Номер: US6984891B2

Автор: Kie Y. Ahn, Leonard Forbes

Принадлежит: Micron Technology Inc

A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Yet, aluminum wires have greater electrical resistance and are less reliable than copper wires. Unfortunately, current techniques for making copper wires are time-consuming and inefficient. Accordingly, the invention provides a method of making wires or interconnects from copper or other metals. One embodiment entails forming a first diffusion barrier inside a trench using ionized-magnetron sputtering for better conformal coating of the trench, and a second diffusion barrier outside the trench using jet-vapor deposition. The jet-vapor deposition has an acute angle of incidence which prevents deposition within the trench and thus eliminates conventional etching steps that would otherwise be required to leave the trench free of this material. After formation of the two diffusion barriers, the trench is filled with metal and annealed.

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Номер записи: 99

02-03-2010 дата публикации

Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals

Номер: US7670469B2

Автор: Kie Y. Ahn, Leonard Forbes

Принадлежит: Micron Technology Inc

In recent years, copper wiring has emerged as a promising substitute for the aluminum wiring in integrated circuits, because copper offers lower electrical resistance and better reliability at smaller dimensions than aluminum. However, use of copper typically requires forming a diffusion barrier to prevent contamination of other parts of an integrated circuit and forming a seed layer to facilitate copper plating steps. Unfortunately, conventional methods of forming the diffusion barriers and seed layers require use of separate wafer-processing chambers, giving rise to transport delays and the introduction of defect-causing particles. Accordingly, the inventors devised unique wafer-processing chambers and methods of forming barrier and seed layers. One embodiment of the wafer-processing chamber includes equipment for physical vapor deposition and equipment for chemical vapor deposition to facilitate formation of diffusion barriers and seed layers within one chamber, thereby promoting fabrication efficiency and reducing defects.

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Номер записи: 100

14-08-2001 дата публикации

Silicon multi-chip module packaging with integrated passive components and method of making

Номер: US6274937B1

Автор: Kie Y. Ahn, Leonard Forbes

Принадлежит: Micron Technology Inc

An apparatus is provided for the supply of passive electronic components to a chip containing circuitry capable of operating in a communications system. The invention provides a silicon interposer element chip package which includes a silicon substrate and which is capable of carrying one or more IC chips and which does not suffer semiconductor leeching problems. A silicon substrate is formed from a silicon layer and an insulating layer, preferably an oxide. The invention also provides passive circuits within the interposer element oxide layer. The interposer element is then bonded to an integrated circuit chip using flip-chip processing.

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Номер записи: 101

05-01-2006 дата публикации

Electronic systems having doped aluminum oxide dielectrics

Номер: US20060001079A1

Автор: Kie Ahn, Leonard Forbes

Принадлежит: Micron Technology Inc

Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques to facilitate formation of a high-purity aluminum oxide layer. A dopant material is embedded in the pores of the porous aluminum oxide layer and subsequently converted to a dielectric form. The degree of porosity of the porous aluminum oxide layer may be controlled during formation to facilitate control of the level of doping of the doped aluminum oxide layer. Such doped aluminum oxide layers are useful as gate dielectric layers, intergate dielectric layers and capacitor dielectric layers in various integrated circuit devices.

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Номер записи: 102

06-08-2002 дата публикации

Efficient CMOS DC-DC converters based on switched capacitor power supplies with inductive current limiters

Номер: US6429632B1

Автор: Kie Y. Ahn, Leonard Forbes

Принадлежит: Micron Technology Inc

A novel class of DC to DC power converters and a method of conversion is provided using high-frequency switched capacitors where the switches are implemented by CMOS transistors or diodes on an integrated-circuit chip and using inductors to limit charging current. High efficiency is achieved using inductors to reduce energy losses in circuit capacitors by high frequency switching when inductor current is zero and capacitor voltage is maximized. The high-frequency (100 MHz or greater) operation of the converter circuit permits the use of inductors with a low inductance value on the order of 100 nH (100×10 −9 Henrys) capable of fabrication directly on an integrated-circuit (IC) chip. The use of CMOS integrated components allows the entire converter to be formed on a single IC chip, saving significant space within the portable system. Output voltage and current is high enough to permit EEPROM programming. In addition, fluctuations in the output voltage (ripple voltage) are substantially eliminated when several of the converter circuits are used in parallel.

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Номер записи: 103

18-03-2003 дата публикации

CMOS voltage controlled phase shift oscillator

Номер: US6535071B2

Автор: Leonard Forbes

Принадлежит: Micron Technology Inc

Structures and methods for CMOS voltage controlled phase shift oscillators are provided. The CMOS voltage controlled phase shift oscillators, or phase shift circuit, includes any odd number of stages coupled in series. Each stage includes a CMOS amplifier. A phase shift network is coupled to the CMOS amplifier. The CMOS amplifier provides a gain and allows a small phase shift in each stage to eventually provide a signal which is 180 degrees out of phase with the input signal. In the CMOS amplifier, the PMOS transistor is a diode connected PMOS transistor which acts as a low valued load resistance. In the phase shift network, an NMOS transistor is used as a voltage variable resistor for providing a resistance value in the circuit.

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Номер записи: 104

18-05-2004 дата публикации

Method and apparatus for providing clock signals at different locations with minimal clock skew

Номер: US6737926B2

Автор: Leonard Forbes

Принадлежит: Micron Technology Inc

A tapped phase shift ring oscillator may be used to provide multiple clock signals having variable phase delays. Phase delays may be selected to compensate for clock skews at different locations on high speed chips, or to provide clock signals having specific, desirable phase relationships, such as quadrature signals. The phase shift ring oscillator includes an odd number of amplifier stages. Each amplifier stage includes a phase shift network and an amplifier network. CMOS components used in the phase shift and amplifier networks provide voltage controlled variable phase shift and low gain, wide bandwidth, and low output impedance.

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Номер записи: 105

14-12-2004 дата публикации

Fully depleted silicon-on-insulator CMOS logic

Номер: US6830963B1

Автор: Leonard Forbes

Принадлежит: Micron Technology Inc

A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without the adverse floating body effects.

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Номер записи: 106

14-04-2005 дата публикации

Fully depleted silicon-on-insulator CMOS logic

Номер: US20050077564A1

Автор: Leonard Forbes

Принадлежит: Micron Technology Inc

A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without the adverse floating body effects.

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Номер записи: 107

23-07-2019 дата публикации

Photosensitive imaging devices and associated methods

Номер: US10361232B2

Автор: Chintamani Palsule, Homayoon Haddad, Jeffrey McKee, Jutao Jiang, Leonard Forbes

Принадлежит: SiOnyx LLC

Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and a passivation region positioned between the textured region and the at least one junction. The passivation region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction.

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Номер записи: 108

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