System-in-a-package based flash memory card

A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.

Identification circuit and method for generating an identification bit using physical unclonable functions

An embodiment of the present invention is an identification circuit installed on an integrated circuit for generating an identification bit, comprising a first circuit to generate a first output signal that is based on random parametric variations in said first circuit, a second circuit to generate a second output signal that is based on random parametric variations in said second circuit, a third circuit capable to be operated in an amplification mode and in a latch mode, wherein in said amplification mode the difference between the first output signal and the second output signal is amplified to an amplified value and, wherein in said latch mode said amplified value is converted into a digital signal.

Electrically measurable on-chip ic serial identifier and methods for producing the same

An apparatus comprising an integrated circuit, an interconnect layer within said integrated circuit, and one or more connections. The integrated circuit may be configured to provide an electrically measurable interconnect pattern by enabling one or more of a plurality of components. The one or more connections may each configured to enable a respective one of the components. The connections may be programmable while the apparatus is part of a wafer. The interconnect pattern may be configured to identify the apparatus after the apparatus has been manufactured.

Electrical Contact Alignment Posts

An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.

Integrated circuit and display device including the same

An integrated circuit that includes a substrate, a semiconductor layer arranged on the substrate and an insulating layer arranged on an upper portion of the semiconductor layer and including a bump provided on an upper surface thereof, wherein the semiconductor layer includes a main semiconductor area and an including an internal alignment mark including a p-type semiconductor that is overlapped by a metallic external alignment mark arranged on the upper surface of the insulating layer. The p-type semiconductor internal alignment mark can be viewed by an infrared camera during a mounting process of the integrated circuit.

Semiconductor device and display device having alignment mark

An exemplary display device includes a transparent substrate and a semiconductor device bonded to the transparent substrate. The transparent substrate includes a first alignment mark. The semiconductor device includes a substrate and a second alignment mark positioned on the substrate. The second alignment mark includes a first pattern structure positioned on the substrate and a second pattern structure positioned on the first pattern structure. The first pattern structure includes a plurality of first non-transparent marks. The second pattern structure includes a second pattern surrounded by the first non-transparent marks. The second pattern is an alignable shape that corresponds to a shape of the first alignment mark on the transparent substrate.

Wafer-level packaging for enhanced performance

The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.

Transition device for flexible device and production method therefor, and method for fabricating flexible device

A transition device for a flexible device and a production method therefor, and a method for fabricating a flexible device are provided. The transition device includes a functional component and a transition base. The functional component has a first surface for mounting with a base and a second surface opposite to the first surface, and the transition base is bonded to the second surface of the functional component by an adhesive layer.

Electronic component device and manufacturing method thereof

An electronic component device includes a first electronic component, a second electronic component disposed on and connected to the first electronic component, a first underfill resin filled between the first electronic component and the second electronic component, the first underfill resin having a base part arranged around the second electronic component and an alignment mark formed on an upper surface of the base part, a third electronic component disposed on and connected to the second electronic component, and a second underfill resin filled between the second electronic component and the third electronic component.

Semiconductor package

A semiconductor package includes a first semiconductor chip including a first surface and a second surface which face each other, an alignment pattern formed on the first surface, a first redistribution layer arranged on the first surface of the first semiconductor chip, a second redistribution layer arranged on the second surface of the first semiconductor chip, and electrically connected with the semiconductor chip, and a first dielectric layer including the alignment pattern between the first redistribution layer and the semiconductor chip, the alignment pattern overlapping the first surface of the first semiconductor chip.

Mobile computing device reconfiguration is response to environmental factors including downloading hardware and software associated with multiple users of the mobile device

A reconfigurable high speed memory chip module includes a type of memory cell array group, a first transmission bus, and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs). The first transmission bus coupled to the type memory cell array group has a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing, a first programmable bus width, and a combination thereof. The logic unit is coupled to the first transmission bus for accessing the type memory cell array group through the first transmission bus.

Optical sensor and manufacturing method thereof

An optical sensor includes a sensing layer, a first shading filter, a second shading filter, and an alignment mark. The sensing layer includes an active area, a shading area, and a peripheral area. The sensing layer includes sensing units located in the active area. The first shading filter is disposed on the shading area. The second shading filter is disposed on the first shading filter. The alignment mark is disposed on the peripheral area. When a light beam is emitted to the shading area, the second shading filter is configured to block a first component of the light beam, and the first shading filter is configured to block a second component of the light beam.

Semiconductor Chip Comprising a Multiplicity of External Contacts, Chip Arrangement and Method for Checking an Alignment of a Position of a Semiconductor Chip

A semiconductor chip includes a mounting surface having a plurality of first conductive contacts and a second conductive contact, wherein each of the first contacts in the plurality is arranged in a regularly spaced apart array such that centroids of immediately adjacent ones of the first contacts are separated from one another in a first direction by a first distance, each of the first contacts in the plurality have an identical first lateral extent, and the second conductive contact is arranged between two of the first conductive contacts in the first direction such that first and second distances between the at least one second conductive contact and the two of the first conductive contacts are each less than the first distance. 1. A semiconductor chip , comprising:a mounting surface comprising a plurality of first conductive contacts and at least one second conductive contact,wherein each of the first conductive contacts in the plurality is arranged in a regularly spaced apart array such that centroids of immediately adjacent ones of the first conductive contacts in the plurality are separated from one another in a first direction by a first distance,wherein each of the first conductive contacts in the plurality have an identical first lateral extent, andwherein the at least one second conductive contact is arranged between two of the first conductive contacts in the first direction such that first and second distances between the at least one second conductive contact and the two of the first conductive contacts are each less than the first distance.2. The semiconductor chip of claim 1 , wherein the at least one second conductive contact is configured to check an alignment of a position of the semiconductor chip in relation to a second semiconductor chip to be mounted on the mounting surface.3. The semiconductor chip of claim 1 , wherein the at least one second conductive contact has a second lateral extent that is less than the first lateral extent.4. The ...

ALIGNMENT OF MULTIPLE IMAGE DICE IN PACKAGE

An image sensor assembly and a method for assembling. The assembly includes: a ceramic package; at least one wall raised from the ceramic package, one of the walls for dividing a first surface region and a second surface region of the ceramic package; a frame supported by the ceramic package; a first set of fiducial markers and a second set of fiducial markers visible on the frame; a first die for placement onto the first surface region, the first die including an image sensor and respective fiducial markers for alignment with the first set of fiducial markers; a second die for placement onto the second surface region, the second die including an image sensor and respective fiducial markers for alignment with the second set of fiducial markers; and at least one optical filter each associated with one of the dice and supported by at least one of the walls. 1. An assembly , comprising:a ceramic package;at least one wall raised from the ceramic package, one of the walls for dividing a first surface region and a second surface region of the ceramic package;a frame supported by the ceramic package;a first set of fiducial markers and a second set of fiducial markers visible on the frame;a first die for placement onto the first surface region, the first die including a first image sensor and respective fiducial markers for alignment with the first set of fiducial markers;a second die for placement onto the second surface region, the second die including a second image sensor and respective fiducial markers for alignment with the second set of fiducial markers; andat least one optical filter each associated with one of the dice and supported by at least one of the walls.2. The assembly as claimed in claim 1 , wherein the first set of fiducial markers on the frame is located adjacent to the first surface region claim 1 , and wherein the second set of fiducial markers on the frame is located adjacent to the second surface region.3. The assembly as claimed in claim 1 , wherein ...

RECLAIMABLE SEMICONDUCTOR DEVICE PACKAGE AND ASSOCIATED SYSTEMS AND METHODS

Several embodiments of reclaimable semiconductor device packages and assemblies are disclosed herein. A semiconductor device assembly () includes a package () having a housing () and a package contact () arranged to receive a signal indicative of a reclamation state. A plurality of modules of semiconductor dies () are located within the housing and electrically coupled to the package contact (). The dies () of the first and second modules dies are configured to store a module configuration state. The first and second modules () are enabled for operation based, at least in part, on the reclamation state and the module configuration state. 111-. (canceled)12. A method of reclaiming a semiconductor device package having a plurality of semiconductor dies arranged in at least a first module of semiconductor dies and a second module of semiconductor dies , the method comprising:determining whether a first semiconductor die in the first module is operable; andstoring a configuration state at a second semiconductor die in the semiconductor device package based on whether the first semiconductor is operable.13. The method of claim 12 , further comprising:determining whether first module is operable and whether the second module is operable; andif both the first and second modules are operable, coupling a package contact to a first contact on a support substrate,else, coupling the package contact to a second contact on a support substrate, wherein coupling the package contact to the second contact enables the first module or the second module based on the configuration state.14. The method of claim 12 , wherein the second semiconductor die is located in the first module.15. The method of claim 12 , wherein the second semiconductor die is located in the second module.16. The method of claim 12 , wherein determining whether the first semiconductor die is inoperable comprises determining whether the first semiconductor die is operating below a yield threshold.17. The method of ...

Semiconductor device having first and second electrode layers electrically disconnected from each other by a slit

A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate.

Display device and bonding accuracy detection method

A display device and a detection method are provided. The display device includes a display panel including an effective area and a peripheral area located around the effective area; and a cover plate attached to the display panel, the cover plate including a visible region, and the boundary of the visible region of the cover plate is located outside the boundary of the effective region of the display panel in a direction parallel to the display panel; at least one pair of light sensitive luminescent marks disposed on the display panel and located near mutually opposite edges of the display panel. Each of the at least one pair of light sensitive luminescent marks is disposed inside or outside an effective area of the display panel in a direction parallel to the display panel.

VISUAL IDENTIFICATION OF SEMICONDUCTOR DIES

Systems and methods for visual identification of semiconductor dies are described. In some embodiments, a method may include: receiving a semiconductor wafer having a plurality of dies and printing a unique visual identification mark on each of the plurality of dies. In other embodiments, a method may include receiving an electronic device comprising a die and a package surrounding at least a portion of the die and reading, from the electronic device, a unique visual identification mark that encodes a Cartesian coordinate of the die relative to a reference point on a semiconductor wafer. 1. An electronic device , comprising:a die; anda package surrounding the die, wherein the electronic device includes a unique visual identification mark, wherein a character in the unique visual identification mark includes at least one line that connects two adjacent sides of a bond pad of the die, wherein the unique visual identification mark encodes a Cartesian coordinate of the die relative to a reference point on a semiconductor wafer.2. The electronic device of claim 1 , wherein the unique visual identification mark further encodes a wafer identification of the semiconductor wafer.3. The electronic device of claim 1 , wherein the unique visual identification mark further encodes a lot identification of the semiconductor wafer.4. The electronic device of claim 1 , wherein the unique visual identification mark includes laser scribed or tip scrubbed bond pad or terminal.5. The electronic device of claim 4 , wherein one or more corners of the bond pad or terminal are marked claim 4 , scratched claim 4 , or cut in a manner corresponding to a respective numeral.6. The electronic device of claim 1 , wherein the character includes at least two lines that together connect three adjacent sides of the bond pad of the die.7. The electronic device of claim 1 , wherein the character includes at least three lines that together connect four adjacent sides of the bond pad of the die.8. The ...

SEMICONDUCTOR APPARATUS AND MEMORY SYSTEM

A semiconductor apparatus includes a chip ID generation unit, a chip ID transmission unit and a chip stack information generation unit. The chip ID generation unit is configured to generate a chip ID signal. The chip ID transmission unit is configured to output the chip ID signal to a common line on the basis of whether another chip is electrically coupled therewith. The chip stack information generation unit is configured to be electrically coupled with the common line in response to the chip ID signal and generate a stack information signal. 1. A semiconductor apparatus comprising:a plurality of chips coupled to one another through a common line,wherein each chip includes a chip identification (ID) transmission unit configured to output, respectively, a chip ID signal to the common line on the basis of whether an output terminal for a respective chip ID transmission unit is electrically coupled with another stacked chip at a next stage.2. The semiconductor apparatus according to claim 1 , wherein claim 1 , if a chip from the plurality of chips corresponds to a last stage claim 1 , then a chip ID signal for the chip is outputted to the common line.3. The semiconductor apparatus according to claim 1 , wherein claim 1 , if a chip from the plurality of chips corresponds to any stage other than a last stage claim 1 , then a chip ID signal for the chip is blocked from being outputted to the common line.4. The semiconductor apparatus according to claim 1 , wherein claim 1 , if the output terminal for the respective chip ID transmission unit is electrically coupled with the another stacked chip at the next stage claim 1 , then the chip ID signal for the corresponding chip is blocked from being outputted to the common line.5. The semiconductor apparatus according to claim 1 , wherein claim 1 , if the output terminal for the respective chip ID transmission unit is not electrically coupled with the another stacked chip at the next stage claim 1 , then the chip ID signal for ...

Integrated wire bonder and 3d measurement system with defect rejection

An apparatus comprises a wire bonder system including a wire bonding device, a measuring device and a rejection device. The wire bonding device is configured to attach wire bond type electrical interconnect to an electronic assembly. A wire bond is formed between a first semiconductor device and a second electronic device to form at least a portion of the electronic assembly. The measuring device is configured to perform a three dimensional measurement associated with a wire bond, and the rejection device is configured to identify an electronic assembly for rejection according to the three dimensional wire bond measurement.

Screening of electronic components for detection of counterfeit articles using automated inspection system

A method includes selecting one or more analysis algorithms to be used to verify an authenticity of an electronic component. Each analysis algorithm identifies a type of data to be analyzed and/or a manner in which the data is to be collected. Each analysis algorithm also defines how the data is to be analyzed to verify the authenticity of the electronic component. The method also includes obtaining data associated with the electronic component. The method further includes analyzing the data associated with the electronic component using the one or more selected analysis algorithms to determine whether the electronic component is authentic. In addition, the method includes generating an output based on the analysis. One or more characteristics of the electronic component could be compared against one or more characteristics of at least one reference component, or variations in one or more characteristics of multiple electronic components could be identified.

Stacked device and method of manufacturing the same

A stacked device encompasses a lower chip including a plurality of wiring lands and a plurality of wall-block patterns, each of the wall-block patterns is allocated at a position except locations where the wiring lands are disposed, each of the wall-block patterns has a inclined plane, a height of each of the wall-block patterns measured from a reference plane of the array of the wiring lands is higher than the wiring lands, and an upper chip including a plurality of wiring bumps assigned correspondingly to the positions of the wiring lands, respectively, and a plurality of cone bumps assigned correspondingly to the positions of the wall-block patterns, respectively.

SEMICONDUCTOR DEVICE STRUCTURES FOR BURN-IN TESTING AND METHODS THEREOF

A semiconductor device structure is provided. The semiconductor device structure includes a substrate, an electrical connection structure extending upwardly from an upper surface of the substrate by a first height, and a contact pad electrically disposed on the upper surface of the substrate. The contact pad has a solder-wettable surface with an area configured to support a solder ball having a second height at least twice the first height. The semiconductor device structure further includes a fuse element with a first end electrically coupled to the electrical connection structure and a second end electrically coupled to the contact pad. 1. A semiconductor device structure , comprising:a substrate;an electrical connection structure extending upwardly from an upper surface of the substrate by a first height;a contact pad electrically disposed on the upper surface of the substrate, the contact pad having a solder-wettable surface with an area configured to support a solder ball having a second height greater than the first height; anda fuse element with a first end electrically coupled to the electrical connection structure and a second end electrically coupled to the contact pad.2. The semiconductor device structure of claim 1 , wherein the first height is between about 5 and 30 μm.3. The semiconductor device structure of claim 1 , wherein the second height is greater than about 30 μm.4. The semiconductor device structure of claim 1 , wherein the electrical connection structure is a copper pillar having a diameter of between about 5 and 30 μm.5. The semiconductor device structure of claim 1 , wherein the area of the contact pad is a circle with a diameter of between about 10 and 50 μm.6. The semiconductor device structure of claim 1 , wherein the fuse element is laser-blowable fuse.7. The semiconductor device structure of claim 6 , wherein the laser-blowable fuse is proximate to the electrical connection structure.8. The semiconductor device structure of claim 1 , ...

Semiconductor package system

A semiconductor package system includes a substrate, a first and a second semiconductor package, a first thermal conductive layer, a first passive device, and a heat radiation structure. The first and second semiconductor package and first passive device may be mounted on a top surface of the substrate. The first semiconductor package may include a first semiconductor chip that includes a plurality of logic circuits. The first thermal conductive layer may be on the first semiconductor package. The heat radiation structure may be on the first thermal conductive layer, the second semiconductor package, and the first passive device. The heat radiation structure may include a first bottom surface physically contacting the first thermal conductive layer, and a second bottom surface at a higher level than that of the first bottom surface. The second bottom surface may be on the second semiconductor package and/or the first passive device.

ALIGNMENT METHOD, METHOD FOR CONNECTING ELECTRONIC COMPONENT, METHOD FOR MANUFACTURING CONNECTION BODY, CONNECTION BODY AND ANISOTROPIC CONDUCTIVE FILM

An alignment mark at a position that overlaps an area in which an anisotropic conductive film is pasted, and to accurately perform alignment using an image captured by a camera. An alignment method in which an electronic component is mounted on the obverse surface of a transparent substrate with a conductive adhesive agent interposed therebetween, a substrate-side alignment mark and a component-side alignment mark are adjusted from the captured image, and the position at which the electronic component is mounted on the transparent substrate is aligned, wherein in the conductive adhesive agent, conductive particles are in a regular arrangement as viewed from a planar perspective, and in the captured image, the outside edges of the alignment marks exposed between the conductive particles are intermittently visible as line segments (S) along the imaginary line segments of the outside edges of the alignment mark. 1. An alignment method comprising:mounting an electronic component having a component-side alignment mark onto a surface of a transparent substrate having a substrate-side alignment mark via an adhesive agent containing conductive particles interposed therebetween;imaging the substrate-side alignment mark and the electronic component-side alignment mark from the back surface side of the transparent substrate; andadjusting a position of the substrate-side alignment mark and the component-side alignment mark by using a captured image obtained by imaging to adjust a mounting position of the electronic component with respect to the transparent substrate;wherein the adhesive agent has the conductive particles arranged regularly as viewed from a planar perspective; andwherein in the captured image, outside edges of the substrate-side alignment mark or the component-side alignment mark exposed between the conductive particles are intermittently visible as line segments along imaginary line segments of the outside edges of the substrate-side alignment mark or the ...

Ncf for pressure mounting, cured product thereof, and semiconductor device including same

There is provided a pre-applied semiconductor sealing film for curing under pressure atmosphere as a non conductive film (NCF) suitable for pressure mounting. This NCF includes (A) a solid epoxy resin, (B) an aromatic amine which is liquid at room temperature and contains at least one of structures represented by formulae 1 and 2 below, (C) a silica filler, and (D) a polymer resin having a mass average molecular weight (Mw) of 6000 to 100000. The epoxy resin of the component (A) has an epoxy equivalent weight of 220 to 340. The component (B) is included in an amount of 6 to 27 parts by mass relative to 100 parts by mass of the component (A). The component (C) is included in an amount of 20 to 65 parts by mass relative to 100 parts by mass in total of the components. A content ratio ((A):(D)) between the component (A) and the component (D) is 99:1 to 65:35. This NCF further has a melt viscosity at 120° C. of 100 Pa·s or less, and has a melt viscosity at 120° C., after heated at 260° C. or more for 5 to 90 seconds, of 200 Pa·s or less.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Provided are a semiconductor device in which abrasive grain marks are formed in a surface of a semiconductor substrate, a dopant diffusion region has a portion extending in a direction which forms an angle included in a range of −5° to +5° with a direction in which the abrasive grain marks extend, and the dopant diffusion region is formed by diffusing a dopant from a doping paste placed on one surface of the semiconductor substrate; and a method for manufacturing the semiconductor device. 1. A semiconductor device , comprising:a semiconductor substrate; anda dopant diffusion region provided in one surface of said semiconductor substrate, whereinabrasive grain marks are formed in said surface of said semiconductor substrate,said dopant diffusion region has a portion extending in a direction which forms an angle included in a range of −5° to +5° with a direction in which said abrasive grain marks extend, andsaid dopant diffusion region is formed by diffusing a dopant from a doping paste placed on the one surface of said semiconductor substrate.2. The semiconductor device according to claim 1 , whereinsaid dopant diffusion region has at least one of an n-type dopant diffusion region and a p-type dopant diffusion region, and an electrode for n type provided on said n-type dopant diffusion region; and', 'an electrode for p type provided on said p-type dopant diffusion region., 'the semiconductor device further comprises3. A method for manufacturing a semiconductor device claim 1 , comprising the steps of:forming abrasive grain marks extending in one direction in a surface of a semiconductor substrate;placing a doping paste having a portion extending in a direction which forms an angle included in a range of −5° to +5° with a direction in which said abrasive grain marks extend, on a portion of said surface of said semiconductor substrate; andforming a dopant diffusion region from a dopant in said doping paste on said semiconductor substrate.4. The method for manufacturing ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a monocrystalline substrate of a material which does not have a liquid phase at atmospheric pressure, and an identification mark disposed on or in the substrate comprising an amorphous region of the material or a region of the material deviated from stoichiometry. 1. A semiconductor device comprising:a monocrystalline substrate comprising a material which does not have a liquid phase at atmospheric pressure; andan identification mark comprising at least one of an amorphous region of the material of the semiconductor substrate and a region of the material of the semiconductor substrate deviated from stoichiometry.2. The device according to claim 1 , wherein the material of the semiconductor substrate comprises SiC.3. The device according to claim 1 , wherein the maximum height (Rz) of a surface of the identification mark is 100 nm or less.4. The device according to claim 1 , whereinthe substrate further includes an element region,the substrate has a front surface, a rear surface, and side surfaces, andthe identification mark is disposed in a region other than the element region on the front surface.5. The device according to claim 1 , whereinthe substrate has a front surface, a rear surface, and side surfaces, andthe identification mark is disposed on the side surface.6. The device according to claim 1 , whereinthe substrate has a front surface, a rear surface, and side surfaces, andthe identification mark is disposed within the substrate inwardly of the front surface or the side surface of the substrate.7. The device according to claim 1 , wherein the identification mark is detectable by x-ray inspection.8. A method for manufacturing a semiconductor device comprising:providing a monocrystalline substrate of a material which does not have a liquid phase at atmospheric pressure: andforming an identification mark by modifying the material of the substrate by irradiating the monocrystalline substrate with laser light that has energy ...

METHOD OF MANUFACTURING FLIP-CHIP TYPE SEMICONDUCTOR DEVICE

An object of the present invention is to provide a method of manufacturing a flip-chip type semiconductor device with a simplified process, in which various types of information are supplied in a visually recognizable manner. The present invention relates to a method of manufacturing a flip-chip type semiconductor device comprising: a step A of laminating on a semiconductor wafer a film for the backside of a flip-chip type semiconductor, in which the film is to be formed on the backside of a semiconductor element that is flip-chip connected onto an adherend; a step B of dicing the semiconductor wafer; and a step C of laser marking the film for the backside of a flip-chip type semiconductor, wherein the film for the backside of a flip-chip type semiconductor in the step C is uncured. 1. A method of manufacturing a flip-chip type semiconductor device comprising:a step A of laminating on a semiconductor wafer a film for the backside of a flip-chip type semiconductor, in which the film is to be formed on the backside of a semiconductor element that is flip-chip connected onto an adherend;a step B of dicing the semiconductor wafer; anda step C of laser marking the film for the backside of a flip-chip type semiconductor, whereinthe film for the backside of a flip-chip type semiconductor in the step C is uncured.2. The method of manufacturing a flip-chip type semiconductor device according to claim 1 , wherein the film for the backside of a semiconductor is formed from a resin composition containing an epoxy resin and a phenol resin claim 1 , and the total amount of the epoxy resin and the phenol resin is 25 parts by weight or less to 100 parts by weight of the resin composition.3. (canceled)4. A flip-chip type semiconductor device obtained with the manufacturing method according to . The present invention relates to a method of manufacturing a flip-chip type semiconductor device and a flip-chip type semiconductor device obtained with the manufacturing method.In recent ...

Magnetic alignment for flip chip microelectronic devices

Incorporating at least one magnetic alignment structure on a microelectronic device and incorporating at least one alignment coil within a microelectronic substrate, wherein the alignment coil may be powered to form a magnetic field to attract the magnetic alignment structure, thereby aligning the microelectronic device to the microelectronic substrate. After alignment, the microelectronic device may be electrically attached to the substrate. Embodiments may include additionally incorporating an alignment detection coil within the microelectronic substrate, wherein the alignment detection coil may be powered to form a magnetic field to detect variations in the magnetic field generated by the alignment coil in order verify the alignment of the microelectronic device to the microelectronic substrate.

Integrated Circuit Substrate and Method for Manufacturing the Same

An integrated circuit substrate and a method for manufacturing the same are disclosed. In an embodiment a method includes providing a wafer having a plurality of active areas, each active area being provided in a separate die area and for each active area, providing a code pattern outside the active area, the code pattern being associated with the die area. 1. A method for use in manufacturing semiconductor chips , the method comprising:providing a wafer having a plurality of active areas, each active area being provided in a separate die area; andfor each active area, providing a code pattern outside the active area, the code pattern being associated with the die area.2. The method of claim 1 , wherein the method comprises removing material from the wafer so as to form one or more scribe line trenches outside the active areas claim 1 , wherein the code pattern is provided on a side wall of the one or more scribe line trenches.3. The method of claim 2 , wherein removing the material is performed essentially by anisotropic etching.4. The method of claim 3 , wherein the anisotropic etching is performed in a plurality of cycles claim 3 , each cycle including an isotropic plasma etching phase followed by a passivation phase claim 3 , the code pattern being provided by varying the time duration of ones of the isotropic plasma etching phases.5. The method of claim 2 , wherein removing the material comprises varying a rate of material removal per unit time to form the code pattern.6. The method of claim 5 , further comprising dicing the wafer wherein material is removed to deepen the scribe line trenches until the wafer is divided up in separate die substrates that each include one of the die areas claim 5 , wherein pattern scallops formed in a die substrate side wall that encases the active area are less wide than dicing scallops formed in a die side wall that encases the die substrate below the active area.7. The method of claim 1 , wherein the code pattern represents ...

Package comprising identifier on and/or in carrier

A package comprising a carrier, an electronic component mounted on the carrier, and an identifier indicative of an origin of the package and being formed on and/or in the carrier is disclosed.

Method of forming a plurality of electronic component packages and packages formed thereby

A method of forming a plurality of electronic component packages includes attaching electronic components to a carrier, wherein high aspect ratio spaces exist between the electronic components. A dielectric sheet is laminated around the electronic components thus filling the spaces and forming a package body. The spaces are completely and reliably filled by the dielectric sheet and thus the package body has an absence of voids. Further, an upper surface of the package body is planar, i.e., has an absence of ripples or other non-uniformities. Further, lamination of the dielectric sheet is performed with a low cost lamination system.

Flexible display panel, method for fabricating the same, and apparatus for forming the same

The present disclosure provides a method for bonding an integrated circuit (IC) chip onto a flexible display body. The method includes providing a substrate having a flexible display body thereon, and aligning a first stiffening component with the flexible display body having an IC bonding region. The method further includes attaching the first stiffening component onto a front surface of the flexible display body, and separating the substrate from the first stiffening component and the flexible display body to expose a back surface of the flexible display body; and bonding an IC chip onto the IC bonding region.

Semiconductor chip and multi-chip package using thereof

The present disclosure provides a semiconductor chip having a non-through plug contour (buried alignment mark) for stacking aligmnent and a multi-chip semiconductor device employing thereof, and to a method for manufacturing same. In some embodiments, the semiconductor chip includes a semiconductor substrate having a first side and a second side, a conductive through plug extending through the semiconductor substrate from the first side to the second side, and a non-through plug extending from the first side to an internal plane of the semiconductor substrate without extending through the second side.

3D semiconductor devices and structures with at least two single-crystal layers

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second transistors each include at least two side-gates, and where through the first metal layers power is provided to at least one of the second transistors.

Sequential unique marking

The present invention comprises a method of sequential unique marking comprising providing a multi-die handling device with a plurality of devices therein, reading an ID code on the multi-die handling device, retrieving a tray map file corresponding to the ID code, determining a tray matrix of the multi-die handling device, retrieving data from the tray map file, the data comprising unique characters correlating to each device of the plurality of devices and marking each device with the data.

Sequential unique marking

The present invention comprises a method of sequential unique marking comprising providing a multi-die handling device with a plurality of devices therein, reading an ID code on the multi-die handling device, retrieving a tray map file corresponding to the ID code, determining a tray matrix of the multi-die handling device, retrieving data from the tray map file, the data comprising unique characters correlating to each device of the plurality of devices and marking each device with the data

Circuit board and method for manufacturing the same

At first, a sprocket hole (12) and a device hole (14) are made in a flexible tape-like transparent or translucent insulating base (11). A conductor is then laminated on the surface of the insulating base to form a conductive layer. Subsequently, a desired part of the conductive layer is etched to form a wiring pattern (13) and an alignment mark (15). Thereafter, a solder resist layer (16) is formed on portions except the terminal part of the wiring pattern and the alignment mark. Finally, a layer (17) having a transparent or translucent surface is formed on the insulating base around the alignment mark so that the light transmits the front and rear surfaces of the circuit board and the position of the alignment mark can be confirmed.

电路基板及电路基板的制造方法

一种电路基板及电路基板的制造方法，首先，在具有柔性、带状、透明或者半透明的绝缘基底(11)上形成链轮孔(12)和器件孔(14)。接着，在绝缘基底的表面上层叠导电体，形成导电层。接着，蚀刻该导电层的所期望的部位，形成布线图形(13)和对准标记(15)。接着，在布线图形的端子部分及对准标记以外的部位形成阻焊层(16)。最后，在对准标记的周围，在绝缘基底上，使光透过电路基板的表面和背面，以可确认对准标记的位置的方式形成其表面透明或半透明的透明层(17)，制成电路基板。

Method for manufacturing printed wiring board

A printed wiring board comprises a wiring substrate provided with at least one conductor circuit, a solder resist layer provided on the surface of the wiring substrate, at least one conductor pad formed from a part of the conductor circuit exposed from an opening provided in the solder resist layer, and at least one solder bump for mounting electronic parts on the conductor pad. In the printed wiring board, since the at least one conductor pad is aligned at a pitch of 200 µm or less, and a ratio (W/D) of a diameter W of the solder bump to an opening diameter D of the opening formed in the solder resist layer is within a range of 1.05 to 1.7, connection reliability and insulation reliability can be easily improved.

Multilayer printed wiring board and method for producing multilayer printed wiring board

A multilayer printed circuit board has an IC chip 20 included in a core substrate 30 in advance and a transition layer 38 provided on a pad 24 of the IC chip 20 . Due to this, it is possible to electrically connect the IC chip to the multilayer printed circuit board without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on the die pad 24 , it is possible to prevent resin residues on the pad 24 and to improve connection characteristics between the pad 24 and a via hole 60 and reliability.

Method for identifying defective elements in array molding of semiconductor packaging

The present invention is a method for identifying defective elements in array molding of semiconductor packaging for mini BGA packaging substrate which comprises a circuit zone and a periphery zone. The method of the present invention is first to form a plurality of package sites disposed in array in the circuit zone, and to form a plurality of marks in a periphery zone. When a defective element is found in the package sites, a symbol is put at the mark or an electronic file is employed to record the location of the defective element, thereby, the defective element in the package sites of the molding array in the circuit zone can be identified.

SEMICONDUCTOR DEVICES HAVING AN e-FUSE STRUCTURE AND METHODS OF FABRICATING THE SAME

이-퓨즈 구조체를 포함하는 반도체 소자 및 그 제조 방법을 제공한다. 이 소자는 이-퓨즈 게이트, 이-퓨즈 게이트 및 활성부 사이에 개재된 플로팅 패턴, 플로팅 패턴 및 이-퓨즈 게이트 사이에 개재된 블로킹 유전 패턴, 및 플로팅 패턴과 활성부 사이에 개재된 이-퓨즈 유전막을 포함한다. 플로팅 패턴은 이-퓨즈 게이트와 성부 사이에 개재된 제1 부분, 및 제1 부분의 양 가장자리로부터 이-퓨즈 게이트의 양 측벽들을 따라 위로 연장된 한쌍의 제2 부분들을 포함한다. A semiconductor device including an e-fuse structure and a method of manufacturing the same are provided. The device includes a floating pattern interposed between the e-fuse gate, the e-fuse gate and the active portion, a blocking dielectric pattern interposed between the floating pattern and the e-fuse gate, and an e-fuse interposed between the floating pattern and the active portion. Dielectric film. The floating pattern includes a first portion interposed between the e-fuse gate and the body portion and a pair of second portions extending upwardly along opposite side walls of the e-fuse gate from both edges of the first portion.

Printed circuit board strip for semiconductor package and defective printed circuit board unit display method of the board strip

Marking machine

Process for manufacturing semiconductor wafer, process for manufacturing semiconductor chip, and ic card

기판(1a)에 복수의 회로소자(41)을 일체로 만들어넣는 공정과, 회로소자(41)과 도통하는 전극패드(11b)위에 전극범프(11)을 형성하는 공정과, 기판(1a)의 소정위치에 스크라이브 라인 또는 스크라이브 라인 마크(21a)를 형성하는 공정과, 각 전극범프(11) 및 스크라이브 라인 또는 스크라이브 라인 마크(21a)를 덮도록하여 이방성도전막(30)을 점착하는 공정을 포함한다. A process of integrally forming a plurality of circuit elements 41 on the substrate 1a, a process of forming the electrode bumps 11 on the electrode pads 11b conducting with the circuit elements 41, and the process of the substrate 1a. Forming a scribe line or scribe line mark 21a at a predetermined position; and attaching the anisotropic conductive film 30 to cover each electrode bump 11 and the scribe line or scribe line mark 21a. do. 가 전극범프(11)을 형성하는 공정과, 스크라이브 라인 또는 스크라이브 라인 마크(21a)를 형성하는 공정과는, 동시에 행하여진다. The process of forming the electrode bump 11 and the process of forming the scribe line or the scribe line mark 21a are performed simultaneously. 전극범프(11) 및 스크라이브 라인 또는 스크라이브 라인 마크(21a)은, 바람직하게는 금으로 형성된다. The electrode bump 11 and the scribe line or the scribe line mark 21a are preferably formed of gold. 이와같은 제조방법으로, 복수의 회로소자가 형성된 반도체웨이퍼에, 이방성도전막을 점착한 경우에 있어서도, 소망하는대로 회로소자를 분획할 수가 있다. In such a manufacturing method, even when the anisotropic conductive film is attached to a semiconductor wafer on which a plurality of circuit elements are formed, the circuit elements can be fractionated as desired.

Ｉｃパツケ−ジの捺印方法

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Circuit board and method for manufacturing the same

먼저, 가요성을 갖고, 테이프 형상이고 투명 또는 반투명의 절연 베이스(11)에 스프로킷 홀(12) 및 디바이스 홀(14)을 형성한다. 다음에 절연 베이스의 표면에 도전체를 라미네이션하여 도전층을 형성한다. 이어서, 그 도전층의 원하는 개소를 에칭하여 배선 패턴(13) 및 얼라인먼트 마크(15)를 형성한다. 이어서, 배선 패턴의 단자부분 및 얼라인먼트 마크 이외의 장소에 솔더레지스트층(16)을 형성한다. 최후에, 얼라인먼트 마크의 주위에서 절연 베이스상에, 회로기판의 표리에 광을 투과하여, 얼라인먼트 마크의 위치를 확인할 수 있도록, 그 표면이 투명 또는 반투명의 투명층(17)을 형성하여, 회로기판을 얻는다. 절연 베이스, 스프로킷 홀, 디바이스 홀, 배선 패턴, 얼라인먼트 마크, 솔더레지스트층, 회로기판, 투명층 First, the sprocket hole 12 and the device hole 14 are formed in the insulating base 11 which is flexible, tape-shaped, and transparent or translucent. Next, the conductor is laminated on the surface of the insulating base to form a conductive layer. Next, desired portions of the conductive layer are etched to form the wiring pattern 13 and the alignment mark 15. Next, the soldering resist layer 16 is formed in the place other than the terminal part of an wiring pattern, and an alignment mark. Finally, a transparent or translucent transparent layer 17 is formed on the surface of the circuit board to allow light to pass through the front and back of the circuit board around the alignment mark so that the position of the alignment mark can be confirmed. Get Insulation base, sprocket hole, device hole, wiring pattern, alignment mark, solder resist layer, circuit board, transparent layer

具有位置信息的布线基板

一种半导体封装的布线板包括具有第一和第二表面的基板；由在第一和第二表面中的至少一个上形成的由必需的布线图形组成的布线层；在形成有布线层的基板的表面上形成的多个半导体元件安装区；以及，用于各半导体元件安装区作为位置信息的特有图形，对于各半导体元件安装区来说，所述特有图形具有特定的形状。作为位置信息的特有图形形成在各个半导体元件安装区周边的区域。

Semiconductor devices having through vias and methods for fabricating the same

본 발명은 관통전극을 갖는 반도체 소자 및 그 제조방법에 관한 것으로, 상면과 그 반대면인 하면을 포함하는 기판과, 상기 기판을 관통하여 상기 기판의 하면 밖으로 돌출된 관통전극과, 상기 기판의 하면을 덮는 하부절연막과, 그리고 상기 하부절연막의 일부가 함몰되어 정의된 정렬 키를 포함한다. 상기 정렬 키의 모서리는 라운딩된 것일 수 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a through electrode, and a method of manufacturing the same, comprising: a substrate including a top surface and a bottom surface opposite to the top surface; And a lower insulating layer covering the portion and an alignment key defined by recessing a portion of the lower insulating layer. The corner of the alignment key may be rounded.

書込み可能な集積回路パッケ−ジ

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Method, system, and apparatus for high volume transfer of dies

A system, method and apparatus for die transfer using a changeable or movable material is described herein. The die plate has a planar body. The body has a plurality of holes therethrough. Each die covers a corresponding hole on a first surface of the die plate. The holes are filled with a material that can be caused to expand, exert pressure, or move when exposed to one or more stimuli. The die plate is positioned to be closely adjacent to the web of substrates. The dies can subsequently be transferred from the die plate to one or more destination substrates or other surfaces by applying one or more stimuli to the material, causing the material to expand, exert pressure, or move. The action of the material causes the dies to separate from the die plate.

Printed wiring board

도체 회로를 형성한 배선 기판에 대하여, 그 표면에 솔더 레지스트층을 형성함과 함께, 그 솔더 레지스트층에 형성한 개구부로부터 노출되는 상기 도체 회로의 일부를 도체 패드로서 형성하여, 그 도체 패드 상에 전자 부품을 실장하기 위한 땜납 범프를 형성하여 이루어지는 프린트 배선판에 있어서, 솔더 레지스트층에 형성한 개구부의 피치가 200㎛ 이하의 협피치 구조에서도, 땜납 범프 직경 (W) 과 개구부의 개구 직경 (D) 의 비 (W/D) 를 1.05 ∼ 1.7 로 함으로써, 접속 신뢰성 및 절연 신뢰성이 향상된다. 프린트 배선판, 솔더 레지스트층, 땜납 범프, 협피치 구조

Multilayer printed wiring board and method for producing multilayer printed wiring board

다층프린트배선판은, 코어기판(30)에 IC칩(20)을 미리 내장시키고, 해 IC칩(20)의 패드(24)에는 트랜지션층(38)을 형성시키고 있다. 이 때문에, 리드부품이나 봉지수지를 사용하지 않고, IC칩과 다층프린트배선판과의 전기적 접속을 취하는 것이 가능하다. 또, 다이패드(24) 상에 동제의 트랜지션층(38)을 설치하는 것으로, 패드(24) 상의 수지잔재를 방지할 수 있어, 패드(24)와 비아홀(60)과의 접속성이나 신뢰성을 향상시킨다. 다층프린트배선판 In the multilayer printed circuit board, the IC chip 20 is built in the core substrate 30 in advance, and the transition layer 38 is formed on the pad 24 of the IC chip 20. For this reason, it is possible to make electrical connection with an IC chip and a multilayer printed wiring board, without using a lead component or sealing resin. In addition, by providing a copper transition layer 38 on the die pad 24, resin residue on the pad 24 can be prevented, and the connection between the pad 24 and the via hole 60 and reliability can be improved. Improve. Multilayer printed wiring board

Method of marking by laser

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Process for mfg. of semiconductor wafer, semiconductor chip and IC card

本发明的半导体晶片制造方法包括将多个电路元件(41)与基板(1a)做成一体的工序、在与电路元件(41)导通的电极区(11b)上形成电极凸点(11)的工序、在基板(1a)规定位置形成划线或划线标记(21a)的工序、以及粘贴各向异性导电膜(30)以覆盖各电极凸点(11)及划线或标线标记(21a)的工序。形成各电极凸点(11)的工序与形成划线或划线标记(21a)的工序同时地进行。电极凸点(11)及划线或划线标记(21a)最好由金形成。根据这样的制造方法,即使是将各向异性电膜粘贴在形成多个电路元件的半导体晶片上的情况,也能够按照所希望的那样分割电路元件。

Changing method of mark

Manufacturing method of semiconductor device

Method for flip chip bonding and flip chip bonder implementing the same

본 발명은 레이저 압착 방식을 적용하여 높은 생산성과 접합 신뢰성을 얻을 수 있는 플립 칩 본딩 방법 및 이를 채택한 플립 칩 본딩 장치를 제공하는 것을 목적으로 하며, 이러한 목적을 달성하기 위하여 본 발명은, 기판이 안착되는 본딩 스테이지와, 반도체 칩을 픽업하여 상기 기판 상에 부착하는 본딩 헤드와, 상기 반도체 칩의 온도를 접합 온도까지 가열하는 반도체칩 가열 기구를 구비하고, 반도체 칩의 가열 기구는 레이저 광원과, 레이저 광원으로부터 나온 레이저 빔의 조사 중심 위치가 반도체 칩 상면에서 변경되도록, 레이저 빔을 반도체 칩 상면으로 굴절하여 조사하는 렌즈 조립체를 구비하는 플립 칩 본딩 장치를 제공한다. An object of the present invention is to provide a flip chip bonding method and a flip chip bonding apparatus employing the same, which can achieve high productivity and bonding reliability by applying a laser crimping method. And a bonding head for picking up and attaching the semiconductor chip to the substrate, and a semiconductor chip heating mechanism for heating the temperature of the semiconductor chip to a bonding temperature, wherein the heating mechanism of the semiconductor chip includes a laser light source and a laser. Provided is a flip chip bonding device having a lens assembly for irradiating and irradiating a laser beam onto an upper surface of the semiconductor chip such that the irradiation center position of the laser beam emitted from the light source is changed on the upper surface of the semiconductor chip.

Alignment key structure of a semiconductor device and method of forming the same

반도체 장치의 얼라인 키 구조물과 이를 형성하는 방법에서, 기판 상에 형성된 집적 회로를 포함하는 절연 구조물 상에 제1금속 배선들을 포함하는 제1층간 절연막과 제2금속 배선들 및 본딩 패드를 포함하는 제2층간 절연막이 형성된다. 상기 제2층간 절연막 상에는 상기 제2금속 배선들 중에서 하나만을 노출시키며 와이어 본딩 공정에서 얼라인 키로서 기능하는 제1개구와, 상기 본딩 패드를 노출시키는 제2개구를 갖는 보호막 패턴이 형성된다. 상기 제1개구는 상기 노출된 제2금속 배선의 폭보다 좁은 폭을 가지며, 상기 노출된 제2금속 배선의 양측 가장자리 부위들을 제외한 나머지 표면 부위를 노출시킨다. 따라서, 상기 제1개구와 제2개구를 형성하는 동안 상기 노출된 제2금속 배선을 제외한 나머지 제2금속 배선들의 식각 손상 및 상기 제1금속 배선들의 플라즈마 손상이 방지될 수 있다. 따라서, 반도체 장치의 동작 신뢰도 및 생산성이 향상될 수 있다. A method of forming an alignment key structure of a semiconductor device, the method comprising: forming a first interlayer insulating film on the insulating structure including an integrated circuit formed on a substrate, the first interlayer insulating film including first metal interconnection lines, A second interlayer insulating film is formed. A protective film pattern having a first opening exposing only one of the second metal wirings on the second interlayer insulating film and functioning as an alignment key in a wire bonding process and a second opening exposing the bonding pad are formed. The first opening has a width narrower than the width of the exposed second metal interconnection and exposes other surface portions except for both side edge portions of the exposed second metal interconnection. Therefore, etch damage of the second metal interconnection except for the exposed second metal interconnection and plasma damage of the first metal interconnection can be prevented while forming the first opening and the second opening. Therefore, operational reliability and productivity of the semiconductor device can be improved.

Tape Carrier Package with Window and Liquid Crystal Display Device containing the TCP

본 발명은 집적회로가 실장되는 테이프 케리어 패키지를 액정패널과 인쇄배선기판 상에 접합시킴에 있어서 테이프 케리어 패키지와 인쇄배선기판의 얼라인먼트 정도를 확인할 수 있도록 윈도우를 가지는 테이프 케리어 패키지 및 이를 장착한 액정표시장치에 관한 것이다. The present invention provides a tape carrier package having a window so as to check the alignment degree of the tape carrier package and the printed wiring board in bonding the tape carrier package on which the integrated circuit is mounted on the liquid crystal panel and the printed wiring board, and a liquid crystal display having the same. Relates to a device. 본 발명의 테이프 케리어 패키지는 베이스 필름과; 베이스필름 상에 탑재된 집적회로와; 집적회로와 접속되어 베이스필름 상에 형성된 입력패드들과; 입력패드들의 측단에 형성된 더미패드들과; 적어도 둘 이상의 더미패드가 노출되도록 베이스필름을 제거하여 형성된 윈도우를 구비한다. The tape carrier package of the present invention comprises a base film; An integrated circuit mounted on the base film; Input pads connected to the integrated circuit and formed on the base film; Dummy pads formed at side ends of the input pads; And a window formed by removing the base film to expose at least two dummy pads. 본 발명에 의하면, 테이프 케리어 패키지의 윈도우를 통하여 테이프 케리어 패키지와 인쇄배선보드간의 접속 얼라인먼트를 확인할 수 있다. According to the present invention, the connection alignment between the tape carrier package and the printed wiring board can be confirmed through the window of the tape carrier package.

Method of crystallizing of an amorphous silicon layer

본 발명에서는, 불균일한 결정 영역을 감소시키고 공정시간을 단축할 수 있는 비정질 실리콘의 결정화 공정 및 이를 포함하는 스위칭 소자용 반도체층의 제조 방법을 제공하기 위하여, 결정화 공정뿐만 아니라 사진식각 공정용 얼라인 키로 겸용할 수 있는 얼라인 키의 제조 방법 및 이러한 얼라인 키를 이용한 결정화 공정 및 반도체층의 제조 방법을 제공하는 것을 특징으로 하며, 이에 따라 첫째 얼라인 키를 기준으로, 비정질 실리콘층의 결정화 공정을 진행하기 때문에 레이저 빔의 정확한 위치제어를 가능하게 함으로써, 레이저 샷의 오버랩에 의한 불균일성을 해소할 수 있으며, 또한 스위칭 소자 채널 내의 그레인 바운더리 위치제어를 할 수 있기 때문에 소자 특성이 우수한 스위칭 소자 제작이 가능하고, 둘째, 완전 용융 영역대 에너지 밀도보다 큰 에너지 밀도를 가지는 레이저 빔의 조사를 통한 어블레이션(ablation) 반응에 의해 원하는 영역만을 선택적으로 제거하는 방법으로 음각형태의 단차 특성을 가지는 얼라인 키를 제조함으로써, 얼라인 키 제조를 위한 별도의 식각 공정을 생략할 수 있고, 비정질 실리콘층의 선택적 결정화 및 후속 반도체층의 사진식각 공정에 이용할 수 있어, 별도의 사진식각 공정용 얼라인 키 제조 공정을 생략함으로써, 공정수를 줄여 생산수율을 높일 수 있는 장점을 가진다.

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Semiconductor device

Epoxy resin composition and resin-encapsulated semiconductor device produced by using same

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

A method for indicating wafer defect according to the composition of the defect

본 발명은 웨이퍼 디펙트 소스에 대한 성분별 불량칩수 표시 방법에 관한 것으로서, 웨이퍼 디펙트 소스에 대한 성분별 불량칩수 표시 방법에 있어서, 반도체 결함 검사 장비를 이용하여 웨이퍼 상의 디펙트 소스를 찾아내고, 상기 디펙트 소스를 반도체 결함 검사 장비를 이용하여 성분 분석하고, 상기 디펙트 소스의 성분 분석된 디펙트에 동일한 원인이 있는 경우 동일한 표시를 하고, 상기 표시에 따라 웨이퍼 상에 디펙트의 산포와 치우침을 나타내고, 그래프 상으로 디펙트의 개수를 나타내어 디펙트의 통계적 처리를 하는 것을 포함하는 것을 특징으로 하는 웨이퍼 디펙트 소스에 대한 성분별 불량칩수 표시 방법을 제공함으로써 반도체 양산에서의 불량을 더욱 신속하고 효과적으로 방지함으로써 반도체 생산 수율 향상을 도모할 수 있다. The present invention relates to a method for displaying the number of defective chips for each component of a wafer defect source. In the method for displaying the number of defective chips for each component of a wafer defect source, a defect source on a wafer is found using a semiconductor defect inspection apparatus. The defect source is analyzed by using a semiconductor defect inspection device, and the same marking is performed when there is the same cause in the component analyzed defect of the defect source, and the distribution and deflection of the defect on the wafer according to the marking The defect chip number display method for each component of the wafer defect source is characterized in that the defect count is statistically processed by indicating the number of defects on a graph. By effectively preventing the semiconductor production yield can be improved.

Method and apparatus for optical alignment of integrated circuit devices

Using a reference technique to improve nominal registration

(57)【要約】 積層基板のコア層の上に位置合せマークを形成することにより該基板を作る方法である。そして該位置合せマークを基準位置合せ点として用いて該コア層の上に第１の層を形成する。該コア層の上の該位置合せマークを露出させるために、該第１の層はレーザ穿孔される。次に該位置合せマークを基準位置合せ点として用いて該第１の層の上に第２の層を形成する。

Ic package structure, lcd apparatus, and electronic device

(57)【要約】 【課題】 不透明な回路基板上にＩＣチップを装着する 作業を簡単且つ迅速に行うことができるようにする。 【解決手段】 不透明な回路基板１に貫通穴によってア ライメントマーク４Ｋを形成する。ＣＣＤカメラ９によ ってアライメントマーク穴４Ｋ越しにＩＣチップ３のア ライメントマーク４Ｉを撮影し、ＩＣ側アライメントマ ーク４Ｉが基板側アライメントマーク穴４Ｋに対して所 定の位置関係になるようにＩＣチップ３の位置を調節す る。そしてその後、ＩＣチップ３をＡＣＦ２等の接合剤 を用いて回路基板１へ接着する。カメラ９による１回の 撮影だけで両アライメントマーク４Ｉ及び４Ｋを同時に 撮影でき、さらに引き続いて位置合わせを行うことがで きる。

Semiconductor device and fabrication method for the same

단결정 Si웨이퍼(100)상의 소자분리영역을 로코스 산화하여, 필드 산화막(SiO 2 막)(104)을 형성한다. 또한, 필드 산화막(104)상에 마커(107)를 형성한다. 이로써, 절연기판(2)상에, 단결정 Si웨이퍼(100)상에 형성된 단결정 Si박막 트랜지스터(16a)가 전사되어 이루어진 반도체장치(20)에 있어서, 전사시 및 전사 후에 게이트전극(106)을 중심으로 하는 얼라인먼트를 가능하게 한다. The device isolation region on the single crystal Si wafer 100 is LOCOS oxidized to form a field oxide film (SiO 2 film) 104. In addition, a marker 107 is formed on the field oxide film 104. Thus, in the semiconductor device 20 in which the single crystal Si thin film transistor 16a formed on the single crystal Si wafer 100 on the insulating substrate 2 is transferred, the gate electrode 106 is centered during and after the transfer. Enable alignment.

Member to be recognized for alignment, head unit and electronic equipment comprising the same, method of producing lcd, method of producing organic el device, method of producing electron emission device, method of producing pdp device, method of producing electrophoresis display, method of producing color filter, method of producing organic el, spacer forming method, metal wiring forming method, lens forming method, resist forming method, and photo diffuser forming method

본 발명은 간단한 구조로 확실하게 화상 인식 가능한 얼라인먼트용 피인식 부재 및 이를 구비한 헤드 유닛, 및 전자 기기를 제공하는 것을 그 과제로 한다. An object of the present invention is to provide an alignment-recognized member capable of reliably image recognition with a simple structure, a head unit having the same, and an electronic device. 위치 결정 대상물에 설치되고, 화상 인식용 마크(26)를 형성한 얼라인먼트용 피인식 부재(12)로서, 기둥 형상으로 형성되고 선단면(29a)을 경면 가공한 부재 본체(25)와, 부재 본체(25)의 선단면(29a)의 대략 중앙부에 형성한 오목 형상의 마크(26)를 구비한 것이다. The member main body 25 which is provided in the positioning target object, and the alignment to-be-recognized member 12 which provided the mark 26 for image recognition, formed in columnar shape, and mirror-processed the front end surface 29a, and the member main body. The recessed mark 26 formed in the substantially center part of the front end surface 29a of (25) is provided.

Semiconductor package, manufacturing method thereof and chip-redistribution encapsulant

Benefits of a composite board with semiconductor chips and plastic housing composition as well as methods and molding for the production thereof

Die Erfindung betrifft einen Nutzen (1) und ein Halbleiterbauteil (30) aus einer Verbundplatte (2) mit Halbleiterchips (3) und Kunststoffgehäusemasse (4) sowie ein Verfahren und eine Moldform zur Herstellung derselben. Der Nutzen (1) weist eine Verbundplatte (2) mit in Zeilen (24) und Spalten (25) angeordneten Halbleiterchips (3) in einer Kunststoffgehäusemasse (4) auf, wobei die aktive Oberseite (8) der Halbleiterchips (3) mit der Oberseite (6) der Verbundplatte (2) eine koplanare Fläche (9) bildet. Der Nutzen (1) weist ein während des Einbettens der Halbleiterchips (3) in die Kunststoffgehäusemasse (4) eingeprägtes Orientierungskennzeichnen (30) auf. The invention relates to a benefit (1) and a semiconductor component (30) made of a composite plate (2) with semiconductor chips (3) and plastic housing compound (4) as well as a method and a mold for producing the same. The panel (1) has a composite plate (2) with semiconductor chips (3) arranged in rows (24) and columns (25) in a plastic housing compound (4), the active top side (8) of the semiconductor chips (3) with the top side (6) the composite plate (2) forms a coplanar surface (9). The benefit (1) has an orientation mark (30) embossed during the embedding of the semiconductor chips (3) in the plastic housing compound (4).

Pcb strip of semiconductor package type

본 발명은 반도체 패키지용 인쇄 회로 기판 스트립에 관한 것으로, 반도체칩 안착 영역과, 상기 반도체 칩 안착영역의 주변에 형성된 구리 박막과, 상기 구리 박막에 형성된 전도성 비아 홀과, 상기 전도성 비아 홀의 외측으로 형성된 사각형상의 봉지부와, 상기 봉지부의 외곽에 사각 형상의 싱귤레이션부로 구성된 인쇄회로 기판 유닛이 다수 연결되어서 이루어진 인쇄 회로 기판 스트립에 있어서, 상기 인쇄 회로 기판 스트립 내의 불량이 발생된 인쇄 회로 기판 유닛에는 통공이 형성된 특징으로 하여, 인쇄 회로 기판 스트립의 휨 현상, 인쇄 회로 기판 스트립 자체의 오염, 몰드 금형의 오염 등을 방지하고 불량 인쇄 회로 기판 스트립 중의 인쇄 회로 기판 유닛을 용이하게 확인하여 작업을 진행할 수 있는 반도체 패키지용 인쇄 기판 스트립. The present invention relates to a printed circuit board strip for a semiconductor package, comprising: a semiconductor chip mounting region, a copper thin film formed around the semiconductor chip mounting region, a conductive via hole formed in the copper thin film, and an outer side of the conductive via hole A printed circuit board strip formed by connecting a rectangular encapsulation portion and a plurality of printed circuit board units composed of a rectangular singulation portion on an outer side of the encapsulation portion, wherein the defects in the printed circuit board strip are formed through holes. This formed feature prevents warpage of the printed circuit board strip, contamination of the printed circuit board strip itself, contamination of the mold mold, and the like, and facilitates work by identifying the printed circuit board unit in the defective printed circuit board strip. Printed board strips for semiconductor packages.

Method for forming a foil carrier structure and packaging integrated circuit devices

본 발명은, 집적 회로 패키지 내에 전기적 상호접속부를 형성하기 위해 얇은 포일을 이용하는 방법 및 장치에 관한 것이다. 일 실시형태에서, 포일 캐리어 구조는 금속 캐리어에 도전성 포일 (conductive foil) 의 부분을 초음파적으로 접합함으로써 형성된다. 접합 부분은 포일 캐리어 구조 내에 패널들을 정의한다. 몇몇 실시형태에서, 포일 캐리어 구조가 절단되어 그 주변을 따라서 밀봉되는 다수의 절연 패널들을 형성한다. 각각의 절연 패널은 대체로 종래의 리드프레임 스트립 또는 패널의 크기일 수도 있다. 그 결과, 기존의 패키징 장비는 패널에 다이, 접합 배선 및 몰딩 재료를 부가하는데 사용될 수도 있다. 초음파 용접은, 이러한 프로세싱 단계들 도중에 원치않는 물질들이 포일 캐리어 구조를 침투하는 것을 방지하는 것을 돕는다. 몰딩된 포일 캐리어 구조의 캐리어 부분이 제거된 후, 이 구조는 집적 회로 패키지로 개별화된다. 몇몇 실시형태는, 전술한 동작들 중 몇몇 또는 모두를 활용하는 방법에 관한 것이다. 다른 실시형태들은 전술한 프로세스에서 이용되는 장치에 관한 것이다. The present invention relates to a method and apparatus for using a thin foil to form electrical interconnects in an integrated circuit package. In one embodiment, the foil carrier structure is formed by ultrasonically bonding a portion of a conductive foil to a metal carrier. The joint defines the panels within the foil carrier structure. In some embodiments, the foil carrier structure is cut to form a plurality of insulating panels that are sealed along its periphery. Each insulating panel may be substantially the size of a conventional lead frame strip or panel. As a result, existing packaging equipment may be used to add die, bond wires and molding material to the panel. Ultrasonic welding helps to prevent unwanted materials from penetrating the foil carrier structure during these processing steps. After the carrier portion of the molded foil carrier structure is removed, the structure is individualized into an integrated circuit package. Some embodiments relate to methods of utilizing some or all of the above-described operations. Other embodiments are directed to devices used in the process described above.

Method and system for marking a workpiece such as a semiconductor wafer and laser marker for use therein

반도체 웨이퍼(3)의 장치가 제공된다. 이 시스템은 (a) 웨이퍼에 대한 레이저마킹 필드을 위치결정하는 제 1 위치결정 서브시스템과; (b) 위치일치 시각 서브시스템과; (c) 레이저 마킹 빔을 이용하여 마킹 필드내의 위치를 마킹하는 레이저를 포함하는 레이저 마커와; (d) 시스템의 하나이상의 서브시스템을 캘리브레이션하느 캘리브레이션 프로그램과; (e)컨트롤러를 구비한다. 마킹 필드는 웨이퍼보다 실질적으로 작고 레이저 마커는 웨이퍼 휨과 관련된 바람직하지 않은 마크 변수와 필드내의 깊이의 변수를 방지하도록 웨이퍼상의 빔에 의해 형성된 스폿을 마킹필드내의 위치주위의 허용가능한 범위내에 광학적으로 유지시키는 스켄 렌즈를 포함한다. The apparatus of the semiconductor wafer 3 is provided. The system includes (a) a first positioning subsystem for positioning a laser marking field relative to the wafer; (b) a location matching time subsystem; (c) a laser marker comprising a laser to mark a position in a marking field using a laser marking beam; (d) a calibration program for calibrating one or more subsystems of the system; (e) A controller is provided. The marking field is substantially smaller than the wafer and the laser marker optically keeps the spots formed by the beam on the wafer within an acceptable range around the location in the marking field to prevent undesirable mark variables associated with wafer warpage and variations in depth in the field. And a scanning lens. 레이저 마커 Laser marker

Marking method and protective film forming and dicing sheet

Circuit board and method of manufacturing circuit board

Marking correction method for laser marking system

【課題】 各チップの整列誤差を検出し、各チップの位置でのマーキング誤差を勘案したマーキングをするレーザマーキングシステムのマーキング補正方法を提供すること。 【解決手段】 本発明はレーザマーキングシステムのマーキング補正方法に関する。開示されたレーザマーキングシステムのマーキング補正方法は、（ａ）各ビジョンカメラに観察対象チップを割り当てる段階と、（ｂ）各ビジョンカメラ及びレーザマーカの座標を一致させる段階と、（ｃ）前記各チップまたは各チップに該当する位置に第１シンボルをマーキングし、当該ビジョンカメラで選択された第１シンボルを観察し、そのシンボルの一点を基準点としてティーチングする段階と、（ｄ）当該ビジョンカメラで前記チップの前記第１シンボル及び基準点を観察して各チップに前記基準点を基準として第２シンボルをマーキングする段階と、（ｅ）選択されたチップ上の第２シンボルを観察してそのシンボルの比較点をティーチングする段階と、（ｆ）各チップ上の前記基準点から前記比較点の位置を検出して各セルでのマーキング誤差を検出する段階と、を備える。

Method for manufacturing electronic component mounting body and electro-optical device

본 발명은 전자 부품을 회로 기판 상에 실장하여 이루어지는 전자 부품 실장체를, 용이하고 저렴하게, 또한 높은 전기적 신뢰성을 갖고 효율적으로 제조할 수 있는 방법을 제공하는 것으로, 본 발명의 전자 부품 실장체의 제조 방법은 외부 실장 단자로서의 범프(11)를 구비한 IC칩(10)을, 열가소성 수지로 이루어지는 기재(基材)(13)에 실장하는 방법으로서, 상기 IC칩(10)을 기재(13)에 대하여 가열 가압함으로써 상기 범프(11)를 상기 기재(13)에 매립하고, 상기 범프(11)의 일부를 상기 IC칩(10)과 반대측의 기재면에 노출시키는 범프 매설 공정과, 상기 범프(11)의 일부가 노출된 기재면에 도전 재료를 배치함으로써 상기 범프(11)와 도전 접속된 도전체를 형성하는 도전체 형성 공정을 포함한다. Disclosure of Invention The present invention provides a method for easily and inexpensively and efficiently and efficiently manufacturing an electronic component package formed by mounting an electronic component on a circuit board. The manufacturing method is a method of mounting the IC chip 10 having the bumps 11 as external mounting terminals on a substrate 13 made of a thermoplastic resin, wherein the IC chip 10 is mounted on the substrate 13. A bump embedding step of embedding the bump 11 in the base material 13 by heating and pressurizing the same, exposing a part of the bump 11 to the base surface on the opposite side to the IC chip 10, and the bump ( And a conductor forming step of forming a conductor electrically conductively connected to the bumps 11 by disposing a conductive material on a substrate surface on which a part of 11) is exposed.

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Patent JPS5214112B2

Method of manufacture chip-size package type semiconductor device

절연막 상의 한 표면에 형성된 절연막 및 와이어링 패턴을 포함하는 반도체칩 및 캐리어 테이프를 포함하는 칩 크기 반도체 장치의 제조 방법에 있어서, 상기 반도체 칩의 접착 영역에 대응하는 선정 크기를 가지는 접착막의 사용에 의해 상기 반도체 칩과 상기 캐리어 테이프를 본딩하는 단계로서 상기 접착막은 가열에 의해 상기 반도체 칩과 상기 캐리어 테이프를 본드하고, 수지 재료에 의해 상기 반도체 칩을 몰딩하며, 상기 캐리어 테이프의 불필요한 부분을 절단하는데, 상기 본딩 단계는 테이블 상에 장착된 상기 반도체 칩 상에 고정된 접착 막 테이프로부터 펀칭에 의해 상기 접착막을 절단하고 상기 접착막을 아래로 이동시킴에 의해 상기 접착 영역 상에 접착막을 세팅하는 부속 단계를 포함한다. A method of manufacturing a chip-size semiconductor device including a semiconductor chip and a carrier tape including an insulating film and a wiring pattern formed on a surface of an insulating film and a carrier tape, characterized by using an adhesive film having a predetermined size corresponding to an adhesive region of the semiconductor chip Bonding the semiconductor chip and the carrier tape, bonding the semiconductor chip and the carrier tape by heating, molding the semiconductor chip by a resin material, cutting an unnecessary portion of the carrier tape, The bonding step includes an attaching step of setting the adhesive film on the adhesive area by cutting the adhesive film by punching from the adhesive film tape fixed on the semiconductor chip mounted on the table and moving the adhesive film downward do.

Laser-marking device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Bonding apparatus of semiconductor chip

본 발명의 기술적 사상에 의한 반도체 칩 본딩 장치는 반도체 칩을 흡착하여 파지하는 본딩 헤드; 상기 반도체 칩이 실장되는 기판이 배치되고, 상기 반도체 칩을 상기 기판에 실장하고 본딩하는 공정이 수행되는 본딩 스테이지; 상기 반도체 칩을 촬상하여 상기 반도체 칩의 위치 정보를 획득하는 제1 카메라; 상기 반도체 칩이 실장되는 기판을 촬상하여 상기 기판의 위치 정보를 획득하는 제2 카메라; 상기 본딩 스테이지의 측면부 일측에 형성되고, 보정용 칩과 보정용 기판을 구비하는 보정 장치 구조체; 및 상기 본딩 헤드로 상기 보정용 칩을 파지하고, 상기 보정용 기판에 실장하여 본딩 위치 보정을 제어하는 본딩 제어부를 포함한다. A semiconductor chip bonding apparatus according to the present invention includes: a bonding head for adsorbing and gripping a semiconductor chip; A bonding stage on which a substrate on which the semiconductor chip is mounted is disposed, and a process of mounting and bonding the semiconductor chip to the substrate is performed; A first camera that captures an image of the semiconductor chip and acquires location information of the semiconductor chip; A second camera for obtaining positional information of the substrate by photographing the substrate on which the semiconductor chip is mounted; A correction device structure formed on one side of a side surface of the bonding stage and including a correction chip and a correction substrate; And a bonding control unit that grips the correction chip by the bonding head and mounts it on the correction substrate to control bonding position correction.

Dicing tape-integrated film for semiconductor back surface, and process for producing semiconductor device

본 발명은 기재 및 점착제 층이 상기 순서로 적층된 다이싱 테이프, 및 상기 다이싱 테이프의 점착제 층 상에 적층된 반도체 이면용 필름을 포함하는 다이싱 테이프 일체형 반도체 이면용 필름으로서, 상기 점착제 층의 두께가 20 ㎛ 내지 40 ㎛인 다이싱 테이프 일체형 반도체 이면용 필름에 관한 것이다. A dicing tape integral type semiconductor backing film comprising a dicing tape in which a base material and a pressure sensitive adhesive layer are laminated in this order and a semiconductor backing film laminated on the pressure sensitive adhesive layer of the dicing tape, And a thickness of 20 占 퐉 to 40 占 퐉.

Semiconductor device

Semiconductor device and manufacture thereof

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Structural member

FIELD: structural members. SUBSTANCE: proposed structural member, for instance semiconductor component, has first integrated circuit disposed on second integrated circuit, both bearing first and second metal coatings facing one another, respectively, on one of their main surfaces. First metal coated areas are designed to electrically interconnect first and second integrated circuits. Newly introduced second metal coated areas are designed as additional electric functioning surfaces made beyond substrates of first and second integrated circuits. EFFECT: facilitated implementation of additional electric functions. 10 cl, 8 dwg ÐÎÑÑÈÉÑÊÀß ÔÅÄÅÐÀÖÈß (19) RU (11) 2 290 718 (13) C2 (51) ÌÏÊ H01L 25/065 (2006.01) ÔÅÄÅÐÀËÜÍÀß ÑËÓÆÁÀ ÏÎ ÈÍÒÅËËÅÊÒÓÀËÜÍÎÉ ÑÎÁÑÒÂÅÍÍÎÑÒÈ, ÏÀÒÅÍÒÀÌ È ÒÎÂÀÐÍÛÌ ÇÍÀÊÀÌ (12) ÎÏÈÑÀÍÈÅ ÈÇÎÁÐÅÒÅÍÈß Ê ÏÀÒÅÍÒÓ (21), (22) Çà âêà: 2004134730/28, 12.03.2003 (72) Àâòîð(û): ÕÞÁÍÅÐ Õîëüãåð (DE) (24) Äàòà íà÷àëà îòñ÷åòà ñðîêà äåéñòâè ïàòåíòà: 12.03.2003 (73) Ïàòåíòîîáëàäàòåëü(è): ÈÍÔÈÍÅÎÍ ÒÅÊÍÎËÎÄÆÈÇ Àà (DE) R U (30) Êîíâåíöèîííûé ïðèîðèòåò: 30.04.2002 DE 10219353.3 (43) Äàòà ïóáëèêàöèè çà âêè: 20.07.2005 (45) Îïóáëèêîâàíî: 27.12.2006 Áþë. ¹ 36 2 2 9 0 7 1 8 (56) Ñïèñîê äîêóìåíòîâ, öèòèðîâàííûõ â îò÷åòå î ïîèñêå: JP 20002235517 À, 11.08.2000. US 5811351 À, 22.09.1998. US 2002017707 A1, 14.02.2002. ÅÐ 0908952 À, 14.04.1999. JP 2000340745 À, 08.12.2000. RU 2006990 C1, 30.01.1994. 2 2 9 0 7 1 8 R U (86) Çà âêà PCT: DE 03/00787 (12.03.2003) C 2 C 2 (85) Äàòà ïåðåâîäà çà âêè PCT íà íàöèîíàëüíóþ ôàçó: 30.11.2004 (87) Ïóáëèêàöè PCT: WO 03/094234 (13.11.2003) Àäðåñ äë ïåðåïèñêè: 129010, Ìîñêâà, óë. Á.Ñïàññêà , 25, ñòð.3, ÎÎÎ "Þðèäè÷åñêà ôèðìà Ãîðîäèññêèé è Ïàðòíåðû", ïàò.ïîâ. Þ.Ä.Êóçíåöîâó, ðåã.¹ 595 (54) ÊÎÍÑÒÐÓÊÒÈÂÍÛÉ ÝËÅÌÅÍÒ (57) Ðåôåðàò: Èçîáðåòåíèå îòíîñèòñ ê êîíñòðóêòèâíîìó ýëåìåíòó. Ñóùíîñòü èçîáðåòåíè : êîíñòðóêòèâíûé ýëåìåíò, â ÷àñòíîñòè ïîëóïðîâîäíèêîâûé êîìïîíåíò, ñîäåðæèò ïåðâóþ ìèêðîñõåìó, ðàçìåùåííóþ íà âòîðîé ìèêðîñõåìå, ïðè÷åì ïåðâà è âòîðà ìèêðîñõåìû ...

ball grid array semiconductor package and method for making the same

본 발명은 반도체패키지 배열에 관한 것이다. 상기 패키지배열은 반도체패키지 배열 내에서 발생되는 열을 분산시키기 위한 방열기를 포함한다. 또 상기 패키지는 전기절연 접착제로 방열기에 부착된 제1 측면을 갖는 접지판을 포함한다. 접지판은 반도체 다이를 수납하도록 구성된 방열기의 표면에 통로를 한정하는 제1 개구부를 가지고 있다. 접속기판은 접지판에 접착되고, 접속기판은 접지판의 제1 개구부에 걸쳐있는 보조 제2 개구부를 가지고 있다. 접속기판은 반도체 다이를 반도체패키지 배열의 외부에 있는 전기접속에 전기접속시키기 위한 다수의 금속패턴을 갖는 것이 바람직하다. 또 패키지 배열은 접속기판을 관통하여 한정되고 접지판과 전기 접촉되어 접속기판의 다수의 금속패턴 중 일부로부터 직접 접지접속되도록 하는 적어도 하나 이상의 도전성 충진 비아를 포함한다. 접지판의 제2 측면은 접속기판을 관통하여 한정되는 적어도 하나 이상의 도전성 충진 비아와 전기 접속되는 소정의 지역에 걸쳐 있는 패턴화된 도금패드를 포함한다.

Substrate for semiconductor package

본 발명은 와이어 본딩 공정 전에 서브스트레이트의 정렬상태 뿐 아니라 서브스트레이트의 솔더마스크 얼라인 상태까지 동시에 확인 할 수 있는 반도체 패키지의 서브스트레이트 및 와이어 본딩머신을 제공하는 것을 그 목적으로 한다. 본 발명의 다른 목적은 본드핑거를 비롯한 솔더마스크 개방부의 영역을 최소화함으로써 서브스트레이트 표면의 디자인 및 공간활용을 효율적으로 하고, 와이어의 소모량을 최소화할 수 있는 반도체 패키지의 서브스트레이트 및 와이어 본딩머신을 제공하는 것이다. 이를 달성하기 위하여 본 발명은, 반도체 칩이 안착되고, 상기 반도체 칩의 외곽으로 본드핑거가 형성된 서브스트레이트에 있어서, 상기 서브스트레이트의 소정부에는 기준마크가 형성되고, 상기 기준마크는 기준메탈과 상기 기준메탈위로 도포되는 솔더마스크의 일부가 오픈된 개방부를 포함하는 것을 특징으로 하는 반도체 패키지의 서브스트레이트를 제공한다. 서브스트레이트, 기준마크, 기준메탈, 와이어, 본딩머신

Laser marking techniques

A laser marking apparatus and method for marking the surface of a semiconductor chip are described herein. A laser beam is directed to a location on the surface of the chip where a laser reactive material, such as a pigment containing epoxy is present. The heat associated with the laser beam causes the laser reactive material to fuse to the surface of the chip creating a visibly distinct mark in contrast to the rest of the surface of the chip. Only reactive material contacted by the laser fuses to the chip surface, and the remaining residue on the non-irradiated portion can be readily removed.

Static semiconductor memory

박막 트랜지스터를 부하 소자로서 사용하는 정적 메모리 셀에 있어서, α선 등의 외난에 대한 소프트 에러 내성의 향상을 도모한다. 벌크형 n채널 MOS트랜지스터(T 2 , T 4 )를 구동 트랜지스터로 하고, p채널 박막 트랜지스터(T 1 , T 3 )를 부하 트랜지스터로 하는 메모리 셀에 있어서, 박막 트랜지스터(T 1 , T 3 )의 게이트 전극과 드레인 사이에 용량 전자(C 1 , C 2 )가 형성된다.

Circuit board and method for manufacturing the same

一种电路基板及电路基板的制造方法，首先，在具有柔性、带状、透明或者半透明的绝缘基底(11)上形成链轮孔(12)和器件孔(14)。接着，在绝缘基底的表面上层叠导电体，形成导电层。接着，蚀刻该导电层的所期望的部位，形成布线图形(13)和对准标记(15)。接着，在布线图形的端子部分及对准标记以外的部位形成阻焊层(16)。最后，在对准标记的周围，在绝缘基底上，使光透过电路基板的表面和背面，以可确认对准标记的位置的方式形成其表面透明或半透明的透明层(17)，制成电路基板。

Semiconductor device having a align mark film and method of fabricating the same

A semiconductor device and its manufacturing method are provided to reduce alignment errors in an assembling step by using an align mark layer. A semiconductor device includes a pad electrode layer, an align mark layer, a passivation layer and a transparent protection layer. The pad electrode layer(130) is formed on a semiconductor substrate(105). The pad electrode layer is used as input/output terminals. The align mark layer(135) is formed on the substrate to be used as an align key in an assembling step. The passivation layer(140) is formed on the substrate to expose partially upper portions of the pad electrode layer and the align mark layer. The transparent protection layer(150) is used for covering at least a portion of the passivation layer and the exposed upper portion of the align mark layer.

Chip-scale marker and marking method

본 발명은 칩 스케일 마커 및 마킹 방법에 관하여 개시한다. 개시된 칩 스케일 마커의 마킹방법은, 레이저 발진기로부터 발진된 레이저 빔을 갈바노 스캐너 및 f-세타 렌즈를 통해서 웨이퍼 홀더에 위치한 웨이퍼의 다수의 칩에 마킹을 하는 칩 스케일 마커의 마킹방법에 있어서, (a)상기 웨이퍼의 다수의 포인트의 위치 정보를 측정하는 단계; (b)상기 측정된 위치 정보를 제어기로 전송하는 단계; (c)상기 전송된 위치정보로부터 상기 f-세타 렌즈 및 상기 포인트 사이의 마킹거리와 상기 f-세타 렌즈의 초점거리 사이의 편차를 계산하는 단계; 및 (d)해당 웨이퍼 칩에서 상기 (c)단계의 편차가 소정 이상인 경우, 상기 f-세타 렌즈의 초점거리에 해당 웨이퍼 칩이 위치하도록 보정하고 마킹하는 단계;를 구비한다. 이에 따르면, 휨 현상이 있는 웨이퍼의 칩들을 f-세타 렌즈로부처 소정거리에 위치하도록 보정하여 마킹을 하므로 마킹 품질을 향상시킬 수 있다. The present invention discloses a chip scale marker and marking method. Disclosed is a method of marking a chip scale marker in which a laser beam oscillated from a laser oscillator is marked on a plurality of chips of a wafer located in a wafer holder through a galvano scanner and an f-theta lens. a) measuring position information of a plurality of points of the wafer; (b) transmitting the measured position information to a controller; (c) calculating a deviation between a marking distance between the f-theta lens and the point and a focal length of the f-theta lens from the transmitted position information; And (d) correcting and marking the wafer chip at a focal length of the f-theta lens when the deviation of the step (c) is greater than or equal to the wafer chip. Accordingly, the marking quality can be improved because the markings of the warped wafers are corrected to be positioned at a predetermined distance from the f-theta lens.

Semiconductor device

Semiconductor device