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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 13121. Отображено 100.
26-01-2012 дата публикации

Switching element, variable inductor, and electronic circuit device having circuit configuration incorporating the switching element and the variable inductor

Номер: US20120018842A1
Автор: Hideo Ishihara, Kunihiko Nakajima, Yuichi Sasajima
Принадлежит: TAIYO YUDEN CO LTD

An inexpensive variable inductor has inductance value continuously changeable without reducing a Q value. When a control voltage is applied to a control terminal of a MOS transistor from a power supply, a continuity region is formed in a channel, and a region between main terminals becomes conductive. When the control voltage is changed, length of the continuity region in the channel is changed. This changes length of a path area of an induced current, flowing in an induced current film. Thus, the amount of induced current is increased or decreased. Therefore, when the control voltage of the MOS transistor is changed, the inductance value of the coil is continuously changed.

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Номер записи: 1
02-02-2012 дата публикации

Methods of operating electronic devices, and methods of providing electronic devices

Номер: US20120028582A1
Автор: Patrick W. Tandy
Принадлежит: Round Rock Research LLC

Some embodiments include a method disposing an integrated circuit die within a housing, the integrated circuit die having integrated circuitry formed thereon, the integrated circuitry including first transponder circuitry configured to transmit and receive radio frequency signals, wherein the integrated circuit die is void of external electrical connections for anything except power supply external connections; and disposing second transponder circuitry, discrete from the first transponder circuitry, within the housing, the second transponder circuitry being configured to transmit and receive radio frequency signals, wherein the first and second transponder circuitry are configured to establish wireless communication between one another within the housing, the second transponder circuitry being disposed within 24 inches of the first transponder circuitry within the housing.

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Номер записи: 2
09-02-2012 дата публикации

Gain Enhanced LTCC System-on-Package for UMRR Applications

Номер: US20120032836A1
Автор: Atif SHAMIM, Farhan Abdul Ghaffar, Khaled Nabil Salama, Muhammad Umair Khalid
Принадлежит: King Abdullah University of Science and Technology KAUST

An apparatus, system, and method for Gain Enhanced LTCC System-on-Package radar sensor. The sensor includes a substrate and an integrated circuit coupled to the substrate, where the integrated circuit is configured to transmit and receive radio frequency (RF) signals. An antenna may be coupled to the integrated circuit and a lens may be coupled to the antenna. The lens may be configured to enhance the gain of the sensor.

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Номер записи: 3
16-02-2012 дата публикации

High-frequency switch

Номер: US20120038411A1
Автор: Hirotsugu Wakimoto, Masanori Ochi, Masayuki Sugiura, Noriyasu Kurihara, Toshiki Seshita, Toshiyuki Shimizu, Yoshio Itagaki, Yoshitomo Sagae
Принадлежит: Toshiba Corp

According to one embodiment, a high-frequency switch includes a high-frequency switch IC chip. The high-frequency switch IC chip has a high-frequency switching circuit section including an input terminal, a plurality of switching elements, a plurality of high-frequency signal lines, and a plurality of output terminals. The input terminal is connected to each of the plurality of output terminals via each of the plurality of switching elements with the high-frequency signal lines having the same lengths. The plurality of output terminals are arranged on a surface at an outer periphery of the high-frequency switch IC chip. The input terminal is arranged on the surface of the high-frequency switch IC chip at the center of the high-frequency switch IC circuit section.

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Номер записи: 4
08-03-2012 дата публикации

Baluns for rf signal conversion and impedance matching

Номер: US20120056297A1
Автор: Petteri Litmanen, Richard Francis Taylor, Siraj Akhtar
Принадлежит: Texas Instruments Inc

A magnetically-coupled structure is integrated with an integrated circuit in back end-of-line (BEOL) digital CMOS fabrication processes. A differential primary (or secondary) coil is formed by patterning a thick copper (Cu) metal layer, and a single-ended secondary (or primary) coil is formed by patterning a thick aluminum (Al) top metal bonding layer. Crossovers and/or cross-unders are formed using thin metal layers. One embodiment provides a stacked balun with a differential primary input winding defined in the copper layer, directly underneath a single-ended spiral winding defined in the aluminum layer. The spiral forms the single-ended secondary output of the balun and is rotated by 90° to prevent metal shorting for its cross-under connections. Another embodiment provides a transformer with one differential primary (or secondary) coil defined in the copper layer and another differential secondary (or primary) coil defined in the aluminum layer and adding a center tap. The position of the tap is selected to compensate for phase differences and provide desired balance.

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Номер записи: 5
15-03-2012 дата публикации

Power amplifier circuit

Номер: US20120062325A1
Автор: Joong Jin NAM, Jun Goo WON, Ki Joong KIM, Seong Geon KIM, Youn Suk Kim
Принадлежит: Samsung Electro Mechanics Co Ltd

There is provided a power amplifier circuit capable of improving cross isolation between a high frequency band power coupler and a low frequency band power coupler, by directly transmitting power to the high frequency band power coupler and the low frequency band power coupler from a power amplifier, and forming a predetermined inductance circuit or an LC resonance circuit in a line transmitting the power to the high frequency band power coupler. The power amplifier circuit may include a power amplifying unit supplied with power from the outside and amplifying an input signal, a coupling unit having a high frequency band power coupler and a low frequency band power coupler, and an isolation unit including a first power line and a second power line, wherein the first power line has an inductor blocking signal interference generated in a predetermined frequency band.

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Номер записи: 6
15-03-2012 дата публикации

Semiconductor package integrated with conformal shield and antenna

Номер: US20120062439A1
Автор: Chi-Hong Chan, Kuo-Hsien Liao, Shih Fuyu
Принадлежит: Advanced Semiconductor Engineering Inc

A semiconductor package integrated with conformal shield and antenna is provided. The semiconductor package includes a semiconductor element, an electromagnetic interference shielding element, a dielectric structure, an antenna element and an antenna signal feeding element. The electromagnetic interference shielding element includes an electromagnetic interference shielding film and a grounding element, wherein the electromagnetic interference shielding film covers the semiconductor element and the grounding element is electrically connected to the electromagnetic interference shielding layer and a grounding segment of the semiconductor element. The dielectric structure covers a part of the electromagnetic interference shielding element and has an upper surface. The antenna element is formed adjacent to the upper surface of the dielectric structure. The antenna signal feeding element passing through the dielectric structure electrically connects the antenna element and the semiconductor element.

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Номер записи: 7
15-03-2012 дата публикации

Thermal interface material application for integrated circuit cooling

Номер: US20120063094A1
Автор: Dong G. Kam, Duixian Liu, Michael A. Gaynes, Scott K. Reynolds
Принадлежит: International Business Machines Corp

Techniques provide improved thermal interface material application in an assembly associated with an integrated circuit package. For example, an apparatus comprises an integrated circuit module, a printed circuit board, and a heat transfer device. The integrated circuit module is mounted on a first surface of the printed circuit board. The printed circuit board has at least one thermal interface material application via formed therein in alignment with the integrated circuit module. The heat transfer device is mounted on a second surface of the printed circuit board and is thermally coupled to the integrated circuit module. The second surface of the printed circuit board is opposite to the first surface of the printed circuit board.

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Номер записи: 8
22-03-2012 дата публикации

Massively Parallel Interconnect Fabric for Complex Semiconductor Devices

Номер: US20120068229A1
Автор: Farhang Yazdani, Majid Bemanian
Принадлежит: Individual

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

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Номер записи: 9
22-03-2012 дата публикации

Multi-function and shielded 3d interconnects

Номер: US20120068327A1
Автор: Belgacem Haba, Craig Mitchell, Ilyas Mohammed, Piyush Savalia, Vage Oganesian
Принадлежит: TESSERA RESEARCH LLC

A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element.

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Номер записи: 10
22-03-2012 дата публикации

High speed digital interconnect and method

Номер: US20120068890A1
Автор: Baher S. Haroun, Marco Corsi, Nirmal C. Warke, Siraj Akhtar
Принадлежит: Texas Instruments Inc

In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.

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Номер записи: 11
19-04-2012 дата публикации

Rf bus controller

Номер: US20120093132A1
Автор: Ahmadreza (Reza) Rofougaran
Принадлежит: Broadcom Corp

A radio frequency (RF) bus controller includes an interface and a processing module. The interface is coupled for communicating intra-device RF bus access requests and allocations. The processing module is coupled to receive an access request to an RF bus via the interface; determine RF bus resource availability; and when sufficient RF bus resources are available to fulfill the access request, allocate, via the interface, at least one RF bus resource in response to the access request.

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Номер записи: 12
31-05-2012 дата публикации

Radiofrequency amplifier

Номер: US20120133442A1
Автор: Igor Blednov
Принадлежит: NXP BV

An integrated radiofrequency amplifier with an operational frequency includes first and second Doherty amplifiers each having a main device, and a peak device connected at respective inputs and outputs by respective phase shift elements configured to provide a 90 degree phase shift at the operational frequency. An input of the amplifier is connected to the input of the main device of the first Doherty amplifier, an output of the amplifier is connected to the outputs of the peak devices of the first and second Doherty amplifiers and the input of the peak device of the first Doherty amplifier is connected to the input of the main device of the second Doherty amplifier by a phase shift element providing a 90 degree phase shift at the operational frequency.

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Номер записи: 13
21-06-2012 дата публикации

Integrated millimeter wave transceiver

Номер: US20120154238A1
Автор: Jean-François Carpentier, Patrice Garcia, Pierre Busson, Pierre Dautriche, Sebastien Pruvost
Принадлежит: STMICROELECTRONICS SA

A millimeter wave transceiver including a plate forming an interposer having its upper surface supporting an interconnection network and having its lower surface intended to be assembled on a printed circuit board by bumps; an integrated circuit chip assembled on the upper surface of the interposer; antennas made of tracks formed on the upper surface of the interposer; and reflectors on the upper surface of the printed circuit board in front of each of the antennas, the effective distance between each antenna and the reflector plate being on the order of one quarter of the wavelength, taking into account the dielectric constants of the interposed materials.

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Номер записи: 14
28-06-2012 дата публикации

Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution Layer

Номер: US20120161279A1
Автор: Kai Liu, KANG Chen, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die.

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Номер записи: 15
05-07-2012 дата публикации

Rf identification device with near-field-coupled antenna

Номер: US20120171953A1
Автор: Alberto Pagani, Alessandro Finocchiaro, Giovanni Girlando, Giuseppe Ferla, Giuseppe Palmisano
Принадлежит: STMICROELECTRONICS SRL

An embodiment of a RF identification device is formed by a tag and by a reader. The tag is formed by a processing circuit and a first antenna, which has the function both of transmitting and of receiving data. The reader is formed by a control circuit and by a second antenna, which has the function both of transmitting and of receiving data. The processing circuit is formed by a resonance capacitor, a modulator, a rectifier circuit, a charge-pump circuit and a detection circuit. The antenna of the tag and the processing circuit are integrated in a single structure in completely monolithic form. The first antenna has terminals connected to the input of the rectifier circuit, the output of which is connected to the charge-pump circuit. The charge-pump circuit has an output connected to the detection circuit.

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Номер записи: 16
26-07-2012 дата публикации

Integrated structures of high performance active devices and passive devices

Номер: US20120192139A1
Автор: Anthony K. Stamper, Daniel S. Vanslette, Robert M. Rassel
Принадлежит: International Business Machines Corp

Integrated structures having high performance CMOS active devices mounted on passive devices are provided. The structure includes an integrated passive device chip having a plurality of through wafer vias, mounted to a ground plane. The structure further includes at least one CMOS device mounted on the integrated passive device chip using flip chip technology and being grounded to the ground plane through the through wafer vias of the integrated passive device chip.

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Номер записи: 17
23-08-2012 дата публикации

Microwave unit and method therefore

Номер: US20120211487A1
Автор: Bengt Madeberg, Leif Bergstedt
Принадлежит: Huawei Technologies Co Ltd

A microwave unit comprising a motherboard and a package adapted to be assembled automatically in, e.g., a Surface Mounted Device, SMD, machine is disclosed. The microwave unit preferably comprises a connecting component interconnecting the motherboard and the package, and operable to make the signal ways on a same level at both the motherboard and at the package. Furthermore, the microwave unit preferably comprises a micro-strip adapted soldering tag for soldering on two sides.

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Номер записи: 18
30-08-2012 дата публикации

Vertical ballast technology for power hbt device

Номер: US20120218047A1
Автор: Julio Costa, Michael Carroll
Принадлежит: RF Micro Devices Inc

Power amplification devices are disclosed having a vertical ballast configuration to prevent thermal runaway in at least one stack of bipolar transistors formed on a semiconductor substrate. To provide a negative feedback to prevent thermal runaway in the bipolar transistors, a conductive layer is formed over and coupled to the stack. A resistivity of the conductive layer provides an effective resistance that prevents thermal runaway in the bipolar transistors. The vertical placement of the conductive layer allows for vertical heat dissipation and thus provides ballasting without concentrating heat.

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Номер записи: 19
06-09-2012 дата публикации

System and method for physically detecting counterfeit electronics

Номер: US20120226463A1
Автор: Jason Galyardt, Stephen Dorn Freeman, Walter J. Keller, III
Принадлежит: Nokomis Inc

A system for inspecting or screening electrically powered device includes a signal generator inputting a preselected signal into the electrically powered device. There is also an antenna array positioned at a pre-determined distance above the electrically powered device. Apparatus collects RF energy emitted by the electrically powered device in response to input of said preselected signal. The signature of the collected RF energy is compared with an RF energy signature of a genuine part. The comparison determines one of a genuine or a counterfeit condition of the electrically powered device.

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Номер записи: 20
27-09-2012 дата публикации

Magnetic integration double-ended converter

Номер: US20120241959A1
Автор: Leif Bergstedt
Принадлежит: Huawei Technologies Co Ltd

The present invention relates to a method of bonding a chip to an external electric circuit. The conductors of the external electric circuit for connection to the chip are formed with physical extensions and the chip is directly bonded to these extensions. The invention also relates to an electric device comprising at least one chip and an external electric circuit. The chip is directly bonded to physical extensions of conductors of the external electric circuit.

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Номер записи: 21
04-10-2012 дата публикации

Integrated circuit package including miniature antenna

Номер: US20120249380A1
Автор: Carles Puente Baliarda, Carmen Borja Borau, Jaume Anguera Pros, Jordi Soler Castany
Принадлежит: Fractus SA

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna.

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Номер записи: 22
11-10-2012 дата публикации

On-Chip RF Shields with Backside Redistribution Lines

Номер: US20120258594A1
Автор: Gottfried Beer, Hans-Joachim Barth, Heinrich Koerner, Jens Pohl
Принадлежит: Individual

Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.

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Номер записи: 23
25-10-2012 дата публикации

Impedance matching arrangement for amplifier having split shunt capacitor and amplifier including the same

Номер: US20120268210A1
Автор: Kohei Fujii
Принадлежит: Avago Technologies Wireless IP Singapore Pte Ltd

An amplifier having an operating frequency includes: an input port and an output port; three gain elements, each having an input terminal and an output terminal; an input matching network; and an output matching network. The input matching network includes: a first microstrip line which is connected to the input port and is an inductor at the operating frequency; a second microstrip line extending between the input terminals of the three gain elements; and a first split shunt capacitor connecting the first microstrip line to the second microstrip line. The output matching network includes: a third microstrip line which is connected to the output port and is an inductor at the operating frequency; a fourth microstrip line extending between the output terminals of the three gain elements; and a second split shunt capacitor connecting the third microstrip line to the fourth microstrip line.

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Номер записи: 24
08-11-2012 дата публикации

Processing Signals by Couplers Embedded in an Integrated Circuit Package

Номер: US20120280763A1
Автор: Ahmadreza Rofougaran
Принадлежит: Broadcom Corp

Methods and systems for processing signals via directional couplers embedded in a package are disclosed and may include generating via a directional coupler, one or more output RF signals that may be proportional to a received RF signal. The directional coupler may be integrated in a multi-layer package. The generated RE signal may be processed by an integrated circuit electrically coupled to the multi-layer package. The directional coupler may include quarter wavelength transmission lines, which may include microstrip or coplanar structures. The directional coupler may be electrically coupled to one or more variable capacitances in the integrated circuit. The variable capacitance may include CMOS devices in the integrated circuit. The directional coupler may include discrete devices, which may be surface mount devices coupled to the multi-layer package or may be devices integrated in the integrated circuit. The integrated circuit may be flip-chip bonded to the multi-layer package.

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Номер записи: 25
15-11-2012 дата публикации

Apparatus and methods for electronic amplification

Номер: US20120286878A1
Автор: Alan W. Ake, David Dening
Принадлежит: Skyworks Solutions Inc

Apparatus and methods for electronic amplification are disclosed herein. In certain implementations, an amplifier is provided for amplifying a RF signal, and the amplifier includes a first transistor and a second transistor electrically connected in a Darlington configuration. The first and second transistors can be, for example, bipolar or field effect transistors and the first transistor can amplify an input signal and provide the amplified input signal to the second transistor. The first and second transistors are electrically connected to a power low node such as a ground node through first and second bias circuits, respectively. In certain implementations, the first transistor includes an inductor disposed in the path from the first transistor to the power low voltage. By including the inductor in the path from the first transistor to the ground node, the third order distortion of the amplifier can be improved.

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Номер записи: 26
29-11-2012 дата публикации

Semiconductor device

Номер: US20120299178A1
Автор: Ko Kanaya, Yoshihiro Tsukahara
Принадлежит: Mitsubishi Electric Corp

A semiconductor device includes: a main body chip; a circuit pattern on a front surface of the main body chip and including a first pad; a cap chip including a first recess in a front surface of the cap chip and a second recess in a back surface of the cap chip, the cap chip being joined to the main body chip with the first recess facing the circuit pattern; a second pad on a bottom surface of the first recess of the cap chip; a first metallic member inlaid in the second recess of the cap chip; a first through electrode electrically connecting the second pad to the first metallic member through the cap chip; and a bump electrically connecting the first pad to the second pad.

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Номер записи: 27
27-12-2012 дата публикации

Through wafer vias and method of making same

Номер: US20120329219A1
Автор: Alvin Jose Joseph, Anthony Kendall Stamper, Hanyi Ding
Принадлежит: International Business Machines Corp

A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

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Номер записи: 28
10-01-2013 дата публикации

Thermal enhanced package

Номер: US20130011964A1
Автор: Chenglin Liu, Shiann-Ming Liou
Принадлежит: MARVELL WORLD TRADE LTD

A method of manufacturing an integrated circuit package. The method includes attaching a first surface of a semiconductor die to a thermally and/or electrically conductive substrate, forming a plurality of die connectors on a second surface of the semiconductor die, and encapsulating the semiconductor die and the plurality of die connectors in an encapsulant material. The method also includes removing a portion of the encapsulant material to expose one or more of the plurality of die connectors, thereby forming a routing surface. The method further includes forming a plurality of conductive traces on the routing surface. Each of the plurality of conductive traces is characterized by a first portion in electrical communication with one of the plurality of die connectors and a second portion in electrical communication with a package connector.

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Номер записи: 29
14-02-2013 дата публикации

Fabrication method of packaging substrate having through-holed interposer embedded therein

Номер: US20130040427A1
Автор: Dyi-chung Hu, Tzyy-Jang Tseng, Yu-Shan Hu
Принадлежит: Unimicron Technology Corp

A packaging substrate having a through-holed interposer embedded therein and a fabrication method of the packaging substrate are provided, where the packaging substrate includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer.

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Номер записи: 30
28-02-2013 дата публикации

Semiconductor Device and Method of Manufacturing a Semiconductor Device Including Grinding Steps

Номер: US20130049205A1
Автор: David O'Sullivan, Klaus Reingruber, Thorsten Meyer
Принадлежит: Intel Mobile Communications GmbH

A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.

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Номер записи: 31
07-03-2013 дата публикации

Semiconductor device

Номер: US20130056730A1
Автор: Satoshi Goto, Satoshi Sakurai, Toru Fujioka
Принадлежит: Individual

A technique capable of promoting miniaturization of an RF power module used in a mobile phone etc. is provided. A directional coupler is formed inside a semiconductor chip in which an amplification part of the RF power module is formed. A sub-line of the directional coupler is formed in the same layer as a drain wire coupled to the drain region of an LDMOSFET, which will serve as the amplification part of the semiconductor chip. Due to this, the predetermined drain wire is used as a main line and the directional coupler is configured by a sub-line arranged in parallel to the main line via an insulating film, together with the main line.

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Номер записи: 32
04-04-2013 дата публикации

Semiconductor package including an integrated waveguide

Номер: US20130082379A1
Автор: Ahmadreza Rofougaran, Arya Reza Behzad, Jesus Alfonso Castaneda, Michael BOERS, Sam Ziqun Zhao
Принадлежит: Broadcom Corp

Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.

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Номер записи: 33
18-04-2013 дата публикации

Packaging structure and method of fabricating the same

Номер: US20130093629A1
Автор: Chao-Ya Yang, Chih-Hsien Chiu, Tsung-Hsien Tsai
Принадлежит: Siliconware Precision Industries Co Ltd

A packaging structure and a method of fabricating the same are provided. The packaging structure includes a substrate, first packaging element disposed on the substrate, a second packaging element disposed on the substrate and spaced apart from the first packaging element, a first antenna disposed on the first packaging element, and a metal layer formed on the second packaging element. The installation of the metal layer and the antenna enhances the electromagnetic shielding effect.

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Номер записи: 34
25-04-2013 дата публикации

Antenna-printed circuit board package

Номер: US20130099006A1
Автор: ALEXANDER Goudelev, Kwang-Hyun Baek, Won-Bin Hong, Young-Hwan Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An antenna-printed circuit board (PCB) package is provided. The antenna-PCB package includes a PCB; an antenna portion formed on an upper surface of the PCB and inside the PCB; and a radio frequency integrated circuit (RFIC) chip bonded to a lower surface of the PCB.

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Номер записи: 35
25-04-2013 дата публикации

Semiconductor device and fabrication method therefore

Номер: US20130100318A1
Автор: Junji Tanaka, Kouichi Meguro, Masanori Onodera
Принадлежит: SPANSION LLC

Various embodiments of the present invention include a semiconductor device and a fabrication method therefore, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefore, in which downsizing and cost reduction can be realized.

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Номер записи: 36
30-05-2013 дата публикации

Interposer and semiconductor package with noise suppression features

Номер: US20130134553A1
Автор: Chewn-Pu Jou, Feng Wei KUO, Huan-Neng CHEN, Hui Yu Lee, Yen-Jen Chen, Yu-Ling Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.

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Номер записи: 37
30-05-2013 дата публикации

Structure for High-Speed Signal Integrity in Semiconductor Package with Single-Metal-Layer Substrate

Номер: US20130134579A1
Автор: Gregory E. Howard, Marie-Solange Anne Milleron, Matthew D. Romig, Souvik Mukherjee
Принадлежит: Texas Instruments Inc

A semiconductor chip ( 101 ) with bond pads ( 110 ) on a substrate ( 103 ) with rows and columns of regularly pitched metal contact pads ( 131 ). A zone comprises a first pair ( 131 a, 131 b ) and a parallel second pair ( 131 c, 131 d ) of contact pads, and a single contact pad ( 131 e ) for ground potential; staggered pairs of stitch pads ( 133 ) connected to respective pairs of adjacent contact pads by parallel and equal-length traces ( 132 a, 132 b , etc.). Parallel and equal-length bonding wires ( 120 a, 120 b , etc.) connect bond pad pairs to stitch pad pairs, forming differential pairs of parallel and equal-length conductor lines. Two differential pairs in parallel and symmetrical position form a transmitter/receiver cell for conducting high-frequency signals.

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Номер записи: 38
06-06-2013 дата публикации

Wireless ic device

Номер: US20130140369A1
Автор: Masahiro Ozawa, Yuya DOKAI
Принадлежит: Murata Manufacturing Co Ltd

A wireless IC device that improves radiation gain without increasing substrate size and easily adjusts impedance, includes a multilayer substrate including laminated base layers. On a side of an upper or first main surface of the multilayer substrate, a wireless IC element is arranged to process a high-frequency signal. On a side of a lower or second main surface of the multilayer substrate, a first radiator is provided and is coupled to the wireless IC element via a feeding circuit including first interlayer conductors. On the side of the first main surface, a second radiator is provided and is coupled to the first radiator via second interlayer conductors.

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Номер записи: 39
20-06-2013 дата публикации

Integrated circuit comprising an integrated transformer of the "balun" type with several input and output channels

Номер: US20130157587A1
Автор: Christophe Arricastres, Denis Pache, Floria Blanchet
Принадлежит: STMICROELECTRONICS SA

An integrated circuit includes an integrated transformer of the balanced-to-unbalanced type with N channels, wherein N is greater than 2. The integrated transformer includes, on a substrate, N inductive circuits that are mutually inductively coupled, and respectively associated with N channels.

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Номер записи: 40
27-06-2013 дата публикации

Semiconductor device

Номер: US20130163206A1
Автор: Narue Kobayashi, Tomoharu Fujii, Yukiharu Takeuchi
Принадлежит: Shinko Electric Industries Co Ltd

A semiconductor device includes a structure in which a semiconductor element (chip) is mounted in a cavity formed in a wiring board with an adhesive interposed between the chip and a bottom surface of the cavity, and electrode terminals of the chip are connected via wires to wiring portions formed on the board around the cavity. The chip is mounted in close contact with a side wall of the cavity, the side wall being near a region where a wiring for higher frequency compared with other wirings within the wiring portion is formed. A recessed portion is provided in a region of the bottom surface of the cavity, and a thermal via extending from the bottom surface of the recessed to the outside of the board is provided, the region being near a portion where the chip is in close contact.

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Номер записи: 41
27-06-2013 дата публикации

Circuit substrate

Номер: US20130163212A1
Автор: Gohki NISHIMURA, Naoyuki Tasaka, Sachiko Tanaka
Принадлежит: TAIYO YUDEN CO LTD

A circuit substrate includes: a laminate substrate in which a conductive layer and an insulating layer are laminated; a filter chip that has an acoustic wave filter and is provided inside of the laminate substrate; and an active component that is provided on a surface of the laminate substrate and is connected with the filter chip, at least a part of the active component overlapping with a projected region that is a region of the filter chip projected in a thickness direction of the laminate substrate.

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Номер записи: 42
01-08-2013 дата публикации

Devices and methods related to electrostatic discharge-protected cmos switches

Номер: US20130194158A1
Автор: Ying-Kuang Chen
Принадлежит: Skyworks Solutions Inc

Disclosed are devices and methods related to a CMOS switch for radio-frequency (RF) applications. In some embodiments, the switch can be configured to include a resistive body-floating circuit to provide improved power handling capability. The switch can further include an electrostatic discharge (ESD) protection circuit disposed relative to the switch to provide ESD protection for the switch. Such a switch can be implemented for different switching applications in wireless devices such as cell phones, including band-selection switching and transmit/receive switching.

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Номер записи: 43
01-08-2013 дата публикации

Transmission line transition having vertical structure and single chip package using land grip array coupling

Номер: US20130194754A1
Автор: Dong-Hyun Lee, Dong-Yun Jung, Jei-Young Lee, Ji-Hoon Kim, Jung-han Choi, Sung-Tae Choi, Young-Hwan Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An apparatus for a single chip package using Land Grid Array (LGA) coupling is provided. The apparatus includes a multi-layer substrate, at least one integrated circuit chip, and a Printed Circuit Board (PCB). The a multi-layer substrate has at least one substrate layer, has at least one first chip region and at least one second chip region in a lowermost substrate layer, configures a transmission line transition of a vertical structure for transmitting a signal from at least one integrated circuit chip coupled in the first chip region in a coaxial shape or in a form of a Co-Planar Waveguide guide (CPW), and has an LGP coupling pad for connecting with a Printed Circuit Board (PCB) in the lowermost layer. The at least one integrated circuit chip is coupled in the first chip region and the second chip region. The PCB is connected with the multi-layer substrate using the LGA coupling via the LGA coupling pad.

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Номер записи: 44
29-08-2013 дата публикации

Semiconductor package, and information processing apparatus and storage device including the semiconductor packages

Номер: US20130222401A1
Автор: Keiju YAMADA, Koh Hashimoto, Koji Akita, Takayoshi Ito, Yukako Tsutsumi
Принадлежит: Toshiba Corp

According to the embodiments, a semiconductor package includes a semiconductor chip, a first conductive layer, a second conductive layer, and a power feeder. The semiconductor chip is provided on a substrate, is sealed with a resin, and contains a transmission/reception circuit. The first conductive layer is grounded and covers a first region on a surface of the resin. The second conductive layer is not grounded and covers a second region on the surface of the resin other than the first region. A power feeder electrically connects the semiconductor chip to the second conductive layer.

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Номер записи: 45
03-10-2013 дата публикации

Stacked module

Номер: US20130257565A1
Автор: Satoshi Masuda
Принадлежит: Fujitsu Ltd

A stacked module includes a first multilayer substrate including an opening having a stepwise wall face, and a first transmission line including a first grounding conductor layer, a second multilayer substrate supported on a stepped portion of the stepwise wall face and including a second transmission line including a second grounding conductor layer, a first chip mounted on a bottom of the opening and coupled to a third transmission line provided on the first multilayer substrate, and a second chip mounted on the front face of the second multilayer substrate and coupled to the second transmission line. A face to which the second grounding conductor layer or a fourth grounding conductor layer coupled thereto is exposed is joined to the stepped portion to which the first grounding conductor layer or a third grounding conductor layer coupled thereto is exposed, and the first and second grounding conductor layers are coupled.

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Номер записи: 46
03-10-2013 дата публикации

Power recovery circuit based on partial standing waves

Номер: US20130260708A1
Автор: Ahmadreza Rofougaran
Принадлежит: Broadcom Corp

A power recovery system includes a transmission line that is coupled to transfer an RF signal received via an antenna. The RF signal generates a partial standing wave in the transmission line and the transmission line has at least one standing wave anti-node. A power recovery circuit converts an anti-node signal from the at least one standing wave anti-node to a power signal.

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Номер записи: 47
10-10-2013 дата публикации

Interchip communication using a dielectric waveguide

Номер: US20130265732A1
Автор: Baher S. Haroun, Hassan Ali, Juan A. Herbsommer, Marco Corsi, Robert F. Payne
Принадлежит: Texas Instruments Inc

An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.

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Номер записи: 48
10-10-2013 дата публикации

Interchip communication using an embedded dielectric waveguide

Номер: US20130265733A1
Автор: Baher S. Haroun, Hassan Ali, Juan A. Herbsommer, Marco Corsi, Robert F. Payne
Принадлежит: Texas Instruments Inc

An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.

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Номер записи: 49
24-10-2013 дата публикации

Dielectric conduits for ehf communications

Номер: US20130278360A1
Автор: Emilio Sovero, Gary D. McCormack, Ian A. Kyles, Mau-Chung Frank Chang, Yanghyo Kim
Принадлежит: Keyssa Inc

Dielectric conduits for the propagation of electromagnetic EHF signals include an elongate body of a dielectric material extending continuously along a longitudinal axis between a first terminus and a second terminus. At each point along the longitudinal axis, an orthogonal cross-section of the elongate body has a first dimension along a major axis of the cross-section, where the major axis extends along the largest dimension of the cross-section. The orthogonal cross-section also has a second dimension along a minor axis of the cross-section, where the minor axis extends along a widest dimension of the cross-section that is at a right angle to the major axis. For each cross-section of the elongate body, the first dimension is greater than the wavelength of the electromagnetic EHF signals and the second dimension is less than the wavelength of the electromagnetic EHF signals.

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Номер записи: 50
07-11-2013 дата публикации

Interlayer communications for 3d integrated circuit stack

Номер: US20130293292A1
Автор: Andre Schaefer, Guido Droege, Niklas Linkewitsch
Принадлежит: Intel Corp

Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.

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Номер записи: 51
28-11-2013 дата публикации

Multi-stacked bbul package

Номер: US20130313727A1
Автор: Eng Huat Goh, Hoay Tien Teoh
Принадлежит: Intel Corp

A method including forming a first portion of a build-up carrier on at least one first die, the at least one first die; coupling at least one second die to the first portion of the build-up carrier, the at least one second die separated from the first die by the at least one layer of conductive material disposed between layers of dielectric material; and after coupling the at least one second die to the first portion of the build-up carrier, forming a second portion of the build-up carrier on the at least one second die. An apparatus including a build-up carrier including including alternating layers of conductive material and dielectric material and at least two dice therein in different planes of the build-up carrier.

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Номер записи: 52
05-12-2013 дата публикации

Mimo antenna device, antenna and antenna package

Номер: US20130321234A1
Автор: Ken-Huang Lin, Tzu-Chun Tang, Tzyy-Sheng Horng
Принадлежит: National Sun Yat Sen University

A multi-input and multi-output antenna device is disclosed. The MIMO antenna device comprises two antennas symmetrically disposed on a substrate. Each antenna comprises a T-shaped feeding unit, a radiation unit and a ground unit. The T-shaped feeding unit and the radiation unit are disposed on a first surface of the substrate. The T-shaped feeding unit forms a strip portion and a top portion. The radiation unit has first and second ends. The radiation unit extends from the first end to the second end to form a rectangular region and a spacing. The first end extends parallel to the top portion. The ground unit is disposed along two sides of the strip portion and electrically coupled to the second end. The two strip portions of the two T-shaped feeding units are parallel to and aligned with each other. The two ground units are electrically connected to each other.

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Номер записи: 53
26-12-2013 дата публикации

Process-compensated hbt power amplifier bias circuits and methods

Номер: US20130344825A1
Автор: David Steven Ripley, Hongxiao Shao, Matthew Thomas Ozalas, Peter J. Zampardi, JR., Philip John Lehtola, Tin Myint Ko
Принадлежит: Skyworks Solutions Inc

The present disclosure relates to a system for biasing a power amplifier. The system can include a first die that includes a power amplifier circuit and a passive component having an electrical property that depends on one or more conditions of the first die. Further, the system can include a second die including a bias signal generating circuit that is configured to generate a bias signal based at least in part on measurement of the electrical property of the passive component of the first die.

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Номер записи: 54
13-02-2014 дата публикации

Method and Apparatus for a Clock and Signal Distribution Network for a 60 GHz Transmitter System

Номер: US20140043104A1
Автор: Jiashu Chen
Принадлежит: Tensorcom Inc

Herein is presented, a low power on-die 60 GHz distribution network for a beamforming system that can be scaled as the number of transmitters increases. The transmission line based power splitters and quadrature hybrids whose size would be proportional to a quarter wavelength (˜600 μm) if formed using transmission lines are instead constructed by inductors/capacitors and reduce the area by more than 80%. An input in-phase I clock and an input quadrature Q clock are combined into a single composite clock waveform locking the phase relation between the in-phase I clock and quadrature Q clock. The composite clock is transferred over a single transmission line formed using a Co-planar Waveguide (CPW) coupling the source and destination locations over the surface of a die. Once the individuals the in-phase I and quadrature Q clocks are required, they can be generated at the destination from the composite clock waveform.

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Номер записи: 55
27-03-2014 дата публикации

Noise attenuation wall

Номер: US20140084477A1
Автор: Christophe Erdmann, Donnacha Lowney, Edward Cullen
Принадлежит: Xilinx Inc

An embodiment of an apparatus is disclosed. For this embodiment of the apparatus, an interposer has first vias. First interconnects and second interconnects respectively are coupled on opposite surfaces of the interposer. A first portion of the first interconnects and a second portion of the first interconnects are spaced apart from one another defining an isolation region between them. A substrate has second vias. Third interconnects and the second interconnects are respectively coupled on opposite surfaces of the package substrate. A first portion of the first vias and a first portion of the second vias are both in the isolation region and are coupled to one another with a first portion of the second interconnects.

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Номер записи: 56
27-03-2014 дата публикации

Efficient Linear Integrated Power Amplifier Incorporating Low And High Power Operating Modes

Номер: US20140085006A1
Автор: Alexander Mostov, Sergey Anderson, Udi Suissa
Принадлежит: DSP Group Israel Ltd

A novel and useful radio frequency (RF) front end module (FEM) circuit that provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard CMOS processes. The FEM circuit includes a power amplifier made up of one or more sub-amplifiers having high and low power circuits and whose outputs are combined to yield the total desired power gain. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provide efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers.

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Номер записи: 57
10-04-2014 дата публикации

Pie Shape Phased Array Antenna Design

Номер: US20140097990A1
Автор: Zaid Aboush
Принадлежит: Cambridge Silicon Radio Ltd

A radially segmented antenna design is described. In an embodiment, the radially segmented antenna is formed from multiple patches which are arranged in a ring around the central point of the radially segmented antenna. Each patch is shaped to form a segment of the ring and is separated from the two adjacent patches. In operation, alternate patches in the ring may be used for transmitting and the remaining patches may be terminated in an open circuit or may be used for receiving. Alternatively, all the patches in the ring may be used for transmitting or receiving. In some examples, there may be more than one concentric ring of patches within the radially segmented antenna and the additional rings may be located on the same face of the antenna as the first ring of patches, or on the opposite face of the antenna.

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Номер записи: 58
01-01-2015 дата публикации

DE-POP ON-DEVICE DECOUPLING FOR BGA

Номер: US20150001716A1
Автор: BROWN Paul James, Chan Alex
Принадлежит:

Embodiments of the invention place surface-mount devices such as decoupling capacitors, resistors or other devices directly on the underside of a ball grid array (BGA) electronic integrated circuit (EIC) package, in place of de-populated BGA pads. 1. An electronic integrated circuit (EIC) package comprising:an EIC substrate;an array of ball grid array (BGA) pads on a first side of said EIC substrate, arranged in a grid pattern of rows and columns; andcontact pads on said first side of said EIC substrate to accommodate electrical connection of a surface-mount device, wherein said surface-mount device occupies a grid location of said grid pattern in place of one or more BGA pads.2. The EIC package of claim 1 , wherein said contact pads comprise at least two adjacent contact pads.3. The EIC package of claim 2 , wherein each of the contact pads is connected to an adjacent BGA pad by a conductor on said first side of said EIC substrate.4. The EIC package of claim 1 , wherein said surface-mount device comprises a two-port device.5. The EIC package of claim 4 , wherein said surface-mount device comprises a decoupling capacitor.6. The EIC package of claim 1 , wherein said surface-mount device is selected from a set of a capacitor claim 1 , a resistor claim 1 , an inductor claim 1 , a diode claim 1 , a transistor claim 1 , a capacitor array claim 1 , and a resistor-capacitor circuit.7. The EIC package of claim 1 , wherein said BGA grid comprises a pitch of between about 0.4 mm×0.4 mm and about 1.27 mm×1.27 mm.8. The EIC package of claim 7 , wherein said BGA grid comprises an irregular pitch.9. A computer-aided design tool for accommodating a surface-mount device on a first surface of a ball grid array (BGA) electronic integrated circuit (EIC) package claim 7 , said tool comprising:a design tool configured to identify, in an EIC configuration of BGA pads in a grid pattern on said first side of said EIC package, at least two contact pads for forming directly on said first ...

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Номер записи: 59
01-01-2015 дата публикации

Semiconductor package having wire bond wall to reduce coupling

Номер: US20150002226A1
Автор: Margaret Szymanowski, Paul Hart, Shun Meen Kuo
Принадлежит: FREESCALE SEMICONDUCTOR INC

A system and method for a package including a wire bond wall to reduce coupling is presented. The package includes a substrate, and a first circuit on the substrate. The first circuit includes a first electrical device, a second electrical device, and a first wire bond array interconnecting the first electrical device and the second electrical device. The package includes a second circuit on the substrate adjacent to the first circuit, the second circuit includes a second wire bond array interconnecting a third electrical device and a fourth electrical device. The package includes a wire bond wall including a plurality of wire bonds over the substrate between the first circuit and the second circuit. The wire bond wall is configured to reduce an electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.

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Номер записи: 60
06-01-2022 дата публикации

Semiconductor device package and semiconductor device

Номер: US20220005751A1
Автор: Kaname Ebihara, Shingo Inoue
Принадлежит: Sumitomo Electric Device Innovations Inc

A semiconductor device package is disclosed. The package according to one example includes a base having a main surface made of a metal, a dielectric side wall having a bottom surface facing the main surface, a joining material containing silver (Ag) and joining the main surface of the base and the bottom surface of the side wall to each other, a lead made of a metal joined to an upper surface of the side wall on a side opposite to the bottom surface, and a conductive layer not containing silver (Ag). The conductive layer is provided between the bottom surface and the upper surface of the side wall at a position overlapping the lead when viewed from a normal direction of the main surface. The conductive layer is electrically connected to the joining material, extends along the bottom surface, and is exposed from a lateral surface of the side wall.

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Номер записи: 61
06-01-2022 дата публикации

INTERPOSER

Номер: US20220005757A1
Автор: AN Youngjun, LEE Gilseon, Oh Changwoo, SHIN Jungkyun
Принадлежит: AMOSENSE CO., LTD

The present disclosure relates to an interposer. The interposer includes: a support body formed of a ceramic material, a connection electrode configured to the top surface and bottom surface of the support body, and a shielding member disposed at an outer surface of the support body. At least a part of the support body is disposed along the edge of a substrate, and electrically connects the substrate and a substrate. The interposer is formed of a ceramic material and thus make it possible to implement a fine pattern, to improve dimensional stability by preventing the bending deformation of ceramic green sheets, and to raise the reliability of signal transmission. Therefore, the interposer can contribute to implementing high performance of an electronic device and reducing the size of the electronic device. 1. An interposer comprising:a support body including a top surface and a bottom surface, at least a part of the support body disposed along the edge of a substrate;a connection electrode configured to connect the top surface and bottom surface of the support body; anda shielding member disposed at an outer surface of the support body.2. The interposer of claim 1 , wherein the support body is disposed along the edge of the substrate claim 1 , as one part or a combination of two or more parts claim 1 , selected from a group including:a straight part disposed in a straight line shape along a part of the edge of the substrate;a inclined part disposed in an inclined shape so as to be adjacent to a part of the edge of the substrate or a corner of the substrate; anda curved part disposed in a round shape.3. The interposer of claim 1 , wherein the support body is formed of a ceramic material.4. The interposer of claim 1 , wherein the connection electrode is formed as a conductive material filled in a via hole formed through the support body in a thickness direction thereof to connect the top and bottom surfaces of the support body.5. The interposer of claim 4 , wherein ...

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Номер записи: 62
06-01-2022 дата публикации

SEMICONDUCTOR PACKAGES AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGES

Номер: US20220006173A1
Автор: Kim Jingu, Lee Sangkyu, Lee Yongkoon
Принадлежит:

A semiconductor package includes a redistribution wiring layer having redistribution wirings, a semiconductor chip on the redistribution wiring layer, a frame on the redistribution wiring layer, the frame surrounding the semiconductor chip, and the frame having core connection wirings electrically connected to the redistribution wirings, and an antenna structure on the frame, the antenna structure including a ground pattern layer, a first antenna insulation layer, a radiator pattern layer, a second antenna insulation layer, and a director pattern layer sequentially stacked on one another. 1. A semiconductor package , comprising:a redistribution wiring layer having redistribution wirings;a semiconductor chip on the redistribution wiring layer;a frame on the redistribution wiring layer, the frame surrounding the semiconductor chip, and the frame having core connection wirings electrically connected to the redistribution wirings; andan antenna structure on the frame, the antenna structure including a ground pattern layer, a first antenna insulation layer, a radiator pattern layer, a second antenna insulation layer, and a director pattern layer sequentially stacked on one another.2. The semiconductor package as claimed in claim 1 , wherein the first antenna insulation layer has a first thermal expansion coefficient claim 1 , and the second antenna insulation layer has a second thermal expansion coefficient smaller than the first thermal expansion coefficient.31314. The semiconductor package as claimed in claim 2 , wherein the second thermal expansion coefficient is within a range of / to / of the first thermal expansion coefficient.4. The semiconductor package as claimed in claim 2 , wherein the second thermal expansion coefficient of the second antenna insulation layer is a same as a thermal expansion coefficient of the frame.5. The semiconductor package as claimed in claim 1 , wherein the first antenna insulation layer has a first thickness claim 1 , and the second ...

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Номер записи: 63
05-01-2017 дата публикации

Electronic apparatus operable in high frequencies

Номер: US20170005047A1
Автор: Mikoto Nakamura, Takeshi Kawasaki
Принадлежит: Sumitomo Electric Industries Ltd

An electronic apparatus that includes a semiconductor device mounted on an assembly base is disclosed. The semiconductor device includes a transmission line, whose impedance is matched to characteristic impedance, and a pad connected to the transmission line, through which a high frequency signal is supplied to or extracted from the semiconductor device. The pad accompanies a stub line that is concurrently formed with the transmission line and grounded within the semiconductor device. The stub line operates as a short stub that may compensate parasitic capacitance attributed to the pad.

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Номер записи: 64
05-01-2017 дата публикации

BIPOLAR TRANSISTOR HAVING COLLECTOR WITH DOPING SPIKE

Номер: US20170005184A1
Автор: JR. Peter J., Kwok Kai Hay, Zampardi
Принадлежит:

This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at a doping spike in the collector. The doping spike can be disposed relatively near an interface between the collector and the base. For instance, the doping spike can be disposed within half of the thickness of the collector from the interface between the collector and the base. Such bipolar transistors can be implemented, for example, in power amplifiers. 1. A bipolar transistor comprising a collector including a first end and a second end opposite the first end , a sub-collector abutting the second end of the collector , a base abutting the first end of the collector , and an emitter , the collector including a doping spike disposed closer to the first end than to the second end , the doping spike having a thickness of 200 Å or less , the collector also including a doped portion disposed between the doping spike and the base , the bipolar transistor being a single heterojunction bipolar transistor.2. The bipolar transistor of wherein the doping spike extends substantially an entire length of the collector in a direction substantially parallel to a base-collector interface.3. The bipolar transistor of wherein the collector includes a second doped portion disposed between the doping spike and the subcollector claim 2 , the second doped portion comprising a substantially flat doping and extending substantially an entire length of the collector in a direction substantially parallel to a base-collector interface.4. The bipolar transistor of wherein the thickness of the doping spike is substantially equal to 150 Å.5. The bipolar transistor of wherein the thickness of the doping spike is substantially equal to 100 Å.6. The bipolar transistor of wherein the doping spike is disposed at a location that results in approximately a local maximum of BVof the bipolar transistor.7. The bipolar transistor of wherein the doping spike is disposed within about 0.5 μm from a base- ...

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Номер записи: 65
13-01-2022 дата публикации

APPARATUS AND METHOD FOR PROVIDING A SCALABLE BALL GRID ARRAY (BGA) ASSIGNMENT AND A PCB CIRCUIT TRACE BREAKOUT PATTERN FOR RF CHIP INTERFACES

Номер: US20220013442A1
Автор: CHEN Nelly, GOPALAN UPPILI Shrinivas, MAY Michael Randy, SRIBOONLUE Varin, ZHANG Gary Yao
Принадлежит:

A pin map covers a surface area of a layer of a printed circuit board (PCB). The pin map includes a plurality of electrical designations for each pin in the pin map and a plurality of empty spaces within the pin map. Each electrical designation may be assigned to a pin on the pin map. Each electrical designation includes a positive polarity (P+) pin, a negative polarity (P−) pin, or an electrical ground (G) pin. If a space in the pin map does not have an electrical designation, then it may include an empty space/plain portion of the printed circuit board (PCB). The pin map may include a plurality of rows and a first repeating pin polarity pattern. The first repeating pin polarity pattern may include a lane unit tile. The pin map may help couple two circuit elements together that are attached to one layer of a PCB. 1. An apparatus , comprising:a first semiconductor die stacked vertically relative to a layer of a printed circuit board (PCB), the first semiconductor die coupled to the PCB with a ball grid array (BGA);a second semiconductor die stacked vertically relative to the layer of the PCB, the second semiconductor die coupled to the PCB with a BGA;a pin map corresponding to each BGA and covering a surface area of the PCB, the pin map comprising a plurality of electrical designations for each pin in the pin map and a plurality of empty spaces within the pin map; each electrical designation of the plurality of electrical designations on the pin map comprising one of a positive polarity (P+), a negative polarity (P−), or an electrical ground (G);each pin map including a first repeating pin polarity pattern; the first repeating pin polarity pattern comprising a lane unit tile, the lane unit tile having a central region defined by four pin map units, two of the four pin map units comprising two pins corresponding to a signal lane within the PCB.2. The apparatus of claim 1 , wherein the pin map comprises a plurality of square units wherein each square unit represents ...

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Номер записи: 66
05-01-2017 дата публикации

SEMICONDUCTOR SWITCH

Номер: US20170005651A1
Автор: ISHIMARU Atsushi
Принадлежит:

A semiconductor switch includes an insulating film on a semiconductor substrate. A switching circuit is on a first portion of the insulating film. The switching circuit is configured to switch a path of a high-frequency signal. A wiring layer is provided on the insulating film. The wiring layering includes a signal wire and a ground wire. A conductive layer is between the wiring layer and the insulating film. The conductive layer, in some embodiments, includes a first conductive region between the high-frequency wiring and the insulating film and a second conductive region between the grounding wiring and the insulating film. 1. A semiconductor switch , comprising:a semiconductor substrate;an insulating film on the semiconductor substrate;a conductive layer on the insulating film;a wiring layer comprising a first wire and a second wire above the conductive layer, the first wire carrying a high-frequency signal and the second wire connected to ground; anda switching circuit on a first portion of the insulating film, the switching circuit configured to switch a path of the high-frequency signal.2. The semiconductor switch according to claim 1 , wherein the insulating film comprises a buried oxide layer claim 1 , a shallow trench isolation layer claim 1 , and an interlayer dielectric layer.3. The semiconductor switch according to claim 2 , wherein the first portion of the insulating film includes only the buried oxide layer.4. The semiconductor switch according to claim 1 , wherein the conductive layer is connectable to a power supply potential such that an electrical potential of the conductive layer is higher than an electrical potential of the semiconductor substrate.5. The semiconductor switch according to claim 2 , whereinthe interlayer dielectric layer covers the conductive layer, anda first via in the interlayer dielectric layer contacts the conductive layer such that the conductive layer is connectable to the power supply potential through the first via.6. The ...

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Номер записи: 67
05-01-2017 дата публикации

DEVICES AND METHODS RELATED TO HIGH POWER DIODE SWITCHES WITH LOW DC POWER CONSUMPTION

Номер: US20170005693A1
Автор: MORESCHI Stephen Richard, PUENTE Richard Mark, Zhang Shuping
Принадлежит:

Devices and methods are disclosed, related to high power diode switches. In some embodiments, a radio-frequency switch circuit can include a first switchable path implemented between a pole and a first throw, the first switchable path including one or more PIN diodes, and a second switchable path implemented between the pole and a second throw, the second switchable path including one or more PIN diodes. The radio-frequency switch circuit can further include a switchable shunt path implemented between the second throw and a ground, the switchable shunt path including at least one shunt PIN diode and a capacitance between the second throw and the at least one shunt PIN diode. The pole can be an antenna port, and the first and second throws can be transmit and receive ports, respectively. 1. A radio-frequency switch circuit comprising:a first switchable path implemented between a pole and a first throw, the first switchable path including one or more PIN diodes;a second switchable path implemented between the pole and a second throw, the second switchable path including one or more PIN diodes; anda switchable shunt path implemented between the second throw and a ground, the switchable shunt path including at least one shunt PIN diode and a capacitance between the second throw and the at least one shunt PIN diode.2. The radio-frequency switch circuit of wherein the pole is an antenna port.3. The radio-frequency switch circuit of wherein the first throw is a transmit port configured to receive an amplified radio-frequency signal.4. The radio-frequency switch circuit of further comprising an additional switchable shunt path implemented between the transmit port and a ground.5. The radio-frequency switch circuit of wherein the additional switchable shunt path includes at least one shunt PIN diode.6. The radio-frequency switch circuit of further comprising a transmit bias port electrically connected to a node between the first throw and the one or more PIN diodes of the ...

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Номер записи: 68
07-01-2016 дата публикации

Chip-type antenna device and chip structure

Номер: US20160006125A1
Автор: Cheng-Min Yang, Shih-Chi Lai, Tzu-Hsiang Chien
Принадлежит: Auden Techno Corp

A chip structure for mounting on a clearance area of a printed circuit board includes a packaged chip and a monopole coupling antenna. The packaged chip has an insulating body, an electronic component embedded in the insulating body, and a plurality of grounding pads electrically connected to the electronic component. The monopole coupling antenna has a grounding radiating metal and a monopole radiating metal. The packaged chip is electrically connected to the grounding radiating metal by the grounding pads. The monopole radiating metal is disposed on the insulating body and spaced apart from the electronic component and the grounding radiating metal. The monopole radiating metal is configured to couple the grounding radiating metal and the electronic component by using a feeding circuit to connect the packaged chip and the monopole radiating metal and using a grounding circuit to connect the grounding radiating metal and the printed circuit board.

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Номер записи: 69
07-01-2016 дата публикации

HIGH-FREQUENCY MODULE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20160006131A1
Автор: Ishibashi Daijiro, KAWANO Yoichi, MATSUMURA Hiroshi, SUZUKI Toshihide
Принадлежит:

A high-frequency module includes an integrated body including a semiconductor chip and a reflector, the semiconductor and the reflector being integrated by a resin; an antenna provided with a space from the reflector; and a rewiring layer provided on the surface of the integrated body, the rewiring layer including a rewiring line electrically coupling the semiconductor chip to the antenna. Further, a method for manufacturing a high-frequency module, the method includes forming an integrated body by integrating a semiconductor chip with a reflector by a resin; and forming a rewiring layer on the surface of the integrated body, the rewiring layer including a rewiring line electrically coupling the semiconductor chip to an antenna provided with a space from the reflector. 1. A high-frequency module comprising:an integrated body including a semiconductor chip and a reflector, the semiconductor and the reflector being integrated by a resin;an antenna provided with a space from the reflector; anda rewiring layer provided on the surface of the integrated body, the rewiring layer including a rewiring line electrically coupling the semiconductor chip to the antenna.2. The high-frequency module according to claim 1 , whereinthe integrated body includes a distance adjuster configured to adjust a distance between the reflector and the antenna.3. The high-frequency module according to claim 2 , whereinthe distance adjuster is a dielectric layer provided on the antenna side of the reflector.4. The high-frequency module according to claim 1 , whereinthe integrated body includes a dielectric layer that comes into contact with the antenna side of the reflector, the dielectric layer including a surface exposed on the surface of the integrated body.5. The high-frequency module according to claim 3 , whereinthe antenna is provided on the surface of the dielectric layer.6. The high-frequency module according to claim 2 , whereinthe distance adjuster is a protrusion part configured to ...

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Номер записи: 70
04-01-2018 дата публикации

SHIELDED PACKAGE WITH INTEGRATED ANTENNA

Номер: US20180005957A1
Автор: DURNAN Gregory J., Vincent Michael B.
Принадлежит:

A semiconductor structure includes a packaged semiconductor device having at least one device, a conductive pillar, an encapsulant over the at least one device and surrounding the conductive pillar, wherein the conductive pillar extends from a first major surface to a second major surface of the encapsulant, and is exposed at the second major surface and the at least one device is exposed at the first major surface. The packaged device also includes a conductive shield layer on the second major surface of the encapsulant and on minor surfaces of the encapsulant and an isolation region at the second major surface of the encapsulant between the encapsulant and the conductive pillar such that the conductive shield layer is electrically isolated from the conductive pillar. The semiconductor structure also includes a radio-frequency connection structure over and in electrical contact with the conductive pillar at the second major surface of the encapsulant. 1. A semiconductor structure , comprising: at least one device,', 'a conductive pillar, and', 'an encapsulant over the at least one device and surrounding the conductive pillar, wherein the conductive pillar extends from a first major surface of the encapsulant to a second major surface of the encapsulant, opposite the first major surface, and is exposed at the second major surface of the encapsulant and the at least one device is exposed at the first major surface of the encapsulant,', 'a conductive shield layer on the second major surface of the encapsulant and on minor surfaces of the encapsulant, and', 'an isolation region configured to electrically isolate that the conductive shield layer from the conductive pillar; and, 'a packaged semiconductor device havinga radio-frequency (RF) connection structure over and in electrical contact with the conductive pillar at the second major surface of the encapsulant.2. The semiconductor structure of claim 1 , wherein the packaged semiconductor device comprises at least one ...

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Номер записи: 71
04-01-2018 дата публикации

METHODS FOR FORMING SHIELDED RADIO-FREQUENCY MODULES HAVING REDUCED AREA

Номер: US20180005958A1
Автор: Chen Howard E., Read Matthew Sean
Принадлежит:

Shielded radio-frequency (RF) module having reduced area. In some embodiments, a method for fabricating a radio-frequency module includes forming or providing a packaging substrate configured to receive a plurality of components. The method may include mounting one or more devices on the packaging substrate such that the packaging substrate includes a first area associated with mounting of each of the one or more devices. In some embodiments, the method further includes forming a plurality of shielding wirebonds on the packaging substrate to provide RF shielding functionality for one or more regions on the packaging substrate, such that the packaging substrate includes a second area associated with formation of each shielding wirebond, the mounting of each device implemented with respect to a corresponding shielding wirebond such that a portion of the first area associated with the device overlaps at least partially with a portion of the second area associated with the corresponding shielding wirebond. 1. A method for fabricating a radio-frequency module , the method comprising:forming or providing a packaging substrate configured to receive a plurality of components;mounting one or more devices on the packaging substrate such that the packaging substrate includes a first area associated with mounting of each of the one or more devices; andforming a plurality of shielding wirebonds on the packaging substrate to provide RF shielding functionality for one or more regions on the packaging substrate, such that the packaging substrate includes a second area associated with formation of each shielding wirebond, the mounting of each device implemented with respect to a corresponding shielding wirebond such that a portion of the first area associated with the device overlaps at least partially with a portion of the second area associated with the corresponding shielding wirebond.2. The method of further comprising forming each of the shielding wirebonds to have a loop shape ...

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Номер записи: 72
04-01-2018 дата публикации

Integrated Tunable Filter Architecture

Номер: US20180005966A1
Автор: Adamski Jaroslaw, Comfoltey Edward Nicholas, Nobbe Dan William, Smith William R., Wang Jingbo
Принадлежит:

An apparatus and method for a frequency based integrated circuit that selectively filters out unwanted bands or regions of interfering frequencies utilizing one or more tunable notch or bandpass filters or tunable low or high pass filters capable of operating across multiple frequencies and multiple bands in noisy RF environments. The tunable filters are fabricated within the same integrated circuit package as the associated frequency based circuitry, thus minimizing R, L, and C parasitic values, and also allowing residual and other parasitic impedance in the associated circuitry and IC package to be absorbed and compensated. 2. The integrated circuit configuration of claim 1 , wherein at least one tunable filter includes at least one of a tunable notch filter or a tunable bandpass filter.3. The integrated circuit configuration of claim 2 , wherein the tunable notch filter or tunable bandpass filter includes a tunable RLC filter.4. The integrated circuit configuration of claim 3 , wherein the tunable RLC filter includes at least one of a tunable capacitor C and a tunable inductor L.5. The integrated circuit configuration of claim 4 , wherein at least one of the tunable capacitor C or tunable inductor L is digitally tunable.6. The integrated circuit configuration of claim 1 , wherein at least one tunable filter includes at least one of a tunable low pass filter or a tunable high pass filter.7. The integrated circuit configuration of claim 6 , wherein the tunable low pass filter or tunable high pass filter includes a tunable RLC filter.8. The integrated circuit configuration of claim 7 , wherein the tunable RLC filter includes at least one of a tunable capacitor C and a tunable inductor L.9. The integrated circuit configuration of claim 8 , wherein at least one of the tunable capacitor C or tunable inductor L is digitally tunable.10. The integrated circuit configuration of claim 1 , wherein the frequency based circuit is at least one of a radio frequency switch claim ...

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Номер записи: 73
07-01-2021 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20210005535A1
Автор: HANGAI Masatake, SHINJO Shintaro, YAMAGUCHI Yutaro, YAMANAKA Koji
Принадлежит: Mitsubishi Electric Corporation

In a semiconductor device including gate fingers each having a linear shape extending from a feed line, and arranged in areas between drain electrodes and source electrodes, open stubs are connected directly to the feed line. 1. A semiconductor device comprising:a semiconductor substrate;a plurality of drain electrodes, each of the drain electrodes being disposed along one direction on the semiconductor substrate;a plurality of source electrodes, each of the source electrodes being disposed in an area between corresponding adjacent two of the drain electrodes on the semiconductor substrate, and being disposed along the one direction;a feed line being disposed on the semiconductor substrate, and having a band shape extending in the one direction; an input line disposed on the semiconductor substrate;', 'an air bridge connecting the feed line and the input line;, 'a plurality of gate fingers, each of the gate fingers having a linear shape extending from the feed line, and being disposed in an area between two adjacent electrodes on the semiconductor substrate, one of the two adjacent electrodes being a corresponding one of the drain electrodes and the other being a corresponding one of the source electrodes; and'}a plurality of open stubs being disposed on the semiconductor substrate, and having a line length that eliminates a target higher harmonic wave, and each of the open stubs passing under the air bridge and being connected directly to the feed line.2. The semiconductor device according to claim 1 , wherein the open stubs are arranged so as to correspond one-to-one to the gate fingers.3. The semiconductor device according to claim 1 , wherein the open stubs are made from a metallic material identical to that of the gate fingers.4. A semiconductor device comprising:a semiconductor substrate;a plurality of drain electrodes, each of the drain electrodes being disposed along one direction on the semiconductor substrate;a plurality of source electrodes, each of the ...

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Номер записи: 74
03-01-2019 дата публикации

Inductor module

Номер: US20190006076A1
Автор: Hirokazu Yazaki
Принадлежит: Murata Manufacturing Co Ltd

An inductor module includes an insulating flexible substrate including a thermoplastic resin, an IC element included in the flexible substrate, chip capacitors included in the flexible substrate, a chip inductor that includes a magnetic-material body and is located on a first main surface of the flexible substrate, and input and output terminals on a second main surface of the flexible substrate. The IC element may be a switching IC element, the chip inductor may be a choke coil, and the inductor module may be a DC/DC converter module.

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Номер записи: 75
02-01-2020 дата публикации

MICROELECTRONIC ASSEMBLIES HAVING INTERPOSERS

Номер: US20200006235A1
Автор: Aleksov Aleksandar, Swan Johanna M.
Принадлежит: Intel Corporation

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a high bandwidth interconnect, a first interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the first interposer is electrically coupled to the high bandwidth interconnect, and a second interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the second interposer is electrically coupled to the high bandwidth interconnect, and wherein the first interposer is electrically coupled to the second interposer via the high bandwidth interconnect. 1. A microelectronic assembly , comprising:a package substrate having a high bandwidth interconnect;a first interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the first interposer is electrically coupled to the high bandwidth interconnect; anda second interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the second interposer is electrically coupled to the high bandwidth interconnect, and wherein the first interposer is electrically coupled to the second interposer via the high bandwidth interconnect.2. The microelectronic assembly of claim 1 , wherein the high bandwidth interconnect is a waveguide.3. The microelectronic assembly of claim 1 , wherein the high bandwidth circuitry of the first interposer is radio frequency (RF) circuitry.4. The microelectronic assembly of claim 1 , further comprising:a first die having a first surface and an opposing second surface, wherein the first surface of the first die is electrically coupled to a surface of the package substrate and the second surface of the first die is electrically coupled to the first interposer; anda second die having a first surface and an ...

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Номер записи: 76
02-01-2020 дата публикации

Semiconductor Device and Method

Номер: US20200006259A1
Автор: Huang Tzu-Sung, Kuo Hung-Yi, Tsai Hao-Yi, Tseng Ming Hung, Yu Chen-Hua
Принадлежит:

In an embodiment, a device includes: a conductive shield on a first dielectric layer; a second dielectric layer on the first dielectric layer and the conductive shield, the first and second dielectric layers surrounding the conductive shield, the second dielectric layer including: a first portion disposed along an outer periphery of the conductive shield; a second portion extending through a center region of the conductive shield; and a third portion extending through a channel region of the conductive shield, the third portion connecting the first portion to the second portion; a coil on the second dielectric layer, the coil disposed over the conductive shield; an integrated circuit die on the second dielectric layer, the integrated circuit die disposed outside of the coil; and an encapsulant surrounding the coil and the integrated circuit die, top surfaces of the encapsulant, the integrated circuit die, and the coil being level. 1. A device comprising:a first dielectric layer;a conductive shield on the first dielectric layer, the conductive shield comprising a center region and a first channel, the first channel connecting the center region to an outer periphery of the conductive shield;a second dielectric layer on the conductive shield and the first dielectric layer, the second dielectric layer extending through the center region and the first channel of the conductive shield, the second dielectric layer being at least one order of magnitude thicker than the conductive shield;a dummy semiconductor structure disposed on the second dielectric layer, a center of the dummy semiconductor structure overlapping the center region of the conductive shield;a coil on the second dielectric layer, the coil being a continuous copper spiral surrounding the dummy semiconductor structure; andan encapsulant surrounding the coil and the dummy semiconductor structure.2. The device of further comprising:an integrated circuit die on the second dielectric layer, the coil being disposed ...

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Номер записи: 77
02-01-2020 дата публикации

INDUCTOR AND TRANSMISSION LINE WITH AIR GAP

Номер: US20200006261A1
Автор: LIN Kevin
Принадлежит:

An integrated circuit structure comprises one or more sets of first and second conductive lines along a same direction in an interlayer dielectric (ILD), the first and second conductive lines having a width greater than 2 μm. An air gap is in the ILD between the first and second conductive lines, the air gap extending across the ILD to sidewalls of the first and second conductive lines. 1. An integrated circuit structure , comprising:one or more sets of first and second conductive lines along a same direction in an interlayer dielectric (ILD), the first and second conductive lines having a width greater than 2 μm; andan air gap in the ILD between the first and second conductive lines, the air gap extending across the ILD to sidewalls of the first and second conductive lines.2. The integrated circuit structure of claim 1 , wherein the width of the air gap and a distance between the first and second conductive lines is approximately 1 to 10 μm.3. The integrated circuit structure of claim 1 , wherein the air gap includes one or more spacers along at least one top corner of the air gap and at least one sidewall of the first and second conductive lines.4. The integrated circuit structure of claim 3 , wherein the one or more spacers leave an opening in the air gap of approximately 100-300 nm.5. The integrated circuit structure of claim 3 , wherein the air gap includes left and right spacers formed along the sidewalls of the first and second conductive lines claim 3 , respectively claim 3 , where the left and right spacers are coplanar with a top surface of the first and second conductive lines.6. The integrated circuit structure of claim 1 , wherein the air gap is formed as a continuous recess between the first and second conductive lines.7. The integrated circuit structure of claim 1 , wherein the air gap is formed as non-contiguous air gap segments that are spaced apart by the ILD to provide structural support to the sidewalls of the first and second conductive lines.8. ...

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Номер записи: 78
03-01-2019 дата публикации

GUARD BOND WIRES IN AN INTEGRATED CIRCUIT PACKAGE

Номер: US20190006286A1
Автор: Cuoco Vittorio, Van Der Zanden Josephus, VOLKHINE Youri, Walesieniuk Anna, ZHU Yi
Принадлежит:

An integrated circuit package is provided. The integrated circuit package comprises a first and second guard bond wire. The first guard bond wire has a first and second end coupled to ground. The second guard bond wire has a first and second end coupled to ground. The integrated circuit package further comprises a die. The die is mounted between the first and second guard bond wires such that the first and second guard bond wires distort a magnetic field between at least an input terminal and an output terminal of the die. 1. An integrated circuit package , comprising:a first guard bond wire having a first and second end coupled to ground;a second guard bond wire having a first and second end coupled to ground;a die mounted between the first and second guard bond wires such that the first and second guard bond wires distort a magnetic field between at least an input terminal and an output terminal of the die, wherein the die has a surface area with a first side and a second side that is opposite to the first side and at least a portion of the first guard bond wire is aligned with the first side of the die and at least a portion of the second guard bond wire is aligned with the second side of the die; anda flange on which the die is mounted;wherein the at least a portion of the first guard bond wire is aligned with the first side such that the at least a portion of the first bond wire runs parallel to the first side of the die, and wherein the at least a portion of the second guard bond wire is aligned with the second side such that the at least a portion of the second guard bond wire runs parallel to the second side of the die,wherein the first and/or second end of the first guard bond wire is/are coupled to ground through a flange mounted first and/or second capacitor, respectively, and the first and/or second end of the second guard bond wire is/are coupled to ground through a flange mounted third and/or fourth capacitor, respectively.215-. (canceled)16. The ...

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Номер записи: 79
03-01-2019 дата публикации

HIGH-POWER AMPLIFIER PACKAGE

Номер: US20190006297A1
Автор: Gittemeier Timothy
Принадлежит: MACOM Technology Solutions Holdings, Inc.

Package assemblies for improving heat dissipation of high-power components in microwave circuits are described. A laminate that includes microwave circuitry may have cut-outs that allow high-power components to be mounted directly on a heat slug below the laminate. Electrical connections to circuitry on the laminate may be made with wire bonds. The packaging allows more flexible design and tuning of packaged microwave circuitry. 1. A high-power amplifier circuit assembled in a package comprising:a microwave circuit formed on a laminate;a case supporting conductive leads that are connected to the microwave circuit;a heat slug connected to the case and extending from an interior region of the case to an exterior region of the case;a cut-out in the laminate; anda first power transistor mounted directly on the heat slug within the cut-out of the laminate and connected to the microwave circuit.2. The high-power amplifier circuit of claim 1 , wherein the first power transistor is capable of outputting power levels between 50 W and 100 W at duty cycles greater than 50% without significant degradation of the amplifier's performance.3. The high-power amplifier circuit of claim 1 , wherein the first power transistor is capable of outputting power levels between 100 W and 200 W at duty cycles greater than 50% without significant degradation of the amplifier's performance.4. The high-power amplifier circuit of claim 3 , wherein the first power transistor comprises GaN.5. The high-power amplifier circuit of claim 4 , further comprising a second power transistor mounted directly on the heat slug in a second cut-out in the laminate and having an output connected to an input of the first power transistor.6. The high-power amplifier circuit of claim 4 , further comprising a second power transistor mounted directly on the heat slug in a second cut-out in the laminate and connected in parallel with the first power transistor in a Doherty configuration.7. The high-power amplifier ...

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Номер записи: 80
03-01-2019 дата публикации

Platform with thermally stable wireless interconnects

Номер: US20190006298A1
Автор: Adel A. Elsherbini, Brandon M. Rawlings, Feras Eid, Georgios C. Dogiamis, Sasha N. OSTER, Telesphor Kamgaing
Принадлежит: Intel Corp

Embodiments of the invention may include a packaged device that includes thermally stable radio frequency integrated circuits (RFICs). In one embodiment the packaged device may include an integrated circuit chip mounted to a package substrate. According to an embodiment, the package substrate may have conductive lines that communicatively couple the integrated circuit chip to one or more external components. One of the external components may be an RFIC module. The RFIC module may comprise an RFIC and an antenna. Additional embodiments may also include a packaged device that includes a plurality of cooling spots formed into the package substrate. In an embodiment the cooling spots may be formed proximate to interconnect lines the communicatively couple the integrated circuit chip to the RFIC.

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Номер записи: 81
03-01-2019 дата публикации

TRANSITION FREQUENCY MULTIPLIER SEMICONDUCTOR DEVICE

Номер: US20190006352A1
Автор: Kobayashi Kevin Wesley
Принадлежит:

A transition frequency multiplier semiconductor device having a first source region, a second source region, and a common drain region is disclosed. A first channel region is located between the first source region and the common drain region, and a second channel region is located between the second source region and the common drain region. A first gate region is located within the first channel region to control current flow between the first source region and the common drain region, while a second gate region is located within the second channel region to control current flow between the second source region and the common drain region. An inactive channel region is located between the first channel region and the second channel region such that the first channel region is electrically isolated from the second channel region. 1. A transition frequency multiplier semiconductor device comprising:a first source region;a second source region;a common drain region;a first channel region located between the first source region and the common drain region;a second channel region located between the second source region and the common drain region;a first gate region located within the first channel region to control current flow between the first source region and the common drain region;a second gate region located within the second channel region to control current flow between the second source region and the common drain region; andan inactive channel region located between the first channel region and the second channel region such that the first channel region is electrically isolated from the second channel region.2. The transition frequency multiplier semiconductor device of further including an interconnect capacitor coupled between the first gate region and the second gate region.3. The transition frequency multiplier semiconductor device of further including an interconnect capacitor coupled between the first source region and the second gate region.4. The ...

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Номер записи: 82
04-01-2018 дата публикации

IMPEDANCE MATCHING CIRCUIT FOR RADIO-FREQUENCY AMPLIFIER

Номер: US20180006626A1
Автор: LYALIN Aleksey A., MUHLMEYER Nicholas Quinn, Reisner Russ Alan, Sun Weimin
Принадлежит:

Impedance matching circuit for radio-frequency amplifier. In some embodiments, an impedance matching circuit can include a primary metal trace having a first end configured to be capable of being coupled to a voltage source for the power amplifier, and a second end configured to be capable of being coupled to an output of the power amplifier. The impedance matching circuit can further include a secondary metal trace having first end coupled to the second end of the primary metal trace, and a second end configured to be capable of being coupled to an output node. The impedance matching circuit can further include a capacitance implemented between the first and second ends of the secondary metal trace, and be configured to trap a harmonic associated with an amplified signal at the output of the power amplifier. 1. An impedance matching circuit for a power amplifier , comprising:a primary metal trace having a first end configured to be capable of being coupled to a voltage source for the power amplifier, and a second end configured to be capable of being coupled to an output of the power amplifier;a secondary metal trace having a first end coupled to the second end of the primary metal trace, and a second end configured to be capable of being coupled to an output node; anda capacitance implemented between the first and second ends of the secondary metal trace, the capacitance configured to trap a harmonic associated with an amplified signal at the output of the power amplifier.2. The impedance matching circuit of further comprising a harmonic trap circuit implemented between the output of the power amplifier and a ground.3. The impedance matching circuit of wherein the harmonic trap circuit includes a series combination of a capacitance and an inductance.4. The impedance matching circuit of wherein the capacitance and the inductance of the harmonic trap are configured to trap a second harmonic associated with the amplified signal.5. The impedance matching circuit of ...

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Номер записи: 83
03-01-2019 дата публикации

SHIELDED INTERCONNECTS

Номер: US20190006572A1
Автор: Caudillo Roman, CLARKE JAMES S., Elsherbini Adel A., Falcon Javier A., Liff Shawna M., Nam Ye Seul, Roberts Jeanette M., Swan Johanna M.
Принадлежит: Intel Corporation

Disclosed herein are shielded interconnects, as well as related methods, assemblies, and devices. In some embodiments, a shielded interconnect may be included in a quantum computing (QC) assembly. For example, a QC assembly may include a quantum processing die; a control die; and a flexible interconnect electrically coupling the quantum processing die and the control die, wherein the flexible interconnect includes a plurality of transmission lines and a shield structure to mitigate cross-talk between the transmission lines. 1. A quantum computing (QC) assembly , comprising:a quantum processing die;a control die; anda flexible interconnect electrically coupling the quantum processing die and the control die, wherein the flexible interconnect includes a plurality of transmission lines and a shield structure to mitigate cross-talk between the transmission lines, and the shield structure includes a plurality of air gaps.2. The QC assembly of claim 1 , wherein the flexible interconnect includes a flexible portion having a first end and an opposing second end claim 1 , a first rigid connection portion at the first end claim 1 , and a second rigid connection portion at the second end.3. The QC assembly of claim 2 , further comprising:a circuit component;wherein the quantum processing die and the first rigid connection portion are coupled to the circuit component, and the circuit component includes electrical pathways to electrically couple the quantum processing die and the first rigid connection portion.4. The QC assembly of claim 1 , wherein the plurality of transmission lines have a longitudinal portion and at least one transverse portion.5. The QC assembly of claim 4 , wherein a pitch of the plurality of transmission lines in the longitudinal portion is less than a pitch of the plurality of transmission lines in the transverse portion.6. The QC assembly of claim 4 , wherein the shield structure includes a plurality of rectangular sleeves in the longitudinal portion ...

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Номер записи: 84
02-01-2020 дата публикации

Method and Apparatus for Integrated Shielded Circulator

Номер: US20200006833A1
Автор: Florian G. Herrault, Jonathan J. Lynch
Принадлежит: HRL LABORATORIES LLC

An RF circulator in combination with a RF integrated circuit, the RF integrated circuit having a plurality of RF waveguide or waveguide-like structures in or on the RF integrated circuit, the RF circulator comprising a disk of ferrite material disposed on a metallic material disposed on or in the RF integrated circuit, the disk of ferrite material extending away from the RF integrated circuit when disposed thereon, the metallic portion having a plurality of apertures therein adjacent the disk of ferrite material which, in use, are in electromagnetic communication with the disk of ferrite material and with the plurality of RF waveguide or waveguide-like structures, the disk of ferrite material being disposed in a metallic cavity.

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Номер записи: 85
02-01-2020 дата публикации

STACKED MEMORY PACKAGE INCORPORATING MILLIMETER WAVE ANTENNA IN DIE STACK

Номер: US20200006845A1
Автор: Fay Owen R., Kaeding John F.
Принадлежит:

A stacked semiconductor device assembly may include a first semiconductor device having a first substrate and a first set of vias through the first substrate. The first set of vias may define a first portion of an antenna structure. The stacked semiconductor device assembly may further include a second semiconductor device having a second substrate and a second set of vias through the second substrate. The second set of vias may define a second portion of the antenna structure. The stacked semiconductor device assembly may also include a stack interconnect structure electrically coupling the first portion of the antenna structure to the second portion of the antenna. 1. A stacked semiconductor device assembly comprising:a first semiconductor device having a first substrate and a first set of vias through the first substrate, the first set of vias defining a first portion of an antenna structure;a second semiconductor device having a second substrate and a second set of vias through the second substrate, the second set of vias defining a second portion of the antenna structure; anda stack interconnect structure electrically coupling the first portion of the antenna structure to the second portion of the antenna structure.2. The assembly of claim 1 , further comprising:one or more additional semiconductor devices, each having an additional substrate and an additional set of vias through the additional substrate, the additional set of vias defining an additional portion of the antenna structure; andone or more additional interconnect structures electrically coupling the additional portion of the antenna structure of each of the additional semiconductor devices to the first portion of the antenna structure and the second portion of the antenna structure.3. The assembly of claim 1 , wherein the first semiconductor device and the second semiconductor device are incorporated into a stacked three-dimensional integrated circuit claim 1 , and wherein the antenna structure ...

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Номер записи: 86
03-01-2019 дата публикации

Power amplifier circuit

Номер: US20190006994A1
Автор: Kenji Sasaki
Принадлежит: Murata Manufacturing Co Ltd

A power amplifier circuit includes a first amplifier transistor and a bias circuit. The first amplifier transistor amplifies a first signal and outputs a second signal. The bias circuit supplies a bias voltage or a bias current to the first amplifier transistor. The first amplifier transistor includes plural unit transistors disposed in a substantially rectangular region. The bias circuit includes first and second bias transistors and first and second voltage supply circuits. The first and second bias transistors respectively supply first and second bias voltages or first and second bias currents to the bases of unit transistors of first and second groups. The first and second voltage supply circuits respectively supply first and second voltages to the bases of the first and second bias transistors. The first and second voltages are decreased in accordance with a temperature increase. The second voltage supply circuit is disposed within the substantially rectangular region.

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Номер записи: 87
02-01-2020 дата публикации

Voltage controlled oscillator circuit, device, and method

Номер: US20200007080A1
Автор: Chi-Hsien Lin, HO-HSIANG Chen, Hsien-Yuan LIAO, Tzu-Jin Yeh, Ying-Ta Lu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A voltage-controlled oscillator (VCO) includes a power supply node configured to have a power supply voltage. A reference node is configured to have a first reference voltage. A transformer-coupled band-pass filter (BPF) is coupled to a cross-coupled pair of transistors. The cross-coupled pair of transistors and the transformer-coupled band-pass filter are positioned between the power supply node and the reference node.

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Номер записи: 88
02-01-2020 дата публикации

RADIO FREQUENCY FILTER AND RADIO FREQUENCY MODULE

Номер: US20200007103A1
Автор: Han Kyu Bum, IM Young Kyoon, LEE Jae Soon, NAM Joong Jin
Принадлежит: SAMSUNG ELECTRO-MECHANICS CO., LTD.

A radio frequency filter includes a first conductive pattern; a second conductive pattern connected to a first point of the first conductive pattern and extended; a third conductive pattern connected to a second point of the first conductive pattern and extended to surround a portion of the second conductive pattern; a fourth conductive pattern; a fifth conductive pattern connected to a third point of the fourth conductive pattern and extended; and a sixth conductive pattern connected to a fourth point of the fourth conductive pattern and extended to surround a portion of the fifth conductive pattern. The first conductive pattern extends toward the fourth conductive pattern and the fourth conductive pattern extends toward the first conductive pattern. A distance between the first conductive pattern and the fourth conductive pattern is greater than or equal to a distance between the third conductive pattern and the sixth conductive pattern. 1. A radio frequency filter comprising:a first conductive pattern extended from a first port and comprising a first point and a second point;a second conductive pattern connected to the first point of the first conductive pattern and extended from the first point;a third conductive pattern connected to the second point of the first conductive pattern and extended to surround at least a portion of the second conductive pattern;a fourth conductive pattern extended from a second port and comprising a third point and a fourth point;a fifth conductive pattern connected to the third point of the fourth conductive pattern and extended from the third point; anda sixth conductive pattern connected to the fourth point of the fourth conductive pattern and extended to surround at least a portion of the fifth conductive pattern,wherein the first conductive pattern extends toward the fourth conductive pattern from the first point and the fourth conductive pattern extends toward the first conductive pattern from the third point, anda separation ...

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Номер записи: 89
02-01-2020 дата публикации

PROCESS-INVARIANT DELAY CELL

Номер: US20200007105A1
Автор: CHENG Haitao, Lu Ye, Qiao Dongjiang, Song Chao
Принадлежит:

An integrated circuit (IC) device includes a first resistive strip having an input terminal and an output terminal. The IC device further includes a second resistive strip having a terminal coupled to a voltage. The second resistive strip may be coplanar with the first resistive strip. The IC device further includes a capacitor formed by the first resistive strip and the second resistive strip. 1. An integrated circuit (IC) device comprising:a first resistive strip having an input terminal and an output terminal;a second resistive strip having a terminal coupled to a voltage, the second resistive strip being coplanar with the first resistive strip; anda capacitor formed by the first resistive strip and the second resistive strip.2. The IC device of claim 1 , wherein the first resistive strip and the second resistive strip comprise polysilicon.3. The IC device of claim 1 , wherein the second resistive strip includes portions substantially parallel to the first resistive strip.4. The IC device of claim 1 , wherein the first resistive strip is interdigitated with the second resistive strip.5. The IC device of claim 1 , wherein the first resistive strip and the second resistive strip are configured to be part of a delay cell or a filter.6. The IC device of claim 1 , wherein the first resistive strip and the second resistive strip are serpentine claim 1 , spiral claim 1 , octagonal claim 1 , and/or circular in shape.7. The IC device of claim 1 , wherein the first resistive strip comprises a first resistive material and the second resistive strip comprises a second resistive material that is different from the first resistive material.8. The IC device of claim 1 , wherein a width of the first resistive strip is substantially equal to a gap between the first resistive strip and the second resistive strip.9. The IC device of claim 8 , wherein the width of the first resistive strip is correlated to the gap between the first resistive strip and the second resistive strip such ...

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Номер записи: 90
20-01-2022 дата публикации

IMPEDANCE ELEMENT WITH BUILT-IN ODD-MODE OSCILLATION SUPPRESSION

Номер: US20220021355A1
Автор: CONRADI Carl, SALMOND Rob, SYCHALEUN Somsack
Принадлежит:

A transistor package for a power amplifier is provided. The transistor package includes a plurality of radio frequency, RF, paths that includes a first RF path and second RF path. Each RF path includes a transistor-carrying die and at least one impedance element. The transistor package includes a circuit portion electrically coupling a first impedance element in the first RF path to a second impedance element in the second RF path where the circuit portion includes at least one resistor. 1. A transistor package for a power amplifier , the transistor package comprising: a transistor-carrying die; and', 'at least one impedance element; and', 'a circuit portion electrically coupling a first impedance element in the first RF path to a second impedance element in the second RF path, the circuit portion including at least one resistor., 'a plurality of radio frequency, RF, paths including a first RF path and second RF path, each RF path including2. The transistor package of claim 1 , wherein the at least one resistor is configured to suppress odd mode signal components associated with the first and second RF paths.3. The transistor package of claim 1 , wherein the at least one resistor includes at least a first resistor and a second resistor claim 1 , the first resistor being electrically coupled to the first impedance element claim 1 , the second resistor being electrically coupled to the second impedance element claim 1 , and the first and second resistors being electrically coupled to each other.4. The transistor package of claim 1 , wherein the at least one resistor includes at least a first resistor and a second resistor claim 1 , the first resistor being integrated with the first impedance element claim 1 , the second resistor being integrated with the second impedance element claim 1 , and the first and second resistors being electrically coupled to each other.5. The transistor package of claim 1 , wherein the circuit portion includes at least one of:at least one ...

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Номер записи: 91
27-01-2022 дата публикации

HIGH-FREQUENCY POWER TRANSISTOR AND HIGH-FREQUENCY POWER AMPLIFIER

Номер: US20220028807A1
Автор: BENGTSSON Olof, KUREMYR Tobias, PAUL Sophie
Принадлежит: FERDINAND-BRAUN-INSTITUT GGMBH, LEIBNIZ-INSTITUT FÜR HÖCHSTFREQUENZTECHNIK

A high-frequency power transistor comprises a transistor, at least one capacitor and a housing, which at least partially encloses the transistor and the capacitor. A first port for a high-frequency input and a gate DC voltage supply are connected to a gate contact of the transistor. A second port is connected to a drain contact of the transistor for a high-frequency output and drain DC voltage supply. A third port and fourth port are connected to a source contact of the transistor. All ports lead out of the same housing. The third port is connected via the capacitor to the source contact, and the fourth port is connected via at least one inductive element to the source contact, so that the third port provides a high-frequency ground, and the fourth port provides a floating low-frequency ground and source DC voltage supply. 1. A high-frequency power transistor comprising:a transistor,at least one capacitor,a housing, which at least partially encloses the transistor and the capacitor,wherein a first port for a high-frequency input and a gate DC voltage supply are connected to a gate contact of the transistor,a second port is connected to a drain contact of the transistor for a high-frequency output and drain DC voltage supply, andwherein a third port and a fourth port are connected to a source contact of the transistor, andwherein the first, second, third and fourth port all lead out of the housing, andwherein the third port is connected via the capacitor to the source contact, and the fourth port is connected via at least one inductive element to the source contact, so that the third port provides a high-frequency ground, and the fourth port provides a floating low-frequency ground and source DC voltage supply, whereinthe inductive element comprises a bond wire or several bond wires connected in parallel.2. (canceled)3. The high-frequency power transistor according to claim 1 , wherein the capacitor is a one-layer capacitor.4. The high-frequency power transistor ...

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Номер записи: 92
14-01-2021 дата публикации

SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, AND METHOD OF OPERATING SEMICONDUCTOR DEVICE

Номер: US20210011077A1
Автор: KAWANO Yoichi, Soga Ikuo
Принадлежит: FUJITSU LIMITED

A semiconductor device includes: a substrate; a circuit element disposed on a first surface side of the substrate; a first transmission line disposed on the first surface side; a first terminal disposed on the first surface side; a first dielectric disposed in a part of the first transmission line; a second terminal disposed on a side of the first dielectric opposite to the first transmission line; a second transmission line disposed on the first surface side and has one end coupled to the circuit element; a third terminal disposed on the first surface side and coupled to the other end of the second transmission line; a second dielectric disposed in a part of the second transmission line; a fourth terminal disposed on a side of the second dielectric opposite to the second transmission line; and a conductor disposed on a second surface side of the substrate. 1. A semiconductor device comprising:a substrate;a circuit element disposed on a first surface side of the substrate;a first transmission line that is disposed on the first surface side of the substrate and has one end coupled to the circuit element;a first terminal that is disposed on the first surface side of the substrate and coupled to the other end of the first transmission line and into which a first direct current voltage and a first alternating current signal for examination or a second direct current voltage for operation are input;a first dielectric that is disposed in a part of the first transmission line on a side opposite to the substrate;a second terminal that is disposed on a side of the first dielectric opposite to the first transmission line so as not to protrude from the first transmission line in a plan view and into which a second alternating current signal for operation is input;a second transmission line that is disposed on the first surface side of the substrate and has one end coupled to the circuit element;a third terminal that is disposed on the first surface side of the substrate and ...

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Номер записи: 93
12-01-2017 дата публикации

CORE FOR HIGH-FREQUENCY TRANSFORMER, AND MANUFACTURING METHOD THEREFOR

Номер: US20170011829A1
Автор: MORITSUGU Nakao, OGURA Katsuhiro
Принадлежит: HITACHI METALS, LTD.

This core for a high-frequency transformer has shape formed by a single roll process by winding a Fe-based nanocrystal alloy thin strip that has a roll contact surface and a free surface while interposing an insulating layer, characterized in that projections having a crater-form depression are dispersed on the free surface of the Fe-based nanocrystal alloy thin strip, and the apexes of the projections are ground and blunted. 1. A core for a high-frequency transformer , having a shape formed by winding an Fe-based nanocrystalline alloy ribbon by a single-roll process with an insulating layer interposed , the Fe-based nanocrystalline alloy ribbon having a roll contact surface and a free surface , whereinthe free surface of the Fe-based nanocrystalline alloy ribbon has dispersed thereon crater-like projections with a concave, and the projections each have a top part that is ground and blunted.2. The core for a high-frequency transformer according to claim 1 , wherein the Fe-based nanocrystalline alloy ribbon has a thickness of 10 to 15 μm.3. A method for manufacturing the core for a high-frequency transformer according to claim 1 , comprising:(1) a step of producing an Fe-based amorphous alloy ribbon for an Fe-based nanocrystalline alloy ribbon by a single-roll process;(2) a step of bring a free surface of the Fe-based amorphous alloy ribbon into contact with a rotating peripheral surface of a cylindrical grindstone, thereby pressure-grinding and blunting top parts of crater-like projections with a concave dispersed on the free surface;(3) a step of forming an insulating layer on the free surface and/or roll contact surface of the Fe-based amorphous alloy ribbon;(4) a step of winding the Fe-based amorphous alloy ribbon having the insulating layer formed thereon; and(5) a step of heat-treating the wound Fe-based amorphous alloy ribbon to cause nanocrystallization, thereby giving an Fe-based nanocrystalline alloy ribbon.4. The core for a high-frequency transformer ...

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Номер записи: 94
12-01-2017 дата публикации

HIGH-FREQUENCY PACKAGE

Номер: US20170012008A1
Автор: Yasooka Kosuke
Принадлежит: Mitsubishi Electric Corporation

A high-frequency package has: a resin substrate; a high-frequency device mounted on a side of a first surface of the resin substrate; a ground surface conductor of a ground potential formed on a second surface of the resin substrate on an opposite side to the first surface; a transmission line for a high-frequency signal formed in an inner layer of the resin substrate; and a ground via of a ground potential formed within the resin substrate. A through hole is formed in the ground surface conductor. The ground via is placed between the transmission line and the through hole. 1. A high-frequency package comprising:a resin substrate;a high-frequency device mounted on a side of a first surface of the resin substrate;a ground surface conductor of a ground potential formed on a second surface of the resin substrate on an opposite side to the first surface;a transmission line for a high-frequency signal formed in an inner layer of the resin substrate; anda ground via of a ground potential formed within the resin substrate, whereina through hole is formed in the ground surface conductor, andthe ground via is placed between the transmission line and the through hole.2. The high-frequency package according to claim 1 , whereina number of the ground via is plural, andthe plural ground vias are placed along the transmission line.3. The high-frequency package according to claim 1 , wherein a diameter of the through hole is less than half of a wavelength of the high-frequency signal.4. A high-frequency package comprising:a resin substrate;a high-frequency device mounted on a side of a first surface of the resin substrate;a ground surface conductor of a ground potential formed on a second surface of the resin substrate on an opposite side to the first surface; anda transmission line for a high-frequency signal formed in an inner layer of the resin substrate, whereina through hole is formed in the ground surface conductor, anda diameter of the through hole is less than half of a ...

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Номер записи: 95
10-01-2019 дата публикации

Packaged Electronic Module and Manufacturing Method Thereof

Номер: US20190012588A1
Автор: Cyril Lalo, Jacques Essebag, Sebastien Pochic
Принадлежит: Cyril Lalo, Jacques Essebag, Sebastien Pochic

The present invention is a packaged electronic module with embedded electronics for use in smart cards. This invention assembles a plurality of electronics components on a flexible printed circuit, together with an integrated circuit chip and a contact plate, into a module. This module can then be embedded into a plastic card, using regular milling techniques, by a card manufacturer. This method packages the plurality of electronics components into a module. The present invention provides a business with the capability to avoid additional capital expenditure required for special equipment and enables all existing card manufacturers to manufacture smart cards with embedded electronics.

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Номер записи: 96
14-01-2016 дата публикации

ELECTRONIC DEVICE

Номер: US20160013130A1
Автор: Baba Osamu, Kawasaki Takeshi
Принадлежит:

An electronic device is disclosed. The electronic device comprises a transistor provided on a substrate, a transmission line provided on the substrate and connected to the transistor, an electrode pad connected to the transmission line, and a connection wiring electrically connecting the electrode pad and the transmission line through a first wiring and a second wiring. Both of the first wiring and the second wiring are connected to different positions of the electrode pad. 1. An electronic device comprising:a transistor provided on a substrate;a transmission line provided on the substrate and connected to the transistor;an electrode pad connected to the transmission line; anda connection wiring electrically connecting the electrode pad and the transmission line through a first wiring and a second wiring,wherein both of the first wiring and the second wiring are connected to different portions of the electrode pad.2. The electronic device according to claim 1 ,wherein the first wiring and the second wiring are connected in parallel between the electrode pad and the transmission line.3. The electronic device according to claim 1 ,wherein the first wiring and the second wiring are larger in an inductor component per unit length than the transmission line.4. The electronic device according to claim 1 ,wherein the transmission line includes one end connected to the transistor and the other end connected to the electrode pad,wherein the first wiring is connected to a first part positioned on a side of the one end of the transmission line with respect to a center part of the electrode pad, andwherein the second wiring is connected to a second part positioned on an opposite side to the side of the one end of the transmission line with respect to the center part of the electrode pad.5. The electronic device according to claim 4 ,wherein the first wiring and the second wiring are point-symmetrical with respect to the center part of the electrode pad, or line-symmetrical with ...

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Номер записи: 97
14-01-2016 дата публикации

RF Switch on High Resistive Substrate

Номер: US20160013141A1
Автор: CHEN Chia-Chung, Fu Shu Fang, Huang Chi-Feng, JOU Chewn-PU, YEH Tzu-Jin
Принадлежит:

A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch. 1. A method comprising:performing a first implantation to implant a semiconductor substrate and to form a deep well region, wherein the semiconductor substrate is of a first conductivity type, and has a resistivity higher than about 5,000 ohm-cm, and wherein in the first implantation, an impurity of a second conductivity type opposite to the first conductivity type is implanted; a top portion overlying the well region; and', 'a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are substantially un-implanted in the first and the second implantations;, 'performing a second implantation to implant the semiconductor substrate, wherein a well region of the first conductivity type is formed over the deep well region, and wherein after the first and the second implantations, the semiconductor substrate comprisesforming a gate dielectric over the top portion of the semiconductor substrate;forming a gate electrode over the gate dielectric; andperforming a third implantation to implant the top portion of the semiconductor substrate and to form a source region and a ...

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Номер записи: 98
11-01-2018 дата публикации

INTEGRATED ANTENNA ON INTERPOSER SUBSTRATE

Номер: US20180012799A1
Автор: CHIEN Chin-Her, Huang Bo-Jr, Lee Yun-Han, Liu Chin-Chou, Shen William Wu
Принадлежит:

Some embodiments relate to a semiconductor module having an integrated antenna structure. The semiconductor module has an excitable element and a first ground plane disposed between a substrate and the excitable element. A second ground plane is separated from the first ground plane by the substrate. The second ground plane is coupled to the first ground plane by one or more through-substrate vias (TSVs) that extend through the substrate. 1. A semiconductor module having an integrated antenna structure , comprising:an excitable element;a first ground plane disposed between a substrate and the excitable element; anda second ground plane separated from the first ground plane by the substrate, wherein the second ground plane is coupled to the first ground plane by one or more through-substrate vias (TSVs) that extend through the substrate.2. The semiconductor module of claim 1 , wherein the first ground plane comprises a first metal interconnect layer surrounded by a first dielectric layer and the excitable element comprises a second metal layer surrounded by a second dielectric layer.3. The semiconductor module of claim 2 , further comprising:one or more additional metal interconnect layers located between the excitable element and the first ground plane.4. The semiconductor module of claim 1 , wherein the second ground plane comprises a printed circuit board or a package substrate including a conductive layer.5. The semiconductor module of claim 1 , wherein the TSVs extend along a first direction through the substrate and the second ground plane extends past outermost sidewalls of the first ground plane along a second direction perpendicular to the first direction.6. The semiconductor module of claim 5 , wherein the second ground plane extends along the second direction past outermost sidewalls of the excitable element.7. The semiconductor module of claim 1 , wherein the excitable element and the first ground plane comprise copper.8. The semiconductor module of claim ...

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Номер записи: 99
11-01-2018 дата публикации

Antenna in Embedded Wafer-Level Ball-Grid Array Package

Номер: US20180012851A1
Автор: Lin Yaojian, Liu Kai
Принадлежит: STATS ChipPAC Pte. Ltd.

A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant. 1. A method of making a semiconductor device , comprising:providing a substrate;forming an antenna over the substrate;forming a ground plane over the substrate opposite the antenna;disposing a semiconductor die adjacent to the substrate; anddepositing an encapsulant over the substrate and semiconductor die.2. The method of claim 1 , further including:providing a dummy die;forming a conductive layer on the dummy die; anddisposing the dummy die over the semiconductor die prior to depositing the encapsulant.3. The method of claim 2 , further including removing the dummy die by backgrinding the dummy die and encapsulant.4. The method of claim 1 , further including forming a conductive layer to electrically couple the antenna to the semiconductor die.5. The method of claim 1 , further including forming the ground plane and the antenna over the substrate prior to depositing the encapsulant.6. The method of claim 1 , further including forming a conductive bump on the ground plane.7. The method of claim 1 , wherein the substrate includes a conductive via between the antenna and semiconductor die.8. A method of making ...

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Номер записи: 100