CHIP PACKAGE, METHOD OF FORMING A CHIP PACKAGE AND METHOD OF FORMING AN ELECTRICAL CONTACT

In various embodiments, a method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.

CHIP PACKAGE AND METHOD OF FORMING A CHIP PACKAGE WITH A METAL CONTACT STRUCTURE AND PROTECTIVE LAYER, AND METHOD OF FORMING AN ELECTRICAL CONTACT

In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

Process for producing a multifunctional dielectric layer on a substrate

A multifunctional dielectric layer can be formed on a substrate, especially on an exposed metallic strip conductor system on a substrate. An additional metal layer is formed across the surface of the exposed metal strip conductors. The metal layer is then at least partially converted to a nonconducting metal oxide, the dielectric layer.

Apparatus and Method For Determining Reliability Of An Integrated Circuit

In an embodiment, an integrated circuit or chip is supplied to its intended application and a measurement quantity representing the state of one or a plurality of electrical connections in the chip is determined within the application environment of the chip and, if the measurement quantity determined does not correspond to predefined criteria, a corresponding signal is output.

Semiconductor devices and methods for forming a semiconductor device

A semiconductor device includes an electrically conductive contact pad structure. Moreover, the semiconductor device includes a bond structure. The bond structure is in contact with the electrically conductive contact pad structure at least at an enclosed interface region. Additionally, the semiconductor device includes a degradation prevention structure laterally surrounding the enclosed interface region. The degradation prevention structure is vertically located between a portion of the bond structure and a portion of the electrically conductive contact pad structure.

On-Chip RF Shields with Backside Redistribution Lines

Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material. 1. A method of forming a system on chip , the method comprising:forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region of the substrate, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry, etching the opening from the back surface using a reactive ion etch, wherein the reactive ion etch starts from the back surface and etches through the substrate and stops on a landing pad, the landing pad being disposed in an insulating layer disposed over the substrate;forming patterns for redistribution lines on a layer disposed at the back surface; andfilling the through substrate opening and the patterns for redistribution lines with a conductive material.2. The method of claim 1 , further comprising:forming devices for RF circuitry and for other circuitry at a top surface before forming the through substrate opening, the top surface being opposite to the back surface;forming interconnect layers before forming the through substrate opening, the interconnect layers interconnecting the devices; andafter forming the interconnect layer, thinning the substrate from a backside to expose the back surface.3. The method of claim 1 , wherein the filled through ...

Semiconductor Device and Method for Making Same

One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer. 1. A method for manufacturing a semiconductor device , the method comprising:forming a first conductive layer with a sidewall;forming a second conductive layer over the first conductive layer such that the second conductive layer has an overhang extending laterally beyond the sidewall of the first conductive layer; andforming a third conductive layer over the second conductive layer, the third conductive layer including a portion formed to a side of the first conductive layer, a dielectric material being between a portion of the third conductive layer and the sidewall, the dielectric material being part of an interlevel dielectric layer.2. The method of claim 1 , wherein the overhang is at least partially formed by a wet etch.3. The method of claim 1 , further comprising forming a passivation layer along the sidewall of the first conductive layer.4. The method of claim 1 , wherein forming the third conductive layer comprises performing a damascene process. This is a divisional application of U.S. application Ser. No. 12/201,888, entitled “Semiconductor Device and Method for Making Same” which was filed on Aug. 29, 2008 and issued on Mar. 31, 2015 as U.S. Pat. No. 8,994,179 and is incorporated herein by reference.The present invention relates to semiconductor devices and methods for making semiconductor devices.In modern integrated circuits, conductive lines may be arranged within dielectric layers to interconnect semiconductor devices. These conductive lines may be formed of metal and may be arranged, for example, on different metallization levels. The conductive lines may be surrounded by, as well as separated by, interlevel ...

On-Chip RF Shields with Backside Redistribution Lines

Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.

Semiconductor Device and Method for Making Same

One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.

System on a chip with on-chip RF shield

Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.

Integrated circuit with improved component interconnections

An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structures levels and elongated interconnects.

Integrated circuit arrangement having a plurality of conductive structure levels and coil, and a method for producing the integrated circuit arrangement

An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structures levels and elongated interconnects.

Method of forming an electrical contact and method of forming a chip package with a metal contact structure and protective layer

A method of forming an electrical contact and a method of forming a chip package are provided. The methods may include arranging a metal contact structure including a non-noble metal and electrically contacting the chip, arranging a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

System on a Chip with On-Chip RF Shield

Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.

CHIP PACKAGE AND METHOD OF FORMING A CHIP PACKAGE

In various embodiments, a chip package is provided. The chip package may include a chip including a chip metal surface, a metal contact structure electrically contacting the chip metal surface, and packaging material including a contact layer being in physical contact with the chip metal surface and/or with the metal contact structure; wherein at least in the contact layer of the packaging material, a summed concentration of chemically reactive sulfur, chemically reactive selenium and chemically reactive tellurium is less than 10 atomic parts per million.

System on a Chip with On-Chip RF Shield

Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.

CHIP PACKAGE, METHOD OF FORMING A CHIP PACKAGE AND METHOD OF FORMING AN ELECTRICAL CONTACT

In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure. 1. A chip package , comprising:a chip comprising a chip metal surface;a metal contact structure, the metal contact structure electrically contacting the chip metal surface;a packaging material; anda protective layer comprising or consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material; 'Ni, Co, Cr, Ti, V, Mn, Zn, Sn, Mo, Zr.', 'wherein the protective layer comprises or essentially consists of at least one material of a group of inorganic materials, the group consisting of'}2. A chip package , comprising:a chip comprising a chip metal surface;a metal contact structure, the metal contact structure electrically contacting the chip metal surface, wherein the metal contact structure comprises copper and/or silver;a packaging material; anda protective layer comprising or consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material;wherein the protective layer comprises or essentially consists of an azole and/or tetracyanoquinodimethane that is different from the packaging material.3. A leadframe based chip package , comprising:a chip;a metal contact structure comprising a non-noble metal and electrically contacting the chip;a packaging material; anda ...

Semiconductor Devices and Methods for Forming a Semiconductor Device

A semiconductor device includes an electrically conductive contact pad structure. Moreover, the semiconductor device includes a bond structure. The bond structure is in contact with the electrically conductive contact pad structure at least at an enclosed interface region. Additionally, the semiconductor device includes a degradation prevention structure laterally surrounding the enclosed interface region. The degradation prevention structure is vertically located between a portion of the bond structure and a portion of the electrically conductive contact pad structure.

Integrated circuit arrangement having a plurality of conductive structure levels and capacitor, and a method for producing the integrated circuit arrangement

An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structure levels in which in each case elongated interconnects are arranged.

METHODS FOR FORMING A CHIP PACKAGE

In various embodiments, methods for forming a chip package are provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.

Process for Producing a Multifunctional Dielectric Layer on a Substrate

A multifunctional dielectric layer can be formed on a substrate, especially on an exposed metallic strip conductor system on a substrate. An additional metal layer is formed across the surface of the exposed metal strip conductors. The metal layer is then at least partially converted to a nonconducting metal oxide, the dielectric layer. 1. A process for producing a multifunctional dielectric layer on a substrate , the process comprising:forming a plurality of metal interconnects that are embedded in an insulator and have been provided with a diffusion barrier at the side walls;applying a further metal layer to uncovered portions of the metal interconnects as a metallic covering, the further metal layer comprising a metal, a metal nitride or a layer sequence of these materials; andconverting the further metal layer into a nonconducting metal oxide thereby forming a dielectric layer.2. The process as claimed in claim 1 , wherein the dielectric layer comprises a barrier layer on at least some interconnects.3. The process as claimed in claim 1 , wherein the dielectric layer comprises a capacitor dielectric for at least one of the interconnects.4. The process as claimed in claim 1 , further comprising covering parts of the further metal layer such that the covered parts form resistors.5. The process as claimed in claim 1 , wherein the metal interconnects comprise a material selected from the group consisting of copper claim 1 , aluminum claim 1 , tungsten claim 1 , and gold.6. The process as claimed in claim 1 , wherein the further metal layer is deposited on the metal interconnects claim 1 , which have a subtractive architecture claim 1 , by virtue of a metal layer that has been deposited over the entire surface of an insulator on the substrate having subsequently been patterned.7. The process as claimed in claim 6 , wherein the metal interconnects comprise aluminum claim 6 , copper claim 6 , tungsten claim 6 , silicides claim 6 , or nitrides.8. The process as claimed ...

System and method for integrated circuit arrangement having a plurality of conductive structure levels

An integrated circuit arrangement includes a substrate with a multiplicity of integrated semiconductor components arranged therein, the substrate having a wiring interconnect near to the substrate, a middle wiring interconnect and a wiring interconnect remote from the substrate, which are arranged in this order at increasing distance from the substrate.

Integrated circuit arrangement with layer stack

An integrated circuit arrangement includes an electrically conductive conduction structure made from copper or a copper alloy. At a side wall of the conduction structure, there is a layer stack which includes at least three layers. Despite very thin layers in the layer stack, it is possible to achieve a high barrier action against copper diffusion combined with a high electrical conductivity, as is required for electrolytic deposition of copper using external current.

Integrated circuit arrangement with layer stack, and process

An integrated circuit arrangement includes an electrically conductive conduction structure made from copper or a copper alloy. At a side wall of the conduction structure, there is a layer stack which includes at least three layers. Despite very thin layers in the layer stack, it is possible to achieve a high barrier action against copper diffusion combined with a high electrical conductivity, as is required for electrolytic deposition of copper using external current.

Semiconductor device and method for making same

One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.

Semiconductor device and method for making same

One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.

Semiconductor device and method for making same

One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.

System and method for integrated circuit arrangement having a plurality of conductive structure levels

An integrated circuit arrangement includes a substrate with a multiplicity of integrated semiconductor components arranged therein, the substrate having a wiring interconnect near to the substrate, a middle wiring interconnect and a wiring interconnect remote from the substrate, which are arranged in this order at increasing distance from the substrate.

Process for producing a multifunctional dielectric layer on a substrate

A multifunctional dielectric layer can be formed on a substrate, especially on an exposed metallic strip conductor system on a substrate. An additional metal layer is formed across the surface of the exposed metal strip conductors. The metal layer is then at least partially converted to a nonconducting metal oxide, the dielectric layer.

On-Chip Radio Frequency Shield with Interconnect Metallization

Structure and method for fabricating a system on chip with an on-chip RF shield including interconnect metallization is described. In one embodiment, the system on chip includes an RF circuitry disposed on a first portion of a top surface of a substrate, and a semiconductor circuitry disposed on a second portion of the top surface of the substrate. An interconnect RF barrier is disposed between the RF circuitry and the semiconductor circuitry, the interconnect RF barrier coupled to a ground potential node.

Long-term heat treated integrated circuit arrangements and methods for producing the same

An explanation is given of, inter alia, methods in which the barrier material is removed at a via bottom or at a via top area by long-term heat treatment. Concurrently or alternatively, interconnects are coated with barrier material in a simple and uncomplicated manner by means of the long-term heat treatment. 1. A method for producing an integrated circuit arrangement , in which heat treatment is effected once or repeatedly , wherein as a result of the heat treatment a barrier material layer between a via conductive structure and an interconnect is removed , perforated or thinned by at least 50%.2. The method as claimed in claim 1 , wherein the barrier material layer between the via conductive structure and the interconnect is removed claim 1 , perforated or thinned by at least 90%.3. The method as claimed in claim 1 , wherein the barrier material is removed in at least one of the following ways:by diffusion along grain boundaries of a conductive structure; andby interface diffusion along an interface between two different materials.4. The method as claimed in claim 1 , wherein the barrier material to be removed is present with a thickness of up to 2 nanometers claim 1 , and heat treatment is effected in total for more than 1.5 hours claim 1 , or the barrier material to be removed is present with a thickness in the range of 2 nanometers to 5 nanometers claim 1 , and heat treatment is effected in total for more than 3 hours claim 1 , the temperature during heat treatment being 430° Celsius.5. The method as claimed in claim 1 , wherein the barrier material to be removed is transported along grain boundaries by at least 5 nanometers during the heat treatment.6. A method for producing an integrated circuit arrangement in which heat treatment is effected once or repeatedly claim 1 , wherein a secondary barrier material is transported from original barrier material by interface diffusion along the interface of a conductive structure.7. The method as claimed in claim 6 , ...

Semiconductor Device and Method for Making Same

One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.

Elimination of Die-Top Delamination

An integrated-circuit module includes an integrated-circuit device having a first surface and a plurality of bond pads disposed on the first surface. The module further includes metallic bond wires or metallic ribbons, which are attached between respective ones of a first subset of the bond pads and a package substrate or leadframe, such that a second subset of the bond pads are not attached to either a package substrate or leadframe. A metallic stud bump is affixed to each of one or more of the second subset of the bond pads. The integrated-circuit module further comprises a molding compound that contacts at least the first surface of the integrated-circuit device and substantially surrounds the bond wires or ribbon wires and the metallic stud bumps. 1. An integrated-circuit module , comprising:an integrated-circuit device having a first surface and a plurality of bond pads disposed on the first surface;metallic bond wires or metallic ribbons attached between respective ones of a first subset of the bond pads and a package substrate or leadframe, such that a second subset of the bond pads are not attached to either a package substrate or leadframe;a metallic stud bump affixed to each of one or more of the second subset of the bond pads; anda molding compound contacting the first surface and substantially surrounding the bond wires or ribbon wires and the metallic stud bumps.2. The integrated-circuit module of claim 1 , wherein one or more of the metallic stud bumps comprise a nail-head bond affixed to a corresponding one of the second subset of the bond pads.3. The integrated-circuit module of claim 2 , wherein the one or more of the metallic stud bumps further comprise a wire segment severed proximate the nailhead bond.4. The integrated-circuit module of claim 1 , wherein the metallic stud bumps comprise a metallic bond wire affixed to each of two of the second subset of the bond pads.5. The integrated-circuit module of claim 1 , wherein an exposed surface of each ...

Integrated circuit arrangement having a plurality of conductive structure levels and capacitor, and a method for producing the integrated circuit arrangement

An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structure levels in which in each case elongated interconnects are arranged.

Long-term heat-treated integrated circuit arrangements and methods for producing the same

An explanation is given of, inter alia, methods in which the barrier material is removed at a via bottom or at a via top area by long-term heat treatment. Concurrently or alternatively, interconnects are coated with barrier material in a simple and uncomplicated manner by means of the long-term heat treatment.

System on a chip with on-chip RF shield

Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.

Chip package and method of forming a chip package with a metal contact structure and protective layer, and method of forming an electrical contact

In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

System on a chip with on-chip RF shield

Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.

METHOD OF MAKING INTERCONNECT STRUCTURE

One or more embodiments relate to a method of forming a semiconductor device having a substrate, comprising: providing a Si-containing layer; forming a barrier layer over the Si-containing layer, the barrier layer comprising a compound including a metallic element; forming a metallic nucleation_seed layer over the Si-containing layer, the nucleation_seed layer including the metallic element; and forming a metallic interconnect layer over the nucleation_seed layer, wherein the barrier layer and the nucleation_seed layer are formed without exposing the semiconductor device substrate to the ambient atmosphere.

Chip package comprising a chemical compound and a method of forming a chip package comprising a chemical compound

In various embodiments, a chip package is provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.

On-Chip RF Shields with Backside Redistribution Lines

Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.

Long-term heat-treated integrated circuit arrangements and methods for producing the same

An explanation is given of, inter alia, methods in which the barrier material is removed at a via bottom or at a via top area by long-term heat treatment. Concurrently or alternatively, interconnects are coated with barrier material in a simple and uncomplicated manner by means of the long-term heat treatment.

Chip package and method of forming a chip package

In various embodiments, a chip package is provided. The chip package may include a chip including a chip metal surface, a metal contact structure electrically contacting the chip metal surface, and packaging material including a contact layer being in physical contact with the chip metal surface and/or with the metal contact structure; wherein at least in the contact layer of the packaging material, a summed concentration of chemically reactive sulfur, chemically reactive selenium and chemically reactive tellurium is less than 10 atomic parts per million.

On-chip radio frequency shield with interconnect metallization

Structure and method for fabricating a system on chip with an on-chip RF shield including interconnect metallization is described. In one embodiment, the system on chip includes an RF circuitry disposed on a first portion of a top surface of a substrate, and a semiconductor circuitry disposed on a second portion of the top surface of the substrate. An interconnect RF barrier is disposed between the RF circuitry and the semiconductor circuitry, the interconnect RF barrier coupled to a ground potential node.

System on a Chip with On-Chip RF Shield

Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.

On-chip RF shields with backside redistribution lines

Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.

On-chip RF shields with backside redistribution lines

Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.

Method for forming a chip package with compounds to improve the durability and performance of metal contact structures in the chip package

In various embodiments, methods for forming a chip package are provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.

On-chip RF shields with backside redistribution lines

Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.

Interconnect structure

One or more embodiments relate to a semiconductor device, comprising: a Si-containing layer; a barrier layer disposed over the Si-containing layer, the barrier layer comprising a compound including a metallic element; a metallic nucleation_seed layer disposed over the barrier layer, the nucleation_seed layer including the metallic element; and a metallic interconnect layer disposed over the nucleation_seed layer, the interconnect layer comprising at least one element selected from the group consisting of Cu (copper), Au (gold), and Ag (silver).

Long-term heat treated integrated circuit arrangements and methods for producing the same

An explanation is given of, inter alia, methods in which the barrier material is removed at a via bottom or at a via top area by long-term heat treatment. Concurrently or alternatively, interconnects are coated with barrier material in a simple and uncomplicated manner by means of the long-term heat treatment.

Chip package and method of forming a chip package

In various embodiments, a chip package is provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.

Metal deposition of contact holes for semiconductor work

(57)【要約】 【課題】半導体素体におけるコンタクトホールの金属被 着方法であって信頼性及び将来技術において無制限に使 用可能なものを提供する。 【解決手段】半導体素体におけるコンタクトホールの金 属被着のために唯一のＣＶＤ室において、先ずチタンリ ッチ膜を、続いて低抵抗のＴｉＳｉ 2 膜をただ１回のＣ ＶＤプロセスで析出する。

Integrated semiconductor product with metal-insulator-metal capacitor

To produce an integrated semiconductor product comprising an integrated metal-insulator-metal capacitor, a dielectric auxiliary layer (6) is first deposited on a first electrode (2, 3, 5). Said auxiliary layer (6) is then opened over the first electrode (15). A dielectric layer (7) is then created, onto which the stack (8, 9, 10) of metal strips for the second electrode is applied. The metal-insulator-metal capacitor is subsequently patterned using conventional etching technology. This allows the production of dielectric capacitor layers comprising freely selectable materials of any thickness. The particular advantage of the invention is that the etching of vias can be carried out in a significantly simpler manner than in prior art, as it is not necessary to etch through the remaining dielectric capacitor layer over the metal strips.

USE OF A MASS FLOW DETECTING DEVICE WORKING ON THE BASIS OF OPTICAL ABSORPTION FOR DOSING SUBSTANCES

The method described calls for the whole of the gas stream to be passed through an absorption cell (3). A beam of light is passed through the absorption cell (3) as well as through a reference cell (4) containing a reference gas. The optical radiation which emerges from the cells is detected by an optical detector (8, 9) and a signal generated which is proportional to the mass rate of flow being measured.

A chip package, method of forming a chip package, and method of forming an electrical contact

Bei diversen Ausführungsformen wird ein Verfahren zum Bilden eines elektrischen Kontakts bereitgestellt. Das Verfahren kann das Einrichten einer Metallkontaktstruktur über oder auf einer Metalloberfläche, das Metallisieren einer Metallschicht auf der Metalloberfläche und auf der Metallkontaktstruktur, wodurch die Metallkontaktstruktur auf der Metalloberfläche fixiert wird und ein elektrischer Kontakt zwischen der Metallkontaktstruktur und der Metalloberfläche gebildet wird oder ein existierender elektrischer Kontakt zwischen der Metallkontaktstruktur und der Metalloberfläche verstärkt oder verdickt wird, aufweisen. In various embodiments, a method of forming an electrical contact is provided. The method may include establishing a metal contact structure over or on a metal surface, metallizing a metal layer on the metal surface and on the metal contact structure, thereby fixing the metal contact structure on the metal surface and forming an electrical contact between the metal contact structure and the metal surface or existing electrical contact between the metal contact structure and the metal surface is reinforced or thickened.

Method for tungsten contact hole filling by full-surface tungsten deposition with reduced layer thickness and back-etching with inverse loading effect

Method for tungsten contact hole filling by full-surface tungsten deposition with reduced layer thickness and back-etching with inverse loading effect. By means of a cooling process, the real wafer temperature during the etching process is kept below 70 DEG C and the etching rate in the contact hole is smaller than or equal to that on the substrate surface. <IMAGE>

Halbleiterbauelemente und Verfahren zum Bilden eines Halbleiterbauelements

Ein Halbleiterbauelement (100, 200, 300, 400, 500, 600, 700, 800), umfassend:eine elektrisch leitfähige Kontaktanschlussflächenstruktur (110);eine Bondstruktur (150), die zumindest an einer umschlossenen Schnittstellenregion (160) in Kontakt mit der elektrisch leitfähigen Kontaktanschlussflächenstruktur (110) ist; undeine Verschlechterungs-Präventionsstruktur (140), die die umschlossene Schnittstellenregion (160) lateral umgibt, wobei die Verschlechterungs-Präventionsstruktur (14) vertikal zwischen einem Abschnitt der Bondstruktur (150) und einem Abschnitt der elektrisch leitfähigen Kontaktanschlussflächenstruktur (110) angeordnet ist,wobei die Bondstruktur (150) zusätzlich an einer Peripherie-Schnittstellenregion in Kontakt mit der elektrisch leitfähigen Kontaktanschlussflächenstruktur (110) ist,wobei die Peripherie-Schnittstellenregion die Verschlechterungs-Präventionsstruktur (140) lateral umgibt.

Chipintegrierte HF-Abschirmungen mit rückseitigen Umverdrahtungsleitungen

Strukturen eines System-auf-Chip und Verfahren zum Ausbilden eines System-auf-Chip werden offenbart. Bei einer Ausführungsform beinhaltet das Verfahren zum Herstellen des System-auf-Chip das Ausbilden einer Durch-Substrat-Öffnung von einer hinteren Oberfläche eines Substrats aus, wobei die Durch-Substrat-Öffnung zwischen einem ersten und einem zweiten Gebiet angeordnet ist, wobei das erste Gebiet Bauelemente für eine HF-Schaltungsanordnung aufweist und das zweite Gebiet Bauelemente für eine andere Schaltungsanordnung aufweist. Das Verfahren bei Umverdrahtungsleitungen auf einer Fotoresistschicht, wobei die Fotoresistschicht unter der hinteren Oberfläche angeordnet ist, und Füllen der Durch-Substrat-Öffnung und der Strukturen für Umverdrahtungsleitungen mit einem leitenden Material.

System auf einem Chip mit HF-Abschirmung auf dem Chip

Es wird ein Halbleiterchip offenbart. Bei einer Ausführungsform weist das Halbleiterchip auf: eine erste Halbleiterkomponente, die in einem ersten Teil eines Substrats angeordnet ist; eine zweite Halbleiterkomponente, die in einem zweiten Teil des Substrats angeordnet ist; eine zwischen dem ersten Teil des Substrats und dem zweiten Teil des Substrats gebildete Hochfrequenz (HF)-Abschirmung, wobei zu und von der ersten Halbleiterkomponente gesendete hochfrequente elektromagnetische Strahlung durch die HF-Abschirmung mindestens teilweise blockiert wird, wobei die HF-Abschirmung um die erste Halbleiterkomponente herum entlang eines äußeren Rands des Substrats nicht angeordnet ist; wobei die HF-Abschirmung Folgendes aufweist: eine obere Abschirmung, die über einer oberen Oberfläche des Substrats über der ersten Halbleiterkomponente angeordnet ist; eine untere Abschirmung, die unter einer rückseitigen Oberfläche des Substrats unter der ersten Halbleiterkomponente angeordnet ist; und eine vertikale Abschirmung, die an der gemeinsamen Grenze zwischen der ersten Halbleiterkomponente und der zweiten Halbleiterkomponente angeordnet ist.

Chipgehäuse und verfahren zum bilden eines chipgehäuses

Bei diversen Ausführungsformen wird ein Chipgehäuse bereitgestellt. Das Chipgehäuse kann einen Chip aufweisen, der eine Chipmetalloberfläche umfasst, eine Metallkontaktstruktur, die die Chipmetalloberfläche elektrisch kontaktiert, ein Packagingmaterial, das den Chip und die Metallkontaktstruktur mindestens teilweise kapselt, und eine chemische Zusammensetzung aufweisen, die das Packagingmaterial und die Chipmetalloberfläche und/oder die Metallkontaktstruktur physisch kontaktiert, wobei die chemische Zusammensetzung ausgelegt sein kann, um eine Haftung zwischen der Metallkontaktstruktur und dem Packagingmaterial und/oder zwischen der Chipmetalloberfläche und dem Packagingmaterial im Vergleich zu einer Haftung in einer Anordnung ohne chemische Zusammensetzung zu verbessern, wobei die chemische Zusammensetzung im Wesentlichen von funktionalen Gruppen, die Schwefel, Selenium oder Tellur umfassen, frei ist.

Chip package, method of forming a chip package and method of forming an electrical contact

A method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.

Briefsammler und -ordner.

Schuhabsatz mit auswechselbarem Lauffleck

Fodder-box.

Verpackungsbeutel, insbesondere aus kunststoff-folie.

Anschlusskabel mit Verschraubung und Sicherung zum direkten Einschrauben in das Sicherungselement

Verfahren zur Bildung einer HF-Abschirmung

Verfahren zur Bildung einer Halbleiterkomponente, mit den folgenden Schritten:Bilden einer ersten Öffnung und einer benachbarten Öffnung in einem Silizium-auf-Isolator (SOI)-Substrat (10, 14, 15), wobei sich die erste Öffnung und die benachbarte Öffnung von einer oberen Oberfläche einer Siliziumschicht (15) des SOI-Substrats aus in eine Siliziumregion (10) unter einer isolierenden Schicht (14) des SOI-Substrats erstreckt;Bilden einer Deckschicht auf den Seitenwänden der ersten Öffnung und der benachbarten Öffnung, wobei die Deckschicht ein dielektrisches Material aufweist;Füllen der ersten Öffnung und der benachbarten Öffnung mit einem Halbleitermaterial (19);Abscheiden einer ersten leitfähigen Schicht (118) über dem Halbleitermaterial (19);Umwandeln des Halbleitermaterials (19) in ein zweites leitfähiges Material durch Einführen von leitfähigen Atomen aus der ersten leitfähigen Schicht (118) in die erste Öffnung und die benachbarte Öffnung; undUmwandeln eines Teils der Siliziumregion (10) innerhalb jeweils einer Region unter der ersten Öffnung und unter der benachbarten Öffnung in ein drittes leitfähiges Material durch Einführen leitfähiger Atome aus der ersten leitfähigen Schicht (118) durch das Halbleitermaterial (19), wobei der Abstand der ersten Öffnung und der benachbarten Öffnung derart eingerichtet ist, dass die jeweils eine Region unter der ersten Öffnung und unter der benachbarten Öffnung zusammenlaufen.

Integrierte Schaltungsanordnung mit mehreren Leitstrukturlagen und Verfahren

Integrated circuit arrangement having a plurality of conductive structure levels and capacitor, and method

Integrated circuit arrangement having a plurality of conductive structure levels and coil, and method