Semiconductor Structures and Method for Fabricating the Same

A semiconductor structure is provided. The semiconductor structure includes a first substrate, a second substrate opposite to the first substrate, a plurality of spacers disposed between the first substrate and the second substrate, and an adhesive material bonded with the first substrate and the second substrate within the two adjacent spacers. The invention also provides a method for fabricating the semiconductor structure.

Tall and fine pitch interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

Method for Manufacturing Metal Powder

A method for manufacturing metal powder comprising: providing a basic metal salt solution; contacting the basic metal salt solution with a reducing agent to precipitate metal powder therefrom; and recovering precipitated metal powder from the solvent.

Tall and Fine Pitch Interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

Carbon nanotube structure, heat dissipation sheet, and method of manufacturing carbon nanotube structure

A carbon nanotube structure includes a plurality of carbon nanotubes, and a graphite film that binds one ends of the plurality of carbon nanotubes. And a heat dissipation sheet includes a plurality of carbon nanotube structures arranged in a sheet form, wherein each of the carbon nanotube structures includes a plurality of carbon nanotubes, and a graphite film that binds one ends of the plurality of carbon nanotubes.

Wafer-level package device having high-standoff peripheral solder bumps

A wafer-level package device and techniques for fabricating the device are described that include a second integrated circuit chip electrically coupled to a base integrated circuit chip, where the second integrated circuit chip is placed on and connected to the base integrated circuit chip between multiple high-standoff peripheral pillars with solder bumps. In implementations, the wafer-level package device that employs example techniques in accordance with the present disclosure includes a base integrated circuit chip, multiple high-standoff peripheral pillars with solder bumps, and a second integrated circuit chip electrically coupled to the base integrated circuit chip and placed on the base integrated circuit chip in the center of an array of high-standoff peripheral pillars with solder bumps.

METAL CORED SOLDER DECAL STRUCTURE AND PROCESS

A system of producing metal cored solder structures on a substrate includes: a decal, a carrier, and receiving elements. The decal includes one or more apertures each of which is tapered from a top surface to a bottom surface thereof. The carrier is positioned beneath the bottom of the decal and includes cavities in a top surface. The cavities are located in alignment with the apertures of the decal. The decal is positioned on the carrier having the decal bottom surface in contact with the carrier top surface to form feature cavities defined by the decal apertures and the carrier cavities. The feature cavities are shaped to receive one or more metal elements and are configured for receiving molten solder cooled in the cavities. The decal is separable from the carrier to partially expose metal core solder contacts. The receiving elements receive the metal core solder contacts thereon. 1. A system for producing metal cored solder structures on a substrate , comprising:a decal having a plurality of apertures, the apertures being tapered from a top surface to a bottom surface of the decal;a carrier configured to be positioned beneath the bottom of the decal, the carrier having one or more cavities in a top surface and the cavities located in alignment with the apertures of the decal;the decal configured to be positioned on the carrier having the decal bottom surface in contact with the carrier top surface to form feature cavities defined by the decal apertures and the carrier cavities, the feature cavities being shaped to receive a plurality of metal elements therein, the feature cavities being configured to receive molten solder being cooled in the cavities, the decal being separable from the carrier to partially expose metal core solder contacts; andreceiving elements of a substrate, the receiving elements being configured to receive the metal core solder contacts thereon, and the metal core solder contacts being exposed and positioned on the substrate.2. The system ...

METHOD OF PRODUCING BUMPS IN ELECTRONIC COMPONENTS, CORRESPONDING COMPONENT AND COMPUTER PROGRAM PRODUCT

An electronic component, such as an integrated circuit, includes one or more circuits with bumps extending in a longitudinal direction outward from the circuit. The bumps may be formed, e.g., by 3D printing, with at least one protrusion extending away from the longitudinal direction. 110-. (canceled)11. A method of producing an electronic component comprising a circuit with at least one bump extending in a longitudinal direction outward from the circuit , the method comprising:forming the at least one bump with at least one protrusion extending away from the longitudinal direction.12. The method of claim 11 , wherein the at least one bump is formed as one piece.13. The method of claim 11 , wherein the at least one protrusion has a T-shape with an enlarged head protruding sidewise of the longitudinal direction to provide a plurality of coupling locations.14. The method of claim 11 , wherein the at least one protrusion has a mushroom-like shape with an enlarged head protruding sidewise of the longitudinal direction to provide a plurality of coupling locations.15. The method of claim 11 , wherein the at least one protrusion has a non-linear shape.16. The method of claim 11 , wherein the at least one protrusion has a curved shape.17. The method of claim 11 , wherein the at least one protrusion has a V-shape.18. The method of claim 11 , wherein the at least one protrusion is resilient.19. The method of claim 11 , wherein the at least one protrusion comprises a cantilevered protrusion.20. The method of claim 11 , wherein the at least one bump is formed by 3D printing.21. The method of claim 11 , wherein the circuit comprises at least one electrically conductive circuit pad on which the at least one bump is formed.22. The method of claim 20 , wherein the at least one bump comprises at least one of copper claim 20 , nickel and tin.23. An electronic component comprising:a circuit;at least one bump extending in a longitudinal direction outward from the circuit; andat least ...

PACKAGE-ON-PACKAGE DEVICE AND CAVITY FORMATION BY SOLDER REMOVAL FOR PACKAGE INTERCONNECTION

In an electronic package that includes an electronic component, a method of forming one or more cavities in the electronic package includes depositing solder material on at least one terminal of the electronic component, encapsulating the electronic component and the solder material in an encapsulant, exposing a top surface of the solder material from the encapsulant, and removing the solder material such that a cavity remains at a location in the encapsulant where the solder material was removed. The solder material can be removed by a hot air solder removal process to yield one or more cavities having a consistent size and shape. In a package-on-package (PoP) process, solder balls on an active surface of another electronic package are positioned in the one or more cavities in alignment with the terminals, and the solder balls are attached to the terminals via solder reflow to produce a PoP device. 1. A method of forming a cavity in an electronic package , said electronic package including an electronic component , and said method comprising:depositing solder material on at least one terminal of said electronic component;encapsulating said electronic component and said solder material in an encapsulant;exposing a top surface of said solder material from said encapsulant; andfollowing said exposing operation, removing said solder material such that said cavity remains at a location where said solder material was removed, wherein said removing operation removes said top surface of said solder material and at least a portion of said solder material below said top surface to produce said cavity.2. The method of wherein said electronic component includes a plurality of terminals claim 1 , said solder material comprises a plurality of solder balls claim 1 , and said depositing comprises forming one each of said plurality of solder balls on one each of said plurality of terminals.3. The method of wherein:said exposing comprises retaining said encapsulant between adjacent ...

SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die. 1. A semiconductor package comprising:a package substrate having planar top and bottom major surfaces, wherein the package substrate is defined with a die region and a non-die region surrounding the die region, and the package substrate comprises a base substrate having a mold material and a plurality of via contacts extending from the top to the bottom major surface of the package substrate;an insulating layer having planar top and bottom surfaces, wherein the insulating layer is disposed directly over the via contacts;a plurality of conductive studs disposed in the insulating layer, wherein the conductive studs extend from the top to the bottom surface of the insulating layer, wherein the conductive studs are disposed in the die region and the non-die region of the package substrate;conductive traces and connection pads disposed directly on the top surface of the insulating layer and over the conductive studs;a die having conductive contacts, wherein the die is disposed in the die region of the package substrate and the conductive contacts of the die are electrically coupled to the conductive traces or connection pads;a cap disposed over the package substrate to encapsulate the die, wherein a side surface of conductive studs disposed at a periphery of the non-die region of the package substrate is exposed.2. The semiconductor package of ...

Semiconductor package and fabricating?method?thereof

본 발명은 반도체 패키지 및 그 제조 방법에 관한 것으로서, 해결하고자 하는 기술적 과제는 파인 피치의 대응에 유리한 도전성 필러를 포함하는 반도체 패키지 및 그 제조 방법을 제공하는데 있다. The present invention relates to a semiconductor package and a method for manufacturing the same, and a technical problem to be solved is to provide a semiconductor package and a method for manufacturing the same comprising a conductive filler in favor of the fine pitch. 이를 위해 본 발명은 평평한 제 1 면 및 제 1 면의 반대면으로써 평평한 제 2 면을 갖고, 제 1 면에 다수의 본드 패드가 형성된 반도체 다이, 본드 패드와 전기적으로 연결되는 언더 범프 메탈층, 평평한 제 1 면 및 제 1 면의 반대면으로써 제 1 면에 비하여 상대적으로 좁은 제 2 면을 갖고, 제 1 면이 언더 범프 메탈층과 접하며, 제 2 면에는 솔더 캡이 형성된 도전성 필러, 솔더 캡과 전기적으로 연결되는 서브스트레이트를 포함하는 반도체 패키지 및 그 제조 방법을 개시한다. To this end, the present invention is a semiconductor die having a flat first surface and a flat second surface as an opposite surface of the first surface, a plurality of bond pads formed on the first surface, an under bump metal layer electrically connected to the bond pads, and a flat surface. A first side and an opposite side of the first side and having a second side relatively narrower than the first side, the first side is in contact with the under bump metal layer, and the second side is formed with a conductive filler, a solder cap, Disclosed are a semiconductor package comprising a substrate connected electrically and a method of manufacturing the same. 이와 같이 하여 본 발명에 의한 반도체 패키지 및 그 제조 방법은 파인 피치를 갖는 서브스트레이트 및 작고 고성능의 반도체 패키지를 구현할 수 있으며, 저비용으로 균일한 전기 전도성을 갖는 도전성 필러를 형성한다. In this way, the semiconductor package and the manufacturing method thereof according to the present invention can implement a substrate having a fine pitch and a small, high performance semiconductor package, and form a conductive filler having uniform electrical conductivity at low cost. 도전 패턴, 도전성 필러, 반도체 다이, 반도체 패키지, 솔더 캡 Conductive Pattern, Conductive Filler, Semiconductor Die, Semiconductor Package, Solder Cap

Conductive connection sheet, connection method between terminals, formation method of connection terminal, semiconductor device and electronic device

Bump forming film, semiconductor device and manufacturing method thereof, and connection structure

Semiconductor packages and methods of packaging semiconductor devices

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.

Method for manufacturing metal powder

一种用于制造金属粉末的方法，包括：提供碱性金属盐溶液；使该碱性金属盐溶液与还原剂接触以从其中沉淀出金属粉末；以及从溶剂中回收所沉淀的金属粉末。

Apparatus for Mounting Conductive Ball

본 발명은 도전성 볼 탑재 장치에 관한 것으로, 더욱 상세하게는 마스크에 형성된 마운팅 홀을 통해 도전성 볼을 기판에 탑재하는 공정을 수행함에 있어서 공정 불량의 발생을 방지할 수 있고 매우 작은 크기의 도전성 볼도 효과적으로 기판에 탑재할 수 있는 구조를 가진 도전성 볼 탑재 장치에 관한 것이다. 본 발명의 도전성 볼 탑재 장치는 마스크의 변형을 방지하여 도전성 볼의 누락 없이 높은 품질로 도전성 볼 탑재 공정을 수행할 수 있는 효과가 있다. 또한, 본 발명의 도전성 볼 탑재 장치는 매우 작은 크기의 도전성 볼의 기판에 탑재하는 공정을 효과적으로 수행할 수 있는 효과가 있다.

Reflow film, solder bump forming method, solder bonding forming method, and semiconductor device

Semiconductor packages and methods of packaging semiconductor devices

本發明揭示半導體封裝及用於形成一半導體封裝之方法。該方法包含提供具有第一主要表面及第二主要表面之一封裝基板。該封裝基板包含：一基底基板，其具有一模製材料；及複數個互連結構，其包含延伸穿過該封裝基板之該第一主要表面至該第二主要表面之導通體觸點。提供在其第一表面或第二表面上具有導電觸點之一晶粒。該晶粒之該等導電觸點電耦合至該等互連結構。一帽蓋形成於該封裝基板上方以囊封該晶粒。

Method for manufacturing metal powder

A method for manufacturing metal powder comprising: providing a basic metal salt solution; contacting the basic metal salt solution with a reducing agent to precipitate metal powder therefrom; and recovering precipitated metal powder from the solvent.

Method for manufacturing metal powder

A method for manufacturing metal powder comprising: providing a basic metal salt solution; contacting the basic metal salt solution with a reducing agent to precipitate metal powder therefrom; and recovering precipitated metal powder from the solvent.

Conductive connecting sheet, connecting method between terminals, method for forming connecting terminals, semiconductor device and electronic machine

Conductive connection sheet, method for connecting terminals, method for forming connection terminal, semiconductor device, and electronic device

本发明的导电连接片（1）由具有树脂组合物层（11、13）和金属层（12）的层叠体构成，并且该树脂组合物层（11、13）满足下述必要条件A。若使用如此构成的导电连接片（1）来形成对端子相互之间进行电连接的连接部时，能够有选择性地使加热熔融的金属材料凝集在端子相互之间来形成连接部，并在其周围形成由树脂成分构成的密封层。其结果，能够用树脂成分来覆盖连接部的周围，因此连接部被固定。另外，通过密封层可确保相邻端子间的绝缘性，因此能够可靠地防止相邻端子相互之间产生漏电流的问题。必要条件A：在树脂组合物层（11、13）中配置了由低熔点的金属材料所构成的金属球的至少一部分的状态下，按照JIS Z 3197中规定的焊接用树脂类助焊剂试验方法，加热至前述金属球的熔融温度以上，然后测定前述金属球的湿润扩散率，此时该湿润扩散率为37%以上。

Manufacturing method of carbon nanotube structure, heat dissipation sheet and carbon nanotube structure

Microelectronic contact structure and the production and use method thereof

초소형 전자 요소 접촉 구조물(260, 360, 460)은 전자 요소와 같은 기판(202, 302, 402)의 표면 상에 마스킹 층(220, 320, 420)을 도포하고, 마스킹 층에 개구(222, 322, 422)를 생성하고, 시드 층(250, 350, 450)의 도전성 트레이스를 마스킹 층 상에 그리고 개구 안에 적층하고, 도전성 트레이스 상에 도전성 재료의 덩어리를 형성함으로써 석판 인쇄식으로 형성되고 제조된다. 개구의 측벽들은 경사(테이퍼)질 수 있다. 도전성 트레이스는 재료를 스텐실 또는 섀도우 마스크(240, 340, 440)를 통해 적층시킴으로써 패터닝될 수 있다. 돌기 형상부(230, 430)는 접촉 구조물의 팁 단부(264, 364, 464)가 토포그래피(topography)를 갖도록 마스킹 층 상에 배치될 수 있다. 모든 이러한 요소들은 복수의 정밀 배치된 탄성 접촉 구조물을 형성하도록 그룹으로서 제조될 수 있다. 접촉 구조물, 전자 요소, 마스킹 층, 시드 층, 도전층

Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages

A nano-sized metal particle composite includes a first metal that has a particle size of about 50 nanometer or smaller. A wire interconnect is in contact with a reflowed nanosolder and has the same metal or alloy composition as the reflowed nanosolder. A microelectronic package is also disclosed that uses the reflowed nanosolder composition. A method of assembling a microelectronic package includes preparing a wire interconnect template. A computing system includes a nanosolder composition coupled to a wire interconnect.

Microelectronic contact structure and the production and use method thereof

초소형 전자 요소 접촉 구조물(260, 360, 460)은 전자 요소와 같은 기판(202, 302, 402)의 표면 상에 마스킹 층(220, 320, 420)을 도포하고, 마스킹 층에 개구(222, 322, 422)를 생성하고, 시드 층(250, 350, 450)의 도전성 트레이스를 마스킹 층 상에 그리고 개구 안에 적층하고, 도전성 트레이스 상에 도전성 재료의 덩어리를 형성함으로써 석판 인쇄식으로 형성되고 제조된다. 개구의 측벽들은 경사(테이퍼)질 수 있다. 도전성 트레이스는 재료를 스텐실 또는 섀도우 마스크(240, 340, 440)를 통해 적층시킴으로써 패터닝될 수 있다. 돌기 형상부(230, 430)는 접촉 구조물의 팁 단부(264, 364, 464)가 토포그래피(topography)를 갖도록 마스킹 층 상에 배치될 수 있다. 모든 이러한 요소들은 복수의 정밀 배치된 탄성 접촉 구조물을 형성하도록 그룹으로서 제조될 수 있다. Subminiature electronic element contact structures 260, 360, 460 apply masking layers 220, 320, 420 on the surface of substrates 202, 302, 402, such as electronic elements, and openings 222, 322 in the masking layer. , 422 is formed and manufactured lithographically by stacking conductive traces of seed layers 250, 350, and 450 on the masking layer and into the openings, and forming agglomerates of conductive material on the conductive traces. Sidewalls of the opening can be tapered. Conductive traces can be patterned by stacking materials through stencils or shadow masks 240, 340, 440. The protrusion features 230, 430 may be disposed on the masking layer such that the tip ends 264, 364, 464 of the contact structure have topography. All these elements can be manufactured as a group to form a plurality of precisely disposed elastic contact structures. 접촉 구조물, 전자 요소, 마스킹 층, 시드 층, 도전층 Contact structure, electronic element, masking layer, seed layer, conductive layer

Method for manufacturing slant sidewall to aperture of mask material layer

(57)【要約】 （修正有） 【課題】半導体デバイス上に超微細小型バネ接触要素を 形成する。 【解決手段】電子部品のような基板２０２の表面上にマ スク層２２０を適用し、このマスク層に開口を生成し、 シード層２５０の導電性トレースを前記マスク層の上と 前記開口の中に堆積して、導電性トレース上に導電性材 料の塊を構築することにより、超小型電子接触構造体２ ６０がリソグラフ的に画定され、製造される。開口の側 壁は傾斜（テーパ）して、形成される。導電性トレース は、ステンシル又はシャドウマスクを介して材料を堆積 することによってパターン化できる。接触構造体の先端 部２６４がトポロジーを取得するように、突出造作２３ ０をマスク層上に配置することができる。これらの構成 要素は全てグループとして構成して、精密に位置決めさ れた複数の弾性接触構造体を形成することができる。

凸塊形成用膜、半導體裝置及其製造方法、以及連接構造體

一種用以於無凸塊IC晶片等半導體裝置形成低成本且可實現穩定之導通可靠性之凸塊的凸塊形成用膜，該凸塊形成用膜以俯視觀之，凸塊用導電填料規則排列於絕緣性接著樹脂層內。該規則排列沿膜之長邊方向具有週期性重複單位，連接膜之厚度方向之凸塊用導電填料之一端部的直線大致平行於膜之表面。

焼結材料、及びそれを用いる接着方法

【課題】各種コンポーネントを接着（接合）するための方法を提供する。【解決手段】フリップチップなどのマルチチップ及び単一コンポーネントのダイ接着のための方法であって、基板の上又はダイの裏側に焼結ペーストをプリントすることを含むことができる。プリンティングは、ステンシルプリンティング、スクリーンプリンティング、又はディスペンシングプリンティングを含むことができる。ペーストは、ダイシングの前に全ウェハの裏側にプリントすることができる、又は個々のダイの裏側にプリントすることができる。また、焼結膜は、作成後、ウェハ、ダイ、又は基板に転写することができる。ポスト焼結工程は、スループットを上げることができる。【選択図】図３２

Three-dimensional integrated circuit structures and methods of forming the same

Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps.

半导体器件及其制作方法

本发明提供一种高效率低成本地制作芯片尺寸封装的方法，通过在半导体芯片电极形成面一侧制作导电引线，扩大该封装的电极间距，特别地，提供一种制作引线和形成凸块的方法。一种半导体器件，包括半导体元件，以及在半导体元件上通过刻蚀形成引线的金属箔而形成的导电引线；一种半导体器件制作方法，包括以下步骤：在电极形成面一侧将形成电极的金属箔层压到半导体上，在金属箔上制作光刻胶引线图形，刻蚀金属箔以及将器件分割成单个的元件。

一种功率芯片混合凸点的结构、制作方法及半导体器件

本发明申请公开了一种功率芯片混合凸点的结构、制作方法及半导体器件，包括源极镀焊层步骤：在晶圆表面涂覆粘接胶并蚀刻后暴露出源极，源极区镀覆一层焊层；金属片电镀步骤：提供一覆层板，在覆层板金属层面贴附感光膜并蚀刻，后暴露出金属层面并在该处镀覆镀层，去除感光膜和覆层板基体，并切割为单一金属片；源极凸点制作步骤：在源极涂覆焊料，将金属片镀层面贴附在焊料上并焊接牢固，完成源极凸点制作；栅极凸点制作步骤：将铜球通过引线键合的方式在栅极上制作凸点，本申请通过采用混合方式分开制作凸点，避免焊接过程中源极和栅极两个区域存在连接短路的风险，导电散热性能好，工艺简单，降本增效。

반도체 패키지 및 그 제조방법

대향하는 제1 면 및 제2 면을 갖고, 상기 제1 면 상에 배치된 패드 구조물들, 및 상기 패드 구조물들과 전기적으로 연결된 재배선층을 포함하는 재배선 부재와, 상기 재배선 부재의 상기 제2 면 상에 배치되고, 상기 재배선층에 전기적으로 연결된 상호연결 회로를 포함하는 상호연결 칩과, 상기 상호연결 칩의 주위에 배치되고, 상기 재배선층에 전기적으로 연결되는 비아 구조물과, 상기 상호연결 칩 및 상기 비아 구조물 각각의 적어도 일부를 봉합하는 봉합재와, 상기 봉합재 상에 배치되는 범프 구조물들을 포함하는 기판; 및 상기 재배선 부재의 상기 제1 면 상에 배치되고, 상기 패드 구조물들에 전기적으로 연결되는 제1 및 제2 칩 구조물을 포함하고, 상기 범프 구조물들은 상기 제2 면에 수직한 제1 방향으로 상기 상호연결 칩의 적어도 일부와 중첩되는 제1 범프 구조물, 및 상기 비아 구조물의 적어도 일부와 중첩되는 제2 범프 구조물을 포함하고, 상기 제1 범프 구조물은 상기 봉합재 상에 배치된 제1 포일층, 및 상기 제1 포일층 상에 배치된 제1 도금층을 포함하고, 상기 제2 범프 구조물은 상기 봉합재 상에 배치된 제2 포일층, 및 상기 제2 포일층을 관통하여 상기 비아 구조물의 적어도 일부를 노출시키는 개구부 내에 배치된 제2 도금층을 포함하는 반도체 패키지를 제공한다.

Metal cored solder decal structure and process

A system of producing metal cored solder structures on a substrate includes: a decal having a plurality of apertures, the apertures being tapered from a top surface to a bottom surface of the decal; a carrier configured for positioning beneath the bottom of the decal, the carrier having cavities in a top surface and the cavities located in alignment with the apertures of the decal; the decal being configured for positioning on the carrier having the decal bottom surface in contact with the carrier top surface to form feature cavities defined by the decal apertures and the carrier cavities, the feature cavities being shaped to receive a plurality of metal elements therein, the feature cavities configured for receiving molten solder being cooled in the cavities, the decal being separable from the carrier to partially expose metal core solder contacts; and receiving elements of a substrate being configured to receive the metal core solder contacts thereon, and the metal core solder contacts being exposed and positioned on the substrate.

Integrated device package comprising photo sensitive fill between a substrate and a die

An integrated device package that includes a die, a substrate, a fill and a conductive interconnect. The die includes a pillar, where the pillar has a first pillar width. The substrate (e.g., package substrate, interposer) includes a dielectric layer and a substrate interconnect (e.g., surface interconnect, embedded interconnect). The fill is located between the die and the substrate. The conductive interconnect is located within the fill. The conductive interconnect includes a first interconnect width that is about the same or less than the first pillar width. The conductive interconnect is coupled to the pillar and the substrate interconnect. The fill is a non-conductive photosensitive material. The fill is a photosensitive film. The substrate interconnect includes a second interconnect width that is equal or greater than the first pillar width. The conductive interconnect includes one of at least a paste, a solder and/or an enhanced solder comprising a polymeric material.

Die attachment for packaged semiconductor device

A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.

Semiconductor package and method of manufacturing the same

A semiconductor package includes: a substrate including a redistribution member having a first surface and a second surface, opposing each other, and including pad structures disposed on the first surface and a redistribution layer electrically connected to the pad structures, an interconnect chip disposed on the second surface of the redistribution member and including an interconnect circuit electrically connected to the redistribution layer, a via structure disposed around the interconnect chip and electrically connected to the redistribution layer, an encapsulant encapsulating at least a portion of each of the interconnect chip and the via structure, and bump structures disposed on the encapsulant; and a first chip structure and a second chip structure disposed on the first surface of the redistribution member and electrically connected to the pad structures.

Semiconductor package and method of manufacturing the same

A semiconductor package includes: a substrate including a redistribution member having a first surface and a second surface, opposing each other, and including pad structures disposed on the first surface and a redistribution layer electrically connected to the pad structures, an interconnect chip disposed on the second surface of the redistribution member and including an interconnect circuit electrically connected to the redistribution layer, a via structure disposed around the interconnect chip and electrically connected to the redistribution layer, an encapsulant encapsulating at least a portion of each of the interconnect chip and the via structure, and bump structures disposed on the encapsulant; and a first chip structure and a second chip structure disposed on the first surface of the redistribution member and electrically connected to the pad structures.

Semiconductor structures and method for fabricating the same

Tall and fine pitch interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

一种面板级封装可焊性镀层的制作方法

本发明申请公开了一种面板级封装可焊性镀层的制作方法，包括以下步骤：涂胶步骤：在封装面板暴露焊盘的一面涂覆粘接胶；蚀刻步骤：在涂粘接胶的一面蚀刻出缺口，以完全暴露出焊盘；焊接步骤：在缺口处涂上焊料，缺口处焊料与焊盘焊接为一体，形成焊柱；研磨步骤：将焊柱和粘接胶研磨，研磨面为一平面；去胶步骤，本申请通过粘接胶涂覆、蚀刻、填焊料、焊接和去胶，形成凸出的焊层，所用的设备都是产线现有的设备，不需要额外采购其他特别的设备，不需要采用昂贵的化学药水，相对于电镀锡和化锡工艺，成本降低，工艺简单，可以根据实际生产的需要制作焊层的厚度，没有焊层的损失风险，产品设计的自由度好。

Semiconductor apparatus, method of manufacturing semiconductor apparatus, and electronic apparatus

A semiconductor apparatus, including: a semiconductor component; a Cu stud bump that is formed on the semiconductor component; and a solder bump configured to electrically connect to the Cu stud bump.

반도체 패키지 및 그 제조 방법

본 발명의 실시 예에 따른 반도체 패키지는: 제 1 패키지 기판; 상기 제 1 패키지 기판상에 실장되고 제 1 패드 및 제 2 패드를 갖는 제 1 반도체 칩; 그리고 상기 제 1 패드 상에 제공되고, 상기 제 1 반도체 칩을, 상기 제 1 반도체 칩의 상면에 제공되는 제 2 반도체 칩 또는 제 2 패키지 기판과 전기적으로 연결하는 클래드 메탈을 포함할 수 있다. 본 발명의 실시 예에 따르면, 반도체 패키지의 제조 비용을 줄일 수 있으며, 반도체 패키지의 열 방출 능력을 향상시킬 수 있다.

Verfahren zur herstellung einer vielzahl von halbleiterbauelementen, halbleiterbauelement und halbleiterbauteil mit einem solchen halbleiterbauelement

Es wird unter anderem ein Verfahren zur Herstellung einer Vielzahl von Halbleiterbauelementen mit den folgenden Schritten angegeben: - Bereitstellen eines Trägers (1) mit einer Vielzahl erster Durchbrüche (11) und zweiter Durchbrüche (12), die sich jeweils vollständig durch den Träger (1) erstrecken, - Füllen der ersten Durchbrüche (11) und der zweiten Durchbrüche (12) mit einem Anschlussmaterial (3), - Aufbringen einer Vielzahl von Halbleiterchips (4) auf den Träger (1), wobei zumindest manche der Vielzahl von Halbleiterchips (4) einen ersten Durchbruch (11) und einen zweiten Durchbruch (12) überdecken, - Herstellen einer elektrisch leitenden Verbindung zwischen zumindest manchen der Vielzahl von Halbleiterchips (4) und dem Anschlussmaterial (3) in den überdeckten ersten Durchbrüchen (11) und in den überdeckten zweiten Durchbrüchen (12), - Vereinzeln in eine Vielzahl von Halbleiterbauelementen (100), wobei jedes Halbleiterbauelement (100) zumindest einen Halbleiterchip (4) umfasst, der über das Anschlussmaterial (3) von der dem Halbleiterchip (4) her abgewandten Seite elektrisch kontaktierbar ist.

전자 회로 장치 및 그 제조 방법

전자부품 칩과 접속용 다층 기판의 안정적인 전기적 접속을 얻을 수 있는, 고밀도로 소형화하여 형성되는 전자 회로 장치 및 그 제조 방법을 제공하는 것을 목적으로 한다. 전자부품 칩 (1) 과 접속용 다층 기판 (2), 또는 전자부품 칩끼리를, 인터포저 (6) 를 통하거나 또는 통하지 않고, 아르곤 등의 불활성 분위기 중 또는 수소 등의 환원성 분위기 중에서 가열하여 압접하는 방법, 또는 접합면을 활성화 처리한 후에 상온 압접 또는 가열 압접하는 방법 중 어느 한 방법을 사용하여 직접 야금학적으로 접합하는 것에 의해 전자 회로 장치 (40) 로 한다.

半导体器件及其制作方法

本发明提供一种高效率低成本地制作芯片尺寸封装的方法，通过在半导体芯片电极形成面一侧制作导电引线，扩大该封装的电极间距，特别地，提供一种制作引线和形成凸块的方法。一种半导体器件，包括半导体元件，以及在半导体元件上通过刻蚀形成引线的金属箔而形成的导电引线；一种半导体器件制作方法，包括以下步骤：在电极形成面一侧将形成电极的金属箔层压到半导体上，在金属箔上制作光刻胶引线图形，刻蚀金属箔以及将器件分割成单个的元件。

Semiconductor apparatus, method of manufacturing semiconductor apparatus, and electronic apparatus

A semiconductor apparatus, including: a semiconductor component; a Cu stud bump that is formed on the semiconductor component; and a solder bump configured to electrically connect to the Cu stud bump.

Semiconductor apparatus, method of manufacturing semiconductor apparatus, and electronic apparatus

A semiconductor apparatus, including: a semiconductor component; a Cu stud bump that is formed on the semiconductor component; and a solder bump configured to electrically connect to the Cu stud bump.

System and method for forming solder bumps

焼結材料、及びそれを用いる接着方法

电子设备和用于制造电子设备的方法

提出一种电子设备，所述电子设备具有第一器件(1)和第二器件(2)，所述第一器件和所述第二器件借助具有第一金属的烧结层(3)彼此连接，其中所述器件(1，2)中的至少一个器件具有至少一个接触层(4，4’)，所述接触层以与所述烧结层(3)直接接触的方式设置，所述烧结层具有与第一金属不同的第二金属并且所述烧结层不含金。此外，提出一种用于制造电子设备的方法。

Fabrication method for a semiconductor device

A method of efficiently and inexpensively fabricating a chip-size package having an electrode pitch expanded by forming a conductor wiring on the electrode forming surface side of a semiconductor chip, especially, a method for facilitating wiring and bump forming. A semiconductor device comprising a semiconductor elements and conductor wirings formed on the semiconductor elements by etching wiring-forming metal foil; and a fabrication method for a semiconductor device comprising the steps of laminating wiring forming metal foil on the electrode forming surface side on the semiconductor, forming a resist wiring pattern on the metal foil, etching the metal foil, and slicing the device into individual elements.

Method for manufacturing metal powder

半导体封装及其制造方法

一种半导体封装，包括：衬底以及第一芯片结构和第二芯片结构，衬底包括：重分布构件，该重分布构件具有彼此相对的第一表面和第二表面，并且包括设置在第一表面上的焊盘结构和电连接到焊盘结构的重分布层；互连芯片，设置在重分布构件的第二表面上，并且包括电连接到重分布层的互连电路；过孔结构，设置在互连芯片周围，并且电连接到重分布层；密封剂，密封互连芯片和过孔结构中的每一个的至少一部分；以及凸块结构，设置在密封剂上，第一芯片结构和第二芯片结构设置在重分布构件的第一表面上，并且电连接到焊盘结构。

System and method for forming solder bumps

In an embodiment, a method for forming a solder bump includes preparing a transfer mold having a solder pillar extending from a mold substrate and through a first photoresist layer and having a shape partially defined by a second photoresist layer that is removed prior to transfer of the solder. In an embodiment, the mold substrate is flexible. In an embodiment, the transfer mold is flexible. In an embodiment, the method includes providing a device substrate having a wettable pad. In an embodiment, the method includes placing the transfer mold and the device substrate into aligned contact such that the solder pillar is in contact with the wettable pad. In an embodiment, the method includes forming a metallic bond between the solder pillar and the wettable pad. In an embodiment, the method includes removing the mold substrate and first photoresist layer.

はんだバンプを形成するためのシステムおよび方法

電子装置、及び電子装置を製造する方法

【課題】２つの構成要素が焼結層によって結合されている装置を提供する。【解決手段】電子装置１００は、第１の構成要素１と第２の構成要素２が第１の金属を有する焼結層３によって互いに結合されており、構成要素の少なくとも一方は、少なくとも１つのコンタクト層４を有する。コンタクト層は、焼結層と直接的にコンタクトされた状態で配置されており、第１の金属とは異なる第２の金属を有し、かつ、金を含まない。【選択図】図１

Semiconductor package and method of manufacturing the same

Provided is a semiconductor package and a method of making same, including a first package substrate; a first semiconductor chip mounted on the first package substrate and having a first pad and a second pad, wherein the first pad is provided on a top of the first semiconductor chip and the second pad is provided on a bottom of the first semiconductor chip, the bottom being an opposite surface of the top; and a clad metal provided on the first pad and electrically connecting the first semiconductor chip to one of a second semiconductor chip and second package substrate provided on the top of the first semiconductor chip.

転写バンプシート

(57)【要約】 【課題】 転写バンプシート上の導体端子を、加熱転写 時においても位置ずれを生じることなく、半導体チップ の電極に対して一括転写することの出来る転写バンプシ ートを提供する。 【解決手段】 転写バンプシート１のベースシート４０ 上の導体端子３を、加熱転写時における常温との温度差 （△Ｔs，△Ｔt）、および半導体チップ１０および転写 バンプシート１の熱膨張係数（α，β）の差を考慮し て、下記の式により算出された位置に形成する。 Ｘtn ＝ Ｘsn・(１＋α・△Ｔs)／(１＋β・△Ｔt)

System und verfahren zum bilden von lötperlen

Ein Verfahren zum Bilden einer Lötperle (122) schließt Vorbereiten einer Transferform (100), die eine Lötmittelsäule (112) aufweist, die sich von einem Formsubstrat (102) und durch eine erste Photoresistschicht (104) erstreckt und eine Form aufweist, die zum Teil durch eine zweite Photoresistschicht (108) definiert wird, die vor dem Überführen des Lötmittels entfernt wird; Bereitstellen eines Einheitensubstrats (114) mit einer benetzbaren Anschlussfläche (120); Anordnen der Transferform (100) und des Einheitensubstrats (114) in ausgerichtetem Kontakt, so dass die Lötmittelsäule (112) in Kontakt mit der benetzbaren Anschlussfläche (120) steht; Bilden einer metallischen Verbindung zwischen der Lötmittelsäule (112) und der benetzbaren Anschlussfläche (120), z.B. durch ein Kaltschweißverfahren oder ein Aufschmelzverfahren; und Entfernen des Formsubstrats (102) und der ersten Photoresistschicht (104) ein. Das Formsubstrat (102) und die Transferform (100) können flexibel sein. Die Transferform kann wenigstens eines aufweisen von: eine Benetzungsschicht über dem Formsubstrat (402), in welchem Fall eine Säule (112), die Aluminium enthält, aufgebracht und aufgeschmolzen werden kann; eine Keimschicht über dem Formsubstrat (402); und eine nichtbenetzende Schicht über der zweiten Photoresistschicht (408). Das Einheitensubstrat (114, 502) kann ein Durchgangsloch (118, 504) aufweisen und kann ein Interposer sein, der aus Silicium, Glas und/oder organischem Substratmaterial hergestellt ist. Das Verfahren kann ferner Befestigen des Interposers (114, 502) an eine Qubit-Halbleitereinheit (einen supraleitenden Chip) (300, 516) einschließen, wobei die Qubit-Halbleitereinheit (300, 516) einen Josephson-Übergang (304, 518) aufweist und wobei das Befestigen des Interposers (114, 502) an der Qubit-Halbleitereinheit (300, 516) Ausrichten des Lochs (118, 504) durch den Interposer (114, 502) auf den Josephson-Übergang (304, 518) einschließt, um einen Weg zum Zugang zu dem Josephson-Übergang ( ...

半導體裝置，製造半導體裝置的方法，以及電子裝置

一種半導體裝置，包括：一半導體構件；一Cu柱形凸塊，形成於該半導體構件上；以及一焊料凸塊，經配置而電性連接於該Cu柱形凸塊。

半導體裝置，製造半導體裝置的方法，以及電子裝置

半导体设备、半导体设备的制造方法以及电子设备

本发明提供半导体设备、半导体设备的制造方法以及电子设备。该半导体设备包括：半导体部件；Cu柱形凸块，形成在半导体部件上；以及焊料凸块，构造为电连接到Cu柱形凸块。

반도체 장치, 반도체 장치의 제조 방법 및 전자 기기

반도체 장치는, 반도체 부재와, 상기 반도체 부재 위에 형성된 Cu 스터드 범프와, 상기 Cu 스터드 범프와 전기적으로 접속하도록 구성된 솔더 범프를 포함한다.

프리폼솔더 제조방법 및 프리폼솔더를 이용한 소자실장방법

접합시간을 단축시키면서도 접합부의 품질을 균일하게 유지시켜 화합물반도체를 이용한 전력반도체나 소자 패키지에서 동작시나 고온 사용환경에서도 접합부의 고내열 특성을 유지할 수 있는 프리폼솔더 제조방법 및 프리폼솔더를 이용한 소자실장방법이 제안된다. 본 발명에 따른 프리폼솔더 제조방법은 구리박막층 상에 솔더층을 형성하는 솔더층형성단계; 및 구리박막층 및 솔더층 사이에 금속간화합물이 형성되도록 솔더층을 금속간화합물층 및 잔여솔더층으로 변환시키는 변환단계;를 포함한다.

はんだバンプを形成するためのシステムおよび方法

実施形態において、はんだバンプを形成するための方法は、モールド基板から第１のフォトレジスト層を通って延び、はんだの転写前に除去される第２のフォトレジスト層によって部分的に規定される形状を持つはんだ柱を有するトランスファ・モールドを準備することを含む。実施形態において、モールド基板は可撓性である。実施形態において、トランスファ・モールドは可撓性である。実施形態において、方法は、湿潤式パッドを有するデバイス基板を設けることを含む。実施形態において、方法は、トランスファ・モールドとデバイス基板とを、はんだ柱が湿潤式パッドに接触するように整列接触させて配置することを含む。実施形態において、方法は、はんだ柱と湿潤式パッドとの間に金属結合を形成することを含む。実施形態において、方法は、モールド基板および第１のフォトレジスト層を除去することを含む。

System and method for forming solder bumps

In an embodiment, a method for forming a solder bump includes preparing a transfer mold having a solder pillar extending from a mold substrate and through a first photoresist layer and having a shape partially defined by a second photoresist layer that is removed prior to transfer of the solder. In an embodiment, the mold substrate is flexible. In an embodiment, the transfer mold is flexible. In an embodiment, the method includes providing a device substrate having a wettable pad. In an embodiment, the method includes placing the transfer mold and the device substrate into aligned contact such that the solder pillar is in contact with the wettable pad. In an embodiment, the method includes forming a metallic bond between the solder pillar and the wettable pad. In an embodiment, the method includes removing the mold substrate and first photoresist layer.

System and method for forming solder bumps

A method for forming a solder bump (122) includes preparing a transfer mold (100) having a solder pillar (112) extending from a mold substrate (102) and through a first photoresist layer (104) and having a shape partially defined by a second photoresist layer (108) that is removed prior to transfer of the solder; providing a device substrate (114) having a wettable pad (120); placing the transfer mold (100) and the device substrate (114) into aligned contact such that the solder pillar (112) is in contact with the wettable pad (120); forming a metallic bond between the solder pillar (112) and the wettable pad (120), e.g. by a cold welding process or a reflow process; and removing the mold substrate (102) and the first photoresist layer (104). The mold substrate (102) and the transfer mold (100) may be flexible. The transfer mold may comprise at least one of: a wetting layer over the mold substrate (402), in which case a pillar (112) including aluminum may be deposited and reflowed; a seed layer over the mold substrate (402); and a non-wetting layer over the second photoresist layer (408). The device substrate (114, 502) may comprise a through hole (118, 504) and may be an interposer made of silicon, glass and/or organic substrate material. The method may further comprise attaching the interposer (114, 502) to a qubit semiconductor device (a superconducting chip) (300, 516), wherein the qubit semiconductor device (300, 516) comprises a Josephson junction (304, 518), and wherein the attaching of the interposer (114, 502) to the qubit semiconductor device (300, 516) includes aligning the hole (118, 504) through the interposer (114, 502) with the Josephson junction (304, 518) to provide a path for accessing the Josephson junction (304, 518), in particular to make adjustments to its design frequency. The solder pillar (122) may be one of a plurality of solder pillars that are formed around the hole (118) between the qubit semiconductor device (300) and the interposer ( ...

電子装置、及び電子装置を製造する方法

半導体装置の作製方法

【課題】高集積化された半導体集積回路の厚さを薄くすることができる。 【解決手段】基板上に、第１のバンプと接続する第１の半導体素子層と、第１のシート状繊維体と第１の有機樹脂を有する第１の構造体と、第１の構造体を貫通する第１の貫通電極を作製し、第２のバンプに接続する第２の半導体素子層と、第２のシート状繊維体と第２の有機樹脂を有する第２の構造体を作製し、第３のシート状繊維体と第３の有機樹脂を有する第３の構造体の、未硬化の第３の有機樹脂上に金属粒子を有する導電性樹脂を配置することより未硬化の第３の有機樹脂が溶解し、金属粒子が第３のシート状繊維体の間を移動し、第３の構造体を貫通する第３の貫通電極が形成され、基板上で第１の貫通電極、第３の貫通電極、第２のバンプが重なり合うように配置し、第３の有機樹脂を硬化させる半導体装置及びその作製方法に関する。 【選択図】図９

用于形成焊料凸块的系统和方法

一种用于形成焊料凸块(122)的方法包括：制备转移模具(100)，该转移模具具有焊料柱(112)，该焊料柱(112)从模具衬底(102)延伸并且穿过第一光致抗蚀剂层(104)并且具有部分地由第二光致抗蚀剂层(108)限定的形状，该第二光致抗蚀剂层(108)在转移焊料之前被去除；提供具有可润湿焊盘(120)的器件衬底(114)：将转移模具(100)和器件衬底(114)置于对准接触中，使得焊料柱(112)与可润湿焊盘(120)接触；在所述焊料柱(112)与所述可润湿焊盘(120)之间形成金属接合，例如，采用冷焊或回流工艺去除所述模具衬底(102)和所述第一光致抗蚀剂层(104)。模具衬底(102)和转移模具(100)可以是柔性的。转移模具可以包括以下至少一个：在模具衬底(402)之上的润湿层，在这种情况下，包括铝的柱(112)可以被沉积和回流：在模具衬底(402)之上的籽晶层以及在第二光致抗蚀剂层(408)之上的非润湿层。器件衬底(114、502)可以包括通孔(118、504)并且可以是由硅、玻璃和/或有机衬底材料制成的内插器。该方法可以进一步包括将该内插器(I14，502)附接到量子位半导体器件(超导芯片)(300，516)上，其中该量子位半导体器件(300，516)包括约瑟夫逊结(304，518)，并且其中将该内插器(114，502)附接到该量子位半导体器件(300，516)上包括将穿过该内插器(11，502)的孔(118，504)与该约瑟夫逊结(304，518)对准以便提供用于访问该约瑟夫逊结(304，518)的路径，特别是对其设计频率做出调整。该焊料柱(122)可以是围绕该量子位半导体器件(300)与该内插器(114)之间的该孔(118)形成的多个焊料柱中的一个，用于提供该约瑟夫逊结(304)的热隔离量，从而在该量子位周围并且在该内插器(114)与该超导芯片(300)之间形成一个圆形壁(200A，200B)，其中该圆形壁(200A，200B)可以包括穿过其中的至少一个空隙(202)。焊料柱(512)可以是转移模具的多个焊料柱(512)中的一个，包括具有第一直径的第一焊料柱(512)和具有第二直径的第二焊料柱(512)，第一直径大于第二直径。器件衬底(602)可以包括半导体衬底，该半导体衬底包括深凹部(604)，其中，电路组件(608)可以包括在深凹部(604)中。转移模具(100)的制备可包括：对第一和第二光致抗蚀剂层(104、108)进行图案化以限定延伸穿过第一和第二光致抗蚀剂层(104、108)的凹部(110)，以及使用注塑焊接(IMS)来用焊料填充凹部(110)以形成焊料柱(112)。可替代地，转移模具的制备可包括：图案化第一光致抗蚀剂层和第二光致抗蚀剂层(404、408)以限定延伸穿过第一光致抗蚀剂层和第二光致抗蚀剂层(404、408)的凹部(410)：形成籽晶层，其中，籽晶层的至少一部分设置在凹部(410)中；以及使用电镀来用焊料填充所述凹部(410)并形成所述焊料柱。柱(112)可以是由镀铜或铜柱凸块形成的3D金属柱。

System and method for forming solder bumps

A method for forming a solder bump (122) includes preparing a transfer mold (100) having a solder pillar (112) extending from a mold substrate (102) and through a first photoresist layer (104) and having a shape partially defined by a second photoresist layer (108) that is removed prior to transfer of the solder; providing a device substrate (114) having a wettable pad (120); placing the transfer mold (100) and the device substrate (114) into aligned contact such that the solder pillar (112) is in contact with the wettable pad (120); forming a metallic bond between the solder pillar (112) and the wettable pad (120), e.g. by a cold welding process or a reflow process; and removing the mold substrate (102) and the first photoresist layer (104). The mold substrate (102) and the transfer mold (100) may be flexible. The transfer mold may comprise at least one of: a wetting layer over the mold substrate (402), in which case a pillar (112) including aluminum may be deposited and reflowed; a seed layer over the mold substrate (402); and a non-wetting layer over the second photoresist layer (408). The device substrate (114, 502) may comprise a through hole (118, 504) and may be an interposer made of silicon, glass and/or organic substrate material. The method may further comprise attaching the interposer (114, 502) to a qubit semiconductor device (a superconducting chip) (300, 516), wherein the qubit semiconductor device (300, 516) comprises a Josephson junction (304, 518), and wherein the attaching of the interposer (114, 502) to the qubit semiconductor device (300, 516) includes aligning the hole (118, 504) through the interposer (114, 502) with the Josephson junction (304, 518) to provide a path for accessing the Josephson junction (304, 518), in particular to make adjustments to its design frequency. The solder pillar (122) may be one of a plurality of solder pillars that are formed around the hole (118) between the qubit semiconductor device (300) and the interposer ( ...

Sintering materials and attachment methods using same

Methods for die attachment of multichip and single components including flip chips may involve printing a sintering paste on a substrate or on the back side of a die. Printing may involve stencil printing, screen printing, or a dispensing process. Paste may be printed on the back side of an entire wafer prior to dicing, or on the back side of an individual die. Sintering films may also be fabricated and transferred to a wafer, die or substrate. A post-sintering step may increase throughput.

재료들의 소결 및 그를 이용하는 부착 방법들

멀티칩 및 플립(flip) 칩들을 포함하는 단일 구성요소들의 다이 부착을 위한 방법들은 소결 페이스트를 기판 상에 또는 다이의 뒷면 상에 프린팅하는 단계를 포함할 수 있다. 프린팅은 스텐실 프린팅, 스크린 프린팅, 또는 디스펜싱(dispensing) 프로세스를 포함할 수 있다. 페이스트는 다이싱(dicing) 이전에 전체 웨이퍼(wafer)의 뒷면 상에, 또는 개별적인 다이의 뒷면 상에 프린팅될 수 있다. 소결 막들이 또한, 제작되고 웨이퍼, 다이 또는 기판으로 이동될 수 있다. 후소결 단계는 처리량을 증가시킬 수 있다.

電子装置、及び電子装置を製造する方法

電子装置において、前記電子装置は、第１の構成要素（１）と第２の構成要素（２）とを有し、前記第１の構成要素（１）と前記第２の構成要素（２）とは、第１の金属を有する焼結層（３）によって互いに結合されており、前記構成要素（１，２）の少なくとも一方は、少なくとも１つのコンタクト層（４，４’）を有し、前記コンタクト層（４，４’）は、前記焼結層（３）と直接的にコンタクトされた状態で配置されており、前記第１の金属とは異なる第２の金属を有し、かつ金を含まない、電子装置が提示される。さらには、電子装置を製造する方法が提示される。

半導体装置の作製方法

半導体装置の製造方法

一种适用于高压大功率的整片晶圆及其制造方法

本申请涉及一种适用于高压大功率的整片晶圆及其制造方法，由于在晶圆制造的工序阶段，在原本源极焊盘的金属化层上加厚一层金属，从而使得在面对热量急剧累积导致芯片内部的物理结构发生变化的情况下金属化层不会损坏；同时由于采取的本申请的加厚方式，是在原本工艺制造的成品基础上新增的工艺步骤，不会对原本的晶圆制造工艺造成影响；本工艺步骤简单，投入成本低；使得晶圆制造的原本不适用高压大功率的芯片，可以在加厚之后进行适用，即通过本制造方法对原本的生产线增加制造新产品的功能。

バンプ形成方法

(57)【要約】 【課題】 簡単な方法で安定した接続が得られるバンプ 形成方法を提供すること。 【解決手段】 ワイヤーボンダーによって転写基板１上 に形成されたバンプ２を電子回路素子３の端子電極３ａ に転写することにより、バンプ２の平坦部分が狭い側を 電子回路素子３の端子電極３ａに接合しているので、バ ンプ２の平坦部分が広い側を回路基板に対する接続面と して使用することができ、平坦部分が狭い側を同接続面 として使用する従来のものに比べ、格段広い接続面積を 確保して安定した接続を行える。

一种适用于高压大功率的整片晶圆及其制造方法

本申请涉及一种适用于高压大功率的整片晶圆及其制造方法，由于在晶圆制造的工序阶段，在原本源极焊盘的金属化层上加厚一层金属，从而使得在面对热量急剧累积导致芯片内部的物理结构发生变化的情况下金属化层不会损坏；同时由于采取的本申请的加厚方式，是在原本工艺制造的成品基础上新增的工艺步骤，不会对原本的晶圆制造工艺造成影响；本工艺步骤简单，投入成本低；使得晶圆制造的原本不适用高压大功率的芯片，可以在加厚之后进行适用，即通过本制造方法对原本的生产线增加制造新产品的功能。

半导体封装及其制造方法

一种半导体封装，包括：衬底以及第一芯片结构和第二芯片结构，衬底包括：重分布构件，该重分布构件具有彼此相对的第一表面和第二表面，并且包括设置在第一表面上的焊盘结构和电连接到焊盘结构的重分布层；互连芯片，设置在重分布构件的第二表面上，并且包括电连接到重分布层的互连电路；过孔结构，设置在互连芯片周围，并且电连接到重分布层；密封剂，密封互连芯片和过孔结构中的每一个的至少一部分；以及凸块结构，设置在密封剂上，第一芯片结构和第二芯片结构设置在重分布构件的第一表面上，并且电连接到焊盘结构。

一种面板级封装可焊性镀层的制作方法

本发明申请公开了一种面板级封装可焊性镀层的制作方法，包括以下步骤：涂胶步骤：在封装面板暴露焊盘的一面涂覆粘接胶；蚀刻步骤：在涂粘接胶的一面蚀刻出缺口，以完全暴露出焊盘；焊接步骤：在缺口处涂上焊料，缺口处焊料与焊盘焊接为一体，形成焊柱；研磨步骤：将焊柱和粘接胶研磨，研磨面为一平面；去胶步骤，本申请通过粘接胶涂覆、蚀刻、填焊料、焊接和去胶，形成凸出的焊层，所用的设备都是产线现有的设备，不需要额外采购其他特别的设备，不需要采用昂贵的化学药水，相对于电镀锡和化锡工艺，成本降低，工艺简单，可以根据实际生产的需要制作焊层的厚度，没有焊层的损失风险，产品设计的自由度好。

一种功率芯片混合凸点的结构、制作方法及半导体器件

本发明申请公开了一种功率芯片混合凸点的结构、制作方法及半导体器件，包括源极镀焊层步骤：在晶圆表面涂覆粘接胶并蚀刻后暴露出源极，源极区镀覆一层焊层；金属片电镀步骤：提供一覆层板，在覆层板金属层面贴附感光膜并蚀刻，后暴露出金属层面并在该处镀覆镀层，去除感光膜和覆层板基体，并切割为单一金属片；源极凸点制作步骤：在源极涂覆焊料，将金属片镀层面贴附在焊料上并焊接牢固，完成源极凸点制作；栅极凸点制作步骤：将铜球通过引线键合的方式在栅极上制作凸点，本申请通过采用混合方式分开制作凸点，避免焊接过程中源极和栅极两个区域存在连接短路的风险，导电散热性能好，工艺简单，降本增效。

用于形成焊料凸块的系统和方法

一种用于形成焊料凸块(122)的方法包括：制备转移模具(100)，该转移模具具有焊料柱(112)，该焊料柱(112)从模具衬底(102)延伸并且穿过第一光致抗蚀剂层(104)并且具有部分地由第二光致抗蚀剂层(108)限定的形状，该第二光致抗蚀剂层(108)在转移焊料之前被去除；提供具有可润湿焊盘(120)的器件衬底(114)：将转移模具(100)和器件衬底(114)置于对准接触中，使得焊料柱(112)与可润湿焊盘(120)接触；在所述焊料柱(112)与所述可润湿焊盘(120)之间形成金属接合，例如，采用冷焊或回流工艺去除所述模具衬底(102)和所述第一光致抗蚀剂层(104)。模具衬底(102)和转移模具(100)可以是柔性的。转移模具可以包括以下至少一个：在模具衬底(402)之上的润湿层，在这种情况下，包括铝的柱(112)可以被沉积和回流：在模具衬底(402)之上的籽晶层以及在第二光致抗蚀剂层(408)之上的非润湿层。器件衬底(114、502)可以包括通孔(118、504)并且可以是由硅、玻璃和/或有机衬底材料制成的内插器。该方法可以进一步包括将该内插器(I14，502)附接到量子位半导体器件(超导芯片)(300，516)上，其中该量子位半导体器件(300，516)包括约瑟夫逊结(304，518)，并且其中将该内插器(114，502)附接到该量子位半导体器件(300，516)上包括将穿过该内插器(11，502)的孔(118，504)与该约瑟夫逊结(304，518)对准以便提供用于访问该约瑟夫逊结(304，518)的路径，特别是对其设计频率做出调整。该焊料柱(122)可以是围绕该量子位半导体器件(300)与该内插器(114)之间的该孔(118)形成的多个焊料柱中的一个，用于提供该约瑟夫逊结(304)的热隔离量，从而在该量子位周围并且在该内插器(114)与该超导芯片(300)之间形成一个圆形壁(200A，200B)，其中该圆形壁(200A，200B)可以包括穿过其中的至少一个空隙(202)。焊料柱(512)可以是转移模具的多个焊料柱(512)中的一个，包括具有第一直径的第一焊料柱(512)和具有第二直径的第二焊料柱(512)，第一直径大于第二直径。器件衬底(602)可以包括半导体衬底，该半导体衬底包括深凹部(604)，其中，电路组件(608)可以包括在深凹部(604)中。转移模具(100)的制备可包括：对第一和第二光致抗蚀剂层(104、108)进行图案化以限定延伸穿过第一和第二光致抗蚀剂层(104、108)的凹部(110)，以及使用注塑焊接(IMS)来用焊料填充凹部(110)以形成焊料柱(112)。可替代地，转移模具的制备可包括：图案化第一光致抗蚀剂层和第二光致抗蚀剂层(404、408)以限定延伸穿过第一光致抗蚀剂层和第二光致抗蚀剂层(404、408)的凹部(410)：形成籽晶层，其中，籽晶层的至少一部分设置在凹部(410)中；以及使用电镀来用焊料填充所述凹部(410)并形成所述焊料柱。柱(112)可以是由镀铜或铜柱凸块形成的3D金属柱。

Elektronische Vorrichtung und Verfahren zur Herstellung einer elektronischen Vorrichtung

Elektronische Vorrichtung mit einem ersten Bauteil (1) und einem zweiten Bauteil (2), die mit einer Sinterschicht (3) mit einem ersten Metall miteinander verbunden sind,wobei zumindest eines der Bauteile (1, 2) zumindest eine Kontaktschicht (4, 4') aufweist, die in unmittelbarem Kontakt mit der Sinterschicht (3) angeordnet ist,wobei die zumindest eine Kontaktschicht (4,4') ein zweites, vom ersten Metall unterschiedliches Metall aufweist und frei von Gold ist, undwobei die Kontaktschicht (4, 4') unmittelbar auf einer Schicht (6, 6', 6") aus einem oxidierbaren Material aufgebracht ist,wobei die Kontaktschicht (4, 4') Rhodium und/oder Iridium aufweist,wobei das oxidierbare Material Titan, Nickel, Chrom und/oder Aluminium aufweist.

激光植金属凸台方法

本发明提出了一种激光植金属凸台方法，用于半导体晶片、芯片以及电路基板上的金属盘植金属凸台。金属箔(5)贴盖金属盘(11)，采用激光切割分离出底层金属箔(51)，之后又金属箔(5)贴盖在底层金属箔(51)上，又激光切割分离出第二层金属箔(52)，这样若干层金属箔累叠构成金属凸台。本发明利用激光精准微小切割，设备造价低，工序简化，效率高。

Three-dimensional integrated circuit structures and methods of forming the same

Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps.

用于安装导电球的设备

提供一种用于安装导电球的设备，且更具体地说，提供一种可防止在通过使用形成于掩模中的安装孔将导电球安装在基底上的工艺期间的缺陷且还可将具有较小大小的导电球有效地安装在基底上的用于安装导电球的设备。根据用于安装导电球的设备，安装导电球的工艺可通过防止掩模的变形从而实现工艺的高质量而不遗失任何导电球来执行。

Three-dimensional integrated circuit structures and methods of forming the same

Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps.

Semiconductor substrate and semiconductor package structure having the same

A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.

Metal cored solder decal structure and process

A system of producing metal cored solder structures on a substrate includes: a decal having a plurality of apertures, the apertures being tapered from a top surface to a bottom surface of the decal; a carrier configured for positioning beneath the bottom of the decal, the carrier having cavities in a top surface and the cavities located in alignment with the apertures of the decal; the decal being configured for positioning on the carrier having the decal bottom surface in contact with the carrier top surface to form feature cavities defined by the decal apertures and the carrier cavities, the feature cavities being shaped to receive a plurality of metal elements therein, the feature cavities configured for receiving molten solder being cooled in the cavities, the decal being separable from the carrier to partially expose metal core solder contacts; and receiving elements of a substrate being configured to receive the metal core solder contacts thereon, and the metal core solder contacts being exposed and positioned on the substrate.

Tall and fine pitch interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

Semiconductor packages and methods of packaging semiconductor devices

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.

Reflow film, solder bump formation method, solder joint formation method, and semiconductor device

The present invention relates to a reflow film containing a thermoplastic resin which is dissolvable in a solvent, and solder particles, wherein the solder particles are dispersed in the film, and also relates to a solder bump formation method which comprises: (A) a step of mounting the reflow film on the electrode surface side of a substrate, (B) a step of mounting and fixing a flat plate, (C) a step of heating, and (D) a step of dissolving and removing the reflow film, and herewith, a reflow film is provided which, by causing localization of the solder component on the electrodes of the substrate by self-assembly, exhibits excellent storage properties, transportability and handling properties during use, and can form solder bumps or solder joints selectively on only the electrodes.

Semiconductor package and method of manufacturing the same

Provided is a semiconductor package and a method of making same, including a first package substrate; a first semiconductor chip mounted on the first package substrate and having a first pad and a second pad, wherein the first pad is provided on a top of the first semiconductor chip and the second pad is provided on a bottom of the first semiconductor chip, the bottom being an opposite surface of the top; and a clad metal provided on the first pad and electrically connecting the first semiconductor chip to one of a second semiconductor chip and second package substrate provided on the top of the first semiconductor chip.

Die attachment for packaged semiconductor device

A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.

Semiconductor substrate and semiconductor package structure having the same

The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump. The conductive circuit layer is recessed from the top surface of the insulating layer, and includes at least one pad. The conductive bump is disposed on the at least one pad. A side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space. The conductive material is electrically connected the conductive bump and the semiconductor chip, and a portion of the conductive material is disposed in the accommodating space.