Chip package with plank stack of semiconductor dies

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...

Method for Manufacturing Metal Powder

A method for manufacturing metal powder comprising: providing a basic metal salt solution; contacting the basic metal salt solution with a reducing agent to precipitate metal powder therefrom; and recovering precipitated metal powder from the solvent.

METHOD OF FORMING A SOLDER BUMP STRUCTURE

A solder bump structure includes a pillar formed on an electrode pad. The pillar has a concave curve-shaped surface and a geometry defined at least in part by dimensions including a first height greater than a first width. The solder bump structure further includes solder formed on the concave curve-shaped surface of the pillar. The solder has a convex top surface and having dimensions including a second height greater than a second width due to the geometry of the pillar. 1. A solder bump structure comprising:a pillar formed on an electrode pad, the pillar having a concave curve-shaped surface and a geometry defined at least in part by dimensions including a first height greater than a first width; andsolder formed on the concave curve-shaped surface of the pillar, the solder having a convex top surface and having dimensions including a second height greater than a second width due to the geometry of the pillar.2. The solder bump structure according to claim 1 , wherein the solder is in contact with an entirety of the curve-shaped surface of the pillar.3. The solder bump structure according to claim 1 , wherein the pillar includes at least one material selected from the group consisting of: copper claim 1 , nickel claim 1 , silver and gold.4. The solder bump structure according to claim 1 , wherein a thickness of a central portion of the pillar is in a range of ⅕ to ⅔ of a length from a surface of the electrode pad to the convex top surface of the solder.5. The solder bump structure according to claim 4 , wherein the electrode pad includes aluminum.6. The solder bump structure according to claim 1 , wherein a thickness of a central portion of the pillar is in a range of 1 to 50 micrometers.7. The solder bump structure according to claim 1 , wherein the solder has a non-spherical shape.8. A solder bump structure comprising:a resist layer including an opening;a pillar formed on an electrode pad and in the opening of the resist layer, the pillar having a concave curve ...

Hybrid bonding structures, semiconductor devices having the same, and methods of manufacturing the semiconductor devices

Provided are a hybrid bonding structure, a solder paste composition, a semiconductor device, and a method of manufacturing the semiconductor device. The hybrid bonding structure includes a solder ball and a solder paste bonded to the solder ball. The solder paste includes a transient liquid phase. The transient liquid phase includes a core and a shell on a surface of the core. A melting point of the shell may be lower than a melting point of the core. The core and the shell are configured to form an intermetallic compound in response to the transient liquid phase at least partially being at a temperature that is within a temperature range of about 20° C. to about 190° C.

Package on package structure and method of manufacturing the same

A package on package structure includes a first substrate having a first region and a second region, a bump formed on the first region of the first substrate, a first semiconductor die bonded to the second region of the first substrate, and a semiconductor die package bonded to the first substrate. The bump includes a metallic structure and a plurality of minor elements dispersed in the metallic structure. The semiconductor die package includes a connector bonded to the bump, and the first semiconductor die is between the semiconductor die package and the first substrate.

Wafer level integration including design/co-design, structure process, equipment stress management and thermal management

A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises applying at least one stress compensating polymer layer to at least one of two heterogeneous wafers and low temperature bonding the two heterogeneous wafers to bond the stress compensating polymer layer to the other of the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, at least one of the heterogeneous wafers having a stress compensating polymer layer. The two heterogeneous wafers are low temperature bonded together to bond the stress compensating polymer layer to the other of the two heterogeneous wafers.

ADHESIVE COMPOSITION, ELECTRONIC-COMPONENT-MOUNTED SUBSTRATE AND

There are provided are an adhesive composition that keeps storage stability and further gives a cured product wherein metallic bonds are formed in the state that the cured product wets its components and is satisfactorily spread between the components (or parts), thereby turning excellent in adhesive property, electroconductivity, and reliability for mounting such as TCT resistance or high-temperature standing resistance; an electronic-component-mounted substrate using the same; and a semiconductor device. The adhesive composition comprises electroconductive particles (A) and a binder component (B), wherein the electroconductive particles (A) include a metal (a1) having a melting point equal to or higher than the reflow temperature and containing no lead, and a metal (a2) having a melting point lower than the reflow temperature and containing no lead, and the binder component (B) includes a thermosetting resin composition (b1) and an aliphatic dihydroxycarboxylic acid (b2). 2. The electronic component structure according to claim 1 , wherein R1 in the general formula (1) is an alkyl group having 1 to 5 carbon atom.3. The electronic component structure according to claim 1 , wherein the aliphatic dihydroxycarboxylic acid (b2) includes 2 claim 1 ,2-bishydroxymethylpropionic acid claim 1 , 2 claim 1 ,2-bishydroxymethylbutanoic acid claim 1 , and 2 claim 1 ,2-bishydroxymethylpentanoic acid.4. The electronic component structure according to claim 1 , wherein the reflow temperature is the temperature for mounting with SnAgCu cream solder.5. The electronic component structure according to claim 1 , wherein the reflow temperature is 260° C.6. The electronic component structure according to claim 1 , wherein the content of the aliphatic dihydroxycarboxylic acid (b2) is 0.1 part or more by weight and 20 parts or less by weight for 100 parts by weight of the metal (a2) having the melting point lower than the reflow temperature and containing no lead.7. The electronic component ...

Junction and electrical connection

A junction at which at least two conductors are connected together includes a compound region containing Cu, Sn and at least one element selected from the group consisting of Si, B, Ti, Al, Ag, Bi, In, Sb, Ga and Zn. The compound region forms a nanocomposite metal diffusion region with the conductor.

Advanced Solder Alloys For Electronic Interconnects

Improved electrical and thermal properties of solder alloys are achieved by the use of micro-additives in solder alloys to engineer the electrical and thermal properties of the solder alloys and the properties of the reaction layers between the solder and the metal surfaces. The electrical and thermal conductivity of alloys and that of the reaction layers between the solder and the -metal surfaces can be controlled over a wide range of temperatures. The solder alloys produce stable microstructures wherein such stable microstructures of these alloys do not exhibit significant changes when exposed to changes in temperature, compared to traditional interconnect materials. 1. A lead-free , antimony-free solder alloy comprising:(a) 10 wt. % or less of silver(b) 10 wt. % or less of bismuth(c) 3 wt. % or less of copper up to 1 wt. % of nickel', 'up to 1 wt. % of titanium', 'up to 1 wt. % of cobalt', 'up to 3.5 wt. % of indium', 'up to 1 wt. % of zinc', 'up to 1 wt. % of cerium, '(d) at least one of the following elements'} 0 to 1 wt. % of manganese', '0 to 1 wt. % of chromium', '0 to 1 wt. % of germanium', '0 to 1 wt. % of iron', '0 to 1 wt. % of aluminum', '0 to 1 wt. % of phosphorus', '0 to 1 wt. % of gold', '0 to 1 wt. % of gallium', '0 to 1 wt. % of tellurium', '0 to 1 wt. % of selenium', '0 to 1 wt. % of calcium', '0 to 1 wt. % of vanadium', '0 to 1 wt. % of molybdenum', '0 to 1 wt. % of platinum', '0 to 1 wt. % of magnesium', '0 to 1 wt. % of rare earths, '(e) optionally one or more of the following elements'}(f) the balance tin, together with any unavoidable impurities.2. A lead-free , solder alloy comprising:(a) 10 wt. % or less of silver(b) 10 wt. % or less of bismuth(c) 3 wt. % or less of copper(d) 4 wt % or less of antimony up to 1 wt % of Ni', 'up to 1 wt. % of titanium', 'up to 1 wt. % of cobalt', 'up to 3.5 wt. % of indium', 'up to 1 wt. % of zinc', 'up to 1 wt. % of cerium, '(e) at least one of the following elements'} 0 to 1 wt. % of manganese', '0 to 1 wt. ...

FORMING OF BUMP STRUCTURE

A technique for fabricating a bump structure is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared, in which the pads includes first conductive material. A metallic adhesion layer is coated on each pad. A bump base is formed on each pad by sintering conductive particles using a mold layer, in which the conductive particles includes second conductive material different from the first conductive material. 1. A method of fabricating a bump structure , the method comprising:preparing a substrate including a set of pads formed on a surface thereof, the pads comprising first conductive material;coating a metallic adhesion layer on each of the pads; andforming a bump on each of the pads by sintering conductive particles using a mold layer, the conductive particles comprising second conductive material different from the first conductive material.2. The method of claim 1 , wherein the mold layer has a set of openings each aligned with one of the pads and forming the bump on each of the pads comprises:disposing the mold layer on the substrate;filling conductive particles into the openings of the mold layer, the conductive particles filled in the openings of the mold layer being sintered to give a bump base on each of the pads; andfilling solder material into remaining space in each of the openings of the mold layer above the bump base to form a solder cap on each bump base.3. The method of claim 1 , wherein the first conductive material comprises Al and the second conductive material comprises Cu.4. The method of claim 2 , wherein the conductive particles are provided in a form of a paste and the bump base formed on each of the pads has a shape of a cup conforming to a contour of the opening of the mold layer and a bottom bonded to the pad by the metallic adhesion layer.5. The method of claim 2 , wherein the method further comprises:applying a resist layer over the surface of the substrate;patterning the resist layer to fabricate the ...

Semiconductor device

A semiconductor device includes an electric conductor, a semiconductor element, and a bonding layer. The electric conductor has a main surface and a rear surface opposite to the main surface in a thickness direction. The semiconductor element includes a main body and electrodes. The main body has a side facing the main surface of the conductor, and the electrodes each protrude toward the main surface from the side of the main body to be electrically connected to the main surface. The bonding layer is held in contact with the main surface and the electrodes. Each electrode includes a base portion in contact with the main body, and a columnar portion protruding toward the main surface from the base portion to be held in contact with the bonding layer, which is a sintered body of a metal powder.

Packaged semiconductor device with a particle roughened surface

A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.

METHOD OF FORMING A SOLDER BUMP STRUCTURE

A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer. 1. A method of forming a solder bump structure , comprising the steps of:filling conductive paste in an opening of a layer formed over an electrode pad;sintering the conductive paste in the opening to cause shrinkage of the conductive paste to form a conductive layer having a cone-shaped surface formed therein, the conductive layer covering a side wall of the opening and a surface of the electrode pad in the opening; andfilling solder in the cone-shaped surface on the conductive layer.2. The method according to claim 1 , wherein the step of filling conductive paste includes a step of screen-printing conductive paste containing metal nanoparticles in a solvent on the substrate.3. The method according to claim 1 , wherein the step of filling conductive paste includes a step of injecting conductive paste containing metal nanoparticles in a solvent into the opening.4. The method according to claim 1 , wherein the conductive paste includes at least one of copper claim 1 , nickel claim 1 , silver or gold.5. The method according to claim 1 , wherein a cross-section of the conductive layer has a conformal shape.6. The method according to claim 1 , wherein a thickness of a central portion of a cross-section of the conductive layer is in a range of ⅕ to ⅔ of a depth of the opening.7. The method according to claim 1 , further comprising a step of etching a surface of the ...

Advanced Solder Alloys For Electronic Interconnects

Improved electrical and thermal properties of solder alloys are achieved by the use of micro-additives in solder alloys to engineer the electrical and thermal properties of the solder alloys and the properties of the reaction layers between the solder and the metal surfaces. The electrical and thermal conductivity of alloys and that of the reaction layers between the solder and the -metal surfaces can be controlled over a wide range of temperatures. The solder alloys produce stable microstructures wherein such stable microstructures of these alloys do not exhibit significant changes when exposed to changes in temperature, compared to traditional interconnect materials.

Structures to enable a full intermetallic interconnect

A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

ELECTRICALLY CONDUCTIVE PASTE FOR FORMING PILLARS

The known electrolytic plating method is disadvantageous in that it is difficult to form thin pillars without being influenced by undercuts. The electroless plating method is disadvantageous in that it is difficult to form pillars in the same shape without voids. As a solution to these, the electrically conductive paste according to the present invention for forming pillars is used to make pillars by filling. This helps prevent undercuts, and it is also intended to provide metal pillars in the same shape with good reproducibility. The inventors found that an electrically conductive paste that is very small fine metal particles and contains a particular percentage of fine metal particles is extraordinarily advantageous in forming pillars. 1. An electrically conductive paste for forming pillars , the paste comprising:fine metal particles: anda protective agent, whereina diameter of the fine metal particles is less than 1 μm, and a percentage of the fine metal particles in the electrically conductive paste is 40% or more and less than 95% concentration by mass.2. The electrically conductive paste according to for forming pillars claim 1 , the paste further comprising a solvent having a boiling point of 250° C. or less.3. The electrically conductive paste according to for forming pillars claim 1 , wherein the protective agent contains an organic compound including a C8 to C200 polyethylene oxide structure.4. The electrically conductive paste according to for forming pillars claim 3 , wherein a percentage of the organic compound including a C8 to C200 polyethylene oxide structure is 15% concentration by mass or less of the entire paste.5. The electrically conductive paste according to for forming pillars claim 1 , wherein the fine metal particle are particles of silver claim 1 , copper claim 1 , or a composite thereof.6. A pillar made using the electrically conductive paste according to for forming pillars. The present invention relates to an electrically conductive ...

Wafer level integration including design/co-design, structure process, equipment stress management and thermal management

A method of manufacturing a multi-layer wafer is provided. The method comprises applying at least one stress compensating polymer layer to at least one of two heterogeneous wafers and low temperature bonding the two heterogeneous wafers to bond the stress compensating polymer layer to the other of the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, at least one of the heterogeneous wafers having a stress compensating polymer layer. The two heterogeneous wafers are low temperature bonded together to bond the stress compensating polymer layer to the other of the two heterogeneous wafers.

Electrode connection structure and electrode connection method

An electrode connection structure includes: a first electrode of an electrical circuit; and a second electrode of the electrical circuit that is electrically connected to the first electrode. The first and second electrodes are oppositely disposed in direct or indirect contact with each other. A plated lamination is substantially uniformly formed by plating process from a surface of a contact region and opposed surfaces of the first and second electrodes. A void near the surface of the contact region is filled by formation of the plated lamination. Portions of the plated lamination formed from the opposed surfaces of the first and second electrodes in a region other than the contact region are not joined together.

Solder paste, joining method using the same and joined structure

A solder paste including a metal component consisting of a first metal powder and a second metal powder having a melting point higher than that of the first metal, and a flux component. The first metal is Sn or an alloy containing Sn, the second metal is one of (1) a Cu—Mn alloy in which a ratio of Mn to the second metal is 5 to 30% by weight and (2) a Cu—Ni alloy in which a ratio of Ni to the second metal is 5 to 20% by weight, and a ratio of the second metal to the metal component is 36.9% by volume or greater.

Microelectronic assemblies

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Light emitting diode display device

A light emitting diode display device includes a display board comprising a plurality of unit pixels, a drive circuit board including a plurality of drive circuit regions corresponding to the plurality of unit pixels, and a plurality of bumps interposed between the plurality of unit pixels and the plurality of drive circuit regions. The plurality of unit pixels comprises a first unit pixel including a first P electrode. The plurality of drive circuit regions comprises a first drive circuit region corresponding to the first unit pixel and a first pad connected to a first drive transistor, the plurality of bumps includes a first solder in contact with the first pad, and a first bump on the first solder and including a first filler in contact with the first P electrode, the first solder includes at least one of tin and silver, and the first filler includes copper or nickel.

Semiconductor structure and manufacturing method thereof

The present disclosure provides a semiconductor structure, including a substrate, a conductive pad, a passivation layer, a recess, a bump pad, and a conductive bump. The conductive pad is disposed over the substrate. The passivation layer is disposed over the substrate and partially covers the conductive pad. The recess extends through the passivation layer and extends at least partially into the conductive pad. The bump pad is disposed over the passivation layer and within the recess; and the conductive bump is disposed over the bump pad. A method of manufacturing the semiconductor structure is also provided.

Reversed build-up substrate for 2.5d

A method of making an assembly can include forming a circuit structure defining front and rear surfaces, and forming a substrate onto the rear surface. The forming of the circuit structure can include forming a first dielectric layer coupled to the carrier. The first dielectric layer can include front contacts configured for joining with contacts of one or more microelectronic elements, and first traces. The forming of the circuit structure can include forming rear conductive elements at the rear surface coupled with the front contacts through the first traces. The forming of the substrate can include forming a dielectric element directly on the rear surface. The dielectric element can have first conductive elements facing the rear conductive elements and joined thereto. The dielectric element can include second traces coupled with the first conductive elements. The forming of the substrate can include forming terminals at a surface of the substrate.

Electrode connection method and electrode connection structure

Provided is an electrode connection method and the like which make it possible to connect tightly without leaving a gap, by connecting by plating while electrodes in an electrical circuit contact one another in a dot or linear pattern. Contact is made directly or indirectly in at least part of the interval between a plurality of electrically connected electrodes in an electrical circuit, and the interval between electrodes is plated and connected while a plating fluid flows around the periphery of the contact section. In addition, the contact section maintains a linear or dot pattern. Furthermore, nickel or a nickel alloy or copper or a copper alloy is used as the material for performing the plating, while the material for the surface of the electrodes to be connected is nickel or a nickel alloy, copper or a copper alloy, gold or a gold alloy, silver or a silver alloy, or palladium or a palladium alloy.

半导体封装及其制造方法

本发明公开了一种半导体封装，其中，半导体芯片和安装器件一起封装在半导体封装中。半导体封装包括半导体芯片、安装块和互连部件，在安装块上的第一安装器件安装在基板上，基板包括形成在其上的电路，互连部件被配置以将半导体芯片电连接至安装块。

semiconductor equipment

Encapsulated semiconductor chip with external contact pads and manufacturing method thereof

A method includes providing a carrier; applying a dielectric layer to the carrier; applying a metal layer to the dielectric layer; placing a first semiconductor chip on the metal layer with contact pads of the first semiconductor chip facing the metal layer; covering the first semiconductor chip with an encapsulation material; and removing the carrier.

Semiconductor device and its manufacturing method

(57)【要約】 【課題】 取り付け高さを低減すると同時に均一化し、 個々のチップ取り付けのための煩雑な工程を必要とせ ず、製造歩留りを向上し、チップの厚さばらつきに影響 されずに半導体装置の高さを均一化し、電気試験の一括 実行が可能な薄型半導体パッケージとしての半導体装置 およびその製造方法を提供する。 【解決手段】 厚さ方向の貫通孔を有する絶縁性のテー プ基材の上面に背面を上方に露出して半導体素子が搭載 され、半導体素子の側面周囲は封止樹脂層で封止され、 テープ基材の下面に形成された金属配線がテープ基材の 貫通孔の底部を画定し、厚さ方向の貫通孔を有するソル ダレジスト層が金属配線およびテープ基材の下面を覆 い、半導体素子のアクティブ面から下方に延びた接続端 子がテープ基材の貫通孔内に挿入され、導電性材料から 成る充填材が接続端子とテープ基材の貫通孔の内壁との 間隙を充填し接続端子と金属配線を電気的に接続してい る半導体装置。

Electrode connection method and electrode connection structure

Low-pressure is sintered powder

一种烧结粉末，其包含：具有从100nm至50μm的平均最长尺寸的第一类型的金属颗粒。

Low-cost flip-chip interconnect with an integrated wafer-applied photo-sensitive adhesive and metal-loaded epoxy paste system

Various exemplary embodiments provide materials and methods for flip-chip packaging technology. The disclosed flip-chip packaging technology can use a single B-stage wafer-applied photo-sensitive adhesive along with printed interconnects, which does not include conventional underfill materials and processes. In one embodiment, a photo-sensitive adhesive can be applied on a semiconductor die or a base substrate with conductive bumps printed in through-openings of the photo-sensitive adhesive. One or more semiconductor dies can be laterally packaged or vertically stacked on the base substrate using the printed conductive bumps as interconnects there-between.

METHOD FOR ASSEMBLING TWO INTEGRATED CIRCUITS AND CORRESPONDING STRUCTURE

Packaged semiconductor device with a particle roughened surface

A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.

Method for manufacturing metal powder

一种用于制造金属粉末的方法，包括：提供碱性金属盐溶液；使该碱性金属盐溶液与还原剂接触以从其中沉淀出金属粉末；以及从溶剂中回收所沉淀的金属粉末。

Substrate assembly with spacer element

Apparatuses, systems, and methods associated with spacer elements for maintaining a distance between a substrate and component during reflow are disclosed herein. In embodiments, a substrate assembly may include a substrate and a component. The component may be coupled to the substrate via a solder joint, wherein the solder joint may include a spacer element and solder, the spacer element to maintain a distance between the substrate and the component. Other embodiments may be described and/or claimed.

MICROSTRUCTURE DEVICE AND METHOD FOR MANUFACTURING MICROSTRUCTURE DEVICE

Semiconductor device and manufacturing method for the same

본 발명은 배리어 메탈의 형성 내지 제거가 불필요하며, 저비용이며, 또한 간편하고 고효율인 반도체 장치의 제조 방법 및 협피치로 형성된 미세한 범프를 갖는 고성능인 반도체 장치의 제공을 목적으로 한다. An object of the present invention is to provide a method of manufacturing a semiconductor device which is not required to form or remove a barrier metal, and which is low in cost, simple and highly efficient, and a high performance semiconductor device having fine bumps formed with narrow pitch. 본 발명의 반도체 장치의 제조 방법은, 반도체 기판(10)의 한쪽 주요면에 복수개의 전극 패드(12)를 형성하는 공정과, 상기 전극 패드(12)의 주연부를 덮어 절연층[예컨대, 무기 절연층(14) 및 유기 절연층(16)]을 형성하는 공정과, 상기 절연층(14 및 16) 상에 선택적으로 마스크층(20)을 형성하는 공정과, 상기 절연층(14 및 16)으로 덮이지 않는 전극 패드(12)의 표면을 청정화하는 공정과, 상기 절연층(14, 16) 및 상기 마스크층(20)에 의해 규정되는 영역에, 상기 전극 패드(12)에 접하여 외부 접속용 단자(46)를 형성하는 공정과, 상기 마스크층(20)을 제거하는 공정을 적어도 포함하는 것을 특징으로 한다. In the method of manufacturing a semiconductor device of the present invention, a step of forming a plurality of electrode pads 12 on one main surface of the semiconductor substrate 10 and an edge of the electrode pad 12 are covered with an insulating layer (for example, inorganic insulation). Layer 14 and organic insulating layer 16), selectively forming a mask layer 20 on the insulating layers 14 and 16, and the insulating layers 14 and 16 The process of cleaning the surface of the electrode pad 12 which is not covered, and the terminal for external connection in contact with the said electrode pad 12 in the area | region defined by the said insulating layers 14 and 16 and the said mask layer 20. And a step of forming the 46 and the step of removing the mask layer 20.

Junction surface and electric distribution

本发明提供一种不会产生空隙、裂纹等的高品质、高可靠度的电极接合部和电配线。将2个导体接合的接合部含有选自Si、B、Ti、Al、Ag、Bi、In、Sb、Ga的组中的至少一种、Cu和Sn，在其与导体之间形成有纳米复合结构的金属扩散区域。

Structures and methods for low temperature bonding

一種製造一組件之方法可包含在一第一構件的一基板的一第一表面形成一第一導電的元件；藉由曝露到一無電的電鍍浴以在該導電的元件的一表面形成導電的奈米粒子；並列該第一導電的元件的該表面以及在一第二構件的一基板的一主要的表面的一第二導電的元件的一對應的表面；以及至少在該些並列的第一及第二導電的元件的介面升高一溫度至一接合溫度，該些導電的奈米粒子在該接合溫度下係使得冶金的接合點形成在該些並列的第一及第二導電的元件之間。該些導電的奈米粒子可被設置在該第一及第二導電的元件的表面之間。該些導電的奈米粒子可以具有小於100奈米的長度尺寸。

Structures and methods for low temperature engagement

一种制造一组件的方法可包含在一第一构件的一基板的一第一表面形成一第一导电的元件；藉由曝露到一无电的电镀浴以在所述导电的元件的一表面形成导电的纳米粒子；并列所述第一导电的元件的所述表面以及在一第二构件的一基板的一主要的表面的一第二导电的元件的一对应的表面；以及至少在所述并列的第一及第二导电的元件的介面升高一温度至一接合温度，所述导电的纳米粒子在所述接合温度下使得冶金的接合点形成在所述并列的第一及第二导电的元件之间。所述导电的纳米粒子可被设置在所述第一及第二导电的元件的表面之间。所述导电的纳米粒子可以具有小于100纳米的长度尺寸。

Semiconductor device and process of prodution of same

장착 높이를 감소시키는 동시에 균일화하고 개개의 칩을 장착하는 복잡한 공정을 필요로 하지 않고, 제조 수율을 높이고, 칩 두께의 변화에 의해 영향을 받지 않고서 반도체 장치의 균일한 높이를 달성하고, 일괄하여 전기적 시험을 실행할 수 있는 반도체 장치, 특히 박형 반도체 패키지로서, 두께 방향의 관통홀을 갖는 절연성 테이프 기재의 상면에 배면을 위쪽으로 노출시켜 반도체 소자가 장착되고, 반도체 소자의 측면 주위는 밀봉 수지로 밀봉되고, 테이프 기재의 하면에 형성된 금속 배선이 테이프 기재의 관통홀의 저부를 한정하고, 두께 방향의 관통홀을 갖는 솔더 레지스트 층이 금속 배선 및 테이프 기재의 하면을 덮고, 반도체 소자의 활성면으로부터 아래쪽으로 연장된 접속 단자가 테이프 기재의 관통홀 내에 삽입되고, 도전성 재료로 이루어진 충전재가 접속 단자와 테이프 기재의 관통홀의 내벽 사이의 갭을 충전하고 접속 단자와 금속 배선을 전기적으로 접속하는 반도체 장치가 제공된다.

Method for manufacturing electronic component device

提供一种制造将芯片元件等安装在布线基板上的电子元件装置的方法，该方法生产效率高、能够降低成本、具有稳定的产品质量。把金属纳米粒子浆(1)施加在基板侧电极(23)上；在布线基板(22)和芯片元件(26)对好位置的状态下，施加负荷(30)，由此使金属纳米粒子浆(1)一直压缩变形到压缩变形极限厚度(31)；接着，加热金属纳米粒子浆(1)，由此得到烧结好金属纳米粒子的接合烧结体(6)，从而将基板侧电极(23)与芯片侧电极(27)相互接合在一起。

Cu-cored solder ball

Semiconductor package structure and method for manufacturing the same

A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pitch region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed.

Semiconductor device

【課題】 エレクトロマイグレーションの発生を抑制することが可能な半導体装置を提供する。 【解決手段】 半導体装置Ａ１０は、導電部材１０と、複数の電極２２を有する半導体素子２０と、導電部材１０と複数の電極２２との双方に接する接合層とを備える。前記接合層は、導電体である。複数の電極２２の各々は、基部と、前記基部から導電部材１０に向けて突出し、かつ前記接合層に接する柱状部とを有する。導電部材１０は、複数の第１リード１１、および複数の第２リード１２を含む。複数の電極２２は、半導体素子２０のスイッチング回路２１２Ａに導通する複数の第１電極２２Ａと、半導体素子２０の制御回路２１２Ｂに導通する複数の第２電極２２Ｂとを含む。複数の第１電極２２Ａの各々は、複数の第１リード１１のいずれかに電気的に接合されている。複数の第２電極２２Ｂの少なくともいずれかは、複数の第２リード１２のいずれかに電気的に接合されている。 【選択図】 図２

Cu core ball

Provided is a Cu core ball that is capable of suppressing soft errors and thus reducing connection failures. The Cu core ball is provided with a solder plating film that is formed on the surface of a Cu ball, wherein: the solder plating film comprises an Sn solder plating film or a lead-free solder alloy containing Sn as a major component and having a U content of 5 ppb or less and a Th content of 5 ppb or less; the purity of the Cu ball is 99.9-99.995% inclusive, the sum of the Pb and/or Bi contents thereof is 1 ppm or more, and the sphericity thereof is 0.95 or more; and the α ray amount of the obtained Cu core ball is 0.0200 cph/cm 2 or less.

Optical display package and the method thereof

The present invention includes a substrate with a glass plate, a plurality of oxide wires on the glass plate and a plurality of flip chip bumps on the oxide wires and an integrated circuit chip with a plurality of bump pads. The substrate and the integrated circuit chip are hot pressed with a predetermined bonding pressure and temperature to bond the bump pads to the flip chip bumps respectively by eutectic bonding.

Method for manufacturing metal powder

A method for manufacturing metal powder comprising: providing a basic metal salt solution; contacting the basic metal salt solution with a reducing agent to precipitate metal powder therefrom; and recovering precipitated metal powder from the solvent.

Copper paste for joining, method for manufacturing joined body, and joined body

A copper paste for joining, containing: copper particles; a polycarboxylic acid having a melting point of no more than 120°C; and a carrier fluid. A method for manufacturing a joined body, comprising: a first step in which a laminate is prepared that has a first member, the copper paste for joining and a second member, laminated in said order; and a second step in which the laminate is heated and the copper paste for joining is sintered, in a gas atmosphere having a hydrogen concentration of no more than 45%. The joined body comprises the first member, the second member, and the sintered body of the copper paste for joining which joins the first member and the second member.

Method of bonding

The present invention provides a bonding method in which a bonded portion having a sufficient bonding strength can be obtained at a relatively low temperature, for example, in die bonding a semiconductor chip. A metal paste 20 was applied to a semiconductor chip 10, the metal paste 20 consisting of metal powder of one or more kinds selected from gold powder, silver powder, platinum powder, and palladium powder having a purity not lower than 99.9 wt % and an average particle diameter of 0.005 μm to 1.0 μm and an organic solvent. After being applied, the metal paste 20 was dried in a vacuum in a dryer. The chip was heated at 230° C. for 30 minutes to sinter the metal paste, by which a metal powder sintered compact 21 was formed. Next, a nickel plate 30 was placed on the semiconductor chip 10, and bonded to the semiconductor chip 10 by heating and pressurization.

Bonded body manufacturing method and bonding material

Method for manufacturing metal powder

A method for manufacturing metal powder comprising: providing a basic metal salt solution; contacting the basic metal salt solution with a reducing agent to precipitate metal powder therefrom; and recovering precipitated metal powder from the solvent.

Metallic nanoink and process for producing the metallic nanoink, as well as methods for chip bonding and device for chip bonding using the metallic nanoink

Metallische Nanotinte zum Bonden einer Elektrode eines Halbleiterchips und einer Elektrode eines Substrats und/oder Bonden einer Elektrode eines Halbleiterchips und einer Elektrode eines anderen Halbleiterchips durch Sintern unter Druck, wobei die metallische Nanotinte zubereitet wird, indem in ein organisches Lösungsmittel metallische Nanopartikel, deren Oberflächen mit einem Dispergator und Sauerstoff beschichtet sind, gemischt werden. Metallic nanoink for bonding an electrode of a semiconductor chip and an electrode of a substrate and / or bonding an electrode of a semiconductor chip and an electrode of another semiconductor chip by sintering under pressure, wherein the metallic nanoink is prepared by adding into an organic solvent metallic nanoparticles whose surfaces a dispersing agent and oxygen are mixed.

Semiconductor package and manufacturing method thereof

在此揭露的是一種半導體封裝，其中一半導體晶片與一安裝元件被一起封裝。該半導體封裝包括：一半導體晶片、一安裝塊以及一互連部分。該安裝塊上為一第一安裝元件被安裝在一基板上，該基板上包括形成的一電路。該互連部分被配置為將該半導體晶片電性連接到該安裝塊。

Electronic component module and method of manufacturing electronic component module

接合材料の内部まで確実に焼結させることができる銅粒子ペーストを用いて形成した、銅粒子の耐酸化性に優れ、かつ、接合信頼性の高い接合部を備えた電子部品モジュール、およびその製造方法を提供する。粒度分布の粒径ピークが０．１〜５．０μｍの範囲、焼結前の平均結晶子径が３０〜１００ｎｍの範囲にあり、凝集を抑制する分散剤を粒子表面に有していない銅粒子と、記銅粒子を焼結させる際の焼成温度で還元作用を奏する有機化合物とを含有する銅粒子ペーストを用いて、外部端子を接続対象に接合する。また、電子部品３１が備える外部端子３３が、接合材料３４を介して、接続対象３６に電気的および機械的に接続された構造を有する電子部品モジュール３０において、上記接合材料を、上記の銅粒子ペーストを焼き付けることにより形成される、平均結晶子径が６０〜１５０ｎｍの範囲にある銅焼結体とする。 An electronic component module that is formed using a copper particle paste that can be surely sintered to the inside of a bonding material, and that has a bonding portion with excellent oxidation resistance of copper particles and high bonding reliability, and its manufacture Provide a method. Copper particles that have a particle size peak in the range of 0.1 to 5.0 μm in the particle size distribution, an average crystallite size before sintering in the range of 30 to 100 nm, and do not have a dispersant for suppressing aggregation on the particle surface And the external terminal is joined to a connection object using the copper particle paste containing the organic compound which has a reduction effect at the calcination temperature at the time of sintering the copper particle. Further, in the electronic component module 30 having a structure in which the external terminal 33 included in the electronic component 31 is electrically and mechanically connected to the connection target 36 via the bonding material 34, the bonding material is the copper particle. A copper sintered body having an average crystallite diameter in the range of 60 to 150 nm formed by baking the paste.

Electronic component packaging method, semiconductor module, and semiconductor device

本发明提供可实现缩小安装面积及薄形化的电子部件的安装方法、半导体模块及半导体器件。本发明的一个课题解决手段是将形成于基板上的电极和形成于电子部件上的电极进行接合的电子部件的安装方法，所述接合通过凝聚了至少一种金属粒子的金属层来进行接合。而且，所述金属粒子以平均粒径为1～50nm构成。另外，最好是构成其厚度为5～100μm的金属层。

Semiconductor device and method for manufacturing the same

A semiconductor device includes a wiring board having a plurality of conductive wires aligned on an insulating base material and a board bump with a plated metal formed on each conductive wire so as to cover an upper surface and both sides of the conductive wire; and a semiconductor chip mounted on the wiring board, with electrodes of the semiconductor chip being connected to the conductive wires via the board bumps. Chip bumps are formed on the electrodes of the semiconductor chip. The electrodes of the semiconductor chip are connected to the conductive wires via a bond between the chip bumps and the board bumps. Protruding portions are formed by part of the plated metal of the board bumps at the bonded portion peeling off and protruding outwardly from a bonding surface of the chip bumps and the board bumps. Mechanical damage to the semiconductor chip caused by ultrasonic vibrations applied during process of mounting the semiconductor chip.

Semiconductor device and manufacturing method thereof

導電ポスト８と被接合部材である半導体チップ６や導電パターン付絶縁基板４を金属ナノ粒子を用いて金属粒子接合する場合に、導電ポスト８の先端の底面１２を凹状にすることで、強固な接合層を得ることができる。 When the metal posts are bonded to the conductive posts 8 and the semiconductor chip 6 or the conductive pattern-attached insulating substrate 4 which are members to be bonded using metal nanoparticles, the bottom surface 12 at the front end of the conductive posts 8 is made concave so as to be strong. A bonding layer can be obtained.

Forming of bump structure

A technique for fabricating a bump structure is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared, in which the pads includes first conductive material. A metallic adhesion layer is coated on each pad. A bump base is formed on each pad by sintering conductive particles using a mold layer, in which the conductive particles includes second conductive material different from the first conductive material.

Conductive connection member and method for producing conductive connection member

A conductive connecting member formed on a bonded face of an electrode terminal of a semiconductor or an electrode terminal of a circuit board, the conductive connecting member comprising a porous body formed in such manner that a conductive paste containing metal fine particles (P) having mean primary particle diameter from 10 to 500 nm and an organic solvent (S), or a conductive paste containing the metal fine particles (P) and an organic dispersion medium (D) comprising the organic solvent (S) and an organic binder (R) is heating-treated so as for the metal fine particles (P) to be bonded, the porous body being formed by bonded metal fine particles (P) having mean primary particle diameter from 10 to 500 nm, a porosity thereof being from 5 to 35 volume%, and mean pore diameter being from 1 to 200 nm.

Semiconductor device package and method of manufacturing the same

本公开的至少一些实施例涉及一种半导体装置封装及一种制造所述半导体装置封装的方法。所述半导体装置封装包含衬底、第一焊膏、电接点和第一囊封体。所述衬底包含导电衬垫。所述第一焊膏安置在所述衬垫上。所述电接点安置在所述第一焊膏上。所述第一囊封体囊封所述电接点的一部分且暴露所述电接点的表面。所述电接点具有背离所述衬底的表面。所述电接点的熔点大于所述第一焊膏的熔点。所述第一囊封体包含面朝所述衬底的第一表面和与所述第一表面相对的第二表面。所述第一囊封体的所述第二表面暴露于空气。

Semiconductor device

Airtightness of a hollow portion is maintained, and yield and durability are improved. A semiconductor device 1 includes a device substrate 2, a semiconductor circuit 3, a sealing frame 7, a cap substrate 8, via portions 10, electrodes 11, 12 and 13, and a bump portion 14 or the like. A hollow portion 9 in which the semiconductor circuit 3 is housed in an airtight state is provided between the device substrate 2 and the cap substrate 8. The bump portion 14 connects all the via portions 10 and the cap substrate 8. Thus, the via portions 10 can be reinforced using the bump portion 14A.

Electrically conductive paste materials and applications

A structure and method of fabrication are described. The structure is a combination of a polymeric material and particles, e.g. Cu, having an electrically conductive coating, e.g. Sn. Heat is applied to fuse the coating of adjacent particles. The polymeric material is a thermoplastic. The structure is disposed between two electrically conductive surfaces, e.g. chip and substrate pads, to provide electrical interconnection and adhesion between their pads.

Package structure and method of optical display

Improving mechanical and thermal reliability in varying form factors

A system for packaging integrated circuits includes an integrated circuit having one or more integrated circuit terminals. The system for packaging integrated circuits also includes a substrate having one or more substrate terminals. The system for packaging integrated circuits further includes an electrically conductive adhesive in communication with the integrated circuit terminals and the substrate terminals. The electrically conductive adhesive establishes an electrical connection between each of the one or more integrated circuit terminals and the one or more substrate terminals. The electrical connection between each of the one or more integrated circuit terminals and the one or more substrate terminals are enclosed in a dielectric. The system for packaging integrated circuits includes a second adhesive in communication with the integrated circuit and the substrate, wherein the second adhesive couples the integrated circuit and substrate together.

Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages

A nano-sized metal particle composite includes a first metal that has a particle size of about 50 nanometer or smaller. A wire interconnect is in contact with a reflowed nanosolder and has the same metal or alloy composition as the reflowed nanosolder. A microelectronic package is also disclosed that uses the reflowed nanosolder composition. A method of assembling a microelectronic package includes preparing a wire interconnect template. A computing system includes a nanosolder composition coupled to a wire interconnect.

Method of bonding

본 발명은 반도체 칩의 다이본딩 등에 있어서, 비교적 저온에서 충분한 접합강도를 갖는 접합부를 얻을 수 있는 방법을 제공한다. 반도체 칩(10)에 순도가 99.9 중량% 이상이고, 평균 입경이 0.005 ㎛~1.0 ㎛인 금분말, 은분말, 백금분말, 또는 팔라듐분말로부터 선택되는 1종 이상의 금속분말과, 유기 용제로 되는 금속 페이스트(20)를 도포하였다. 금속 페이스트(20)를 도포한 후, 이를 건조기에서 진공 건조하고, 칩을 230℃에서 30분 가열하여 금속 페이스트를 소결(sintering)하여, 분말 금속 소결체(21)로 하였다. 다음으로, Ni판(30)을 반도체 칩(10) 상에 올려놓고, 가열 및 가압하여 접합한다. The present invention provides a method for obtaining a bonded portion having sufficient bonding strength at a relatively low temperature in die bonding of a semiconductor chip. At least one metal powder selected from gold powder, silver powder, platinum powder, or palladium powder having a purity of 99.9% by weight or more and an average particle diameter of 0.005 µm to 1.0 µm in the semiconductor chip 10, and a metal which is an organic solvent Paste 20 was applied. After apply | coating the metal paste 20, it was vacuum-dried in the dryer, the chip was heated at 230 degreeC for 30 minutes, and the metal paste was sintered, and it was set as the powder metal sintered compact 21. Next, the Ni plate 30 is placed on the semiconductor chip 10, and heated and pressed to join.

Semiconductor device and method of making bumpless flipchip interconnect structures

A semiconductor device includes a substrate with contact pads. A mask is disposed over the substrate. Aluminum-wettable conductive paste is printed over the contact pads of the substrate. A semiconductor die is disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure over the contact pads of the substrate. The contact pads include aluminum. Contact pads of the semiconductor die are disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure between the contact pads of the semiconductor die and the contact pads of the substrate. The interconnect structure is formed directly on the contact pads of the substrate and semiconductor die. The contact pads of the semiconductor die are etched prior to reflowing the aluminum-wettable conductive paste. An epoxy pre-dot to maintain a separation between the semiconductor die and substrate.

Display panel comprising micro light-emitting diodes and a connection layer comprising conductive particles and method for making same

A micro LED display panel includes a substrate, a plurality of first metal electrodes and a plurality of metal pads on a surface of the substrate, a connection layer on the substrate, a plurality of micro LEDs on a side of the connection layer away from the substrate. The connection layer includes conductive particles. Each of the micro LEDs is coupled to at least one of the first metal electrode. A side of each of the metal pads away from the substrate is coupled to some of the conductive particles in the connection layer to form a metal retaining wall. The metal retaining walls enhance structural strength of the micro LED display panel and avoid breakage of any of the micro LEDs.

Semiconductor device and semiconductor device manufacturing method

A semiconductor device includes a substrate that includes a first insulating layer, a conductive layer on the first insulating layer, a second insulating layer on the conductive layer, and an opening that passes through the conductive layer and the second insulating layer and in which part of the conductive layer is exposed, a conductive material that contacts at least the first insulating layer and the part of the conductive layer in the opening, and a semiconductor chip that has an electrode extending towards the first insulating layer within the opening and contacting the conductive material.

Conductive connecting member and manufacturing method of same

本发明提供由热循环特性优异的金属多孔质体构成的导电性凸块、导电性芯片焊接部等导电连接部件。所述导电连接部件在半导体元件的电极端子或电路基板的电极端子的接合面形成，其特征在于，该导电连接部件是对包含平均一次粒径为10nm～500nm的金属微粒(P)和有机溶剂(S)或者由有机溶剂(S)与有机粘结剂(R)构成的有机分散介质(D)的导电性糊料进行加热处理而使金属微粒彼此结合所形成的金属多孔质体，该金属多孔质体的空隙率为5体积%～35体积%，构成该金属多孔质体的金属微粒的平均粒径为10nm～500nm的范围，且存在于该金属微粒间的平均空穴直径为1nm～200nm的范围。

Method of forming a solder bump structure

A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer.

Methods for forming pillar bumps on semiconductor wafers

本案所含之請求標的揭示用於在半導體晶圓上的凸塊下金屬墊上形成垂直金屬柱及在該金屬柱之頂表面上施用不連續焊帽的方法，其中該金屬柱是由至少一光阻層所界定而成。該方法包括加熱多元素金屬膏，該多元素金屬膏含有可變量的金屬粉末、熔點降低劑及助焊劑，以使金屬粉末燒結成金屬柱並同時使該金屬柱附著於該凸塊下金屬墊。

Method for producing metal ball, joining material, and metal ball

Produced is a metal ball which suppresses an emitted α dose. Contained are the steps of melting a pure metal by heating the pure metal at a temperature which is higher than a boiling point of an impurity to be removed, higher than a melting point of the pure metal, and lower than a boiling point of the pure metal, the pure metal containing a U content of 5 ppb or less, a Th content of 5 ppb or less, purity of 99.9% or more and 99.995% or less, and a Pb or Bi content or a total content of Pb and Bi of 1 ppm or more, and the pure metal having the boiling point higher than the boiling point at atmospheric pressure of the impurity to be removed; and sphering the molten pure metal in a ball.

Cu-cored solder ball

Method of forming a solder bump structure

A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer.

Terminal structure and manufacturing method thereof, and electronic device and manufacturing method thereof

A conductor having a projecting portion is formed which forms a terminal portion. An uncured prepreg including a reinforcing material is closely attached to the conductor and the prepreg is cured to form an insulating film including the reinforcing material. When the prepreg is closely attached, the prepreg is stretched by the projecting portion, so that a region of the prepreg, which is closely attached to the conductor, can be thinner than the other region of the prepreg. Then, by reducing the thickness of the entire insulating film, an opening can be formed in the portion having a smaller thickness. The step of reducing the thickness can be performed by etching. Further, it is preferable not to remove the reinforcing material in this step. The strength of a terminal and an electronic device can be increased by leaving the reinforcing material at the opening.

Cu core ball

소프트 에러를 억제하여 접속 불량을 저감시킬 수 있는 Cu 핵 볼을 제공한다. Cu 볼의 표면에 형성된 땜납 도금 피막은, Sn 땜납 도금 피막 또는 Sn을 주성분으로 하는 무연 땜납 합금으로 이루어지고, U의 함유량이 5ppb 이하이고, Th의 함유량이 5ppb 이하이고, 상기 Cu 볼의 순도는 99.9％ 이상 99.995％ 이하이고, Pb 및/또는 Bi의 함유량의 합계량이 1ppm 이상, 진구도가 0.95 이상이고, 얻어진 Cu 핵 볼의 α선량은 0.0200cph/㎠ 이하이다. Thereby providing a Cu nucleus ball capable of suppressing soft errors and reducing connection defects. Wherein the solder plated film formed on the surface of the Cu ball is made of a Sn solder plated film or a lead-free solder alloy containing Sn as a main component, the content of U is 5 ppb or less, the content of Th is 5 ppb or less, The total amount of Pb and / or Bi is 1 ppm or more, and the sphericity is 0.95 or more. The alpha dose of the obtained Cu nuclei balls is 0.0200 cph / cm 2 or less.

Semiconductor package structure and manufacturing method thereof

本公开提供了一种半导体封装结构，所述半导体封装结构包含：半导体管芯表面，所述半导体管芯表面具有较窄间距区域和与所述较窄间距区域相邻的较宽间距区域；多个第一类型导电柱，所述第一类型导电柱位于所述较窄间距区域中，所述第一类型导电柱中的每个第一类型导电柱具有铜‑铜界面；以及多个第二类型导电柱，所述第二类型导电柱位于所述较宽间距区域中，所述第二类型导电柱中的每个第二类型导电柱具有铜‑焊料界面。还公开了一种用于制造本文所述的半导体封装结构的方法。

Hybrid manufacturing for integrated circuit devices and assemblies

Hier werden mikroelektronische Baugruppen, die unter Verwendung einer hybriden Herstellung gefertigt werden, sowie zugehörige Vorrichtungen und Verfahren offenbart. So wie „hybride Herstellung“ hier verwendet wird, bezieht es sich auf das Fertigen einer mikroelektronischen Baugruppe, indem mindestens zwei IC-Strukturen zusammen angeordnet werden, die durch unterschiedliche Hersteller unter Verwendung unterschiedlicher Materialien oder unterschiedlicher Herstellungstechniken gefertigt werden. Zum Beispiel kann eine mikroelektronische Baugruppe eine erste IC-Struktur, die erste Zwischenverbindungen beinhaltet, und eine zweite IC-Struktur beinhalten, die zweite Zwischenverbindungen beinhaltet, wobei mindestens einige der ersten und zweiten Zwischenverbindungen eine Auskleidung und ein elektrisch leitfähiges Füllmaterial beinhalten können, und wobei sich eine Materialzusammensetzung der Auskleidung und/oder des elektrisch leitfähigen Füllmaterials der ersten Zwischenverbindungen von einer Materialzusammensetzung der Auskleidung und/oder des elektrisch leitfähigen Füllmaterials der zweiten Zwischenverbindungen unterscheiden kann. Disclosed herein are microelectronic assemblies fabricated using hybrid fabrication, as well as associated devices and methods. As used herein, "hybrid fabrication" refers to fabricating a microelectronic assembly by assembling at least two IC structures together that are manufactured by different manufacturers using different materials or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, wherein at least some of the first and second interconnects may include a liner and an electrically conductive filler material, and wherein a material composition of the lining and/or the electrically conductive filling material of the first interconnects can differ from a material composition of the ...

Pin-grid-array-type semiconductor package

A semiconductor package of a pin-grid-array type includes a bump pad on a first substrate, a metal socket on a second substrate, a core material for reverse reflow on the bump pad, and solder paste or a solder bump forming a solder layer on the core material for reverse reflow. The solder paste or the solder bump is in contact with the bump pad. The core material for reverse reflow and the solder paste or the solder bump bonded to the core material for reverse reflow are used as a pin and detachably attached to the metal socket. The core material for reverse reflow includes a core, a first metal layer directly coated on the core, and a second metal layer directly coated on the first metal layer.

Flip chip mounting method and method for connecting substrates

A flip chip mounting method which is applicable to the flip chip mounting of a next-generation LSI and high in productivity and reliability as well as a method for connecting substrates are provided. A circuit board 10 having a plurality of connecting terminals 11 and a semiconductor chip 20 having a plurality of electrode terminals 21 are disposed in mutually facing relation and a resin 13 containing conductive particles 12 and a gas bubble generating agent is supplied into the space therebetween. In this state, the resin 13 is heated to generate gas bubbles 30 from the gas bubble generating agent contained in the resin 13. The resin 13 is pushed toward the outside of the generated gas bubbles 30 by the growth thereof. The resin 13 pushed to the outside is self-assembled in the form of columns between the respective terminals of the circuit board 10 and the semiconductor chip 20. In this state, by pressing the semiconductor chip 20 against the circuit board 10, the conductive particles 12 contained in the resin 13 self-assembled between the facing terminals are brought into contact with each other to provide electrical connection between the terminals.

Conductive paste for die bonding, and die bonding method using conductive paste for die bonding

The present invention provides a conductive paste for die bonding comprising a metal powder and an organic solvent, the metal powder comprising: one or more metal particles selected from a silver powder, a palladium powder, and a copper powder, the metal particles having a purity of 99.9% by mass or higher and an average particle size of 0.01 µm to 1.0 µm; and a coating layer made of gold covering at least part of the metal particles. The conductive paste according to the present invention can suppress the occurrence of defects such as voids in a bonded part when a semiconductor element or the like is die-bonded to a substrate.

Patent JPWO2021066026A1

Cu CORE BALL, SOLDER PASTE, FORMED SOLDER, Cu CORE COLUMN, AND SOLDER JOINT

Semiconductor device

保持中空部的氣密性且提昇良率及耐久性。半導體裝置1具有裝置基板2、半導體電路3、封裝框7、蓋基板8、路由部10、電極11、12、13、及凸塊部14等。裝置基板2及蓋基板8之間，設有以氣密狀態收容半導體電路3的中空部9。凸塊部14連結全部的路由部10及蓋基板8。藉此，使用凸塊部14A能補強路由部10。

焼結材料、及びそれを用いる接着方法

【課題】各種コンポーネントを接着（接合）するための方法を提供する。【解決手段】フリップチップなどのマルチチップ及び単一コンポーネントのダイ接着のための方法であって、基板の上又はダイの裏側に焼結ペーストをプリントすることを含むことができる。プリンティングは、ステンシルプリンティング、スクリーンプリンティング、又はディスペンシングプリンティングを含むことができる。ペーストは、ダイシングの前に全ウェハの裏側にプリントすることができる、又は個々のダイの裏側にプリントすることができる。また、焼結膜は、作成後、ウェハ、ダイ、又は基板に転写することができる。ポスト焼結工程は、スループットを上げることができる。【選択図】図３２

微电子组件

本文公开了微电子组件、相关的设备和方法。在一些实施例中，微电子组件可以包括：具有第一表面和相对的第二表面的封装衬底；嵌入在第一电介质层中的第一管芯，第一管芯具有第一表面和相对的第二表面，其中，第一管芯的第一表面通过第一互连耦合到封装衬底的第二表面；嵌入在第二电介质层中的第二管芯，第二管芯具有第一表面和相对的第二表面，其中，第二管芯的第一表面通过第二互连耦合到第一管芯的第二表面；以及嵌入在第三电介质层中的第三管芯，第三管芯具有第一表面和相对的第二表面，其中，第三管芯的第一表面通过第三互连耦合到第二管芯的第二表面。

Microelectronic assemblies with communication networks

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

接合結構體之製造方法

本發明之接合結構體之製造方法具備回焊步驟，該回焊步驟係於回焊爐內，於使焊料材料與第1構件接觸之狀態下進行加熱，使構成上述焊料材料之焊料合金熔融；且上述回焊步驟包括：第1回焊步驟，其係於將上述回焊爐內之環境減壓至低於大氣壓之第1壓力P 1 之狀態下使上述焊料合金熔融；及第2回焊步驟，其係於上述第1回焊步驟後，於將上述回焊爐內之環境減壓至低於上述第1壓力P 1 之第2壓力P 2 之狀態下使上述焊料合金熔融。

Electronics assemblies employing copper in multiple locations

Electronic assemblies may be fabricated with interconnects of different types present in multiple locations and comprising fused copper nanoparticles. Each interconnect or a portion thereof comprises a bulk copper matrix formed from fusion of copper nanoparticles or a reaction product formed from copper nanoparticles. The interconnects may comprise a copper-based wire bonding assembly, a copper-based flip chip connection, a copper-based hermetic seal assembly, a copper-based connector between an IC substrate and a package substrate, a copper-based component interconnect, a copper-based interconnect comprising via copper for establishing electrical communication between opposite faces of a package substrate, a copper-based interconnect defining a heat channel formed from via copper, and any combination thereof.

Semiconductor device having a resin that seals a rewiring

A semiconductor device includes a semiconductor layer that has a main surface, an electrode pad that is formed on the main surface, a rewiring that has a first wiring surface connected to the electrode pad and a second wiring surface positioned on a side opposite to the first wiring surface and being roughened, the rewiring being formed on the main surface such as to be drawn out to a region outside the electrode pad, and a resin that covers the second wiring surface on the main surface and that seals the rewiring.

使用導電糊之導電柱之製造方法

於作為習知方法之電鍍法中，存在難以不受底切之影響地形成微細之柱的問題。又，於無電解鍍覆法中，存在難以形成無孔隙且相同形狀之柱的問題。 本發明人等為了解決上述諸問題而反覆進行苦心研究，結果發現：於減壓狀態下塗佈含有金屬微粒子之導電糊後，使其成為標準氣壓，藉此可於具有電極部之基板上容易地形成微細且縱橫比高之導電柱。本發明對作為倒裝晶片構裝端子之金屬柱之製造格外有效果。

Engineered polymer-based electronic materials

发光二极管显示装置

提供了一种发光二极管显示装置。所述发光二极管显示装置包括：显示板，包括多个单元像素；驱动电路板，包括与所述多个单元像素对应的多个驱动电路区域；以及多个凸块，置于所述多个单元像素与所述多个驱动电路区域之间。所述多个单元像素包括包含第一P电极的第一单元像素。所述多个驱动电路区域包括与第一单元像素对应的第一驱动电路区域，第一驱动电路区域包括连接到第一驱动晶体管的第一焊盘，所述多个凸块包括第一凸块，第一凸块包括与第一焊盘接触的第一焊料和在第一焊料上并与第一P电极接触的第一填料，第一焊料包括锡和银中的至少一种，并且第一填料包括铜或镍。

Microelectronic assemblies with communication networks

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

발광 다이오드 디스플레이 장치

발광 다이오드 디스플레이 장치가 제공된다. 발광 다이오드 디스플레이 장치는, 발광 다이오드 디스플레이 장치는, 복수의 단위 픽셀을 포함하는 디스플레이 기판, 복수의 단위 픽셀 각각과 대응되는 복수의 구동회로 영역을 포함하는 구동회로 기판 및 복수의 단위 픽셀 각각과, 복수의 구동회로 영역 각각의 사이에 개재되어, 디스플레이 기판과 구동회로 기판을 연결하는 복수의 범프를 포함하고, 복수의 단위 픽셀은, 제1 P전극을 포함하는 제1 단위 픽셀을 포함하고, 복수의 구동회로 영역은, 제1 단위 픽셀과 대응되고, 제1 구동 트랜지스터와 연결된 제1 패드를 포함하는 제1 구동회로 영역을 포함하고, 복수의 범프는, 제1 패드와 직접 접하는 제1 솔더와, 제1 솔더 상에 배치되고 제1 P전극과 직접 접하는 제1 필러를 포함하는 제1 범프를 포함하고, 제1 솔더는 주석 및 은 중 적어도 어느 하나를 포함하고, 제1 필러는 구리와 니켈 중 어느 하나를 포함한다.

导电性柱、接合结构、电子设备及导电性柱的制造方法

本发明提供一种可经由接合层将基材与被接合构件以高接合强度接合的导电性柱及其制造方法。具体而言，制成如下导电性柱1，包含设置于基材11上的金属微粒的烧结体12，金属微粒的使用X射线小角散射测定法测定的平均粒径不足1μm，烧结体12的上表面12b为向基材11侧凹陷的凹型形状。金属微粒优选为选自Ag及Cu中的一种以上的金属。