Dreidimensionale (3D) integrierte Schaltung mit verbessertem Kupfer-Kupfer-Bonding

Mindestens eine metallische Adhäsionsschicht wird auf mindestens einer Cu-Fläche eines ersten Bauelement-Wafers gebildet. Ein zweiter Bauelement-Wafer mit einer weiteren Cu-Fläche wird über der Cu-Fläche des ersten Bauelement-Wafers und auf der mindestens einen metallischen Adhäsionsschicht positioniert. Der erste und der zweite Bauelement-Wafer werden dann zusammengebondet. Das Bonden beinhaltet das Erwärmen der Bauelement-Wafer auf eine Temperatur von weniger als 400°C mit oder ohne Anwendung eines äußerlich angewandten Drucks. Während des Erwärmens werden die beiden Cu-Flächen zusammengebondet und die mindestens eine metallische Adhäsionsschicht erhält Sauerstoffatome von den beiden Cu-Flächen und bildet mindestens eine Metalloxid-Bondschicht zwischen den Cu-Flächen.

Method for assembling a camera module

A camera module includes a composite printed circuit board 21, an image sensing chip 22 and an underfill 24. The composite printed circuit board 21 includes a signal terminal 211A to be connected with a conductive bump 23 of the image sensing chip 22. The underfill 24 is formed around a connecting region between the conductive bump 23 and the signal terminal 211A before the image sensing chip and the circuit board are laminated together. This eliminates the need to make the printed circuit board larger than the image sensing chip for the purposes of applying underfill after lamination (see figure 1).

Backside metal treatment of semiconductor chips

An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate. The TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is over the backside of the semiconductor substrate and connected to the back end of the TSV. A silicide layer is over and contacting the RDL.

Interconnection [...] structure and method

DEVICE OF CONNECTION AND PROCESS OF CONNECTION

PLATING BATH AND METHOD

PLATING BATH AND METHODAbstract of the DisclosureSilver electroplating baths having certain sulfide compounds and methods of electrodepositing a silver-containing layer using these baths are disclosed. Such electroplating baths are useful to provide silver-containing solder deposits having reduced void formation and improved within-die uniformity.NO FIGURE ...

STRUCTURE AND METHOD FOR RELIABLE SOLDER JOINTS

A solder joint (200) has a first contact pad (114) and a second contact pad (124) of a first metal, preferably copper, facing each other across a gap. A coat (115 and 125, respectively) of a second metal, preferably nickel, covers each pad. A layer (201) of crystals of first intermetallic compounds, such as Ni3Sn4 and (Ni, Cu)3Sn4, covers the surface of each coat. Isolated crystals (202) of second intermetallic compounds, such as Cu6Sn5 and (Cu, Ni)6Sn5, different from the first intermetallic compounds, are dispersed on top of the layer of crystals of the first intermetallic compounds. A solder alloy (203) including a third metal, preferably tin, and the first metal fills the gap. The solder alloy may further include a fourth metal, preferably selected from a group of metals including silver, zinc, and indium.

Semiconductor device

A novel structure capable of reducing the stress in the insulating layer in the semiconductor element and thereby securing reliability is provided. When the semiconductor element and the substrate are connected with a solder, the stress generated in the insulating layer is reduced by placing a spherical core made of a material having a greater rigidity inside the solder and satisfying the following inequalities: 1 GPa<(Young's modulus of a encapsulation resin)<30 GPa, 20 ppm/k<(linear coefficient of expansion of the encapsulation resin)<200 ppm/k, and 10 MPa<(yield stress of the solder at room temperature)<30 MPa. At the time of connection, the thickness of the solder to be placed between the land on the surface of the semiconductor element and the core is adjusted to 1/10 or less of the terminal pitch.

Thermo-compression bonded electrical interconnect structure and method

An electrical structure and method for forming electrical interconnects. The method includes positioning a sacrificial carrier substrate such that a first surface of a non-solder metallic core structure within the sacrificial carrier substrate is in contact with a first electrically conductive pad. The first surface is thermo-compression bonded to the first electrically conductive pad. The sacrificial carrier substrate is removed from the non-solder metallic core structure. A solder structure is formed on a second electrically conductive pad. The first substrate comprising the non-solder metallic core structure is positioned such that a second surface of the non-solder metallic core structure is in contact with the solder structure. The solder structure is heated to a temperature sufficient to cause the solder structure to melt and form an electrical and mechanical connection between the second surface of the non-solder metallic core structure and the second electrically conductive pad.

Semiconductor integrated circuit device and manufacturing method of that

A laser beam is irradiated onto a photocurable resin layer formed on an electrode part before rearrangement. By scanning the resin on the periphery of a metal wiring formation area extending from the electrode part before rearrangement to a bump electrode contact area, is cured. As a result, a cured resin part is formed which works as a guide layer and a protection film for protecting the metal wire in which the metal wiring formation area has a hollow shape. Thereafter, the metal wire is formed inside the cured resin part.

SILVER-COATED BALL AND METHOD FOR MANUFACTURING SAME

A silver-coated ball 10 according to the present invention includes: a spherical core 1; and a coating layer 2 including silver superfine particles, which is arranged so as to surround the core 1. The silver superfine particles included in the coating layer 2 have a mean particle size of 1 nm to 50 nm.

Interconnection of lead frame to die utilizing flip chip process

Embodiments in accordance with the present invention relate to techniques which avoid the problems of deformation in the shape of a solder connection in a flip chip package, resulting from solder reflow. In one embodiment, a solder-repellent surface is created adjacent to the solder to constrain the reflow and thereby maintain the vertical profile of the solder. Examples of such a solder-repellent surface include an oxide (such as Brown Oxide) of the lead frame, or a tape (such as Kapton) which is used as a dam bar to control/constrain the solder flow on the leads prior to the encapsulation step. In another embodiment, the solder connection may be formed from at least two components. The first component may reflow at high temperatures to provide the necessary adhesion between solder ball and the die, with the second component reflowing at a lower temperature to provide the necessary adhesion between the solder ball and the leads. An example of such multi-component connections include a ...

Flip chip assembly and process with sintering material on metal bumps

A method is disclosed of fabricating a microelectronic package comprising a substrate overlying the front face of a microelectronic element. A plurality of metal bumps project from conductive elements of the substrate towards the microelectronic element, the metal bumps having first ends extending from the conductive elements, second ends remote from the conductive elements, and lateral surfaces extending between the first and second ends. The metal bumps can be wire bonds having first and second ends attached to a same conductive pad of the substrate. A conductive matrix material contacts at least portions of the lateral surfaces of respective ones of the metal bumps and joins the metal bumps with contacts of the microelectronic element.

Method of mounting an electronic component on a circuit board

When mounting an IC chip (1) on a circuit board (4), bumps (3) are formed on electrodes (2) on the IC chip, and the bumps and the electrodes (5) of the circuit board are aligned in position with each other with interposition of an insulative thermosetting resin (6). The resin sheet (6) is provided with through holes (15) in which are embedded conductive particles (14). The bumps (3), the through holes (15) and the electrodes are aligned. The IC chip is pressed against the circuit board with a pressure force of not smaller than 20 gf per bump by a heated head (8) so as to perform warp correction of the IC chip and the board, while the resin interposed between the IC chip and the circuit board is hardened to bond the IC chip and the circuit board together.

Ball contact for flip-chip devices

FLUXLESS CONTACTING OF COMPONENTS

SEMICONDUCTOR PACKAGE HAVING BUMP BALL

PROBLEM TO BE SOLVED: To provide a semiconductor package having a bump ball which suppresses formation of a reaction intermediate product of double layers causing stress concentration upon bump formation and mutual connection of such packages. SOLUTION: The semiconductor package includes a bump ball 30 as an external connection terminal. The bump ball 30 includes: a core layer 31 containing copper, copper alloy, aluminum, aluminum alloy, or a combination thereof; and a shell layer 32 surrounding the core layer 31 and containing tin, tin alloy, or a combination thereof. COPYRIGHT: (C)2010,JPO&INPIT ...

WAFER LEVEL ELECTROLESS COPPER METALLIZATION AND BUMPING PROCESS, AND PLATING SOLUTIONS FOR SEMICONDUCTOR WAFER AND MICROCHIP

SOLDER INTERCONNECTIONS AND METHODS FOR MAKING SAME

Integrated circuit element and packaging component

The invention provides an integrated circuit element and a packaging component. The integrated circuit element comprises a semiconductor substrate, a conductive column which is disposed on the semiconductor substrate and has a side wall surface and an upper surface, a boss lower metal layer which is disposed between the semiconductor substrate and the conductive column and has a surface area which is adjacently connected to the side wall surface of the conductive column and extends from the side wall surface, and a protection structure which is disposed on the side wall surface of a copper column and on the surface area of the boss lower metal layer. The protection structure is made of metal materials and the conductive column is composed by copper layers. The side wall protection structure covers at least a part of the side wall surface of the boss structure, and the protection structures disposed on the copper column side wall and on the surface area of the boss lower metal layer are ...

METHOD OF FORMING CONDUCTIVE INTERCONNECTS ON A SUBSTRATE AND INTERCONNECTIONS THUS OBTAINED

Procédé de réalisation d'une structure de connexion, comprenant des étapes consistant à : a) former au moins un pilier conducteur sur une couche conductrice d'accroche disposée sur un support, la couche conductrice d'accroche étant à base d'au moins un premier matériau conducteur, b) déposer un deuxième matériau conducteur sur le pilier conducteur, le deuxième matériau conducteur étant fusible, c) effectuer au moins un traitement thermique de sorte à faire fondre le deuxième matériau conducteur pour qu'une portion du deuxième matériau conducteur coule contre le pilier conducteur et réagisse avec la couche conductrice en formant une zone (45) à base d'un alliage située autour et contre une base du pilier conducteur, d) graver sélectivement la couche conductrice d'accroche autour du pilier conducteur par rapport à ladite zone (45) d'alliage, la zone (45) d'alliage formant une protection à la gravure de la couche conductrice d'accroche située en regard du pilier conducteur (figure 1F).

Self-assembled interconnection particles

SEMICONDUCTOR DEVICE USING A STUD BUMP FOR CONNECTION, A MANUFACTURING METHOD THEREOF, AND AN ELECTRONIC DEVICE

PURPOSE: A semiconductor device, a manufacturing method thereof, and an electronic device are provided to improve the connection reliability of the semiconductor device by performing a flip chip connection at low temperatures. CONSTITUTION: A semiconductor device includes a semiconductor member(31), a Cu stud bump(41), a solder bump(44), and a plating layer. The Cu stud bump is formed on the semiconductor device. The solder bump is electrically connected to the Cu stud bump. The plating layer is formed on the surface of the Cu stud bump. COPYRIGHT KIPO 2013 ...

IMPROVEMENT OF A SOLDER INTERCONNECT BY ADDING COPPER, WHICH FORMS AN IMC SECTION BETWEEN A SOLDER BUMP AND A BUMP PAD

PURPOSE: An improvement of a solder interconnect by adding copper, which forms an IMC section between a solder bump and a bump pad, is provided to reduce bump malfunction and to improve the mechanical property of a joint between the bump and pad. CONSTITUTION: An improvement of a solder interconnect by adding copper comprises next steps. An electronic device(100) and a substrate(120) are offered. A copper - layer of inclusion is formed on a nickel - layer of inclusion before a reflow process is applied to an electronic device. A solder bump pad(130) is installed on the substrate. COPYRIGHT KIPO 2011 ...

Cu column, Cu nuclear column, solder joint, and through-silicon via

A Cu column having low Vickers hardness and small arithmetic average roughness; a Cu nuclear column; a solder joint; and a through-silicon via. The Cu column 1 according to the present invention has purity of 99.9 to 99.995% inclusive, arithmetic average roughness of 0.3 [mu]m or less and Vickers hardness of 20 to 60 HV inclusive. The Cu column 1 cannot be melted at a temperature at which soldering is to be carried out and ensures a constant stand-off height (a space between substrates). Therefore, the Cu column 1 can be used suitably in three-dimensional mounting and narrow-pitch mounting.

Method for forming bump, semiconductor device and method for making the same, circuit board, and electronic machine

The subject of the present invention is to provide a bump formation method for easily forming a bump with a desired width, a semiconductor device and a method for making the same, a circuit board, and an electronic device. A method for forming a bump includes forming an opening 16 in an insulating film 15, which exposes at least a part of a pad 12; and forming the bump 12 so as to be connected to the pad. A resist layer 20 of the through hole 22, which overlaps at least a part of the pad 12 on the plane, is formed. An opening portion 16 is formed on the insulation film 15. A metal layer is formed to connect to the pad 12 exposed from the opening portion 16.

INTERCONNECT SYSTEM AND METHOD OF FABRICATION

Embodiments of the present invention relate generally to interconnect systems. One embodiment relates to an interconnect system (11) having a first substrate (10), and a standoff (20) that extends from said first substrate. The interconnect system further includes a cap (22), intended for subsequent reflow attachment, that covers a first end of the standoff and does not cover the sides of the standoff. The interconnect system further includes a nonwettable surface layer (24) on the sides of the standoff such that the cap is prevented from substantially wetting the sides of the standoff when the cap is in a fluid state. The interconnect system may further include a second substrate (28) attached to the cap where substantially all of the cap is located at the first end of the standoff. Another embodiment of the present inventions relates to a method of fabricating the interconnect system.

CONTACT ARRANGEMENT LINKING TWO SUBSTRATES AND METHOD FOR THE PRODUCTION OF SAID CONTACT ARRANGEMENT

The invention relates to a contact arrangement (10) linking two substrates (11,12) and to a method for producing said contact arrangement, comprising the following steps: soldering material (23) is deposited on contact areas (16) of a first substrate to form spaced metallic coatings (19), and the first substrate (11) is contacted to a second substrate (12) whereby contacting occurs between the contact areas (16) of the first substrate (11) and a contact surface of the second substrate (12) by means of an electroconductive adhesive material (20).

Semiconductor device having conductive bumps and fabrication method thereof

A semiconductor device having conductive bumps and a fabrication method thereof is proposed. The fabrication method includes the steps of forming a first metallic layer on a substrate having solder pads and a passivation layer formed thereon, and electrically connecting it to the solder pads; applying a second covering layer over exposed parts of the first metallic layer; subsequently, forming a second metallic layer on the second covering layer, and electrically connecting it to the exposed parts of the first metallic layer; applying a third covering layer, and forming openings for exposing parts of the second metallic layer to form thereon a conductive bump having a metallic standoff and a solder material. The covering layers and the metallic layers can provide a buffering effect for effectively absorbing the thermal stress imposed on the conductive bumps to prevent delamination caused by the UBM layers.

ELECTRONIC DEVICE INCLUDING FIRST SUBSTRATE HAVING FIRST AND SECOND SURFACES OPPOSITE FROM EACH OTHER, SECOND SUBSTRATE FACING FIRST SURFACE, AND DRIVE CIRCUIT FACING SECOND SURFACE

An electronic device includes: a first substrate having a first surface and a second surface opposite from the first surface; a second substrate facing the first surface; driven elements provided at the second substrate; a drive circuit facing the second surface; a first interconnect provided at the first surface; a second interconnect provided at the second surface; a through-substrate interconnection part penetrating the first substrate in a thickness direction thereof; a first bump part; and a second bump part. The drive circuit is capable of outputting drive signals for driving the driven elements. The through-substrate interconnection part electrically connects the first interconnect and the second interconnect. The first bump part electrically connects the first interconnect and the driven elements. The second bump part electrically connects the second interconnect and the drive circuit. The through-substrate interconnection part has an electrical resistance lower than an electrical ...

Redistribution Layers And Methods Of Fabricating The Same In Semiconductor Devices

A semiconductor structure includes a first passivation layer disposed over a metal line, a copper-containing RDL disposed over the first passivation layer, where the copper-containing RDL is electrically coupled to the metal line and where a portion of the copper-containing RDL in contact with a top surface of the first passivation layer forms an acute angle, and a second passivation layer disposed over the copper-containing RDL, where an interface between the second passivation layer and a top surface of the copper-containing RDL is curved. The semiconductor structure may further include a polymeric layer disposed over the second passivation layer, where a portion of the polymeric layer extends to contact the copper-containing RDL, a bump electrically coupled to the copper-containing RDL, and a solder layer disposed over the bump. 1. A method , comprising:providing an interconnect structure disposed over a semiconductor substrate, wherein the interconnect structure includes a metal line;forming a first dielectric layer over the metal line;patterning the first dielectric layer to expose a portion of the metal line in a first opening;forming a pattern-forming layer over the first dielectric layer, thereby filling the first opening;forming a second opening in the pattern-forming layer;forming a footing profile to laterally extend the second opening;forming a redistribution layer (RDL) in the second opening, such that the RDL is electrically coupled to the metal line, wherein the RDL includes a curved top surface; andforming a second dielectric layer over the RDL.2. The method of claim 1 , further comprising:forming a seed layer on the first dielectric layer before forming the pattern-forming layer; andremoving portions of the seed layer not covered by the RDL before forming the second dielectric layer.3. The method of claim 1 , wherein forming the pattern-forming layer includes forming a photoresist layer on the first dielectric layer.4. The method of claim 3 , ...

SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA COVERED BY A SOLDER BALL AND RELATED METHOD OF PRODUCTION

The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises a void (101), which may be filled with air or another gas. A solder ball (100) closes the void without completely filling it. A variety of interconnections for three dimensional integration is offered by this scheme.

Metal bump formation

A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps.

Stress Reduction in Chip Packaging by Using a Low-Temperature Chip-Package Connection Regime

A semiconductor chip and a package substrate may be directly connected on the basis of form closure by providing appropriately shaped complementary contact structures in the semiconductor chip and the package substrate. Consequently, solder material may no longer be required and thus any elevated temperatures during the assembly process may be avoided, which may conventionally result in significant stress forces, thereby creating damage, in particular in very complex metallization systems.

Methods for pillar connection on frontside and passive device integration on backside of die

An integrated circuit device includes a radio frequency transistor amplifier die having a first surface, a second surface, a semiconductor layer structure that is between the first and second surfaces and includes a plurality of transistor cells adjacent the first surface, and terminals coupled to the transistor cells. At least one passive electronic component is provided on the second surface of the die and is electrically connected to at least one of the terminals, for example, by at least one conductive via. One or more conductive pillar structures may protrude from the first surface of the die to provide electrical connections to one or more of the terminals.

Conductive external connector structure and method of forming

External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

Höckergehäuse und Verfahren zu seiner Herstellung

Gemäß einer Ausführungsform der vorliegenden Erfindung umfasst ein Halbleitergehäuse einen Halbleiterchip (50) und einen Höcker (110). Der Halbleiterchip (50) weist auf einer Hauptfläche eine Kontaktstelle (310) auf. Der Höcker (110) ist auf der Kontaktstelle (310) des Halbleiterchips (50) angeordnet. Eine Lötschicht (120) ist auf Seitenwänden des Höckers (110) angeordnet.

Semiconductor device and method of manufacturing the same

The invention provides a semiconductor device and a method of manufacturing the same. In this semiconductor device, the through-hole is formed in the substrate, and is located under the conductive pattern. The insulating layer is located at the bottom surface of the through-hole. The conductive pattern is located on one surface side of the substrate. The opening pattern is formed in the insulating layer which is located between the through-hole and the conductive pattern, where the distance r3 from the circumference of the opening pattern to the central axis of the through-hole is smaller than the distance r1 in the through-hole. By providing the opening pattern, the conductive pattern is exposed at the bottom surface of the through-hole. The bump is located on the back surface side of the substrate, and is formed integrally with the through-electrode.

Barrier cover of lower metal block

A process for preparing solder blocks on semiconductor chip with metallic welding pads includes such steps as providing at least one metallic attach/barrier/electroplating contact layer on welding pad, generating protective layer with window of welding pad, providing a solder attach layer in window under block metal, removing part of protecting layer from window area to form a window between edgeof metal layer and protecting layer, providing a metal barrier layer on solder attachable metal layer, generating a solder block on the barrier layer, removing protecting layer, and removing and exposing attach/barrier layer.

FLIP CHIP ASSEMBLY METHOD COMPRISING PRE-COATING THE INTERCONNECTING MEMBERS

Ce procédé d'assemblage d'un premier et d'un second composants électroniques (50, 52), comporte : ▪ la réalisation d'éléments de connexion sur une face d'assemblage du premier composant (50) et la réalisation d'éléments de connexion sur une face d'assemblage du second composant (52) ; ▪ le dépôt d'une couche liquide de matériau durcissable et électriquement isolant (70) sur la face d'assemblage du premier et/ou du second composant ; ▪ le report des premier et second composants (50, 52) l'un sur l'autre de manière à mettre les éléments de connexion du second composant en face des éléments de connexion du premier composant ; ▪ l'application d'une force selon une direction prédéterminée (A) sur le premier et/ou le second des composants (50, 52) de manière à créer des interconnexions électriques constituées chacune d'un élément de connexion (56) du premier composant (50) et d'un élément de connexion (58) du second composant (52); ▪ et le durcissement du matériau durcissable (70). Les éléments ...

Method for assembling integrated circuit with another integrated circuit to form three-dimensional integrated structure, involves realizing electrically conducting pillar crossing from integrated circuit front face and leading to metal line

Structure intégrée tridimensionnelle et procédé d'assemblage de circuits intégrés correspondant, ladite structure comprenant un assemblage d'un premier circuit intégré (CI1) et d'un deuxième circuit intégré (CI2), dans lequel la face arrière (BF1) du premier circuit intégré est collée directement à la face avant (FF2) du deuxième circuit intégré et comprenant au moins un pilier électriquement conducteur (PC) traversant le premier circuit intégré depuis le voisinage de la face avant du premier circuit intégré et débouchant sur une ligne métallique (LM2) du deuxième circuit intégré.

Bump structure and the method for fabricating the same

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor device and method of manufacturing the same

A semiconductor device includes a semiconductor chip. A substrate is arranged in opposition to the semiconductor chip. A first electrode is placed on the semiconductor chip while a second electrode is placed on the substrate. An intermetallic compound layer is arranged between the first electrode and the second electrode. Each of the first and second electrodes is made of predetermined electrode material. The intermetallic compound layer is made of the electrode material and bonding material supplied to at least one of the first and second electrodes.

Solder pillar bumping and a method of making the same

Semiconductor device and method of production of same

A semiconductor device provided with transistors or other semiconductor elements formed on a semiconductor substrate, external connection terminals connecting these elements to an external circuit, and interconnection patterns connecting electrodes of the semiconductor elements to the external connection terminals, wherein the external connection terminals are formed by wires comprised of a conductive material and the parts of the wires bonded to the interconnection patterns are buried in the metal layer forming the interconnection patterns. A method of production of the semiconductor device is also disclosed.

Device having a compliant element pressed between

Package structure

Integrated circuit devices and packaging assembly

A sidewall protection structure is provided for covering at least a portion of a sidewall surface of a bump structure, in which a protection structure on the sidewall of a Cu pillar and a surface region of an under-bump-metallurgy (UBM) layer is formed of at least one non-metal material layers, for example a dielectric material layer, a polymer material layer, or combonations thereof.

Semiconductor device and method of forming interconnect structure over seed layer on contact pad of semiconductor die without undercutting seed layer beneath interconnect structure

A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure.

Bulk metallic glass solders, foamed bulk metallic glass solders, foamed-solder bond pads in chip packages, methods of assembling same, and systems containing same

A foamed bulk metallic glass electrical connection is formed on a substrate of an integrated circuit package. The foamed bulk metallic glass electrical connection exhibits a low modulus that resists cracking during shock and dynamic loading. The foamed bulk metallic glass electrical connection is used as a solder bump for communication between an integrated circuit device and external structures. A process of forming the foamed bulk metallic glass electrical connection includes mixing bulk metallic glass with a blowing agent.

Semiconductor device and manufacturing method thereof

A semiconductor device includes (i) spacers between a first electronic component and a second electronic component facing each other, for keeping a distance between the first and second electronic components constant and (ii) combining parts for combining the first electronic component with the second electronic component. The spacers are made of liquid resin material made of thermosetting resin, and the combining parts are made of liquid conductive combining material including metal and thermosetting resin. A manufacturing method of the semiconductor device includes the steps of: forming the spacers on first electrode pads by hardening the liquid resin material; providing the liquid conductive combining material on either the first electrode pads or second electrode pads; aligning the first electronic component with the second electronic component so that (i) the spacers contact with the second electrode pads and (ii) the liquid conductive combining material contact with either at least ...

METHOD FOR FABRICATING HIGH-EFFICIENCY MICRO-LED MODULE

Disclosed is a method for fabricating a high-efficiency micro-LED module. The method includes: preparing a micro-LED in which an epilayer is grown on a sapphire substrate, a plurality of LED cells are formed on the epilayer, a plurality of individual electrode pads are disposed such that one individual electrode pad is assigned to each LED cell, and a common electrode pad is formed on an area surrounding the plurality of LED cells; preparing a submount substrate including a plurality of individual electrodes corresponding to the individual electrode pads and a common electrode corresponding to the common electrode pad; mounting the micro-LED on the submount substrate such that the plurality of individual electrodes are connected to the plurality of individual electrode pads and the common electrode pad is connected to the common electrode through a plurality of bonding connection members; forming a buffer layer between the micro-LED and the submount substrate; and irradiating a laser around ...

Method for forming a wafer level chip scale package, and package formed thereby

A method for fabricating a chip scale package is described. The method utilizes wafer level processes to obtain a chip level package. The method particularly avoids the use of mechanical grinding by the novel use of molding, extruding, and etching technology.

PROTECTIVE LAYER FOR PROTECTING TSV TIPS DURING THERMO-COMPRESSIVE BONDING

A method of protecting through substrate via (TSV) die from bonding damage includes providing a substrate including a plurality of TSV die having a topside including active circuitry, a bottomside, and a plurality of TSVs that include an inner metal core that reaches from the topside to protruding TSV tips that extend out from the bottomside. A protective layer is formed on or applied to the bottomside of the TSV die including between and over the protruding TSV tips. The TSV die is bonded with its topside down onto a workpiece having a workpiece surface and its bottomside up and in contact with a bond head. The protective layer reduces damage from the bonding process including warpage of the TSV die by preventing the bond head from making direct contact to the protruding TSV tips.

Microelectronic packages and methods therefor

A microelectronic package includes a microelectronic element having a first face including contacts, and a flexible substrate having a first surface and a second surface, conductive posts projecting from the first surface and conductive terminals accessible at the second surface, at least some of the conductive terminals and the conductive posts being electrically interconnected and at least some of the conductive terminals being offset from the conductive posts. The first surface of the flexible substrate is juxtaposed with the first face of the microelectronic element so that the conductive posts project from the flexible substrate toward the first face of the microelectronic element. The conductive posts are electrically interconnected with the contacts of the microelectronic element and at least some of the conductive terminals are movable relative to the microelectronic element.

HALBLEITERBAUGRUPPE MIT LEITENDEM RAHMEN FÜR E/A-ABSTAND UND THERMISCHE DISSIPATION

Halbleiterbauelement mit einem leitenden Rahmen, der eine Die-Befestigungsfläche aufweist, die im wesentlichen planar ist, einem Halbleiterdie mit einem ersten Anschluss auf einer Rückseite und einem zweiten Anschluss, der auf einer Hauptoberfläche angeordnet ist, einer ersten leitenden Kontaktstruktur, die auf der Die-Befestigungsfläche angeordnet ist, und einer zweiten leitenden Kontaktstruktur auf der Hauptoberfläche. Die erste leitende Kontaktstruktur erstreckt sich vertikal über eine Ebene der Hauptoberfläche des Halbleiterdies hinaus. Die erste leitende Kontaktstruktur ist von der Hauptoberfläche des Halbleiterdies durch eine elektrische Isolationsstruktur elektrisch isoliert. Eine obere Oberfläche der elektrischen Isolationsstruktur befindet sich unterhalb der Hauptoberfläche des Halbleiterdies.

Camera module and assembling process thereof

Process for single mask C4 solder bump fabrication

ELECTRICAL CONNECTING STRUCTURE AND PROCEDURE FOR YOUR EDUCATION

Wafer level electroless copper metallization and bumping process, and plating solutions for semiconductor wafer and microchip

Formation of welding flux with resin parts as strengthening element

METHOD OF MANUFACTURING A BONDING PAD FOR A THERMO-COMPRESSION BONDING PAD AND OBTAINED

INTEGRATED CIRCUIT DIE AND METHOD OF MAKING.

A MANUFACTURING MANAGING METHOD OF SEMICONDUCTOR DEVICES

작은 간극 내의 상호접속 구조체의 국소화된 밀봉

... 장치는 일반적으로 마이크로전자 디바이스에 관한 것이다. 그러한 장치에서, 제1 기판이 제1 표면을 갖고, 제1 표면 상에 제1 상호접속부들이 위치되며, 제2 기판이 제1 표면으로부터 이격되는 제2 표면을 갖고, 제1 표면과 제2 표면 사이에 간극이 있다. 제2 상호접속부들이 제2 표면 상에 위치된다. 제1 상호접속부들의 하부 표면들과 제2 상호접속부들의 상부 표면들이 제1 기판과 제2 기판 사이의 전기 전도성을 위해 서로 결합된다. 전도성 칼라가 제1 및 제2 상호접속부들의 측벽들 주위에 있고, 유전체 층이 전도성 칼라 주위에 있다.

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a device, a conductive pad on the device, and a Ag1-xYx alloy bump over the conductive pad. The Y of the Ag1-xYx bump comprises metals forming complete solid solution with Ag at arbitrary weight percentage, and the X of the Ag1-xYx alloy bump is in a range of from about 0.005 to about 0.25. A difference between one standard deviation and a mean value of a grain size distribution of the Ag1-xYx alloy bump is in a range of from about 0.2 m to about 0.4 m. An average grain size of the Ag1-xYx alloy bump on a longitudinal cross sectional plane is in a range of from about 0.5 m to about 1.5 m.

Cu core ball, solder joint, foam solder, and solder paste

The present invention suppresses occurrences of soft errors while assuring alignment properties when mounting a Cu core ball on an electrode. A Cu core ball (11) is provided with a Cu ball (1) and a metal layer (2) that coats the surface of this Cu ball (1). The metal layer (2) is formed from one or more elements selected from Ni, Co, and Fe. The Cu ball (1) is such that the purity is 99.9 - 99.995%, the U content is 5 ppb or less, the Th content is 5 ppb or less, the total amount for the content of at least one of Pb and Bi is 1 ppm or greater, the sphericity is 0.95 or greater, and the alpha dose is 0.0200 cph/cm2 or less.

METHOD FOR FORMING A WAFER LEVEL CHIP SCALE PACKAGE, AND PACKAGE FORMED THEREBY

A layer of gold (405) is disposed on upper surfaces (225) of copper pillars (210) on a bumped wafer (205). Coating material (410) is then applied to a level which is less than the height of the copper pillars (210), and etchant is disposed to remove coating material on the layer of gold (405) and to remove coating material (410) adhering to side surfaces of the copper pillars (210). Solder balls (405) are then disposed on the ends of the copper pillars (210), with the copper pillars (210) protruding into the solder balls (405). In an alternative embodiment, solder balls are first attached to the free ends of the copper pillars and coating material applied to encapsulate the solder balls and the copper pillars on the semiconductor wafer. An etchant is then used to remove a portion of the coating material, substantially exposing the solder balls.

METHOD OF BONDING A FIRST SUBSTRATE AND A SECOND SUBSTRATE

A method for bonding a first substrate and a second substrate, the first substrate having at least one first connection extending from one side of the first substrate, the method comprising fabricating a first adhesive material around and along a height of the at least one first connection; and bonding the at least one first connection, the first adhesive material, and the second substrate. 1. A method for bonding a first substrate and a second substrate , the first substrate having at least one first connection extending from one side of the first substrate and the second substrate including at least one under bump metallization (UBM) portion wherein the at least one UBM portion has a broader width across the second substrate than a width of the first connection across the first substrate , the method comprising:fabricating a first adhesive material only around and along a height of the at least one first connection;aligning centerlines of the at least one first connection and a corresponding one of the at least one UBM portion of the second substrate and bonding the at least one first connection, the first adhesive material, and the corresponding one of the at least one UBM portion of the second substrate using a flip chip bonding technique; andthereafter permanently bonding the at least one first connection, the first adhesive material, and the corresponding one of the at least one UBM portion of the second substrate using a global bonder technique.2. (canceled)3. A method for bonding a first substrate and a second substrate , the first substrate having at least one first connection extending from one side of the first substrate and the second substrate having at least one second connection extending from one side of the second substrate , the method comprising:fabricating a first adhesive material only around and along a height of the at least one first connection;fabricating a second adhesive material only around and along a height of the at least one second ...

Thermo-compression bonded electrical interconnect structure and method

An electrical structure and method for forming. The electrical structure includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure and a first solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. A second portion of the non-solder metallic core structure is thermo-compression bonded to the second electrically conductive pad.

Anchoring structure of fine pitch bva

A microelectronic package can include a substrate having a first surface and a second surface opposite therefrom, the substrate having a first conductive element at the first surface, and a plurality of wire bonds, each of the wire bonds having a base electrically connected to a corresponding one of the first conductive elements and having a tip remote from the base, each wire bond having edge surfaces extending from the tip toward the base. The microelectronic package can also include an encapsulation having a major surface facing away from the first surface of the substrate, the encapsulation having a recess extending from the major surface in a direction toward the first surface of the substrate, the tip of a first one of the wire bonds being disposed within the recess, and an electrically conductive layer overlying an inner surface of the encapsulation exposed within the recess, the electrically conductive layer overlying and electrically connected with the tip of the first one of the ...

Semiconductor device and method of manufacturing the same

A dielectric resin layer R covers a wiring layer 7 and a metal post 8 which are made of Cu. The dielectric resin layer is made of shrinkable resin whose film thickness is greatly reduced during thermal setting. This makes it unnecessary to perform a step of grinding the dielectric resin layer to expose a head of the metal post.

Semiconductor devices with compliant interconnects

A method forms a connecting pillar to a bonding pad of an integrated circuit. A seed layer is formed over the bond pad. Photoresist is deposited over the integrated circuit. An opening is formed in the photoresist over the bond pad. The connecting pillar is formed in the opening by plating.

Localized sealing of interconnect structures in small gaps

An apparatus relates generally to a microelectronic device. In such an apparatus, a first substrate has a first surface with first interconnects located on the first surface, and a second substrate has a second surface spaced apart from the first surface with a gap between the first surface and the second surface. Second interconnects are located on the second surface. Lower surfaces of the first interconnects and upper surfaces of the second interconnects are coupled to one another for electrical conductivity between the first substrate and the second substrate. A conductive collar is around sidewalls of the first and second interconnects, and a dielectric layer is around the conductive collar.

Method For Manufacturing A Semiconductor Structure

The present invention provides a method for manufacturing a semiconductor structure, comprising the following steps of: forming a substrate having a package array, wherein the package array has a plurality of contact pads and a protection layer, and the plurality of contact pads are exposed to the outer side of the protection layer; forming a thermosetting non-conductive layer covering the substrate; partially solidifying the thermosetting non-conductive layer to form a semi-solid non-conductive layer; connecting chips to the package array on the substrate, wherein each of the chips has an active surface, a plurality of chip pads and a plurality of composite bumps, the chip pads are formed on the active surface, and the composite bumps are formed on the chip pads so that the composite bumps electrically connect to each of the contact pads; pressing and heating the chips and the substrate so that the semi-solid non-conductive layer adheres with the chips and the substrate; pre-heating an ...

Semiconductor structure having a silver alloy bump body and manufacturing method thereof

The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a conductive pad on a semiconductor die; forming a seed layer over the conductive pad; defining a first mask layer over the seed layer; and forming a silver alloy bump body in the first mask layer. The forming a silver alloy bump body in the first mask layer includes operations of preparing a first cyanide-based bath; controlling a pH value of the first cyanide-based bath to be within a range of from about 6 to about 8; immersing the semiconductor die into the first cyanide-based bath; and applying an electroplating current density of from about 0.1 ASD to about 0.5 ASD to the semiconductor die.

Semiconductor device with through-substrate via covered by a solder ball

The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises an annular cavity (18) and a void (101), which may be filled with air or another gas. A solder ball (100) closes the void without completely filling it. A variety of interconnections for three-dimensional integration is offered by this scheme.

Semiconductor device and semiconductor assembly with lead-free solder

A semiconductor device includes a semiconductor substrate, a pad region on the semiconductor substrate, a passivation layer over the semiconductor substrate and at least a portion of the pad region, and a bump structure overlying the pad region. The passivation layer has an opening defined therein to expose at least another portion of the pad region. The bump structure is electrically connected to the pad region via the opening. The bump structure includes a copper layer and a SnAg layer overlying the copper layer. The SnAg layer has a melting temperature higher than the eutectic temperature of Sn and Ag.

Die structure and die connecting method

A die structure and a die connecting method using the same are provided. The die structure includes a die and a bump structure. The bump structure includes a body and a solder layer. The body is disposed on the die. The solder layer is disposed on the body. The method includes providing a die structure mentioned above, providing a circuit board mentioned above, and soldering the solder layer of the die structure with the tine layer on the copper block of the circuit board. In different embodiments, a tin layer is omitted from the circuit board, wherein the solder layer of the die structure is directly soldered onto the surface of the copper block.

ALIGNED CORE BALLS FOR INTERCONNECT JOINT STABILITY

Embodiments herein relate to systems, apparatuses, or processes directed to an interconnect joint that includes multiple core balls within a solder compound where the multiple core balls are substantially linearly aligned. The multiple core balls, which may include copper or be a polymer, couple with each other within the solder and form a substantially linear alignment during reflow. In embodiments, four or more core balls may be used to achieve a high aspect ratio interconnect joint with a tight pitch.

CAMERA MODULE AND ASSEMBLING PROCESS THEREOF

A camera module and an assembling process thereof are provided. The camera module includes a composite printed circuit board, an image sensing chip and an underfill. The composite printed circuit board includes a signal terminal to be connected with a conductive bump of the image sensing chip. The underfill is formed around a connecting region between the conductive bump and the signal terminal.

Electronic device, and manufacturing method of electronic device

An electronic device includes a drive substrate (a pressure chamber substrate and a vibration plate) including a piezoelectric element and electrode wirings related to driving of the piezoelectric element formed thereon, and a sealing plate bonded thereto, the electrode wirings are made of wiring metal containing gold (Au) on the drive substrate through an adhesion layer which is a base layer, and has a removed portion in which a portion of the wiring metal in a region containing a part bonded to a bonding resin is removed and the adhesion layer is exposed.

Embedded graphite heat spreader for 3DIC

A device with thermal control is presented. In some embodiments, the device includes a plurality of die positioned in a stack, each die including a chip, interconnects through a thickness of the chip, metal features of electrically conductive composition connected to the interconnects on a bottom side of the chip, and adhesive or underfill layer on the bottom side of the chip. At least one thermally conducting layer, which can be a pyrolytic graphite layer, a layer formed of carbon nanotubes, or a graphene layer, is coupled between a top side of one of the plurality of die and a bottom side of an adjoining die in the stack. A heat sink can be coupled to the thermally conducting layer.

Semiconductor element, semiconductor element mounted board, and method of manufacturing semiconductor element

A semiconductor element includes connection terminals. The connection terminals are each shaped in such a manner that the transverse cross-sectional area in a portion near the leading end thereof decreases toward the leading end. Specifically, the shape of each of the connection terminals is columnar except for the portion near the leading end, and the side surface in the portion near the leading end of the connection terminal is shaped in a tapered form. Furthermore, a metal layer for improving a solder wettability may be formed at least on the side surface shaped in the tapered form, of the connection terminal.

SEMICONDUCTOR PACKAGE

A semiconductor package is provided. The semiconductor package includes: a first stack including a first semiconductor substrate; a through via that penetrates the first semiconductor substrate in a first direction; a second stack that includes a second face facing a first face of the first stack, on the first stack; a first pad that is in contact with the through via, on the first face of the first stack; a second pad including a concave inner side face that defines an insertion recess, the second pad located on the second face of the second stack; and a bump that connects the first pad and the second pad, wherein the bump includes a first upper bump on the first pad, and a first lower bump between the first upper bump and the first pad.

Multi-chip package and manufacturing method thereof

A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a wiring structure and an interposer via electrically connected to the wiring structure; a plurality of semiconductor chips located on a first surface of the interposer and electrically connected to each other through the interposer; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface, wherein the plurality of semiconductor chips are electrically connected to the redistribution circuit structure through at least the interposer.

SEMICONDUCTOR DEVICE AND METHOD THEREFOR

PROBLEM TO BE SOLVED: To realize a semiconductor device which is capable of preventing reduction in reliability, and which can be manufactured at a cost lower than the conventional types, and to realize a method for manufacturing the same. SOLUTION: An electrode pad 2 is provided, electrically connected to an electric circuit formed on the device forming surface of a silicon wafer 4. A rewired wiring pattern 5 is provided that is electrically connected to the electrode pad 2. An oxide film 10 is formed on the surface of the wiring pattern 5 by the oxidation of the wiring pattern 5. COPYRIGHT: (C)2005,JPO&NCIPI ...

LÖTELEMENT FÜR GEDRUCKTE LEITERPLATTEN

SOLDER INTERCONNECTIONS AND METHODS FOR MAKING SAME

The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier (12) a pad (14) is formed on which a solder mass (16) is deposited and capped with a metal layer (19), thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass (26) on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.

Semiconductor assembly, semiconductor device and manufacturing method

The invention provides a semiconductor assembly, a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a pad region located on the semiconductor substrate; a bump structure disposed over the pad region and electrically connected with the pad region. The bump structure includes a copper layer and a lead-free solder layer over the copper layer. The lead-free solder layer is a SnAg layer, and the Ag content in the SnAg layer is less than 1.6 weight percent. When the Ag content in the lead-free bump, the hardness of the bump will be reduced. Asofter bump could remove the crack owing to the heat stress.

Semiconductor device and method for manufacturing the same

Method of forming metal pillar

DEVICE OF CONNECTION AND PROCESS OF CONNECTION

L'invention concerne un dispositif de connexion comportant un élément en matériau conducteur (2) à mémoire de forme comportant au moins partiellement, dans des zones destinées à être en contact avec des éléments à connecter, une surface présentant une bonne mouillabilité sur un matériau de brasure à base de plomb et/ou d'étain. Applications: Connexion de circuits intégrés sous broche sur une plaque de circuits imprimés.

CHIP OF CIRCUITS JUST AND MANUFACTORING PROCESS.

Procédé de réalisation d'un moyen de connexion électrique d'une puce de circuits intégrés et puce de circuits intégrés comprenant une plaque de substrat et, sur une face avant de la plaque de substrat, des circuits intégrés et une couche intégrant un réseau avant d'interconnexion électrique, dans lesquels au moins un via local de connexion électrique (7a) en une matière conductrice de l'électricité, est formé dans un trou (8a) et un évidement (8b) de la plaque de substrat (2) et est reliée à une portion de connexion (9) dudit réseau d'interconnexion électrique ; un pilier de connexion électrique (16) en une matière conductrice de l'électricité, est formé sur une partie arrière du via de connexion électrique ; et une couche extérieure locale de protection (18) peut recouvrir au moins en partie le via de connexion électrique et le pilier de connexion électrique.

Method for realizing three-dimensional integrated structure, involves realizing electrically conductive through-connection extending between non-assembled face and metal line of interconnection part of one of two integrated circuits

Procédé de réalisation d'une structure intégrée tridimensionnelle, et structure correspondante, ledit procédé comprenant un collage direct de la face avant d'un premier circuit intégré (CI1) et de la face avant d'un deuxième circuit intégré (CI2), et une réalisation d'au moins une liaison traversante électriquement conductrice s'étendant entre une face non assemblée (BF11) du premier circuit intégré, opposée à sa face avant, et une ligne métallique (LM1) de la partie d'interconnexion d'un des deux circuits intégrés.

Methods for optimized fabrication of a structure to be assembled by hybridization and a device comprising such a structure

Metal Bump Formation

A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps.

Packaging Structures and Methods with a Metal Pillar

A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

Bump Structure and Method of Forming Same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

Metal Bump and Method of Manufacturing Same

An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width.

Solder interconnect with non-wettable sidewall pillars and methods of manufacture

A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.

SEMICONDUCTOR DEVICE WITH A HETEROGENEOUS SOLDER JOINT AND METHOD FOR FABRICATING THE SAME

A method for fabricating a semiconductor device with a heterogeneous solder joint includes: providing a semiconductor die; providing a coupled element; and soldering the semiconductor die to the coupled element with a first solder joint. The first solder joint includes: a solder material including a first metal composition; and a coating including a second metal composition, different from the first metal composition, the coating at least partially covering the solder material. The second metal composition has a greater stiffness and/or a higher melting point than the first metal composition. 1. A method for fabricating a semiconductor device with a heterogeneous solder joint , the method comprising:providing a semiconductor die;providing a coupled element; and a solder material comprising a first metal composition; and', 'a coating comprising a second metal composition, different from the first metal composition, the coating at least partially covering the solder material,', 'wherein the second metal composition has a greater stiffness and/or a higher melting point than the first metal composition., 'soldering the semiconductor die to the coupled element with a first solder joint, the first solder joint comprising2. The method of claim 1 , wherein the solder material is covered with a coating precursor prior to soldering the semiconductor die to the coupled element claim 1 , and wherein soldering the semiconductor die to the coupled element further comprises converting the coating precursor into the coating.3. The method of claim 2 , further comprising:depositing the solder material on the semiconductor die or on the coupled element; andafterwards covering the deposited solder material with the coating precursor.4. The method of claim 3 , wherein soldering the semiconductor die to the coupled element comprises heating the deposited solder material to melt the deposited solder material claim 3 , and wherein the act of heating the deposited solder material forms the ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a wiring board; a first semiconductor chip including a first surface, a second surface, and a connection bump on the first surface, the first semiconductor chip coupled to the wiring board through the connection bump; a resin layer covering the connection bump between the first semiconductor chip and the wiring board, an upper surface of the resin layer parallel to the second surface of the first semiconductor chip; and a second semiconductor chip including a third surface, a fourth surface, and an adhesive layer on the third surface, the second semiconductor chip adhering to the second surface of the first semiconductor chip and the upper surface of the resin layer through the adhesive layer. The upper surface of the resin layer projects outside a portion of at least an outer edge of the second semiconductor chip when viewed from the top. 1. A semiconductor device comprising:a wiring board;a first semiconductor chip including a first surface, a second surface opposite to the first surface, and a connection bump on the first surface, the first semiconductor chip coupled to the wiring board through the connection bump;a resin layer covering the connection bump between the first semiconductor chip and the wiring board, an upper surface of the resin layer substantially parallel to the second surface of the first semiconductor chip; anda second semiconductor chip including a third surface, a fourth surface opposite to the third surface, and an adhesive layer on the third surface, the second semiconductor chip adhering to the second surface of the first semiconductor chip and the upper surface of the resin layer through the adhesive layer,wherein the upper surface of the resin layer projects outside a portion of at least an outer edge of the second semiconductor chip when viewed from the top.2. The semiconductor device according to claim 1 ,wherein a spacer is not provided between the second semiconductor chip and the wiring board.3. The ...

PACKAGE METHOD AND PACKAGE STRUCTURE OF FAN-OUT CHIP

A packaging method and a package structure of a fan-out chip are disclosed. The package structure comprises a first chip with bumps and a second chip without bumps, a first dielectric layer formed on a surface of the second chip and through-holes fabricated in the first dielectric layer; a plastic package material; a second dielectric layer; a metal redistribution layer for interconnecting within and between the first chip and the second chip; under bump metallization layers and micro-bumps. By fabricating the dielectric layers with the through-holes on the surfaces of the first chip and the second chip, exposing the bumps of the first chip and metal pads of the second chip and subsequently fabricating the metal redistribution layer, the interconnections within and between the first chip and the second chip are achieved and thereby the integrated package of the first chip and the second chip is achieved. 1. A packaging method of a fan-out chip , comprising:step 1): providing a first chip with bumps and a second chip without bumps, forming a first dielectric layer on a surface of the second chip, and fabricating through-holes in the first dielectric layer;step 2): providing a carrier with a bonding layer formed on a surface, and bonding the first chip and the second chip to the bonding layer side by side;step 3): packing the first chip and the second chip, wherein the bumps of the first chip and the through-holes of the first dielectric layer on the surface of the second chip are exposed after the packing.step 4): depositing a second dielectric layer covering the first chip and the second chip, patterning a plurality of windows each aligned to one bump of the first chip and one through-hole of the second chip;step 5): fabricating a metal redistribution layer to fill the plurality of windows, wherein the metal redistribution layer provides electrical connection within the first chip and the second chip, wherein the metal redistribution layer interconnects between the ...

Semiconductor device with through-substrate via covered by a solder ball

The semiconductor device comprises a semiconductor substrate ( 10 ) with a metallization ( 111 ) having an upper terminal layer ( 22 ) located at a front side ( 20 ) of the substrate. The metallization forms a through-substrate via ( 23 ) from the upper terminal layer to a rear terminal layer ( 13 ) located opposite to the front side at a rear side ( 21 ) of the substrate. The through-substrate via comprises an annular cavity ( 18 ) and a void ( 101 ), which may be filled with air or another gas. A solder ball ( 100 ) closes the void without completely filling it. A variety of interconnections for three-dimensional integration is offered by this scheme.

SEMICONDCUTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device and a manufacturing method for the semiconductor device are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump a spacer and surrounds the bump and disposed between the etching stop layer and the bump. 17-. (canceled)8. A manufacturing method for a semiconductor device , comprising:forming an etching stop layer over a first dielectric layer, wherein the first dielectric layer is formed over a conductive structure;forming a sacrificial layer over the etching stop layer, wherein an opening passes through the sacrificial layer and the etching stop layer to expose a portion of the conductive structure;forming a spacer on a sidewall of the opening;after forming the spacer, forming a bump in the opening to electrically connect the conductive structure, wherein the spacer is disposed between the etching stop layer and the bump; andafter forming the bump, removing a portion of the spacer on the sidewall of the opening.9. The method as claimed in claim 8 , wherein the spacer is formed over the first dielectric layer between the etching stop layer and the bump.10. The method as claimed in claim 8 , wherein forming the bump and the spacer comprises:forming a spacer layer on the sidewall and a bottom of the opening;removing the spacer layer on the bottom of the opening, to expose the conductive structure and form the spacer;forming the bump in the opening, wherein the spacer on the sidewall of the opening surrounds the bump; andremoving the portion of the spacer on the sidewall of the opening.11. The method as claimed in claim 8 , further comprising forming a second dielectric layer over a portion of the first dielectric layer ...

CHIP ATTACHMENT SYSTEM

Forming the chip attachment system includes obtaining a chip having a bump core on a die. The method also includes obtaining an intermediate structure having a transfer pad on a substrate. The method further includes transferring the transfer pad from the substrate to the bump core such that the transfer pad becomes a solder layer on the bump core. 1. A flip chip system , comprising:a contact pad on a die;a chip bump on the contact pad, the chip bump including a solder layer on a bump core.2. The flip chip system of claim 1 , wherein the solder layer has a melting point between a melting point of the die and a melting point of the bump core.3. The flip chip system of claim 1 , wherein the chip bump is not connected to an external device other than the contact pad.4. The flip chip system of claim 1 , wherein the chip bump is constructed such that a plane parallel to a surface of the die and extending through the chip bump exposes a cross section where the solder layer surrounds the bump core.5. The flip chip system of claim 1 , wherein the chip bump attaches the flip chip to an electronic device.6. The flip chip system of claim 1 , wherein solder layer contacts the contact pad and a second contact pad on the electronic device.7. The flip chip system of claim 6 , wherein the solder layer surrounds the bump core.8. A method of forming a flip chip system claim 6 , comprising:obtaining a chip having a bump core on a die;obtaining an intermediate structure having a transfer pad on a substrate; andtransferring the transfer pad from the substrate to the bump core such that the transfer pad becomes a solder layer on the bump core.9. The method of claim 8 , wherein transferring the transfer pad from the substrate to the bump core includes removing the substrate from the transfer pad.10. The method of claim 8 , wherein transferring the transfer pad from the substrate to the bump core includes reflowing the transfer pad.11. The method of claim 8 , wherein the solder layer ...

SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE

A method for manufacturing a semiconductor device includes providing an adhesive film over a first surface of a semiconductor wafer on which a semiconductor device layer and a bump electrically connected to the semiconductor device layer are formed, forming a slit in the adhesive film, fragmenting the semiconductor wafer into semiconductor chips along the slit, and connecting the bump to a wiring of a circuit board within the adhesive film. 1. A method for manufacturing a semiconductor device , comprising:providing an adhesive film over a first surface of a semiconductor wafer on which a semiconductor device layer and a bump electrically connected to the semiconductor device layer are formed;forming a slit in the adhesive film;fragmenting the semiconductor wafer into semiconductor chips along the slit; andconnecting the bump to a wiring of a circuit board within the adhesive film.2. The method according to claim 1 , wherein the slit does not reach the semiconductor wafer.3. The method according to claim 2 , wherein the slit has a depth that is at least one-third of a thickness of the adhesive film.4. The method according to claim 1 , further comprising:before providing the adhesive film, emitting laser light towards a region in a second surface of the semiconductor wafer corresponding to a region of the adhesive film where the slit is to be formed.5. The method according to claim 4 , whereina crystal property of an internal portion of the semiconductor wafer is modified by the laser light, andthe fragmenting includes cleaving the semiconductor wafer at a modified region including the internal portion of the semiconductor wafer where the crystal property was modified.6. The method according to claim 5 , further comprising:after emitting the laser light but before providing the adhesive film, inspecting a condition of a crack that extends from the modified region towards the first or the second surface.7. The method according to claim 1 , wherein the forming of the ...

PRINTABLE COMPONENT STRUCTURE WITH ELECTRICAL CONTACT

A printable component structure includes a chiplet having a semiconductor structure with a top side and a bottom side, one or more top electrical contacts on the top side of the semiconductor structure, and one or more bottom electrical contacts on the bottom side of the semiconductor structure. One or more electrically conductive spikes are in electrical contact with the one or more top electrical contacts. Each spike protrudes from the top side of the semiconductor structure or a layer in contact with the top side of the semiconductor structure. 1. A printable component , comprising:a semiconductor structure with a top side and a bottom side;one or more top electrical contacts on the top side of the semiconductor structure;one or more bottom electrical contacts exposed on the bottom side of the semiconductor structure; andone or more electrically conductive spikes in electrical contact with the one or more top electrical contacts, wherein each spike protrudes from the top side of the semiconductor structure and forms an exposed electrical contact.26-. (canceled)7. The printable component of claim 1 , wherein the semiconductor structure is a multi-layer semiconductor structure having sub-layers.8. The printable component of claim 1 , wherein the semiconductor sub-layers comprises one or more members selected from the group consisting of one or more of a doped semiconductor layer claim 1 , an n-doped semiconductor layer claim 1 , and a p-doped semiconductor layer.911-. (canceled)12. The printable component of claim 1 , wherein the spike is a multi-layer spike having a spike coated with an electrically conductive spike layer.13. (canceled)14. The printable component of claim 1 , comprising one or more electrically conductive bottom spikes in electrical contact with the one or more bottom electrical contacts claim 1 , wherein each bottom spike protrudes from the bottom side of the semiconductor structure.1520-. (canceled)21. A printed structure claim 1 , comprising:a ...

Semiconductor integrated circuit device

A semiconductor integrated circuit chip, in which multi-core processors are integrated, is usually mounted over an organic wiring board by FC bonding to form a BGA package by being integrated with the substrate. In such a structure, power consumption is increased, and hence the power supplied only from a peripheral portion of the chip is insufficient, so that a power supply pad is also provided in the chip central portion. However, because of an increase in the wiring associated with the integration of a plurality of CPU cores, etc., there occurs a portion between the peripheral portion and the central portion of the chip, where a power supply pad cannot be arranged. According to the outline of the present application, in a semiconductor integrated circuit device such as a BGA, etc., in which a semiconductor chip is mounted over an interposer, such as a multilayer organic wiring board, in a face-up manner, a first group of metal through electrodes, which are provided in the semiconductor chip to supply a power supply potential to a core circuit, etc., and a first metal land over the interposer are interconnected by a first conductive adhesive member film.

Package-On-Package (PoP) Structure Including Stud Bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first surface of a first substrate;a second pad on a second surface of a second substrate;a metallic element interposed between the first pad and the second pad, the metallic element electrically coupled to the first pad, the metallic element comprising a base portion and an elongated portion extending from the base portion toward the second pad;a solder connector in contact with the elongated portion and electrically coupled to the second pad; andan inter-metallic compound (IMC) between the elongated portion and the solder connector.2. The device of claim 1 , further comprising a protection layer extending over the base portion and the elongated portion.3. The device of claim 1 , further comprising a die attached to the first substrate adjacent the metallic element.4. The device of claim 3 , wherein a height of the metallic element from the first substrate is greater than a height of the die from the first substrate.5. The device of claim 1 , wherein the metallic element comprises a copper wire.6. The device of claim 1 , wherein the base portion and the elongated portion comprises a single continuous element.7. A device comprising:a first substrate having a first pad;a second substrate having a second pad;a first connector interposed between the first pad and the second pad, the first connector having a first wide portion and a second elongated portion, the first wide portion being ...

CHIPLETS WITH CONNECTION POSTS

A component includes a plurality of electrical connections on a process side opposed to a back side of the component. Each electrical connection includes an electrically conductive multi-layer connection post protruding from the process side. A printed structure includes a destination substrate and one or more components. The destination substrate has two or more electrical contacts and each connection post is in contact with, extends into, or extends through an electrical contact of the destination substrate to electrically connect the electrical contacts to the connection posts. The connection posts or electrical contacts are deformed. Two or more connection posts can be electrically connected to a common electrical contact. 1. A printable component , comprising:a chiplet having a semiconductor substrate; anda plurality of electrical connections, wherein each electrical connection comprises an electrically conductive connection post protruding from the semiconductor substrate, wherein the connection post is a multi-layer connection post.2. The printable component of claim 1 , wherein the connection post comprises a bulk material coated with a conductive material different from the bulk material.3. The printable component of claim 2 , wherein the bulk material is electrically conductive.4. The printable component of claim 2 , wherein the conductive material has a melting point less than the melting point of the bulk material.5. The printable component of claim 2 , wherein the bulk material is an electrical insulator.6. The printable component of claim 2 , wherein the bulk material is a resin claim 2 , a polymer claim 2 , or a cured resin.7. The printable component of claim 2 , wherein the bulk material is softer than the conductive material.8. The printable component of claim 2 , wherein the conductive material is softer than the bulk material.923-. (canceled)24. A printed structure comprising a destination substrate and one or more printable components claim 2 , ...

SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME

A semiconductor package includes a first semiconductor chip having a through-electrode and an upper connection pad on an upper surface of the first semiconductor chip that is connected to the through-electrode; a second semiconductor chip stacked on the first semiconductor chip, and having a lower connection pad on a lower surface of the second semiconductor chip; a non- conductive film between the first semiconductor chip and the second semiconductor chip, with the non-conductive film including voids having an average diameter of 1μm to 100 um, the voids having a volume fraction of 0.1 to 5 vol %; and a connection conductor that penetrates the non- conductive film and connects the upper connection pad and the lower connection pad.

SEMICONDUCTOR STRUCTURE AND METHOD FOR PREPARING THE SAME

The present disclosure provides a semiconductor structure and a method for preparing it. After planarization of the Cu layer, by means of wet etch process, Cu residues near an edge of a Cu post can be effectively removed, and a first height difference is configured to be between the Cu post and an insulating layer. Further, an Si substrate is then dry etched, so that a second height difference is configured to be between the Si substrate and the insulating layer, and the second height difference is arranged to be greater than the first height difference. In this way, a connection of Cu inside and outside the insulating layer may be further avoided, thereby effectively avoiding an influence on electrical properties of a device. 1. A method for preparing a semiconductor structure , comprising following steps:providing a Si substrate;patterning a groove in the Si substrate;forming an insulating layer in the groove to cover a bottom surface and side walls of the groove;forming a Cu layer and filling the groove with a Cu post;performing planarization on the Cu layer to expose the Si substrate, the insulating layer, and the Cu post;performing a wet etch process to remove Cu residues and a part of the Cu post, wherein a first height difference is configured to be between a top surface of the Cu post and a top surface of the insulating layer; anddry etching the Si substrate, wherein a second height difference is configured to be between a top surface of the Si substrate and the top surface of the insulating layer, and wherein the second height difference is configured to be greater than the first height difference.2. The method for preparing the semiconductor structure according to claim 1 , wherein an etchant solution used during the wet etch process comprises an acid solution for a chemical reaction with Cu claim 1 , and wherein the acid solution comprises one or more of an HOsolution claim 1 , an HPOsolution claim 1 , and an HSOsolution.3. The method for preparing the ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint coupled with and standing on the first pad, a joint encapsulating the post and bonding the first pad with the second pad, a first entire contact interface between the first pad and the joint, a second entire contact interface between the first pad and the post, and a third entire contact interface between the joint and the second pad. The first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces. A distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface. The second entire contact interface is a continuous surface. 1. A semiconductor device , comprising:a silicon substrate;a carrier;a first pad on the silicon substrate;a second pad on the carrier;a post on a surface of the first pad, wherein the post consists of a metal or a metal alloy;a joint disposed between the silicon substrate and the carrier, contacted with the first pad and the second pad, and encapsulating the post;a first entire contact interface between the first pad and the joint;a second entire contact interface between the first pad and the post; anda third entire contact interface between the joint and the second pad,wherein an outer surface of the joint is concaved and curved towards the post, and a height of the post is greater than or equal to ⅓ of a height of the joint between the first pad and the second pad, the first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces, wherein a distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface, ...

Anisotropic conductive film structures

Anisotropic conductive film (ACF) structures and manufacturing methods for forming the same are described. The manufacturing methods include preventing clusters of conductive particles from forming between adjacent bonding pads and that are associated with electrical shorting of ACF structures. In some embodiments, the methods involve use of multiple layered ACF materials that include a non-electrically conductive layer that reduces the likelihood of formation of conductive particle clusters between bonding pads. In some embodiment, the methods include the use of ultraviolet sensitive ACF material combined with lithography techniques that eliminate conductive particles from between neighboring bonding pads. In some embodiments, the methods involve the use of insulation spacers that block conductive particles from entering between bonding pads. Any suitable combination of the described methods can be used.

CHIP PACKAGE STRUCTURE

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first bump and a first dummy bump between the chip and the substrate. The first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump. 1. A chip package structure , comprising:a substrate;a chip over the substrate; anda first bump and a first dummy bump between the chip and the substrate, wherein the first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump.2. The chip package structure as claimed in claim 1 , wherein the first dummy bump has a first strip portion and a second strip portion claim 1 , and the first strip portion is not parallel to the second strip portion.3. The chip package structure as claimed in claim 2 , wherein the chip has a first edge and a second edge claim 2 , the first edge and the second edge meet at the corner of the chip claim 2 , and the first strip portion is substantially parallel to the first edge.4. The chip package structure as claimed in claim 3 , wherein the second strip portion is substantially parallel to the second edge.5. The chip package structure as claimed in claim 1 , further comprising:an underfill layer between the chip and the substrate and between the first dummy bump and the substrate.6. The chip package structure as claimed in claim 1 , further comprising:a second bump between the first bump and the substrate; anda second dummy bump between the chip and the substrate, wherein the second dummy bump is connected to the ...

PACKAGED SEMICONDUCTOR DEVICES WITH UNIFORM SOLDER JOINTS

An example apparatus includes a semiconductor die including a bond pad; a conductive post on the bond pad; a solder joint electrically connecting the conductive post to a substrate; and ink residue of solder mask material surrounding a portion of the solder joint, the ink residue covering a portion of the substrate. Methods for forming the apparatus are disclosed. 1. An apparatus , comprising:a semiconductor die including a bond pad electrically connected to a circuitry in the semiconductor die;a conductive post on the bond pad;a solder joint electrically connecting the conductive post to a substrate; andink residue of solder mask material contacting and surrounding a portion of the solder joint, the ink residue covering a portion of the substrate.2. The apparatus of claim 1 , wherein the ink residue is an ink-jet deposited material.3. The apparatus of claim 1 , wherein the ink residue is one selected from a group consisting essentially of: DiPaMat SM G01 (Agfa) claim 1 , SMI100 (Adeon) claim 1 , and SMI-200F (Adeon).4. The apparatus of claim 1 , wherein the ink residue is at least 15 μm thick.5. The apparatus of claim 1 , wherein an ink residue geometry surrounding a solder joint region is at least about 50 μm wide.6. The apparatus of claim 1 , wherein the conductive post is directly on the bond pad claim 1 , and the conductive post comprises copper or copper alloy.7. A method for forming an apparatus claim 1 , comprising:ink-jet depositing material forming an ink residue surrounding a portion of a solder joint area and covering a portion of a surface of a substrate;bringing a solder bump that is atop a conductive post, the conductive post directly on a bond pad of a semiconductor die, into contact with the solder joint area; andmelting the solder bump and forming a solder joint between the conductive post and the surface of the substrate, the solder joint partially surrounded by the ink residue.8. The method of claim 7 , where the ink residue is a solder mask ...

CHIP WITH MAGNETIC INTERCONNECT ALIGNMENT

An electronic assembly, and a method for making the electronic assembly, includes a first electronic component, a second electronic component, and a plurality of interconnects. The plurality of interconnects electrically couple the first electronic component to the second electronic component. Each of the plurality of interconnects comprise one of a plurality of first magnetic components in physical alignment with an associated one of a plurality of second magnetic components, the plurality of second magnetic components being components of one of the second electronic component and the plurality of interconnects. 125-. (canceled)26. An electronic assembly , comprising:a first electronic component;a second electronic component; anda plurality of interconnects, electrically coupling the first electronic component to the second electronic component, each of the plurality of interconnects comprising one of a plurality of first magnetic components in physical alignment with an associated one of a plurality of second magnetic components, the plurality of second magnetic components being components of one of the second electronic component and the plurality of interconnects.27. The electronic assembly of :wherein the first electronic component is a die and the plurality of interconnects are interconnects of the die; andwherein the second electronic component is a substrate and the plurality of second magnetic components of are conductive magnetic pads positioned on a major surface of the substrate.28. The electronic assembly of claim 27 , wherein each of the plurality of interconnects further comprise a nonmagnetic conductor coupled to the die and each of the plurality of first magnetic components is a conductive magnetic cap electrically coupled between the nonmagnetic conductor and the associated one of the conductive magnetic pads.29. The electronic assembly of claim 28 , wherein the conductive magnetic cap is bonded to the associated one of the conductive magnetic pads ...

METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURE FOR JOINING WAFERS AND RESULTING STRUCTURE

The disclosure is directed to an integrated circuit structure for joining wafers. The IC structure may include: a metallic pillar over a substrate, the metallic pillar including an upper surface; a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and a solder material over the upper surface of the metallic pillar, the solder material being within and constrained by the wetting inhibitor layer. The sidewall of the metallic pillar may be free of the solder material. 1. An integrated circuit structure for joining wafers , the integrated circuit structure comprising:a metallic pillar over a substrate, the metallic pillar including an upper surface;a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar, wherein the wetting inhibitor layer includes a periphery with a first thickness and an inner edge with a second thickness, wherein the first thickness is greater than the second thickness; anda solder material over the upper surface of the metallic pillar, the solder material being within and constrained by the wetting inhibitor layer.2. The integrated circuit structure of claim 1 , wherein the wetting inhibitor layer includes a dielectric or a fluorocarbon.3. The integrated circuit structure of claim 1 , wherein the metallic pillar includes at least one of copper or nickel.4. The integrated circuit structure of claim 1 , wherein the wetting inhibitor layer includes a width of approximately 2.0 micrometers (μm) to approximately 6.0 μm.5. (canceled)6. The integrated circuit structure of claim 1 , wherein a sidewall of the metallic pillar is free of the solder material.7. The integrated circuit of claim 1 , wherein the metallic pillar includes a plurality of layers.8. The integrated circuit of claim 1 , wherein an upper surface of the metallic pillar is substantially circular.9. The integrated circuit structure of claim 8 , wherein the wetting inhibitor layer defines an annular ring over the metallic ...

SEMICONDUCTOR PACKAGE INTERCONNECT

A semiconductor package interconnect system may include a conductive pillar having a core, a first layer surrounding the core, and a second layer surrounding the first layer. The core may be composed of a drawn copper wire, the first layer may be composed of nickel, and the second layer may be composed of a solder. A method for manufacturing a semiconductor package with such a conductive pillar may include placing a plurality of conductive pillars on a substrate using a stencil process. 1. A package interconnect apparatus , comprising:a conductive pillar with a core and a first layer that at least partially surrounds the core, the core comprises a copper material;a redistribution layer coupled to the conductive pillar; anda die coupled to the redistribution layer proximate to the conductive pillar.2. The package interconnect apparatus system of . wherein the core is composed of a drawn copper wire and the first layer is composed of a solder material.3. The package interconnect apparatus of claim 1 , wherein the conductive pillar has a second layer surrounding the first layer claim 1 , the first layer is composed of a conductive interface material and the second layer is composed of a solder material.4. The package interconnect apparatus of claim 1 , further comprising:a conductive pad coupled to the redistribution layer; anda solder joint on the conductive pad between the conductive pad and the conductive pillar.5. The package interconnect apparatus system of claim 1 , wherein the conductive pillar has a aspect ratio of a height to a width greater than 2 to 1.6. The package interconnect apparatus of claim 1 , further comprising:a plurality of additional conductive pillars, each of the plurality of additional conductive pillars having a core, a first layer surrounding the core, and a second layer surrounding the first layer;a plurality of conductive pads coupled to the redistribution layer;a plurality of solder joints coupled between the plurality of conductive pads ...

SERIALIZER-DESERIALIZER DIE FOR HIGH SPEED SIGNAL INTERCONNECT

In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed. 1. A semiconductor package comprising:a first die;a second die; anda first serializer/deserializer (SerDes) die physically coupled with the first die and communicatively coupled with the second die, wherein the first SerDes die is to serialize signals transmitted from the first die to the second die, and the first SerDes die is to deserialize signals received from the second die.2. The semiconductor package of claim 1 , wherein the die is a monolithic die or a composite die.3. The semiconductor package of claim 1 , further comprising a second SerDes die physically coupled with the second die and communicatively coupled with the first SerDes die claim 1 , wherein the second SerDes die is to serialize signals transmitted from the second die to the first die claim 1 , and the second SerDes die is to deserialize signals received from the first die.4. The semiconductor package of claim 1 , wherein the first SerDes die has first pads at a first pitch at a side of the SerDes die coupled with the first die claim 1 , and the first SerDes die has second pads at a second pitch at a side of the SerDes die communicatively coupled with the second die.5. The semiconductor package of claim 4 , wherein the first pitch is larger than the second pitch.6. The semiconductor package of claim 1 , wherein the second die is an interposer.7. The semiconductor package of claim 1 , wherein the second die is a dual-sided interconnect die that includes an active component.8. A method of forming a die with a serializer/deserializer (SerDes) die attached thereto claim 1 , the method comprising: ...

SEMICONDUCTOR DEVICE HAVING BUMP STRUCTURES AND SEMICONDUCTOR PACKAGE HAVING THE SAME

A semiconductor device including a substrate including a first conductive pad on a first surface thereof, at least one first bump structure on the first conductive pad, the first bump structure including a first connecting member and a first delamination prevention layer, the first delamination prevention layer on the first connecting member and having a greater hardness than the first connecting member, and a first encapsulant above the first surface of the substrate and surrounding the first bump structure may be provided. 1. A semiconductor device comprising:a substrate including a first conductive pad on a first surface thereof;at least one first bump structure on the first conductive pad, the first bump structure including a first connecting member and a first delamination prevention layer, the first delamination prevention layer on the first connecting member and having a greater hardness than the first connecting member; anda first encapsulant above the first surface of the substrate and surrounding the first bump structure.2. The semiconductor device of claim 1 , wherein the first delamination prevention layer comprises an intermetallic compound.3. The semiconductor device of claim 2 , wherein the intermetallic compound comprises a Cu—Sn based intermetallic compound claim 2 , an Au-Sn based intermetallic compound claim 2 , or a combination thereof.4. The semiconductor device of claim 1 , wherein the first bump structure further comprises a metal layer disposed on an upper surface of the first delamination prevention layer.5. The semiconductor device of claim 1 , wherein an upper surface of the first delamination prevention layer is exposed to an outside of the first encapsulant.6. The semiconductor device of claim 1 , wherein a thickness of the first delamination prevention layer is smaller than a thickness of the first connecting member.7. The semiconductor device of claim 1 , whereinan upper surface of the first delamination prevention layer and an upper ...

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pith region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed. 1. A semiconductor package structure , comprising:a first carrier having a first surface, the first surface comprising a first region and a second region;a second carrier having a second surface opposing the first surface, the second surface comprising a third region corresponding to the first region and a fourth region corresponding to the second region;a plurality of first type conductive pillars between the first region of the first surface and the third region of the second surface; anda plurality of second type conductive pillars between the second region of the first surface and the fourth region of the second surface;wherein a contact resistance of each of the first type conductive pillars is lower than a contact resistance of each of the second type conductive pillars.2. The semiconductor package structure of claim 1 , wherein each of the plurality of first type conductive pillars comprises a copper-copper interface.3. The semiconductor package structure of claim 2 , wherein each of the plurality of second type conductive pillars comprises a copper-solder interface.4. The semiconductor package structure of claim 1 , wherein a pitch of the first type conductive pillars in the first region is smaller than a pitch of the second type conductive pillars in the second region.5. The semiconductor package structure of claim 4 , wherein the pitch of the first type conductive pillars in the first region is ...

Cu pillar bump with l-shaped non-metal sidewall protection structure

A method of forming an integrated circuit device includes forming a bump structure on a substrate, wherein the bump structure has a top surface and a sidewall surface, and the substrate has a surface region exposed by the bump structure. The method further includes depositing a non-metal protection layer on the top surface and the sidewall surface of the bump structure and the surface region of the substrate. The method further includes removing the non-metal protection layer from the top surface of the bump structure, wherein a remaining portion of the non-metal protection layer forms an L-shaped protection structure, and a top surface of the remaining portion of the non-metal protection layer is farther from the substrate than a top surface of the bump structure.

DRIVER INTEGRATED CIRCUIT CHIP, DISPLAY DEVICE HAVING THE SAME, AND METHOD OF MANUFACTURING A DRIVER INTEGRATED CIRCUIT CHIP

A driver integrated circuit chip is provided. The driver integrated circuit chip includes a base substrate including at least one driver integrated circuit, a plurality of metal lines, and a passivation layer covering the driver integrated circuit and the metal lines; a plurality of input bumps arranged near a first longer side of the base substrate; a plurality of output bumps arranged near a second longer side of the base substrate; and a plurality of dummy bumps arranged on a central region of the base substrate, the dummy bumps being arranged between the input bumps and the output bumps. Each of the dummy bumps has a stacked layer structure that is different from a stacked layer structure of each of the input bumps and the output bumps. 1. A driver integrated circuit chip comprising:a base substrate including at least one driver integrated circuit, a plurality of metal lines, and a passivation layer covering the driver integrated circuit and the metal lines;a plurality of input bumps arranged near a first longer side of the base substrate;a plurality of output bumps arranged near a second longer side of the base substrate; anda plurality of dummy bumps arranged on a central region of the base substrate, the dummy bumps being arranged between the input bumps and the output bumps,wherein each of the dummy bumps has a stacked layer structure that is different from a stacked layer structure of each of the input bumps and the output bumps.2. The driver integrated circuit chip of claim 1 , wherein a first metal is stacked on portions of the passivation layer where the dummy bumps are arranged.3. The driver integrated circuit chip of claim 2 , wherein the first metal is stacked on portions of the metal lines where the input bumps and the output bumps are arranged.4. The driver integrated circuit chip of claim 3 , wherein the passivation layer includes an insulating material.5. The driver integrated circuit chip of claim 1 , wherein the base substrate includes a ...

Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration

A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.

SEMICONDUCTOR DEVICE

A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer. 1. A semiconductor comprising:an insulating layer;a barrier electrode layer formed on the insulating layer;a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer; andan outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.2. The semiconductor device according to claim 1 , wherein the outer-surface insulating film is in contact with the principal surface of the barrier electrode layer at a position with an interval from a peripheral edge of the barrier electrode layer toward an inward side of the barrier electrode layer.3. The semiconductor device according to claim 1 , wherein the Cu electrode layer includes a first surface and a second surface that is positioned on a side opposite to the first surface and that is connected to the barrier electrode layer claim 1 , anda peripheral edge of the second surface of the Cu electrode layer is formed at a position with an interval from the peripheral edge of the barrier electrode layer toward the inward side of the barrier electrode layer.4. The semiconductor device according to claim 1 , wherein the Cu electrode layer includes a first surface and a second surface that is positioned on a side opposite to the first surface and that is connected to the barrier electrode layer claim 1 , andthe second surface of the Cu electrode layer is formed narrower than ...

Thermocompression bonding of electronic components

A method for producing an electronic module includes providing a first substrate including at least one first electrical contacting surface, an electronic component including at least one second electrical contacting surface, and a first material layer made of a thermoplastic material including at least one recess extending through the material layer. The first substrate, the electronic component and the first material layer are arranged with the first material layer disposed between the first substrate and the electronic component, and the at least one first electrical contacting surface, the at least one second electrical contacting surface and the at least one recess aligned relative to one another. The first substrate, the electronic component and the material layer are thermocompression bonded. A joint formed between the at least one first electrical contacting surface and the at least one second electrical contacting surface is surrounded or enclosed by the first material layer.

ELECTRONIC COMPONENT, ELECTRONIC APPARATUS, AND METHOD OF MANUFACTURING ELECTRONIC APPARATUS

An electronic component includes a substrate configured to include a first portion that first thermal conductivity, and have a first surface and a second surface opposite to the first surface;a second portion configured to be formed inside the first portion, and have second thermal conductivity lower than the first thermal conductivity;a first terminal configured to be formed to correspond to the second portion on a side of the first surface; and a second terminal configured to be formed on a side of the second surface. 1. An electronic component comprising: include a first portion that first thermal conductivity, and', 'have a first surface and a second surface opposite to the first surface;, 'a substrate configured to'} be formed inside the first portion, and', 'have second thermal conductivity lower than the first thermal conductivity;, 'a second portion configured to'}a first terminal configured to be formed to correspond to the second portion on a side of the first surface; anda second terminal configured to be formed on a side of the second surface.2. The electronic component according to claim 1 ,wherein the second portion includes a hollow portion.3. The electronic component according to claim 1 ,wherein the substrate includes an insulation layer that is formed between the second portion and the first terminal and covers the second portion.4. The electronic component according to claim 1 ,wherein the first terminal includes a solder.5. An electronic apparatus comprising: a first substrate configured to', 'include a first portion having first thermal conductivity, and', 'have a first surface and a second surface opposite to the first surface,, 'a first electronic component configured to include'} be formed inside the first portion, and', 'have second thermal conductivity lower than the first thermal conductivity,, 'a second portion configured to'} 'a second terminal configured to be formed on a side of the second surface of the first substrate opposite to the ...

Semiconductor packages

A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.

SEMICONDUCTOR CONTACT STRUCTURE HAVING STRESS BUFFER LAYER FORMED BETWEEN UNDER BUMP METAL LAYER AND COPPER PILLAR

Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer. 1. A semiconductor apparatus , comprising:a semiconductor substrate having at least one metal pad;a first passivation layer formed on the semiconductor substrate and covering a portion of the at least one metal pad, the first passivation layer having at least one first passivation layer opening to expose a first portion of the at least one metal pad;a second passivation layer formed on the first passivation layer, the second passivation layer having at least one second passivation layer opening to expose a second portion of the at least one metal pad;an under bump metal layer at least formed on the second portion of the at least one metal pad exposed by the second passivation layer opening;a stress buffer layer formed on the under bump metal layer, wherein the material of the stress buffer layer comprises tin, tin-silver, tin alloy, indium or indium alloy; anda copper pillar disposed on the stress buffer layer.2. The semiconductor apparatus according to claim 1 , wherein the material of the under bump metal layer comprises ...

Bonded Structures for Package and Substrate

The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.

PACKAGE ON PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

The described embodiments of mechanisms of forming a package on package (PoP) structure involve bonding with connectors with non-solder metal balls to a packaging substrate. The non-solder metal balls may include a solder coating layer. The connectors with non-solder metal balls can maintain substantially the shape of the connectors and control the height of the bonding structures between upper and lower packages. The connectors with non-solder metal balls are also less likely to result in bridging between connectors or disconnection (or cold joint) of bonded connectors. As a result, the pitch of the connectors with non-solder metal balls can be kept small. 1. A semiconductor device package , comprising:a substrate with a contact pad;a semiconductor die bonded to the contact pad by a first bonding structure; andwherein the first bonding structure includes a metal ball comprising a non-solder material, a solder layer over a surface of the non-solder material, and an intermediate layer between the solder layer and the non-solder material, wherein the intermediate layer is configured to prevent formation of an intermetallic compound between the metal ball and the solder layer, wherein the non-solder material includes copper, aluminum, silver, gold, nickel, tungsten, alloys thereof, or combinations thereof, and the intermediate layer comprises titanium.2. The semiconductor device package of claim 1 , wherein a width or diameter of the metal ball is in a range from about 100 μm to about 200 μm.3. The semiconductor device package of claim 1 , wherein the semiconductor device package has another metal ball next to the metal ball claim 1 , and a pitch of the metal ball and the another metal ball is in a range from about 150 μm to about 300 μm.4. The semiconductor device package of claim 1 , wherein the solder layer is a continuous layer that coats the intermediate layer.5. The semiconductor device package of claim 1 , wherein the metal ball is arranged over and electrically ...

Integrated device comprising interconnect structures having an inner interconnect, a dielectric layer and a conductive layer

An integrated device that includes a substrate, an interconnect portion and an interconnect structure. The interconnect portion is located over the substrate. The interconnect portion includes a plurality of interconnects and at least one dielectric layer. The interconnect structure is located over the interconnect portion. The interconnect structure includes an inner interconnect, a dielectric layer coupled to the inner interconnect, and an outer conductive layer coupled to the dielectric layer. The outer conductive layer is configured to operate as a shield for the inner interconnect.

CIRCUIT SYSTEM HAVING COMPACT DECOUPLING STRUCTURE

A circuit system having compact decoupling structure, including: a mother board; at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, the substrate having a first surface and a second surface, the first metal contacts being formed on the first surface and soldered onto the mother board, the second metal contacts being formed on the logic-circuit die and soldered onto the second surface to form flip-chip pillars, and the flip-chip pillars determining a height of a gap between the die and the substrate; and at least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit; wherein each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die and at least one stack-type integrated-passive-device die. 1. A circuit system having compact decoupling structure , including:a mother board;at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, wherein the substrate has a first surface and a second surface opposing the first surface, the first metal contacts are formed on the first surface and soldered onto the mother board, the second metal contacts are formed on the logic-circuit die and soldered onto the second surface of the substrate to form flip-chip pillars, and the flip-chip pillars determine a height of a gap between the logic-circuit die and the substrate; andat least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit;wherein, each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die, at least one stack-type integrated-passive-device die, and a plurality of third metal contacts, the third metal contacts being formed on the mother die and soldered onto the logic-circuit die, and ...

CHIPLETS WITH CONNECTION POSTS

A component includes a plurality of electrical connections on a process side opposed to a back side of the component. Each electrical connection includes an electrically conductive multi-layer connection post protruding from the process side. A printed structure includes a destination substrate and one or more components. The destination substrate has two or more electrical contacts and each connection post is in contact with, extends into, or extends through an electrical contact of the destination substrate to electrically connect the electrical contacts to the connection posts. The connection posts or electrical contacts are deformed. Two or more connection posts can be electrically connected to a common electrical contact. 181-. (canceled)82. A printed structure , comprising:a chiplet comprising a chiplet substrate and a connection post protruding from the chiplet substrate, wherein the connection post has a base area greater than a peak area; anda destination substrate comprising a non-planar contact, wherein the non-planar contact has a perimeter portion surrounding a recessed central portion and the non-planar contact is sized and shaped to accept the connection post, andwherein the connection post is inserted into the non-planar contact.83. The printed structure of claim 82 , wherein the connection post comprises a bulk material coated with a material that is different from the bulk material.84. The printed structure of claim 83 , wherein the coated material is a metal.85. The printed structure of claim 82 , wherein the connection post comprises a bulk material.86. The printed structure of claim 85 , wherein the bulk material is silicon dioxide claim 85 , silicon nitride claim 85 , a resin claim 85 , a polymer claim 85 , or a cured resin.87. The printed structure of claim 82 , wherein the connection post has substantially planar sides claim 82 , has a sharp point claim 82 , or is substantially pyramidal.88. The printed structure of claim 82 , wherein the ...

Anchoring structure of fine pitch bva

A microelectronic package can include a substrate having a first surface and a second surface opposite therefrom, the substrate having a first conductive element at the first surface, and a plurality of wire bonds, each of the wire bonds having a base electrically connected to a corresponding one of the first conductive elements and having a tip remote from the base, each wire bond having edge surfaces extending from the tip toward the base. The microelectronic package can also include an encapsulation having a major surface facing away from the first surface of the substrate, the encapsulation having a recess extending from the major surface in a direction toward the first surface of the substrate, the tip of a first one of the wire bonds being disposed within the recess, and an electrically conductive layer overlying an inner surface of the encapsulation exposed within the recess, the electrically conductive layer overlying and electrically connected with the tip of the first one of the wire bonds.

Semiconductor packages and methods of manufacturing the same

A semiconductor package includes a first semiconductor chip having a through-electrode and an upper connection pad on an upper surface of the first semiconductor chip that is connected to the through-electrode; a second semiconductor chip stacked on the first semiconductor chip, and having a lower connection pad on a lower surface of the second semiconductor chip; a non-conductive film between the first semiconductor chip and the second semiconductor chip, with the non-conductive film including voids having an average diameter of 1 μm to 100 μm, the voids having a volume fraction of 0.1 to 5 vol %; and a connection conductor that penetrates the non-conductive film and connects the upper connection pad and the lower connection pad.

Package-On-Package (PoP) Structure Including Stud Bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first surface of a first package;a second pad on a second surface of a second package;a metallic element interposed between the first pad and the second pad, the metallic element comprising a base portion and an elongated portion, the base portion being coupled to the first pad, the elongated portion extending from the base portion toward the second pad, wherein a width of the base portion is greater than a width of the elongated portion;a solder connector in contact with the elongated portion and electrically coupled to the second pad; andan inter-metallic compound (IMC) between the elongated portion and the solder connector.2. The device of claim 1 , wherein the first package comprises a first substrate and a first integrated circuit die attached to the first substrate claim 1 , wherein the second package comprises a second substrate and a second integrated circuit die attached to the second substrate.3. The device of claim 2 , wherein the metallic element is laterally adjacent the first integrated circuit die with the first integrated circuit die and the metallic element being interposed between the first substrate and the second substrate.4. The device of claim 3 , wherein the metallic element extends closer to the second substrate than the first integrated circuit die.5. The device of claim 1 , wherein a height of the metallic element is between about 20 micrometers and about 200 ...

Method for forming through silicon via with wafer backside protection

Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.

PACKAGE ON PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface. 1. A semiconductor device comprising a solder ball , the solder ball comprising:a metal ball;a layer of solder over an outer surface of the metal ball; andan intermediate layer separating the metal ball and the layer of solder, wherein the intermediate layer has a first annular thickness on a first portion of the metal ball and has a second annular thickness on a second portion of the metal ball, the second annular thickness being greater than the first annular thickness.2. The semiconductor device of claim 1 , further comprising:a semiconductor substrate; anda contact pad over the semiconductor substrate, wherein the metal ball is disposed over the contact pad; andwherein the intermediate layer is elongated along an axis that is perpendicular to an upper surface of the contact pad, such that the intermediate layer has a height as measured from the upper surface of the contact pad to an uppermost extent of the intermediate layer along the axis, and has a diametric width between its outermost sidewalls, the diametric width being less than the height.3. The semiconductor device of claim 1 , wherein the intermediate layer is configured to prevent formation of an intermetallic compound between the metal ...

CHIP PACKAGE ASSEMBLY WITH ENHANCED INTERCONNECTS AND METHOD FOR FABRICATING THE SAME

An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a first substrate containing first circuitry, a first contact pad, a first pillar, a first pillar protection layer, a second substrate containing second circuitry, and a solder ball disposed on the first pillar and electrically and mechanically coupling the first substrate to the second substrate. The first contact pad is disposed on the first substrate and coupled to the first circuitry. The first pillar electrically disposed over the first contact pad. The first pillar protection layer is hydrophobic to solder and is disposed on a side surface of the first pillar. 1. An integrated circuit interconnect comprising:a first substrate containing first circuitry;a first contact pad disposed on the first substrate and coupled to the first circuitry;a first pillar electrically disposed over the first contact pad;a first pillar protection layer disposed on a side surface of the first pillar, the first pillar protection layer being hydrophobic to solder, wherein the first pillar protection layer is copper sulfide;a second substrate containing second circuitry; anda solder ball disposed on the first pillar and electrically and mechanically coupling the first substrate to the second substrate.2. The integrated circuit interconnect of claim 1 , wherein the first pillar protection layer comprises:an inorganic passivation material that is hydrophobic to solder.3. (canceled)4. The integrated circuit interconnect of claim 1 , wherein the first pillar protection layer can be expressed as CuS.5. The integrated circuit interconnect of claim 1 , wherein the first pillar protection layer is at least one of CuS and CuS.6. The integrated circuit interconnect of claim 1 , wherein the first pillar protection layer is not formed on a bottom surface or a top surface of the first pillar.7. The ...

FABRICATION METHOD OF HIGH ASPECT RATIO SOLDER BUMPING WITH STUD BUMP AND INJECTION MOLDED SOLDER, AND FLIP CHIP JOINING WITH THE SOLDER BUMP

A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps. 1. A method for fabricating bumps on a substrate , the method comprising:preparing a substrate including a set of pads formed on a surface thereof;forming a bump base on each pad of the substrate, each bump base having a tip extending outwardly from the corresponding pad;patterning a resist layer on the substrate to have a set of holes through the resist layer, each hole being aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad;filling the set of the holes with conductive material to form a set of bumps on the substrate; andstripping the resist layer from the substrate leaving the set of the bumps.2. The method of claim 1 , wherein the conductive material is solder material and injected into each hole in a molten state and the set of the bumps is a set of solder capped bumps each being made of material of the bump base formed on the substrate and the solder material filled into the hole.3. The method of claim 1 , wherein each bump base extends the tip in a direction approximately normal to the surface of the substrate claim 1 , and the resist layer has a thickness aligned to the levels of the tips of the bump bases.4. The method of claim 1 , wherein each bump base is a stud bump formed by ...

ELECTRICALLY CONDUCTIVE PILLAR, BONDING STRUCTURE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING ELECTRICALLY CONDUCTIVE PILLAR

An electrically conductive pillar that can bond a base member and a member to be bonded together with high bonding strength with a bonding layer interposed therebetween and a method for manufacturing the same. Specifically, an electrically conductive pillar is composed of a sintered body of metal micro-particles disposed on a base member . The average particle size of the metal micro-particles is less than 1 μm as measured using a small-angle X-ray scattering method. An upper surface of the sintered body has a concave shape recessed on the base member side. The metal micro-particles are preferably made of one or more metals selected from Ag and Cu. 1. An electrically conductive pillar composed of a sintered body of metal micro-particles disposed on a base member ,wherein an average particle size of the metal micro-particles is less than 1 μm as measured using a small-angle X-ray scattering method, andan upper surface of the sintered body has a concave shape recessed on a base member side.2. The electrically conductive pillar according to claim 1 , wherein the metal micro-particles are made of one or more metals selected from Ag and Cu.3. A bonding structure disposed between a base member and a member to be bonded claim 1 , the member to be bonded being disposed opposite to the base member claim 1 , the bonding structure comprising:an electrically conductive pillar composed of a sintered body of metal micro-particles disposed on the base member, an average particle size of the metal micro-particles being less than 1 μm as measured using a small-angle X-ray scattering method, an upper surface of the sintered body having a concave shape recessed on a base member side; anda bonding layer provided along the concave shape of the electrically conductive pillar.4. The bonding structure according to claim 3 , wherein the electrically conductive pillar has a plurality of groove sections that extend from the upper surface toward the base member and has anchoring sections made ...

METHOD FOR MANUFACTURING INTERCONNECT STRUCTURE

A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b). 1. A method of manufacturing a conductive interconnect structure , comprising:disposing a cover layer on a semiconductor package;forming a through opening in the cover layer;filling a first conductive material into the through opening by a first operation, wherein the first operation is configured to generate an average grain size (a) of the first conductive material;forming a mask layer around the first conductive material with a gap between the mask layer and a sidewall surface of the first conductive material; andforming a second conductive material on an outer surface of the first conductive material by a second operation, wherein the second operation is configured to generate an average grain size (b) of the second conductive material,wherein the average grain size (a) is greater than the average grain size (b), and wherein the first conductive material and the second conductive material are substantially the same.2. The method in claim 1 , wherein the second conductive material is further formed on the sidewall surface of the first conductive material through the gap between the mask layer and the sidewall surface of the first conductive material.3. The method in claim 1 , wherein the forming the mask layer around the first conductive material with the gap between the mask layer and the sidewall ...

ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME

An electronic device includes a dielectric layer, a redistribution layer, a conductive structure, an insulating layer and a solder bump. The dielectric layer has a first surface and a second surface opposite to the first surface, and defines a through hole extending between the first surface and the second surface. The redistribution layer is disposed on the first surface of the dielectric layer and in the through hole. The conductive structure is disposed on the redistribution layer. The conductive structure includes an upper portion and a lower portion. The lower portion is disposed on the redistribution layer, and the upper portion is disposed on the lower portion. The insulating layer covers a portion of the redistribution layer and surrounds a first portion of the lower portion of the conductive structure. The solder bump covers a portion of the conductive structure. 1. An electronic device , comprising:a dielectric layer having a first surface and a second surface opposite to the first surface, and defining a through hole extending between the first surface and the second surface;a redistribution layer disposed on the first surface of the dielectric layer and in the through hole;a conductive structure disposed on the redistribution layer, wherein the conductive structure includes an upper portion and a lower portion, the upper portion has a cone shape and has a convex side wall that bulges outwards, the lower portion has a disk shape and has a convex side wall that bulges outwards, the lower portion is disposed on the redistribution layer, and the upper portion is disposed on the lower portion;an insulating layer covering a portion of the redistribution layer and surrounding a first portion of the lower portion of the conductive structure; anda solder bump covering a portion of the conductive structure.2. The electronic device of claim 1 , wherein a volume of the lower portion of the conductive structure is greater than a volume of the upper portion of the ...

Methods of forming semiconductor die assemblies

Semiconductor assemblies, structures, and methods of fabrication are disclosed. A coating is formed on an electrically conductive pillar. The coating, which may be formed from at least one of a silane material and an organic solderability protectant material, may bond to a conductive material of the electrically conductive pillar and, optionally, to other metallic materials of the electrically conductive pillar. The coating may also bond to substrate passivation material, if present, or to otherwise-exposed surfaces of a substrate and a bond pad. The coating may be selectively formed on the conductive material. Material may not be removed from the coating after formation thereof and before reflow of the solder for die attach. The coating may isolate at least the conductive material from solder, inhibiting solder wicking or slumping along the conductive material and may enhance adhesion between the resulting bonded conductive element and an underfill material.

TRANSIENT INTERFACE GRADIENT BONDING FOR METAL BONDS

A method and apparatus for performing metal-to-metal bonding for an electrical device and an electrical device produced thereby. For example and without limitation, various aspects of this disclosure provide a process that comprises depositing a thin metal layer on a copper pillar and then mating the copper pillar with another copper element. Atoms of the thin metal layer may, for example, form a substitutional solid solution or intermetallic compounds with copper. A concentration gradient is introduced by the thin metal layer, and diffusion at the Cu-Cu interface begins immediately. The thin metal film and the copper may, for example, diffuse until the interface disappears or substantially disappears. 1. A method comprising:providing a first substrate comprising a first metal structure of a first metal;providing a second substrate comprising a second metal structure of the first metal;depositing a layer of a second metal on the first metal structure, wherein the second metal is a metal capable of diffusing into the first metal structure to form a substitutional solid solution with the first metal of the first metal structure;after said depositing, mating the first and second substrates to bring the deposited layer on the first metal structure in direct contact with the second metal structure; andapplying a pressure of less than 100 MPa while diffusion of the layer of the second metal into the first metal structure and into the second metal structure takes place.2. The method of claim 1 , wherein said applying a pressure comprises applying a pressure of less than 10 MPa.3. The method of claim 1 , wherein a time between said depositing and said mating is small enough to result in a concentration gradient between the layer of the second metal and the first metal structure at a time of said mating.4. The method of claim 1 , wherein said depositing a layer comprises:adhering the layer of the second metal to a surface;after said adhering, placing the first metal ...

Package on package structure and method for forming the same

Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.

SEMICONDUCTOR DEVICE WITH INTERCONNECT STRUCTURE AND METHOD FOR PREPARING THE SAME

A semiconductor device includes a conductive pattern disposed over a semiconductor substrate, and an interconnect structure disposed over the conductive pattern. The semiconductor device also includes an interconnect liner formed between the interconnect structure and the conductive pattern and surrounding the interconnect structure. The inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern. The semiconductor device further includes a semiconductor die bonded to the semiconductor substrate. The semiconductor die includes a conductive pad facing the interconnect structure, wherein the conductive pad is electrically connected to the conductive pattern. 1. A semiconductor device , comprising:a conductive pattern disposed over a semiconductor substrate;an interconnect structure disposed over the conductive pattern;an interconnect liner disposed between the interconnect structure and the conductive pattern and surrounding the interconnect structure, wherein inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern; anda semiconductor die bonded to the semiconductor substrate, wherein the semiconductor die comprises a conductive pad facing the interconnect structure; and the conductive pad is electrically connected to the conductive pattern.2. The semiconductor device of claim 1 , wherein a width of the interconnect structure is greater than the width of the conductive pattern.3. The semiconductor device of claim 1 , wherein the interconnect liner has a protruding portion in direct contact with a sidewall surface of the conductive pattern.4. The semiconductor device of claim 3 , further comprising:a sidewall spacer ...

BRASS-COATED METALS IN FLIP-CHIP REDISTRIBUTION LAYERS

In some examples, a package comprises a die and a redistribution layer coupled to the die. The redistribution layer comprises a metal layer, a brass layer abutting the metal layer, and a polymer layer abutting the brass layer. 1. A package , comprising:a die; and a metal layer;', 'a brass layer abutting the metal layer; and', 'a polymer layer abutting the brass layer., 'a redistribution layer coupled to the die, the redistribution layer comprising2. The package of claim 1 , wherein the package is a wafer chip scale package (WCSP).3. The package of claim 1 , wherein the polymer layer comprises a polyimide material.4. The package of claim 1 , wherein the brass layer has a thickness ranging from 0.3 microns to 4.0 microns.5. The package of claim 1 , further comprising an under bump metallurgy (UBM) abutting the brass layer and a solder bump abutting the UBM.6. The package of claim 1 , further comprising an under bump metallurgy (UBM) abutting the metal layer and a solder bump abutting the UBM.7. The package of claim 1 , further comprising a solder bump abutting the brass layer.8. The package of claim 1 , further comprising a solder bump abutting the metal layer and the polymer layer.9. The package of claim 1 , wherein the metal layer is a copper layer.10. The package of claim 1 , further comprising multiple metal plugs communicably coupled to the die and to the polymer layer.11. A package claim 1 , comprising:a die having a bond pad; and a polymer layer abutting the die; and', 'a metal layer at least partially positioned within the polymer layer, the metal layer abutting a brass layer., 'a redistribution layer coupled to the die, the redistribution layer comprising12. The package of claim 11 , wherein the package comprises a wafer chip scale package (WCSP).13. The package of claim 11 , further comprising an under bump metallurgy (UBM) having a first surface abutting a solder bump and a second surface abutting the brass layer.14. The package of claim 11 , further ...

Conductive External Connector Structure and Method of Forming

External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

Solder bumps formed on wafers using preformed solder balls with different compositions and sizes

Solder-bumped semiconductor substrates (e.g., semiconductor wafers) and methods for forming solder bumped semiconductor substrates are provided, in which solder bumps are formed on a semiconductor substrate using preformed solder balls having different compositions and/or sizes. Two or more solder balls masks are successively utilized to place different types of preformed solder balls (differing in composition and/or size) into corresponding cavities of a solder ball fixture, and thereby form an array of different types of preformed solder balls arranged in the solder ball fixture. The array of preformed solder balls in the solder ball fixture are then transferred to corresponding contact pads of a semiconductor substrate (e.g., semiconductor wafer) using a single solder reflow process. This process allows different types of preformed solder bumps to be bonded to a semiconductor substrate at the same time using a single solder reflow process.

SEMICONDUCTOR PACKAGE

A semiconductor package includes an interposer, a semiconductor die, an underfill layer and an encapsulant. The semiconductor die is disposed over and electrically connected with the interposer, wherein the semiconductor die has a front surface, a back surface, a first side surface and a second side surface, the back surface is opposite to the front surface, the first side surface and the second side surface are connected with the front surface and the back surface, and the semiconductor die comprises a chamfered corner connected with the back surface, the first side surface and the second side surface, the chamfered corner comprises at least one side surface. The underfill layer is disposed between the front surface of the semiconductor die and the interposer. The encapsulant laterally encapsulates the semiconductor die and the underfill layer, wherein the encapsulant is in contact with the chamfered corner of the semiconductor die. 1. A semiconductor package , comprising:an interposer;a semiconductor die disposed over and electrically connected with the interposer, wherein the semiconductor die has a front surface, a back surface, a first side surface and a second side surface, the back surface is opposite to the front surface, the front surface faces toward the interposer, the first side surface and the second side surface are connected with the front surface and the back surface, and the semiconductor die comprises a chamfered corner connected with the back surface, the first side surface and the second side surface, the chamfered corner comprises at least one side surface;an underfill layer disposed between the front surface of the semiconductor die and the interposer; andan encapsulant laterally encapsulating the semiconductor die and the underfill layer, wherein the encapsulant is in contact with the chamfered corner of the semiconductor die.2. The semiconductor package of claim 1 , wherein a first offset of the chamfered corner along a first direction ...

Method for manufacturing electronic component

A manufacturing method comprises preparing a bonding substrate having bumps thereon; preparing a mounted member having external conductive members; applying a fixing material to the surface of the bonding substrate and/or to a surface of the mounted member; and fixing the bonding substrate and the mounted member with the fixing material such that the bumps contact the external conductive members. The fixing material is prepared to contain a first compound and a second compound, each having respective viscosities which change depending on their respective temperature profiles; and applying the fixing material to the bonding substrate and/or the mounted member at a temperature lower than a first temperature, and the fixing comprises pressing the bonding substrate against the mounted member when the fixing material has a temperature lower than the first temperature; and heating the fixing material to a temperature higher than the second temperature and curing the fixed material.

High density package interconnects

Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

Integrated circuits including copper pillar structures and methods for fabricating the same

Integrated circuits including copper pillar structures and methods for fabricating the same are disclosed. In one exemplary embodiment, an integrated circuit includes a last metal layer and a passivation layer disposed over the last metal layer, both the last metal and passivation layers being disposed over an integrated circuit active device on a semiconductor substrate. The integrated circuit further includes a copper pillar structure disposed partially within a first portion of the passivation layer and immediately over the last metal layer. The first portion of the passivation layer is defined by first and second sidewalls of the passivation layer and an upper surface of the last metal layer. The copper pillar structure includes a liner formed along the first and second sidewalls and over the upper surface of the last metal and a copper material within the liner. The copper pillar structure, including both the liner and the copper material within the liner, further extends to a height above an upper surface of the passivation layer.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A method of manufacturing a semiconductor device includes providing a carrier, disposing a first pad on the carrier, forming a post on the first pad, and disposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post. The first entire contact interface and the second entire contact interface are flat surfaces. 1. A method of manufacturing a semiconductor device , comprising:providing a first carrier;disposing a first pad on the first carrier;forming a post on the first pad; anddisposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post, wherein the first entire contact interface and the second entire contact\ interface are flat surfaces.2. The method of manufacturing the semiconductor device of claim 1 , wherein the disposing of the joint is performed by pasting a solder over the post and the first pad through a stencil.3. The method of manufacturing the semiconductor device of claim 1 , further comprising providing a second carrier and disposing a second pad on the second carrier.4. The method of manufacturing the semiconductor device of claim 3 , wherein a height of the post is greater than or equal to ⅓ of a distance between the first pad and the second pad.5. The method of manufacturing the semiconductor device of claim 3 , further comprising disposing the joint between the first pad and the second pad to bond the first pad with the second pad and to form a third entire contact interface between the joint and the second pad claim 3 , wherein the third entire contact interface is a flat surface.6. The method of manufacturing the semiconductor device of claim 5 , further comprising disposing a pre-soldering bump on the second pad prior to disposing the joint between the first ...

Power Module Having Stacked Flip-Chip and Method for Fabricating the Power Module

Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method. The method includes forming bumps on power and control device chips on a wafer level; separately sawing the power and control device chips into individual chips; adhering the power device chip onto a thermal substrate and the control device chip onto an interconnecting substrate; combining a lead frame, the thermal substrate, and the interconnecting substrate with one another in a multi-jig; and sealing the power and control device chips, and the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.

HIGH DENSITY PACKAGE INTERCONNECTS

Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed. 126-. (canceled)27. A method for forming an interconnect , comprising:providing a first metal bump electrically coupled to an I/O signal region on a die, the first metal bump including a solder resistant coating that covers a first portion of the first metal bump and leaves a second portion of the first metal bump uncovered;providing a substrate having a first pad, the first pad having a pad width;forming a solder connection between the first metal bump and the first pad, wherein the solder connection includes an interface between the solder connection and the second portion of the first metal bump, the interface having a width; andwherein the solder connection is controlled so that the width of the interface between the solder connection and the second portion of the first metal bump is greater than the pad width of the first pad.28. The method of claim 27 , further comprising:providing a second metal bump electrically coupled to a power region on the die, the second metal bump including a solder resistant coating that covers a first portion of the second metal bump and leaves a second portion of the second metal bump uncovered;providing a second pad on the substrate, the second pad having a pad width;forming a second solder connection between the second metal bump and the second pad, wherein the second solder connection includes an interface between the second solder connection and the second portion of the second metal bump, the interface having a width; andwherein the second solder connection is ...

PACKAGING METHOD AND PACKAGE STRUCTURE OF FAN-OUT CHIP

A packaging method and a package structure of a fan-out chip are disclosed. The package structure comprises a first chip with bumps and a second chip without bumps, a first dielectric layer formed on a surface of the second chip and through-holes fabricated in the first dielectric layer; a plastic package material; a second dielectric layer; a metal redistribution layer for interconnecting within and between the first chip and the second chip; under bump metallization layers and micro-bumps. By fabricating the dielectric layers with the through-holes on the surfaces of the first chip and the second chip, exposing the bumps of the first chip and metal pads of the second chip and subsequently fabricating the metal redistribution layer, the interconnections within and between the first chip and the second chip are achieved and thereby the integrated package of the first chip and the second chip is achieved. 1. A packaging method of a fan-out chip , comprising:step 1): providing a first chip with bumps and a second chip without bumps, forming a first dielectric layer on a surface of the second chip, and fabricating through-holes in the first dielectric layer;step 2): providing a carrier with a bonding layer formed on a surface, and bonding the first chip and the second chip to the bonding layer side by side;step 3): packing the first chip and the second chip, wherein the bumps of the first chip and the through-holes of the first dielectric layer on the surface of the second chip are exposed after the packing.step 4): depositing a second dielectric layer covering the first chip and the second chip, patterning a plurality of windows each aligned to one bump of the first chip and one through-hole of the second chip;step 5): fabricating a metal redistribution layer to fill the plurality of windows, wherein the metal redistribution layer provides electrical connection within the first chip and the second chip, wherein the metal redistribution layer interconnects between the ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a conductive bump for disposing over a substrate and an elongated ferromagnetic member surrounded by the conductive bump, including a first end and a second end, and extending from the first end to the second end, the elongated ferromagnetic member is disposed substantially orthogonal to the substrate to dispose the conductive bump at a predetermined orientation and at a predetermined position of the substrate. Further, a method of manufacturing a semiconductor structure includes providing a substrate, forming a conductive trace within the substrate, applying an electric current passing through the conductive trace to generate an electromagnetic field and disposing a conductive bump including an elongated ferromagnetic member in a predetermined orientation and at a predetermined position above the substrate in response to the electromagnetic field generated by the conductive trace. 1. A semiconductor structure , comprising:a conductive bump for disposing over a substrate; andan elongated ferromagnetic member surrounded by the conductive bump, including a first end and a second end, and extended from the first end to the second end,wherein the elongated ferromagnetic member is disposed substantially orthogonal to the substrate to dispose the conductive bump at a predetermined orientation and at a predetermined position over the substrate.2. The semiconductor structure of claim 1 , wherein the elongated ferromagnetic member has a ratio of a width to a length of about 1:2 to about 1:20.3. The semiconductor structure of claim 1 , wherein the predetermined orientation is a center of the conductive bump disposed on a central axis of the elongated ferromagnetic member.4. The semiconductor structure of claim 1 , wherein the first end is exposed from an outer surface of the conductive bump.5. The semiconductor structure of claim 1 , wherein the first end is covered by an outer surface of the conductive bump.6. The semiconductor structure of ...

STRUCTURES AND METHODS FOR LOW TEMPERATURE BONDING USING NANOPARTICLES

A method of making an assembly can include forming a first conductive element at a first surface of a substrate of a first component, forming conductive nanoparticles at a surface of the conductive element by exposure to an electroless plating bath, juxtaposing the surface of the first conductive element with a corresponding surface of a second conductive element at a major surface of a substrate of a second component, and elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles cause metallurgical joints to form between the juxtaposed first and second conductive elements. The conductive nanoparticles can be disposed between the surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. 1. An assembly , comprising:a first component including a substrate having a first surface and a plurality of substantially rigid first posts at the first surface, the first posts extending away from the first surface in a first direction, each first post having a top surface generally facing in the first direction, the top surface of each of the first posts projecting a height above the first surface such that the top surface is remote from the first surface, each first post having edge surfaces extending at substantial angles away from the top surface thereof; anda second component including a substrate having a major surface and a plurality of second conductive elements at the major surface, each second conductive element having a top surface generally facing in a second direction,the first posts being joined with the second conductive elements, such that the top surfaces of the first posts at least partially confront the top surfaces of the second conductive elements, the top surfaces of at least some of the first posts being non-coplanar with respect to one another,each first post being ...

Mechanisms for Forming Post-Passivation Interconnect Structure

Mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer. 1. A semiconductor device , comprising:an integrated circuit;an insulating layer overlying the integrated circuit;a post-passivation interconnect layer over the insulating layer; and a bump comprising a first material, and', 'a diffusion barrier region enclosing the bump and comprising the first material doped with a dopant., 'a connector electrically connected to the post-passivation layer, the connector including2. The semiconductor device as claimed in claim 1 , wherein the dopant in the diffusion barrier region includes nickel.3. The semiconductor device as claimed in claim 1 , wherein the first material includes a solder material or copper.4. The semiconductor device as claimed in claim 1 , wherein a portion of the diffusion barrier region is between a bottom of the bump and the post-passivation interconnect layer.5. The semiconductor device as claimed in claim 4 , further comprising a diffusion barrier layer directly below a diffusion barrier region of the bump and directly above the post-passivation interconnect layer.6. The semiconductor device as claimed in claim 1 , wherein the bump comprises a solder bump.7. The semiconductor device as claimed ...

CIRCUIT SYSTEM HAVING COMPACT DECOUPLING STRUCTURE

A circuit system having compact decoupling structure, including: a mother board; at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, the substrate having a first surface and a second surface, the first metal contacts being formed on the first surface and soldered onto the mother board, the second metal contacts being formed on the logic-circuit die and soldered onto the second surface to form flip-chip pillars, and the flip-chip pillars determining a height of a gap between the die and the substrate; and at least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit; wherein each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die and at least one stack-type integrated-passive-device die. 1. A circuit system having compact decoupling structure , including:a mother board;at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, wherein the substrate has a first surface and a second surface opposing the first surface, the first metal contacts are formed on the first surface and soldered onto the mother board, the second metal contacts are formed on the logic-circuit die and soldered onto the second surface of the substrate to form flip-chip pillars, and the flip-chip pillars determine a height of a gap between the logic-circuit die and the substrate; andat least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit;wherein, each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die, at least one stack-type integrated-passive-device die, and a plurality of third metal contacts, the third metal contacts being formed on the mother die and soldered onto the logic-circuit die, and ...

SEMICONDUCTOR DEVICE

A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer. 1. A semiconductor device comprising:an insulating layer;a barrier electrode layer formed over a part of a region of a surface of the insulating layer;a bonding pad formed on a principal surface of the barrier electrode layer,wherein the bonding pad has three layers which include a Cu electrode layer that includes a metal composed mainly of copper, a nickel layer, and a surface metal layer, those layers are formed from bottom to top; andwherein a surface of the surface metal layer is fully exposed from the insulating layer for connecting a bonding wire on the surface, a thickness of the surface metal layer is thinner than a thickness of the nickel layer, and a thickness of the nickel layer is thinner than a thickness of the Cu electrode layer.2. The semiconductor device according to claim 1 , wherein a width of the surface metal layer is wider than a width of the Cu electrode layer in a sectional view.3. The semiconductor device according to claim 1 , wherein a curved portion is formed around a bottom of the Cu electrode layer to make an upper portion of the Cu electrode layer wider.4. The semiconductor device according to claim 3 , wherein an insulating material is intruding to the curved portion so that part of the Cu electrode layer is on the insulating material.5. The semiconductor device according to claim 1 , wherein a thickness of the insulating layer is thicker than a thickness of the barrier electrode layer.6. The semiconductor device according to claim 1 , wherein the Cu electrode layer and the insulating ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

According to one embodiment, a semiconductor device includes a first conductive portion, a second conductive portion, a first layer, and a second layer. The first conductive portion includes a first end portion and a first extending portion. The first extending portion extends in a first direction. The length of the first extending portion in a second direction is shorter than a length of at least a part of the first end portion in the second direction. The first layer includes multiple semiconductor chips, multiple passive chip components, and a resin. The first extending portion includes a first portion and a second portion. The first layer is provided around the first portion. The first layer expands along a first plane. The first plane intersects the first direction. The second layer includes a first multilayer wiring. The second layer expands along a second plane intersecting the first direction. 1. A semiconductor device comprising: a first end portion which contains a first conductive material, and', 'a first extending portion in the form of a cylinder, the first extending portion extending in a first direction, containing the first conductive material, and being connected to the first end portion, a length of the first extending portion in a second direction being shorter than a length of at least a part of the first end portion in the second direction, the second direction intersecting the first direction, the first extending portion including a first portion and a second portion, and the second portion arranged with the first portion in the first direction;, 'a first conductive portion including'}a second conductive portion including a second end portion, the second end portion being separated from the first end portion in the first direction, the second end portion being electrically connected to the first extending portion, the first extending portion being provided between the first end portion and the second end portion; the first layer being provided ...

Chip package structure and method for forming the same

A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a bump and a dummy bump over a second surface of the first substrate. The dummy bump is close to a first corner of the first substrate, and the dummy bump is wider than the bump. The method includes bonding the first substrate to a second substrate through the bump. The dummy bump is electrically insulated from the chip and the second substrate. The method includes forming a protective layer between the first substrate and the second substrate. The protective layer surrounds the dummy bump and the bump, and the protective layer is between the dummy bump and the second substrate.

BUMP PLANARITY CONTROL

A method for manufacturing an integrated circuit package includes depositing a first layer of metal at a location of a first metal post that is for connecting an IC die to an external circuit. The method also includes depositing a second layer of metal at the location of the first metal post, and a first layer of metal at a location of a second metal post that is for connecting the IC die to an external circuit. 1. A method for manufacturing an integrated circuit (IC) package , comprising:depositing a first layer of metal at a location of a first metal post that is capable of electrically connecting to an IC die; andconcurrently depositing a second layer of metal on the first layer of metal, and the first layer of metal at a location of a second metal post that is capable of electrically connecting to the IC die.2. The method of claim 1 , wherein claim 1 , after depositing the second layer of metal claim 1 , a height of the first metal post is substantially the same as a height of the second metal post claim 1 , the height of the first metal post and the height of the second metal post including all the layers of metal deposited on each of the first metal post and the second metal post.3. The method of claim 1 , further comprising claim 1 , prior to depositing the first layer of metal claim 1 , applying a layer of photoresist material to the location of the first metal post and the location of the second metal post.4. The method of claim 3 , further comprising:removing the photoresist from the location of the first metal post; andretaining the photoresist at the location of the second metal post.5. The method of claim 1 , further comprising claim 1 , after depositing the first layer of metal claim 1 , applying a layer of photoresist material to the location of the first metal post and the location of the second metal post.6. The method of claim 5 , further comprising:removing the photoresist from the location of the first metal post; andremoving the photoresist from ...

INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS

An interconnect structure for a semiconductor device is provided herein. The interconnect structure generally includes a conductive pillar electrically coupled to a conductive contact positioned on a semiconductor die and a trace receiver on a distal end of the pillar. The trace receiver has a body electrically coupled to the distal end, and may include a first leg projecting from a first side of the body away from the distal end and a second leg projecting from a second side of the body away from the distal end, such that the body, the first leg, and the second leg together form a cavity. During assembly of the semiconductor device, the cavity is configured to at least partially surround a portion of a semiconductor trace positioned in an insulated substrate. To form the electrical connection, a solder material may be disposed between the trace receiver and the trace. 1. An interconnect structure for a semiconductor device , the interconnect structure comprising:a conductive pillar electrically coupled to a conductive contact positioned on a semiconductor die, the conductive pillar having a distal end opposite the conductive contact; and a body electrically coupled to the distal end of the pillar;', 'a first leg projecting from a first side of the body away from the distal end; and', 'a second leg projecting from a second side of the body away from the distal end, wherein the body, the first leg, and the second leg together form a cavity configured to receive a portion of a semiconductor trace therein., 'a trace receiver having2. The interconnect structure of claim 1 , wherein the first leg and the second leg extend at least partially along peripheral surfaces of the semiconductor trace when the semiconductor device is in an assembled position.3. The interconnect structure of claim 1 , further comprising a solder material disposed in at least a portion of the cavity.4. The interconnect structure of claim 3 , wherein the solder material contacts a distal surface of ...

METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURE FOR JOINING WAFERS AND RESULTING STRUCTURE

The disclosure is directed to an integrated circuit structure for joining wafers and methods of forming same. The IC structure may include: a metallic pillar over a substrate, the metallic pillar including an upper surface; a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and a solder material over the upper surface of the metallic pillar, the solder material being within and constrained by the wetting inhibitor layer. The sidewall of the metallic pillar may be free of the solder material. The method may include: forming a metallic pillar over a substrate, the metallic pillar having an upper surface; forming a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and forming a solder material over the upper surface of the metallic pillar within and constrained by the wetting inhibitor layer. 8. A method of forming an integrated circuit structure for joining wafers , the method comprising:forming a metallic pillar over a substrate, the metallic pillar having an upper surface;forming a wetting inhibitor layer over the upper surface of the metallic pillar;patterning a photoresist over the wetting inhibitor layer such that a first portion of the wetting inhibitor layer about the periphery of the upper surface of the metallic pillar is covered and a second portion of the wetting inhibitor layer over a central portion of the metallic pillar is exposed;removing the exposed second portion of the wetting inhibitor layer to expose the central portion of the metallic pillar thereunder; andremoving the photoresist to expose the first portion of the wetting inhibitor layer about the periphery of the upper surface of the metallic pillar; andforming a solder material over the upper surface of the metallic pillar within and constrained by the first portion of the wetting inhibitor layer about the periphery of the upper surface of the metallic pillar.9. (canceled)101. The method of claim , wherein the forming ...

Semiconductor Device, Method for Fabricating a Semiconductor Device and Method for Reinforcing a Die in a Semiconductor Device

A semiconductor device includes a semiconductor die having a first main face, a second main face and side faces connecting the first main face and the second main face. The semiconductor device also includes a conductive column arranged on the first main face of the semiconductor die and electrically coupled to the semiconductor die, and an insulating body arranged on the first main face of the semiconductor die. The insulating body has an upper main face and side faces. The upper main surface of the insulating body is coplanar with a top face of the conductive pillar. The semiconductor device further includes a metal layer arranged on the top face of the conductive pillar. The side faces of the semiconductor die and the side faces of the insulating body are coplanar.

Optimised fabrication methods for a structure to be assembled by hybridisation and a device comprising such a structure

A method of fabrication of a semiconducting structure intended to be assembled to a second support by hybridisation. The semiconducting structure comprising an active layer comprising a nitrided semiconductor. The method comprises a step for the formation of at least one first and one second insert and during this step, a nickel layer is formed in contact with the support surface, and a localised physico-chemical etching step of the active layer, a part of the active layer comprising the active region being protected by the nickel layer. 1. Method of fabrication of a semiconducting structure intended to be connected by hybridisation to a second support , the method for fabricating a semiconducting structure including the following steps:supply a first support that comprises a substrate and at least one active layer, said active layer (comprising at least one nitrided semiconducting material, at least one active region of said semiconducting structure and at least one first connection zone and at least one second connection zone of said active region being arranged in said active layer, the first connection zone and the second connection zone of said active region flush with a surface of the first support,formation of at least one first insert body and one second insert body in electrical contact with the first and second connection zones respectively, said formation step comprising formation of a nickel layer covering a portion of the surface of the first support, said nickel layer being arranged on the support surface at the active region, at least partially covering the first and second connection zones,localised physico-chemical etching of the active layer, the localisation of the etching being provided by protecting part of the active layer comprising the active region by the nickel layer,physico-chemical etching of the nickel layer, the etching being stopped after the release of at least part of the surface of the first support of said nickel layer, the part of ...

PACKAGED SEMICONDUCTOR DEVICE WITH ELECTROPLATED PILLARS

In a described example, a device includes an overcoat layer covering an interconnect; an opening in the overcoat layer exposing a portion of a surface of the interconnect; a stud on the exposed portion of the surface of the interconnect in the opening; a surface of the stud approximately coplanar with a surface of the overcoat layer; and a conductive pillar covering the stud and covering a portion of the overcoat layer surrounding the stud, the conductive pillar having a planar and un-dished surface facing away from the stud and the overcoat layer. 1. A device , comprising:an overcoat layer covering an interconnect;an opening in the overcoat layer exposing a portion of a surface of the interconnect;a stud on the exposed portion of the surface of the interconnect in the opening;a surface of the stud approximately coplanar with a surface of the overcoat layer; anda conductive pillar covering the stud and covering a portion of the overcoat layer surrounding the stud, the conductive pillar having a planar and un-dished surface facing away from the stud and the overcoat layer.2. The device of claim 1 , wherein the device is a semiconductor device.3. The device of claim 1 , wherein the device is a circuit board.4. The device of claim 1 , wherein the interconnect is one selected from a group consisting essentially of: aluminum claim 1 , tungsten claim 1 , titanium/tungsten claim 1 , copper and alloys thereof.5. The device of claim 1 , wherein the conductive pillar comprises copper.6. The device of claim 5 , wherein the conductive pillar comprises electroplated copper.7. The device of claim 1 , wherein the conductive pillar comprises an electroplated material that is one selected from a group consisting essentially of: silver claim 1 , gold claim 1 , nickel claim 1 , palladium claim 1 , and copper.8. The device of claim 1 , wherein the stud comprises copper.9. The device of claim 8 , wherein the stud comprises electroplated copper.10. The device of claim 8 , wherein the ...

Method of Manufacturing Semiconductor Device and Semiconductor Device Manufacturing Apparatus

A method of manufacturing a semiconductor device according to the present invention comprises: a bump forming step of forming a bump electrode 100 on a semiconductor chip 1, the bump electrode 100 protruding in a substantially conical shape; a pad forming step of forming a pad electrode 200 on a substrate 10, the pad electrode 200 having a recess 210 with inner lateral surfaces thereof defining a substantially pyramidal shape or a prism shape; a pressing step of pressing the bump electrode 100 and the pad electrode 200 in a direction which brings them closer to each other, with the bump electrode 100 being inserted in the recess 210 so that the central axis of the bump electrode 100 and the central axis of the recess 210 coincide with each other; and an ultrasonic joining step of joining the bump electrode 100 and the pad electrode 200 by vibrating at least one of the bump electrode 100 and the pad electrode 200 using ultrasonic waves.

Semiconductor devices

Semiconductor devices are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump. The spacer surrounds the bump and disposed between the etching stop layer and the bump.

Semiconductor device

A semiconductor device includes: a first switching element that is provided on a high side; a first diode element that is connected in parallel to the first switching element; a second switching element that is provide on a low side and connected in series to the first switching element; and a second diode element that is connected in parallel to the second switching element, wherein the first switching element and one of the first diode element and the second diode element are stacked adjacently to each other in a vertical direction of respective electrode surfaces thereof via a conductive electrode, the second switching element and the other of the first diode element and the second diode element that is different from the diode element adjacent to the first switching element are stacked adjacently to each other in a vertical direction of respective electrode surfaces thereof via a conductive electrode, and the first switching element and the second switching element are not adjacent in a vertical direction of respective electrode surfaces thereof.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a substrate; a conductive pad disposed over the substrate; a passivation disposed over the substrate and covering a portion of the conductive pad; a bump pad disposed over the conductive pad and the passivation; a conductive bump including a conductive pillar disposed over the bump pad and a soldering member disposed over the conductive pillar; and a dielectric member disposed over the passivation and surrounding the conductive pillar. 1. A semiconductor structure , comprising:a substrate;a conductive pad disposed over the substrate;a passivation disposed over the substrate and covering a portion of the conductive pad;a bump pad disposed over the conductive pad and the passivation;a conductive bump including a conductive pillar disposed over the bump pad and a soldering member disposed over the conductive pillar; anda dielectric member disposed over the passivation and surrounding the conductive pillar.2. The semiconductor structure of claim 1 , wherein the soldering member is exposed from the dielectric member.3. The semiconductor structure of claim 1 , wherein the dielectric member is in contact with the bump pad and the conductive pillar.4. The semiconductor structure of claim 1 , wherein a first interface is disposed between the dielectric member and the passivation.5. The semiconductor structure of claim 4 , wherein material of the dielectric member is different from material of the passivation.6. The semiconductor structure of claim 1 , wherein a second interface between the soldering member and the conductive pillar is substantially coplanar with an exposed surface of the dielectric member.7. The semiconductor structure of claim 6 , wherein a third interface between the conductive pillar and the dielectric member is substantially orthogonal to the second interface between the soldering member and the conductive pillar.8. The semiconductor structure of claim 1 , wherein the conductive pillar is enclosed by the bump pad claim ...

SEMICONDUCTOR DEVICE

A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer. 1. A semiconductor device comprising:an insulating layer;a TiN layer formed over a part of a region of a surface of the insulating layer;a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the TiN layer; anda nickel layer formed on the Cu electrode layer,wherein a width of the nickel layer is wider than a width of the Cu electrode layer in a sectional view.2. The semiconductor device according to claim 1 , wherein a surface metal layer is formed on the nickel layer.3. The semiconductor device according to claim 2 , wherein a thickness of the surface metal layer is thinner than a thickness of the nickel layer.4. The semiconductor device according to claim 3 , wherein a width of the surface metal layer is wider than a width of the Cu electrode layer in a sectional view.5. The semiconductor device according to claim 4 , wherein a curved portion is formed around a bottom of the Cu electrode layer to make an upper portion of the Cu electrode layer wider.6. The semiconductor device according to claim 5 , wherein an insulating material is intruding to the curved portion so that part of the Cu electrode layer is on the insulating material.7. The semiconductor device according to claim 6 , wherein a thickness of the insulating layer is thicker than a thickness of the TiN layer.8. The semiconductor device according to claim 7 , wherein the Cu electrode layer and the insulating layer are connected by the TiN layer disposed between the Cu electrode layer and the ...

CHIPLETS WITH CONNECTION POSTS

A component includes a plurality of electrical connections on a process side opposed to a back side of the component. Each electrical connection includes an electrically conductive multi-layer connection post protruding from the process side. A printed structure includes a destination substrate and one or more components. The destination substrate has two or more electrical contacts and each connection post is in contact with, extends into, or extends through an electrical contact of the destination substrate to electrically connect the electrical contacts to the connection posts. The connection posts or electrical contacts are deformed. Two or more connection posts can be electrically connected to a common electrical contact. 1. A printed structure , comprising:a component comprising a chiplet and a protruding connection post; anda destination substrate comprising a recessed contact,wherein the connection post is inserted into the recessed contact.2. The printed structure of claim 1 , wherein the recessed contact has a perimeter portion surrounding a recessed central portion.3. The printed structure of claim 1 , wherein the component comprises a component substrate that comprises a substrate material and wherein the connection post comprises the substrate material.4. (canceled)5. The printed structure of claim 3 , wherein at least a portion of the connection post and at least a portion of the component substrate are a unitary structure.6. The printed structure of claim 5 , wherein the connection post has a peak area greater than a base area.7. The printed structure of claim 3 , wherein the substrate material is a semiconductor or an oxide.8. The printed structure of claim 6 , wherein the substrate material is silicon claim 6 , a compound semiconductor claim 6 , silicon oxide claim 6 , silicon dioxide claim 6 , silicon nitride claim 6 , a resin claim 6 , a polymer claim 6 , or a cured resin.9. The printed structure of claim 1 , wherein the connection post has a base ...

FLIP CHIP INTERCONNECTION WITH REDUCED CURRENT DENSITY

A method and system for electrically connect a semiconductor device with a flip-chip form factor to a printed circuit board. An exemplary embodiment of the method comprises: aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, and, applying a supply current only directly to a buried layer of the first copper and not directly to the layer which is nearest the device, such that no current is sourced to the device through the layer nearest the device. 1. A method of connecting a device to external circuitry comprising:aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, wherein the first copper contact comprises a plurality of electrically connected layers; and,applying a source current only directly to a layer of the first copper contact other than the layer nearest the solder contacts, such that no current is sourced to the device through the layer nearest the device.2. The method of claim 1 , wherein the device has a flip chip form factor.3. The method of claim 2 , wherein the external circuitry is a part of a printed circuit board comprising the plurality of electrically connected layers.4. The method of claim 2 , wherein the device is a semiconductor device.5. The method of claim 1 , wherein the first copper contact and the second copper contact are each comprised of multiple copper layers electrically connected by metal filled vias.6. The method of claim 1 , wherein the first copper contact and second copper contact each have more than two layers.7. A system for electrically connecting a device to external circuitry comprising:at least one solder contact electrically connected to the device;at least one copper contact electrically connected to the external circuitry and the solder contact of the device, the copper contact being formed of multiple layers, wherein a first layer of the multiple layers is closest to the device and ...

PACKAGE STRUCTURE AND METHOD FOR CONNECTING COMPONENTS

A package structure and a method for connecting components are provided, in which the package includes a first substrate including a first wiring and at least one first contact connecting to the first wiring; a second substrate including a second wiring and at least one second contact connecting to the second wiring, the at least one first contact and the at least one second contact partially physically contacting with each other or partially chemically interface reactive contacting with each other; and at least one third contact surrounding the at least one first contact and the at least one second contact. The first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact. 1. A package structure , comprising:a first substrate, comprising a first wiring and at least one first contact, wherein the at least one first contact is electrically connected to the first wiring;a second substrate, comprising a second wiring and at least one second contact, wherein the at least one second contact is electrically connected to the second wiring, and the at least one first contact and the at least one second contact partially physically contact with each other or partially chemically interface reactive contact with each other; andat least one third contact, surrounding the at least one first contact and the at least one second contact,wherein the first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact.2. The package structure according to claim 1 , wherein the at least one third contact is disposed between the at least one first contact and the at least one second contact.3. The package structure according to claim 1 , further comprising an intermetallic compound (IMC) or an alloy solid solution formed after the at least one first contact contacts the at least one ...

MICRO-LED MODULE AND METHOD FOR FABRICATING THE SAME

A method for fabricating a micro-LED module is disclosed. The method includes: preparing a micro-LED including a plurality of electrode pads and a plurality of LED cells; preparing a submount substrate including a plurality of electrodes corresponding to the plurality of electrode pads; and flip-bonding the micro-LED to the submount substrate through a plurality of solders located between the plurality of electrode pads and the plurality of electrodes. The flip-bonding includes heating the plurality of solders by a laser. 1. A method for flip-bonding a micro-LED to a submount substrate , comprising:forming a plurality of LED cells on an LED substrate to prepare the micro-LED;preparing the submount substrate having a coefficient of thermal expansion different from that of the micro-LED; andflip-bonding the micro-LED to the submount substrate through solders located therebetween,wherein the submount substrate and the micro-LED are controlled to different temperatures corresponding to different heating-cooling curves during the flip-bonding such that a difference in strain caused by the different coefficients of thermal expansion of the LED substrate and the submount substrate is suppressed.2. The method according to claim 1 , wherein the submount substrate and the micro-LED are controlled to different temperatures in a heating zone claim 1 , a holding zone claim 1 , and a cooling zone during the flip-bonding.3. The method according to claim 2 , wherein claim 2 , in the heating zone claim 2 , the LED substrate is heated from room temperature to a first holding temperature along a first heating slope and the submount substrate is heated from room temperature to a second holding temperature higher than the first holding temperature along a second heating slope steeper than the first heating slope.4. The method according to claim 2 , wherein claim 2 , in the holding zone claim 2 , the LED substrate is maintained at the first holding temperature for an indicated time and ...

SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS

Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer. 1. A semiconductor apparatus , comprising:a semiconductor substrate having at least one metal pad;a first passivation layer formed on the semiconductor substrate and covering a portion of the at least one metal pad, the first passivation layer having at least one first passivation layer opening to expose a first portion of the at least one metal pad;a second passivation layer formed on the first passivation layer, the second passivation layer having at least one second passivation layer opening to expose a second portion of the at least one metal pad;an under bump metal layer at least formed on the second portion of the at least one metal pad exposed by the second passivation layer opening;a stress buffer layer formed on the under bump metal layer; anda copper pillar disposed on the stress buffer layer.2. The semiconductor apparatus according to claim 1 , wherein the material of the stress buffer layer comprises tin claim 1 , tin-silver claim 1 , tin alloy claim 1 , indium or indium alloy claim 1 , and the material of the under ...

SOLDER-COATED BALL AND METHOD FOR MANUFACTURING SAME

A solder-coated ball (A) includes a spherical core containing Ni and P; and a solder layer () formed to coat the core (). A solder-coated ball (B) further includes a Cu plating layer () formed between the core () and the solder layer (). A solder-coated ball (C) further includes an Ni plating layer () formed between the Cu plating layer () and the solder layer (). 1. A solder-coated ball , comprising:a spherical core containing Ni and P; anda solder layer formed to coat the core.2. The solder-coated ball according to claim 1 , further comprising a Cu plating layer formed between the core and the solder layer.3. The solder-coated ball according to claim 2 , further comprising an Ni plating layer formed between the Cu plating layer and the solder layer.4. The solder-coated ball according to claim 2 , wherein the Cu plating layer has a thickness of 0.01 μm or greater and 50 μm or less.5. The solder-coated ball according to claim 1 , wherein the solder layer has a thickness of 0.01 μm or greater and 50 μm or less.6. The solder-coated ball according to claim 1 , wherein the core has an average particle diameter of 150 μm or less and a sphericity of 0.98 or greater.7. The solder-coated ball according to claim 1 , wherein the core contains P at 1% by mass or greater and 15% by mass or less claim 1 , Cu optionally incorporated at 18% by mass at most and Sn optionally incorporated at 5% by mass at most claim 1 , and the remaining part contains Ni and unavoidable impurities.8. A method for manufacturing solder-coated ball comprising a spherical core containing Ni and P claim 1 , and a solder layer formed to coat the core claim 1 , the method comprising a step of preparing the core claim 1 ,wherein the step includes a step of manufacturing, by an electroless reduction method, a powder of spherical particles containing Ni and P, the powder fulfilling [(d90−d10)/d50]≦0.8, where particles exhibiting 90% by volume, 10% by volume and 50% by volume in an accumulated volume ...

HIGH DENSITY PACKAGE INTERCONNECTS

Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed. 17-. (canceled)8. An apparatus comprising:a semiconductor die structure including I/O signal lines and power lines, the power lines including at least one of core power lines and I/O power lines;the die structure including a plurality of metal bumps, including a first group of metal bumps coupled to the I/O signal lines, and a second group of metal bumps coupled to the power lines; andwherein at least some of the metal bumps of the first group have a different pitch than at least some of the metal bumps of the second group.9. The apparatus of claim 8 , wherein at least some of metal bumps of the first group have at least one difference selected from the group consisting of a different shape and a different width claim 8 , than at least some of the metal bumps of the second group.10. The apparatus of claim 8 , wherein at least some of the metal bumps of the first group are rectangular in shape.11. The apparatus of claim 9 , wherein at least some of the metal bumps of the second group are circular in shape.12. The apparatus of claim 8 , wherein the first group of metal bumps includes a first sub-group of metal bumps and a second sub-group of metal bumps claim 8 , wherein the first sub-group has a smaller pitch than the second sub-group.13. The apparatus of claim 8 , further comprising a solder coupled to each of the first group of metal bumps claim 8 , wherein the solder defines an interface on the metal bump where the solder and metal bump are in contact claim 8 , and wherein the interface has a width that is ...

Bump structure manufacturing method

Provided is a method of manufacturing a bump structure, the method including a first step for preparing a wafer including a plurality of chips each including a die pad, an under bump metal (UBM) layer on the die pad, and a bump pattern on the UBM layer, a second step for attaching a backgrinding film to an upper surface of the wafer, a third step for grinding a rear surface of the wafer by a certain thickness, a fourth step for forming a flexible material layer on a second rear surface of the wafer after being ground, and then attaching dicing tape including a ring frame, to the flexible material layer, a fifth step for removing the backgrinding film and then performing a curing process to harden the flexible material layer, and a sixth step for performing a dicing process to cut the plurality of chips into individual chips.

Cu PILLAR CYLINDRICAL PREFORM FOR SEMICONDUCTOR CONNECTION

A material for Cu pillars is formed as cylindrical preforms in advance and connecting these cylindrical preforms to electrodes on a semiconductor chip to form Cu pillars. Due to this, it becomes possible to make the height/diameter ratio of the Cu pillars 2.0 or more. Since electroplating is not used, the time required for production of the Cu pillars is short and the productivity can be improved. Further, the height of the Cu pillars can be raised to 200 μm or more, so these are also preferable for moldunderfill. The components can be freely adjusted, so it is possible to easily design the alloy components to obtain highly reliable Cu pillars. 1. A cylindrical preform having Cu as a main component , satisfying one or more of (a) to (d) among (a) having one or more of Pd , Pt , Au , and Ni in a total of 5.0 mass % or less , (b) having Ti in 15 mass ppm or less , (c) having P in 150 mass ppm or less , and (d) having a total of a content of S and a content of Cl contained as impurities of 1 mass ppm or less , having a cylindrical shape with a diameter of 50 to 100 μm , having a height/diameter ratio of that cylinder of 2.0 or more , and used as a Cu pillar for semiconductor connection.2. A cylindrical preform having Cu as a main component , satisfying one or more of (a) to (d) among (a) having one or more of Pd , Pt , Au , and Ni in a total of 5.0 mass % or less , (b) having Ti in 15 mass ppm or less , (c) having P in 150 mass ppm or less , and (d) having a total of a content of S and a content of Cl contained as impurities of 1 mass ppm or less , having a cylindrical shape with a diameter of 100 to 400 μm , and used as a Cu pillar for semiconductor connection.3. The cylindrical preform according to claim 2 , wherein the cylinder has a height of 200 to 800 μm.4. The cylindrical preform according to claim 1 , further containing one or more of Pd claim 1 , Pt claim 1 , Au claim 1 , and Ni in a total of 5.0 mass % or less in range.5. The cylindrical preform according to ...

Cu Column, Cu Core Column, Solder Joint, and Through-Silicon Via

Provided are a Cu column, a Cu core column, a solder joint, and a through-silicon via, which have the low Vickers hardness and the small arithmetic mean roughness. For the Cu column 1 according to the present invention, its purity is equal to or higher than 99.9% and equal to or lower than 99.995%, its arithmetic mean roughness is equal to or less than 0.3 μm, and its Vickers hardness is equal to or higher than 20 HV and equal to or less than 60 HV. Since the Cu column 1 is not melted at a melting temperature in the soldering and a definite stand-off height (a space between the substrates) can be maintained, it is preferably applied to the three dimensional mounting or the pitch narrowing mounting. 1. A Cu column containing:purity which is equal to or higher than 99.9% and equal to or lower than 99.995%,arithmetic mean roughness which is equal to or less than 0.3 μm, andVickers hardness which is equal to or higher than 20 HV and equal to or less than 60 HV.2. The Cu column according to claim 1 , wherein an alpha dose is equal to or less than 0.0200 cph/cm.3. The Cu column according to claim 1 , wherein said Cu column is composed of a column which has a diameter of the top surface of 1-1000 m claim 1 , a diameter of the bottom surface of 1-1000 μm claim 1 , and a height of 1-3000 μm.4. The Cu column according to claim 1 , wherein the Cu column is coated with a flux layer.5. The Cu column according to claim 1 , wherein the Cu column is coated with an organic film containing an imidazole compound.6. A Cu core column claim 1 , containing:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the Cu column according to ; and'}a solder layer which coats the Cu column.7. A Cu core column containing:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the Cu column according to ; and'}a plating layer which includes at least one element selected from a group of Ni, Fe and Co, the plating layer coating the Cu column.8. The Cu core column according to claim 7 , further comprising:a ...

Package on package structure and method for forming the same

Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.

MICROELECTRONIC SUBSTRATE HAVING EMBEDDED TRACE LAYERS WITH INTEGRAL ATTACHMENT STRUCTURES

A microelectronic substrate may be formed to have an embedded trace which includes an integral attachment structure that extends beyond a first surface of a dielectric layer of the microelectronic substrate for the attachment of a microelectronic device. In one embodiment, the embedded trace may be fabricated by forming a dummy layer, forming a recess in the dummy layer, conformally depositing surface finish in the recess, forming an embedded trace layer on the dummy layer and abutting the surface finish, and removing the dummy layer. 1. A method of fabricating a microelectronic structure , comprising:forming a dummy layer;forming at least one recess in the dummy layer;conformally depositing a surface finish in the at least one recess;forming an embedded trace layer on the dummy layer and abutting the surface finish; andremoving the dummy layer.2. The method of claim 1 , wherein forming the recess in the dummy layer comprises:forming an etch mask on the dummy layer wherein the etch mask includes openings therethrough; andetching the dummy layer to form the recesses.3. The method of claim 2 , wherein conformally depositing the surface finish comprises conformally depositing the surface finish through the etch mask.4. The method of claim 1 , wherein forming the embedded trace layer comprises forming an embedded trace mask on the dummy metal layer claim 1 , wherein the embedded trace mask includes openings therethrough claim 1 , and depositing an embedded trace layer through the embedded trace mask openings.5. The method of claim 1 , further including forming a dielectric material layer on the embedded trace layer and the dummy layer.6. The method of claim 5 , further including forming at least one conductive via through the dielectric material layer to contact the at least one embedded trace and forming at least one conductive trace contacting the conductive via prior to removing the dummy layer.7. The method of claim 1 , wherein forming the embedded trace material ...

Solderless Interconnection Structure and Method of Forming Same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion. 1. A device comprising:a substrate trace extending along a first substrate, the substrate trace having a first shape in a plan view; anda metal ladder bump extending from an integrated circuit, the metal ladder bump having a second shape in the plan view, the second shape being different from the first shape,wherein the metal ladder bump and the substrate trace are physically and electrically coupled together through direct metal-to-metal bonds, an interface between the metal ladder bump and the substrate trace being free from solder.2. The device of claim 1 , wherein the substrate trace has a first length claim 1 , the metal ladder bump has a second length claim 1 , and the first length is greater than the second length claim 1 , the first length and the second length each being measured in a direction parallel to a longitudinal axis of the substrate trace.3. The device of claim 1 , wherein the second shape is a quadrilateral.4. The device of claim 1 , wherein the second shape is a circle.5. The device of claim 1 , wherein the metal ladder bump and the substrate trace are copper claim 1 , and wherein the interface between the metal ladder bump and the substrate trace is free from intermetallic compounds.6. The device of claim 1 , wherein the substrate trace has a first end proximate the first substrate and a second end distal the first substrate claim 1 , the first end having a greater width than the second end. ...

Bonded Structures for Package and Substrate

The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.