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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 911. Отображено 100.
12-01-2012 дата публикации

Method of forming cu pillar capped by barrier layer

Номер: US20120007231A1
Автор: Wei Sen CHANG
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper portion of the mask layer is removed after the formation of the Cu pillar so as to expose the upper sidewall surface of the Cu pillar. The nickel barrier layer is then deposited on the exposed sidewall surface of the Cu pillar followed by removing and the lower portion of the mask layer.

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Номер записи: 1
23-08-2012 дата публикации

Electroconductive bonding material, method for bonding conductor, and method for manufacturing semiconductor device

Номер: US20120211549A1
Автор: Kuniko Ishikawa, Masayuki Kitajima, Takashi Kubota, Takatoyo Yamakami
Принадлежит: Fujitsu Ltd

An electro-conductive bonding material includes: metal components of a high-melting-point metal particle that have a first melting point or higher; a middle-melting-point metal particle that has a second melting point which is first temperature or higher, and second temperature or lower, the second temperature is lower than the first melting point and higher than the first temperature; and a low-melting-point metal particle that has a third melting point or lower, the third melting point is lower than the first temperature.

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Номер записи: 2
30-08-2012 дата публикации

Bonded Semiconductor Structure With Pyramid-Shaped Alignment Openings and Projections

Номер: US20120217610A1
Автор: Luu Nguyen, Peter J. Hopper, Peter Johnson, Peter Smeys
Принадлежит: National Semiconductor Corp

A bonded semiconductor structure is formed in a method that first forms a female semiconductor structure with pyramid-shaped openings and a male semiconductor structure with pyramid-shaped projections, and then inserts the projections into the openings to align the male semiconductor structure to the female semiconductor structure for bonding.

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Номер записи: 3
25-04-2013 дата публикации

Semiconductor package and stacked semiconductor package

Номер: US20130099359A1
Автор: Sung Min Kim
Принадлежит: SK hynix Inc

A semiconductor package includes a semiconductor chip having a plurality of bonding pads, dielectric members formed over the semiconductor chip in such a way as to expose portions of respective bonding pads and having a trapezoidal sectional shape, and bumps formed to cover the exposed portions of the respective bonding pads and portions of the dielectric members and having a step-like sectional shape.

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Номер записи: 4
06-01-2022 дата публикации

SEMICONDUCTOR DEVICE WITH A HETEROGENEOUS SOLDER JOINT AND METHOD FOR FABRICATING THE SAME

Номер: US20220005778A1
Автор: Chan Sook Woon, Lee Swee Kah, Lum Fong Mei, Mahler Joachim, Muhammat Sanusi Muhammad
Принадлежит:

A method for fabricating a semiconductor device with a heterogeneous solder joint includes: providing a semiconductor die; providing a coupled element; and soldering the semiconductor die to the coupled element with a first solder joint. The first solder joint includes: a solder material including a first metal composition; and a coating including a second metal composition, different from the first metal composition, the coating at least partially covering the solder material. The second metal composition has a greater stiffness and/or a higher melting point than the first metal composition. 1. A method for fabricating a semiconductor device with a heterogeneous solder joint , the method comprising:providing a semiconductor die;providing a coupled element; and a solder material comprising a first metal composition; and', 'a coating comprising a second metal composition, different from the first metal composition, the coating at least partially covering the solder material,', 'wherein the second metal composition has a greater stiffness and/or a higher melting point than the first metal composition., 'soldering the semiconductor die to the coupled element with a first solder joint, the first solder joint comprising2. The method of claim 1 , wherein the solder material is covered with a coating precursor prior to soldering the semiconductor die to the coupled element claim 1 , and wherein soldering the semiconductor die to the coupled element further comprises converting the coating precursor into the coating.3. The method of claim 2 , further comprising:depositing the solder material on the semiconductor die or on the coupled element; andafterwards covering the deposited solder material with the coating precursor.4. The method of claim 3 , wherein soldering the semiconductor die to the coupled element comprises heating the deposited solder material to melt the deposited solder material claim 3 , and wherein the act of heating the deposited solder material forms the ...

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Номер записи: 5
07-01-2016 дата публикации

Structure and Method of Batch-Packaging Low Pin Count Embedded Semiconductor Chips

Номер: US20160005705A1
Автор: Mutsumi Masumoto
Принадлежит: Texas Instruments Inc

A method for fabricating packaged semiconductor devices in panel format. A flat panel sheet dimensioned for a set of contiguous chips includes a stiff substrate of an insulating plate, and a tape having a surface layer of a first adhesive releasable at elevated temperatures, a core base film, and a bottom layer with a second adhesive attached to the substrate. Attaching a set onto the first adhesive layer, the chip terminals having terminals with metal bumps facing away from the first adhesive layer. Laminating low CTE insulating material to fill gaps between the bumps and to form an insulating frame surrounding the set. Grinding lamination material to expose the bumps. Plasma-cleaning assembly, sputtering uniform metal layer across assembly, optionally plating metal layer, and patterning metal layer to form rerouting traces and extended contact pads.

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Номер записи: 6
02-01-2020 дата публикации

Semiconductor structure and method for forming the same

Номер: US20200006130A1
Автор: Gung-Pei Chang, Hai-Dang Trinh, Yao-Wen Chang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor structure includes a first substrate, a metallic pad disposed over the first substrate, a dielectric structure disposed over the first substrate and exposing a portion of the metallic pad, a bonding structure disposed over and electrically connected to the metallic pad, a barrier ring surrounding the bonding structure, and a through-hole penetrating the first substrate and the dielectric structure. The bonding structure includes a bottom and a sidewall, the bottom of the bonding structure is in contact with the metallic pad, a first portion of the sidewall of the bonding structure is in contact with the dielectric structure, and a second portion of the sidewall of the bonding structure is in contact with the barrier ring.

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Номер записи: 7
15-01-2015 дата публикации

INTERCONNECT STRUCTURE

Номер: US20150014850A1
Автор: Gupta Debabrata, Hashimoto Yukio, Katkar Rajesh, Mirkarimi Laura Wills, Mohammed Ilyas
Принадлежит:

A microelectronic assembly includes first and second surfaces, a first thin conductive element, a first conductive projection, and a first fusible mass. The first thin conductive element includes a face that has first and second regions. The first conductive projection covers the first region of the first face. A barrier may be formed along a portion of the first region. The second face includes a second conductive projection that extends away therefrom. The first fusible metal mass connects the first conductive projection to the second conductive projection such that the first surface of the first face is oriented toward the second surface of the second substrate. The first mass extends along a portion of the first conductive projection to a location toward the first edge of the barrier. The barrier is disposed between the first thin element and the first metal mass. 1. A microelectronic assembly comprising:a first surface;a first thin conductive element exposed on the first surface and having a first face consisting of first and second regions;a first conductive projection connected to and covering the first region of the first face and extending to an end remote therefrom and having a barrier formed along a portion thereof having a first edge remote from the first thin conductive element;a second surface having a second conductive projection extending away therefrom; anda first fusible metal mass connecting the first conductive projection to the second conductive projection such that the first region of the first face is oriented toward the second surface of the second substrate, wherein the first mass extends along a portion of the first conductive projection to a location toward the first edge of the barrier, the barrier being disposed between the first thin element and the first metal mass.2. The microelectronic assembly of claim 1 , wherein the barrier is a surface-treatment layer formed in the first conductive projection.3. The microelectronic assembly of ...

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Номер записи: 8
10-01-2019 дата публикации

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20190013284A1
Автор: FANG Jen-Kuang, Lu Wen-Long
Принадлежит: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

A semiconductor package device includes a carrier, a first electronic component, and a conductive element on the carrier. The first electronic component is over the carrier. The conductive element is on the carrier and electrically connects the first electronic component to the carrier. The conductive element includes at least one conductive particle and a solder material covering the conductive particle, and the conductive particle includes a metal core, a barrier layer covering the metal core, and a metal layer covering the barrier layer. 1. A conductive particle , comprising:a metal core;a barrier layer surrounding the metal core;a first conductive layer surrounding the barrier layer; anda second conductive layer surrounding the first conductive layer,wherein a ratio of a sum of volumes of the metal core, the barrier layer and the first conductive layer to a volume of the second conductive layer is from about 0.1 to about 200.21. The conductive particle of claim 1 , wherein a ratio of a thickness (t) of the second conductive layer to a distance (r) between a center of the metal core and an outer surface of the first conductive layer is from about 0.04 to about 110.31. The conductive particle of claim 2 , wherein about 0.05 micrometers (μm) Подробнее

Номер записи: 9
16-01-2020 дата публикации

Bonding Package Components Through Plating

Номер: US20200020662A1
Автор: Ho MIng-Che, Lim Zheng-Yi, Liu Chung-Shi, Wu Yi-Wen, Yang Tzong-Hann
Принадлежит:

A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

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Номер записи: 10
26-01-2017 дата публикации

Pre-package and methods of manufacturing semiconductor package and electronic device using the same

Номер: US20170025302A1
Автор: Gun-ho Chang, Tae-Je Cho, Un-Byoung Kang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate.

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Номер записи: 11
25-01-2018 дата публикации

INTERCONNECT STRUCTURE WITH REDUNDANT ELECTRICAL CONNECTORS AND ASSOCIATED SYSTEMS AND METHODS

Номер: US20180026015A1
Автор: Chandolu Anilkumar
Принадлежит:

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film. 1. A semiconductor device , comprising:a semiconductor substrate;a dielectric material over the substrate;a conductive trace extending at least partially through the dielectric material; and a conductive member coupled to the conductive trace, and', 'a conductive bond material bonded to the conductive member,, 'a plurality of redundant electrical connectors extending from the conductive trace and through at least a portion of the dielectric material, wherein each of the redundant electrical connectors includes—'}wherein all of the redundant electrical connectors are coupled to the conductive trace.2. The semiconductor device of wherein the dielectric includes a plurality of openings exposing portions of the conductive trace claim 1 , wherein the redundant electrical connectors are formed in the openings.3. The semiconductor device of wherein the conductive member comprises copper and the bond material comprises a solder material.4. The semiconductor device of wherein the conductive member includes an end portion claim 1 , and wherein the conductive bond material and conductive member form a conductive joint at the end portion.5. The semiconductor device of claim 1 , further comprising a through-substrate via (TSV) extending at least partially through the substrate claim 1 , ...

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Номер записи: 12
24-01-2019 дата публикации

SEMICONDCUTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20190027452A1
Автор: Chen Chen-Shien, Chen Ching-Hui, Huang Hon-Lin, KU Chin-Yu, KUO Chien-Hung, WANG CHAO-YI, Yang Cheng-Lung
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device and a manufacturing method for the semiconductor device are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump a spacer and surrounds the bump and disposed between the etching stop layer and the bump. 17-. (canceled)8. A manufacturing method for a semiconductor device , comprising:forming an etching stop layer over a first dielectric layer, wherein the first dielectric layer is formed over a conductive structure;forming a sacrificial layer over the etching stop layer, wherein an opening passes through the sacrificial layer and the etching stop layer to expose a portion of the conductive structure;forming a spacer on a sidewall of the opening;after forming the spacer, forming a bump in the opening to electrically connect the conductive structure, wherein the spacer is disposed between the etching stop layer and the bump; andafter forming the bump, removing a portion of the spacer on the sidewall of the opening.9. The method as claimed in claim 8 , wherein the spacer is formed over the first dielectric layer between the etching stop layer and the bump.10. The method as claimed in claim 8 , wherein forming the bump and the spacer comprises:forming a spacer layer on the sidewall and a bottom of the opening;removing the spacer layer on the bottom of the opening, to expose the conductive structure and form the spacer;forming the bump in the opening, wherein the spacer on the sidewall of the opening surrounds the bump; andremoving the portion of the spacer on the sidewall of the opening.11. The method as claimed in claim 8 , further comprising forming a second dielectric layer over a portion of the first dielectric layer ...

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Номер записи: 13
24-01-2019 дата публикации

DIRECT SUBSTRATE TO SOLDER BUMP CONNECTION FOR THERMAL MANAGEMENT IN FLIP CHIP AMPLIFIERS

Номер: US20190028067A1
Автор: Gill Bharatjeet Singh, Kovacic Stephen Joseph, McPartlin Michael Joseph
Принадлежит:

Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps. 1. A device comprising:an amplifier including at least one transistor formed over a silicon substrate; anda metal pillar formed with respect to the silicon substrate such that a portion of the metal pillar is in direct contact with the silicon substrate, heat generated during operation of the at least one transistor being transferred through the silicon substrate to the portion of the metal pillar.2. The device of further comprising a first resistor in communication with an emitter of the at least one transistor and with the metal pillar.3. The device of further comprising a second resistor in communication with a base of the at least one transistor.4. The device of wherein the metal pillar is formed within a cavity etched into the silicon substrate.5. The device of wherein the metal pillar protrudes outward and upward from the cavity.6. The device of wherein the portion of the metal pillar in direct contact with the silicon substrate is a bottom and at least a portion of sides of the metal pillar7. The device of wherein the portion of the metal pillar in direct contact with the silicon substrate is a bottom of the metal pillar.8. The device of wherein the metal pillar is configured to provide a flip chip interconnection for the amplifier.9. The device of wherein the metal pillar is adjacent to the at least one transistor.10. A method to implement an emitter-ballasted amplifier in a flip chip configuration claim 1 , the method comprising:forming an amplifier including at ...

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Номер записи: 14
04-02-2016 дата публикации

CHIP INTEGRATION MODULE, CHIP PACKAGE STRUCTURE, AND CHIP INTEGRATION METHOD

Номер: US20160035689A1
Автор: Fu HuiLi, Gao Song
Принадлежит:

The present invention provides a chip integration module, including a die, a passive device, and a connecting piece, where the die is provided with a die bonding portion, the passive device is provided with a passive device bonding portion, the die bonding portion of the die and the passive device bonding portion of the passive device are disposed opposite to each other, and the connecting piece is disposed between the die bonding portion and the passive device bonding portion and is connected to the die bonding portion and the passive device bonding portion. The chip integration module of the present invention achieves easy integration and has low costs. Moreover, a path connecting the die to the passive device becomes shorter, which can improve performance of the passive device. The present invention further discloses a chip package structure and a chip integration method. 1. A chip integration module , comprising a die , a passive device , and a connecting piece , wherein the die is provided with a die bonding portion , the passive device is provided with a passive device bonding portion , the die bonding portion of the die and the passive device bonding portion of the passive device are disposed opposite to each other , and the connecting piece is disposed between the die bonding portion and the passive device bonding portion , and is connected to the die bonding portion and the passive device bonding portion.2. The chip integration module according to claim 1 , wherein the die bonding portion of the die and the passive device bonding portion of the passive device are made of metal.3. The chip integration module according to claim 2 , wherein the connecting piece is made of any one of gold claim 2 , silver claim 2 , copper claim 2 , titanium claim 2 , nickel claim 2 , and aluminum claim 2 , or an alloy of any two or more of the foregoing metal.4. The chip integration module according to claim 3 , wherein the connecting piece is connected to the die bonding ...

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Номер записи: 15
01-02-2018 дата публикации

Semiconductor Die Singulation and Structures Formed Thereby

Номер: US20180033695A1
Автор: Chang Fu-Chen, Chen Wen-Ming, Huang Cheng-Lin
Принадлежит:

An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate. 1. A method comprising:receiving a wafer comprising:a first integrated circuit die;a second integrated circuit die; anda scribe line region between the first integrated circuit die and the second integrated circuit die; andforming a kerf in the scribe line region, wherein the kerf extends through a plurality of dielectric layers into a semiconductor substrate, and wherein the kerf comprises:a first width at an interface between the plurality of dielectric layers and the semiconductor substrate; anda second width at a surface of the plurality of dielectric layers opposite the semiconductor substrate, wherein a ratio of the first width to the second width is at least about 0.6.2. The method of claim 1 , wherein an angle between a bottom surface of the kerf and a sidewall of the kerf is about 90° to about 135°.3. The method of further comprising after forming the kerf claim 1 , using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die.4. The method of claim 3 , wherein the mechanical sawing process comprises using a saw blade having a third width claim 3 , wherein the third width is less than the first width.5. The method of claim 1 , wherein forming the kerf in the scribe line region comprises a laser ablation process.6. The method of claim 5 , wherein the laser ablation process further forms a recast region on a sidewall of the plurality of dielectric layers and a sidewall ...

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Номер записи: 16
01-02-2018 дата публикации

Integrated circuit chip and display device including the same

Номер: US20180033755A1
Автор: Jeong Do Yang, Jeong Ho Hwang, Jung Yun Jo, Sang Hyeon SONG, Seung-Hwa HA
Принадлежит: Samsung Display Co Ltd

An exemplary embodiment provides a driving circuit chip including: a substrate; a terminal electrode disposed on the substrate; and an electrode pad disposed on the terminal electrode, wherein the electrode pad includes: a bump structure protruded from the substrate to include a short side and a long side; and a bump electrode disposed on the bump structure and connected with the terminal electrode around a short edge portion of the bump structure, wherein the bump electrode is disposed to not cover at least a part of a long edge portion of the bump structure.

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Номер записи: 17
30-01-2020 дата публикации

BUMP BOND STRUCTURE FOR ENHANCED ELECTROMIGRATION PERFORMANCE

Номер: US20200035633A1
Автор: Mishra Dibyajat, Nguyen Hau, Nguyen Luu Thanh, NOGUCHI Tomoko, Poddar Anindya, Prabhu Ashok, YOSHINO Makoto
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint. 1. A microelectronic device , comprising:a die having a terminal;a copper-containing pillar electrically coupled to the terminal, the copper-containing pillar including at least 90 weight percent copper; andan intermetallic joint on the copper-containing pillar, the intermetallic joint electrically coupling the copper pillar to an external terminal; [{'sub': 6', '5', '3, 'the intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound (IMC) selected from the group consisting of CuSnand CuSn;'}, 'the intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and', 'the intermetallic joint is free of a void having a volume greater than 5 percent of the volume of the intermetallic joint., 'wherein2. The microelectronic device of claim 1 , wherein the intermetallic joint includes 0.1 weight percent to 5 weight percent silver.3. The microelectronic device of claim 1 , further including a dielectric material surrounding the intermetallic joint.4. The microelectronic ...

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Номер записи: 18
24-02-2022 дата публикации

DESIGNS AND METHODS FOR CONDUCTIVE BUMPS

Номер: US20220059484A1
Автор: Balakrishnan Sridhar, BOHR Mark, Dubin Valery M.
Принадлежит:

Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer. 1. An assembly comprising:a die;a pad on the die, the pad including aluminum;a passivation layer on the die, the passivation layer having an opening over the pad;a base layer metal on the pad in the opening of the passivation layer, the base layer metal further on a portion of the passivation layer, and the base layer metal including titanium;a copper bump on the base layer metal;a diffusion barrier layer on the copper bump, the diffusion barrier layer including nickel;a conductive material above the diffusion barrier layer, the conductive material comprising tin and copper; anda solder layer on the conductive material, the solder layer comprising tin, silver and copper.2. The assembly of claim 1 , wherein the diffusion barrier layer has a thickness of approximately 5 microns.3. The assembly of claim 1 , wherein the passivation layer comprises silicon and nitrogen.4. The assembly of claim 1 , wherein the passivation layer comprises a polyimide.5. The assembly of claim 1 , wherein the base layer metal further comprises copper.6. The assembly of claim 1 , wherein the conductive material further comprises silver.7. The ...

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Номер записи: 19
15-02-2018 дата публикации

Package-On-Package (PoP) Structure Including Stud Bulbs

Номер: US20180047709A1
Автор: Cheng Ming-Da, Lii Mirng-Ji, Liu Chung-Shi, Yu Chen-Hua
Принадлежит:

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first surface of a first substrate;a second pad on a second surface of a second substrate;a metallic element interposed between the first pad and the second pad, the metallic element electrically coupled to the first pad, the metallic element comprising a base portion and an elongated portion extending from the base portion toward the second pad;a solder connector in contact with the elongated portion and electrically coupled to the second pad; andan inter-metallic compound (IMC) between the elongated portion and the solder connector.2. The device of claim 1 , further comprising a protection layer extending over the base portion and the elongated portion.3. The device of claim 1 , further comprising a die attached to the first substrate adjacent the metallic element.4. The device of claim 3 , wherein a height of the metallic element from the first substrate is greater than a height of the die from the first substrate.5. The device of claim 1 , wherein the metallic element comprises a copper wire.6. The device of claim 1 , wherein the base portion and the elongated portion comprises a single continuous element.7. A device comprising:a first substrate having a first pad;a second substrate having a second pad;a first connector interposed between the first pad and the second pad, the first connector having a first wide portion and a second elongated portion, the first wide portion being ...

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Номер записи: 20
22-02-2018 дата публикации

Semiconductor Packages and Methods of Forming the Same

Номер: US20180053730A1
Автор: Chen-Hua Yu, Chih-Hang Tung, Tung-Liang Shao
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Semiconductor packages and methods of forming the same are disclosed. Embodiments include forming a first recess in a first substrate, wherein a first area of an opening of the first recess is larger than a second area of a bottom of the first recess. The embodiments also include forming a first device, wherein a third area of a top end of the first device is larger than a fourth area of a bottom end of the first device. The embodiments also include placing the first device into the first recess, wherein the bottom end of the first device faces the bottom of the first recess, and bonding a sidewall of the first device to a sidewall of the first recess.

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Номер записи: 21
23-02-2017 дата публикации

INTEGRATED CIRCUIT PACKAGE

Номер: US20170053883A1
Автор: How You Chye, Tay Huay Yann
Принадлежит:

An integrated circuit (“IC”) package including at least one IC die having a first side with at least two adjacent bump pads thereon and a second side opposite the first side; a first substrate having a first side with a plurality of electrical contact surfaces thereon; and a plurality of copper pillars, each having a first end attached to one of the adjacent bump pads and a second end attached to one of the electrical contact surfaces. 1. An integrated circuit (IC) package comprising:an IC die having a first side and a second side opposite the first side;a bump pad on the first side;a first substrate having a first side with a plurality of electrical contact surfaces;a plurality of metal pillars, each having a first end attached to the bump pad via a passivation layer, and a second end attached to one of a plurality of electrical contact surfaces of a first substrate;an intermetallic compound surrounding portions of the plurality of metal pillars; anda mold compound encapsulating the intermetallic compound.2. The IC package of claim 1 , wherein the plurality of metal pillars include copper.3. The IC package of claim 1 , wherein the intermetallic compound comprises a copper and lead compound.4. The IC package of claim 3 , wherein the copper and lead compound comprises CuSn.5. The IC package of claim 3 , wherein the copper and lead compound comprises CuSn.6. The IC package of further comprising a second substrate attached to the second side of the IC die.7. The IC package of claim 6 , wherein the mold compound encapsulates at least a portion of the IC die claim 6 , and the first and second substrates.8. The IC package of claim 6 , wherein said first substrate comprises a first leadframe and wherein said second substrate comprises a second leadframe.9. The IC package of claim 1 , wherein the intermetallic compound has higher melting temperatures than solder and lower coefficients of expansion than solder.10. An integrated circuit (“IC”) package comprising:an IC die ...

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Номер записи: 22
01-03-2018 дата публикации

Semiconductor chip, display panel, and electronic device

Номер: US20180061748A1
Автор: Byoung Yong Kim, Jeong Ho Hwang
Принадлежит: Samsung Display Co Ltd

A semiconductor chip, a display device or an electronic device includes a substrate, one or more conductive pads disposed on the substrate, and one or more bumps electrically connected to the one or more conductive pads, in which the one or more bumps includes a metal core, a polymer layer disposed over a surface of the metal core, and a conductive coating layer disposed over a surface of the polymer layer and electrically connected to the one or more conductive pads.

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Номер записи: 23
28-02-2019 дата публикации

Wiring substrate and semiconductor device

Номер: US20190067224A1
Автор: Jun Furuichi
Принадлежит: Shinko Electric Industries Co Ltd

A wiring substrate includes a first wiring structure. The first wiring structure has a first insulation layer including a reinforcement material. A first wiring layer is embedded in the first insulation layer. A second wiring structure having a higher wiring density than the first wiring structure is formed on the first insulation layer. The second wiring structure includes at least one second insulation layer and two or more second wiring layers. A lower surface of the first wiring layer is flush with a lower surface of the first insulation layer. The reinforcement material is located toward the second wiring structure from a thickness-wise center of the first insulation layer and laid out at a thickness-wise center of a thickness from the lower surface of the first insulation layer to an upper surface of the uppermost second wiring layer in the second wiring structure.

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Номер записи: 24
27-02-2020 дата публикации

METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURE FOR JOINING WAFERS AND RESULTING STRUCTURE

Номер: US20200066667A1
Автор: Atanasova Tanya A., Farooq Mukta G.
Принадлежит:

The disclosure is directed to an integrated circuit structure for joining wafers. The IC structure may include: a metallic pillar over a substrate, the metallic pillar including an upper surface; a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and a solder material over the upper surface of the metallic pillar, the solder material being within and constrained by the wetting inhibitor layer. The sidewall of the metallic pillar may be free of the solder material. 1. An integrated circuit structure for joining wafers , the integrated circuit structure comprising:a metallic pillar over a substrate, the metallic pillar including an upper surface;a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar, wherein the wetting inhibitor layer includes a periphery with a first thickness and an inner edge with a second thickness, wherein the first thickness is greater than the second thickness; anda solder material over the upper surface of the metallic pillar, the solder material being within and constrained by the wetting inhibitor layer.2. The integrated circuit structure of claim 1 , wherein the wetting inhibitor layer includes a dielectric or a fluorocarbon.3. The integrated circuit structure of claim 1 , wherein the metallic pillar includes at least one of copper or nickel.4. The integrated circuit structure of claim 1 , wherein the wetting inhibitor layer includes a width of approximately 2.0 micrometers (μm) to approximately 6.0 μm.5. (canceled)6. The integrated circuit structure of claim 1 , wherein a sidewall of the metallic pillar is free of the solder material.7. The integrated circuit of claim 1 , wherein the metallic pillar includes a plurality of layers.8. The integrated circuit of claim 1 , wherein an upper surface of the metallic pillar is substantially circular.9. The integrated circuit structure of claim 8 , wherein the wetting inhibitor layer defines an annular ring over the metallic ...

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Номер записи: 25
17-03-2016 дата публикации

Semiconductor package structure

Номер: US20160079157A1
Автор: Jen-Kuang Fang, Kuo-Hua Chen
Принадлежит: Advanced Semiconductor Engineering Inc

The present disclosure relates to a semiconductor package structure, including a die and a package substrate. The die includes a semiconductor substrate, multiple interconnect metal layers, and at least one inter-level dielectric disposed between ones of the interconnect metal layers. Each inter-level dielectric is formed of a low k material. An outermost interconnect metal layer has multiple first conductive segments exposed from a surface of the inter-level dielectric. The package substrate includes a substrate body and multiple second conductive segments exposed from a surface of the substrate body. The second conductive segments are electrically connected to the first conductive segments.

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Номер записи: 26
17-03-2016 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20160079195A1
Автор: TANAKA Jun
Принадлежит:

A semiconductor device includes a first substrate and a second substrate facing the first substrate, each substrate having conductive pads disposed thereon, an insulating adhesive layer sealing the space between the first substrate and the second substrate, and a plurality of bumps penetrating the insulating adhesive layer and electrically connecting the plurality of first conductive pads and the plurality of second conductive pads. The plurality of bumps include at least a first bump having a first height and a second bump that is provided in a position closer to a geometric center of the second substrate than the first bump and has a second height greater than the first height. 1. A semiconductor device comprising:a first substrate having a surface;a plurality of first conductive pads provided on the surface of the first substrate;a second substrate having a surface;a plurality of second conductive pads provided below the surface of the second substrate, wherein the surface of the first substrate faces the surface of the second substrate;a sealing layer sealing a space between the first substrate and the second substrate; anda plurality of bumps electrically connecting the plurality of first conductive pads and the plurality of second conductive pads,wherein the plurality of bumps include at least a first bump and a second bump, wherein the second bump is provided in a position closer to a geometric center of the second substrate than the first bump,the first bump has a first height, andthe second bump has a second height greater than the first height.2. The semiconductor device according to claim 1 , whereinthe plurality of bumps is disposed on a plurality of circumferences of a plurality of circles that share a geometric center of the second substrate,the first bump is disposed on a circumference of a first circle, the second bump is disposed on a circumference of a second circle, and a diameter of the first circle is greater than a diameter of the second circle ...

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Номер записи: 27
05-03-2020 дата публикации

SERIALIZER-DESERIALIZER DIE FOR HIGH SPEED SIGNAL INTERCONNECT

Номер: US20200075521A1
Автор: Elsherbini Adel A., Liff Shawna M., Pasdast Gerald S., Swan Johanna M.
Принадлежит: Intel Corporation

In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed. 1. A semiconductor package comprising:a first die;a second die; anda first serializer/deserializer (SerDes) die physically coupled with the first die and communicatively coupled with the second die, wherein the first SerDes die is to serialize signals transmitted from the first die to the second die, and the first SerDes die is to deserialize signals received from the second die.2. The semiconductor package of claim 1 , wherein the die is a monolithic die or a composite die.3. The semiconductor package of claim 1 , further comprising a second SerDes die physically coupled with the second die and communicatively coupled with the first SerDes die claim 1 , wherein the second SerDes die is to serialize signals transmitted from the second die to the first die claim 1 , and the second SerDes die is to deserialize signals received from the first die.4. The semiconductor package of claim 1 , wherein the first SerDes die has first pads at a first pitch at a side of the SerDes die coupled with the first die claim 1 , and the first SerDes die has second pads at a second pitch at a side of the SerDes die communicatively coupled with the second die.5. The semiconductor package of claim 4 , wherein the first pitch is larger than the second pitch.6. The semiconductor package of claim 1 , wherein the second die is an interposer.7. The semiconductor package of claim 1 , wherein the second die is a dual-sided interconnect die that includes an active component.8. A method of forming a die with a serializer/deserializer (SerDes) die attached thereto claim 1 , the method comprising: ...

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Номер записи: 28
05-03-2020 дата публикации

SEMICONDUCTOR DEVICE HAVING BUMP STRUCTURES AND SEMICONDUCTOR PACKAGE HAVING THE SAME

Номер: US20200075524A1
Автор: CHOI Ju Il, Lee Dong Hoon, LIM Dong Chan, PARK Su Jeong, SEO Ju Bin
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor device including a substrate including a first conductive pad on a first surface thereof, at least one first bump structure on the first conductive pad, the first bump structure including a first connecting member and a first delamination prevention layer, the first delamination prevention layer on the first connecting member and having a greater hardness than the first connecting member, and a first encapsulant above the first surface of the substrate and surrounding the first bump structure may be provided. 1. A semiconductor device comprising:a substrate including a first conductive pad on a first surface thereof;at least one first bump structure on the first conductive pad, the first bump structure including a first connecting member and a first delamination prevention layer, the first delamination prevention layer on the first connecting member and having a greater hardness than the first connecting member; anda first encapsulant above the first surface of the substrate and surrounding the first bump structure.2. The semiconductor device of claim 1 , wherein the first delamination prevention layer comprises an intermetallic compound.3. The semiconductor device of claim 2 , wherein the intermetallic compound comprises a Cu—Sn based intermetallic compound claim 2 , an Au-Sn based intermetallic compound claim 2 , or a combination thereof.4. The semiconductor device of claim 1 , wherein the first bump structure further comprises a metal layer disposed on an upper surface of the first delamination prevention layer.5. The semiconductor device of claim 1 , wherein an upper surface of the first delamination prevention layer is exposed to an outside of the first encapsulant.6. The semiconductor device of claim 1 , wherein a thickness of the first delamination prevention layer is smaller than a thickness of the first connecting member.7. The semiconductor device of claim 1 , whereinan upper surface of the first delamination prevention layer and an upper ...

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Номер записи: 29
18-03-2021 дата публикации

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20210082853A1
Автор: FANG Hsu-Nan, KAO Chin-Li, LIN Yung-Sheng
Принадлежит: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pith region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed. 1. A semiconductor package structure , comprising:a first carrier having a first surface, the first surface comprising a first region and a second region;a second carrier having a second surface opposing the first surface, the second surface comprising a third region corresponding to the first region and a fourth region corresponding to the second region;a plurality of first type conductive pillars between the first region of the first surface and the third region of the second surface; anda plurality of second type conductive pillars between the second region of the first surface and the fourth region of the second surface;wherein a contact resistance of each of the first type conductive pillars is lower than a contact resistance of each of the second type conductive pillars.2. The semiconductor package structure of claim 1 , wherein each of the plurality of first type conductive pillars comprises a copper-copper interface.3. The semiconductor package structure of claim 2 , wherein each of the plurality of second type conductive pillars comprises a copper-solder interface.4. The semiconductor package structure of claim 1 , wherein a pitch of the first type conductive pillars in the first region is smaller than a pitch of the second type conductive pillars in the second region.5. The semiconductor package structure of claim 4 , wherein the pitch of the first type conductive pillars in the first region is ...

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Номер записи: 30
23-03-2017 дата публикации

DESIGNS AND METHODS FOR CONDUCTIVE BUMPS

Номер: US20170084564A1
Автор: Balakrishnan Sridhar, BOHR Mark, Dubin Valery M.
Принадлежит:

Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer. 1. A method of forming an assembly , comprising:providing a die, the die having a metal pad including aluminum, a base layer metal (BLM) disposed on the metal pad, the BLM including titanium, a bump disposed on the BLM, the bump including copper, and a first solder layer disposed on the bump, the first solder layer including tin;providing a package, the package having a first side and an opposing second side, and a second solder layer disposed on the first side of the package, the second solder layer including tin;connecting the second solder layer of the package to the first solder layer of the die to enable electrical current to flow between the package and the die.2. The method of claim 1 , wherein the bump is disposed directly on the BLM.3. The method of claim 1 , wherein the base layer metal (BLM) further includes copper.4. The method of claim 1 , wherein the first solder layer further includes silver.5. The method of claim 1 , wherein the second solder layer on the package further includes silver and copper.6. The method of claim 1 , wherein the die further comprises a diffusion barrier layer disposed between the ...

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Номер записи: 31
29-03-2018 дата публикации

FILM-TYPE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Номер: US20180090459A1
Автор: KIM Jung-woo, KIM Woon-bae, NOH Bo-in, Park Ji-Yong, SEONG Go-woon
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A film-type semiconductor package includes a metal lead portion arranged on a film substrate, a semiconductor chip including a pad, and a bump connecting the metal lead portion to the pad of the semiconductor chip. The bump includes a metal pillar arranged on the pad and including a first metal and a soldering portion arranged on an entire surface of the metal pillar, bonded to the metal lead portion, and including the first metal and a second metal that is different from the first metal. 1. A film-type semiconductor package comprising:a metal lead portion on a film substrate;a semiconductor chip including a pad; and a metal pillar on the pad and including a first metal; and', 'a soldering portion on an entire surface of the metal pillar, bonded to the metal lead portion, and including the first metal and a second metal that is different from the first metal;, 'a bump connecting the metal lead portion to the pad of the semiconductor chip, the bump including,'}wherein the metal lead portion comprises a metal lead and a lead protective layer protecting a surface of the metal lead;the metal lead includes a copper layer, andthe lead protective layer includes a tin layer.23-. (canceled)4. The film-type semiconductor package of claim 1 , wherein the metal pillar comprises a gold layer or a copper layer.5. The film-type semiconductor package of claim 1 , wherein the soldering portion comprises a gold-tin eutectic alloy layer.6. The film-type semiconductor package of claim 5 , wherein a content of tin atoms in the gold-tin eutectic alloy layer is equal to or greater than about 25% and equal to or less than about 45%.7. The film-type semiconductor package of claim 1 , wherein the soldering portion surrounds a bottom and opposite side surfaces of the metal lead portion.8. The film-type semiconductor package of claim 1 , wherein the diffusion preventing layer includes a third metal that is different from the first metal and the second metal.9. The film-type semiconductor ...

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Номер записи: 32
29-03-2018 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20180090461A1
Автор: KAGEYAMA Satoshi, TANAKA Bungo, Wada Keiji
Принадлежит: ROHM CO., LTD.

A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer. 1. A semiconductor comprising:an insulating layer;a barrier electrode layer formed on the insulating layer;a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer; andan outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.2. The semiconductor device according to claim 1 , wherein the outer-surface insulating film is in contact with the principal surface of the barrier electrode layer at a position with an interval from a peripheral edge of the barrier electrode layer toward an inward side of the barrier electrode layer.3. The semiconductor device according to claim 1 , wherein the Cu electrode layer includes a first surface and a second surface that is positioned on a side opposite to the first surface and that is connected to the barrier electrode layer claim 1 , anda peripheral edge of the second surface of the Cu electrode layer is formed at a position with an interval from the peripheral edge of the barrier electrode layer toward the inward side of the barrier electrode layer.4. The semiconductor device according to claim 1 , wherein the Cu electrode layer includes a first surface and a second surface that is positioned on a side opposite to the first surface and that is connected to the barrier electrode layer claim 1 , andthe second surface of the Cu electrode layer is formed narrower than ...

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Номер записи: 33
21-03-2019 дата публикации

LATERALLY EXTENDED CONDUCTIVE BUMP BUFFER

Номер: US20190088610A1
Автор: Chen Hsin-Hung, LAI Chia-Ping, Tsai Yu-Hsiang
Принадлежит:

A semiconductor device includes: a conductive structure, a conductive bump extending into the conductive structure and contacting the conductive structure along a first surface, the conductive bump configured to interface with an external semiconductor device at a second surface opposite the first surface, the conductive bump being wider along the first surface than the second surface. 1. A semiconductor device , comprising:a conductive structure,a conductive bump extending into the conductive structure and contacting the conductive structure with a buffer material along a first surface, the conductive bump with a head material configured to interface with an external semiconductor device at a second surface opposite the first surface, the conductive bump being wider along the first surface with the buffer material contacting and laterally surrounded by the conductive structure than along the second surface with the head material.2. The semiconductor device of claim 1 , wherein the conductive bump extends into the conductive structure along an isotropic recess that extends into the conductive structure.3. The semiconductor device of claim 2 , wherein the conductive bump is formed in an anisotropic recess formed using anisotropic etching.4. The semiconductor device of claim 1 , wherein the conductive bump comprises nickel at the first surface and gold at the second surface.5. The semiconductor device of claim 4 , wherein the conductive structure comprises copper.6. The semiconductor device of claim 1 , wherein the conductive bump comprises sidewalls that are nonlinear.7. The semiconductor device of claim 1 , wherein the conductive bump comprises sidewalls that include a corner.8. A semiconductor device claim 1 , comprising:a horizontal conductive structure;a layer overlaying the horizontal conductive structure; and a head material, and', 'a buffer material adjoining the head material, the buffer material extending into and laterally surrounded by the horizontal ...

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Номер записи: 34
01-04-2021 дата публикации

Thermocompression bonding of electronic components

Номер: US20210098416A1
Автор: Eckardt Bihler, Marc Hauer
Принадлежит: DYCONEX AG

A method for producing an electronic module includes providing a first substrate including at least one first electrical contacting surface, an electronic component including at least one second electrical contacting surface, and a first material layer made of a thermoplastic material including at least one recess extending through the material layer. The first substrate, the electronic component and the first material layer are arranged with the first material layer disposed between the first substrate and the electronic component, and the at least one first electrical contacting surface, the at least one second electrical contacting surface and the at least one recess aligned relative to one another. The first substrate, the electronic component and the material layer are thermocompression bonded. A joint formed between the at least one first electrical contacting surface and the at least one second electrical contacting surface is surrounded or enclosed by the first material layer.

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Номер записи: 35
06-04-2017 дата публикации

Semiconductor device

Номер: US20170098625A1
Автор: Hirofumi Takeda, Yoshihisa Takada
Принадлежит: ROHM CO LTD

A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device ( 1 D) includes, a substrate ( 100 D), which includes a main surface ( 101 D) and a recess ( 108 D) depressed from the main surface ( 101 D), and includes a semiconductor material; a wiring layer ( 200 D) in which at least a portion thereof is formed on the substrate ( 100 D); one or more first elements ( 370 D) accommodated in the recess ( 108 D); a sealing resin ( 400 D) covering at least a portion of the one or more first elements ( 370 D) and filled in the recess ( 108 D); and a plurality of columnar conductive portions ( 230 D) penetrating through the sealing resin ( 400 D) in the depth direction of the recess ( 108 D), and respectively connected with the portion of the wiring layer ( 200 D) that is formed at the recess ( 108 D).

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Номер записи: 36
28-03-2019 дата публикации

SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Номер: US20190096832A1
Автор: CHANG Kuo-Chin, HSIAO HUANG-TING, TSAO Pei-Haw, XU AN-TAI
Принадлежит:

A method for fabricating a semiconductor structure is provided. The method includes: providing a semiconductor chip comprising an active surface; forming a conductive bump over the active surface of the semiconductor chip; and coupling the conductive bump to a substrate. The conductive bump includes a plurality of bump segments including a first group of bump segments and a second group of bump segments. Each bump segment has a same segment thickness in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment has a volume defined by a multiplication of the same segment thickness with an average cross-sectional area of the bump segment in a plane parallel to the active surface of the semiconductor chip. A ratio of a total volume of the first group of bump segments to a total volume of the second group of bump segments is between 0.03 and 0.8. 1. A method for fabricating a semiconductor structure comprising:providing a semiconductor chip comprising an active surface;forming a conductive bump over the active surface of the semiconductor chip; andcoupling the conductive bump to a substrate,wherein the conductive bump comprises:a plurality of bump segments comprising a first group of bump segments and a second group of bump segments, wherein each bump segment has a same segment thickness in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment has a volume defined by a multiplication of the same segment thickness with an average cross-sectional area of the bump segment in a plane parallel to the active surface of the semiconductor chip;wherein a ratio of a total volume of the first group of bump segments to a total volume of the second group of bump segments is between 0.03 and 0.8.2. The method of claim 1 , wherein each bump segment comprises a shape of a pillar or a frustum.3. The method of claim 1 , wherein forming the conductive bump over the semiconductor chip comprises forming different ...

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Номер записи: 37
04-04-2019 дата публикации

POLYMER LID WAFER-LEVEL PACKAGE WITH AN ELECTRICALLY AND THERMALLY CONDUCTIVE PILLAR

Номер: US20190103852A1
Автор: Barfknecht Andrew Thomas, Franosch Martin, Gilbert Stephen Roy, RUBY Richard C., Sridaran Suresh
Принадлежит:

An apparatus include a device substrate having an upper surface, and a frame layer having an upper surface. The frame layer is disposed over the upper surface of the device substrate, and a first opening exists in the frame layer. The apparatus also includes a seed layer disposed over the device substrate and substantially bounded by the first opening; and a lid layer having an upper surface. The lid layer is disposed over the upper surface of the frame layer. A second opening exists in the lid layer, and the second opening is aligned with the first opening. The apparatus also includes an electrically and thermally conductive pillar disposed in the first opening and the second opening. 1. An apparatus , comprising:a device substrate having an upper surface;a frame layer having an upper surface, the frame layer being disposed over the upper surface of the device substrate, wherein a first opening exists in the frame layer;a seed layer disposed over the device substrate and substantially bounded by the first opening;a lid layer having an upper surface, the lid layer disposed over the upper surface of the frame layer, wherein a second opening exists in the lid layer, and the second opening is aligned with the first opening;an electrically and thermally conductive pillar disposed in the first opening and the second opening, the electrically and thermally conductive pillar having an upper surface that is beneath the upper surface of the lid layer; andan electrically and thermally conductive layer disposed over the upper surface of the electrically and thermally conductive pillar, and extending above the upper surface of the lid layer.2. The apparatus of claim 1 , wherein a portion of the seed layer is between a lower surface of the frame layer and the upper surface of the device substrate.3. The apparatus of claim 1 , wherein the electrically and thermally conductive pillar comprises a first material claim 1 , and the electrically and thermally conductive layer comprises ...

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Номер записи: 38
02-06-2022 дата публикации

METHOD FOR ASSEMBLING COMPONENTS IMPLEMENTING A PRE-TREATMENT OF THE SOLDER BUMPS ALLOWING AN ASSEMBLY BY FLUXLESS AND RESIDUE-FREE SOLDERING

Номер: US20220173069A1
Автор: CAICEDO PANQUEVA Nohora-Lizeth, CASTANY Olivier, Miloud-Ali Nadia, ZONOU Yezouma-dieudonne
Принадлежит: Commissariat A L'Energie Atomique Et Aux Energies Alternatives

A method for assembling components implementing includes a pre-treatment of the solder bumps allowing an assembly by fluxless and residue-free soldering. A first component carrying solder bumps is assembled with a second component carrying connectors. Beforehand, a pre-treatment of the components carrying solder bumps is carried out by contacting them with a pre-treatment liquid which makes their subsequent fluxless and residue-free soldering possible. 1. A solder bump assembly method , comprising:assembling a first component including solder bumps with a second component including connectors,the assembly of the components being preceded by pre-treating the first and second components wherein the solder bumps are contacted with a pre-treatment liquid configured to at least partially remove an oxide layer initially present on the solder, andthe assembly of the components being carried out after the pre-treatment in the absence of liquid or gas flux wherein the pre-treatment liquid is an aqueous solution containing carboxylic acids or polycarboxylic acids.2. The method according to claim 1 , wherein the contacting with the pre-treatment liquid is configured to leave a thin film on the surface of the treated components claim 1 , with a thickness less than 100 nm claim 1 , the thin film having a property of promoting effective soldering without leaving residues after assembly claim 1 , the method comprising prolonging action of the pre-treatment so that soldering can be done more than one hour after the pre-treatment without reducing the assembly efficiency.3. The method according to claim 1 , the aqueous solution containing amines or polyamines.4. The method according to claim 1 , the aqueous solution containing amino acids or poly amino acids.5. The method according to claim 1 , wherein the pre-treatment liquid is an aqueous solution containing glutamic acid hydrochloride claim 1 , in a concentration comprised between 10 and 20% by mass.6. The method according to ...

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Номер записи: 39
27-04-2017 дата публикации

Anchoring structure of fine pitch bva

Номер: US20170117243A1
Автор: Cyprian Emeka Uzoh, Gabriel Z. Guevara, Guilian Gao, Liang Wang, Rajesh Katkar, Xuan Li
Принадлежит: Invensas LLC

A microelectronic package can include a substrate having a first surface and a second surface opposite therefrom, the substrate having a first conductive element at the first surface, and a plurality of wire bonds, each of the wire bonds having a base electrically connected to a corresponding one of the first conductive elements and having a tip remote from the base, each wire bond having edge surfaces extending from the tip toward the base. The microelectronic package can also include an encapsulation having a major surface facing away from the first surface of the substrate, the encapsulation having a recess extending from the major surface in a direction toward the first surface of the substrate, the tip of a first one of the wire bonds being disposed within the recess, and an electrically conductive layer overlying an inner surface of the encapsulation exposed within the recess, the electrically conductive layer overlying and electrically connected with the tip of the first one of the wire bonds.

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Номер записи: 40
27-04-2017 дата публикации

SOLDER BUMP PLACEMENT FOR GROUNDING IN FLIP CHIP AMPLIFIERS

Номер: US20170117857A1
Автор: Gill Bharatjeet Singh, McPartlin Michael Joseph
Принадлежит:

Metal pillars are placed adjacent to NPN transistor arrays that are used in the power amplifier for RF power generation. By placing the metal pillars in intimate contact with the silicon substrate, the heat generated by the NPN transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar also forms an electrical ground connection in close proximity to the NPN transistors to function as a grounding point for emitter ballast resistors, which form an optimum electrothermal configuration for a linear SiGe power amplifier. 1. A method to implement an emitter-ballasted amplifier in a flip chip configuration , the method comprising:forming at least one transistor over a silicon substrate;forming a metal pillar over the silicon substrate; andforming a first resistor having a first end in electrical communication with an emitter of the at least one transistor and a second end in electrical communication with the metal pillar, the first resistor configured to provide emitter-ballasting for a radio frequency amplifier that includes the at least one transistor, the metal pillar configured to provide a ground connection for the radio frequency amplifier.2. The method of wherein the metal pillar is configured to provide a flip chip interconnection for the radio frequency amplifier.3. The method of wherein the metal pillar is further configured to provide a thermal path for heat generated by the at least one transistor when the radio frequency amplifier is operating.4. The method of wherein the silicon substrate claim 3 , the metal pillar claim 3 , and the at least one transistor are arranged with respect to one another to provide the thermal path for the heat generated by the at least one transistor.5. The method of further comprising forming inter-level metals and contacts under the metal pillar claim 4 , between the metal pillar and the silicon substrate claim 4 , the inter-level metals forming a part of the thermal path.6. The method of ...

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Номер записи: 41
13-05-2021 дата публикации

Device and Method for UBM/RDL Routing

Номер: US20210143131A1
Автор: Lee Meng-Tsan, Lin Tsung-Shu, WU Wei-Cheng
Принадлежит:

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad. 1. A micro-electromechanical systems (MEMS) package structure , comprising:a circuit layer;a MEMS die on the circuit layer;a conductive pillar having a top surface and disposed on the circuit layer adjacent to the MEMS die;an encapsulant on the circuit layer and encapsulating the MEMS die and the conductive pillar; anda polymer layer disposed on the encapsulant and on the top surface of the conductive pillar, wherein the polymer layer defines a recess that exposes at least a portion of the top surface of the conductive pillar.2. The MEMS package structure of claim 1 , further comprising a seed layer within the conductive pillar.3. The MEMS package structure of claim 1 , wherein a sidewall of the conductive pillar directly contacts the encapsulant.4. The MEMS package structure of claim 1 , wherein the polymer layer comprises polyimide (PI) or polybenzoxazole (PBO).5. The MEMS package structure of claim 1 , further comprising an external connector located within the recess and in physical contact with the top surface of the conductive pillar.6. The MEMS package structure of claim 5 , further comprising a package bonded to the external connector.7. The MEMS package structure ...

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Номер записи: 42
25-04-2019 дата публикации

Package-On-Package (PoP) Structure Including Stud Bulbs

Номер: US20190123027A1
Автор: Cheng Ming-Da, Lii Mirng-Ji, Liu Chung-Shi, Yu Chen-Hua
Принадлежит:

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first surface of a first package;a second pad on a second surface of a second package;a metallic element interposed between the first pad and the second pad, the metallic element comprising a base portion and an elongated portion, the base portion being coupled to the first pad, the elongated portion extending from the base portion toward the second pad, wherein a width of the base portion is greater than a width of the elongated portion;a solder connector in contact with the elongated portion and electrically coupled to the second pad; andan inter-metallic compound (IMC) between the elongated portion and the solder connector.2. The device of claim 1 , wherein the first package comprises a first substrate and a first integrated circuit die attached to the first substrate claim 1 , wherein the second package comprises a second substrate and a second integrated circuit die attached to the second substrate.3. The device of claim 2 , wherein the metallic element is laterally adjacent the first integrated circuit die with the first integrated circuit die and the metallic element being interposed between the first substrate and the second substrate.4. The device of claim 3 , wherein the metallic element extends closer to the second substrate than the first integrated circuit die.5. The device of claim 1 , wherein a height of the metallic element is between about 20 micrometers and about 200 ...

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Номер записи: 43
16-04-2020 дата публикации

SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20200118968A1
Автор: Hung Chih-Ming, OU Jen-Kai, Tsai Tsung-Yueh, WANG MENG-JEN
Принадлежит: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

A semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface; an electronic component disposed on the first surface of the substrate; a sensor disposed adjacent to the second surface of the substrate; an electrical contact disposed on the first surface of the substrate; and a package body exposing a portion of the electrical contact. 1. A semiconductor device , comprising:a substrate having a first surface and a second surface opposite to the first surface;an electronic component disposed on the first surface of the substrate;a sensor disposed adjacent to the second surface of the substrate;an electrical contact disposed on the first surface of the substrate; anda package body exposing a portion of the electrical contact.2. The semiconductor device of claim 1 , wherein the package body comprises a transparent material and covers a surface of the sensor.3. The semiconductor device of claim 1 , wherein a sensing area of the sensor is disposed adjacent to the second surface of the substrate.4. The semiconductor device of claim 1 , wherein the sensor is a light-sensing sensor.5. The semiconductor device of claim 1 , further comprising:a passive electrical component disposed on the first surface of the substrate.6. The semiconductor device of claim 1 , wherein the package body defines a cavity to expose the portion of the electrical contact claim 1 , and a sidewall of the cavity of the package body is spaced apart from a portion of the electrical contact.7. The semiconductor device of claim 1 , wherein a portion of the electrical contact protrudes from a surface of the package body facing away from the first surface of the substrate.8. A semiconductor device claim 1 , comprising:a substrate having a first surface, a second surface opposite to the first surface and a third surface extending between the first surface and the second surface;an electronic component disposed on the first surface of the substrate;a ...

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Номер записи: 44
25-04-2019 дата публикации

FLIP CHIP AMPLIFIER FOR WIRELESS DEVICE

Номер: US20190123693A1
Автор: Gill Bharatjeet Singh, McPartlin Michael Joseph
Принадлежит:

Metal pillars are placed adjacent to transistor arrays in the power amplifiers that can be used in wireless devices. By placing the metal pillars in intimate contact with the silicon substrate and not over a substantial portion of the transistor arrays, the heat generated by the transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar forms a solder bump of a flip chip power amplifier die, which when soldered to a module, further conducts the heat away from the transistor array. 1. A wireless mobile device comprising:an antenna configured to receive and transmit radio frequency signals;a transmit/receive switch configured to pass an amplified radio frequency signal to the antenna for transmission; anda multi-chip module including a flip chip amplifier die that includes at least one emitter-ballasted amplifier configured to amplify a radio frequency input signal and to generate the amplified radio frequency signal, the at least one emitter-ballasted amplifier including at least one transistor formed over and in thermal communication with a silicon substrate, a first resistor in communication with an emitter of the at least one transistor to form at least one emitter-ballasted transistor of the emitter-ballasted amplifier, and a metal pillar formed adjacent to the at least one emitter-ballasted transistor, in electrical communication with the first resistor, and in thermal communication with the silicon substrate, and an output matching network die including an output matching network circuit configured to match an impedance of a fundamental frequency of the amplified radio frequency signal.2. The wireless mobile device of wherein the at least one emitter-ballasted amplifier further includes a second resistor in communication with a base of the at least one emitter-ballasted transistor to provide base resistance.3. The wireless mobile device of wherein claim 1 , when looking down onto the metal pillar and the at least one ...

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Номер записи: 45
11-05-2017 дата публикации

Bump Structure for Yield Improvement

Номер: US20170133346A1
Автор: Chen Hsien-Wei, CHIU Tzu-Wei, Hou Shang-Yun, Jeng Shin-Puu, Teng Hung-An, Wang Tzu-Yu, WU Wei-Cheng
Принадлежит:

A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components. 1. A method of forming a device , the method comprising:forming a first non-flat portion on a first bump;covering the first bump with a first material;forming a second non-flat portion on a second bump, the first non-flat portion having a same number of recesses as the second non-flat portion has projections;covering the second non-flat portion with a second material;aligning the recesses of the first non-flat portion with the projections of the second non-flat portion; andreflowing the first material and the second material, thereby forming a bond between the first non-flat portion and the second non-flat portion.2. The method of claim 1 , wherein the first material is solder and the second material is electroless nickel electroless palladium immersion gold.3. The method of claim 1 , wherein the second non-flat portion comprises a flat shoulder along a periphery.4. The method of claim 1 , wherein forming the second non-flat portion on the second bump comprises:forming a first patterned mask over a passivation layer, the passivation layer having a first opening, the first opening exposing a contact pad, the first patterned mask having a second opening, the contact pad being exposed in the second opening;forming a first conductive element in the second opening, the first conductive element extending above an upper surface of the passivation layer;removing the first patterned mask;forming a second patterned mask over the passivation layer, the second patterned ...

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Номер записи: 46
02-05-2019 дата публикации

CHIP PACKAGE ASSEMBLY WITH ENHANCED INTERCONNECTS AND METHOD FOR FABRICATING THE SAME

Номер: US20190131265A1
Автор: Gandhi Jaspreet Singh
Принадлежит: XILINX, INC.

An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a first substrate containing first circuitry, a first contact pad, a first pillar, a first pillar protection layer, a second substrate containing second circuitry, and a solder ball disposed on the first pillar and electrically and mechanically coupling the first substrate to the second substrate. The first contact pad is disposed on the first substrate and coupled to the first circuitry. The first pillar electrically disposed over the first contact pad. The first pillar protection layer is hydrophobic to solder and is disposed on a side surface of the first pillar. 1. An integrated circuit interconnect comprising:a first substrate containing first circuitry;a first contact pad disposed on the first substrate and coupled to the first circuitry;a first pillar electrically disposed over the first contact pad;a first pillar protection layer disposed on a side surface of the first pillar, the first pillar protection layer being hydrophobic to solder, wherein the first pillar protection layer is copper sulfide;a second substrate containing second circuitry; anda solder ball disposed on the first pillar and electrically and mechanically coupling the first substrate to the second substrate.2. The integrated circuit interconnect of claim 1 , wherein the first pillar protection layer comprises:an inorganic passivation material that is hydrophobic to solder.3. (canceled)4. The integrated circuit interconnect of claim 1 , wherein the first pillar protection layer can be expressed as CuS.5. The integrated circuit interconnect of claim 1 , wherein the first pillar protection layer is at least one of CuS and CuS.6. The integrated circuit interconnect of claim 1 , wherein the first pillar protection layer is not formed on a bottom surface or a top surface of the first pillar.7. The ...

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Номер записи: 47
18-05-2017 дата публикации

Composite solder ball, semiconductor package using the same, semiconductor device using the same and manufacturing method thereof

Номер: US20170136582A1
Автор: Shih-Chin Lin, Tao Cheng, Wen-Sung Hsu
Принадлежит: MediaTek Inc

A semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate.

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Номер записи: 48
26-05-2016 дата публикации

Semiconductor structure and method of manufacturing the same

Номер: US20160148891A1
Автор: An-Tai Xu, Huang-Ting Hsiao, Kuo-Chin Chang, Pei-Haw Tsao
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a semiconductor chip; a substrate facing an active surface of the semiconductor chip; and a conductive bump extending from the active surface of the semiconductor chip toward the substrate, wherein the conductive bump comprises: a plurality of bump segments comprising a first group of bump segments and a second group of bump segments, wherein each bump segment comprises the same segment height in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment comprises a volume defined by the multiplication of the segment height with the average cross-sectional area of the bump segment; wherein the ratio of the total volume of the first group of bump segments to the total volume of the second group of bump segments is between about 0.03 and about 0.8.

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Номер записи: 49
10-06-2021 дата публикации

SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20210175205A1
Автор: Hung Chih-Ming, OU Jen-Kai, Tsai Tsung-Yueh, WANG MENG-JEN
Принадлежит: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

A semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface; an electronic component disposed on the first surface of the substrate; a sensor disposed adjacent to the second surface of the substrate; an electrical contact disposed on the first surface of the substrate; and a package body exposing a portion of the electrical contact. 1. A semiconductor device , comprising:a substrate having a first surface, a second surface opposite to the first surface, and a lateral surface extending between the first surface and the second surface;an electronic component disposed on the first surface of the substrate;a first package body covering the electronic component and the first surface of the substrate; anda second package body covering a lateral surface of the first package body and the lateral surface of the substrate.2. The semiconductor device of claim 1 , wherein the lateral surface of the first package body and the lateral surface of the substrate are substantially coplanar.3. The semiconductor device of claim 1 , wherein the second package body covers the second surface of the substrate.4. The semiconductor device of claim 3 , further comprising:a sensor disposed adjacent to the second surface of the substrate.5. The semiconductor device of claim 1 , further comprising:an electrical contact electrically connected to the substrate and exposed from the first package body.6. The semiconductor device of claim 1 , further comprising:an electronic element disposed proximal to the second surface of the substrate.7. The semiconductor device of claim 6 , wherein the electronic element comprises a sensor.8. The semiconductor device of claim 7 , wherein the sensor is configured for sensing through the second package body.9. The semiconductor device of claim 7 , wherein the second package body covers the sensor.10. The semiconductor device of claim 9 , further comprising:an electrical contact electrically connected to ...

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Номер записи: 50
15-09-2022 дата публикации

ELECTRICALLY CONDUCTIVE PILLAR, BONDING STRUCTURE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING ELECTRICALLY CONDUCTIVE PILLAR

Номер: US20220293543A1
Автор: Yada Makoto, Yamaguchi Ryota
Принадлежит: DIC CORPORATION

An electrically conductive pillar that can bond a base member and a member to be bonded together with high bonding strength with a bonding layer interposed therebetween and a method for manufacturing the same. Specifically, an electrically conductive pillar is composed of a sintered body of metal micro-particles disposed on a base member . The average particle size of the metal micro-particles is less than 1 μm as measured using a small-angle X-ray scattering method. An upper surface of the sintered body has a concave shape recessed on the base member side. The metal micro-particles are preferably made of one or more metals selected from Ag and Cu. 1. An electrically conductive pillar composed of a sintered body of metal micro-particles disposed on a base member ,wherein an average particle size of the metal micro-particles is less than 1 μm as measured using a small-angle X-ray scattering method, andan upper surface of the sintered body has a concave shape recessed on a base member side.2. The electrically conductive pillar according to claim 1 , wherein the metal micro-particles are made of one or more metals selected from Ag and Cu.3. A bonding structure disposed between a base member and a member to be bonded claim 1 , the member to be bonded being disposed opposite to the base member claim 1 , the bonding structure comprising:an electrically conductive pillar composed of a sintered body of metal micro-particles disposed on the base member, an average particle size of the metal micro-particles being less than 1 μm as measured using a small-angle X-ray scattering method, an upper surface of the sintered body having a concave shape recessed on a base member side; anda bonding layer provided along the concave shape of the electrically conductive pillar.4. The bonding structure according to claim 3 , wherein the electrically conductive pillar has a plurality of groove sections that extend from the upper surface toward the base member and has anchoring sections made ...

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Номер записи: 51
31-05-2018 дата публикации

Packaging Structures of Integrated Circuits

Номер: US20180151528A1
Автор: Huang Ru-Ying, Kuo Yian-Liang, TSAI Tsung-Fu, TU Chia-Wei
Принадлежит:

A chip includes a first group of dummy bumps disposed at a top surface of the chip in a first corner of the chip, a second group of dummy bumps disposed at the top surface of the chip in a second corner of the chip, and active bump connectors disposed at the top surface of the chip. The chip also includes an outer seal ring disposed around a periphery of the chip, a first seal ring arrangement disposed around the first group of dummy bumps, and a second seal ring arrangement disposed around the second group of dummy bumps. The first seal ring arrangement and second seal ring arrangement are disposed in dielectric layers underlying the first and second groups of dummy bumps. 1. A device comprising a chip , the chip comprising:a first group of dummy bumps comprising a plurality of dummy bump connectors, the first group of dummy bumps disposed at a top surface of the chip in a first corner of the chip, the first corner being disposed immediately adjacent two intersecting edges of the chip;a second group of dummy bumps comprising one or more dummy bump connectors, the second group of dummy bumps disposed at the top surface of the chip in a second corner of the chip, the second corner being disposed immediately adjacent two intersecting edges of the chip,wherein the first and second groups of dummy bumps are disposed in different corners of the chip;a plurality of active bump connectors disposed at the top surface of the chip, the plurality of active bump connectors and the first and second groups of dummy bumps arranged in a pattern in a top down view of the chip;an outer seal ring disposed around a periphery of the chip;a first seal ring arrangement disposed around the first group of dummy bumps;a second seal ring arrangement disposed around the second group of dummy bumps; anddielectric layers underlying the first and second groups of dummy bumps and the plurality of active bump connectors,wherein the first seal ring arrangement is disposed in the dielectric layers, ...

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Номер записи: 52
11-06-2015 дата публикации

Methods of forming semiconductor die assemblies

Номер: US20150162302A1
Автор: Jaspreet S. Gandhi
Принадлежит: Micron Technology Inc

Semiconductor assemblies, structures, and methods of fabrication are disclosed. A coating is formed on an electrically conductive pillar. The coating, which may be formed from at least one of a silane material and an organic solderability protectant material, may bond to a conductive material of the electrically conductive pillar and, optionally, to other metallic materials of the electrically conductive pillar. The coating may also bond to substrate passivation material, if present, or to otherwise-exposed surfaces of a substrate and a bond pad. The coating may be selectively formed on the conductive material. Material may not be removed from the coating after formation thereof and before reflow of the solder for die attach. The coating may isolate at least the conductive material from solder, inhibiting solder wicking or slumping along the conductive material and may enhance adhesion between the resulting bonded conductive element and an underfill material.

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Номер записи: 53
07-06-2018 дата публикации

STRUCTURES AND METHODS TO ENABLE A FULL INTERMETALLIC INTERCONNECT

Номер: US20180158797A1
Автор: Arvin Charles L., Muzzy Christopher D., Sauter Wolfgang
Принадлежит:

A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process. 1. A method forming an interconnect structure , the method comprising:depositing a first solder bump on a chip;depositing a second solder bump on a laminate, the second solder bump comprising a nickel copper colloid;joining the chip to the laminate;depositing an underfill material around the first solder bump and the second solder bump; andperforming a reflow process at a temperature that is lower than a temperature used to join the chip to the laminate to convert the first solder bump and the second solder bump to an all intermetallic interconnect.2. The method of claim 1 , wherein the nickel copper colloid is surrounded by a nickel shell.3. The method of claim 2 , wherein the nickel copper colloid surrounded by the nickel shell is suspended in a tin-based solder.4. The method of claim 3 , wherein the tin-based solder comprises a tin silver alloy.5. The method of claim 2 , wherein the nickel shell has a thickness of about 0.1 to 0.5 microns.6. The method of claim 1 , wherein the nickel copper colloid is surrounded by a copper shell.7. The method of claim 6 , wherein the nickel copper colloid surrounded by the copper shell is suspended in a tin-based solder.8. The method of claim 6 , wherein the copper ...

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Номер записи: 54
08-06-2017 дата публикации

TRANSIENT INTERFACE GRADIENT BONDING FOR METAL BONDS

Номер: US20170162535A1
Автор: Rinne Glenn
Принадлежит:

A method and apparatus for performing metal-to-metal bonding for an electrical device and an electrical device produced thereby. For example and without limitation, various aspects of this disclosure provide a process that comprises depositing a thin metal layer on a copper pillar and then mating the copper pillar with another copper element. Atoms of the thin metal layer may, for example, form a substitutional solid solution or intermetallic compounds with copper. A concentration gradient is introduced by the thin metal layer, and diffusion at the Cu-Cu interface begins immediately. The thin metal film and the copper may, for example, diffuse until the interface disappears or substantially disappears. 1. A method comprising:providing a first substrate comprising a first metal structure of a first metal;providing a second substrate comprising a second metal structure of the first metal;depositing a layer of a second metal on the first metal structure, wherein the second metal is a metal capable of diffusing into the first metal structure to form a substitutional solid solution with the first metal of the first metal structure;after said depositing, mating the first and second substrates to bring the deposited layer on the first metal structure in direct contact with the second metal structure; andapplying a pressure of less than 100 MPa while diffusion of the layer of the second metal into the first metal structure and into the second metal structure takes place.2. The method of claim 1 , wherein said applying a pressure comprises applying a pressure of less than 10 MPa.3. The method of claim 1 , wherein a time between said depositing and said mating is small enough to result in a concentration gradient between the layer of the second metal and the first metal structure at a time of said mating.4. The method of claim 1 , wherein said depositing a layer comprises:adhering the layer of the second metal to a surface;after said adhering, placing the first metal ...

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Номер записи: 55
18-06-2015 дата публикации

CHIP ELEMENT AND CHIP PACKAGE

Номер: US20150171041A1
Автор: CHEN Po Ching, HWAN Lu-Chen
Принадлежит:

A chip package of the present invention including a substrate, a chip, at least one electrical connecting element and a solder layer is provided. The substrate has at least one contact. The chip is disposed on the substrate and has at least one pad. The electrical connecting element includes a copper bump and an anti-oxidation layer. The copper bump is disposed on the pad. The anti-oxidation layer is disposed on at least part of an outside surface of the copper bump and the outside surface of the copper bump is not connected to the pad. The solder layer is disposed between the copper bump and the contact. The pad is electrically connected to the contact through the electrical connecting element and solder layer. In addition, a chip element of the present invention is also provided. 1. A chip package , comprising:a substrate, having at least one contact;a chip, disposed on the substrate and having at least one pad; a copper bump, disposed on the pad; and', 'an anti-oxidation layer, disposed on at least part of an outside surface of the copper bump, wherein the outside surface of the copper bump is not connected to the pad; and, 'at least one electrical connecting element, comprisinga solder layer, disposed between the copper bump and the contact, wherein the pad is electrically connected to the contact through the electrical connecting element and the solder layer.2. The chip package as claimed in claim 1 , wherein the material of the anti-oxidation layer is tin claim 1 , gold claim 1 , silver claim 1 , or organic solderability preservative.3. The chip package as claimed in claim 1 , wherein the anti-oxidation layer is formed by chemical plating claim 1 , immersion claim 1 , or spray coating.4. The chip package as claimed in claim 1 , wherein the chip is a fingerprint identification chip and has a two-dimensional sensing area claim 1 , and the substrate has a through opening corresponding to the two-dimensional sensing area.5. The chip package as claimed in claim 4 , ...

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Номер записи: 56
24-06-2021 дата публикации

BRASS-COATED METALS IN FLIP-CHIP REDISTRIBUTION LAYERS

Номер: US20210193600A1
Автор: Dadvand Nazila, Manack Christopher Daniel, Pavone Salvatore Frank, SRIDHARAN Vivek Swaminathan, Thompson Patrick Francis
Принадлежит:

In some examples, a package comprises a die and a redistribution layer coupled to the die. The redistribution layer comprises a metal layer, a brass layer abutting the metal layer, and a polymer layer abutting the brass layer. 1. A package , comprising:a die; and a metal layer;', 'a brass layer abutting the metal layer; and', 'a polymer layer abutting the brass layer., 'a redistribution layer coupled to the die, the redistribution layer comprising2. The package of claim 1 , wherein the package is a wafer chip scale package (WCSP).3. The package of claim 1 , wherein the polymer layer comprises a polyimide material.4. The package of claim 1 , wherein the brass layer has a thickness ranging from 0.3 microns to 4.0 microns.5. The package of claim 1 , further comprising an under bump metallurgy (UBM) abutting the brass layer and a solder bump abutting the UBM.6. The package of claim 1 , further comprising an under bump metallurgy (UBM) abutting the metal layer and a solder bump abutting the UBM.7. The package of claim 1 , further comprising a solder bump abutting the brass layer.8. The package of claim 1 , further comprising a solder bump abutting the metal layer and the polymer layer.9. The package of claim 1 , wherein the metal layer is a copper layer.10. The package of claim 1 , further comprising multiple metal plugs communicably coupled to the die and to the polymer layer.11. A package claim 1 , comprising:a die having a bond pad; and a polymer layer abutting the die; and', 'a metal layer at least partially positioned within the polymer layer, the metal layer abutting a brass layer., 'a redistribution layer coupled to the die, the redistribution layer comprising12. The package of claim 11 , wherein the package comprises a wafer chip scale package (WCSP).13. The package of claim 11 , further comprising an under bump metallurgy (UBM) having a first surface abutting a solder bump and a second surface abutting the brass layer.14. The package of claim 11 , further ...

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Номер записи: 57
23-06-2016 дата публикации

Reducing solder pad topology differences by planarization

Номер: US20160181216A1
Автор: Alexander H. Nickel, Jipu Lei, Mooi Guan Ng, Salman Akram, Stefano Schiaffino
Принадлежит: Koninklijke Philips NV

A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a substrate. The chip is provided with solder pads that may have different heights. A dielectric layer is formed between the solder pads. A relatively thick metal layer is plated over the solder pads. The metal layer is planarized to cause the top surfaces of the metal layer portions over the solder pads to be in the same plane and above the dielectric layer. A substantially uniformly thin layer of solder is deposited over the planarized metal layer portions so that the top surfaces of the solder bumps are substantially in the same plane. The chip is then positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.

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Номер записи: 58
22-06-2017 дата публикации

WIRING BOARD AND SEMICONDUCTOR DEVICE

Номер: US20170179022A1
Автор: FUKASE Katsuya, KONDO Hitoshi, Matsumoto Shunichiro
Принадлежит:

A wiring board includes a single-layer insulating layer, and a single-layer interconnect layer embedded in the insulating layer, wherein an entirety of a first surface of the interconnect layer is exposed in a recessed position relative to a first surface of the insulating layer, and a second surface of the interconnect layer is partially exposed in a recessed position relative to a second surface of the insulating layer. 1. A wiring board , comprising:a single-layer insulating layer; anda single-layer interconnect layer embedded in the insulating layer,wherein an entirety of a first surface of the interconnect layer is exposed in a recessed position relative to a first surface of the insulating layer, anda second surface of the interconnect layer is partially exposed in a recessed position relative to a second surface of the insulating layer.2. The wiring board as claimed in claim 1 , wherein the first surface of the interconnect layer is an electronic-component mounting surface claim 1 , and the second surface of the interconnect layer is an external-connection-terminal mounting surface.3. The wiring board as claimed in claim 1 , further comprising a surface treatment film selectively formed on the first surface of the interconnect layer.4. The wiring board as claimed in claim 1 , further comprising a surface treatment film formed on the entirety of the first surface of the interconnect layer claim 1 , wherein a first surface of the surface treatment film is exposed in a recessed position relative to the first surface of the insulating layer.5. A semiconductor device claim 1 , comprising:a wiring board including a single-layer insulating layer and a single-layer interconnect layer embedded in the insulating layer; anda semiconductor chip mounted on a first surface side of the insulating layer,wherein an entirety of a first surface of the interconnect layer is exposed in a recessed position relative to a first surface of the insulating layer, anda second surface of ...

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Номер записи: 59
22-06-2017 дата публикации

Structures to enable a full intermetallic interconnect

Номер: US20170179068A1
Автор: Charles L. Arvin, Christopher D. Muzzy, Wolfgang Sauter
Принадлежит: International Business Machines Corp

A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

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Номер записи: 60
22-06-2017 дата публикации

STRUCTURES AND METHODS TO ENABLE A FULL INTERMETALLIC INTERCONNECT

Номер: US20170179071A1
Автор: Arvin Charles L., Muzzy Christopher D., Sauter Wolfgang
Принадлежит:

A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process. 1. A method forming an interconnect structure , the method comprising:depositing a first solder bump on a chip;depositing a second solder bump on a laminate, the second solder bump comprising a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder;aligning the chip with the laminate;performing a first reflow process to join the chip to the laminate;depositing an underfill material around the first solder bump and the second solder bump; andperforming a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect;wherein depositing the underfill material is performed before or after performing the second reflow process.2. The method of claim 1 , wherein the the nickel shell micrometers or the nickel shell has a thickness of about 0.1 to 0.5 microns.3. The method of claim 1 , wherein the copper shell has a thickness of about 0.5 to about 1.0 microns.4. The method of claim 1 , wherein the tin-based solder of the second solder bump comprises a tin silver alloy.5. The method of claim 1 , wherein the first solder bump comprises a tin silver alloy.6. ...

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Номер записи: 61
02-07-2015 дата публикации

Integrated circuits including copper pillar structures and methods for fabricating the same

Номер: US20150187714A1
Автор: Liu Wei, Mahesh Anant Bhatkar, OSWALD Jens, TAN Juan Boon
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

Integrated circuits including copper pillar structures and methods for fabricating the same are disclosed. In one exemplary embodiment, an integrated circuit includes a last metal layer and a passivation layer disposed over the last metal layer, both the last metal and passivation layers being disposed over an integrated circuit active device on a semiconductor substrate. The integrated circuit further includes a copper pillar structure disposed partially within a first portion of the passivation layer and immediately over the last metal layer. The first portion of the passivation layer is defined by first and second sidewalls of the passivation layer and an upper surface of the last metal layer. The copper pillar structure includes a liner formed along the first and second sidewalls and over the upper surface of the last metal and a copper material within the liner. The copper pillar structure, including both the liner and the copper material within the liner, further extends to a height above an upper surface of the passivation layer.

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Номер записи: 62
13-06-2019 дата публикации

Wafer Level Molded PPGA (Pad Post Grid Array) for Low Cost Package

Номер: US20190181115A1
Автор: Jesus Mennen Belonio, JR., Shou Cheng Eric Hu
Принадлежит: Dialog Semiconductor BV

A method to fabricate a land grid array wafer level chip scale package is described. A silicon die is provided. A dielectric layer is deposited on the silicon die. An opening is etched through the dielectric layer to a metal pad on the silicon die. At least one redistribution layer is formed over the dielectric layer and contacting the metal pad. At least one copper post is formed on the at least one redistribution layer and forms a land grid array. The wafer is sawed partially through on scribe lines to form cuts exposing sides of the silicon die. Thereafter, a molding compound is applied over the at least one redistribution layer and in the cuts wherein the molding compound encapsulates top and side surfaces of the silicon die.

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Номер записи: 63
25-09-2014 дата публикации

TIN-BASED SOLDER BALL AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

Номер: US20140284794A1
Автор: HONG Sung Jae, Kim II Ho, LEE Jae Hong, MOON Jeong Tak
Принадлежит: MK ELECTRON CO., LTD.

A tin (Sn)-based solder ball having appropriate characteristics for electronic products and a semiconductor package including the same are provided. The tin-based solder ball includes about 0.3 to 3.0 wt. % silver (Ag), about 0.4 to 0.8 wt. % copper (Cu), about 0.01 to 0.09 wt. % nickel (Ni), about 0.1% to 0.5 wt. % bismuth (Bi), and balance of tin (Sn) and unavoidable impurities. 1. A tin(Sn)-based solder ball comprising:about 0.3 to 3.0 wt. % silver (Ag);about 0.4 to 0.8 wt. % copper (Cu);about 0.01 to 0.09 wt. % nickel (Ni);about 0.1% to 0.5 wt. % bismuth (Bi); andbalance of tin (Sn) and unavoidable impurities.2. The tin-based solder ball of claim 1 , wherein bismuth is contained at a content of about 0.1 to 0.3 wt. %.3. The tin-based solder ball of claim 1 , wherein bismuth is contained at a content of about 0.2(±0.02) wt. %.4. The tin-based solder ball of claim 1 , wherein nickel is contained at a content of about 0.05(±0.01) wt. %.5. The tin-based solder ball of claim 1 , wherein silver is contained at a content of about 2.5 wt. % claim 1 , copper is contained at a content of about 0.8 wt. % claim 1 , nickel is contained at a content of about 0.05 wt. % claim 1 , and bismuth is contained at a content of about 0.2 wt. %.6. A tin(Sn)-based solder ball comprising silver (Ag) claim 1 , copper (Cu) claim 1 , nickel (Ni) claim 1 , bismuth (Bi) claim 1 , and balance of tin (Sn) and unavoidable impurities claim 1 , the tin-based solder ball from which phosphorus (P) is removed.7. A semiconductor package comprising a tin(Sn)-based solder ball claim 1 ,wherein the tin-based solder ball comprises:about 0.3 to 3.0 wt. % silver (Ag);about 0.4 to 0.8 wt. % copper (Cu);about 0.01 to 0.09 wt. % nickel (Ni);about 0.1% to 0.5 wt. % bismuth (Bi); andbalance of tin (Sn) and unavoidable impurities This application claims the benefit of International Application No. PCT/KR2012/009317, filed Nov. 7, 2012, which is incorporated by reference as if fully set forth.The present invention ...

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Номер записи: 64
27-06-2019 дата публикации

DESIGNS AND METHODS FOR CONDUCTIVE BUMPS

Номер: US20190198472A1
Автор: Balakrishnan Sridhar, BOHR Mark, Dubin Valery M.
Принадлежит:

Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer. 1. (canceled)2. An assembly comprising:a die;a pad disposed on the die, the pad including aluminum;a base layer metal on the pad, the base layer metal including titanium;a copper bump disposed on the base layer metal;a diffusion barrier layer on the copper bump, the diffusion barrier layer including nickel; anda solder layer on the diffusion barrier layer, the solder layer comprising tin, silver and copper.3. The assembly of claim 2 , further comprising a package claim 2 , the package comprising a package layer coupled to the solder layer.4. The assembly of claim 2 , wherein the die is a silicon die.5. The assembly of claim 2 , wherein the base layer metal further includes copper.6. The assembly of claim 2 , wherein the diffusion barrier further includes phosphorous.7. The assembly of claim 2 , wherein the diffusion barrier further includes boron.8. The assembly of claim 2 , wherein the solder layer further includes bismuth.9. The assembly of claim 2 , wherein the solder layer further includes antimony.10. The assembly of claim 2 , wherein the assembly is substantially free of lead. This is a Continuation of application ...

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Номер записи: 65
19-07-2018 дата публикации

Chip integration module, chip package structure, and chip integration method

Номер: US20180204825A1
Автор: Huili Fu, Song Gao
Принадлежит: Huawei Technologies Co Ltd

The present invention provides a chip integration module, including a die, a passive device, and a connecting piece, where the die is provided with a die bonding portion, the passive device is provided with a passive device bonding portion, the die bonding portion of the die and the passive device bonding portion of the passive device are disposed opposite to each other, and the connecting piece is disposed between the die bonding portion and the passive device bonding portion and is connected to the die bonding portion and the passive device bonding portion. The chip integration module of the present invention achieves easy integration and has low costs. Moreover, a path connecting the die to the passive device becomes shorter, which can improve performance of the passive device. The present invention further discloses a chip package structure and a chip integration method.

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Номер записи: 66
29-07-2021 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20210233882A1
Автор: KAGEYAMA Satoshi, TANAKA Bungo, Wada Keiji
Принадлежит:

A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer. 1. A semiconductor device comprising:an insulating layer;a barrier electrode layer formed over a part of a region of a surface of the insulating layer;a bonding pad formed on a principal surface of the barrier electrode layer,wherein the bonding pad has three layers which include a Cu electrode layer that includes a metal composed mainly of copper, a nickel layer, and a surface metal layer, those layers are formed from bottom to top; andwherein a surface of the surface metal layer is fully exposed from the insulating layer for connecting a bonding wire on the surface, a thickness of the surface metal layer is thinner than a thickness of the nickel layer, and a thickness of the nickel layer is thinner than a thickness of the Cu electrode layer.2. The semiconductor device according to claim 1 , wherein a width of the surface metal layer is wider than a width of the Cu electrode layer in a sectional view.3. The semiconductor device according to claim 1 , wherein a curved portion is formed around a bottom of the Cu electrode layer to make an upper portion of the Cu electrode layer wider.4. The semiconductor device according to claim 3 , wherein an insulating material is intruding to the curved portion so that part of the Cu electrode layer is on the insulating material.5. The semiconductor device according to claim 1 , wherein a thickness of the insulating layer is thicker than a thickness of the barrier electrode layer.6. The semiconductor device according to claim 1 , wherein the Cu electrode layer and the insulating ...

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Номер записи: 67
04-07-2019 дата публикации

BUMP PLANARITY CONTROL

Номер: US20190206820A1
Автор: GUEVARA, III Rafael Jose Lizares
Принадлежит:

A method for manufacturing an integrated circuit package includes depositing a first layer of metal at a location of a first metal post that is for connecting an IC die to an external circuit. The method also includes depositing a second layer of metal at the location of the first metal post, and a first layer of metal at a location of a second metal post that is for connecting the IC die to an external circuit. 1. A method for manufacturing an integrated circuit (IC) package , comprising:depositing a first layer of metal at a location of a first metal post that is capable of electrically connecting to an IC die; andconcurrently depositing a second layer of metal on the first layer of metal, and the first layer of metal at a location of a second metal post that is capable of electrically connecting to the IC die.2. The method of claim 1 , wherein claim 1 , after depositing the second layer of metal claim 1 , a height of the first metal post is substantially the same as a height of the second metal post claim 1 , the height of the first metal post and the height of the second metal post including all the layers of metal deposited on each of the first metal post and the second metal post.3. The method of claim 1 , further comprising claim 1 , prior to depositing the first layer of metal claim 1 , applying a layer of photoresist material to the location of the first metal post and the location of the second metal post.4. The method of claim 3 , further comprising:removing the photoresist from the location of the first metal post; andretaining the photoresist at the location of the second metal post.5. The method of claim 1 , further comprising claim 1 , after depositing the first layer of metal claim 1 , applying a layer of photoresist material to the location of the first metal post and the location of the second metal post.6. The method of claim 5 , further comprising:removing the photoresist from the location of the first metal post; andremoving the photoresist from ...

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Номер записи: 68
05-08-2021 дата публикации

LOW TEMPERATURE HYBRID BONDING STRUCTURES AND MANUFACTURING METHOD THEREOF

Номер: US20210242166A1
Автор: HUANG SHUN-PING
Принадлежит:

Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. The fill layer is composed of noble metal (such as copper) and active metal (such as Zn). Then the fill metal layer is turned into a metal alloy after annealing. A dealloying is performed to the metal alloy to remove the active metal from the metal alloy while the noble metal remains to self-assemble into porous (nanoporous) structure metal. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using dielectric-to-dielectric direct bonding techniques, with the fill nanoporous metal layer in the recesses in one of the first and second interconnect structures. After the following batch annealing, the fill nanoporous metal layer turns into pure bulk metal same as conductive interconnect structures due to the heat expansion of conductive interconnect structures and nanoporous metal densification. 1. A method of bonding a pair of semiconductor structures together , the method comprising:providing a pair of semiconductor structures comprising corresponding dielectric layers and corresponding copper features arranged in the dielectric layers, wherein the pair of semiconductor structures comprises a first semiconductor structure and a second semiconductor structure;arranging a precursor alloy on the copper feature of the first semiconductor structure, wherein the precursor alloy comprising copper and an active metal;performing a vacuum thermal dealloying on the precursor alloy to remove the active metal from the precursor alloy so that the remnants of the precursor alloy self-organize into a porous copper fill layer;arranging the porous copper fill layer between the two copper features and bonding the two dielectric layers of the two semiconductor structures together; andperforming an anneal to ...

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Номер записи: 69
04-08-2016 дата публикации

Chip Scale Package

Номер: US20160225733A1
Автор: Wilcoxen Duane Thomas
Принадлежит:

A novel semiconductor chip scale package encapsulates a semiconductor chip on the device side, the non-device side, and the four edges with a mold compound. One process to fabricate such a semiconductor chip scale package involves forming trenches on the surface of a wafer around the chips and filling the trenches and covering the device side of the chips with a first mold compound. The wafer is subsequently thinned from the non-device side until the bottom portion of the trenches and the mold compound in the portion are also removed. The thinning process creates a plane that contains the back side of the chips and the mold compound exposed in the trench. This plane is subsequently covered with a second mold compound. 1. A semiconductor device package , comprising:a semiconductor chip having a device side with metallic contact bumps thereon, a non-device side opposite the device side, and four edges;a first layer of mold compound covering the four edges and the device side of the chip;a second layer of mold compound covering the non-device side of the chip; andthe first layer of mold compound joining the second layer of mold compound at a plane that is coplanar to the non-device side of the chip.2. The semiconductor device package of claim 1 , in which a top portion of the contact bumps on the device side of the semiconductor chip protrude from the first layer of mold compound.3. The semiconductor device package of claim 2 , in which the protruding portion of the contact bumps is covered with a metallic film containing gold.4. The semiconductor device package of claim 3 , in which the contact bums nickel.5. The semiconductor device package of claim 1 , in which the first layer of mold compound contains filler particles.6. The semiconductor device package of claim 5 , further comprising partially ground filler particles near the plane where the first layer and the second layer of mold compound meet.7. The semiconductor of claim 6 , in which the partially ground ...

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Номер записи: 70
02-08-2018 дата публикации

METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURE FOR JOINING WAFERS AND RESULTING STRUCTURE

Номер: US20180218991A1
Автор: Atanasova Tanya A., Farooq Mukta G.
Принадлежит:

The disclosure is directed to an integrated circuit structure for joining wafers and methods of forming same. The IC structure may include: a metallic pillar over a substrate, the metallic pillar including an upper surface; a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and a solder material over the upper surface of the metallic pillar, the solder material being within and constrained by the wetting inhibitor layer. The sidewall of the metallic pillar may be free of the solder material. The method may include: forming a metallic pillar over a substrate, the metallic pillar having an upper surface; forming a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and forming a solder material over the upper surface of the metallic pillar within and constrained by the wetting inhibitor layer. 8. A method of forming an integrated circuit structure for joining wafers , the method comprising:forming a metallic pillar over a substrate, the metallic pillar having an upper surface;forming a wetting inhibitor layer over the upper surface of the metallic pillar;patterning a photoresist over the wetting inhibitor layer such that a first portion of the wetting inhibitor layer about the periphery of the upper surface of the metallic pillar is covered and a second portion of the wetting inhibitor layer over a central portion of the metallic pillar is exposed;removing the exposed second portion of the wetting inhibitor layer to expose the central portion of the metallic pillar thereunder; andremoving the photoresist to expose the first portion of the wetting inhibitor layer about the periphery of the upper surface of the metallic pillar; andforming a solder material over the upper surface of the metallic pillar within and constrained by the first portion of the wetting inhibitor layer about the periphery of the upper surface of the metallic pillar.9. (canceled)101. The method of claim , wherein the forming ...

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Номер записи: 71
02-07-2020 дата публикации

PACKAGED SEMICONDUCTOR DEVICE WITH ELECTROPLATED PILLARS

Номер: US20200211990A1
Автор: Clarina, Escano Maricel Fabia, Esquejo Jovenic Romero, JR. Armando Tresvalles, Mallari Arvin Cedric Quiambao
Принадлежит:

In a described example, a device includes an overcoat layer covering an interconnect; an opening in the overcoat layer exposing a portion of a surface of the interconnect; a stud on the exposed portion of the surface of the interconnect in the opening; a surface of the stud approximately coplanar with a surface of the overcoat layer; and a conductive pillar covering the stud and covering a portion of the overcoat layer surrounding the stud, the conductive pillar having a planar and un-dished surface facing away from the stud and the overcoat layer. 1. A device , comprising:an overcoat layer covering an interconnect;an opening in the overcoat layer exposing a portion of a surface of the interconnect;a stud on the exposed portion of the surface of the interconnect in the opening;a surface of the stud approximately coplanar with a surface of the overcoat layer; anda conductive pillar covering the stud and covering a portion of the overcoat layer surrounding the stud, the conductive pillar having a planar and un-dished surface facing away from the stud and the overcoat layer.2. The device of claim 1 , wherein the device is a semiconductor device.3. The device of claim 1 , wherein the device is a circuit board.4. The device of claim 1 , wherein the interconnect is one selected from a group consisting essentially of: aluminum claim 1 , tungsten claim 1 , titanium/tungsten claim 1 , copper and alloys thereof.5. The device of claim 1 , wherein the conductive pillar comprises copper.6. The device of claim 5 , wherein the conductive pillar comprises electroplated copper.7. The device of claim 1 , wherein the conductive pillar comprises an electroplated material that is one selected from a group consisting essentially of: silver claim 1 , gold claim 1 , nickel claim 1 , palladium claim 1 , and copper.8. The device of claim 1 , wherein the stud comprises copper.9. The device of claim 8 , wherein the stud comprises electroplated copper.10. The device of claim 8 , wherein the ...

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Номер записи: 72
20-08-2015 дата публикации

Method of Manufacturing Semiconductor Device and Semiconductor Device Manufacturing Apparatus

Номер: US20150235984A1
Автор: Fumiki Kato, Lai Na Ma, Masahiro Aoyagi, Motohiro Suzuki, Naoya Watanabe, Shunsuke Nemoto, Thanh Tung Bui
Принадлежит: National Institute of Advanced Industrial Science and Technology AIST

A method of manufacturing a semiconductor device according to the present invention comprises: a bump forming step of forming a bump electrode 100 on a semiconductor chip 1, the bump electrode 100 protruding in a substantially conical shape; a pad forming step of forming a pad electrode 200 on a substrate 10, the pad electrode 200 having a recess 210 with inner lateral surfaces thereof defining a substantially pyramidal shape or a prism shape; a pressing step of pressing the bump electrode 100 and the pad electrode 200 in a direction which brings them closer to each other, with the bump electrode 100 being inserted in the recess 210 so that the central axis of the bump electrode 100 and the central axis of the recess 210 coincide with each other; and an ultrasonic joining step of joining the bump electrode 100 and the pad electrode 200 by vibrating at least one of the bump electrode 100 and the pad electrode 200 using ultrasonic waves.

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Номер записи: 73
11-08-2016 дата публикации

Contact bumps methods of making contact bumps

Номер: US20160233188A1
Автор: Carsten Nieland, Frank Kriebel
Принадлежит: SMARTRAC TECHNOLOGY GMBH

Contact bumps between a contact pad and a substrate can include a rough surface that can mate with the material of the substrate. The rough surface can enhance the bonding strength of the contacts, for example, against shear and tension forces, especially for flexible systems such as smart cards.

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Номер записи: 74
19-08-2021 дата публикации

Semiconductor device and method of fabricating the same

Номер: US20210257294A1
Автор: Donghyeon Jang, Hyunsoo Chung, Inyoung LEE, Jinkuk BAE
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a semiconductor substrate, a conductive pad disposed on the semiconductor substrate, and a pillar pattern disposed on the conductive pad. The semiconductor device further includes a solder seed pattern disposed on the pillar pattern, and a solder portion disposed on the pillar pattern and the solder seed pattern. A first width of the solder seed pattern is less than a second width of a top surface of the pillar pattern.

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Номер записи: 75
18-08-2016 дата публикации

Planarity-tolerant reworkable interconnect with integrated testing

Номер: US20160240513A1
Автор: Bing Dang, John U. Knickerbocker, Steven L. Wright, Yang Liu, Yu Luo
Принадлежит: International Business Machines Corp

A structure includes an electrical interconnection between a first substrate including a plurality of protrusions and a second substrate including a plurality of solder bumps, the plurality of protrusions includes sharp tips that penetrate the plurality of solder bumps, and a permanent electrical interconnection is established by physical contact between the plurality of protrusions and the plurality of solder bumps including a metallurgical joint.

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Номер записи: 76
16-08-2018 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20180233468A1
Автор: KAMOTO Taku, MIGITA Tatsuo, Watanabe Shinya
Принадлежит:

According to one embodiment, a semiconductor device includes a first semiconductor substrate having a first wiring electrode on a first surface thereof, a first protective layer on the semiconductor substrate, having an opening therethrough at the location of first wiring electrode, a first bump electrode in the opening of the first protective layer, the first bump electrode including a base overlying the wiring electrode and an opposed bump receiving surface, and a first bump comprising a bump diameter of 30 μm or less connected to the first bump electrode. The width of the base of the first bump electrode within the opening is equal to or less than 1.5 times the thickness of the first protective layer. 1. A semiconductor device comprising:a first semiconductor substrate having a first wiring electrode on a first surface thereof;a first protective layer on the semiconductor substrate, having an opening therethrough at the location of first wiring electrode;a first bump electrode in the opening of the first protective layer, the first bump electrode including a base overlying the wiring electrode and an opposed bump receiving surface; anda first bump comprising a bump diameter of 30 μm or less connected to the first bump electrode,wherein the width of the base of the first bump electrode within the opening is equal to or less than 1.5 times the thickness of the first protective layer.2. The semiconductor device according to claim 1 , wherein the width of the base of the first bump electrode within the opening is equal to or less than the film thickness of the first protective layer.3. The semiconductor device according to claim 1 , wherein the first bump electrode is also located on the first protective layer claim 1 , and the film thickness of the first bump electrode on the first protective layer is 3 μm or less.4. The semiconductor device according to claim 1 , further comprising a plurality of bumps on the first surface claim 1 , wherein the distance between the ...

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Номер записи: 77
25-07-2019 дата публикации

Semiconductor devices

Номер: US20190229081A1
Автор: chao-yi Wang, Chen-Shien Chen, Cheng-Lung Yang, Chien-Hung Kuo, Chin-Yu Ku, Ching-Hui Chen, Hon-Lin Huang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Semiconductor devices are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump. The spacer surrounds the bump and disposed between the etching stop layer and the bump.

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Номер записи: 78
16-07-2020 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20200227368A1
Автор: WU TUNG-JIUN
Принадлежит:

A semiconductor structure includes a substrate; a conductive pad disposed over the substrate; a passivation disposed over the substrate and covering a portion of the conductive pad; a bump pad disposed over the conductive pad and the passivation; a conductive bump including a conductive pillar disposed over the bump pad and a soldering member disposed over the conductive pillar; and a dielectric member disposed over the passivation and surrounding the conductive pillar. 1. A semiconductor structure , comprising:a substrate;a conductive pad disposed over the substrate;a passivation disposed over the substrate and covering a portion of the conductive pad;a bump pad disposed over the conductive pad and the passivation;a conductive bump including a conductive pillar disposed over the bump pad and a soldering member disposed over the conductive pillar; anda dielectric member disposed over the passivation and surrounding the conductive pillar.2. The semiconductor structure of claim 1 , wherein the soldering member is exposed from the dielectric member.3. The semiconductor structure of claim 1 , wherein the dielectric member is in contact with the bump pad and the conductive pillar.4. The semiconductor structure of claim 1 , wherein a first interface is disposed between the dielectric member and the passivation.5. The semiconductor structure of claim 4 , wherein material of the dielectric member is different from material of the passivation.6. The semiconductor structure of claim 1 , wherein a second interface between the soldering member and the conductive pillar is substantially coplanar with an exposed surface of the dielectric member.7. The semiconductor structure of claim 6 , wherein a third interface between the conductive pillar and the dielectric member is substantially orthogonal to the second interface between the soldering member and the conductive pillar.8. The semiconductor structure of claim 1 , wherein the conductive pillar is enclosed by the bump pad claim ...

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Номер записи: 79
10-09-2015 дата публикации

COMBINED SUBSTRATE

Номер: US20150255433A1
Автор: Adachi Takema, DAIZO Tomoya, FURUSAWA Takeshi, HIRABAYASHI Tomoyoshi, ITO Yuki, Nakamura Wataru, YOSHIKAWA Yuki
Принадлежит: IBIDEN CO., LTD.

A combined substrate includes a first substrate having multiple first metal posts, a second substrate having multiple second metal posts such that the second metal posts are positioned to oppose the first metal posts, respectively, and multiple solder structures interposed between the first metal posts and the second metal posts, respectively. The first metal posts and/or the second metal posts have recessed surfaces formed such that the solder structures are formed on the recessed surfaces, respectively. 1. A combined substrate , comprising:a first substrate having a plurality of first metal posts;a second substrate having a plurality of second metal posts such that the plurality of second metal posts is positioned to oppose the plurality of first metal posts, respectively; anda plurality of solder structures interposed between the plurality of first metal posts and the plurality of second metal posts, respectively,wherein at least one of the plurality of first metal posts and the plurality of second metal posts has a plurality of recessed surfaces configured such that the plurality of solder structures is formed on the plurality of recessed surfaces, respectively.2. A combined substrate according to claim 1 , wherein the plurality of first metal posts and the plurality of second metal posts have the plurality of recessed surfaces.3. A combined substrate according to claim 1 , wherein each of the first metal posts and the second metal posts comprises a metal post comprising copper plating material.4. A combined substrate according to claim 1 , wherein each of the first metal posts has a diameter which is greater than a diameter of each of the second metal posts.5. A combined substrate according to claim 1 , wherein each of the first metal posts has an axial length which is different from an axial length of each of the second metal posts.6. A combined substrate according to claim 1 , wherein one of the plurality of first metal posts and the plurality of second posts ...

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Номер записи: 80
01-08-2019 дата публикации

VISIBILITY EVENT NAVIGATION METHOD AND SYSTEM

Номер: US20190236964A1
Автор: JENKINS Barry L.
Принадлежит: PRIMAL SPACE SYSTEMS, INC.

A method of visibility event navigation includes receiving, via processing circuitry of a client device, a first visibility event packet from a server, the first visibility event packet including information representing 3D surface elements of an environmental model that are occluded from a first viewcell and not occluded from a second viewcell, the first and second viewcells representing spatial regions of a specified navigational route within a real environment modeled by the environmental model. The method also includes acquiring, surface information representing the visible surfaces of the real environment at a sensor and determining, a position in the real environment by matching the surface information to the visibility event packet information. The method further includes transmitting, the position from the client device to the server and receiving a second visibility event packet from the server if the at least one position is within the specified navigational route. 1receiving, via processing circuitry of a client device, at least one visibility event packet of the one or more visibility event packets from the server;detecting, via the circuitry, surface information representing one or more visible surfaces of the real environment at a sensor in communication with the client device;calculating, via the circuitry, at least one position of the client device in the real environment by matching the surface information to the visibility event packet information corresponding to a first visibility event packet of the one or more visibility event packets;transmitting, via the circuitry, the at least one position from the client device to the server; andreceiving, via the circuitry, at least one second visibility event packet of the one or more visibility event packets when the at least one position is within the navigational route at the client device from the server.. A method of visibility event navigation, including one or more visibility event packets located ...

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Номер записи: 81
01-08-2019 дата публикации

Coaxial-Interconnect Structure for a Semiconductor Component

Номер: US20190237418A1
Автор: Lijuan Zhang, Marc Jacobs
Принадлежит: MARVELL WORLD TRADE LTD

The present disclosure describes a coaxial-interconnect structure that is integrated into a semiconductor component and methods of forming the coaxial-interconnect structure. The coaxial interconnect-structure, which electrically couples circuitry of an integrated-circuit (IC) die to traces of a packaging substrate, comprises a signal core elongated about an axis, a ground shield elongated about the axis, and an insulator disposed between the signal core and the ground shield.

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Номер записи: 82
23-07-2020 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20200235064A1
Автор: KAGEYAMA Satoshi, TANAKA Bungo, Wada Keiji
Принадлежит:

A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer. 1. A semiconductor device comprising:an insulating layer;a TiN layer formed over a part of a region of a surface of the insulating layer;a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the TiN layer; anda nickel layer formed on the Cu electrode layer,wherein a width of the nickel layer is wider than a width of the Cu electrode layer in a sectional view.2. The semiconductor device according to claim 1 , wherein a surface metal layer is formed on the nickel layer.3. The semiconductor device according to claim 2 , wherein a thickness of the surface metal layer is thinner than a thickness of the nickel layer.4. The semiconductor device according to claim 3 , wherein a width of the surface metal layer is wider than a width of the Cu electrode layer in a sectional view.5. The semiconductor device according to claim 4 , wherein a curved portion is formed around a bottom of the Cu electrode layer to make an upper portion of the Cu electrode layer wider.6. The semiconductor device according to claim 5 , wherein an insulating material is intruding to the curved portion so that part of the Cu electrode layer is on the insulating material.7. The semiconductor device according to claim 6 , wherein a thickness of the insulating layer is thicker than a thickness of the TiN layer.8. The semiconductor device according to claim 7 , wherein the Cu electrode layer and the insulating layer are connected by the TiN layer disposed between the Cu electrode layer and the ...

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Номер записи: 83
30-08-2018 дата публикации

GRID ARRAY CONNECTION DEVICE AND METHOD

Номер: US20180247908A1
Автор: Gurumurthy Charavanakumara, Selvamuniandy Tamil Selvy, Sim Kian Sin, Tai Siew Fong, Toyama Munehiro
Принадлежит:

A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results. 1. An electronic device comprising:a chip package that includes a chip connection structure, to mount the chip package on a circuit board, wherein the chip connection structure includes:a first layer that includes nickel (Ni); anda second layer that includes palladium (Pd), disposed on the first layer, wherein the second layer comprises a substantially amorphous structure.2. The electronic device of claim 1 , further comprising a metallic connection structure provided on a side of the chip package that is to be mounted on the circuit board claim 1 , wherein the first layer is coupled with the metallic connection structure.3. The electronic device of claim 2 , wherein the metallic connection structure comprises a pad.4. The electronic device of claim 1 , wherein the second layer further comprises a substantially non-porous structure claim 1 , to prevent corrosion of the first layer.5. The electronic device of claim 1 , further comprising a third layer disposed on the second layer claim 1 , wherein the third layer has a determined thickness.6. The electronic device of claim 5 , wherein the third layer comprises gold claim 5 , wherein the determined thickness of the third layer is between 50 and 80 μm.7. The electronic device of claim 1 , wherein the metallic connection structure comprises copper (Cu).8. The electronic device of claim 1 , wherein the second layer further includes phosphorus (P).9. The electronic device of claim 1 , ...

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Номер записи: 84
08-09-2016 дата публикации

EPHEMERAL BONDING

Номер: US20160257861A1
Автор: BAI Zhifeng, Gallagher Michael K., OLIVER Mark S.
Принадлежит:

Compositions containing an adhesive material, a release additive and a copper passivation agent are suitable for temporarily bonding two surfaces, such as a semiconductor substrate active side and a carrier substrate. These compositions are useful in the manufacture of electronic devices where a temporary bonding of a component to a substrate having a copper surface is desired. 1. A method of releasably attaching a semiconductor substrate to a carrier substrate comprising:(a) providing a semiconductor substrate having a front side and a back side, the front side having a copper surface;(b) providing a carrier substrate having an attachment surface;(c) disposing a temporary bonding composition comprising a curable adhesive material, a release additive, and a copper passivation agent between the front side of the semiconductor substrate and the attachment surface of the carrier substrate, wherein the release additive is chosen from polyether compounds, polyetheramine compounds, and mixtures thereof;(d) curing the adhesive material to provide a temporary bonding layer disposed between the front side of the semiconductor substrate and the attachment surface of the carrier substrate; wherein the temporary bonding layer adjacent to the attachment surface of the carrier substrate comprises a relatively lower amount of the release additive and the temporary bonding layer adjacent to the front side of the semiconductor substrate comprises a relatively higher amount of the release additive;(e) performing an operation on the back side of the semiconductor substrate; and(f) separating the front side of the semiconductor substrate from the temporary bonding layer.2. The method of wherein the curable adhesive material is chosen from polyarylene oligomers claim 1 , cyclic-olefin oligomers claim 1 , arylcyclobutene oligomers claim 1 , vinyl aromatic oligomers claim 1 , and mixtures thereof.3. (canceled)4. The method of wherein the polyether compounds are chosen from polyalkylene ...

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Номер записи: 85
15-09-2016 дата публикации

COMPOSITE SOLDER BALL, SEMICONDUCTOR PACKAGE USING THE SAME, SEMICONDUCTOR DEVICE USING THE SAME AND MANUFACTURING METHOD THEREOF

Номер: US20160263709A1
Автор: Cheng Tao, HSU Wen-Sung, LIN Shih-Chin
Принадлежит:

A semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate. 1. A composite solder ball , comprising:a core;an encapsulating layer; anda barrier layer disposed between the core and the encapsulating layer;wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer.2. The composite solder ball as claimed in claim 1 , wherein the encapsulating layer has an outer diameter ranging between 120 micrometers and 130 micrometers.3. The composite solder ball as claimed in claim 1 , wherein the core is made of tin claim 1 , bismuth or a combination thereof.4. The composite solder ball as claimed in claim 1 , wherein the core is made of a material in absence of copper.5. The composite solder ball as claimed in claim 1 , wherein the encapsulating layer is made of an alloy material including at least two of tin claim 1 , silver and copper.6. A semiconductor package claim 1 , comprising:a first substrate;a second substrate;{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a composite solder ball as claimed in , disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate; and'}a first semiconductor component, disposed between ...

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Номер записи: 86
24-09-2015 дата публикации

Semiconductor Device and Method of Forming 3D Dual Side Die Embedded Build-Up Semiconductor Package

Номер: US20150270237A1
Автор: Chi HeeJo, Cho NamJu, Shin HanGil
Принадлежит: STATS CHIPPAC, LTD.

A semiconductor device has a plurality of semiconductor die. A substrate is provided with bumps disposed over the substrate. A first prefabricated insulating film is disposed between the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The bumps include a copper core encapsulated within copper plating. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The substrate includes a conductive layer formed in the substrate and coupled to the bumps. The semiconductor die is disposed between the bumps of the substrate. The bumps and the semiconductor die are embedded within the first prefabricated insulating film. A portion of the first prefabricated insulating film is removed to expose the bumps. The bumps electrically connect the substrate to the interconnect structure. 1. A method of making a semiconductor device , comprising:providing a plurality of semiconductor die;providing a substrate including bumps disposed over the substrate;disposing a first prefabricated insulating film between the semiconductor die and substrate; andforming an interconnect structure over the semiconductor die and first prefabricated insulating film.2. The method of claim 1 , further including:providing a copper core; anddisposing a conductive material around the copper core to form the bumps.3. The method of claim 1 , wherein the first prefabricated insulating film includes glass cloth claim 1 , glass fiber claim 1 , or glass fillers.4. The method of claim 1 , further including forming a conductive layer in the substrate and coupled to the bumps.5. The method of claim 1 , further including disposing the semiconductor die between the bumps of the substrate with the bumps and semiconductor die embedded within the first prefabricated insulating film.6. The method of claim 1 , further including disposing a second prefabricated insulating film over the first ...

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Номер записи: 87
24-09-2015 дата публикации

FLIP CHIP INTERCONNECTION WITH REDUCED CURRENT DENSITY

Номер: US20150270241A1
Автор: Beach Robert, Cao Jianjun, Kolluri Seshadri, Nakata Alana, Strittmatter Robert
Принадлежит:

A method and system for electrically connect a semiconductor device with a flip-chip form factor to a printed circuit board. An exemplary embodiment of the method comprises: aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, and, applying a supply current only directly to a buried layer of the first copper and not directly to the layer which is nearest the device, such that no current is sourced to the device through the layer nearest the device. 1. A method of connecting a device to external circuitry comprising:aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, wherein the first copper contact comprises a plurality of electrically connected layers; and,applying a source current only directly to a layer of the first copper contact other than the layer nearest the solder contacts, such that no current is sourced to the device through the layer nearest the device.2. The method of claim 1 , wherein the device has a flip chip form factor.3. The method of claim 2 , wherein the external circuitry is a part of a printed circuit board comprising the plurality of electrically connected layers.4. The method of claim 2 , wherein the device is a semiconductor device.5. The method of claim 1 , wherein the first copper contact and the second copper contact are each comprised of multiple copper layers electrically connected by metal filled vias.6. The method of claim 1 , wherein the first copper contact and second copper contact each have more than two layers.7. A system for electrically connecting a device to external circuitry comprising:at least one solder contact electrically connected to the device;at least one copper contact electrically connected to the external circuitry and the solder contact of the device, the copper contact being formed of multiple layers, wherein a first layer of the multiple layers is closest to the device and ...

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Номер записи: 88
15-08-2019 дата публикации

PACKAGE STRUCTURE AND METHOD FOR CONNECTING COMPONENTS

Номер: US20190252345A1
Автор: Chang Tao-Chih, Lin Yu-Min, LO Wei-Chung
Принадлежит: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

A package structure and a method for connecting components are provided, in which the package includes a first substrate including a first wiring and at least one first contact connecting to the first wiring; a second substrate including a second wiring and at least one second contact connecting to the second wiring, the at least one first contact and the at least one second contact partially physically contacting with each other or partially chemically interface reactive contacting with each other; and at least one third contact surrounding the at least one first contact and the at least one second contact. The first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact. 1. A package structure , comprising:a first substrate, comprising a first wiring and at least one first contact, wherein the at least one first contact is electrically connected to the first wiring;a second substrate, comprising a second wiring and at least one second contact, wherein the at least one second contact is electrically connected to the second wiring, and the at least one first contact and the at least one second contact partially physically contact with each other or partially chemically interface reactive contact with each other; andat least one third contact, surrounding the at least one first contact and the at least one second contact,wherein the first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact.2. The package structure according to claim 1 , wherein the at least one third contact is disposed between the at least one first contact and the at least one second contact.3. The package structure according to claim 1 , further comprising an intermetallic compound (IMC) or an alloy solid solution formed after the at least one first contact contacts the at least one ...

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Номер записи: 89
01-10-2015 дата публикации

MANUFACTURE OF COATED COPPER PILLARS

Номер: US20150279797A1
Автор: BECK Thomas, STEINBERGER Gerhard, WALTER Andreas
Принадлежит:

The present invention relates to a method for forming a copper pillar on a semiconducting substrate, the copper pillar having an underbump metallization area comprising a metal less noble than copper and optionally a solder bump on the top portion, and having a layer of a second metal selected from tin, tin alloys, silver, and silver alloys deposited onto the side walls of said copper pillar. A layer of a first metal which is more noble than copper is deposited onto the entire outer surface of the copper pillar prior to deposition of the second metal layer. The layer of a second metal then has at least a reduced number of undesired pin-holes and serves as a protection layer for the underlying copper pillar. 1. A method for manufacture of coated copper pillars on a semiconducting substrate comprising , in this order , the steps ofa. providing a semiconducting substrate with an array of copper pillars, the copper pillars having an underbump metallization area comprising a metal or metal alloy less noble than copper, and a solder cap layer attached to the top portion of the copper pillars,b. depositing a first metal layer comprising a metal which is more noble than copper onto the entire outer surface of the copper pillars, andc. depositing a second metal layer selected from the group consisting of tin, tin alloys, silver, and silver alloys by immersion-type plating onto the first metal layer.2. The method for manufacture of coated copper pillars according to wherein the semiconducting substrate is a silicon substrate.3. The method for manufacture of coated copper pillars according to wherein the solder cap layer comprises tin.4. The method for manufacture of coated copper pillars according to wherein the metal which is more noble than copper is selected from the group consisting of silver claim 1 , palladium claim 1 , platinum claim 1 , rhodium claim 1 , ruthenium claim 1 , gold and alloys thereof with the proviso that silver and silver alloys are not selected as ...

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Номер записи: 90
01-10-2015 дата публикации

Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment

Номер: US20150279801A1
Автор: Haruki Ito
Принадлежит: Seiko Epson Corp

A semiconductor device is provided with a plurality of protrusions which are made of a resin and which protrude higher than electrodes, and conductive layers which are electrically connected to the electrodes and which cover the top surfaces of the protrusions. A method for manufacturing the semiconductor device includes a step of applying a layer of the resin to the semiconductor device except for the electrodes, a step of patterning the conductive layers on the electrodes and the layer of the resin in accordance with the protrusions, and a step of removing the layer of the resin located between the conductive layers by the use of the patterned conductive layers as masks so as to form the protrusions.

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Номер записи: 91
22-09-2016 дата публикации

ELECTRONIC DEVICE, AND MANUFACTURING METHOD OF ELECTRONIC DEVICE

Номер: US20160276300A1
Автор: MATSUO Yoshihide, YOSHIIKE Masashi
Принадлежит:

An electronic device includes a drive substrate (a pressure chamber substrate and a vibration plate) including a piezoelectric element and electrode wirings related to driving of the piezoelectric element formed thereon, and a sealing plate bonded thereto, the electrode wirings are made of wiring metal containing gold (Au) on the drive substrate through an adhesion layer which is a base layer, and has a removed portion in which a portion of the wiring metal in a region containing a part bonded to a bonding resin is removed and the adhesion layer is exposed. 1. An electronic device comprising:a drive substrate including a drive element and a wiring related to driving of the drive element, which are formed thereon; anda stacked body that is formed and spaced from the drive substrate, by interposing the drive element, the wiring, and a bonding resin therebetween,wherein the wiring is made of wiring metal containing gold (Au) on the drive substrate through a base layer, andwherein a portion of the base layer is exposed by removing a portion of the wiring metal, and the exposed base layer includes a portion covered with the bonding resin, and a portion that is not covered with the bonding resin.2. The electronic device according to claim 1 ,wherein a wiring metal removal region, which is a portion of the base layer including the portion covered with the bonding resin and a portion that is not covered with the bonding resin, is surrounded by the wiring metal in a plan view.3. The electronic device according to claim 1 ,wherein a dimension in a wiring direction of the wiring metal removal region is greater than a width in the wiring direction of a portion in which the bonding resin is bonded to the base layer.4. The electronic device according to claim 1 ,wherein the wiring metal removal region is subjected to a surface treatment by an organic molecule having a functional group that is chemically bonded to the bonding resin.5. The electronic device according to claim 4 , ...

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Номер записи: 92
21-09-2017 дата публикации

INDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20170271432A1
Автор: HU Yu-Wen, LAI Wei-Ming
Принадлежит:

A manufacturing method of an inductor structure includes the following steps. A protection layer is formed on a substrate, such that bond pads of the substrate are respectively exposed form protection layer openings of the protection layer. A conductive layer is formed on the bond pads and the protection layer. A patterned first photoresist layer is formed on the conductive layer. Copper bumps are respectively formed on the conductive layer located in the first photoresist layer openings. A patterned second photoresist layer is formed on the first photoresist layer, such that at least one of the copper bumps is exposed through second photoresist layer opening and the corresponding first photoresist layer opening. A diffusion barrier layer and an oxidation barrier layer are formed on the copper bump. The first and second photoresist layers, and the conductive layer not covered by the copper bumps are removed.

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Номер записи: 93
20-09-2018 дата публикации

VISIBILITY EVENT NAVIGATION METHOD AND SYSTEM

Номер: US20180268724A1
Автор: JENKINS Barry L.
Принадлежит: PRIMAL SPACE SYSTEMS, INC.

A method of visibility event navigation includes receiving, via processing circuitry of a client device, a first visibility event packet from a server, the first visibility event packet including information representing 3D surface elements of an environmental model that are occluded from a first viewcell and not occluded from a second viewcell, the first and second viewcells representing spatial regions of a specified navigational route within a real environment modeled by the environmental model. The method also includes acquiring, surface information representing the visible surfaces of the real environment at a sensor and determining, a position in the real environment by matching the surface information to the visibility event packet information. The method further includes transmitting, the position from the client device to the server and receiving a second visibility event packet from the server if the at least one position is within the specified navigational route. 1receiving, via processing circuitry of a client device, at least one visibility event packet of the one or more visibility event packets from the server;detecting, via the circuitry, surface information representing one or more visible surfaces of the real environment at a sensor in communication with the client device;calculating, via the circuitry, at least one position of the client device in the real environment by matching the surface information to the visibility event packet information corresponding to a first visibility event packet of the one or more visibility event packets;transmitting, via the circuitry, the at least one position from the client device to the server; andreceiving, via the circuitry, at least one second visibility event packet of the one or more visibility event packets when the at least one position is within the navigational route at the client device from the server.. A method of visibility event navigation, including one or more visibility event packets located ...

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Номер записи: 94
13-08-2020 дата публикации

Cold-welded flip chip interconnect structure

Номер: US20200259064A1
Автор: Eric Peter Lewandowski, Jae-Woong Nah, Nicholas Torleiv Bronn
Принадлежит: International Business Machines Corp

In an embodiment, a quantum device includes a first set of protrusions formed on a substrate and a second set of protrusions formed on a qubit chip. In the embodiment, the quantum device includes a set of bumps formed on an interposer, the set of bumps formed of a material having above a threshold ductility at a room temperature range, wherein a first subset of the set of bumps is configured to cold weld to the first set of protrusions and a second subset of the set of bumps is configured to cold weld to the second set of protrusions.

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Номер записи: 95
11-11-2021 дата публикации

BONDED BODY AND MANUFACTURING METHOD OF BONDED BODY

Номер: US20210351148A1
Автор: Kobayashi Hiroshi
Принадлежит: OLYMPUS CORPORATION

A bonded body includes: a first base body including a first wiring, a first electrode made of an electroplating film and including a first surface having a first region covering a periphery of an end portion of the first wiring and a second region covering the end portion of the first wiring, and a first passivation layer made of an insulating material and covering a periphery of the first electrode; a second base body including a second electrode; and solder disposed between the first region of the first electrode and the second electrode. 1. A bonded body comprising:a first base body comprising a first principal surface on which a first wiring, a first electrode made of an electroplating film, and a first passivation layer made of an insulating material are disposed, the first electrode including a first surface having a first region covering a periphery of an end portion of the first wiring and a second region covering the end portion of the first wiring, the first passivation layer covering a periphery of the first electrode;a second base body comprising a second principal surface on which a second electrode is disposed; andsolder disposed between the first region of the first electrode and the second electrode.2. The bonded body according to claim 1 , whereinthe first electrode is provided in an opening of the passivation layer,the second region has a height higher than a height of the first region due to a thickness of the first wiring, andthe first wiring is electrically connected to the first electrode in the opening.3. The bonded body according to claim 1 , wherein the second region of the first electrode is in contact with the second electrode.4. The bonded body according to claim 1 , wherein the second surface of the second electrode includes a third region claim 1 , and a fourth region claim 1 , an entire outer periphery of which is surrounded by the third region claim 1 , the fourth region having a height lower than a height of the third region.5. A ...

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Номер записи: 96
28-09-2017 дата публикации

METAL PILLAR WITH CUSHIONED TIP

Номер: US20170278815A1
Автор: Hu Dyi-Chung
Принадлежит:

A metal pillar with cushioned tip is disclosed. The cushioned tip offsets height difference among metal pillars. So that the height difference among metal pillars gives no significant effect to electrical coupling. The cushioned tip is a metal sponge. Additional one embodiment shows a second metal is plated on a tip of the metal sponge. A hardness of the second metal is greater than a hardness of a metal of the metal sponge, so that the second metal can stab into a corresponding metal sponge for electrical coupling. 1. Metal pillars with cushioned tips , comprising:a first metal pillar, configured on a bottom surface of a first device;a second metal pillar, configured on a bottom surface of the first device;a height difference between the first metal pillar and the second metal pillar;a first metal sponge, configured on a tip of the first metal pillar; anda second metal sponge, configured on a tip of the second metal pillar.2. Metal pillars with cushioned tips as claimed in claim 1 , further comprises:a first metal pad and a second metal pad, configured on a top surface of a second electronic device;a first solder layer, configured on a top surface of the first metal pad; anda second solder layer, configured on a top surface of the second metal pad; the solder melted and absorbed into the sponges while the plurality of metal pillars electrically coupled to the metal pads.3. Metal pillars with cushioned tips as claimed in claim 1 , further comprises:a third metal pillar, configured on a top surface of a second electronic device;a fourth metal pillar, configured on a top surface of the second electronic device;a third metal sponge, configured on a tip of the third metal pillar;a fourth metal sponge, configured on a tip of the fourth metal pillar; anda plurality of second metals, each plated on a tip of a corresponding metal sponge among the third metal sponge and the fourth metal sponge; wherein the second metal has a hardness greater than a hardness of a first metal ...

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Номер записи: 97
20-08-2020 дата публикации

Bump structure manufacturing method

Номер: US20200266163A1
Автор: Jin Kuk Lee
Принадлежит: LB Semicon Inc

Provided is a method of manufacturing a bump structure, the method including a first step for preparing a wafer including a plurality of chips each including a die pad, an under bump metal (UBM) layer on the die pad, and a bump pattern on the UBM layer, a second step for attaching a backgrinding film to an upper surface of the wafer, a third step for grinding a rear surface of the wafer by a certain thickness, a fourth step for forming a flexible material layer on a second rear surface of the wafer after being ground, and then attaching dicing tape including a ring frame, to the flexible material layer, a fifth step for removing the backgrinding film and then performing a curing process to harden the flexible material layer, and a sixth step for performing a dicing process to cut the plurality of chips into individual chips.

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Номер записи: 98
27-08-2020 дата публикации

VISIBILITY EVENT NAVIGATION METHOD AND SYSTEM

Номер: US20200273354A1
Автор: JENKINS Barry L.
Принадлежит: PRIMAL SPACE SYSTEMS, INC.

A method of visibility event navigation includes receiving, via processing circuitry of a client device, a first visibility event packet from a server, the first visibility event packet including information representing 3D surface elements of an environmental model that are occluded from a first viewcell and not occluded from a second viewcell, the first and second viewcells representing spatial regions of a specified navigational route within a real environment modeled by the environmental model. The method also includes acquiring, surface information representing the visible surfaces of the real environment at a sensor and determining, a position in the real environment by matching the surface information to the visibility event packet information. The method further includes transmitting, the position from the client device to the server and receiving a second visibility event packet from the server if the at least one position is within the specified navigational route. 1receiving, via processing circuitry of a client device, at least one visibility event packet of the one or more visibility event packets from the server;detecting, via the circuitry, surface information representing one or more visible surfaces of the real environment at a sensor in communication with the client device;calculating, via the circuitry, at least one position of the client device in the real environment by matching the surface information to the visibility event packet information corresponding to a first visibility event packet of the one or more visibility event packets;transmitting, via the circuitry, the at least one position from the client device to the server; andreceiving, via the circuitry, at least one second visibility event packet of the one or more visibility event packets when the at least one position is within the navigational route at the client device from the server.. A method of visibility event navigation, including one or more visibility event packets located ...

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Номер записи: 99
04-10-2018 дата публикации

RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20180286827A1
Автор: Kimura Noriyuki
Принадлежит:

The resin-encapsulated semiconductor device includes a bump electrode () formed on an element surface side of a semiconductor chip (), a conductive layer () electrically connected to the bump electrode (), and a resin encapsulation body () covering the semiconductor chip (), the bump electrode (), and the conductive layer (). On a back surface of the semiconductor chip () that is flush with a back surface of the resin encapsulation body (), a metal layer () and a laminated film () are formed. The laminated film () is formed on a front surface of the conductive layer (). The external terminal () is arranged on an inner side of an outer edge of the semiconductor chip (). 1. A resin-encapsulated semiconductor device , comprising:a resin encapsulation body having a first surface and a second surface that is opposite to the first surface;a semiconductor chip embedded in the resin encapsulation body, and having an element surface and a back surface that is opposite to the element surface, the back surface being flush with the second surface;an external terminal formed on the element surface of the semiconductor chip, and embedded in the resin encapsulation body;a laminated film provided on the external terminal, and being exposed from the first surface; anda metal layer formed on the back surface of the semiconductor chip, and protruding from the second surface.2. The resin-encapsulated semiconductor device according to claim 1 , wherein the metal layer has an outer edge that is matched with an outer edge of the semiconductor chip so that the metal layer and the semiconductor chip have the same size in plan view.3. The resin-encapsulated semiconductor device according to claim 1 , wherein the metal layer has an outer edge that is matched with an outer edge of the resin encapsulation body so that the metal layer and the resin encapsulation body have the same size in plan view.4. The resin-encapsulated semiconductor device according to claim 1 , wherein the laminated film ...

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Номер записи: 100