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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 3670. Отображено 100.
23-02-2012 дата публикации

Mechanisms for forming copper pillar bumps using patterned anodes

Номер: US20120043654A1

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

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22-03-2012 дата публикации

Massively Parallel Interconnect Fabric for Complex Semiconductor Devices

Номер: US20120068229A1
Принадлежит: Individual

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

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22-03-2012 дата публикации

Integrated circuit packaging system with active surface heat removal and method of manufacture thereof

Номер: US20120068328A1
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.

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12-04-2012 дата публикации

Semiconductor assembly and semiconductor package including a solder channel

Номер: US20120086123A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

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26-07-2012 дата публикации

Semiconductor chip module, semiconductor package having the same and package module

Номер: US20120187560A1
Принадлежит: Hynix Semiconductor Inc

A semiconductor module comprising a plurality of semiconductor chips where at least one semiconductor chip is laterally offset with respect to a second semiconductor chip, and substantially aligned with a third semiconductor chip such that an electrical connection can be made between an electrical contact in the first semiconductor chip and an electrical contact in the third semiconductor chip.

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23-08-2012 дата публикации

Chip package with plank stack of semiconductor dies

Номер: US20120211878A1
Принадлежит: Oracle International Corp

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

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04-10-2012 дата публикации

Heat conduction for chip stacks and 3-d circuits

Номер: US20120248627A1
Принадлежит: INTERSIL AMERICAS LLC

A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.

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03-01-2013 дата публикации

Bump-on-trace (bot) structures

Номер: US20130001778A1

A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

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21-02-2013 дата публикации

Package-on-package structures

Номер: US20130043587A1
Принадлежит: MARVELL WORLD TRADE LTD

Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.

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11-04-2013 дата публикации

Semiconductor device having multiple bump heights and multiple bump diameters

Номер: US20130087910A1
Принадлежит: Texas Instruments Inc

A semiconductor die includes a first contact stack including a first UBM pad on a first die pad, a second contact stack including a second UBM pad on a second die pad, and a third contact stack including a third UBM pad on a third die pad. The second UBM pad perimeter is shorter than the first UBM pad perimeter, and the third UBM pad perimeter is longer than the second UBM pad perimeter. A first solder bump is on the first UBM pad, a second solder bump is on the second UBM pad, and a third solder bump is on the third UBM pad. The first solder bump, second solder bump and third solder bump all have different sizes.

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23-05-2013 дата публикации

Adjusting Sizes of Connectors of Package Components

Номер: US20130127059A1

A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.

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20-06-2013 дата публикации

Electrical Contact Alignment Posts

Номер: US20130157455A1
Принадлежит: International Business Machines Corp

An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.

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25-07-2013 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20130187271A1
Принадлежит: Denso Ten Ltd, Fujitsu Ltd

A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

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26-09-2013 дата публикации

Probing Chips during Package Formation

Номер: US20130249532A1
Автор: Jing-Cheng Lin, Szu Wei Lu

A method includes bonding a first package component on a first surface of a second package component, and probing the first package component and the second package component from a second surface of the second package component. The step of probing is performed by probing through connectors on the second surface of the second package component. The connectors are coupled to the first package component. After the step of probing, a third package component is bonded on the first surface of the second package component.

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14-11-2013 дата публикации

Semiconductor Die Connection System and Method

Номер: US20130299976A1

A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.

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05-12-2013 дата публикации

Sapphire substrate configured to form light emitting diode chip providing light in multi-directions, light emitting diode chip, and illumination device

Номер: US20130320363A1
Принадлежит: Formosa Epitaxy Inc

A sapphire substrate configured to form a light emitting diode (LED) chip providing light in multi-directions, a LED chip and an illumination device are provided in the present invention. The sapphire substrate includes a growth surface and a second main surface opposite to each other. A thickness of the sapphire substrate is thicker than or equal to 200 micrometers. The LED chip includes the sapphire substrate and at least one LED structure. The LED structure is disposed on the growth surface and forms a first main surface where light emitted from with a part of the growth surface without the LED structures. At least a part of light beams emitted from the LED structure pass through the sapphire substrate and emerge from the second main surface. The illumination device includes at least one LED chip and a supporting base. The LED chip is disposed on the supporting base.

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19-12-2013 дата публикации

Shaped and oriented solder joints

Номер: US20130335939A1
Принадлежит: Intel Corp

The present description relates to the field of fabricating microelectronic assemblies, wherein a microelectronic device may be attached to a microelectronic substrate with a plurality of shaped and oriented solder joints. The shaped and oriented solder joints may be substantially oval, wherein the major axis of the substantially oval solder joints may be substantially oriented toward a neutral point or center of the microelectronic device. Embodiments of the shaped and oriented solder joint may reduce the potential of solder joint failure due to stresses, such as from thermal expansion stresses between the microelectronic device and the microelectronic substrate.

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23-01-2014 дата публикации

Semiconductor package with single sided substrate design and manufacturing methods thereof

Номер: US20140021636A1
Принадлежит: Advanced Semiconductor Engineering Inc

A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.

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06-02-2014 дата публикации

Interface Substrate with Interposer

Номер: US20140035162A1
Принадлежит: Broadcom Corp

An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided.

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20-02-2014 дата публикации

Multi-Chip Module with Multiple Interposers

Номер: US20140048928A1
Принадлежит: Cisco Technology Inc

A Multi-Chip Module is presented herein that comprises a package substrate, at least two integrated circuit devices, each of which is electrically coupled to the package substrate, and an interposer. Formed in the interposer are electrical connections which are predominantly horizontal interconnects. The first interposer is arranged to electrically couple the two integrated circuit devices to each other. Methods for manufacturing a Multi-Chip Module are also presented herein.

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20-03-2014 дата публикации

Bump Structure and Method of Forming Same

Номер: US20140077358A1

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

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20-03-2014 дата публикации

Metal Bump and Method of Manufacturing Same

Номер: US20140077365A1

An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width.

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05-01-2017 дата публикации

SYSTEMS AND METHODS FOR HIGH-SPEED, LOW-PROFILE MEMORY PACKAGES AND PINOUT DESIGNS

Номер: US20170005056A1
Принадлежит:

Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides. 125.-. (canceled)26. An integrated circuit (“IC”) package substrate , comprising a bottom surface comprising an array of contacts , the array of contacts comprising a plurality of data I/O contacts , wherein:a first subset of the plurality of data I/O contacts forms a first C-shaped layout arranged on a first portion of the bottom surface;a second subset of the plurality of data I/O contacts forms a second C-shaped layout arranged on a second portion of the bottom surface; andthe first portion and the second portion are reflectively symmetrical about a central axis.27. The IC package substrate of claim 26 , the array of contacts further comprising a plurality of ground (“GND”) contacts claim 26 , wherein at least one GND contact of the plurality of GND contacts is surrounded by the data I/O contacts of each of the first and second subsets of the plurality of data I/O contacts.28. The IC package substrate of claim 26 , the array of contacts further comprising a plurality of data queue stroke (“DQS”) contacts claim 26 , wherein at least one DQS contact of the plurality of DQS contacts is surrounded by the data I/O contacts of each of the first and second subsets of the plurality of data I/O contacts.29. The IC package substrate of claim 26 , wherein the first subset of the plurality of data I/O contacts comprises a first communications channel claim 26 , and the second subset of the plurality of data I/O contacts comprises a second communications channel.30. The IC package of claim 29 , the array of contacts further comprising a plurality of chip enable (“CE”) contacts claim ...

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07-01-2016 дата публикации

Semiconductor devices having through electrodes, methods of manufacturing the same, and semiconductor packages including the same

Номер: US20160005706A1
Автор: Wan Choon PARK
Принадлежит: SK hynix Inc

A semiconductor device includes a semiconductor layer having a first surface and a second surface, a through electrode penetrating the semiconductor layer and having a protruding portion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed on the first surface of the semiconductor layer and electrically coupled to the through electrode, a passivation pattern including a first insulation pattern that surrounds a sidewall of the protruding portion of the through electrode and extends onto the second surface of the semiconductor layer and a second insulation pattern that covers the first insulation pattern and has an etch selectivity with respect to the first insulation pattern, and a back-side bump covering an end surface of the protruding portion of the through electrode and extending onto the passivation pattern.

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07-01-2021 дата публикации

Method and apparatus for manufacturing array device

Номер: US20210005520A1
Принадлежит: Sharp Corp

A method for manufacturing an array device includes a placing step of providing a plurality of elements in an array on a first surface of a substrate, an element separating step of separating a plurality of element chips from one another so that each element chip includes one or more elements, an inspecting step of inspecting the plurality of elements, a removing step of removing any element chip of the plurality of element chips from the surface of the substrate on the basis of a result of the inspecting step, and a mounting step of, after the removing step, mounting an element of at least the elements other than an element of the element chip thus removed onto a mounting substrate by transfer from the substrate, the mounting substrate being different from the substrate.

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04-01-2018 дата публикации

SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF

Номер: US20180005987A1
Принадлежит:

A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die. 1. A method of making an electronic device , the method comprising:receiving a first portion of a signal redistribution structure;forming a first functional die interconnection structure on the signal redistribution structure;forming a second functional die interconnection structure on the signal redistribution structure;coupling a back side of a connect die to the signal redistribution structure, the connect die comprising a first connect die interconnection structure coupled to a front side of the connect die and a second connect die interconnection structure coupled to the front side of the connect die;coupling a first interconnection structure of a first functional die to the first functional die interconnection structure; andcoupling a second interconnection structure of the first functional die to the first connect die interconnection structure.2. The method of claim 1 , wherein:said receiving the first portion of the signal redistribution structure comprises receiving the first portion of the signal distribution structure on a carrier; andthe method further comprises removing the carrier.3. The method of claim 1 , comprising:coupling a third interconnection structure of a second functional die to the second functional die interconnection structure; andcoupling a fourth interconnection structure of the second functional die to the second connect die interconnection structure.4. The method of claim 2 , comprising after said removing the carrier claim 2 , adding at least one dielectric layer and at least one conductive layer to the signal redistribution structure.5. The method of claim 1 , comprising before said coupling the first and ...

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04-01-2018 дата публикации

SEMICONDUCTOR LIGHT EMITTING ELEMENT WITH DISPERSIVE OPTICAL UNIT AND ILLUMINATION DEVICE COMPRISING THE SAME

Номер: US20180006199A9
Принадлежит:

A semiconductor light emitting element includes a transparent substrate and a plurality of light emitting diode (LED) chips. The transparent substrate has a support surface and a second main surface disposed opposite to each other. At least some of the LED structures are disposed on the support surface and form a first main surface where light emitted from with a part of the support surface without the LED structures. Each of the LED structures includes a first electrode and a second electrode. Light emitted from at least one of the LED structures passes through the transparent substrate and emerges from the second main surface. An illumination device includes the semiconductor light emitting element and a supporting base. The semiconductor light emitting element is disposed on the supporting base, and an angle is formed between the semiconductor light emitting element and the supporting base. 1. A semiconductor light emitting element , comprising:a transparent substrate, having a support surface and a second main surface disposed opposite to each other;a light emitting diode (LED) structure disposed on the support surface, a first main surface, where light emitted from, being formed by the LED structure and at least a part of the support surface without the LED structure, and at least a part of the light emitted from the LED structure may pass through the transparent substrate and emerge from the second main surface; andan optical unit disposed on the first main surface, the optical unit comprising a covering side facing the transparent substrate, and a light dispersion side corresponding to the covering surface;wherein the optical unit further comprises at least one optical structure disposed on the light dispersion side to disperse light received from the covering side to different directions corresponding to wavelength of the light.2. The semiconductor light emitting element of claim 1 , further comprising:a wavelength conversion layer sandwiched by the optical ...

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03-01-2019 дата публикации

SEMICONDUCTOR CHIP

Номер: US20190006306A1
Принадлежит: MURATA MANUFACTURING CO., LTD.

A semiconductor chip includes a semiconductor substrate having a main surface, first and second electrodes, a first insulating layer, and first and second bumps. The first and second electrodes are formed above the main surface of the semiconductor substrate. The first insulating layer is formed above a first portion of the first electrode. The first bump is formed above a second portion of the first electrode and above the first insulating layer and is electrically connected to the first electrode. The second bump is formed above the second electrode. The area of the second bump is larger than that of the first bump in a plan view of the main surface of the semiconductor substrate. The first insulating layer adjusts the distance from the main surface of the semiconductor substrate to the top surface of the first bump in a direction normal to the main surface. 1. A semiconductor chip comprising:a semiconductor substrate having a main surface;a first electrode formed above the main surface of the semiconductor substrate;a second electrode formed above the main surface of the semiconductor substrate;a first insulating layer formed above a first portion of the first electrode;a first bump that is formed above a second portion of the first electrode and above the first insulating layer, and that is electrically connected to the first electrode; anda second bump formed above the second electrode, an area of the second bump being larger than an area of the first bump in a plan view of the main surface of the semiconductor substrate,wherein a level on which the first bump is formed is higher than a level on which the second bump is formed.2. The semiconductor chip according to claim 1 , wherein a longest distance from the main surface of the semiconductor substrate to a top surface of the first bump in a direction normal to the main surface of the semiconductor substrate is substantially equal to a longest distance from the main surface of the semiconductor substrate to a ...

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03-01-2019 дата публикации

THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYSTEMS AND METHODS

Номер: US20190006323A1
Принадлежит:

Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures. 1. A semiconductor die , comprising:a semiconductor substrate having a first surface and a second surface angled relative to the first surface, wherein the second surface at least partially defines an opening in the first surface;an interconnect extending at least partially through the semiconductor substrate, wherein the interconnect includes an end portion projecting from the opening, and wherein the end portion has a sidewall exposed from the semiconductor substrate in the opening;a metallization structure extending at least partially around the sidewall of the end portion of the interconnect, wherein the metallization structure is laterally spaced apart from the second surface of the semiconductor substrate; anda thermal pad on the first surface of the semiconductor substrate, wherein the thermal pad and the metallization structure project to generally the same vertical height above the first surface of the semiconductor substrate.2. The semiconductor die of claim 1 , further comprising a passivation material at least partially on the first surface of the semiconductor substrate.3. The semiconductor die of claim 1 , further comprising a passivation material in the opening between the metallization structure and the semiconductor substrate.4. The ...

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12-01-2017 дата публикации

Chip package and manufacturing method thereof

Номер: US20170012081A1
Принадлежит: XinTec Inc

A manufacturing method of a chip package includes the following steps. A patterned solder paste layer is printed on a patterned conductive layer of a wafer. Plural solder balls are disposed on the solder paste layer that is on a first portion of the conductive layer. A reflow process is performed on the solder balls and the solder paste layer. A flux layer converted from a surface of the solder paste layer is cleaned.

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15-01-2015 дата публикации

Light emitting diode package structure

Номер: US20150014720A1
Автор: Yun-Yi Tien
Принадлежит: Lextar Electronics Corp

A LED package structure including a carrier and a light emitting diode (LED) chip is provided. The LED chip includes a substrate, a patterned structure, a first semiconductor layer, an active layer and a second semiconductor layer. The substrate has a first surface and a second surface opposite to the first surface. The patterned structure is formed on the second surface of the substrate. The first semiconductor layer is disposed on the first surface of the substrate. The active layer is disposed on a portion of a surface of the first semiconductor layer, and other portion of the surface not covered by the active layer is exposed. The second semiconductor layer is disposed on the active layer. The LED chip is disposed on the carrier by way of flip-chip so that the first and the second semiconductor layers face towards the carrier.

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15-01-2015 дата публикации

HYBRID LEAD FRAME AND BALL GRID ARRAY PACKAGE

Номер: US20150014834A1
Принадлежит:

A semiconductor device includes a first substrate having opposing first and second main surfaces, a first die disposed on the first main surface of the first substrate, a first bond wire coupled to the first die, a first packaging material encapsulating the first die and the first bond wire, and a lead frame disposed on the first main surface of the first substrate and in electrical communication with the first bond wire. At least a portion of the lead frame extends outside of the packaging material. A top package includes first and second main surfaces and an electrical contact on the second main surface. The electrical contact is electrically connected to the lead frame and connects the top package to either the first die and/or external circuitry.

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10-01-2019 дата публикации

Tall and fine pitch interconnects

Номер: US20190013287A1
Принадлежит: Invensas LLC

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

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10-01-2019 дата публикации

Interconnect structures with intermetallic palladium joints and associated systems and methods

Номер: US20190013296A1
Автор: Jaspreet S. Gandhi
Принадлежит: Micron Technology Inc

Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

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14-01-2021 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20210013165A1
Принадлежит:

A semiconductor device includes a semiconductor substrate, a transistor, and a first harmonic termination circuit. The transistor is formed at the semiconductor substrate. The transistor amplifies an input signal supplied to an input end and outputs an amplified signal through an output end. The first harmonic termination circuit attenuates a harmonic component included in the amplified signal. The first harmonic termination circuit is formed at the semiconductor substrate such that one end of the first harmonic termination circuit is connected to the output end of the transistor and the other end of the first harmonic termination circuit is connected to a ground end of the transistor. 1. A semiconductor device comprising:a semiconductor substrate;a transistor that amplifies an input signal supplied to an input end and outputs an amplified signal through an output end, the transistor being on or in the semiconductor substrate, and the transistor being a multi-finger transistor having a plurality of unit transistors;a first harmonic termination circuit that is configured to attenuate a harmonic component of an amplified signal output from an output end of a first unit transistor, the first harmonic termination circuit being on the semiconductor substrate such that a first end of the first harmonic termination circuit is connected to the output end of the first unit transistor and a second end of the first harmonic termination circuit is connected to a ground end of the first unit transistor; anda second harmonic termination circuit configured to attenuate a harmonic component of an amplified signal output from an output end of a second unit transistor, the second harmonic termination circuit being on the semiconductor substrate such that a first end of the second harmonic termination circuit is connected to the output end of the second unit transistor and a second end of the second harmonic termination circuit is connected to a ground end of the second unit ...

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09-01-2020 дата публикации

Substrate design for semiconductor packages and method of forming same

Номер: US20200013635A1

A device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity.

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09-01-2020 дата публикации

METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES

Номер: US20200013734A1
Принадлежит:

Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate. 1. A semiconductor structure , comprising:a substrate having an insulating layer thereon, the substrate having a perimeter, and the substrate comprising silicon;a metallization structure on the insulating layer, the metallization structure comprising conductive routing in a dielectric material stack;a first metal guard ring in the dielectric material stack and continuous around the conductive routing;a second metal guard ring in the dielectric material stack and continuous around the first metal guard ring;a plurality of staggered mini guard rings between the first metal guard ring and the second metal guard ring; anda metal-free region of the dielectric material stack surrounding the second metal guard ring, the metal-free region adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.2. The semiconductor structure of claim 1 , wherein at least one of the first metal guard ring or the second metal guard ring provides a hermetic seal for the metallization structure.3. The semiconductor structure of claim 1 , further comprising:a metal feature between the first metal ...

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09-01-2020 дата публикации

DUAL BOND PAD STRUCTURE FOR PHOTONICS

Номер: US20200014171A1
Принадлежит:

A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads. 1. A method , comprising:forming a masking layer over a bonding layer;patterning the bonding layer to form bonding pads;attaching a laser diode to selected bonding pads using solder connections formed on the laser diode such that the laser diode is unobstructed by solder bumps and the selected bonding pads; andattaching an interposer substrate to the solder bumps which are on the bonding pads such that the interposer substrate is spaced away and disconnected from the laser diode.2. The method of claim 1 , wherein the masking layer is formed over portions of the bonding layer which are to be attached to the laser diode.3. The method of claim 1 , wherein the solder bumps are formed through a resist pattern claim 1 , after the forming of the masking layer over the bonding layer.4. The method of claim 1 , further comprising forming the solder bumps on the bonding layer.5. The method of claim 4 , wherein the patterning of the bonding layer is performed after the forming of the solder bumps such that the solder bumps and the masking layer protect underlying portions of the bonding layer during an etching process.6. The method of claim 5 , further comprising removing the masking layer and attaching the solder connections formed on the laser diode directly to the bonding pads which are formed underneath the masking layer prior to removal.7. The method of claim 6 , ...

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21-01-2016 дата публикации

SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF

Номер: US20160020195A1
Принадлежит:

A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.

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03-02-2022 дата публикации

FLOW GUIDING STRUCTURE OF CHIP

Номер: US20220037275A1
Автор: CHEN PO-CHI, TSENG KUO-WEI
Принадлежит:

The present invention provides a flow guiding structure of chip, which comprises at least one flow guiding member disposed on a surface of a chip and adjacent to a plurality of connecting bumps disposed on the surface of the chip. When the chip is disposed on a board member, the at least one flow guiding member may guide the conductive medium on the surface of the chip to flow toward the connecting bumps and drive a plurality of conductive particles of the conductive medium to move toward the connecting bumps and thus increasing the number of the conductive particles on the surfaces of the connecting bumps. Alternatively, the flow guiding member may retard the flow of the conductive medium for avoiding the conductive particles from leaving the surfaces of the connecting bumps and thus preventing reduction of the number of the conductive particles on the surfaces of the connecting bumps. 1. A flow guiding structure of chip , comprising:a plurality of connecting bumps, disposed on a surface of a chip; andat least one flow guiding member, disposed on said surface of said chip, and adjacent to said connecting bumps.2. The flow guiding structure of chip of claim 1 , wherein a height of said at least one flow guiding member is smaller than or equal to a height of said connecting bumps.3. The flow guiding structure of chip of claim 1 , wherein at least one side of said at least one flow guiding member is adjacent to said connecting bumps; and said at least one side of said at least one flow guiding member is a sloped surface.4. The flow guiding structure of chip of claim 1 , wherein said at least one flow guiding member includes a plurality of flow guiding members; said flow guiding members include a plurality of flow guiding bumps; and said flow guiding bumps are adjacent to said connecting bumps.5. The flow guiding structure of chip of claim 4 , wherein a first side of said flow guiding bumps corresponds to a second side of said connecting bumps; and an area of said ...

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03-02-2022 дата публикации

ELECTRONIC DEVICE

Номер: US20220037446A1
Автор: CHO Youngmin, KIM HONGAM
Принадлежит: Samsung Display Co., Ltd.

An electronic device includes a first electronic component and a second electronic component. The first electronic component includes a first pad area including first pads and second pads spaced apart from the first pads. A number of the first pads is greater than a number of the second pads. The second electronic component includes first bumps electrically connected to the first pads, and second bumps electrically connected to the second pads. Each of the second bumps has a bonding area greater than a bonding area of each of the first bumps. A conductive adhesive layer is disposed between the first electronic component and the second electronic component to electrically connect the first pads to the first bumps. 1. An electronic device comprising:a first electronic component comprising a first pad area including first pads and second pads spaced apart from the first pads, wherein a number of the first pads is greater than a number of the second pads; first bumps electrically connected to the first pads; and', 'second bumps electrically connected to the second pads, wherein each of the second bumps has a bonding area greater than a bonding area of each of the first bumps; and, 'a second electronic component comprisinga conductive adhesive layer disposed between the first electronic component and the second electronic component to electrically connect the first pads to the first bumps.2. The electronic device of claim 1 , whereinthe first electronic component comprises a display area adjacent to the first pad area, wherein a pixel is disposed in the display area, andthe second electronic component comprises a driving chip.3. The electronic device of claim 2 , wherein the first electronic component comprises a second pad area comprising third pads electrically connected to the second pads.4. The electronic device of claim 3 , further comprising a circuit board electrically connected to the second pad area.5. The electronic device of claim 3 , whereinthe driving chip ...

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18-01-2018 дата публикации

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

Номер: US20180019191A1
Принадлежит: INVENSAS CORPORATION

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...

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18-01-2018 дата публикации

FAN OUT SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF SEMICONDUCTOR DIE

Номер: US20180019228A1

A semiconductor package is disclosed including a number of stacked semiconductor die, electrically connected to each other with wire bonds. The stacked semiconductor die are provided in a mold compound such that a spacing exists between a top die in the die stack and a surface of the mold compound. The wire bonds to the top die may be provided in the spacing. An RDL pad is affixed to the surface of the mold compound. Columns of bumps may be formed on the die bond pads of the top die in the die stack to electrically couple the RDL pad to the die stack across the spacing. 1. A semiconductor package , comprising:a plurality of stacked semiconductor die, each including die bond pads, the plurality of stacked semiconductor die including a first semiconductor die at a top of the stacked semiconductor die;mold compound, the plurality of semiconductor die encapsulated within the mold compound so that a surface of the first semiconductor die including the die bond pads is within the mold compound and spaced from a surface of the mold compound;wire bonds affixed on the die bond pads of the plurality of stacked semiconductor die, the wire bonds electrically coupling the plurality of stacked semiconductor die;columns of one or more bumps formed on top of the wire bonds at the die bond pads on the first semiconductor die, the one or more bumps of each column having a surface of a bump exposed through the surface of the mold compound; contact pads on a first surface of the RDL pad mating with the exposed bump of each column at the surface of the mold compound,', 'solder bumps on a second surface of the RDL pad, and', 'a conductance pattern for electrically connecting the contact pads on the first surface of the RDL pad with select ones of the solder bumps on the second surface of the RDL pad., 'a redistribution layer (RDL) pad affixed to the surface of the mold compound, the redistribution layer pad comprising2. The semiconductor package of claim 1 , wherein a height a column of ...

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22-01-2015 дата публикации

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices

Номер: US20150021769A1
Принадлежит: Micron Technology Inc

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a microelectronic device includes attaching a microelectronic die to a support member by forming an attachment feature on at least one of a back side of the microelectronic die and the support member. The attachment feature includes a volume of solder material. The method also includes contacting the attachment feature with the other of the microelectronic die and the support member, and reflowing the solder material to join the back side of the die and the support member via the attachment feature. In several embodiments, the attachment feature is not electrically connected to internal active structures of the die.

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17-01-2019 дата публикации

Methods of fluxless micro-piercing of solder balls, and resulting devices

Номер: US20190019774A1
Автор: Teck Kheng Lee
Принадлежит: Micron Technology Inc

A method of establishing conductive connections is disclosed. The method includes providing an integrated circuit die having a plurality of solder balls each of which has an oxide layer on an outer surface of the solder ball. The method also includes performing a heating process to heat at least the solder balls and applying a force causing each of a plurality of piercing bond structures on a substrate to pierce one of the solder balls and its associated oxide layer to thereby establish a conductive connection between the solder ball and the piercing bond structure.

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16-01-2020 дата публикации

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

Номер: US20200020654A1

A structure and method for performing metal-to-metal bonding in an electrical device. For example and without limitation, various aspects of this disclosure provide a structure and method that utilize an interlocking structure configured to enhance metal-to-metal bonding.

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16-01-2020 дата публикации

SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND ASSOCIATED SEMICONDUCTOR DIE

Номер: US20200020655A1
Принадлежит:

A semiconductor device manufacturing method including: simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site; wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range. 1. A semiconductor device manufacturing method , comprising:simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site;wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range.2. The method of claim 1 , wherein forming a plurality of bumps comprises providing a patterned mask on a substrate.3. The method of claim 2 , wherein the patterned mask includes a plurality of trenches claim 2 , and each trench exposes a bottom surface configured as an area of one formation site.4. The method of claim 3 , wherein simultaneously forming a plurality of bumps comprises filling a conductive material into the plurality of trenches simultaneously.5. The method of claim 3 , wherein forming a plurality of formation sites comprises a photolithography operation claim 3 , and the predetermined range is determined by a unit exposure area of the photolithography operation.6. The method of claim 5 , wherein the photolithography operation comprises disposing a photosensitive material on the substrate and patterning the photosensitive material to form the patterned mask claim 5 , and the forming factor is an exposure energy.7. The method of claim 5 , ...

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21-01-2021 дата публикации

SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF

Номер: US20210020605A1
Принадлежит:

A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die. 1. An electronic device comprising:a signal redistribution structure (SRS) comprising a top SRS side, a bottom SRS side, and a plurality of lateral SRS sides, where the signal redistribution structure is coreless;a lower electronic component (LEC) comprising a top LEC side, a bottom LEC side, and a plurality of lateral LEC sides, where the top LEC side is coupled to the bottom SRS side;a vertical interconnect structure coupled to the bottom SRS side at a position that is laterally offset from the lower electronic component;an LEC interconnect structure that is coupled to the top LEC side and to the bottom SRS side, such that the lower electronic component is electrically coupled to the signal redistribution structure through at least the LEC interconnect structure;a semiconductor die comprising a top die side, a bottom die side, and a plurality of lateral die sides;a first die interconnect structure coupled to the top SRS side and to the bottom die side, such that the semiconductor die is electrically coupled to the vertical interconnect structure; anda second die interconnect structure coupled to the top SRS side and to the bottom die side, such that the semiconductor die is electrically coupled to the lower electronic component.2. The electronic device of claim 1 , wherein:the semiconductor die is electrically coupled to the vertical interconnect structure through at least the first die interconnect structure and the signal redistribution structure; andthe semiconductor die is electrically coupled to the lower electronic component through at least the second die interconnect structure, the signal redistribution structure, and the LEC ...

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21-01-2021 дата публикации

Semiconductor structure and manufacturing method thereof

Номер: US20210020606A1

A method of manufacturing a semiconductor structure includes providing a substrate including a redistribution layer (RDL) disposed over the substrate, disposing a first patterned mask over the RDL, disposing a first conductive material over the RDL exposed from the first patterned mask to form a first conductive pillar, removing the first patterned mask, disposing a second patterned mask over the RDL, disposing a second conductive material over the RDL exposed from the second patterned mask to form a second conductive pillar, removing the second patterned mask, disposing a first die over the first conductive pillar, and disposing a second die over the second conductive pillar. A height of the second conductive pillar is substantially greater than a height of the first conductive pillar.

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26-01-2017 дата публикации

Pre-package and methods of manufacturing semiconductor package and electronic device using the same

Номер: US20170025302A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate.

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28-01-2016 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20160027758A1
Принадлежит: PS4 Luxco S.a.r.l.

[Problem] To provide a semiconductor device with a wafer level package structure that allows for probing while reducing the area occupied by the pad electrodes. [Solution] In the present invention, the following are provided: a semiconductor chip (100) that has first and second pad electrodes (120, 120) disposed on the main surface thereof; insulating films (310, 330) that cover the main surface of the semiconductor chip (100); a rewiring layer (320) that is disposed between the insulating films (310, 330); and a plurality of external terminals (340) disposed on the top of the insulating film (330). The plane size of the first pad electrode (120) and the second pad electrode (120) differ from one another, and the first pad electrode (120) and the second pad electrode (120) are connected to any of the plurality of external terminals (340) via the rewiring layer (320). According to the present invention, because the pad electrodes (120, 120) of different sizes are intermixed, probing can be easily performed while reducing the area occupied by the pad electrodes. 1. A semiconductor device , comprising:a semiconductor chip;a plurality of first pad electrodes formed running in a first direction through a center portion of a principal surface of the semiconductor chip; anda plurality of second pad electrodes formed on the principal surface of the semiconductor chip between a pad column formed by the first pad electrodes and a side of the semiconductor chip,wherein the first pad electrodes and the second pad electrodes have a different planar size.2. The semiconductor device as claimed in claim 1 , wherein the first pad electrodes supply a first power source voltage claim 1 , and the second pad electrodes supply a second power source voltage.3. The semiconductor device as claimed in claim 2 , wherein the first pad electrodes and the second pad electrodes both supply a same power source voltage.4. The semiconductor device as claimed in claim 1 , further comprising an ...

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24-01-2019 дата публикации

Semiconductor device with photonic and electronic functionality and method for manufacturing a semiconductor device

Номер: US20190025505A1
Принадлежит: ams AG

A semiconductor device has a semiconductor substrate and a first metallization stack arranged on the substrate. The substrate has and/or carries a plurality of electronic circuit elements. The first metallization stack has electrically insulating layers and at least one metallization layer. The semiconductor device further has a second metallization stack arranged on the first metallization stack and comprising further electrically insulating layers and an optical waveguide layer. The optical waveguide layer has at least one optical waveguide structure. Furthermore, one of the electrically insulating layers and one of the further electrically insulating layers are in direct contact with each other and form a pair of directly bonded layers.

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25-01-2018 дата публикации

3D Semiconductor Package Interposer with Die Cavity

Номер: US20180026008A1
Принадлежит:

Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects. 1. A device , comprising:a substrate having a top surface;an interposer over the top surface of the substrate, the interposer being connected to the substrate by first interconnects;a first integrated circuit die connected to a first side of the interposer by first connectors;a second integrated circuit die connected to a second side of the interposer opposite the first side by second connectors, the second integrated circuit die having a smaller footprint than the interposer; anda fan-out structure disposed over a top surface of the interposer and extending beyond outermost edges of the interposer, wherein the fan-out structure is electrically connected to second interconnects, the second interconnects in contact with the top surface of the substrate.2. The device of claim 1 , further comprising third connectors connecting the fan-out structure to the second integrated circuit die.3. The device of claim 1 , further comprising a cavity in the top surface of the substrate claim 1 , wherein the first integrated circuit die extends into the cavity.4. The device of claim 1 , further comprising:a first molding compound on sidewalls of the interposer, the first interconnects, and the second interconnects; anda second molding compound on the first molding compound, the fan-out structure, and the second integrated circuit die.5. The device of claim 1 , ...

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29-01-2015 дата публикации

SEMICONDUCTOR DEVICES WITH BALL STRENGTH IMPROVEMENT

Номер: US20150028481A1
Принадлежит:

A semiconductor device includes a contact region over a substrate. The semiconductor device further includes a metal pad over the contact region. Additionally, the semiconductor device includes a post passivation interconnect (PPI) line over the metal pad, where the PPI line is in contact with the metal pad. Furthermore, the semiconductor device includes an under-bump-metallurgy (UBM) layer over the PPI line. Moreover, the semiconductor device includes a plurality of solder balls over the UBM layer, the plurality of solder balls being arranged at some, but not all, intersections of a number of columns and rows of a ball pattern. 1. A semiconductor device , comprising:a contact region over a substrate;a metal pad over the contact region;a post passivation interconnect (PPI) line over the metal pad, wherein the PPI line is in contact with the metal pad;an under-bump-metallurgy (UBM) layer over the PPI line; anda plurality of solder balls over the UBM layer, the plurality of solder balls being arranged at some, but not all, intersections of a number of columns and rows of a ball pattern.2. The semiconductor device of claim 1 , wherein the plurality of solder balls comprises at least one connection ball and at least one dummy ball.3. The semiconductor device of claim 1 , wherein the columns and the rows are perpendicular to each other.4. The semiconductor device of claim 1 , wherein the ball pattern is free of any isolated balls claim 1 , wherein an isolated ball is a ball having at most one ball in an adjacent intersection of the columns and rows.5. The semiconductor device of claim 1 , wherein an intersection of the columns and rows in a corner of the ball pattern is free of any solder ball of the plurality of solder balls.6. The semiconductor device of claim 1 , further comprising a seed layer between the PPI layer and the UBM layer claim 1 , wherein the seed layer comprises at least one of aluminum claim 1 , copper alloy claim 1 , silver claim 1 , or gold.7. The ...

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28-01-2021 дата публикации

TIN OR TIN ALLOY PLATING SOLUTION AND BUMP FORMING METHOD

Номер: US20210025069A1
Автор: Tatsumi Koji
Принадлежит:

This tin or tin alloy plating solution includes a soluble salt including at least a stannous salt (A), an acid selected from an organic acid and an inorganic acid or a salt thereof (B), a surfactant (C), benzalacetone (D), and a solvent (E), wherein the plating solution is used to form a pattern in which bump diameters are different from each other on a base material, an amount of the benzalacetone (D) is 0.05 g/L to 0.2 g/L, a mass ratio (C/D) of the surfactant (C) to the benzalacetone (D) is 10 to 200, and a mass ratio (E/D) of the solvent (E) to the benzalacetone (D) is 10 or more. 1. A tin or tin alloy plating solution comprising:a soluble salt including at least a stannous salt (A);an acid selected from an organic acid and an inorganic acid or a salt thereof (B);a surfactant (C);benzalacetone (D); anda solvent (E),wherein the plating solution is used to form a pattern in which bump diameters are different from each other on a base material,the benzalacetone (D) is included in the plating solution in an amount of 0.1 g/L to 0.2 g/L,the solvent (E) is included in the plating solution in an amount of 5 g/L to 10 g/L,a mass ratio (C/D) of the surfactant (C) to the benzalacetone (D) is 50 to 200, anda mass ratio (E/D) of the solvent (E) to the benzalacetone (D) is 50 to 100.2. The tin or tin alloy plating solution according to claim 1 ,wherein the surfactant (C) is a nonionic surfactant obtained by condensing polyoxyethylene (EO) and polyoxypropylene (PO) or a nonionic surfactant obtained by condensing any one selected from phenol, alkylphenol, styrenated phenol, β-naphthol, bisphenols, and cumylphenol and polyoxyethylene (EO).3. A method for forming bumps claim 1 , the method comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a step of forming a plurality of tin or tin-alloy plated-deposited layers having different diameters on a base material using the tin or tin-alloy plating solution according to ; and'}a subsequent step of carrying out a reflow ...

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24-01-2019 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20190027455A1
Принадлежит:

To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged. 1. A semiconductor device comprising:(a) a semiconductor substrate of substantially rectangular shape having a pair of long edges and a pair of short edges;(b) an internal circuit including a plurality of MISFETs formed over the semiconductor substrate;(c) a plurality of protection elements formed over the semiconductor substrate so as to protect the internal circuit against static electricity;(d) a first insulating film formed over the semiconductor substrate so as to cover the plurality of MISFETs and the plurality of protection elements; and(e) a plurality of bump electrodes formed over the first insulating film, the plurality of bump electrodes being arranged along a first long edge of the pair of long edges,wherein the plurality of bump electrodes are bump electrodes for receiving input signals from an external device,wherein the plurality of protection elements are electrically coupled between the respective plurality of bump electrodes and the internal circuit,wherein the plurality of bump electrodes include a first bump electrode and a second bump electrode,wherein the plurality of protection elements include a first protection element and a second protection element,wherein the first protection element electrically coupled to the first bump electrode is disposed at a position overlapped with the first bump electrode in a planar view when ...

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23-01-2020 дата публикации

WAFER LEVEL INTEGRATION OF PASSIVE DEVICES

Номер: US20200027861A1
Автор: Zhai Jun
Принадлежит:

A semiconductor device is described that includes an integrated circuit coupled to a first semiconductor substrate with a first set of passive devices (e.g., inductors) on the first substrate. A second semiconductor substrate with a second set of passive devices (e.g., capacitors) may be coupled to the first substrate. Interconnects in the substrates may allow interconnection between the substrates and the integrated circuit. The passive devices may be used to provide voltage regulation for the integrated circuit. The substrates and integrated circuit may be coupled using metallization. 1. A semiconductor device , comprising:an integrated circuit comprising an active surface;a first metallization coupled to the active surface of the integrated circuit;a first semiconductor substrate attached to the integrated circuit with the first metallization, wherein the first semiconductor substrate comprises passive devices of a first type in the first semiconductor substrate, and wherein at least some of the capacitors are in contact with at least some of the first metallization;a second metallization coupled to the first semiconductor substrate; anda second semiconductor substrate attached to the first semiconductor substrate with the second metallization, wherein the second semiconductor substrate comprises passive devices of a second type in the second semiconductor substrate;wherein the passive devices of the first type and the passive devices of the second type are different types of passive devices.2. The device of claim 1 , wherein the passive devices of the first type are capacitors and the passive devices of the second type are inductors.3. The device of claim 1 , wherein the passive devices of the first type and the passive devices of the second type are connected to the integrated circuit to provide voltage regulation for the integrated circuit.4. The device of claim 1 , wherein an upper surface of the first semiconductor substrate is in contact with the first ...

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23-01-2020 дата публикации

Micro light emitting device and display apparatus

Номер: US20200028028A1
Принадлежит: Pixeled Display Co Ltd

A micro light emitting device including a component layer, a first electrode and a second electrode is provided. The component layer includes a main body and a protruding structure disposed on the main body. The first electrode is electrically connected to the component layer. The second electrode is electrically connected to the component layer. The first electrode, the second electrode and the protruding structure are disposed on the same side of the main body. The protruding structure is located between the first electrode and the second electrode. A connection between the first electrode and the second electrode traverses the protruding structure. The main body has a surface. The protruding structure has a first height with respect to the surface. Any one of the first electrode and the second electrode has a second height with respect to the surface. The relation 0.8≤H1/H2≤1.2 is satisfied, wherein H1 is the first height and H2 is the second height. A display apparatus having a plurality of micro light emitting devices is provided as well.

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17-02-2022 дата публикации

Semiconductor Die Package and Method of Manufacture

Номер: US20220052009A1

In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

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30-01-2020 дата публикации

Semiconductor Bonding Structures and Methods

Номер: US20200035510A1
Принадлежит:

A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill. 1. A method of manufacturing a semiconductor device , the method comprising:applying an underfill material to a substrate;patterning the underfill material to form a first opening through the underfill material and a second opening through the underfill material, wherein the first opening has a first width, the second opening has a second width, and the first width is different from the second width; andafter the patterning the underfill material, bonding a first semiconductor die to the substrate through the first opening and bonding a first package to the substrate through the second opening.2. The method of claim 1 , wherein the first width is between about 10 μm and about 100 μm.3. The method of claim 2 , wherein the second width is between about 50 μm and about 400 μm.4. The method of claim 1 , further comprising partially curing the underfill material prior to the patterning the underfill material.5. The method of claim 4 , further comprising curing the underfill material after the bonding the first semiconductor die.6. The method of claim 1 , further comprising forming external connectors to the substrate claim 1 , wherein the external connectors are located on an opposite side of the substrate from the first semiconductor die.7. A method of manufacturing a semiconductor device claim 1 , the method comprising:removing a first portion of an underfill material to expose a first portion of a substrate;removing a second portion of the underfill material to expose a second portion of the substrate;after the removing the first portion of the underfill ...

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12-02-2015 дата публикации

SEMICONDUCTOR DEVICES INCLUDING UNITARY SUPPORTS

Номер: US20150041973A1
Принадлежит:

A semiconductor device includes a plurality of cylindrical structures located at vertices and central points of a plurality of hexagons in a honeycomb pattern, and a unitary support having a plurality of openings. Each of the openings exposes a part each of four of the cylindrical structures. Each of the openings has the shape of a parallelogram or an oval substantially. A first distance between opposite cylindrical structures of a first pair of the four cylindrical structures exposed by each opening is shorter than a second distance between opposite cylindrical structures of a second pair of the four cylindrical structures exposed by the opening. The first distance is equal to a distance between the central point and each of the vertices of the hexagon. 1. A semiconductor device comprising:a two-dimensional horizontal array of cylindrical structures, the cylindrical structures being disposed at vertices and central points of a plurality of hexagons, respectively, wherein the hexagons have the pattern of a honeycomb; anda contiguous support spanning the cylindrical structures horizontally so as to support the cylindrical structures, the support having a two-dimensional horizontal array of openings therethrough, each of the openings exposing respective parts each of four of the cylindrical structures,wherein the plurality of hexagons, having the pattern of a honeycomb, include first to seventh hexagons,wherein six vertices of the first hexagon coincide with respective ones of six central points of the second to seventh hexagons, and the central point of the first hexagon coincides with one vertex of each of the second to seventh hexagons,wherein the shape of each of the openings as viewed from above is substantially that of a parallelogram shape or an oval, andwherein the four cylindrical structures exposed by each of the openings include a first pair of the four cylindrical structures disposed opposite one another across the opening and a second pair of the four ...

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04-02-2021 дата публикации

BUMP STRUCTURE HAVING A SIDE RECESS AND SEMICONDUCTOR STRUCTURE INCLUDING THE SAME

Номер: US20210035938A1
Принадлежит:

The present disclosure relates to an integrated chip structure having a first copper pillar disposed over a metal pad of an interposer substrate. The first copper pillar has a sidewall defining a recess. A nickel layer is disposed over the first copper pillar and a solder layer is disposed over the first copper pillar and the nickel layer. The solder layer continuously extends from directly over the first copper pillar to within the recess. A second copper layer is disposed between the solder layer and a second substrate. 1. An integrated chip structure , comprising:a first copper pillar disposed over a metal pad of an interposer substrate, wherein the first copper pillar has a sidewall defining a recess;a nickel layer disposed over the first copper pillar;a solder layer disposed over the first copper pillar and the nickel layer, wherein the solder layer continuously extends from directly over the first copper pillar to within the recess; anda second copper layer disposed between the solder layer and a second substrate.2. The integrated chip structure of claim 1 , wherein the first copper pillar has a width that is between about 10 microns and about 200 microns.3. The integrated chip structure of claim 1 , wherein the first copper pillar has a width that is between about 25 microns and about 50 microns.4. The integrated chip structure of claim 1 , wherein the sidewall of the first copper pillar defining the recess is a curved surface.5. The integrated chip structure of claim 1 , wherein the recess has a depth of between about 1 micron and about 15 microns.6. The integrated chip structure of claim 1 ,wherein the recess has a depth; andwherein a ratio of the depth to an overall width of the first copper pillar is in a range from about 0.05 to about 0.2.7. The integrated chip structure of claim 1 , wherein the solder layer has a height of between about 10 microns and about 50 microns.8. The integrated chip structure of claim 1 , wherein the first copper pillar is ...

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09-02-2017 дата публикации

SEMICONDUCTOR DEVICE HAVING CONDUCTIVE VIAS

Номер: US20170040277A1
Принадлежит:

A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield. 112-. (canceled)13. A semiconductor device , comprising:a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces;an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom;a redistribution layer formed on the end portions of the conductive vias and the insulating layer;a dielectric layer formed on the insulating layer and the redistribution layer and having a dielectric layer opening exposing a portion of the redistribution layer; anda buffer layer formed on the dielectric layer at a periphery of the dielectric layer opening.14. The semiconductor device of claim 13 , further comprising an under bump metallurgy formed on the exposed portion of the redistribution layer and formed between the dielectric layer and the buffer layer claim 13 , wherein the buffer layer exposes a portion of the under bump metallurgy.15. The semiconductor device of claim 14 , further comprising a plurality of conductive bumps formed on the buffer layer and the exposed portion of the under bump metallurgy.16. The semiconductor device of claim 13 , wherein the buffer layer is further formed at a periphery of the insulating layer. 1. Field of the InventionThis invention relates to semiconductor devices, and, more particularly, to a semiconductor device having conductive vias.2. Description of Related ArtWith the constantly progressing of electronic industry, more and more electronic ...

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09-02-2017 дата публикации

PRINTED CIRCUIT BOARD (PCB), METHOD OF MANUFACTURING THE PCB, AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE USING THE PCB

Номер: US20170040293A1
Принадлежит:

Provided are a printed circuit board (PCB) capable of blocking introduction of impurities during a molding process so as to reduce damage on a semiconductor package, a method of manufacturing the PCB, and a method of manufacturing a semiconductor package by using the PCB. An embodiment includes an apparatus comprising: a substrate body comprising an active area and a dummy area on an outer portion of the active area, the substrate body extending lengthwise in a first direction; a plurality of semiconductor units mounted on the active area; and a barrier formed on the dummy area, wherein the barrier extends in the first direction. 1. An apparatus , comprising:a substrate body comprising an active area and a dummy area on an outer portion of the active area, the substrate body extending lengthwise in a first direction;a plurality of semiconductor units mounted on the active area; anda barrier formed on the dummy area,wherein the barrier extends in the first direction.2. The apparatus of claim 1 , wherein the barrier comprises at least one row of solder balls disposed on the dummy area.3. The apparatus of claim 1 , wherein the barrier comprises at least two rows of solder balls claim 1 , and solder balls of one of the at least two rows are offset in the first direction from solder balls in at least one other row of the at least two rows.4. The apparatus of claim 1 , wherein the barrier comprises at least two rows of solder balls claim 1 , and solder balls of one of the at least two rows are larger than solder balls in at least one other row of the at least two rows.5. The apparatus of claim 1 , wherein the barrier has a structure comprising at least one continuous wall or at least one row of separated walls.6. The apparatus of claim 1 , wherein:the barrier comprises at least one row of first solder balls; andthe substrate body further comprises second solder balls disposed on the active area; andheights of the first solder balls from an upper surface of the substrate ...

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09-02-2017 дата публикации

Semiconductor device assembly with through-package interconnect and associated systems, devices, and methods

Номер: US20170040303A1
Автор: Chan Yoo, Todd O. Bolken
Принадлежит: Micron Technology Inc

Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.

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08-02-2018 дата публикации

Semiconductor package including a rewiring layer with an embedded chip

Номер: US20180040548A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.

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08-02-2018 дата публикации

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Номер: US20180040579A1
Автор: Saito Hirokazu
Принадлежит:

The present disclosure provides a semiconductor device including: a substrate including, in a central portion the substrate, n first element formation regions having a rectangular shape and are arrayed along a first direction, and n+m second element formation regions arrayed along the first direction adjacent to the first element formation regions; plural projecting electrodes formed at each of the first and the second element formation regions; and plural dummy projecting electrodes formed, at a peripheral portion, overlapping a triangle defined by a first edge of the first element formation region that forms a boundary between the first element formation region and the peripheral portion, and a second edge of the second element formation region that is adjacent to a corner of the first edge and that forms a boundary between the second element formation region and the peripheral portion. 1. A semiconductor device comprising:a substrate including, in a central portion of a main face of the substrate, n first element formation regions having a rectangular flat plane shape and arrayed along a first direction, and n+m second element formation regions having the same shape as the first element formation regions and arrayed along the first direction and adjacent to the first element formation regions in a second direction intersecting the first direction;a plurality of projecting electrodes formed at each of the first element formation regions and at each of the second element formation regions;a first row of dummy projecting electrodes arrayed, at a peripheral portion of the main face, in the second direction along a first edge of the first element formation regions that forms a boundary between the first element formation regions and the peripheral portion; anda second row of dummy projecting electrodes arrayed, at a peripheral portion of the main face, in the first direction along a second edge of the second element formation regions that forms a boundary between the ...

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08-02-2018 дата публикации

SEMICONDUCTOR DEVICE, DISPLAY PANEL ASSEMBLY, SEMICONDUCTOR STRUCTURE

Номер: US20180040596A1
Принадлежит: NOVATEK MICROELECTRONICS CORP.

A semiconductor device includes a chip, a plurality of first bumps, and a plurality of second bumps. The chip includes an active surface. The first bumps are disposed on the active surface along a first direction. The second bumps are disposed on the active surface along a second direction parallel to the first direction, wherein one of the second bumps is located between adjacent two of the first bumps, a closest distance from the second bumps to the fan-out region is smaller than a closest distance from the first bumps to the fan-out region, and a first width of one of the first bumps is larger than a second width of one of the second bumps. 1. A semiconductor device , comprising:a chip comprising an active surface, wherein the chip is configured to be disposed on a flexible circuit film, the flexible circuit film comprises a fan-out region, a chip region and at least one cut-out opening, and the fan-out region and the cut-out opening are located at two opposite sides of the chip region respectively;a plurality of first bumps disposed on the active surface along a first direction; anda plurality of second bumps, disposed on the active surface along a second direction parallel to the first direction, wherein one of the second bumps is located between adjacent two of the first bumps, and a first width of one of the first bumps is larger than a second width of one of the second bumps.2. (canceled)3. The semiconductor device as claimed in claim 1 , wherein the flexible circuit film comprises a plurality of traces extended from the chip region to the fan-out region claim 1 , the chip is disposed on the chip region and the first bumps and the second bumps are electrically connected to the traces.4. The semiconductor device as claimed in claim 3 , wherein a closest distance from the second bumps to the fan-out region is smaller than a closest distance from the first bumps to the fan-out region.5. The semiconductor device as claimed in claim 3 , wherein a first portion of ...

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04-02-2021 дата публикации

Printed wiring board and method for manufacturing printed wiring board

Номер: US20210037660A1
Автор: Satoru Kawai
Принадлежит: Ibiden Co Ltd

A printed wiring board includes a base insulating layer, a conductor layer formed on the base layer and including first and second pads, a solder resist layer formed on the base layer such that the solder resist layer has first opening exposing the first pad and second opening exposing the second pad with diameter smaller than diameter of the first opening, and bumps including a first bump on the first pad and a second bump on the second pad such that the second bump has diameter smaller than diameter of the first bump. The first bump has a base plating layer formed in the first opening and having raised portion, and a top plating layer formed on the base plating layer, and the second bump has a base plating layer formed in the second opening and having raised portion, and a top plating layer formed on the base plating layer.

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24-02-2022 дата публикации

BUMP COPLANARITY FOR SEMICONDUCTOR DEVICE ASSEMBLY AND METHODS OF MANUFACTURING THE SAME

Номер: US20220059485A1
Автор: Lin Ko Han, Tsai Tsung Che
Принадлежит:

Improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. The additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. Subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity. 1. A semiconductor die , comprising:a passivation layer including a dielectric layer over a bond pad and a polyimide layer over the dielectric layer;a first opening in the passivation layer, the first opening extending from a surface of the passivation layer to a surface of the bond pad;a first conductive pillar disposed within the first opening, the first conductive pillar connected to the bond pad and having a first height above the surface of the passivation layer;a second opening in the passivation layer, the second opening extending from the surface of the passivation layer past the polyimide layer; anda second conductive pillar disposed within the second opening, the second conductive pillar having a second height above the surface of the passivation layer, wherein a difference between the first and second heights is less than or equal to a predetermined value.2. The semiconductor die of claim 1 , wherein the predetermined value is greater than or equal to five (5) and less than or equal to seven (7) micrometers.3. The semiconductor die of claim 1 , wherein:the first opening has a first depth; andthe second opening has a second depth less than the ...

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24-02-2022 дата публикации

COPLANAR BUMP CONTACTS OF DIFFERING SIZES

Номер: US20220059486A1
Автор: SU Cheng-Yang
Принадлежит: STMicroelectronics Ltd

The present disclosure is directed to a die including a first contact with a first shape (e.g., a ring-shape contact) and second contact with a second shape different from the first shape (e.g., a cylindrical-shape contact). The first contact has an opening that extends through a central region of a surface of the first contact. A first solder portion is coupled to the surface of the first contact and the first solder portion has the first shape. A second solder portion is coupled to a surface of the second contact and the second solder portion has the second shape. The first solder portion and the second solder portion both have respective points furthest away from a substrate of the die. These respective points of the first solder portion and the second solder portion are co-planar with each other such that a standoff height of the die remains consistent when coupled to a PCB or an electronic component. 1. A device , comprising:a substrate having a first surface; a second surface facing away from the substrate;', 'an opening extending towards the substrate;', 'an interior sidewall that surrounds the opening; and', 'an exterior sidewall that surrounds the opening, the interior sidewall, and the second surface., 'a ring-shaped conductive structure on the substrate, the ring-shaped conductive structure extending away from the substrate, the ring-shaped conductive structure including2. The device of claim 1 , wherein the second surface of the ring-shaped conductive structure extends between and separates the interior sidewall and the exterior sidewall.3. The device of claim 1 , wherein a ring-shaped solder portion is on the second surface of the ring-shaped conductive structure.4. The device of claim 1 , further comprising a cylindrical conductive structure on the first surface of the substrate claim 1 , the cylindrical conductive structure extending away from the first surface of the substrate claim 1 , the cylindrical conductive structure includes:a third surface ...

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07-02-2019 дата публикации

Semiconductor package with high routing density patch

Номер: US20190043829A1
Принадлежит: Amkor Technology Inc

Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.

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18-02-2016 дата публикации

SEMICONDUCTOR DEVICES AND PACKAGE SUBSTRATES HAVING PILLARS AND SEMICONDUCTOR PACKAGES AND PACKAGE STACK STRUCTURES HAVING THE SAME

Номер: US20160049377A1
Принадлежит:

A semiconductor device, a semiconductor package, and a package stack structure include a semiconductor substrate, a first bonding pad disposed on a first surface of the semiconductor substrate, and a first pillar disposed on the first bonding pad. An upper surface of the first pillar has a concave shape. Side surfaces of the first pillar are substantially planar. 1. A semiconductor device , comprising:a semiconductor substrate comprising a first surface;one or more first bonding pads disposed on the first surface of the semiconductor substrate; anda first pillar disposed on at least one first bonding pad, an upper surface of the first pillar comprising a concave shape and a side surface of the first pillar being substantially planar.2. The semiconductor device according to claim 1 , further comprising:one or more through-substrate vias penetrating the semiconductor substrate, at least one through-substrate via being aligned with the at least one first bonding pad.3. The semiconductor device according to claim 2 , wherein the semiconductor substrate comprises a second surface opposite the first surface claim 2 ,the semiconductor device further comprising:one or more second bonding pads disposed on the second surface, andwherein at least one second bonding pad is electrically connected with a corresponding first bonding pad by the through-substrate via.4. The semiconductor device according to claim 3 , further comprising a second pillar disposed on the at least one second bonding pad.5. The semiconductor device according to claim 4 , wherein the second pillar comprises a concave upper surface claim 4 , and substantially planar side surfaces.6. The semiconductor device according to claim 1 , further comprising:a solder ball disposed on the first pillar, a vertical height of the solder ball being greater than a horizontal width of the solder ball.7. The semiconductor device according to claim 6 , wherein the first pillar comprises copper and/or nickel.8. The ...

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16-02-2017 дата публикации

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS

Номер: US20170047266A1
Принадлежит:

A semiconductor device includes a substrate and a semiconductor element mounted on the top surface of the substrate. On the top surface of the substrate, one or more pads are disposed outside the mounted semiconductor element when seen in a plan view. Then, a protrusion is disposed on each of the pads. A heat sink is disposed above the semiconductor element and the protrusions, and then bonded to the substrate by an adhesive provided between the heat sink and the substrate. The adhesive is provided in such a manner as to be in contact with the protrusions on the substrate. 1. A semiconductor device comprising:a substrate;a semiconductor element mounted on a first surface of the substrate;a first pad disposed on the first surface and outside of the semiconductor element in a plan view;a first protrusion disposed on the first pad;a heat sink disposed above the semiconductor element and the first protrusion; anda first adhesive disposed between the first surface and the heat sink to bond the first protrusion and the heat sink.2. The semiconductor device according to claim 1 , wherein:the first pad, the first protrusion, and the first adhesive are electrically conductive respectively, andthe first pad is electrically connected to the heat sink through the first protrusion and the first adhesive.3. The semiconductor device according to claim 1 , wherein:the heat sink includes a flat surface opposing the first surface.4. The semiconductor device according to claim 1 , wherein:the first protrusion is disposed away from the heat sink.5. The semiconductor device according to claim 1 , wherein:the first protrusion is contact with the heat sink.6. The semiconductor device according to claim 1 , further comprising a bump disposed between the semiconductor element and the first surface claim 1 ,wherein size of the first protrusion is same as size of the bump.7. The semiconductor device according to claim 1 , further comprising a second adhesive that includes a first part ...

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15-02-2018 дата публикации

Method and System for Packing Optimization of Semiconductor Devices

Номер: US20180047692A1
Принадлежит:

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently. 1. A substrate comprising interconnects , wherein the interconnects comprise edge interconnects along edges of the substrate , and at least one of the edges is a rounded non-linear edge.2. The substrate of claim 1 , wherein the interconnects comprise a plurality of non-circular interconnects with a major axis and a minor axis.3. The substrate of claim 2 , wherein the major axis of at least one of the plurality of non-circular interconnects is substantially perpendicular to: a radial axis of the substrate claim 2 , or to a line that is parallel to a radial axis of the substrate.4. The substrate of claim 1 , wherein the edge interconnects are configured to form interconnects that hang over a corresponding edge when solder of the substrate is reflowed.5. The substrate of claim 1 , wherein a perimeter of the substrate tracks a contour of individual ones of the edge interconnects.6. The substrate of claim 1 , comprising:a first row of horizontally aligned first interconnects; anda second row of second interconnects that are immediately below the first row of first interconnects, the first row is parallel to the second row,', 'the first interconnects have a first pitch,', 'the second interconnects have the first pitch,', 'a first line through a center of each of the first interconnects is parallel to a second line through a center of each of the second interconnects, and', 'the first pitch is different than a vertical distance from the first line to the second line., 'wherein7. A substrate comprising interconnects claim 1 , wherein:a plurality of the interconnects are non-circular interconnects, and each non-circular interconnect has a major axis and a minor axis,a first substrate axis extends from a center of the substrate to a perimeter of the substrate; anda first row of the ...

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16-02-2017 дата публикации

CHIPLETS WITH CONNECTION POSTS

Номер: US20170048976A1
Принадлежит:

A component includes a plurality of electrical connections on a process side opposed to a back side of the component. Each electrical connection includes an electrically conductive multi-layer connection post protruding from the process side. A printed structure includes a destination substrate and one or more components. The destination substrate has two or more electrical contacts and each connection post is in contact with, extends into, or extends through an electrical contact of the destination substrate to electrically connect the electrical contacts to the connection posts. The connection posts or electrical contacts are deformed. Two or more connection posts can be electrically connected to a common electrical contact. 1. A printable component , comprising:a chiplet having a semiconductor substrate; anda plurality of electrical connections, wherein each electrical connection comprises an electrically conductive connection post protruding from the semiconductor substrate, wherein the connection post is a multi-layer connection post.2. The printable component of claim 1 , wherein the connection post comprises a bulk material coated with a conductive material different from the bulk material.3. The printable component of claim 2 , wherein the bulk material is electrically conductive.4. The printable component of claim 2 , wherein the conductive material has a melting point less than the melting point of the bulk material.5. The printable component of claim 2 , wherein the bulk material is an electrical insulator.6. The printable component of claim 2 , wherein the bulk material is a resin claim 2 , a polymer claim 2 , or a cured resin.7. The printable component of claim 2 , wherein the bulk material is softer than the conductive material.8. The printable component of claim 2 , wherein the conductive material is softer than the bulk material.923-. (canceled)24. A printed structure comprising a destination substrate and one or more printable components claim 2 , ...

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26-02-2015 дата публикации

Electronic device

Номер: US20150054178A1
Принадлежит: Murata Manufacturing Co Ltd

An electronic device includes a surface-mounted component and a mounting component on which the surface-mounted component is mounted, the surface-mounted component includes a first bump and a second bump, a cross-sectional area of which in an in-plane direction of a surface facing the mounting component is larger than that of the first bump, on the surface facing the mounting component, the mounting component includes a first pad that is soldered to the first bump and a second pad soldered to the second bump on the surface facing the surface-mounted component, and a ratio of an area of the second pad to the cross-sectional area of the second bump is larger than a ratio of an area of the first pad to the cross-sectional area of the first bump.

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03-03-2022 дата публикации

SEMICONDUCTOR PACKAGE WITH HYBRID THROUGH-SILICON-VIAS

Номер: US20220068764A1
Принадлежит:

According to various examples, a device is described. The device may include an interposer. The device may also include a plurality of first through-silicon-vias disposed in the interposer, wherein the plurality of first through-silicon-vias have a first diameter. The device may also include a plurality of second through-silicon-vias disposed in the interposer, wherein the plurality of second through-silicon-vias have a second diameter larger than the first via diameter. The device may also include a first recess in the interposer positioned at bottom ends of the plurality of second through-silicon-vias.

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03-03-2022 дата публикации

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE SAME

Номер: US20220068865A1
Автор: HUANG Hsin He

A semiconductor device includes a semiconductor die having a first surface and a second surface opposite to the first surface, a plurality of first real conductive pillars in a first region on the first surface, and a plurality of supporters in a second region adjacent to the first region. An area density of the plurality of supporters in the second region is in a range of from about 50% to about 100% to an area density of the plurality of first real conductive pillars in the first region. A method for manufacturing a semiconductor package including the semiconductor device is also disclosed in the present disclosure. 1. A semiconductor device , comprising:a semiconductor die having a surface;a first real conductive pillar in a first region on the surface;a supporter in a second region adjacent to the first region; anda conductive wiring layer electrically coupled to the first real conductive pillar.2. The semiconductor device of claim 1 , wherein the second region is around the first region.3. The semiconductor device of claim 1 , further comprising a plurality of the supporters and a plurality of the first real conductive pillars claim 1 , wherein a pitch of the supporters is substantially the same as a pitch of the first real conductive pillars.4. The semiconductor device of claim 1 , further comprising a plurality of the first real conductive pillars claim 1 , wherein a pitch of the first real conductive pillars is substantially the same as a smallest distance between the supporter and the first real conductive pillar adjacent to the supporter.5. The semiconductor device of claim 1 , wherein an upper surface of the supporter substantially aligns to an upper surface of the first real conductive pillars.6. The semiconductor device of claim 5 , further comprising an encapsulant encapsulating the semiconductor die and a lateral surface of the supporter.7. The semiconductor device of claim 1 , wherein the semiconductor die comprises a bridge trace below the supporter ...

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25-02-2016 дата публикации

Dual side solder resist layers for coreless packages and packages with an embedded interconnect bridge and their methods of fabrication

Номер: US20160056102A1
Принадлежит: Individual

A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.

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25-02-2016 дата публикации

Fabricating pillar solder bump

Номер: US20160056116A1
Принадлежит: International Business Machines Corp

A substrate bonding method is able to reliably bond substrates while avoiding a reduction in yield made worse by finer pitches. The substrate bonding method can include: forming an adhesive resin layer on a surface of a first substrate on which a pad has been formed; forming an opening on the adhesive resin layer above the pad; filling the opening with molten solder to form a pillar-shaped solder bump; and applying heat and pressure to the first substrate and a second substrate while a terminal formed on the second substrate is aligned with the solder bump.

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22-02-2018 дата публикации

Land grid based multi size pad package

Номер: US20180053740A1
Принадлежит: Qualcomm Inc

The present disclosure provides packages and methods for fabricating packages. A package may comprise a wafer-level package (WLP) layer comprising first and second WLP contacts and first and second conductive pillars disposed on the first and second WLP contacts. Each conductive pillar may comprise a surface opposite the WLP contact that forms an array pad. The array pads may have different sizes. The package may further comprise a mold over the WLP layer and at least partially surrounding the conductive pillars, wherein the mold compound and the first array pads form a substantially planar LGA contact surface that is configured to couple the package to a land grid array.

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22-02-2018 дата публикации

Bump structure having a side recess and semiconductor structure including the same

Номер: US20180053741A1

In some embodiments, the present disclosure relates to a method of integrated chip bonding. The method is performed by forming a metal layer on a substrate, and forming a solder layer on the metal layer. The solder layer is reflowed. The metal layer and the solder layer have sidewalls defining a recess that is at least partially filled by the solder layer during reflowing of the solder layer.

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15-05-2014 дата публикации

Solder fatigue arrest for wafer level package

Номер: US20140131859A1
Принадлежит: Maxim Integrated Products Inc

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

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25-02-2021 дата публикации

Sawing Underfill in Packaging Processes

Номер: US20210057383A1

A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

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25-02-2021 дата публикации

Light-emitting device, manufacturing method thereof and display module using the same

Номер: US20210057395A1
Принадлежит: Epistar Corp

The application discloses a light-emitting device including a carrier which includes an insulating layer, an upper conductive layer formed on the insulating layer, a plurality of conducting vias passing through the insulating layer, and a lower conductive layer formed under the insulating layer; four light-emitting elements arranged in rows and columns flipped on the carrier; and a light-passing unit formed on the carrier and covering the four light-emitting elements; wherein each of the light-emitting elements including a first light-emitting bare die emitting a first dominant wavelength, a second light-emitting bare die emitting a second dominant wavelength, and a third light-emitting bare die emitting a third dominant wavelength; and wherein two adjacent first light-emitting bare die in a row has a first distance W1, two adjacent first light-emitting bare die in a column has a second distance W2, and W1 is the same as W2.

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23-02-2017 дата публикации

TALL AND FINE PITCH INTERCONNECTS

Номер: US20170053886A1
Принадлежит: INVENSAS CORPORATION

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers. 1. A method , comprising:applying a conductive layer to a carrier;forming patterned interconnect structures comprising reflowable conductive material on a surface of the conductive layer;etching the conductive layer to remove portions of the conductive layer to form a patterned conductive structure, such that at least portions of the conductive layer covered by the patterned interconnect structures are not removed;mounting a first microelectronic element to the patterned interconnect structures;removing the carrier; andmounting a second microelectronic element with interconnect structures onto the patterned conductive structure, on a side previously occupied by the carrier.2. The method of claim 1 , further comprising coupling the conductive layer to the carrier using a temporary adhesive.3. The method of claim 1 , further comprising screen printing the reflowable conductive material onto the conductive layer to form the patterned interconnect structures.4. The method of claim 1 , further comprising etching the conductive layer and the reflowable conductive material during a same process to form the patterned interconnect structures and the patterned conductive structure concurrently.5. The method of claim 1 , further comprising coupling the first microelectronic element to the patterned interconnect structures via heated reflow.6. The method of claim 1 , further comprising coupling the second microelectronic element to the patterned conductive structure via ...

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23-02-2017 дата публикации

Semiconductor device

Номер: US20170053900A1
Автор: Hironori KAWAMINAMI
Принадлежит: Fujitsu Ltd

A semiconductor device includes a first semiconductor chip including plural circuit blocks provided on a semiconductor substrate, and plural through-silicon vias that are arranged so as to surround the outer periphery of each of the plural circuit blocks and that penetrate the semiconductor substrate, and a second semiconductor chip that is stacked on the first semiconductor chip, and that is supplied with a power source through the plural through-silicon vias.

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13-02-2020 дата публикации

HIGH FREQUENCY MODULE AND COMMUNICATION DEVICE

Номер: US20200051941A1
Принадлежит:

A high frequency module includes a transmission power amplifier, a bump electrode connected to a principal surface of the transmission power amplifier and having an elongated shape in a plan view of the principal surface, and a mounting board on which the transmission power amplifier is mounted, wherein the mounting board includes a via conductor having an elongated shape in the plan view, the length direction of the bump electrode and the length direction of the via conductor are aligned in the plan view, and the bump electrode and the via conductor are connected in an overlapping area where the bump electrode and the via conductor overlap at least partially in the plan view, and the overlapping area is an area elongated in the length direction. 1. A high frequency module comprising:a high frequency component;a first bump electrode connected to the high frequency component, the first bump electrode having an elongated shape in a plan view of the high frequency component; anda mounting board on which the high frequency component is mounted, whereinthe mounting board includes a via conductor having an elongated shape in a plan view of the mounting board,a length direction of the first bump electrode and a length direction of the via conductor are aligned in the plan view, and the first bump electrode and the via conductor are connected in an overlapping area where the first bump electrode and the via conductor overlap at least partially in the plan view, andthe overlapping area is an area elongated in the length direction.2. The high frequency module according to claim 1 , whereinthe high frequency component is at least one of a power amplifier, a low-noise amplifier, and a filter connected to an output terminal of a power amplifier.3. The high frequency module according to claim 1 , whereinthe high frequency component is a power amplifier and includes a bipolar transistor having a base terminal, a collector terminal, and an emitter terminal, in which a drive current ...

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13-02-2020 дата публикации

RADIO-FREQUENCY MODULE AND COMMUNICATION DEVICE

Номер: US20200051942A1
Принадлежит:

A radio-frequency module includes: a transmission power amplifier that includes first and second amplification transistors that are cascade connected to each other; and a mounting substrate that has first and second main surface that face each other, the transmission power amplifier being mounted on the first main surface. The first amplification transistor is arranged in a final stage and has a first emitter terminal. The second amplification transistor is arranged in a stage preceding the first amplification transistor and has a second emitter terminal. The mounting substrate has first to fourth ground electrode layers in order of proximity to the first main surface. The first emitter terminal and the second emitter terminal are not electrically connected to each other via an electrode on the first main surface and are not electrically connected to each other via the first ground electrode layer. 1. A radio-frequency module comprising:a power amplifier composed of a plurality of cascade-connected amplification elements; anda mounting substrate having a first main surface and a second main surface that face each other, the power amplifier being mounted on the first main surface;wherein the plurality of amplification elements includes a first amplification element arranged in a final stage of the plurality of amplification elements and having a first ground terminal, anda second amplification element arranged in a stage preceding the first amplification element and having a second ground terminal,an inside of the mounting substrate includes a plurality of ground electrode layers substantially parallel to the first main surface and having first to nth ground electrode layers in order of proximity to the first main surface, wherein n is an integer greater than or equal to 2 andthe first ground terminal and the second ground terminal are not electrically connected to each other via an electrode on the first main surface of the mounting substrate and are not ...

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05-03-2015 дата публикации

Stack packages and methods of manufacturing the same

Номер: US20150061120A1
Принадлежит: SK hynix Inc

Embodiments of a stack package may include an upper chip on a lower chip, a backside passivation layer covering the backside surface of the lower chip and having a thickness which is substantially equal to a height of the protrusion portion of a lower through via electrode, a backside bump substantially contacting the protrusion portion, and a front side bump electrically connected to a chip contact portion of the upper chip and physically and electrically connected to the backside bump. The backside passivation layer may include a first insulation layer provided over a sidewall of the protrusion portion and the backside surface of the lower chip. Embodiments of fabrication methods are also disclosed.

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05-03-2015 дата публикации

Bump Electrode, Board Which Has Bump Electrodes, and Method for Manufacturing the Board

Номер: US20150061129A1
Принадлежит: SENJU METAL INDUSTRY CO., LTD.

A bump electrode is formed on an electrode pad using a Cu core ball in which a core material is covered with solder plating, and a board which has bump electrodes such as semiconductor chip or printed circuit board mounts such a bump electrode. Flux is coated on a substrate and the bump electrodes are then mounted on the electrode pad. In a step of heating the electrode pad and the Cu core ball to melt the solder plating, a heating rate of the substrate is set to have not less than 0.01° C./sec and less than 0.3. 1. A bump electrode formed on an electrode pad with a solder joint in which a core material that becomes a core is covered with solder plating , wherein the solder joint is configured so as to have a heating rate of 0.01° C./sec or more and less than 0.3° C./sec in a step of heating and melting the solder plating after the solder joint has been mounted on the electrode pad.2. A board which has a bump electrode , the board comprising:a substrate;an electrode pad provided on the substrate; and{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the bump electrode according to that is joined with the electrode pad.'}3. A method for manufacturing a board which has a bump electrode , the method comprising the steps of:mounting a solder joint in which a core material that becomes a core is covered with solder plating on an electrode pad of a substrate; andheating the substrate to melt the solder plating that is covered over the core material, wherein a heating rate of the substrate is configured so as to have not less than 0.01° C./sec and less than 0.3° C./sec in the step of heating and melting the solder plating.4. The method for manufacturing a board which has a bump electrode according to wherein when mounting the solder joint on the electrode pad claim 3 , flux is used. The present invention contains subject matter related to Japanese Patent Application No. 2013-182296 filed in the Japanese Patent Office on Sep. 3, 2013, the entire contents of which being ...

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01-03-2018 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20180061798A1
Принадлежит:

A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint coupled with and standing on the first pad, a joint encapsulating the post and bonding the first pad with the second pad, a first entire contact interface between the first pad and the joint, a second entire contact interface between the first pad and the post, and a third entire contact interface between the joint and the second pad. The first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces. A distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface. The second entire contact interface is a continuous surface. 1. A semiconductor device , comprising:a silicon substrate;a carrier;a first pad on the silicon substrate;a second pad on the carrier;a post on a surface of the first pad, wherein the post consists of a metal or a metal alloy;a joint disposed between the silicon substrate and the carrier, contacted with the first pad and the second pad, and encapsulating the post;a first entire contact interface between the first pad and the joint;a second entire contact interface between the first pad and the post; anda third entire contact interface between the joint and the second pad,wherein an outer surface of the joint is concaved and curved towards the post, and a height of the post is greater than or equal to ⅓ of a height of the joint between the first pad and the second pad, the first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces, wherein a distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface, ...

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02-03-2017 дата публикации

Semiconductor device

Номер: US20170062301A1
Автор: Hiroshi Okumura
Принадлежит: ROHM CO LTD

A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1 , a first electrode pad 21 laminated on the semiconductor chip 1 , an intermediate layer 4 having a rectangular shape defined by first edges 49 a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1 . The first edges 49 a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21 . The first bump 51 is arranged at one end in the direction x and one end in the direction y.

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02-03-2017 дата публикации

BUMP STRUCTURE HAVING A SIDE RECESS AND SEMICONDUCTOR STRUCTURE INCLUDING THE SAME

Номер: US20170062371A1
Принадлежит:

In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure may have a first conductive structure and a second conductive structure arranged over a first substrate. A bump structure is arranged between the first conductive structure and a second substrate. A solder layer is configured to electrically couple the first conductive structure and the bump structure. The bump structure has a recess that is configured to reduce a protrusion of the solder layer in a direction extending from the first conductive structure to the second conductive structure. 1. A semiconductor structure , comprising:a first conductive structure and a second conductive structure arranged over a first substrate;a bump structure arranged between the first conductive structure and a second substrate; anda solder layer configured to electrically couple the first conductive structure and the bump structure, wherein the bump structure comprises a recess configured to reduce a protrusion of the solder layer in a direction extending from the first conductive structure to the second conductive structure.2. The semiconductor structure of claim 1 , wherein the recess straddles a line that extends through a center of the bump structure along the direction extending from the first conductive structure to the second conductive structure.3. The semiconductor structure of claim 1 ,wherein the bump structure has a recessed side facing the second conductive structure, which comprises the recess; andwherein the bump structure has a non-recessed side facing away from the second conductive structure, which does not have a recess.4. The semiconductor structure of claim 2 , further comprising:an under-bump metallurgy (UBM) layer arranged between the second substrate and the bump structure, wherein an outer sidewall of the UBM layer is linearly aligned with the non-recessed side of the bump structure.5. The semiconductor structure of claim 1 , wherein the recess has a ...

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04-03-2021 дата публикации

Multiple ball grid array (bga) configurations for a single integrated circuit (ic) package

Номер: US20210066178A1
Принадлежит: Intel Corp

An integrated circuit package may include a semiconductor die on a first side of the integrated circuit package, a first ball grid array (BGA) connection on the first side of the integrated circuit package, and a second BGA connection on a second side of the integrated circuit package. The integrated circuit package may include one or more traces that route data from the first BGA connection and the second BGA connection.

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04-03-2021 дата публикации

INTERCONNECT FOR ELECTRONIC DEVICE

Номер: US20210066229A1
Принадлежит:

A semiconductor die includes a substrate and an integrated circuit provided on the substrate and having contacts. An electrically conductive layer is provided on the integrated circuit and defines electrically conductive elements electrically connected to the contacts. Electrically conductive interconnects coupled with respective electrically conductive elements. The electrically conductive interconnects have at least one of different sizes or shapes from one another. 1. An electronic package comprising:a substrate including conductive elements electrically connected to an integrated circuit of the substrate, a portion of at least one of the conductive element in between fingers of another conductive element;at least two conductive interconnects, each electrically coupled to the integrated circuit via the conductive elements, wherein the at least two conductive interconnects include different size and shape from one another, and wherein each of the at least two conductive interconnects include a first portion including tin and a second portion of copper, the second portion attached to the conductive elements; anda portion of a leadframe attached to the first portion of each of the at least two conductive interconnects.2. The electronic package recited in claim 1 , wherein one of the at least two conductive interconnects has a thickness extending away from the conductive elements greater than a width extending perpendicular to the thickness.3. The electronic package recited in claim 1 , wherein at least one of the conductive interconnects is polygonal in shape.4. The electronic package recited in claim 1 , wherein at least one of the conductive interconnects is rectangular in shape.5. The electronic package recited in claim 1 , wherein at least one of the conductive interconnects has an aspect ratio greater than 1:1.6. The electronic package recited in claim 1 , further comprising an insulating layer provided over the substrate and in between the at least two ...

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04-03-2021 дата публикации

CHIP PACKAGE STRUCTURE

Номер: US20210066230A1

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first bump and a first dummy bump between the chip and the substrate. The first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump. 1. A chip package structure , comprising:a substrate;a chip over the substrate; anda first bump and a first dummy bump between the chip and the substrate, wherein the first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump.2. The chip package structure as claimed in claim 1 , wherein the first dummy bump has a first strip portion and a second strip portion claim 1 , and the first strip portion is not parallel to the second strip portion.3. The chip package structure as claimed in claim 2 , wherein the chip has a first edge and a second edge claim 2 , the first edge and the second edge meet at the corner of the chip claim 2 , and the first strip portion is substantially parallel to the first edge.4. The chip package structure as claimed in claim 3 , wherein the second strip portion is substantially parallel to the second edge.5. The chip package structure as claimed in claim 1 , further comprising:an underfill layer between the chip and the substrate and between the first dummy bump and the substrate.6. The chip package structure as claimed in claim 1 , further comprising:a second bump between the first bump and the substrate; anda second dummy bump between the chip and the substrate, wherein the second dummy bump is connected to the ...

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12-03-2015 дата публикации

Copper pillar bump and flip chip package using same

Номер: US20150069603A1
Принадлежит: Individual

Electrically conductive pillars with a solder cap are formed on a substrate with an electroplating process. A flip-chip die having solder wettable pads is attached to the substrate with the conductive pillars contacting the solder wettable pads.

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17-03-2022 дата публикации

Electronic device package and method for manufacturing the same

Номер: US20220084972A1
Принадлежит: Advanced Semiconductor Engineering Inc

An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

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