Semiconductor Packaging Structure and Method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections. 1. A method for forming a semiconductor device , the method comprising:forming a first external conductive connector in physical contact with a first post-contact material over a first underbump metallization of a first package, the first underbump metallization being over a first contact, wherein the first external conductive connector comprises a single material throughout the first external conductive connector, wherein the single material, the first contact, the first underbump metallization and the first post-contact material each have a different composition from each other; andbonding a second package to a second underbump metallization over a second contact, wherein the first external conductive connector extends away from the first package a first distance, the second package extends away from the first package a second distance, the second distance being parallel to and less than the first distance, and wherein the second package comprises a second conductive connector in physical contact with the second underbump metallization.2. The method of claim 1 , further comprising forming through substrate vias in the first package prior to the forming the first external conductive connector.3. The method of claim 2 , wherein the forming the through substrate vias comprises:forming an opening in a substrate of the first package;filling the opening with a conductive material; andthinning the substrate to expose the conductive material.4. The method of claim 2 , wherein the forming the through substrate vias comprises:forming an opening in a ...

Package-on-package structure with epoxy flux residue

A structure includes a first package and a second package. The second package is coupled to the first package by one or more connectors. Epoxy flux residue is disposed around the connectors and in contact with the connectors. A method includes providing a first package having first connector pads and providing a second package having corresponding second connector pads. Solder paste is printed on each of the first connector pads. Epoxy flux is printed on each of the solder paste. The first and second connector pads are aligned and the packages are pressed together. The solder paste is reflowed to connect the first connector pads to the second connector pads while leaving an epoxy flux residue around each of the connections.

Alignment in the packaging of integrated circuits

A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package, wherein the top package is aligned to the bottom package after the placing the top package over the bottom package. A reflow is then performed to bond the top package to the bottom package.

Semiconductor packaging having warpage control and methods of forming same

An embodiment method for forming a semiconductor device package comprises bonding a first die to a package substrate and forming a molding compound over the package substrate and around the first die. A surface of the first die opposing the package substrate is exposed after forming the molding compound. The method further comprises bonding a plurality of second dies to the surface of the first die opposing the package substrate after forming the molding compound.

Package on package bonding structure and method for forming the same

A method of forming a package on package (PoP) structure includes forming a first die package, and bonding an external connector of a second die package to a solder paste layer of the first die package. The forming the first die package includes forming a contact pad over a substrate, attaching a metal ball with a convex surface to the contact pad, and applying a solder paste layer over a distal end of the metal ball and leaving at least a portion of the metal ball without solder paste. The forming the first die package also includes attaching a semiconductor die to the substrate, and forming a molding compound between the semiconductor die and the metal ball, where the solder paste layer has a first portion extending above an upper surface of the molding compound and a second portion extending below the upper surface of the molding compound.

Semiconductor Packaging Having Warpage Control and Methods of Forming Same

An embodiment method for forming a semiconductor device package comprises bonding a first die to a package substrate and forming a molding compound over the package substrate and around the first die. A surface of the first die opposing the package substrate is exposed after forming the molding compound. The method further comprises bonding a plurality of second dies to the surface of the first die opposing the package substrate after forming the molding compound.

Semiconductor packaging structure and method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Packaging methods for semiconductor devices

Packaging methods for semiconductor devices are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a workpiece including a plurality of packaging substrates. A portion of the workpiece is removed between the plurality of packaging substrates. A die is attached to each of the plurality of packaging substrates.

Process for forming package-on-package structures

A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material.

Semiconductor packaging structure and method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Package on Package Bonding Structure and Method for Forming the Same

A method of forming a package on package (PoP) structure includes forming a first die package, and bonding an external connector of a second die package to a solder paste layer of the first die package. The forming the first die package includes forming a contact pad over a substrate, attaching a metal ball with a convex surface to the contact pad, and applying a solder paste layer over a distal end of the metal ball and leaving at least a portion of the metal ball without solder paste. The forming the first die package also includes attaching a semiconductor die to the substrate, and forming a molding compound between the semiconductor die and the metal ball, where the solder paste layer has a first portion extending above an upper surface of the molding compound and a second portion extending below the upper surface of the molding compound. 1. A method of forming a package on package (PoP) structure comprising: attaching a metal ball with a convex surface to a first contact pad on a substrate;', 'applying a solder paste layer over a distal end of the metal ball and leaving at least a portion of the metal ball without solder paste, wherein the distal end is a furthest end of the metal ball from the substrate;', 'attaching a semiconductor die to the substrate; and', 'forming a molding compound between the semiconductor die and the metal ball, wherein the solder paste layer has a first portion extending above an upper surface of the molding compound and a second portion extending below the upper surface of the molding compound; and, 'forming a first die package, comprisingbonding an external connector of a second die package to the solder paste layer of the first die package.2. The method of claim 1 , wherein the solder paste layer has a first width at an interface between the solder paste layer and the molding compound claim 1 , and a second width for the second portion of the solder paste layer claim 1 , wherein the first width is smaller than the second width.3. ...

Process for Forming Package-on-Package Structures

A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material. 1. A method comprising:forming a first plurality of redistribution lines;forming metal posts over and electrically coupled to the first plurality of redistribution lines;attaching a back surface of a first device die to one of the first plurality of redistribution lines through a die-attach film, wherein the die-attach film contacts the one of the first plurality of redistribution lines;encapsulating the first device die and the metal posts in an encapsulation material; andforming a second plurality of redistribution lines electrically coupling to the first device die, wherein the first plurality of redistribution lines and the second plurality of redistribution lines are on opposite sides of the metal posts.2. The method of claim 1 , wherein top surfaces of the metal posts are coplanar with a top surface of the encapsulation material claim 1 , and bottom surfaces of the metal posts are in contact with top surfaces of the first plurality of redistribution lines.3. The method of claim 1 , wherein the metal posts are formed as protruding over top surfaces of the first plurality of redistribution lines.4. The method of further comprising claim 1 , after the encapsulating claim 1 , performing a lithography process on the encapsulation material to expose the metal posts and electrical connectors of the first device die.5. The method of further comprising ...

Semiconductor package

A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The distance between the conductive pillar and the conductive trace is less than or equal to about 16 mum.

Package-on-Package Structure Including a Thermal Isolation Material and Method of Forming the Same

A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component. 1. A method comprising:bonding a first die to a first substrate to form a first package component;disposing a thermal isolation material to form a seal ring on a top surface of the first die, wherein the seal ring has a plurality of sides, each adjacent to an edge of the first die; andbonding a second package component to the first package component, wherein a bottom surface of the second package component contacts the seal ring, and the first die, the second package component, and the seal ring encloses air or vacuum therein.2. The method of further comprising dispensing an encapsulating material to encircle the seal ring and the first die.3. The method of claim 2 , wherein the encapsulating material is in contact with outer edges of the seal ring claim 2 , and inner edges of the seal ring are exposed to the air or the vacuum.4. The method of further comprising forming the second package component comprising:bonding a second die to a second substrate; andencapsulating the second die in a molding compound.5. The method of claim 1 , wherein the seal ring encircles air therein.6. The method of claim 1 , wherein a space encircled by the seal ring is vacuumed.7. The method of claim 1 , wherein the thermal isolation material is dispensed to have outer edges of the seal ring aligned to corresponding edges of the first die.8. A method comprising:bonding a first die to a first ...

Semiconductor package

A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The distance between the conductive pillar and the conductive trace is less than or equal to about 16 μm.

Package on-package structures and methods for forming the same

A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound.

Package-on-package structure including a thermal isolation material and method of forming the same

A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component.

Packaging methods and structures for semiconductor devices

Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.

Semiconductor packaging structure and method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Packaging process tools and systems, and packaging methods for semiconductor devices

Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

Alignment in the Packaging of Integrated Circuits

A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package, wherein the top package is aligned to the bottom package after the placing the top package over the bottom package. A reflow is then performed to bond the top package to the bottom package.

Semiconductor Packaging Structure and Method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections. 1. A method for forming a semiconductor device , the method comprising:forming a first contact and a second contact on a first package;forming a first underbump metallization in physical contact with the first contact;forming a second underbump metallization in physical contact with the second contact;adjusting a height of the first contact relative to the second contact by forming a first post-contact material over the first contact, wherein the first contact, the first underbump metallization and the first post-contact material each have a different composition from each other;forming a first external conductive connector in physical contact with the first post-contact material, wherein the first external conductive connector comprises a single material throughout the first external conductive connector, the single material having a different composition than the first post-contact material; andbonding a second package to the second contact, wherein the first external conductive connector extends away from the first package a first distance, the second package extends away from the first package a second distance, the second distance being parallel to and less than the first distance, and wherein the second package comprises a second conductive connector in physical contact with the second underbump metallization.2. The method of claim 1 , wherein the bonding the second package onto the second contact bonds the second package to the second contact but not to the first contact.3. The method of claim 2 , further comprising encapsulating the second ...

Package-on-package structures and methods for forming the same

A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound.

Package-on-Package Structures and Methods for Forming the Same

A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound. 1. A method comprising:encapsulating a device die over a package substrate in an encapsulating material to form a first package, wherein a first electrical connector of the first package is exposed through a top surface of the encapsulating material; andremoving a top portion of the first electrical connector using an electrical arc, wherein a bottom portion of the first electrical connector remains after the top portion of the first electrical connector is removed.2. The method of further comprising bonding a top package component to the package substrate claim 1 , wherein the top package component is bonded to the package substrate through the first electrical connector.3. The method of claim 1 , wherein the removing the top portion of the first electrical connector is performed until a portion of a top surface of the first electrical connector is lower than the top surface of the encapsulating material.4. The method of claim 1 , wherein the first electrical connector comprises a solder region claim 1 , and the method further comprises:placing a solder ball over a metal pad of the package substrate; andbefore the encapsulating the device die, reflowing the solder ball to form the first electrical connector.5. The method of claim 1 , wherein after the removing the top portion of the first electrical connector claim 1 , an entirety of a top surface of a remaining portion of the first electrical connector is lower than the top surface of the encapsulating ...

Methods and apparatus for thin die processing

A vacuum tip and methods for processing thin integrated circuit dies are disclosed. The vacuum tip for attaching to an integrated circuit die is disclosed comprising a vacuum port configured to connect to a vacuum supply on an upper surface and having a bottom surface; and at least one vacuum hole extending through the vacuum tip and exposed at the bottom surface of the vacuum tip; wherein the vacuum tip is configured to physically contact a surface of an integrated circuit die. Methods for processing integrated circuit dies are disclosed. The invention further provides a method and a device for processing thin dies.

Thermal Compress Bonding

A method includes providing a substrate carrier including work piece holders, and placing a first plurality of work pieces into the work piece holders. A second plurality of work pieces is picked up and placed, with each of the second plurality of work pieces being placed on one of the first plurality of work pieces. Solder bumps between the first and the second plurality of work pieces are then reflowed to simultaneously bond the first and the second plurality of work pieces together. 1. A method comprising:providing a substrate carrier comprising work piece holders;placing a first plurality of work pieces into the work piece holders;picking up and placing a second plurality of work pieces, with each of the second plurality of work pieces being placed on one of the first plurality of work pieces;heating the first plurality of work pieces with a first heating tool;heating the second plurality of work pieces with a second heating tool different than the first heating tool; andreflowing solder bumps between the first and the second plurality of work pieces to simultaneously bond the first and the second plurality of work pieces together.2. The method of claim 1 , wherein the step of reflowing the solder bumps is performed by contacting the second heating tool with the second plurality of work pieces claim 1 , and by the heating the second plurality of work pieces claim 1 , the heating being simultaneous to the second plurality or work pieces.3. The method of claim 2 , wherein the second heating tool comprises a plurality of heating heads claim 2 , and wherein the plurality of heating heads are configured to heat the second plurality of work pieces simultaneously.4. The method of claim 2 , wherein the second heating tool comprises a single heating head contacting all of the second plurality of work pieces claim 2 , and wherein the single heating head is configured to heat the second plurality of work pieces simultaneously.5. The method of further comprising:before the ...

Forming Low Stress Joints Using Thermal Compress Bonding

A method of forming a bump structure includes providing a first work piece including a dielectric layer having a top surface; placing a second work piece facing the first work piece; placing a heating tool contacting the second work piece; and heating the second work piece using the heating tool to perform a reflow process. A first solder bump between the first and the second work pieces is melted to form a second solder bump. Before the second solder bump solidifies, pulling the second work piece away from the first work piece, until an angle formed between a tangent line of the second solder bump and the top surface of the dielectric layer is greater than about 50 degrees, wherein the tangent line is drawn at a point where the second solder bump joins the dielectric layer. 1. A method comprising:providing a first work piece comprising a dielectric layer having a top surface;placing a second work piece facing the first work piece;placing a heating tool contacting the second work piece;heating the second work piece using the heating tool to perform a reflow process, wherein a first solder bump between the first and the second work pieces is melted to form a second solder bump; andbefore the second solder bump solidifies, pulling the second work piece away from the first work piece, until an angle formed between a tangent line of the second solder bump and the top surface of the dielectric layer is greater than about 50 degrees, wherein the tangent line is drawn at a point where the second solder bump joins the dielectric layer.2. The method of claim 1 , wherein the angle is greater than about 60 degrees.3. The method of claim 2 , wherein the angle is greater than about 75 degrees.4. The method of claim 1 , wherein the first work piece is a package substrate.5. The method of claim 1 , wherein the first work piece is a device die.6. The method of claim 1 , wherein before the step of placing the second work piece facing the first work piece claim 1 , the first solder ...

Package Assembly Cleaning Process Using Vaporized Solvent

A method includes generating a solvent-containing vapor that contains a solvent. The solvent-containing vapor is conducted to a package assembly to clean the package assembly. The solvent-containing vapor condenses to form a liquid on a surface of the package assembly, and flows off from the surface of the package assembly. 1. A method comprising:generating a solvent-containing vapor, wherein the solvent-containing vapor comprises a solvent; andconducting the solvent-containing vapor to a package assembly to clean the package assembly, wherein the solvent-containing vapor condenses to form a liquid on a surface of the package assembly.2. The method of claim 1 , wherein the step of conducting the solvent-containing vapor to the package assembly comprises:placing the package assembly in a sealed chamber; andconducting the solvent-containing vapor into the sealed chamber.3. The method of claim 2 , wherein during the step of conducting the solvent-containing vapor into the sealed chamber claim 2 , a pressure of the solvent-containing vapor in the chamber is greater than 1 atmosphere.4. The method of further comprising claim 2 , after the step of conducting the solvent-containing vapor into the chamber claim 2 , conducting a clean water vapor into the chamber.5. The method of further comprising claim 4 , after the step of conducting the clean water vapor into the chamber claim 4 , conducting clean air into the chamber.6. The method of claim 1 , wherein the solvent is capable of dissolving solder flux claim 1 , and wherein the package assembly comprises solder flux residue.7. The method of further comprising:replenishing a solvent-containing solution in a vapor generation chamber, wherein the solvent-containing solution comprises the solvent and water; andblowing the solvent-containing solution and air to a vibrator to generate solvent-containing droplets and the solvent-containing vapor, wherein the solvent-containing vapor is conducted through a pipe to the package ...

Packaging Methods and Structures for Semiconductor Devices

Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL. 1. A packaged semiconductor device , comprising;a redistribution layer (RDL), the RDL comprising a first surface and a second surface opposite the first surface;at least one integrated circuit coupled to the first surface of the RDL;a plurality of metal bumps coupled to the second surface of the RDL; anda molding compound disposed over the at least one integrated circuit and the first surface of the RDL.2. The packaged semiconductor device according to claim 1 , wherein the at least one integrated circuit comprises a substrate with a plurality of through-substrate vias (TSVs) formed therein claim 1 , wherein the at least one integrated circuit comprises at least one first integrated circuit claim 1 , further comprising at least one second integrated circuit disposed over at least a portion of the at least one first integrated circuit claim 1 , portions of the at least one second integrated circuit being electrically coupled to portions of the at least one first integrated circuit claim 1 , to the RDL claim 1 , or to both the at least one first integrated circuit and the RDL.3. The packaged semiconductor device according to claim 1 , wherein the at least one integrated circuit comprises at least one first integrated circuit claim 1 , further comprising at least one second integrated circuit disposed over at least the RDL claim 1 , the at least one second integrated circuit being electrically coupled to the RDL by a plurality of connections disposed in the molding compound between the ...

Packaging Process Tools and Packaging Methods for Semiconductor Devices

Packaging process tools and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure including a frame. The frame includes a plurality of apertures adapted to retain a plurality of integrated circuit dies therein. The frame includes at least one hollow region. 1. A packaging process tool for semiconductor devices , comprising:a mechanical structure comprising a frame including a plurality of apertures adapted to retain a plurality of integrated circuit dies therein, wherein the frame comprises at least one hollow region.2. The packaging process tool according to claim 1 , wherein the mechanical structure comprises a jig.3. The packaging process tool according to claim 2 , wherein the frame of the mechanical structure includes a first side claim 2 , a second side opposite the first side claim 2 , and a plurality of connecting members coupled between the first side and the second side at edges of the first side and the second side.4. The packaging process tool according to claim 3 , wherein the first side claim 3 , the second side claim 3 , and the plurality of connecting members of the frame comprise a thickness of about 0.1 mm to about 10 mm.5. The packaging process tool according to claim 3 , wherein the first side claim 3 , the second side claim 3 , and the plurality of connecting members of the frame comprise stainless steel claim 3 , aluminum claim 3 , ceramic claim 3 , rubber claim 3 , epoxy claim 3 , a plastic polymer claim 3 , or combinations thereof.6. The packaging process tool according to claim 3 , wherein the frame further comprises at least one support member coupled between the first side and the second side or between opposing connecting members.7. The packaging process tool according to claim 6 , wherein the at least one support member of the frame is disposed substantially perpendicular to the first side and the second side or to the opposing ...

Process for Forming Package-on-Package Structures

A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material. 1. A device comprising:an inter-layer dielectric;a first device die under the inter-layer dielectric;a die-attach film under the inter-layer dielectric and over the first device die, wherein the die-attach film is attached to the device die;a first plurality of redistribution lines comprising first portions level with the die-attach film;a first plurality of Z-interconnects electronically coupled to the device die and the first plurality of redistribution lines; anda first polymer-comprising material under the inter-layer dielectric, wherein the first device die, the die-attach film, and the first plurality of Z-interconnects are disposed in the first polymer-comprising material.2. The device of claim 1 , wherein a top surface of the die-attach film contacts a bottom surface of the inter-layer dielectric.3. The device of claim 1 , wherein the first plurality of redistribution lines further comprises second portions extending into the inter-layer dielectric claim 1 , wherein top surfaces of the first plurality of redistribution lines and a top surface of the inter-layer dielectric form a planar surface.4. The device of further comprising:a second plurality of redistribution lines electrically coupled to the first plurality of Z-interconnects, wherein the first and the second plurality of redistribution lines are on opposite sides of the first plurality ...

Methods for Forming 3DIC Package

A method includes dispensing an underfill between a first package component and a second package component, wherein the first package component is placed on a lower jig, and the second package component is over and bonded to the first package component. A through-opening is in the lower jig and under the first package component. The underfill is cured, wherein during the step of curing the underfill, a force is applied to flatten the first package component. The force is applied by performing an action selected from the group consisting of vacuuming and air blowing through the through-opening. 1. A method comprising:dispensing an underfill between a first package component and a second package component, wherein the first package component is placed on a lower jig, and the second package component is over and bonded to the first package component, and wherein a through-opening is in the lower jig and under the first package component; andcuring the underfill, wherein during the step of curing the underfill, a force is applied to flatten the first package component, and wherein the force is applied by performing an action selected from the group consisting of vacuuming and air blowing through the through-opening.2. The method of claim 1 , wherein before the step of curing claim 1 , the first package component comprises a center portion and edge portions claim 1 , wherein the center portion is higher than the edge portions claim 1 , and wherein the action comprises vacuuming.3. The method of claim 1 , wherein before the step of curing claim 1 , the first package component comprises a center portion and edge portions claim 1 , wherein the center portion is lower than the edge portions claim 1 , and wherein the action comprises air blowing.4. The method of further comprising claim 3 , during the step of curing claim 3 , applying a blocker over and in contact with a top surface of the second package component to prevent the first and the second package components from ...

Packaging Methods for Semiconductor Devices

Packaging methods for semiconductor devices are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a workpiece including a plurality of packaging substrates. A portion of the workpiece is removed between the plurality of packaging substrates. A die is attached to each of the plurality of packaging substrates. 1. A method of packaging a semiconductor device , the method comprising:providing a workpiece, the workpiece including a plurality of packaging substrates;removing a portion of the workpiece between the plurality of packaging substrates; andattaching a die to each of the plurality of packaging substrates.2. The method according to claim 1 , wherein attaching the die comprises providing a die including a plurality of bumps disposed on the surface thereof claim 1 , and attaching the plurality of bumps on the surface of the die to each of the plurality of packaging substrates.3. The method according to claim 2 , wherein providing the die comprises providing a die wherein the plurality of bumps disposed thereon comprises solder.4. The method according to claim 3 , further comprising performing a solder process claim 3 , a solder reflow process claim 3 , or a thermal compression bonding process.5. The method according to claim 3 , wherein removing the portion of the workpiece comprises removing about 20 μm or greater of the workpiece.6. The method according to claim 1 , wherein removing the portion of the workpiece comprises removing a top portion of the workpiece proximate the dies claim 1 , removing a bottom portion of the workpiece on an opposite side from the dies claim 1 , or both removing a top portion of the workpiece proximate the dies and removing a bottom portion of the workpiece on an opposite side from the dies.7. The method according to claim 1 , further comprising forming an under-fill material over the dies claim 1 , and forming a molding compound over the dies and the under-fill material.8. A method of ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The distance between the conductive pillar and the conductive trace is less than or equal to about 16 μm. 1. A semiconductor package , comprising:a workpiece comprising a conductive trace; anda chip comprising a conductive pillar,wherein the chip is attached to the workpiece through a solder joint region formed between the conductive pillar and the conductive trace;wherein a distance between the conductive pillar and the conductive trace is less than or equal to 16 μm, andthe conductive trace extends outside the solder joint region along an axis parallel to a top surface of the workpiece.2. The semiconductor package of claim 1 , wherein the distance between the conductive pillar and the conductive trace is less than or equal to 12 μm.3. (canceled)4. The semiconductor package of claim 1 , wherein the conductive pillar comprises copper.5. The semiconductor package of claim 1 , wherein the workpiece comprises a dielectric substrate.6. The semiconductor package of claim 1 , wherein the conductive trace comprises copper.7. The semiconductor package of claim 1 , wherein the distance between the conductive pillar and the conductive trace is at a range between 5 μm and 16 μm.8. A semiconductor package claim 1 , comprising:a substrate comprising a conductive trace; anda chip comprising a bump structure, wherein the bump structure comprises a conductive pillar and a solder layer formed on the conductive pillar;wherein the chip is electrically coupled to the substrate, and the bump structure is electrically connected to the conductive trace to form a bump-on-trace (BOT) interconnect structure;wherein the conductive trace extends beyond the conductive pillar on at least two sides of the conductive pillar, andwherein in the BOT interconnect ...

SEMICONDUCTOR PACKAGE HAVING SOLDER JOINTED REGION WITH CONTROLLED AG CONTENT

A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The silver (Ag) content in the solder layer is between 0.5 and 1.8 weight percent. 1. A semiconductor package , comprising:a workpiece comprising a conductive trace; anda chip comprising a bump structure,wherein the chip is attached to the workpiece and the bump structure is electrically connected to the conductive trace to form a bump-on-trace (BOT) interconnect structure; andwherein the BOT interconnect structure comprises a solder region, and a silver (Ag) content in the solder region is not greater than 1.8 weight percent.2. The semiconductor package of claim 1 , wherein the Ag content in the solder region is between 0.5 and 1.8 weight percent.3. The semiconductor package of claim 1 , wherein the Ag content in the solder region is between 0.5 and 1.0 weight percent.4. The semiconductor package of claim 1 , wherein the Ag content in the solder region is between 1.1 and 1.5 weight percent.5. The semiconductor package of claim 1 , wherein bump structure is an elongated shape.6. The semiconductor package of claim 1 , wherein the bump structure comprises a conductive pillar.7. The semiconductor package of claim 6 , wherein the conductive pillar comprises copper.8. The semiconductor package of claim 1 , wherein the workpiece comprises a dielectric substrate and the conductive trace comprises copper.9. The semiconductor package of claim 1 , wherein the solder region is free of lead (Pb).10. A semiconductor package claim 1 , comprising:a workpiece comprising a conductive trace; anda chip comprising a conductive pillar and a solder layer on the conductive pillar,wherein the chip is attached to the workpiece and the conductive pillar is electrically connected to the conductive trace through the solder layer,wherein a silver (Ag) content in ...

Process for Forming Packages

A method includes loading a first package component on a concave boat, and placing a second package component over the first package component. A load clamp is placed over the second package component, wherein the load clamp is supported by a temperature-variable spacer of the concave boat. A reflow step is performed to bond the second package component to the first package component. During a temperature-elevation step of the reflow step, the temperature-variable spacer is softened in response to an increase in temperature, and a height of the softened temperature-variable spacer is reduced, until the load clamp is stopped by a rigid spacer of the concave boat. 1. A method comprising:loading a first package component on a concave boat;placing a second package component over the first package component;placing a load clamp over the second package component, wherein the load clamp is supported by a temperature-variable spacer of the concave boat; andperforming a reflow step to bond the second package component to the first package component, wherein during a temperature-elevation step of the reflow step, the temperature-variable spacer is softened in response to an increase in temperature, and wherein a height of the softened temperature-variable spacer is reduced, until the load clamp is stopped by a rigid spacer of the concave boat.2. The method of claim 1 , wherein the reflow step further comprises a temperature-lowering step claim 1 , and wherein during the temperature-lowering step claim 1 , the temperature-variable spacer is hardened claim 1 , and raises the load clamp up from the rigid spacer.3. The method of further comprising removing the load clamp from over the concave boat after a temperature of the concave boat is lowered claim 1 , and a top surface of the temperature-variable spacer is higher than a top surface of the rigid spacer.4. The method of claim 1 , wherein during the reflow step claim 1 , no additional force is applied on the load clamp to push ...

Contact and Method of Formation

A system and method for forming contacts is provided. An embodiment comprises forming the contacts on a substrate and then coining the contacts by physically shaping them using, e.g., a molding chamber. The physical shaping of the contacts may be performed using a patterned portion of the molding chamber or else by placing a patterned stencil around the contacts prior before a force is applied to physically reshape the contacts. The contacts may be reshaped into a cylindrical, oval, cuboid, or rectangular shape, for example. 1. A method for manufacturing semiconductor devices , the method comprising:providing a contact on a substrate, the contact comprising a first material with a first melting point; andapplying a force to physically reshape the contact at a temperature below the melting point.2. The method of claim 1 , wherein the applying the force further comprises pressing the contact with patterned plate.3. The method of claim 1 , wherein the applying the force further comprises:placing a stencil around the contact; andpressing the contact with a flat plate.4. The method of claim 1 , further comprising encapsulating the substrate after the applying the force.5. The method of claim 4 , wherein the applying the force is performed in a first molding chamber and the encapsulating the substrate is performed in the first molding chamber.6. The method of claim 5 , further comprising replacing a molding portion in the first molding chamber after the applying the force and prior to the encapsulating the substrate.7. The method of claim 4 , wherein the applying the force is performed in a first molding chamber and the encapsulating the substrate is performed in a second molding chamber different from the first molding chamber.8. The method of claim 1 , wherein the applying the force shapes the contact into a cylindrical shape.9. The method of claim 1 , wherein the applying the force shapes the contact into a cuboid shape.10. A method of manufacturing a semiconductor ...

Thermal Compress Bonding

A method includes providing a substrate carrier including work piece holders, and placing a first plurality of work pieces into the work piece holders. A second plurality of work pieces is picked up and placed, with each of the second plurality of work pieces being placed on one of the first plurality of work pieces. Solder bumps between the first and the second plurality of work pieces are then reflowed to simultaneously bond the first and the second plurality of work pieces together.

Forming Low Stress Joints Using Thermal Compress Bonding

A method of forming a bump structure includes providing a first work piece including a dielectric layer having a top surface; placing a second work piece facing the first work piece; placing a heating tool contacting the second work piece; and heating the second work piece using the heating tool to perform a reflow process. A first solder bump between the first and the second work pieces is melted to form a second solder bump. Before the second solder bump solidifies, pulling the second work piece away from the first work piece, until an angle formed between a tangent line of the second solder bump and the top surface of the dielectric layer is greater than about 50 degrees, wherein the tangent line is drawn at a point where the second solder bump joins the dielectric layer.

Packaging Process Tools and Systems, and Packaging Methods for Semiconductor Devices

Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

Semiconductor Packaging Structure and Method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Fine-Pitch Package-on-Package Structures and Methods for Forming the Same

A method includes laminating a Non-Conductive Film (NCF) over a first package component, and bonding a second package component on the first package component. The NCF and the second package component are on a same side of the first package component. Pillars of a mold tool are then forced into the NCF to form openings in the NCF. The connectors of the first package component are exposed through the openings. 1. A method comprising:laminating a Non-Conductive Film (NCF) over a first package component;bonding a second package component on the first package component, wherein the NCF and the second package component are on a same side of the first package component; andforcing pillars of a mold tool into the NCF to form openings in the NCF, wherein connectors of the first package component are exposed through the openings.2. The method of further comprising:placing solder balls into the openings; andreflowing the solder balls to form solder regions on the connectors.3. The method of further comprising bonding a top package to the first package component claim 1 , wherein the top package is bonded to the first package component through solder regions in the openings.4. The method of claim 1 , wherein the step of laminating the NCF over the first package component is performed before the step of bonding the second package component on the first package component.5. The method of claim 1 , wherein the step of laminating the NCF over the first package component is performed after the step of bonding the second package component on the first package component.6. The method of claim 5 , wherein the NCF is laminated over the first package component and the second package component claim 5 , and wherein the method further comprises:laminating an additional NCF film on a wafer; andsawing the wafer and the additional NCF film into a plurality of pieces, wherein one of the plurality of pieces comprises a piece of the additional NCF and the second package component, wherein after ...

Contact and Method of Formation

A system and method for forming contacts is provided. An embodiment comprises forming the contacts on a substrate and then coining the contacts by physically shaping them using, e.g., a molding chamber. The physical shaping of the contacts may be performed using a patterned portion of the molding chamber or else by placing a patterned stencil around the contacts prior before a force is applied to physically reshape the contacts. The contacts may be reshaped into a cylindrical, oval, cuboid, or rectangular shape, for example.

BUMP-ON-TRACE PACKAGING STRUCTURE AND METHOD FOR FORMING THE SAME

A device comprises a first package component, and a first metal trace and a second metal trace on a top surface of the first package component. The device further includes a dielectric mask layer covering the top surface of the first package component, the first metal trace and the second metal trace, wherein the dielectric mask layer has an opening therein exposing the first metal trace. The device also includes a second package component and an interconnect formed on the second package component, the interconnect having a metal bump and a solder bump formed on the metal bump, wherein the solder bump contacts the first metal trace in the opening of the dielectric mask layer. 1. A device comprising:a first package component;a first metal trace and a second metal trace on a top surface of the first package component;a dielectric mask layer covering a top surface of the first package component, the first metal trace and the second metal trace, wherein the dielectric mask layer has an opening therein exposing the first metal trace but not the second metal trace;a second package component; andan interconnect formed on the second package component, the interconnect having a metal bump and a solder bump formed on the metal bump, wherein the solder bump contacts the first metal trace in the opening of the dielectric mask layer.2. The device of claim 1 , wherein the first package component comprises a package substrate and the second package component comprises a device die.3. The device of claim 1 , wherein the first and the second metal trace comprise a material selected from the group consisting of copper claim 1 , copper alloy claim 1 , aluminum claim 1 , aluminum alloy claim 1 , tungsten claim 1 , tungsten alloy claim 1 , nickel claim 1 , nickel alloy claim 1 , palladium claim 1 , palladium alloy claim 1 , gold claim 1 , and alloys thereof.4. The device of claim 1 , wherein the second metal trace is adjacent to the first metal trace.5. The device of claim 4 , wherein ...

WARPAGE CONTROL IN A PACKAGE-ON-PACKAGE STRUCTURE

The present disclosure relates to a tool arrangement and method to reduce warpage within a package-on-package semiconductor structure, while minimizing void formation within an electrically-insulating adhesive which couples the packages. A pressure generator and a variable frequency microwave source are coupled to a process chamber which encapsulates a package-on-package semiconductor structure. The package-on-package semiconductor structure is simultaneously heated by the variable frequency microwave source at variable frequency, variable temperature, and variable duration and exposed to an elevated pressure by the pressure generator. This combination for microwave heating and elevated pressure limits the amount of warpage introduced while preventing void formation within an electrically-insulating adhesive which couples the substrates of the package-on-package semiconductor structure. 1. A tool arrangement for package-on-package thermal processing to limit warpage and void formation , comprising:a process chamber configured to surround a package-on-package structure and to isolate the package-on-package structure from an ambient environment surrounding the tool arrangement;a variable frequency microwave source configured to irradiate the package-on-package structure with microwave radiation at variable frequency, variable temperature, and variable duration;a pressure generator configured to generate an inert gas and deliver the inert gas to the process chamber simultaneous to irradiating the package-on-package structure with microwave radiation; anda controller configured to independently control operation of the pressure generator and the variable frequency microwave source.2. The tool arrangement of claim 1 , wherein the pressure generator is configured to generate the inert gas at a pressure greater than approximately 1 atmosphere to reduce voids in an electrically-insulating adhesive within the package-on-package structure.3. The tool arrangement of claim 1 , ...

Methods for Forming 3DIC Package

A method includes dispensing an underfill between a first package component and a second package component, wherein the first package component is placed on a lower jig, and the second package component is over and bonded to the first package component. A through-opening is in the lower jig and under the first package component. The underfill is cured, wherein during the step of curing the underfill, a force is applied to flatten the first package component. The force is applied by performing an action selected from the group consisting of vacuuming and air blowing through the through-opening.

Package-on-Package Process for Applying Molding Compound

A method of packaging includes placing a package component over a release film, wherein solder regions on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder regions remain in physical contact with the release film.

Bonding Through Multi-Shot Laser Reflow

A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot. 1. A package comprising:a first package component comprising a first metallic feature and a second metallic feature at a surface of the first package component;a second package component comprising a third metallic feature and a fourth metallic feature at a surface of the second package component;a first solder region joining the first metallic feature to the third metallic feature;a first Inter-Metallic Compound (IMC) between and adjoining the first metallic feature and the first solder region, wherein the first IMC has a first thickness;a second solder region joining the second metallic feature to the fourth metallic feature; anda second IMC between and adjoining the second metallic feature and the second solder region, wherein the second IMC has a second thickness greater than the first thickness.2. The package of claim 1 , wherein a ratio of the second thickness to the first thickness is greater than about 1.2.3. The package of claim 2 , wherein the ratio is in a range between about 1.2 and about 2.4. The package of claim 1 , wherein the first thickness is in a first range between about 4 μm and about 6 μm claim 1 , and the second thickness is in a second range between about 7.2 μm and about 8 μm.5. The package of further comprising:a first column of metallic features comprised in the first package component, with the first metallic feature being in the first column of metallic features;a first column ...

Package-on-Package Structure Including a Thermal Isolation Material and Method of Forming the Same

A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component.

Semiconductor Bonding Structures and Methods

A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill. 1. A method of manufacturing a semiconductor device , the method comprising:applying an underfill material to a substrate;patterning the underfill material to form a first opening through the underfill material and a second opening through the underfill material, wherein the first opening has a first width, the second opening has a second width, and the first width is different from the second width; andafter the patterning the underfill material, bonding a first semiconductor die to the substrate through the first opening and bonding a first package to the substrate through the second opening.2. The method of claim 1 , wherein the first width is between about 10 μm and about 100 μm.3. The method of claim 2 , wherein the second width is between about 50 μm and about 400 μm.4. The method of claim 1 , further comprising partially curing the underfill material prior to the patterning the underfill material.5. The method of claim 4 , further comprising curing the underfill material after the bonding the first semiconductor die.6. The method of claim 1 , further comprising forming external connectors to the substrate claim 1 , wherein the external connectors are located on an opposite side of the substrate from the first semiconductor die.7. A method of manufacturing a semiconductor device claim 1 , the method comprising:removing a first portion of an underfill material to expose a first portion of a substrate;removing a second portion of the underfill material to expose a second portion of the substrate;after the removing the first portion of the underfill ...

Packaging Methods and Structures for Semiconductor Devices

Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL. 1. A method comprising:forming a redistribution layer (RDL) comprising at least one inter-level dielectric (ILD) and at least one first metallization layer formed in the at least one ILD;coupling a first integrated circuit to a first surface of the RDL, the first integrated circuit in electrical contact with first traces of the at least one first metallization layer;forming a first molding compound over the first integrated circuit and the first surface of the RDL, a first surface of the first molding compound disposed above a top surface of the first integrated circuit;forming a second metallization layer having second traces on the first surface of the first molding compound, the second traces in electrical contact with the first traces;coupling a second integrated circuit to the second traces; andforming a second molding compound over the second integrated circuit and in direct contact with a portion of the first surface of the first molding compound.2. The method of claim 1 , further comprising forming vertical connections over the RDL prior to the forming the first molding compound;wherein the forming the first molding compound comprises forming the first molding compound around the vertical connections; andwherein the forming the second metallization layer comprises forming the second traces in electrical contact with the first traces through the vertical connections.3. The method according to claim 1 , wherein the first integrated circuit comprises through vias;wherein the ...

PACKAGE-ON-PACKAGE STRUCTURE INCLUDING A THERMAL ISOLATION MATERIAL AND METHOD OF FORMING THE SAME

A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component. 1. A semiconductor device , comprising:a first package component having a first die formed on a first substrate;a second package component having a second die formed on a second substrate;a first set of conductive elements coupling the first package component to the second package component; anda thermal isolation material interjacent the first package component and the second package component.2. The semiconductor device of claim 1 , further comprising:a second set of conductive elements coupling the first die to the first substrate; anda third set of conductive elements coupling the second die to the second substrate.3. The semiconductor device of claim 2 , wherein the third set of conductive elements comprises bonding wires.4. The semiconductor device of claim 2 , further comprising a molding compound molded on the first substrate and surrounding the first die claim 2 , the first set of conductive elements and the second set of conductive elements claim 2 , and the molding compound further molded on the second substrate and surrounding the second die and the third set of conductive elements.5. The semiconductor device of claim 1 , wherein the first die is a logic chip.6. The semiconductor device of claim 1 , wherein the second die is a memory chip.7. The semiconductor device of claim 1 , wherein the thermal isolation material is a seal ring having air or vacuum therein.8. ...

Semiconductor Packaging Structure and Method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections. 1. A semiconductor device comprising:a first external conductive connector in physical contact with a first post-contact material over a first underbump metallization over a first contact of a first package; anda second package over the first package, wherein the first external conductive connector extends away from the first package a first distance, the second package extends away from the first package a second distance, the second distance being parallel to and less than the first distance, and wherein the second package comprises a second conductive connector in physical contact with a second underbump metallization.2. The semiconductor device of claim 1 , wherein the first external conductive connector comprises a solder material.3. The semiconductor device of claim 1 , wherein the first post-contact material has a thickness of between about 10 μm and about 200 μm.4. The semiconductor device of claim 1 , wherein the second package comprises a semiconductor die.5. The semiconductor device of claim 1 , wherein the second conductive connector comprises solder.6. The semiconductor device of claim 5 , wherein the second package comprises a copper pillar is physical contact with the second conductive connector.7. A semiconductor device comprising:a post contact material located on a first set of a first plurality of package contacts on a first side of a first package;a second package with external connections bonded directly to a second set of the first plurality of package contacts, the second package comprising a first surface facing away from ...

SEMICONDUCTOR PACKAGING HAVING WARPAGE CONTROL AND METHODS OF FORMING SAME

An embodiment method for forming a semiconductor device package comprises bonding a first die to a package substrate and forming a molding compound over the package substrate and around the first die. A surface of the first die opposing the package substrate is exposed after forming the molding compound. The method further comprises bonding a plurality of second dies to the surface of the first die opposing the package substrate after forming the molding compound. 1. A method for forming a semiconductor device package comprising:bonding a first die to a package substrate;forming a molding compound over the package substrate and around the first die, wherein a surface of the first die opposing the package substrate is exposed after forming the molding compound; andbonding a plurality of second dies to the surface of the first die opposing the package substrate using a plurality of connectors after forming the molding compound, the plurality of connectors electrically coupling the first die to the plurality of second dies.2. The method of claim 1 , wherein at least about 90 percent of a top surface of the package substrate is covered after forming the molding compound.3. The method of claim 1 , wherein a portion of a top surface of the package substrate remains exposed after forming the molding compound.4. The method of claim 3 , further comprising attaching a retaining ring to the portion of the top surface of the package substrate.5. The method of claim 3 , wherein the portion of the top surface of the package substrate encircles the first die and the molding compound.6. The method of claim 1 , wherein the molding compound is a molded underfill comprising an epoxy claim 1 , a resin claim 1 , a hardener claim 1 , a filler claim 1 , an adhesion promoter claim 1 , or a combination thereof.7. The method of claim 1 , wherein forming the molding compound comprises a transfer molding process claim 1 , and wherein the transfer molding process comprises covering the surface ...

Semiconductor Bonding Structures and Methods

A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.

PACKAGE ON PACKAGE BONDING STRUCTURE AND METHOD FOR FORMING THE SAME

The described embodiments of mechanisms of forming a die package and package on package (PoP) structure involve forming a solder paste layer over metal balls of external connectors of a die package. The solder paste layer protects the metal balls from oxidation. In addition, the solder paste layer enables solder to solder bonding with another die package. Further, the solder paste layer moves an intermetallic compound (IMC) layer formed between the solder paste layer and the metal balls below a surface of a molding compound of the die package. Having the IMC layer below the surface strengthens the bonding structure between the two die packages. 1. A die package , comprising:a semiconductor die, wherein at least a portion of the semiconductor die is surrounded by a molding compound;a substrate with interconnect structures, wherein the semiconductor die is bonded to the substrate and is electrically connected to the interconnect structures;wherein molding compound covers a first portion of a surface of the substrate, wherein the semiconductor die is bonded to a second portion of the surface; and a contact pad,', 'a metal ball, wherein the metal ball is bonded to the contact pad, and', 'a solder paste layer formed over a portion of metal ball, wherein a portion of the solder paste layer is exposed., 'an external connector surrounding the semiconductor die, wherein the external connector is electrically connected to the interconnect structures and to the semiconductor die, wherein the external connector is embedded in the molding compound, wherein the external connector comprises2. The die package of claim 1 , wherein the solder paste layer has a thickness in a range from about 10 μm to about 50 μm.3. The die package of claim 1 , wherein a top surface of the metal ball is below the surface of the molding compound at a distance in a range from about 50 μm to about 200 μm.4. The die package of claim 1 , wherein a distance from a top surface of the solder paste layer to ...

Packaging Methods for Semiconductor Devices

Packaging methods for semiconductor devices are disclosed. A method of packaging a semiconductor device includes providing a workpiece including a plurality of packaging substrates. A portion of the workpiece is removed between the plurality of packaging substrates. A die is attached to each of the plurality of packaging substrates. 1. A method comprising:forming a first packaging substrate and a second packaging substrate in a workpiece, wherein a separation region is interposed between the first packaging substrate and the second packaging substrate;removing a top portion of the separation region to form a top trench in the workpiece;removing a bottom portion of the separation region to form a bottom trench in the workpiece, wherein the top trench and the bottom trench are vertically aligned, and wherein at least a portion of the separation region is interposed between a bottom of the top trench and a bottom of the bottom trench; andbonding a die to each of the first packaging substrate and the second packaging substrate.2. The method of claim 1 , wherein the top trench extends into the workpiece to a first depth claim 1 , and wherein the first depth is less than about 100 μm.3. The method of claim 2 , wherein the top trench has a width greater than about 20 μm.4. The method of claim 1 , wherein removing the top portion of the separation region comprises performing an etch process on the separation region.5. The method of claim 1 , wherein the top portion of the separation region is removed by a laser or a die saw.6. The method of claim 1 , further comprising forming a molding compound over the workpiece claim 1 , wherein the molding compound fills the top trench.7. The method of claim 1 , further comprising performing a singulation process on the workpiece at the separation region.8. A method comprising:forming a first packaging substrate and a second packaging substrate in a workpiece, wherein a separation region is interposed between the first packaging ...

Tools and Systems for Processing Semiconductor Devices, and Methods of Processing Semiconductor Devices

Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a method of using a tool for processing semiconductor devices includes a tool with a second material disposed over a first material, and a plurality of apertures disposed within the first material and the second material. The second material comprises a higher reflectivity than the first material. Each of the apertures is adapted to retain a package component over a support during an exposure to energy.

Tools and Systems for Processing Semiconductor Devices, and Methods of Processing Semiconductor Devices

Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a tool for processing semiconductor devices includes a second material disposed over a first material, and a plurality of apertures disposed within the first material and the second material. The second material comprises a higher reflectivity than the first material. Each of the apertures is adapted to retain a package component over a support.

Package-on-Package Structure with Epoxy Flux Residue

A structure includes a first package and a second package. The second package is coupled to the first package by one or more connectors. Epoxy flux residue is disposed around the connectors and in contact with the connectors. A method includes providing a first package having first connector pads and providing a second package having corresponding second connector pads. Solder paste is printed on each of the first connector pads. Epoxy flux is printed on each of the solder paste. The first and second connector pads are aligned and the packages are pressed together. The solder paste is reflowed to connect the first connector pads to the second connector pads while leaving an epoxy flux residue around each of the connections.

Process for Forming Package-on-Package Structures

A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material.

Package-on-Package Structures and Methods for Forming the Same

A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound. 1. A package comprising: [ a top surface; and', 'a metal pad at the top surface of the first package component;, 'a first package component comprising, 'a non-reflowable electrical connector over and bonded to the metal pad; and', 'a molding material over the first package component, with the non-reflowable electrical connector partially molded in the molding material and in contact with the molding material, wherein the non-reflowable electrical connector has a top surface lower than a top surface of the molding material;, 'a bottom package comprisinga top package over the bottom package; anda solder region bonding the non-reflowable electrical connector to the top package, wherein the solder region and the non-reflowable electrical connector comprise different materials.2. The package of claim 1 , wherein the top surface of the non-reflowable electrical connector comprises a rounded portion claim 1 , with a center portion of the rounded portion being lower than remaining portions of the top surface.3. The package of claim 1 , wherein the non-reflowable electrical connector has a rounded bottom surface claim 1 , with the bottom surface having a shape of a part of a ball.4. The package of further comprising a solder paste disposed between claim 3 , and in contact with claim 3 , the rounded bottom surface of the non-reflowable electrical connector.5. The package of claim 1 , wherein the non-reflowable electrical connector is in physical contact with the solder ...

Package on Package Bonding Structure and Method for Forming the Same

The described embodiments of mechanisms of forming a die package and package on package (PoP) structure involve forming a solder paste layer over metal balls of external connectors of a die package. The solder paste layer protects the metal balls from oxidation. In addition, the solder paste layer enables solder to solder bonding with another die package. Further, the solder paste layer moves an intermetallic compound (IMC) layer formed between the solder paste layer and the metal balls below a surface of a molding compound of the die package. Having the IMC layer below the surface strengthens the bonding structure between the two die packages. 1. A die package comprising:a semiconductor die attached to a substrate having interconnect structures, wherein the semiconductor die is electrically connected to the interconnect structures; and a first contact pad,', 'a metal ball with a convex surface, wherein the metal ball is bonded to the first contact pad, and', 'a solder paste layer over an upper surface of the metal ball, wherein an upper surface of the solder paste layer substantially conforms to the upper surface of the metal ball, and wherein the solder paste layer has a first portion above an upper surface of the molding compound and a second portion extending lower than the upper surface of the molding compound, wherein the second portion surrounds the first portion., 'a first external connector adjacent to the semiconductor die, wherein the first external connector is electrically connected to the interconnect structures, wherein the first external connector is embedded in a molding compound interposed between the semiconductor die and the first external connector, wherein the first external connector comprises2. The die package of claim 1 , wherein the molding compound is a molded underfill (MUF) interposed between the semiconductor die and the first external connector claim 1 , and wherein the MUF extends into a gap between the semiconductor die and the ...

Package-on-Package Structures and Methods for Forming the Same

A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound. 1. A package comprising: [ a top surface; and', 'a conductive pad at the top surface;, 'a first package component comprising, 'an electrical connector over and contacting the conductive pad, wherein a top surface of the electrical connector comprises a rounded portion, with a center portion of the rounded portion being lower than surrounding portions of the rounded portion; and', 'an encapsulating material over the first package component., 'a bottom package comprising2. The package of claim 1 , wherein the electrical connector has a rounded bottom surface claim 1 , with the rounded bottom surface having a shape of a part of a ball.3. The package of further comprising a solder paste contacting both the rounded bottom surface of the electrical connector and a top surface of the conductive pad.4. The package of further comprising:a top package over the bottom package; anda solder region bonding the electrical connector to the top package, wherein the solder region contacts the rounded portion of the top surface of the electrical connector.5. The package of claim 4 , wherein the electrical connector is formed of a non-solder conductive material.6. The package of claim 4 , wherein the encapsulating material comprises a top surface claim 4 , and the solder region extends to a level lower than the top surface of the encapsulating material.7. The package of further comprising a device die bonded to the top surface of the first package component claim 1 , wherein the ...

Packaging Process Tools and Packaging Methods for Semiconductor Devices

Packaging process tools and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure including a frame. The frame includes a plurality of apertures adapted to retain a plurality of integrated circuit dies therein. The frame includes at least one hollow region. 1. A packaging tool for semiconductor devices comprising:a mechanical structure comprising a frame including a plurality of apertures adapted to retain a plurality of integrated circuit dies therein, wherein the frame comprises at least one enclosed hollow region.2. The packaging tool according to claim 1 , further comprising:a first support for a packaging substrate; anda second support for the mechanical structure proximate the first support for the packaging substrate.3. The packaging tool according to claim 1 , wherein the frame of the mechanical structure includes a first side claim 1 , a second side opposite the first side claim 1 , and a plurality of connecting members coupled between the first side and the second side at edges of the first side and the second side.4. The packaging tool according to claim 3 , wherein the first side claim 3 , the second side claim 3 , and the plurality of connecting members of the frame comprise a thickness of about 0.1 mm to about 10 mm.5. The packaging tool according to claim 3 , wherein the first side claim 3 , the second side claim 3 , and the plurality of connecting members of the frame comprise stainless steel claim 3 , aluminum claim 3 , ceramic claim 3 , rubber claim 3 , epoxy claim 3 , a plastic polymer claim 3 , or combinations thereof.6. The packaging tool according to claim 3 , wherein the frame further comprises at least one support member coupled between the first side and the second side or between opposing connecting members.7. The packaging tool according to claim 6 , wherein the at least one support member of the frame is disposed substantially ...

Packaging Methods and Packaged Semiconductor Devices

An embodiment is a method including forming a first package and a second package. The first package includes packaging a first die, forming a plurality of solder balls on the first die, and coating the plurality of solder balls with an epoxy flux. The second package includes forming a first electrical connector, attaching a second die adjacent the first electrical connector, forming a interconnect structure over the first die and the first electrical connector, the interconnect structure being a frontside of the second package, forming a second electrical connector over the interconnect structure, and the second electrical connector being coupled to both the first die and the first electrical connector. The method further includes bonding the first package to the backside of the second package with the plurality of solder balls forming a plurality of solder joints, each of the plurality of solder joints being surrounded by the epoxy flux.

Alignment in the Packaging of Integrated Circuits

A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package, wherein the top package is aligned to the bottom package after the placing the top package over the bottom package. A reflow is then performed to bond the top package to the bottom package. 1. A method comprising:aligning a top package to a bottom package, wherein the aligning is performed using an alignment mark in the bottom package;placing the top package over the bottom package, with the top package aligned to the bottom package after the placing the top package over the bottom package; andperforming a reflow to bond the top package to the bottom package.2. The method of claim 1 , wherein the bottom package comprises a device die bonded to a substrate claim 1 , and wherein the aligning is performed using the alignment mark in the device die.3. The method of further comprising forming the bottom package comprising:bonding a device die onto a package substrate; anddispensing a molding material to mold at least a lower portion of the device die.4. The method of further comprising claim 3 , after the dispensing the molding material claim 3 , forming the alignment mark extending from a top surface of the molding material into the molding material.5. The method of further comprising claim 3 , after the dispensing the molding material claim 3 , forming the alignment mark extending from a back surface of the device die into the device die.6. The method of further comprising claim 3 , before the aligning the top package to the bottom package claim 3 , forming the device die claim 3 , wherein the forming the device die comprises forming the alignment mark.7. The method of further comprising claim 1 , before the aligning the top package to the bottom package claim 1 , placing the bottom package in an opening of a reflow boat.8. A method comprising:bonding a device die onto a package substrate to form a bottom ...

Bonding Through Multi-Shot Laser Reflow

A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot. 1. A method comprising:performing a first laser shot on a first portion of a top surface of a first package component, wherein the first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot; andafter the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, wherein a second solder region between the first package component and the second package component is reflowed by the second laser shot.2. The method of claim 1 , wherein:the first portion of the top surface overlaps a first plurality of solder regions, and the first plurality of solder regions are reflowed by the first laser shot; andthe second portion of the top surface overlaps a second plurality of solder regions, and the second plurality of solder regions are reflowed by the second laser shot.3. The method of claim 2 , wherein the first plurality of solder regions and the second plurality of solder regions comprise common solder regions.4. The method of claim 2 , wherein the first plurality of solder regions are separate ones from the second plurality of solder regions.5. The method of claim 1 , wherein the first solder region is solidified when the second laser shot is started.6. The method of further comprising:after the second laser shot, performing ...

Semiconductor Package and Method

In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region. 1. A method comprising:aligning a first package component with a second package component, the first package component having a first region and a second region, the first region comprising a first conductive connector, the second region comprising a second conductive connector;performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; andafter performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.2. The method of claim 1 , wherein the first portion and the second portion of the top surface of the first package component partially overlap.3. The method of claim ...

Process for Forming Package-on-Package Structures

A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material. 1. A method comprising:forming a first plurality of redistribution lines;forming first Z-interconnects over and electrically coupled to the first plurality of redistribution lines;attaching a first device die, wherein a portion of the first device die is substantially coplanar with a portion of the first Z-interconnects;after the forming the first Z-interconnects, encapsulating the first device die and the first Z-interconnects in a first encapsulation material; andforming a second plurality of redistribution lines electrically coupling to the first device die, wherein the first plurality of redistribution lines and the second plurality of redistribution lines are on opposite sides of the first Z-interconnects.2. The method of claim 1 , wherein the first encapsulation material comprises a photo-sensitive material claim 1 , and the method further comprises claim 1 , after the encapsulating the first encapsulation material claim 1 , performing a lithography process on the first encapsulation material to expose the first Z-interconnects and electrical connectors of the first device die.3. The method of claim 1 , wherein the first encapsulation material comprises a molding compound covering photo resist patterns of the first device die claim 1 , with the photo resist patterns covering electrical connectors of the first device die claim 1 , and wherein the ...

Semiconductor Bonding Structures and Methods

A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.

Bump-on-trace packaging structure and method for forming the same

A device comprises a first package component, and a first metal trace and a second metal trace on a top surface of the first package component. The device further includes a dielectric mask layer covering the top surface of the first package component, the first metal trace and the second metal trace, wherein the dielectric mask layer has an opening therein exposing the first metal trace. The device also includes a second package component and an interconnect formed on the second package component, the interconnect having a metal bump and a solder bump formed on the metal bump, wherein the solder bump contacts the first metal trace in the opening of the dielectric mask layer.

PACKAGE-ON-PACKAGE STRUCTURE WITH EPOXY FLUX RESIDUE

A structure includes a first package and a second package. The second package is coupled to the first package by one or more connectors. Epoxy flux residue is disposed around the connectors and in contact with the connectors. A method includes providing a first package having first connector pads and providing a second package having corresponding second connector pads. Solder paste is printed on each of the first connector pads. Epoxy flux is printed on each of the solder paste. The first and second connector pads are aligned and the packages are pressed together. The solder paste is reflowed to connect the first connector pads to the second connector pads while leaving an epoxy flux residue around each of the connections. 115-. (canceled)16. A method comprising:providing a first package having one or more first connector pads;providing a second package having second connector pads for connecting to corresponding first connector pads of the first package;printing solder paste on each of the first connector pads;printing epoxy flux on each of the solder paste;aligning the second package over the first package, wherein the aligning aligns the first connector pads of the first package with the second connector pads of the second package;pressing the first package and the second package together; andreflowing the solder paste, the reflowing creating a solder connection between each of the second connector pads and the corresponding first connector pad, wherein an epoxy flux residue forms around each of the solder connections, wherein the first package is an integrated fan out wafer level package.17. The method of claim 16 , further comprising:printing center supporting epoxy flux between at least two of the first connector pads of the first package; andcuring the center supporting epoxy flux.18. The method of claim 17 , further comprising:printing peripheral epoxy flux between at least one of the first connector pads and a lateral extent defined by an edge of the ...

Tools and Systems for Processing Semiconductor Devices, and Methods of Processing Semiconductor Devices

Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a method of using a tool for processing semiconductor devices includes a tool with a second material disposed over a first material, and a plurality of apertures disposed within the first material and the second material. The second material comprises a higher reflectivity than the first material. Each of the apertures is adapted to retain a package component over a support during an exposure to energy.

Package-on-Package Structures and Methods for Forming the Same

A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound.

Image processing method capable of reducing color shift

Contact structure

A system and method for forming contacts is provided. An embodiment comprises forming the contacts on a substrate and then coining the contacts by physically shaping them using, e.g., a molding chamber. The physical shaping of the contacts may be performed using a patterned portion of the molding chamber or else by placing a patterned stencil around the contacts prior before a force is applied to physically reshape the contacts. The contacts may be reshaped into a cylindrical, oval, cuboid, or rectangular shape, for example.

Bonding through multi-shot laser reflow

A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot.

Process for forming package-on-package structures

A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material.

Semiconductor packaging structure and method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Warpage control in a package-on-package structure

The present disclosure relates to a tool arrangement and method to reduce warpage within a package-on-package semiconductor structure, while minimizing void formation within an electrically-insulating adhesive which couples the packages. A pressure generator and a variable frequency microwave source are coupled to a process chamber which encapsulates a package-on-package semiconductor structure. The package-on-package semiconductor structure is simultaneously heated by the variable frequency microwave source at variable frequency, variable temperature, and variable duration and exposed to an elevated pressure by the pressure generator. This combination for microwave heating and elevated pressure limits the amount of warpage introduced while preventing void formation within an electrically-insulating adhesive which couples the substrates of the package-on-package semiconductor structure.

Liquid crystal display panel with eliminating image sticking abilities and method of the same

The present invention provides a liquid crystal display panel with eliminating image sticking abilities. The liquid crystal display panel includes a main thin film transistor disposed on a substrate which includes a first gate coupled to a corresponding scanning line, a first source coupled to a corresponding data line. A sub thin film transistor disposed on the substrate includes a second gate coupled to pro-scanning line of the corresponding scanning line, a second source coupled to the adjacent data line of the corresponding data line. The main thin film transistor and the sub thin film transistor are disposed on a pixel.

Pixel array structure

Package structure and manufacturing method thereof

A package structure includes a die, a first redistribution circuit structure, a first redistribution circuit structure, a second redistribution circuit structure, an enhancement layer, first conductive terminals, and second conductive terminals. The first redistribution circuit structure is disposed on a rear side of the die and electrically coupled to thereto. The second redistribution circuit structure is disposed on an active side of the die and electrically coupled thereto. The enhancement layer is disposed on the first redistribution circuit structure. The first redistribution circuit structure is disposed between the enhancement layer and the die. The first conductive terminals are connected to the first redistribution circuit structure. The first redistribution circuit structure is between the first conductive terminals and the die. The second conductive terminals are connected to the second redistribution circuit structure. The enhancement layer is between the second conductive terminals and the second redistribution circuit structure.

Package-on-Package Structure Including a Thermal Isolation Material

A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component.

Package-on-package structure including a thermal isolation material

A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component.

Liquid crystal display device

A multi-domain vertical alignment liquid crystal display device includes a data line, a first gate line, a second gate line, a first sub-pixel unit, and a second sub-pixel unit. The first sub-pixel unit includes a first switch, a first liquid-crystal capacitor and a first storage capacitor. The first switch functions to control writing the data signal of the data line into the first liquid-crystal and storage capacitors based on the first gate signal of the first gate line. The second sub-pixel unit includes a second switch, a second liquid-crystal capacitor, an auxiliary switch, a second storage capacitor and a third storage capacitor. The second and auxiliary switches are employed to control writing the data signal into the second liquid-crystal capacitor, the second storage capacitor and the third storage capacitor based on the first gate signal and the second gate signal of the second gate line respectively.

接合方法

Semiconductor package and method

In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.

Semiconductor Package and Method

In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.

Halbleiter-Package und Verfahren

In einer Ausführungsform enthält ein Verfahren Folgendes: Ausrichten einer ersten Package-Komponente auf eine zweite Package-Komponente, wobei die erste Package-Komponente eine erste Region und eine zweite Region aufweist, wobei die erste Region einen ersten leitfähigen Verbinder enthält, und die zweite Region einen zweiten leitfähigen Verbinder enthält; Ausführen eines ersten Laserimpulses auf einem ersten Abschnitt einer Oberseite der ersten Package-Komponente, wobei der erste Laserimpuls den ersten leitfähigen Verbinder der ersten Region wiederaufschmilzt, wobei der erste Abschnitt der Oberseite der ersten Package-Komponente die erste Region vollständig überlappt; und nach dem Ausführen des ersten Laserimpulses, Ausführen eines zweiten Laserimpulses auf einem zweiten Abschnitt der Oberseite der ersten Package-Komponente, wobei der zweite Laserimpuls den zweiten leitfähigen Verbinder der zweiten Region wiederaufschmilzt, und der zweite Abschnitt der Oberseite der ersten Package-Komponente die zweite Region vollständig überlappt.

Methods of forming semiconductor packages

In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region

Bonding through multi-shot laser reflow

A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot.

Driving Method and Driving Apparatus for Displaying Apparatus

A driving method for driving a display apparatus is provided. The driving method includes: configuring a plurality of driving voltages corresponding to a plurality of gray scales, where the gray scales include a first gray scale and a second gray scale smaller than the first gray scale, and a first driving voltage corresponding to the first gray scale is lower than a second driving voltage corresponding to the second gray scale; and controlling the display apparatus to display a gray scale merely up to the second gray scale. In this way, the driving method hence reduces the response time of the display apparatus, which may be an LCD display panel.

Touch display panel

Liquid crystal display panel

液晶表示パネル及びこれを用いる残像消去方法

【課題】残像を消去することのできる液晶表示パネルを提供する。 【解決手段】液晶表示パネルの第１基板の画素上にメイン薄膜トランジスタ９０とサブ薄膜トランジスタ９１が配置される。メイン薄膜トランジスタ９０は、当列走査線に接続される第１ゲート９０ａと、当列データ線に接続される第１ソース９０ｂを有する。サブ薄膜トランジスタ９１は、前列走査線に接続される第２ゲート９１ａと、次列データ線に接続される第２ソース９１ｂを有する。これにより、画素に蓄積した電荷が次列データ線から放出を促進されて効果的に残像を消去することができる。また、液晶表示時間を短縮することができる。 【選択図】図４

Driving method and driving apparatus for display apparatus

Bonding through multi-shot laser reflow

A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot.

Semiconductor bonding structures and methods

A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.

主動元件陣列基板的製造方法

Method of manufacturing active device array substrate

Method for manufacturing liquid crystal panel

Semiconductor bonding structures and methods

A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.