Lichtemittierendes Element, Beleuchtungsvorrichtung und deren Vorrichtungsrahmen

Beleuchtungsvorrichtung, umfassend:- eine Tragbasis (5);- ein lichtemittierendes Element (1), das auf der Tragbasis (5) angeordnet ist, wobei das lichtemittierende Element (1) folgendes aufweist:- ein Substrat (2) mit einer Auflagerfläche (210) und einer Seitenfläche, und- mehrere Licht emittierende Dioden-, LED, Chips (14), die auf der Auflagerfläche (210) angeordnet sind und mehrere Außenoberflächen aufweisen;- eine erste Wellenlängenumwandlungsschicht (4), die die mehreren Außenoberflächen bedeckt, ohne die Seitenfläche zu bedecken,wobei das lichtemittierende Element (1) eine erste Hauptoberfläche (21A) aufweist, die durch die mehreren Außenoberflächen gebildet wird und einen Teil der Auflagerfläche (210), der nicht von den mehreren LED Chips (14) bedeckt ist, und eine zweite Hauptoberfläche (21B) aufweist, die der Auflagerfläche (210) gegenüberliegt,wobei wenigstens einer der mehreren LED Chips (14) betrieben wird, um Licht zu emittieren, welches vorgesehen ist, das Substrat (2) zu ...

Alternate bump metallurgy bars for power and ground routing

Semiconductor package and method of manufacturing thereof

ASSEMBLING AN INTEGRATED CIRCUIT DIE AND A PLATE

Method for assembling e.g. two components in face to face manner, involves depositing volume of welding material on surface, where welding material comprises melting point, which is higher than that of another welding material

Un procédé d'assemblage face contre face d'un premier et d'un deuxième composants (34, 42), consiste : ▪ à réaliser entre les composants : o des colonnes (30, 38, 46) ayant un volume (38) de premier matériau de soudure; o des calles (36, 40) de hauteur inférieure à celle colonnes (30, 38, 46), et ayant une température de fusion supérieure à celle des colonnes ; et ▪ à appliquer un premier chauffage aux colonnes (30, 38, 46) à une température supérieure à la température de fusion des colonnes de soudure et inférieure à la température de fusion des calles (36, 40), La réalisation d'une calle (36, 40) consiste à : ▪ à réaliser une surface mouillable (36) sur le premier ou le deuxième composant (34); ▪ à déposer un volume (40) de deuxième matériau de soudure sur la surface mouillable (36), de température de fusion supérieure à celle des colonnes ; et ▪ à appliquer un deuxième chauffage au volume (40) de deuxième matériau à une température supérieure à la température de fusion du deuxième matériau ...

반도체 패키지 및 반도체 패키지 모듈

... 범프를 통하여 회로 기판과 연결되는 반도체 패키지가 제공된다. 본 발명의 일 실시예에 따른 반도체 패키지는, 복수개의 접속 패드가 노출되도록 형성된 반도체 칩; 상기 각 접속 패드 상에 형성되며, 제1 필라부 및 상기 제1 필라부 상측에 형성되는 제1 솔더부를 포함하는 연결용 범프들; 상기 접속 패드 주변에서 상기 접속 패드의 상부 표면 보다 높은 위치에 형성되며, 솔더 유도부가 형성되어 있는 제2 필라부 및 상기 제2 필라부 상측에 형성되는 제2 솔더부를 포함하는 지지용 범프들;을 포함한다.

Device and method for an integrated ultra-high-density device

A device and method for an integrated device includes a first redistribution layer comprising one or more first conductors, one or more first dies mounted to a first surface of the first redistribution layer and electrically coupled to the first conductors, one or more first posts having first ends attached to the first dies and second ends opposite the first ends, one or more second posts having third ends attached to the first surface of the first redistribution layer and fourth ends opposite the third ends, and a second redistribution layer comprising one or more second conductors, the second redistribution layer being attached to the second ends of the first posts and to the fourth ends of the second posts. In some embodiments, the integrated device further includes a heat spreader mounted to a second surface of the first redistribution layer. The second surface is opposite the first surface.

Method and system for packing optimization of semiconductor devices

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

Method for producing a semiconductor device and corresponding semiconductor device

The present invention provides a method for producing a semiconductor device, with the steps of: applying an interconnect level (11, 12) to a semiconductor substrate (10); structuring the interconnect level (12); and applying a solder layer (13) on the structured interconnect level (11, 12) in such a way that the solder layer ...

CONTROLLED-SHAPED SOLDER RESERVOIRS FOR INCREASING THE VOLUME OF SOLDER BUMPS, AND STRUCTURES FORMED THEREBY

Electronic device, method for manufacturing the electronic device, and electronic apparatus

An electronic device includes: a first circuit board; a second circuit board located above a first region of the first circuit board; a first semiconductor element located above a second region of the first circuit board, which is different from the first region, and above a third region of the second circuit board; a first connection interposed between the first semiconductor element and the second region so as to electrically interconnect the first semiconductor element and the first circuit board; and a second connection interposed between the first semiconductor element and the third region so as to electrically interconnect the first semiconductor element and the second circuit board.

Fan-out wafer-level packaging using metal foil lamination

Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.

BUMP STRUCTURE HAVING A SIDE RECESS AND SEMICONDUCTOR STRUCTURE INCLUDING THE SAME

The present disclosure, in some embodiments, relates to a bump structure. The bump structure includes a conductive layer and a solder layer. The solder layer is disposed vertically below and laterally between portions of the conductive layer along a cross-section. The conductive layer is continuous between the portions. 1. A bump structure , comprising:a conductive layer;a solder layer; andwherein the solder layer is disposed vertically below and laterally between portions of the conductive layer along a cross-section, the conductive layer continuous between the portions.2. The bump structure of claim 1 , wherein the solder layer is directly between sidewalls of the conductive layer along the cross-section.3. The bump structure of claim 2 , wherein the sidewalls of the conductive layer extend between a top surface of the conductive layer and a bottom surface of the conductive layer.4. The bump structure of claim 2 , wherein the sidewalls of the conductive layer are arranged along an outer perimeter of the conductive layer.5. The bump structure of claim 2 ,wherein the sidewalls of the conductive layer define a recessed region along a side of the conductive layer, the recessed region having a first width along a first direction; andwherein a ratio of the first width to a maximum width of the conductive layer along the first direction is in a range of between about 0.02 and about 0.5.6. The bump structure of claim 1 , wherein the conductive layer has a smaller height along a vertical direction than the solder layer.7. The bump structure of claim 1 , wherein the solder layer contacts an outermost sidewall of the conductive layer along a second cross-section that is perpendicular to the cross-section.8. The bump structure of claim 1 , wherein the conductive layer comprises a metal.9. A conductive bump structure claim 1 , comprising:a conductive layer;a solder material contacting a bottom of the conductive layer along an interface; andwherein the solder material ...

SEMICONDUCTOR DEVICE

A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.

Interconnect for electronic device

A semiconductor die includes a substrate and an integrated circuit provided on the substrate and having contacts. An electrically conductive layer is provided on the integrated circuit and defines electrically conductive elements electrically connected to the contacts. Electrically conductive interconnects coupled with respective electrically conductive elements. The electrically conductive interconnects have at least one of different sizes or shapes from one another.

MANUFACTURING METHOD OF PRINTED CIRCUIT BOARD UNIT, MANUFACTURING APPARATUS THEREOF, MANUFACTURING METHOD OF ELECTRONIC COMPONENT, AND ELECTRONIC COMPONENT

A manufacturing method of a printed circuit board unit is provided. A portion of bumps which is arranged on an electronic component is pressed to lower heights of the portion of bumps as compared to other bumps.

Substrate Stand-Offs for Semiconductor Devices

Substrate stand-offs for use with semiconductor devices are provided. Active pillars and dummy pillars are formed on a first substrate such that the dummy pillars may have a height greater than a height of the active pillars. The dummy pillars act as stand-offs when joining the first substrate to a second substrate, thereby creating greater uniformity. In an embodiment, the dummy pillars may be formed simultaneously as the active pillars by forming a patterned mask having openings with a smaller width for the dummy pillars than for the active pillars. When an electro-plating process of the like is used to form the dummy and active pillars, the smaller width of the dummy pillar openings in the patterned mask causes the dummy pillars to have a greater height than the active pillars.

Mechanisms for forming hybrid bonding structures with elongated bumps

Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

Semiconductor device package and method for forming the same

A semiconductor device package ready for assembly includes: a semiconductor substrate; a first under-bump-metallurgy (UBM) layer disposed on the semiconductor substrate; a first conductive pillar disposed on the first UBM layer; and a second conductive pillar disposed on the first conductive pillar. A material of the first conductive pillar is different from a material of the second conductive pillar, and the material of the second conductive pillar includes an antioxidant.

Semiconductor device and semiconductor package

A semiconductor device includes a semiconductor die having a first surface and a second surface opposite to the first surface, a plurality of first real conductive pillars in a first region on the first surface, and a plurality of supporters in a second region adjacent to the first region. An area density of the plurality of supporters in the second region is in a range of from about 50% to about 100% to an area density of the plurality of first real conductive pillars in the first region. A method for manufacturing a semiconductor package including the semiconductor device is also disclosed in the present disclosure.

Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structurs formed thereby

A controlled-shaped solder reservoir (32) provides additional solder to a bump (36) in the flow step for increasing the volume of solder forming the solder bump (36). The controlled shaped reservoirs (32) can be shaped and sized to provide predetermined amounts of solder to the solder bump (36). Thus, the height of the resulting solder bump can be predetermined. The solder reservoirs (32) can be shaped to take a minimum amount of space, such as by at least partially wrapping around the solder bump. Consequently, the solder bumps may have increased height without adding to the space requirements of the solder bump, or without increasing the fabrication cost. In addition, due to the finite time required for solder flow, a means of sequencing events during soldering is provided.

Chipanordnungen

Chipanordnung (310), welche aufweist:eine Leiterplatte (362), welche aufweist:• ein Durchgangsloch (364), das in der Leiterplatte (362) ausgebildet ist,• und ein oder mehrere Leiterplattenkontaktgebiete (366S, 366G, 366D) , die in der Nähe des Durchgangslochs (364) angeordnet sind, undein Chipgehäuse (210, 160) mit einem Chip (104), das innerhalb des Durchgangslochs (364) angeordnet ist, wobei mindestens ein Leiterplattenkontaktgebiet (366S, 366G) elektrisch mit einem oder mit mehreren elektrisch leitenden Verbindungsstrukturen (144, 146) verbunden ist, die über einer Oberseite (152) des Chipgehäuses (210, 160) ausgebildet sind und in elektrischem Kontakt mit einer Chipoberseite (122) stehen, undwobei mindestens ein weiteres Leiterplattenkontaktgebiet (366D) elektrisch mit einer elektrisch leitenden Verbindungsstruktur (148) verbunden ist, die über einer Unterseite (154) des Chipgehäuses (210, 160) ausgebildet ist und in elektrischem Kontakt mit einer Chipunterseite (124) steht,wobei das ...

Substrate on which ball grid array type electrical part is mounted and method for mounting ball grid array type electrical part on substrate

Microelectronic joining processes

Wafer level packaging of light emitting diodes (LEDs)

An LED wafer includes LED dies on an LED substrate. The LED wafer and a carrier wafer are joined. The LED wafer that is joined to the carrier wafer is shaped. Wavelength conversion material is applied to the LED wafer that is shaped. Singulation is performed to provide LED dies that are joined to a carrier die. The singulated devices may be mounted in an LED fixture to provide high light output per unit area.

IMPROVED METHOD FOR PRODUCING A STRUCTURE CONTACT ELEMENT

Semiconductor package

MICROELECTRONIC ASSEMBLY WITH THERMALLY AND ELECTRICALLY CONDUCTIVE UNDERFILL

A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer.

Semiconductor devices having through electrodes, methods of manufacturing the same, and semiconductor packages including the same

A semiconductor device includes a semiconductor layer having a first surface and a second surface, a through electrode penetrating the semiconductor layer and having a protruding portion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed on the first surface of the semiconductor layer and electrically coupled to the through electrode, a passivation pattern including a first insulation pattern that surrounds a sidewall of the protruding portion of the through electrode and extends onto the second surface of the semiconductor layer and a second insulation pattern that covers the first insulation pattern and has an etch selectivity with respect to the first insulation pattern, and a back-side bump covering an end surface of the protruding portion of the through electrode and extending onto the passivation pattern.

CHIP PACKAGES, CHIP ARRANGEMENTS, A CIRCUIT BOARD, AND METHODS FOR MANUFACTURING CHIP PACKAGES

A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.

Electronic assembly having multi-material interconnects

According to one aspect of the invention, an electronic assembly is provided. The electronic assembly includes a first substrate having an integrated circuit formed therein and a second substrate. The first and second substrates are interconnected by a plurality of bi-material interconnects that are electrically connected to the integrated circuit and have a first component comprising a conductive first material with a first coefficient of thermal expansion and a second component comprising a second material with a second coefficient of thermal expansion. The first and second components are connected and shaped such that when the temperature of the bi-material interconnects changes the interconnects each bend towards the first or second component. When the temperature of the second substrate increases, the second substrate expands away from a central portion thereof. The bi-material interconnects are arranged such that the bi-material interconnects bend away from the central portion of ...

Method and apparatus for improved power routing

An apparatus comprising: a die having a top metal layer, the top metal layer comprised of at least a first metal line and a second metal line; a passivation layer covering the top metal layer; a C4 bump on the passivation layer; and a first passivation opening and a second passivation opening in the passivation layer, the first passivation opening to connect the first metal line to the C4 bump, and the second passivation opening to connect the second metal line to the C4 bump.

CONNECTION STRUCTURE

A method for manufacturing connection structure, the method includes arranging conductive particles and a first composite on a first electrode located on a first surface of a first member, arranging a second composite on the first electrode and a region other than the first electrode of the first surface, arranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite.

Capacitor and semiconductor device and method for fabricating the semiconductor device

A capacitor comprises a first conducting film 12 formed on a substrate 10, a first dielectric film 14 formed on the first conducting film, a second conducting film 18 formed on the first dielectric film, a second dielectric film 22 formed above the second conducting film, covering the edge of the second conducting film, a third conducting film 34 formed above the second dielectric film, covering a part of the second dielectric film covering the edge of the second conducting film. The capacitor further comprises an insulation film 28 covering the edge of the second conducting film or the part of the second dielectric film. An effective thickness of the insulation film between the second conducting film and the third conducting film in the region near the edge of the second conducting film can be increased, whereby concentration of electric fields in the region near the edge of the second conducting film. Consequently, the capacitor can have large capacitance without lowering voltage resistance ...

Apparatus and methods for substantial planarization of solder bumps

Apparatus and methods for substantial planarization of solder bumps. In one embodiment, an apparatus includes a planarization member engageable with at least some of the plurality of outer surfaces to apply a planarization action on one or more of the outer surfaces to substantially planarize the plurality of outer surfaces, and a securing element to securely position the bumped device during engagement with the planarization member, Through application of "additive" and/or "subtractive" processes, the solder balls are substantially planarized. In alternate embodiments, the planarization member includes a cutting tool and the planarization action comprises a milling action; or the planarization member includes a heated platen and the planarization action comprises a thermo-mechanical deformation action; or the planarization member includes an abrasive surface and the planarization action comprises a grinding action; or the planarization member includes a chemical solution and the planarization ...

Illumination device with inclined light emitting element disposed on a transparent substrate

A semiconductor light emitting element includes a transparent substrate and a plurality of light emitting diode (LED) structures. The transparent substrate has a support surface and a second main surface disposed opposite to each other. At least some of the LED structures are disposed on the support surface and form a first main surface where light emitted from with a part of the support surface without the LED structures. Each of the LED structures includes a first electrode and a second electrode. Light emitted from at least one of the LED structures passes through the transparent substrate and emerges from the second main surface. An illumination device includes the semiconductor light emitting element and a supporting base. The semiconductor light emitting element is disposed on the supporting base, and an angle is formed between the semiconductor light emitting element and the supporting base.

Electrical contact alignment posts

An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.

Stress Reduction in Chip Packaging by Using a Low-Temperature Chip-Package Connection Regime

A semiconductor chip and a package substrate may be directly connected on the basis of form closure by providing appropriately shaped complementary contact structures in the semiconductor chip and the package substrate. Consequently, solder material may no longer be required and thus any elevated temperatures during the assembly process may be avoided, which may conventionally result in significant stress forces, thereby creating damage, in particular in very complex metallization systems.

Bump-on-Trace Structures with High Assembly Yield

A package includes first package component, which further includes a first metal trace at a surface of the first package component, with the first metal trace having a trace width measured in a direction perpendicular to a lengthwise direction of the first metal trace. The first package component further includes a second metal trace at the surface of the first package component. The first metal trace and the second metal trace are parallel to each other. A second package component is overlying the first package component, wherein the second package component includes a metal bump. A solder region bonds the metal bump to the first metal trace, wherein the solder region contacts a top surface and sidewalls of the first portion of the first metal trace. A ratio of a volume of the solder region to the trace width is between about 1,100 μm2 and about 1,300 μm2.

Bump structure design for stress reduction

Low stress bumps can be used to reduce stress and strain on bumps bonded to a substrate with different coefficients of thermal expansion (CTEs) from the die. The low stress bumps include multiple polymer layers. More than one type of bump is coupled to a die, with low stress bumps placed on areas subjected to high stress.

SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor device of which operational reliability is improved. SOLUTION: A bump electrode 8s for a source electrode is provided as an oscillation shield between a bump electrode 8g for the gate electrode of a semiconductor chip 1 constituting an RF power module and a bump electrode 8d for a drain electrode. The bump electrode 8s for the source electrode is formed like a longer band pattern than the other bump electrodes 8g and 8d. The bump electrodes 8g, 8d and 8s have a vertical structure wherein a metal layer is formed on a bonding pad with a base metal in-between and a solder layer is formed thereon. COPYRIGHT: (C)2007,JPO&INPIT ...

FLIP CHIP STRUCTURE OF SEMICONDUCTOR

PROBLEM TO BE SOLVED: To provide a flip chip structure of a semiconductor which has a soldered pillar-shaped bump at a surface joining device. SOLUTION: The flip chip structure of a semiconductor includes a substrate 210, a chip 220, and a first solder 230 and additional solder 240. On the substrate 210, first connecting pads 211 and additional pads 212 are located, and the first connecting pads 211 are arranged on a first arranged line, and along it, the first connecting pad width and the first connecting pad pitch are defined. The first connecting pad pitch is longer than the first connecting pad width. On the chip 220, a group of first pillar-shaped bumps 221 which extrude on the same surface older-jointed to a group of the first connecting pads 211 through a group of the first solders 230 and a group of additional bumps 222 which are solder-jointed to a group of the additional pads 212 through a group of the additional solders 240. COPYRIGHT: (C)2011,JPO&INPIT ...

МЕТАЛЛИЧЕСКИЙ НАПОЛНИТЕЛЬ, РАЗДЕЛЯЮЩИЙ СЛОИ р- И n-ТИПА, ДЛЯ СВЕТОИЗЛУЧАЮЩИХ ДИОДОВ, МОНТИРУЕМЫХ МЕТОДОМ ПЕРЕВЕРНУТОГО КРИСТАЛЛА

Структура (10) светоизлучающих диодов (СИДов) имеет полупроводниковые слои, включающие в себя слой p-типа, активный слой и слой n-типа. Слой p-типа имеет нижнюю поверхность, а слой n-типа имеет верхнюю поверхность, через которую излучается свет. Участки слоя p-типа и активного слоя стравливают, открывая слой n-типа. На поверхности СИДа формируют рисунок с помощью фоторезиста и на открытых поверхностях осаждают медь, формируя p- и n-электроды, находящиеся в электрическом контакте с соответствующими им полупроводниковыми слоями. Между p- и n-электродами имеется зазор. Для обеспечения механической поддержки полупроводниковых слоев в пределах зазора в зазоре формируют диэлектрический слой (34) с последующим заполнением зазора металлом (42). В металле формируют рисунок, чтобы сформировать столбиковые выводы (40, 42, 44), которые, по существу, покрывают нижнюю поверхность кристалла СИДа, но не замыкают электроды накоротко. По существу, равномерное покрытие поддерживает полупроводниковый слой ...

МЕТАЛЛИЧЕСКИЙ НАПОЛНИТЕЛЬ, РАЗДЕЛЯЮЩИЙ СЛОИ Р- И N-ТИПА, ДЛЯ СВЕТОИЗЛУЧАЮЩИХ ДИОДОВ, МОНТИРУЕМЫХ МЕТОДОМ ПЕРЕВЕРНУТОГО КРИСТАЛЛА

... 1. Структура перевернутых кристаллов светоизлучающих диодов (СИДов), содержащая:полупроводниковые слои, включающие в себя слой первой проводимости, активный слой и слой второй проводимости, причем полупроводниковые слои имеют нижнюю поверхность, обращенную к кристаллодержателю, и верхнюю поверхность, через которую излучается свет;первый электрод напротив нижней поверхности, электрически соединенный со слоем первой проводимости;второй электрод напротив нижней поверхности, электрически соединенный со слоем второй проводимости, причем между первым электродом и вторым электродом имеется, по меньшей мере, один зазор;первый диэлектрический слой, изолирующий боковые стенки упомянутого, по меньшей мере, одного зазора; ипервый металлический слой, сформированный отдельно от первого электрода и второго электрода, причем первый участок первого металлического слоя, по меньшей мере, частично заполняет упомянутый, по меньшей мере, один зазор и электрически изолирован от второго электрода.2. Структура ...

Substrate on which ball grid array type electrical part is mounted and method for mounting ball grid array type electrical part on substrate

HIGH HEAT DISSIPATION SOLDER-REFLOW FLIP CHIP TRANSISTOR

HIGH HEAT DISSIPATION SOLDER-REFLOW FLIP CHIP TRANSISTOR

SELF-ALIGNING ELECTRICAL CONTACT ARRAY

A surface mount component placement arrangement includes a circuit supporting substrate (202) having a first surface (308), and disposed thereon are a first pad array (502) and a first at least one aligning pad (506). A component (802) has a second surface (801), the second surface (801) substantially opposing the first surface (308), and disposed on the second surface (801) are second pad array (406) and a second at least one aligning pad (508). The first and second pad arrays (406, 502) at least partially overlap with each other. The aligning pads (506, 508) at least partially overlap with each other relative to a second tolerance of the placement operation. The partially overlapping pair of pads (506, 508) are oriented relative to each other such that when solder therebetween is liquid the surface tension of the solder can move the component (802) relative to the circuit supporting substrate.

Surface mounting chip

Snubber circuit and method of using bipolar junction transistor in snubber circuit

MANUFACTORING PROCESS OF STUDS OF ELECTRIC CONNECTION Of a PLATE

Procédé de fabrication de plots de connexion électrique sur une face d'une plaque, comprenant : la réalisation de zones conductrices de l'électricité (6a, 6b) et de branches de connexion électrique (7) reliant ces zones; le dépôt d'une couche (8) en une matière de masque; la réalisation, dans cette couche de masque, d'ouvertures (9a, 9b) qui s'étendent au-dessus desdites zones conductrices et dont au moins certaines (9a) s'étendent au moins en partie au-delà des bords périphériques des zones conductrices sous-jacentes (6a) ; la réalisation de blocs (12a, 12b) en une matière de soudure dans lesdites ouvertures par dépôt électrolytique dans un bain; la suppression de la matière de masque; la coupure des branches de connexion (7) ; et le passage ou la mise dans un four de façon à conformer, sur les zones conductrices, lesdits blocs en des plots de connexion électrique (3a, 3b) substantiellement bombés.

A METHOD OF JOINING TWO ELECTRONIC COMPONENTS TOGETHER, FLIP CHIP TYPE

L'invention concerne un procédé d'assemblage de type flip-chip, de deux composants microélectroniques (1,2) l'un à l'autre. Selon l'invention, on prévoit soit de dimensionner des cales (24) en sus des protubérances d'interconnexion (22) soit de sur-dimensionner ces dernières de sorte que leur déformation revienne élastique une fois le contact d'assemblage entre composants (1, 2) atteint, après avoir été plastique lors de l'insertion par des inserts (12) de connexion. Grâce à l'invention, on peut maîtriser très finement l'espacement entre les deux composants lors de leur assemblage et ceci sans ajouter d'étape supplémentaire à leur fabrication ni au process d'assemblage.

HIGH HEAT DISSIPATION SOLDER-REFLOW FLIP CHIP TRANSISTOR

ASSEMBLING A INTEGRATED CIRCUIT DIE AND A PLATE

FLIP CHIP PACKAGE HAVING CHIP FIXING STRUCTURE

A flip chip package comprises: a chip having a main bump and a dummy bump arranged in a first area and a second area, respectively; a substrate having a dam protruded from one surface, and a connection pad connected to the main bump; and an attaching means for mutually attaching the dummy bump and the dam. COPYRIGHT KIPO 2016 ...

METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE CAPABLE OF SUPPRESSING A DIFFERENCE IN THERMAL EXPANSION COEFFICIENTS BETWEEN A CAP SUBSTRATE WAFER AND A DEVICE SUBSTRATE WAFER

PURPOSE: A method for manufacturing a semiconductor package is provided to prevent creak or twisting generated when boning cap substrate wafer and a device substrate wafer by bonding the cap substrate wafer with the device substrate wafer at a lower temperature, slicing the cap substrate wafer into chip sizes, and then bonding them with each other at a high temperature. CONSTITUTION: A via and a via electrode, which is connected to the via, are arranged on a lower surface of a cap substrate wafer. Plural external terminals are connected to the via. A circuit portion and a connection electrode, which is connected to the circuit portion, are formed on an upper surface of a device substrate wafer(20). The capacitor substrate wafer is bonded with the device substrate wafer at a primary bonding process by using a primary adhesive agent(30). A trench(50), which exposes the upper surface of the device substrate wafer, is formed along an outer periphery of the primary adhesive agent. A secondary ...

Method of connecting an integrated circuit to a substrate and corresponding circuit arrangement

ELECTRONIC STRUCTURE AND MANUFACTURING METHOD THEREOF

Integrated circuit packaging system with active surface heat removal and method of manufacture thereof

Method of repairing pillar bumps

Semiconductor package assembly and method for forming the same

STACKED PACKAGE STRUCTURE FOR INTEGRATED CIRCUITS

In an apparatus for connecting integrated circuit devices, a plurality of primary electrically conductive contacts and a plurality of primary electrically conductive pillars are electrically coupled to a primary integrated circuit device. The plurality of primary electrically conductive contacts form a pattern corresponding to secondary electrically conductive contacts disposed on one or more secondary integrated circuit devices. The plurality of primary electrically conductive pillars extends away from the primary integrated circuit device. The plurality of primary electrically conductive pillars forms a pattern that corresponds to substrate electrically conductive contacts that are disposed on a substrate. The plurality of primary electrically conductive pillars and associated connecting material provide a standoff height between the primary integrated circuit device and the substrate that is greater than or equal to a height of the one or more secondary integrated circuit devices.

Apparatus and methods for substantial planarization of solder bumps

Apparatus and methods for substantial planarization of solder bumps. In one embodiment, an apparatus includes a planarization member engageable with at least some of the plurality of outer surfaces to apply a planarization action on one or more of the outer surfaces to substantially planarize the plurality of outer surfaces, and a securing element to securely position the bumped device during engagement with the planarization member. Through application of "additive" and/or "subtractive" processes, the solder balls are substantially planarized. In alternate embodiments, the planarization member includes a cutting tool and the planarization action comprises a milling action; or the planarization member includes a heated platen and the planarization action comprises a thermo-mechanical deformation action; or the planarization member includes an abrasive surface and the planarization action comprises a grinding action; or the planarization member includes a chemical solution and the planarization ...

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE SAME

A semiconductor device includes a semiconductor die having a first surface and a second surface opposite to the first surface, a plurality of first real conductive pillars in a first region on the first surface, and a plurality of supporters in a second region adjacent to the first region. An area density of the plurality of supporters in the second region is in a range of from about 50% to about 100% to an area density of the plurality of first real conductive pillars in the first region. A method for manufacturing a semiconductor package including the semiconductor device is also disclosed in the present disclosure. 1. A semiconductor device , comprising:a semiconductor die having a surface;a first real conductive pillar in a first region on the surface;a supporter in a second region adjacent to the first region; anda conductive wiring layer electrically coupled to the first real conductive pillar.2. The semiconductor device of claim 1 , wherein the second region is around the first region.3. The semiconductor device of claim 1 , further comprising a plurality of the supporters and a plurality of the first real conductive pillars claim 1 , wherein a pitch of the supporters is substantially the same as a pitch of the first real conductive pillars.4. The semiconductor device of claim 1 , further comprising a plurality of the first real conductive pillars claim 1 , wherein a pitch of the first real conductive pillars is substantially the same as a smallest distance between the supporter and the first real conductive pillar adjacent to the supporter.5. The semiconductor device of claim 1 , wherein an upper surface of the supporter substantially aligns to an upper surface of the first real conductive pillars.6. The semiconductor device of claim 5 , further comprising an encapsulant encapsulating the semiconductor die and a lateral surface of the supporter.7. The semiconductor device of claim 1 , wherein the semiconductor die comprises a bridge trace below the supporter ...

Chip package and method for fabricating the same

A chip package includes a semiconductor substrate, a first metal pad over the semiconductor substrate, and a second metal pad over the semiconductor substrate. In a case, the first metal pad is tape automated bonded thereto, and the second metal pad is solder bonded thereto. In another case, the first metal pad is tape automated bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is solder bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is solder bonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is wirebonded thereto.

MICROELECTRONIC ASSEMBLY WITH THERMALLY AND ELECTRICALLY CONDUCTIVE UNDERFILL

A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer ...

Semiconductor die packages using thin dies and metal substrates

A semiconductor die package is disclosed. The semiconductor die package comprises a metal substrate, and a semiconductor die comprising a first surface comprising a first electrical terminal, a second surface including a second electrical terminal, and at least one aperture. The metal substrate is attached to the second surface. A plurality of conductive structures is on the semiconductor die, and includes at least one conductive structure disposed in the at least one aperture. Other conductive structures may be disposed on the first surface of the semiconductor die.

Capacitor and semiconductor device and method for fabricating the semiconductor device

A capacitor comprises a first conducting film 12 formed on a substrate 10, a first dielectric film 14 formed on the first conducting film, a second conducting film 18 formed on the first dielectric film, a second dielectric film 22 formed above the second conducting film, covering the edge of the second conducting film, a third conducting film 34 formed above the second dielectric film, covering a part of the second dielectric film covering the edge of the second conducting film. The capacitor further comprises an insulation film 28 covering the edge of the second conducing film or the part of the second dielectric film. An effective thickness of the insulation film between the second conducting film and the third conducing film in the region near the edge of the second conducting film can be increased, whereby concentration of electric fields in the region near the edge of the second conducting film. Consequently, the capacitor can have large capacitance without lowering voltage resistance ...

Method and system for packing optimization of semiconductor devices

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

Integrated circuit packages and methods of forming same

Integrated circuit packages and methods of forming the same are disclosed. A first die is mounted on a first side of a workpiece, the workpiece including a second die. The workpiece is mounted to a front side of a package substrate, where the first die is at least partially disposed in a through hole in the package substrate. A heat dissipation feature may be attached on a second side of the workpiece. An encapsulant may be formed on the front side of the package substrate around the workpiece.

Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structurs formed thereby

A controlled-shaped solder reservoir (32) provides additional solder to a bump (36) in the flow step for increasing the volume of solder forming the solder bump (36). The controlled shaped reservoirs (32) can be shaped and sized to provide predetermined amounts of solder to the solder bump (36). Thus, the height of the resulting solder bump can be predetermined. The solder reservoirs (32) can be shaped to take a minimum amount of space, such as by at least partially wrapping around the solder bump. Consequently, the solder bumps may have increased height without adding to the space requirements of the solder bump, or without increasing the fabrication cost. In addition, due to the finite time required for solder flow, a means of sequencing events during soldering is provided.

LOTHÖCKERMETALLURGIESCHIENEN FÜR VERSORGUNGS- UND MASSENLEITUNGSFÜHRUNG

Chipgehäuse, Chipanordnungen, eine Leiterplatte und Verfahren zur Herstellung von Chipgehäusen

Es ist ein Chipgehäuse (210) vorgesehen, welches aufweist: einen Chipträger (102), einen Chip (104), der über einer Chipträgeroberseite (106) angeordnet ist und elektrisch damit verbunden ist, ein elektrisch isolierendes Material (108), das über dem Chip (104) angeordnet ist und diesen zumindest teilweise umgibt, ein oder mehrere elektrisch leitende Kontaktgebiete (112), die über dem elektrisch isolierenden Material (108) ausgebildet sind und in elektrischer Verbindung mit dem Chip (104) stehen, und ein weiteres elektrisch isolierendes Material (114), das über einer Chipträgerunterseite angeordnet ist, wobei ein elektrisch leitendes Kontaktgebiet (112) auf der Chipträgerunterseite von dem weiteren elektrisch isolierenden Material (114) befreit ist.

PLUMB BOB PEAK METALLURGY RAILS FOR VERSORGUNGSUND MASS WIRING

Packaging structure and forming method thereof

Can not be remove the bump non-lead package

Semiconductor device and method for manufacturing the same

With passes through the encapsulation of the interconnected semiconductor device assembly and the associated system, device and method

Structure for microelectronic packaging with bond elements to encapsulation surface

A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element.

Semiconductor device

To provide a semiconductor device with a wafer level package structure that allows for probing while reducing the area occupied by the pad electrodes. In the present invention, the following are provided: a semiconductor chip (100) that has first and second pad electrodes (120a, 120b) disposed on the main surface thereof; insulating films (310, 330) that cover the main surface of the semiconductor chip (100); a rewiring layer (320) that is disposed between the insulating films (310, 330); and a plurality of external terminals (340) disposed on the top of the insulating film (330). The plane size of the first pad electrode (120a) and the second pad electrode (120b) differ from one another, and the first pad electrode (120a) and the second pad electrode (120b) are connected to any of the plurality of external terminals (340) via the rewiring layer (320). According to the present invention, because the pad electrodes (120a, 120b) of different sizes are intermixed, probing can be easily performed ...

Bonding method for chips and driving chip of display

A chip bonding method for bonding a chip on a display panel is provided. The chip includes a joint face, a rear face, a plurality of input bumps and a plurality of output bums. The joint face having a first symmetry axis is relative to the rear face. The plurality of input bumps located on one side of the symmetry axis are disposed on the joint face and the plurality of output bumps located on the other side of the symmetry axis are disposed on the joint face. The chip bonding method includes: calculating a first centroid collectively formed by a contact face of each input bumps and each output bumps, defining a straight line passes the first centroid and is parallel to the first symmetry axis, and applying pressure on the rear face of the chip by a force face which is parallel to the joint face, wherein the force face having at least one second symmetry axes which is aligned parallel to the straight line.

STRESS FREE PACKAGE AND LAMINATE-BASED ISOLATOR PACKAGE

Various methods are described where the semiconductor die and the lead frame (or the BGA or LGA substrate) are spaced apart to reduce stress. In one scenario, an air gap is formed between the semiconductor die and the lead frame by depositing a perimeter (made, for example, using polymer) either on the semiconductor die or the lead frame. In another scenario, an anisotropic conducting film (ACF) is formed with an air gap between the semiconductor die and the lead frame (or the BGA or LGA substrate). The air gap relieves stress on the semiconductor die. Further, a lead frame-based isolator package and a BGA (or LGA) isolator package are described. A window-frame ACF based isolation method for magnetic coupling in a lead-frame package and BGA (or LGA) package is also described.

Semiconductor device having bumps in a same row for staggered probing

A semiconductor device has a plurality of bumps in a same row for staggered probing. The bumps in a same row are disposed on a chip and include a plurality of regular bumps and a plurality of irregular bumps. The regular bumps and the irregular bumps are interspersed in a same pitch. Along a defined line, the widths of the irregular bumps are narrower than the ones of the regular bumps for fine pitch applications. Additionally, the irregular bumps have a plurality of integral probed portions far away the line, top surfaces of which are expanded such that probed points can be defined on the probed portions for staggered probing.

Electronic apparatus, fabrication method therefor and electronic part

An electronic apparatus includes a first circuit board, a stacked circuit that is provided on the first circuit board through first coupling terminals and has a structure in which arithmetic elements and memory elements are stacked through inter-element coupling terminals and to which a signal is inputted from the first circuit board, and a second circuit board that is provided on the stacked circuit through second coupling terminals and to which a result of processing is outputted from the stacked circuit, wherein a number of the first coupling terminals and a number of the second coupling terminals are smaller than that of the inter-element coupling terminals.

Fabrication method and structure of PCB assembly, and tool for assembly thereof

A fabrication method and structure for a PBCA, and tool for assembly of the structure. The structure includes a circuit board, at least one first solder joint, a plurality of second solder joints, and an electronic device. The circuit board has a solder mask, having a plurality of openings exposing at least one first pad and a plurality of second pads arranged beyond the first pad, on a surface. The first solder joint has a maximum width J1 and electrically connects to the first pad. The second solder joints respectively have a maximum width J2 exceeding J1 and respectively electrically connect to the second pads. The electronic device has a plurality of third pads, arranged substantially corresponding to the openings, respectively electrically connecting to the first pad and second pads.

Semiconductor device of chip-on-chip structure

A semiconductor device including a first semiconductor chip, a second semiconductor chip bonded to the first semiconductor chip in a stacked relation, and a registration structure which causes the first and second semiconductor chips to be positioned with respect to each other by depression-projection engagement therebetween. The registration structure includes, for example, a registration recess provided on a surface of the first semiconductor chip, and a registration projection provided on a surface of the second semiconductor chip for engagement with the registration recess. The registration projection may be a spherical member provided on the surface of the second semiconductor chip.

Repairing anomalous stiff pillar bumps

A system for repairing pillar bumps includes a pillar bump repair device that is adapted to form a plurality of strain-relieving notches in a pillar bump that is positioned above a metallization system of a semiconductor chip. The system further includes a pillar bump support device that is adapted to substantially support the pillar bump while the pillar bump repair device is forming each of the plurality of strain-relieving notches.

Electrical contact alignment posts

An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.

Apparatus and methods for substantial planarization of solder bumps

Apparatus and methods for substantial planarization of solder bumps. In one embodiment, an apparatus includes a planarization member engageable with at least some of the plurality of outer surfaces to apply a planarization action on one or more of the outer surfaces to substantially planarize the plurality of outer surfaces, and a securing element to securely position the bumped device during engagement with the planarization member. Through application of "additive" and/or "subtractive" processes, the solder balls are substantially planarized. In alternate embodiments, the planarization member includes a cutting tool and the planarization action comprises a milling action; or the planarization member includes a heated platen and the planarization action comprises a thermo-mechanical deformation action; or the planarization member includes an abrasive surface and the planarization action comprises a grinding action; or the planarization member includes a chemical solution and the planarization ...

SELF-ALIGNING CONDUCTIVE BUMP STRUCTURE AND METHOD OF MAKING THE SAME

The disclosure relates to a conductive bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface and conductive bumps distributed over the major surface of the substrate. Each of a first subset of the conductive bumps comprise a regular body, and each of a second subset of the conductive bumps comprise a ring-shaped body.

SEMICONDUCTOR PACKAGE

Disclosed is a semiconductor package including a package substrate, a semiconductor chip mounted on the package substrate, a connection solder pattern between the package substrate and the semiconductor chip, and a dummy bump between the package substrate and the semiconductor chip and spaced apart from the connection solder pattern. The connection solder pattern includes a first intermetallic compound layer, a connection solder layer, and a second intermetallic compound layer. The dummy bump includes a dummy pillar and a dummy solder pattern. A thickness of the dummy solder pattern is less than a thickness of the connection solder pattern. A melting point of the dummy solder pattern is greater than that of the connection solder layer.

はんだバンプのセルフアライメントに利用するスタッドの作成

ELECTRONIC DEVICE AND METHOD OF MOUNTING

PROBLEM TO BE SOLVED: To facilitate positioning an electronic device and ensure reliable connections of bump electrodes by providing reinforcing bumps for maintaining electrical connections between the bump electrodes and wiring on a circuit board. SOLUTION: An electronic device 20 having bump electrodes 11 for connection to wiring on the circuit board is provided with reinforcement bumps 40 for maintaining the connections between the bump electrodes and the wiring on the board. For example, four reinforcement bumps 40 (reinforcement lands) are provided at four corners of the reverse side 21 of the electronic device in such a manner that they are outside a predetermined arrangement of a large number of bump electrodes 11. The reinforcement bumps 4 and bump electrodes 11 are both made of solder and spherical or semispherical. The diameter 11 of the reinforcement bumps is greater than the diameter 12 of the bump electrodes so that users can definitely discriminate them. COPYRIGHT: (C)1997 ...

Back electrode type electronic part and electronic assembly with the same mounted on printed circuit board

Mounting a ball grid array device on a printed circuit board

A method of mounting a ball grid array device on a substrate includes providing device electrodes 12 to be soldered 22 to substrate electrodes 3 on a PCB. At least one group of device electrodes 13 is connected to a reinforced enlarged substrate electrode 4. The connection between the enlarged electrode and the substrate material is reinforced, for example by filled anchoring through holes 5 or recesses.

Semiconductor device

MANUFACTORING PROCESS OF STUDS OF ELECTRIC CONNECTION Of a PLATE

A METHOD OF JOINING TWO ELECTRONIC COMPONENTS TOGETHER, FLIP CHIP TYPE

Integrated circuit packaging system with active surface heat removal and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.

Semiconductor assembly and semiconductor package including a solder channel

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Chip package with plank stack of semiconductor dies

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

Electrical Contact Alignment Posts

An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.

Sapphire substrate configured to form light emitting diode chip providing light in multi-directions, light emitting diode chip, and illumination device

A sapphire substrate configured to form a light emitting diode (LED) chip providing light in multi-directions, a LED chip and an illumination device are provided in the present invention. The sapphire substrate includes a growth surface and a second main surface opposite to each other. A thickness of the sapphire substrate is thicker than or equal to 200 micrometers. The LED chip includes the sapphire substrate and at least one LED structure. The LED structure is disposed on the growth surface and forms a first main surface where light emitted from with a part of the growth surface without the LED structures. At least a part of light beams emitted from the LED structure pass through the sapphire substrate and emerge from the second main surface. The illumination device includes at least one LED chip and a supporting base. The LED chip is disposed on the supporting base.

Shaped and oriented solder joints

The present description relates to the field of fabricating microelectronic assemblies, wherein a microelectronic device may be attached to a microelectronic substrate with a plurality of shaped and oriented solder joints. The shaped and oriented solder joints may be substantially oval, wherein the major axis of the substantially oval solder joints may be substantially oriented toward a neutral point or center of the microelectronic device. Embodiments of the shaped and oriented solder joint may reduce the potential of solder joint failure due to stresses, such as from thermal expansion stresses between the microelectronic device and the microelectronic substrate.

Multi-Chip Module with Multiple Interposers

A Multi-Chip Module is presented herein that comprises a package substrate, at least two integrated circuit devices, each of which is electrically coupled to the package substrate, and an interposer. Formed in the interposer are electrical connections which are predominantly horizontal interconnects. The first interposer is arranged to electrically couple the two integrated circuit devices to each other. Methods for manufacturing a Multi-Chip Module are also presented herein.

Bump Structure and Method of Forming Same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

Metal Bump and Method of Manufacturing Same

An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width.

Semiconductor devices having through electrodes, methods of manufacturing the same, and semiconductor packages including the same

A semiconductor device includes a semiconductor layer having a first surface and a second surface, a through electrode penetrating the semiconductor layer and having a protruding portion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed on the first surface of the semiconductor layer and electrically coupled to the through electrode, a passivation pattern including a first insulation pattern that surrounds a sidewall of the protruding portion of the through electrode and extends onto the second surface of the semiconductor layer and a second insulation pattern that covers the first insulation pattern and has an etch selectivity with respect to the first insulation pattern, and a back-side bump covering an end surface of the protruding portion of the through electrode and extending onto the passivation pattern.

SEMICONDUCTOR LIGHT EMITTING ELEMENT WITH DISPERSIVE OPTICAL UNIT AND ILLUMINATION DEVICE COMPRISING THE SAME

A semiconductor light emitting element includes a transparent substrate and a plurality of light emitting diode (LED) chips. The transparent substrate has a support surface and a second main surface disposed opposite to each other. At least some of the LED structures are disposed on the support surface and form a first main surface where light emitted from with a part of the support surface without the LED structures. Each of the LED structures includes a first electrode and a second electrode. Light emitted from at least one of the LED structures passes through the transparent substrate and emerges from the second main surface. An illumination device includes the semiconductor light emitting element and a supporting base. The semiconductor light emitting element is disposed on the supporting base, and an angle is formed between the semiconductor light emitting element and the supporting base. 1. A semiconductor light emitting element , comprising:a transparent substrate, having a support surface and a second main surface disposed opposite to each other;a light emitting diode (LED) structure disposed on the support surface, a first main surface, where light emitted from, being formed by the LED structure and at least a part of the support surface without the LED structure, and at least a part of the light emitted from the LED structure may pass through the transparent substrate and emerge from the second main surface; andan optical unit disposed on the first main surface, the optical unit comprising a covering side facing the transparent substrate, and a light dispersion side corresponding to the covering surface;wherein the optical unit further comprises at least one optical structure disposed on the light dispersion side to disperse light received from the covering side to different directions corresponding to wavelength of the light.2. The semiconductor light emitting element of claim 1 , further comprising:a wavelength conversion layer sandwiched by the optical ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate, a transistor, and a first harmonic termination circuit. The transistor is formed at the semiconductor substrate. The transistor amplifies an input signal supplied to an input end and outputs an amplified signal through an output end. The first harmonic termination circuit attenuates a harmonic component included in the amplified signal. The first harmonic termination circuit is formed at the semiconductor substrate such that one end of the first harmonic termination circuit is connected to the output end of the transistor and the other end of the first harmonic termination circuit is connected to a ground end of the transistor. 1. A semiconductor device comprising:a semiconductor substrate;a transistor that amplifies an input signal supplied to an input end and outputs an amplified signal through an output end, the transistor being on or in the semiconductor substrate, and the transistor being a multi-finger transistor having a plurality of unit transistors;a first harmonic termination circuit that is configured to attenuate a harmonic component of an amplified signal output from an output end of a first unit transistor, the first harmonic termination circuit being on the semiconductor substrate such that a first end of the first harmonic termination circuit is connected to the output end of the first unit transistor and a second end of the first harmonic termination circuit is connected to a ground end of the first unit transistor; anda second harmonic termination circuit configured to attenuate a harmonic component of an amplified signal output from an output end of a second unit transistor, the second harmonic termination circuit being on the semiconductor substrate such that a first end of the second harmonic termination circuit is connected to the output end of the second unit transistor and a second end of the second harmonic termination circuit is connected to a ground end of the second unit ...

FLOW GUIDING STRUCTURE OF CHIP

The present invention provides a flow guiding structure of chip, which comprises at least one flow guiding member disposed on a surface of a chip and adjacent to a plurality of connecting bumps disposed on the surface of the chip. When the chip is disposed on a board member, the at least one flow guiding member may guide the conductive medium on the surface of the chip to flow toward the connecting bumps and drive a plurality of conductive particles of the conductive medium to move toward the connecting bumps and thus increasing the number of the conductive particles on the surfaces of the connecting bumps. Alternatively, the flow guiding member may retard the flow of the conductive medium for avoiding the conductive particles from leaving the surfaces of the connecting bumps and thus preventing reduction of the number of the conductive particles on the surfaces of the connecting bumps. 1. A flow guiding structure of chip , comprising:a plurality of connecting bumps, disposed on a surface of a chip; andat least one flow guiding member, disposed on said surface of said chip, and adjacent to said connecting bumps.2. The flow guiding structure of chip of claim 1 , wherein a height of said at least one flow guiding member is smaller than or equal to a height of said connecting bumps.3. The flow guiding structure of chip of claim 1 , wherein at least one side of said at least one flow guiding member is adjacent to said connecting bumps; and said at least one side of said at least one flow guiding member is a sloped surface.4. The flow guiding structure of chip of claim 1 , wherein said at least one flow guiding member includes a plurality of flow guiding members; said flow guiding members include a plurality of flow guiding bumps; and said flow guiding bumps are adjacent to said connecting bumps.5. The flow guiding structure of chip of claim 4 , wherein a first side of said flow guiding bumps corresponds to a second side of said connecting bumps; and an area of said ...

SEMICONDUCTOR DEVICE

[Problem] To provide a semiconductor device with a wafer level package structure that allows for probing while reducing the area occupied by the pad electrodes. [Solution] In the present invention, the following are provided: a semiconductor chip (100) that has first and second pad electrodes (120, 120) disposed on the main surface thereof; insulating films (310, 330) that cover the main surface of the semiconductor chip (100); a rewiring layer (320) that is disposed between the insulating films (310, 330); and a plurality of external terminals (340) disposed on the top of the insulating film (330). The plane size of the first pad electrode (120) and the second pad electrode (120) differ from one another, and the first pad electrode (120) and the second pad electrode (120) are connected to any of the plurality of external terminals (340) via the rewiring layer (320). According to the present invention, because the pad electrodes (120, 120) of different sizes are intermixed, probing can be easily performed while reducing the area occupied by the pad electrodes. 1. A semiconductor device , comprising:a semiconductor chip;a plurality of first pad electrodes formed running in a first direction through a center portion of a principal surface of the semiconductor chip; anda plurality of second pad electrodes formed on the principal surface of the semiconductor chip between a pad column formed by the first pad electrodes and a side of the semiconductor chip,wherein the first pad electrodes and the second pad electrodes have a different planar size.2. The semiconductor device as claimed in claim 1 , wherein the first pad electrodes supply a first power source voltage claim 1 , and the second pad electrodes supply a second power source voltage.3. The semiconductor device as claimed in claim 2 , wherein the first pad electrodes and the second pad electrodes both supply a same power source voltage.4. The semiconductor device as claimed in claim 1 , further comprising an ...

3D Semiconductor Package Interposer with Die Cavity

Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects. 1. A device , comprising:a substrate having a top surface;an interposer over the top surface of the substrate, the interposer being connected to the substrate by first interconnects;a first integrated circuit die connected to a first side of the interposer by first connectors;a second integrated circuit die connected to a second side of the interposer opposite the first side by second connectors, the second integrated circuit die having a smaller footprint than the interposer; anda fan-out structure disposed over a top surface of the interposer and extending beyond outermost edges of the interposer, wherein the fan-out structure is electrically connected to second interconnects, the second interconnects in contact with the top surface of the substrate.2. The device of claim 1 , further comprising third connectors connecting the fan-out structure to the second integrated circuit die.3. The device of claim 1 , further comprising a cavity in the top surface of the substrate claim 1 , wherein the first integrated circuit die extends into the cavity.4. The device of claim 1 , further comprising:a first molding compound on sidewalls of the interposer, the first interconnects, and the second interconnects; anda second molding compound on the first molding compound, the fan-out structure, and the second integrated circuit die.5. The device of claim 1 , ...

BUMP STRUCTURE HAVING A SIDE RECESS AND SEMICONDUCTOR STRUCTURE INCLUDING THE SAME

The present disclosure relates to an integrated chip structure having a first copper pillar disposed over a metal pad of an interposer substrate. The first copper pillar has a sidewall defining a recess. A nickel layer is disposed over the first copper pillar and a solder layer is disposed over the first copper pillar and the nickel layer. The solder layer continuously extends from directly over the first copper pillar to within the recess. A second copper layer is disposed between the solder layer and a second substrate. 1. An integrated chip structure , comprising:a first copper pillar disposed over a metal pad of an interposer substrate, wherein the first copper pillar has a sidewall defining a recess;a nickel layer disposed over the first copper pillar;a solder layer disposed over the first copper pillar and the nickel layer, wherein the solder layer continuously extends from directly over the first copper pillar to within the recess; anda second copper layer disposed between the solder layer and a second substrate.2. The integrated chip structure of claim 1 , wherein the first copper pillar has a width that is between about 10 microns and about 200 microns.3. The integrated chip structure of claim 1 , wherein the first copper pillar has a width that is between about 25 microns and about 50 microns.4. The integrated chip structure of claim 1 , wherein the sidewall of the first copper pillar defining the recess is a curved surface.5. The integrated chip structure of claim 1 , wherein the recess has a depth of between about 1 micron and about 15 microns.6. The integrated chip structure of claim 1 ,wherein the recess has a depth; andwherein a ratio of the depth to an overall width of the first copper pillar is in a range from about 0.05 to about 0.2.7. The integrated chip structure of claim 1 , wherein the solder layer has a height of between about 10 microns and about 50 microns.8. The integrated chip structure of claim 1 , wherein the first copper pillar is ...

Semiconductor device assembly with through-package interconnect and associated systems, devices, and methods

Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS

A semiconductor device includes a substrate and a semiconductor element mounted on the top surface of the substrate. On the top surface of the substrate, one or more pads are disposed outside the mounted semiconductor element when seen in a plan view. Then, a protrusion is disposed on each of the pads. A heat sink is disposed above the semiconductor element and the protrusions, and then bonded to the substrate by an adhesive provided between the heat sink and the substrate. The adhesive is provided in such a manner as to be in contact with the protrusions on the substrate. 1. A semiconductor device comprising:a substrate;a semiconductor element mounted on a first surface of the substrate;a first pad disposed on the first surface and outside of the semiconductor element in a plan view;a first protrusion disposed on the first pad;a heat sink disposed above the semiconductor element and the first protrusion; anda first adhesive disposed between the first surface and the heat sink to bond the first protrusion and the heat sink.2. The semiconductor device according to claim 1 , wherein:the first pad, the first protrusion, and the first adhesive are electrically conductive respectively, andthe first pad is electrically connected to the heat sink through the first protrusion and the first adhesive.3. The semiconductor device according to claim 1 , wherein:the heat sink includes a flat surface opposing the first surface.4. The semiconductor device according to claim 1 , wherein:the first protrusion is disposed away from the heat sink.5. The semiconductor device according to claim 1 , wherein:the first protrusion is contact with the heat sink.6. The semiconductor device according to claim 1 , further comprising a bump disposed between the semiconductor element and the first surface claim 1 ,wherein size of the first protrusion is same as size of the bump.7. The semiconductor device according to claim 1 , further comprising a second adhesive that includes a first part ...

Method and System for Packing Optimization of Semiconductor Devices

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently. 1. A substrate comprising interconnects , wherein the interconnects comprise edge interconnects along edges of the substrate , and at least one of the edges is a rounded non-linear edge.2. The substrate of claim 1 , wherein the interconnects comprise a plurality of non-circular interconnects with a major axis and a minor axis.3. The substrate of claim 2 , wherein the major axis of at least one of the plurality of non-circular interconnects is substantially perpendicular to: a radial axis of the substrate claim 2 , or to a line that is parallel to a radial axis of the substrate.4. The substrate of claim 1 , wherein the edge interconnects are configured to form interconnects that hang over a corresponding edge when solder of the substrate is reflowed.5. The substrate of claim 1 , wherein a perimeter of the substrate tracks a contour of individual ones of the edge interconnects.6. The substrate of claim 1 , comprising:a first row of horizontally aligned first interconnects; anda second row of second interconnects that are immediately below the first row of first interconnects, the first row is parallel to the second row,', 'the first interconnects have a first pitch,', 'the second interconnects have the first pitch,', 'a first line through a center of each of the first interconnects is parallel to a second line through a center of each of the second interconnects, and', 'the first pitch is different than a vertical distance from the first line to the second line., 'wherein7. A substrate comprising interconnects claim 1 , wherein:a plurality of the interconnects are non-circular interconnects, and each non-circular interconnect has a major axis and a minor axis,a first substrate axis extends from a center of the substrate to a perimeter of the substrate; anda first row of the ...

Electronic device

An electronic device includes a surface-mounted component and a mounting component on which the surface-mounted component is mounted, the surface-mounted component includes a first bump and a second bump, a cross-sectional area of which in an in-plane direction of a surface facing the mounting component is larger than that of the first bump, on the surface facing the mounting component, the mounting component includes a first pad that is soldered to the first bump and a second pad soldered to the second bump on the surface facing the surface-mounted component, and a ratio of an area of the second pad to the cross-sectional area of the second bump is larger than a ratio of an area of the first pad to the cross-sectional area of the first bump.

Fabricating pillar solder bump

A substrate bonding method is able to reliably bond substrates while avoiding a reduction in yield made worse by finer pitches. The substrate bonding method can include: forming an adhesive resin layer on a surface of a first substrate on which a pad has been formed; forming an opening on the adhesive resin layer above the pad; filling the opening with molten solder to form a pillar-shaped solder bump; and applying heat and pressure to the first substrate and a second substrate while a terminal formed on the second substrate is aligned with the solder bump.

Bump structure having a side recess and semiconductor structure including the same

In some embodiments, the present disclosure relates to a method of integrated chip bonding. The method is performed by forming a metal layer on a substrate, and forming a solder layer on the metal layer. The solder layer is reflowed. The metal layer and the solder layer have sidewalls defining a recess that is at least partially filled by the solder layer during reflowing of the solder layer.

Solder fatigue arrest for wafer level package

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint coupled with and standing on the first pad, a joint encapsulating the post and bonding the first pad with the second pad, a first entire contact interface between the first pad and the joint, a second entire contact interface between the first pad and the post, and a third entire contact interface between the joint and the second pad. The first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces. A distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface. The second entire contact interface is a continuous surface. 1. A semiconductor device , comprising:a silicon substrate;a carrier;a first pad on the silicon substrate;a second pad on the carrier;a post on a surface of the first pad, wherein the post consists of a metal or a metal alloy;a joint disposed between the silicon substrate and the carrier, contacted with the first pad and the second pad, and encapsulating the post;a first entire contact interface between the first pad and the joint;a second entire contact interface between the first pad and the post; anda third entire contact interface between the joint and the second pad,wherein an outer surface of the joint is concaved and curved towards the post, and a height of the post is greater than or equal to ⅓ of a height of the joint between the first pad and the second pad, the first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces, wherein a distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface, ...

BUMP STRUCTURE HAVING A SIDE RECESS AND SEMICONDUCTOR STRUCTURE INCLUDING THE SAME

In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure may have a first conductive structure and a second conductive structure arranged over a first substrate. A bump structure is arranged between the first conductive structure and a second substrate. A solder layer is configured to electrically couple the first conductive structure and the bump structure. The bump structure has a recess that is configured to reduce a protrusion of the solder layer in a direction extending from the first conductive structure to the second conductive structure. 1. A semiconductor structure , comprising:a first conductive structure and a second conductive structure arranged over a first substrate;a bump structure arranged between the first conductive structure and a second substrate; anda solder layer configured to electrically couple the first conductive structure and the bump structure, wherein the bump structure comprises a recess configured to reduce a protrusion of the solder layer in a direction extending from the first conductive structure to the second conductive structure.2. The semiconductor structure of claim 1 , wherein the recess straddles a line that extends through a center of the bump structure along the direction extending from the first conductive structure to the second conductive structure.3. The semiconductor structure of claim 1 ,wherein the bump structure has a recessed side facing the second conductive structure, which comprises the recess; andwherein the bump structure has a non-recessed side facing away from the second conductive structure, which does not have a recess.4. The semiconductor structure of claim 2 , further comprising:an under-bump metallurgy (UBM) layer arranged between the second substrate and the bump structure, wherein an outer sidewall of the UBM layer is linearly aligned with the non-recessed side of the bump structure.5. The semiconductor structure of claim 1 , wherein the recess has a ...

INTERCONNECT FOR ELECTRONIC DEVICE

A semiconductor die includes a substrate and an integrated circuit provided on the substrate and having contacts. An electrically conductive layer is provided on the integrated circuit and defines electrically conductive elements electrically connected to the contacts. Electrically conductive interconnects coupled with respective electrically conductive elements. The electrically conductive interconnects have at least one of different sizes or shapes from one another. 1. An electronic package comprising:a substrate including conductive elements electrically connected to an integrated circuit of the substrate, a portion of at least one of the conductive element in between fingers of another conductive element;at least two conductive interconnects, each electrically coupled to the integrated circuit via the conductive elements, wherein the at least two conductive interconnects include different size and shape from one another, and wherein each of the at least two conductive interconnects include a first portion including tin and a second portion of copper, the second portion attached to the conductive elements; anda portion of a leadframe attached to the first portion of each of the at least two conductive interconnects.2. The electronic package recited in claim 1 , wherein one of the at least two conductive interconnects has a thickness extending away from the conductive elements greater than a width extending perpendicular to the thickness.3. The electronic package recited in claim 1 , wherein at least one of the conductive interconnects is polygonal in shape.4. The electronic package recited in claim 1 , wherein at least one of the conductive interconnects is rectangular in shape.5. The electronic package recited in claim 1 , wherein at least one of the conductive interconnects has an aspect ratio greater than 1:1.6. The electronic package recited in claim 1 , further comprising an insulating layer provided over the substrate and in between the at least two ...

CHIP PACKAGE STRUCTURE

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first bump and a first dummy bump between the chip and the substrate. The first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump. 1. A chip package structure , comprising:a substrate;a chip over the substrate; anda first bump and a first dummy bump between the chip and the substrate, wherein the first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump.2. The chip package structure as claimed in claim 1 , wherein the first dummy bump has a first strip portion and a second strip portion claim 1 , and the first strip portion is not parallel to the second strip portion.3. The chip package structure as claimed in claim 2 , wherein the chip has a first edge and a second edge claim 2 , the first edge and the second edge meet at the corner of the chip claim 2 , and the first strip portion is substantially parallel to the first edge.4. The chip package structure as claimed in claim 3 , wherein the second strip portion is substantially parallel to the second edge.5. The chip package structure as claimed in claim 1 , further comprising:an underfill layer between the chip and the substrate and between the first dummy bump and the substrate.6. The chip package structure as claimed in claim 1 , further comprising:a second bump between the first bump and the substrate; anda second dummy bump between the chip and the substrate, wherein the second dummy bump is connected to the ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a substrate, a package, first conductors and second conductors. The substrate includes a first surface and a second surface opposite to the first surface. The package is disposed over the substrate. The first conductors are disposed over the substrate. The second conductors are disposed over the substrate, wherein the first conductors and the second conductors are substantially at a same tier, and a width of the second conductor is larger than a width of the first conductor. 1. A semiconductor device , comprising:a substrate including a first surface and a second surface opposite to the first surface;a package over the substrate;a plurality of first conductors over the substrate;a plurality of second conductors over the substrate, wherein the plurality of first conductors and the plurality of the second conductors are substantially at a same tier, and a width of a second conductor of the plurality of second conductors is larger than a width of a first conductor of the plurality of first conductors;a plurality of first bonding pads on the substrate and configured to receive and electrically connect to the plurality of first conductors, respectively;a plurality of second bonding pads on the substrate and configured to receive and electrically connect to the plurality of second conductors, respectively; anda passivation layer over the substrate, wherein the passivation layer includes a plurality of first recesses exposing the plurality of first bonding pads respectively, and a plurality of second recesses exposing the plurality of second bonding pads respectively, and a width of the first recess is wider than a width of the second recess, wherein the first conductor is apart from an edge of the respective first recess, and the second conductor is in contact with an edge of the respective second recess.2. The semiconductor device of claim 1 , wherein a volume of a second conductor of the plurality of second conductors is substantially ...

CHIP MOUNTING STRUCTURE

Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate. 1. A method for changing a shape of a substrate to reduce stress exerted on an interlayer insulating layer of a chip , the method comprising:providing the substrate;mounting the chip on the substrate such that a center of the chip corresponds to a center of the substrate and such that sides of the chip are parallel to sides of the substrate;measuring a distance B between a side of the chip and a nearest side of the substrate; andcutting off square portions of the substrate from each corner of the substrate such that a distance between a corner of the chip and a nearest corner of the substrate is less than the distance B.2. The method of claim 1 , wherein each square portion has sides of a length c.4. A method for mounting a chip on a substrate claim 1 , the method comprising:providing a chip having an interlayer insulating layer, the interlayer insulating layer having a low dielectric constant;mounting the chip to a substrate such that there is a distance B between a side of the chip and a nearest side of the substrate;connecting the chip to the substrate using flip-chip bumps; andcutting off right-angle isosceles triangle portions of the substrate from each ...

PACKAGE SUBSTRATES

A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy region, the circuit region including unit regions arranged in a matrix shape, and solders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern. 1. A package substrate , comprising:a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy region, the circuit region including unit regions arranged in a matrix shape; andsolders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern.2. The package substrate of claim 1 , wherein the substrate further comprises:a core portion including interconnection layers and insulating layers alternatingly stacked with each other;an upper circuit pattern provided on a top surface of the core portion; andthe lower circuit pattern provided on a bottom surface of the core portion.3. The package substrate of claim 2 , further comprising:a solder resist selectively covering the top and bottom surfaces of the core portion to expose at least a portion of the lower circuit pattern.4. The package substrate of claim 1 , wherein the solders protrude from a bottom surface of the substrate by a height of about 1 μm to about 5 μm.5. The package substrate of claim 1 , wherein the solders are along an edge of the substrate to form a ring-shaped arrangement.6. The package substrate of claim 5 , wherein the solders comprise:a set of first solders along the edge of the substrate; anda set of second solders around and outside the set of first solders,wherein the set of first solders are different from the set of second solders, in terms of their sizes.7. The package substrate of claim 1 , wherein the solders comprise a set of first solders on two opposite regions relative to the circuit region in a first direction.8. The ...

BUMP STRUCTURE HAVING A SINGLE SIDE RECESS

A bump structure includes a first end, and a second end opposite the first end. The bump structure further includes a first side connected between the first end and the second end. The bump structure further includes a second side opposite the first side. The second side is connected between the first end and the second end, and the second side comprises a recess for a reflowed solder material to fill. 1. A bump structure comprising:a first end;a second end opposite the first end;a first side connected between the first end and the second end; anda second side opposite the first side, wherein the second side is connected between the first end and the second end, and the second side comprises a recess for a reflowed solder material to fill.2. The bump structure of claim 1 , wherein the first side is a non-recessed side.3. The bump structure of claim 1 , wherein a ratio of a depth of the recess to an overall width of the bump structure ranges from about 0.05 to about 0.2.4. The bump structure of claim 1 , wherein the recess comprises a length adjacent to an outer edge of the bump structure claim 1 , and a ratio of the length to an overall length of the bump structure ranges from about 0.5 to about 0.3.5. The bump structure of claim 1 , wherein the recess comprises a length closest to the first side claim 1 , and a ratio of the length to an overall length of the bump structure is less than or equal to about 0.3.6. The bump structure of claim 1 , wherein a center of the recess is aligned with a center of the bump structure.7. The bump structure of claim 1 , wherein a center of the recess is offset by a distance from a center of the bump structure.8. The bump structure of claim 1 , wherein a ratio between the distance and an overall length of the bump structure is less than or equal to about 0.15.9. The bump structure of claim 1 , wherein the recess is curved or polygonal.10. A semiconductor structure comprising: a first end;', 'a second end opposite the first end;', 'a ...

Electrochemical additive manufacturing of interconnection features

A system and method of using electrochemical additive manufacturing to add interconnection features, such as wafer bumps or pillars, or similar structures like heatsinks, to a plate such as a silicon wafer. The plate may be coupled to a cathode, and material for the features may be deposited onto the plate by transmitting current from an anode array through an electrolyte to the cathode. Position actuators and sensors may control the position and orientation of the plate and the anode array to place features in precise positions. Use of electrochemical additive manufacturing may enable construction of features that cannot be created using current photoresist-based methods. For example, pillars may be taller and more closely spaced, with heights of 200 μm or more, diameters of 10 μm or below, and inter-pillar spacing below 20 μm. Features may also extend horizontally instead of only vertically, enabling routing of interconnections to desired locations.

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

A package structure is provided. The package structure includes a dielectric layer on a die, a RDL structure and a conductive terminal. The RDL structure comprises a redistribution layer in and on the dielectric layer. The redistribution layer comprises a via and a conductive plate. The via is located in and penetrating through the dielectric layer to be connected to the die. The conductive plate is on the via and the dielectric layer, and is connected to the die through the via. The conductive terminal is electrically connected to the die through the RDL structure. The via is ring-shaped. 1. A package structure , comprising:a die;a dielectric layer on the die; a via located in and penetrating through the dielectric layer to be connected to the die, wherein the via is ring-shaped; and', 'a conductive plate on the via and the dielectric layer, and is connected to the die through the via; and, 'an RDL structure comprising a redistribution layer in and on the dielectric layer, wherein the redistribution layer comprisesa conductive terminal, electrically connected to the die through the RDL structure,wherein the dielectric layer comprises a first portion enclosed by an inner sidewall of the via and in physical contact with the die.2. The package structure of claim 1 , wherein the dielectric layer further comprises a second portion outside an outer sidewall of the via claim 1 , wherein the first portion and the second portion of the dielectric layer are separated from each other by the via therebetween.3. The package structure of claim 1 , wherein the via and the conductive plate are coaxial.4. The package structure of claim 3 , wherein the RDL comprises multilayers of the vias and conductive plates stacked alternately claim 3 , and diameters of the conductive plates are increased progressively from bottom to top claim 3 , the vias are staggered with each other or partially overlapped with each other.5. The package structure of claim 1 , wherein the via has a circular ...

CHIP PACKAGES, CHIP ARRANGEMENTS, A CIRCUIT BOARD, AND METHODS FOR MANUFACTURING CHIP PACKAGES

A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material. 1. A chip arrangement comprising: a cavity formed in the circuit board;', 'and one or more circuit board contact regions arranged proximate to the cavity;, 'a circuit board comprisinga chip package arranged within the cavity,wherein at least one circuit board contact region is electrically connected to the one or more electrically conductive contact regions formed over a top side of the chip package and in electrical connection with a chip top side; andwherein at least one further circuit board contact region is electrically connected to an electrically conductive contact region formed over a bottom side of the chip package and in electrical connection with a chip bottom side.2. The chip arrangement according to claim 1 , wherein the chip package further comprises:a chip disposed over and electrically connected to a chip carrier top side;an electrically insulating material disposed over and at least partially surrounding the chip, wherein the one or more electrically conductive contact regions over the chip carrier top side comprises two or more electrically conductive contact regions formed through the electrically insulating material; anda further electrically insulating material disposed under a chip carrier bottom side wherein an electrically conductive contact region over the chip carrier bottom side is formed through the electrically insulating material. ...

Interconnect structure for a microelectronic device

A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.

Integrated Circuit Packages and Methods of Forming Same

Integrated circuit packages and methods of forming the same are disclosed. A first die is mounted on a first side of a workpiece, the workpiece including a second die. The workpiece is mounted to a front side of a package substrate, where the first die is at least partially disposed in a through hole in the package substrate. A heat dissipation feature may be attached on a second side of the workpiece. An encapsulant may be formed on the front side of the package substrate around the workpiece. 1. A method comprising:bonding a die stack to a workpiece, the die stack comprising one or more integrated circuit dies;mounting the workpiece on a first side of a package substrate, the package substrate comprising a through hole, wherein the die stack is at least partially disposed in the through hole of the package substrate;attaching a heat dissipation feature to the workpiece, the workpiece being interposed between the heat dissipation feature and the die stack, wherein the heat dissipation feature is completely separated from the package substrate; andforming a first encapsulant on the first side of the package substrate, wherein the first encapsulant extends along sidewalls of the workpiece.2. The method of claim 1 , wherein the workpiece is an integrated circuit die claim 1 , the first encapsulant extending along sidewalls of the integrated circuit die.3. The method of claim 1 , wherein the workpiece comprises an integrated circuit die encapsulated by a second encapsulant claim 1 , the second encapsulant being interposed between the integrated circuit die and the first encapsulant.4. The method of claim 1 , wherein a thermal interface material is interposed between the workpiece and the heat dissipation feature.5. The method of claim 1 , wherein a portion of the first encapsulant is interposed between the workpiece and the die stack.6. The method of claim 1 , wherein the first encapsulant extends along sidewalls of the heat dissipation feature.7. The method of claim 1 ...

Semiconductor packages

A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.

Semiconductor package, method for forming semiconductor package, and method for forming semiconductor assembly

A semiconductor package includes a first package component include a first side, a second side opposite to the first side, and a plurality of recessed corners over the first side. The semiconductor package further includes a plurality of first stress buffer structures disposed at the recessed corners, and each of the first stress buffer structures has a curved surface. The semiconductor package further includes a second package component connected to the first package component and a plurality of connectors disposed between the first package component and the second package component. The connectors are electrically coupled the first package component and the second package component. The semiconductor package further includes an underfill material between the first package component and the second package component, and at least a portion of the curved surface of the first stress buffer structures is in contact with and embedded in the underfill material.

WAFER LEVEL PACKAGING OF LIGHT EMITTING DIODES (LEDS)

An LED wafer includes LED dies on an LED substrate. The LED wafer and a carrier wafer are joined. The LED wafer that is joined to the carrier wafer is shaped. Wavelength conversion material is applied to the LED wafer that is shaped. Singulation is performed to provide LED dies that are joined to a carrier die. The singulated devices may be mounted in an LED fixture to provide high light output per unit area. 1. A lighting device comprising:a crystalline substrate comprising an inner face, an outer face opposing the inner face, and a thickness;an array of LEDs supported by the crystalline substrate proximate to the inner face, wherein the array of LEDs comprises a plurality of anode contacts and a plurality of cathode contacts in conductive electrical communication with the array of LEDs, and the array of LEDs is arranged to transmit LED emissions through the crystalline substrate to exit the outer face;a plurality of recesses arranged between LEDs of the plurality of LEDs, and extending from the outer face in a direction toward the inner face; anda wavelength conversion material arranged on or over the outer face of the crystalline substrate;wherein each recess of the plurality of recesses is partially filled with the wavelength conversion material, and is partially not filled with the wavelength conversion material.2. The lighting device of claim 1 , wherein the crystalline substrate is continuous between different LEDs of the array of LEDs.3. The lighting device of claim 2 , wherein each recess of the plurality of recesses extends through less than an entirety of the thickness of the crystalline substrate.4. The lighting device of claim 1 , wherein the crystalline substrate comprises one of silicon carbide or sapphire.5. The lighting device of claim 1 , wherein the outer face of the crystalline substrate comprises textural features.6. The lighting device of claim 1 , wherein the crystalline substrate comprises a crystalline growth substrate on which epitaxial ...

Manufacturing method of wafer level chip scale package structure

A manufacturing method of wafer level chip scale package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided. An active surface of one of the semiconductor devices has an active an active region and an outer region. A first electrode and a second electrode are arranged on the active region, and the outer region has a cutting portion and a channel portion. Next, a patterned protecting layer having a plurality of openings is formed on the active surface to respectively expose the first and second electrodes and channel portion. Subsequently, a wafer back thinning process is performed and then a back electrode layer is deposited. Subsequently, the channel portion is etched to form a trench exposing the back electrode layer, and a conductive structure connected to the back electrode layer is formed through the trench. Thereafter, the wafer is cut along the cutting portion.

Eutectic Electrode Structure of Flip-chip LED Chip and Flip-chip LED Chip

A light emitting diode includes: a light emitting structure including a first semiconductor layer, a light emitting layer arranged on at least part of the first semiconductor layer, a second semiconductor layer arranged on the light emitting layer; a first metal layer arranged on at least part of the first semiconductor layer and in contact with the first semiconductor layer; an insulating layer covered a surface of the light emitting structure; and an electrode layer arranged on the insulating layer and having at least one region that is not overlapped with the first metal layer or the second metal layer in a vertical direction. 1. A light emitting diode , comprising:a light emitting structure including a first semiconductor layer, a light emitting layer arranged on at least part of the first semiconductor layer, and a second semiconductor layer arranged on the light emitting layer;a first metal layer arranged on at least part of the first semiconductor layer and contact with the first semiconductor layer;a second metal layer arranged over at least of the second semiconductor layer and electrical contact the second semiconductor layer; andan electrode layer arranged over the second semiconductor layer, and has a bonding region is available for bonding with a package substrate,wherein the bonding region includes a first bonding region electrically connected to the first semiconductor layer and a second bonding region electrically connected to the second semiconductor layer; andthe first metal layer is not overlapped with first bonding region or the second bonding region in a vertical direction.2. The light emitting diode of claim 1 , further comprising a transparent conducting layer arranged between the second semiconductor layer and the second metal layer.3. The light emitting diode of claim 1 , further comprising an insulating layer arranged between the second metal layer and the electrode layer.4. The light emitting diode of claim 1 , wherein the second metal ...

SEMICONDUCTOR DEVICE

A semiconductor chip is mounted on a mounting substrate. The semiconductor chip includes plural first bumps on a surface facing the mounting substrate. The plural first bumps each have a shape elongated in a first direction in plan view and are arranged in a second direction perpendicular to the first direction. The mounting substrate includes, on a surface on which the semiconductor chip is mounted, at least one first land connected to the plural first bumps. At least two first bumps of the plural first bumps are connected to each first land. The difference between the dimension of the first land in the second direction and the distance between the outer edges of two first bumps at respective ends of the arranged first bumps connected to the first land is 20 μm or less. 1. A semiconductor device comprising:a mounting substrate; anda semiconductor chip mounted on the mounting substrate,whereinthe semiconductor chip includes a plurality of first bumps on a surface facing the mounting substrate, the plurality of first bumps each having a shape elongated in a first direction in plan view and being arranged in a second direction perpendicular to the first direction,the mounting substrate includes, on a surface on which the semiconductor chip is mounted, at least one first land connected to the plurality of first bumps, at least two first bumps of the plurality of first bumps being connected to each first land, anda difference between a dimension of the first land in the second direction and a distance between outer edges of two first bumps at respective ends of the arranged first bumps connected to the first land is 20 μm or less.2. The semiconductor device according to claim 1 , wherein the dimension of the first land in the second direction is identical to the distance between outer edges of two first bumps at respective ends of the arranged first bumps connected to the first land.3. The semiconductor device according to claim 1 , wherein the at least one first land ...

Forming Large Chips Through Stitching

A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE SAME

A semiconductor device includes a semiconductor die having a first surface and a second surface opposite to the first surface, a plurality of first real conductive pillars in a first region on the first surface, and a plurality of supporters in a second region adjacent to the first region. An area density of the plurality of supporters in the second region is in a range of from about 50% to about 100% to an area density of the plurality of first real conductive pillars in the first region. A method for manufacturing a semiconductor package including the semiconductor device is also disclosed in the present disclosure. 1. A semiconductor device , comprising:a semiconductor die having a first surface and a second surface opposite to the first surface;a plurality of first real conductive pillars in a first region on the first surface; anda plurality of supporters in a second region adjacent to the first region,wherein an area density of the plurality of supporters in the second region is in a range of from about 50% to about 100% to an area density of the plurality of first real conductive pillars in the first region.2. The semiconductor device of claim 1 , wherein the plurality of supporters comprise a dummy pillar.3. The semiconductor device of claim 1 , wherein a volume density of the plurality of supporters in the second region is in a range of from about 50% to about 100% to a volume density of the plurality of first real conductive pillars in the first region.4. The semiconductor device of claim 1 , wherein a shape of each of the supporters in the second region is different from a shape of each of the plurality of first real conductive pillar in the first region from a top view perspective.5. The semiconductor device of claim 1 , wherein a height of the each of the plurality of supporters in the second region is lower from a height of each of the plurality of first real conductive pillar in the first region.6. The semiconductor device of claim 1 , wherein a ...

SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR FORMING THE SAME

A semiconductor device package ready for assembly includes: a semiconductor substrate; a first under-bump-metallurgy (UBM) layer disposed on the semiconductor substrate; a first conductive pillar disposed on the first UBM layer; and a second conductive pillar disposed on the first conductive pillar. A material of the first conductive pillar is different from a material of the second conductive pillar, and the material of the second conductive pillar includes an antioxidant. 1. A semiconductor device package ready for assembly , comprising:a semiconductor substrate;a first under-bump-metallurgy (UBM) layer disposed on the semiconductor substrate;a first conductive pillar disposed on the first UBM layer; anda second conductive pillar disposed on the first conductive pillar;wherein a material of the first conductive pillar is different from a material of the second conductive pillar, and the material of the second conductive pillar includes an antioxidant, and the first conductive pillar has a width, the second conductive pillar has a height, and the height is greater than the width by at least 0.65 times.2. The semiconductor device package of claim 1 , wherein the first conductive pillar is a copper pillar claim 1 , and the second conductive pillar is a solder pillar including the antioxidant.3. The semiconductor device package of claim 2 , wherein a stannic oxide layer is formed on a surface of the second conductive pillar claim 2 , and a thickness of the stannic oxide layer is less than 10 nm.4. (canceled)5. The semiconductor device package of claim 1 , wherein the first conductive pillar has a first circumference claim 1 , the second conductive pillar has a second circumference claim 1 , and the second circumference is substantially equal to the first circumference.6. The semiconductor device package of claim 5 , wherein a lateral periphery of the first conductive pillar is aligned with a lateral periphery of the second conductive pillar.7. The semiconductor device ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor chip is mounted on a mounting substrate. The semiconductor chip includes plural first bumps on a surface facing the mounting substrate. The plural first bumps each have a shape elongated in a first direction in plan view and are arranged in a second direction perpendicular to the first direction. The mounting substrate includes, on a surface on which the semiconductor chip is mounted, at least one first land connected to the plural first bumps. At least two first bumps of the plural first bumps are connected to each first land. The difference between the dimension of the first land in the second direction and the distance between the outer edges of two first bumps at respective ends of the arranged first bumps connected to the first land is 20 μm or less. 1. A semiconductor device comprising:a mounting substrate; anda semiconductor chip mounted on the mounting substrate,whereinthe semiconductor chip includes a plurality of first bumps and a plurality of second bumps on a surface facing the mounting substrate, the plurality of first bumps each having a shape elongated in a first direction in plan view and being arranged in a second direction perpendicular to the first direction,the mounting substrate includes, on a surface on which the semiconductor chip is mounted, at least one first land connected to the plurality of first bumps and a plurality of second lands connected to the plurality of second bumps, at least two first bumps of the plurality of first bumps being connected to each first land and each second land being connected to at least one bump of the plurality of second bumps,a difference between a dimension of the first land in the second direction and a distance between outer edges of two first bumps at respective ends of the arranged first bumps connected to the first land is 20 μm or less.2. The semiconductor device according to claim 1 , wherein the plurality of second bumps each have a shape elongated in the second direction in plan ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate, a transistor, and a first harmonic termination circuit. The transistor is formed at the semiconductor substrate. The transistor amplifies an input signal supplied to an input end and outputs an amplified signal through an output end. The first harmonic termination circuit attenuates a harmonic component included in the amplified signal. The first harmonic termination circuit is formed at the semiconductor substrate such that one end of the first harmonic termination circuit is connected to the output end of the transistor and the other end of the first harmonic termination circuit is connected to a ground end of the transistor. 1. A semiconductor device comprising:a semiconductor substrate;a transistor that amplifies an input signal supplied to an input end and outputs an amplified signal through an output end, the transistor being formed at the semiconductor substrate; anda first harmonic termination circuit configured to attenuate a harmonic component of the amplified signal, the first harmonic termination circuit being formed on the semiconductor substrate such that a first end of the first harmonic termination circuit is connected to the output end of the transistor and a second end of the first harmonic termination circuit is connected to a ground end of the transistor.2. The semiconductor device according to claim 1 ,wherein the transistor is a multi-finger transistor having a plurality of unit transistors, the first harmonic termination circuit being configured to attenuate a harmonic component of an amplified signal output from an output end of a first unit transistor, and being connected between the output end and a ground end of the first unit transistor,wherein the semiconductor device further comprises a second harmonic termination circuit configured to attenuate a harmonic component of an amplified signal output from an output end of a second unit transistor, the second harmonic termination ...

Mechanisms for Forming Hybrid Bonding Structures with Elongated Bumps

Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1. 1. A package structure , comprising:a first substrate;a second substrate;a pillar bump bonded to the first substrate and the second substrate, the pillar bump being electrically coupled to the first substrate and the second substrate, wherein the pillar bump comprises a pillar and a bonding layer, the pillar is a non-solder material having a higher reflow temperature than the bonding layer, the bonding layer is between the pillar and the second substrate, and the pillar includes a linear sidewall profile; andan elongated solder bump bonded to the first substrate and the second substrate, wherein a height of the elongated solder bump is substantially equal to a height of the pillar bump, wherein the elongated solder bump and the bonding layer are formed of a solder.2. The package structure of claim 1 , wherein the first substrate comprises a semiconductor die.3. The package structure of claim 2 , wherein the bonding layer is interposed between the pillar and the second substrate.4. The package structure of claim 1 , wherein the elongated solder bump has convex sidewalls.5. The package structure of claim 1 , wherein the elongated solder bump has a solder portion having a first width at a first horizontal plane passing through an upper end of a sidewall surface of the elongated ...

THIN-FILM CAPACITOR STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE THIN-FILM CAPACITOR STRUCTURE

A thin-film capacitor structure () is joined to an electrode pad surface (S) of an area array integrated circuit () having a plurality of electrode pads (G, P, S) arranged in an area array on the electrode pad surface (S). The thin-film capacitor structure () includes a thin-film capacitor () including a first sheet electrode (), a second sheet electrode (), and a thin-film dielectric layer () formed between the first sheet electrode () and the second sheet electrode (), a first insulating film (), a second insulating film (), and a plurality of through holes (P, G, S). The plurality of through holes (P, G, S) are bored from the first insulating film () to the second insulating film () through the thin-film capacitor () and formed in positions corresponding to the plurality of electrode pads (G, P, S). 1. A thin-film capacitor structure that is joined to an electrode pad surface of an area array integrated circuit having a plurality of electrode pads , arranged in an area array in the electrode pad surface , that include power supply pads , ground pads , and signal pads ,the thin-film capacitor structure comprising:a thin-film capacitor including a first sheet electrode, a second sheet electrode, and a thin-film dielectric layer formed between the first sheet electrode and the second sheet electrode;a first insulating film that insulated the first sheet electrode;a second insulating film that insulates the second sheet electrode; anda plurality of through holes, bored from the first insulating film to the second insulating film through the thin-film capacitor and formed in positions corresponding to the plurality of electrode pads, that include power supply through holes formed in positions corresponding to the power supply pads, ground through holes formed in positions corresponding to the ground pads, and signal through holes formed in positions corresponding to the signal pads.2. The thin-film capacitor structure according to claim 1 , wherein first overhangs ...

SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME

A semiconductor device may include a semiconductor substrate, a conductive pad on the semiconductor substrate, a passivation layer overlying the semiconductor substrate and exposing the conductive pad, and a bump structure. The bump structure may include a first bump structure on the conductive pad and a second bump structure on the passivation layer. The first bump structure may include a base bump layer, a first pillar bump layer, and a first solder bump layer that are sequentially stacked on the conductive pad. The second bump structure may include a second pillar bump layer and a second solder bump layer that are sequentially stacked on the passivation layer. 1. A semiconductor device , comprising:a semiconductor substrate;a conductive pad on the semiconductor substrate;a passivation layer on the semiconductor substrate, the passivation layer including an opening exposing the conductive pad;a first under bump metal (UBM) layer on the exposed conductive pad, and a second under bump metal (UBM) layer on the passivation layer;a first bump structure on the first UBM layer, the first bump structure including a base bump layer, a first pillar bump layer, and a first solder bump layer sequentially stacked on the first UBM layer; anda second bump structure on the second UBM layer, the second bump structure including a second pillar bump layer and a second solder bump layer sequentially stacked on the second UBM layer.2. The semiconductor device of claim 1 , wherein each of horizontal widths of the opening and the base bump layer is greater than a horizontal width of the first pillar bump layer.3. The semiconductor device of claim 1 , wherein the base bump layer comprises a base portion underneath the first pillar bump layer and a protrusion portion spaced apart from the first pillar bump layer.4. The semiconductor device of claim 3 , wherein the base portion fills at least a portion of the opening.5. The semiconductor device of claim 3 , wherein the protrusion portion ...

Integrated fan-out package and manufacturing method thereof

An integrated fan-out (InFO) package includes at least one die, a plurality of conductive structures, an encapsulant, an enhancement layer, and a redistribution structure. The die has an active surface and includes a plurality of conductive posts on the active surface. The conductive structures surround the die. The encapsulant partially encapsulates the die. The enhancement layer is over the encapsulant. A top surface of the enhancement layer is substantially coplanar with top surfaces of the conductive posts and the conductive structures. A material of the enhancement layer is different from a material of the encapsulant. A roughness of an interface between the encapsulant and the enhancement layer is larger than a roughness of the top surface of the enhancement layer. The redistribution structure is over the enhancement layer and is electrically connected to the conductive structures and the die.

SEMICONDUCTOR CHIP

A semiconductor chip has a first transistor that amplifies a first signal and outputs a second signal, a second transistor that amplifies the second signal and outputs a third signal, and a semiconductor substrate having a main surface parallel to a plane defined by first and second directions and which has the first and second transistors formed thereon. The main surface has thereon a first bump connected to a collector or drain of the first transistor, a second bump connected to an emitter or source of the first transistor, a third bump connected to a collector or drain of the second transistor, and a fourth bump connected to an emitter or source of the second transistor. The first bump is circular, the second through fourth bumps are rectangular or oval, and the area of each of the second through fourth bumps is larger than that of the first bump. 1. A semiconductor chip comprising:a first transistor which amplifies a first signal and outputs a second signal;a second transistor which amplifies the second signal and outputs a third signal; anda semiconductor substrate which has a main surface parallel to a plane defined by a first direction and a second direction intersecting with the first direction and which has the first transistor and the second transistor formed thereon, a first bump electrically connected to a collector or a drain of the first transistor;', 'a second bump electrically connected to an emitter or a source of the first transistor; and', 'a fourth bump electrically connected to an emitter or a source of the second transistor; and, 'the main surface of the semiconductor substrate being provided with 'an area of each of the second and the fourth bumps is larger than an area of the first bump.', 'in a planar view of the main surface of the semiconductor substrate,'}2. The semiconductor chip according to claim 1 , wherein:the main surface of the semiconductor substrate being provided with a third bump electrically connected to a collector or a drain ...

Packages for Semiconductor Devices, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices

Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region, a molding material around the integrated circuit die mounting region, and an interconnect structure over the molding material and the integrated circuit die mounting region. The interconnect structure has contact pads, and connectors are coupled to the contact pads. Two or more of the connectors have an alignment feature formed thereon. 1. A method of packaging a semiconductor device , the method comprising:providing a packaged semiconductor device including an integrated circuit die disposed in a molding material and an interconnect structure disposed over the integrated circuit die and the molding material, the interconnect structure comprising a plurality of contact pads;providing a plate comprising a plurality of connector patterns disposed thereon, two or more of the plurality of connector patterns including an alignment pattern disposed thereon; andforming a connector material in the plurality of connector patterns of the plate, wherein forming the connector material comprises forming a plurality of first connectors and a plurality of second connectors in the plurality of connector patterns of the plate, wherein the plurality of first connectors each comprises an alignment feature disposed thereon, and wherein the alignment features of the plurality of first connectors are formed from the alignment patterns of the two or more of the plurality of connector patterns on the plate.2. The method according to claim 1 , further comprising coupling each of the plurality of second connectors to a contact pad of a substrate or printed circuit board (PCB).3. The method according to claim 1 , further comprising aligning the packaged semiconductor device using the alignment features of the plurality of first connectors.4. The method ...

SEMICONDUCTOR CHIP

A semiconductor chip has a first transistor that amplifies a first signal and outputs a second signal, a second transistor that amplifies the second signal and outputs a third signal, and a semiconductor substrate having a main surface parallel to a plane defined by first and second directions and which has the first and second transistors formed thereon. The main surface has thereon a first bump connected to a collector or drain of the first transistor, a second bump connected to an emitter or source of the first transistor, a third bump connected to a collector or drain of the second transistor, and a fourth bump connected to an emitter or source of the second transistor. The first bump is circular, the second through fourth bumps are rectangular or oval, and the area of each of the second through fourth bumps is larger than that of the first bump. 1. A semiconductor chip comprising:a first transistor which amplifies a first signal and outputs a second signal;a second transistor which amplifies the second signal and outputs a third signal; anda semiconductor substrate which has a main surface parallel to a plane defined by a first direction and a second direction intersecting with the first direction and which has the first transistor and the second transistor formed thereon, the main surface of the semiconductor substrate that has a first side and a second side, which are parallel to the first direction, and a third side and a fourth side, which are parallel to the second direction, a centerline of the chip being provided at a point that is a midpoint between the third side and the fourth side and the centerline intersecting each of the first side and the second side, a first bump electrically connected to a collector or a drain of the first transistor;', 'a second bump electrically connected to an emitter or a source of the first transistor;', 'a third bump electrically connected to a collector or a drain of the second transistor;', 'a fourth bump electrically ...

Reducing solder pad topology differences by planarization

A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a substrate. The chip is provided with solder pads that may have different heights. A dielectric layer is formed between the solder pads. A relatively thick metal layer is plated over the solder pads. The metal layer is planarized to cause the top surfaces of the metal layer portions over the solder pads to be in the same plane and above the dielectric layer. A substantially uniformly thin layer of solder is deposited over the planarized metal layer portions so that the top surfaces of the solder bumps are substantially in the same plane. The chip is then positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.

High density package interconnects

Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A method of manufacturing a semiconductor device includes providing a carrier, disposing a first pad on the carrier, forming a post on the first pad, and disposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post. The first entire contact interface and the second entire contact interface are flat surfaces. 1. A method of manufacturing a semiconductor device , comprising:providing a first carrier;disposing a first pad on the first carrier;forming a post on the first pad; anddisposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post, wherein the first entire contact interface and the second entire contact\ interface are flat surfaces.2. The method of manufacturing the semiconductor device of claim 1 , wherein the disposing of the joint is performed by pasting a solder over the post and the first pad through a stencil.3. The method of manufacturing the semiconductor device of claim 1 , further comprising providing a second carrier and disposing a second pad on the second carrier.4. The method of manufacturing the semiconductor device of claim 3 , wherein a height of the post is greater than or equal to ⅓ of a distance between the first pad and the second pad.5. The method of manufacturing the semiconductor device of claim 3 , further comprising disposing the joint between the first pad and the second pad to bond the first pad with the second pad and to form a third entire contact interface between the joint and the second pad claim 3 , wherein the third entire contact interface is a flat surface.6. The method of manufacturing the semiconductor device of claim 5 , further comprising disposing a pre-soldering bump on the second pad prior to disposing the joint between the first ...

Multilayer structure for a semiconductor device and a method of forming a multilayer structure for a semiconductor device

A multilayer structure for a semiconductor device and a method of forming a multilayer structure for a semiconductor device. The multilayer structure comprises: a substrate having an electrically conductive portion thereon; a dielectric layer formed over the substrate; the dielectric layer comprising an opening over at least part of the electrically conductive portion; and a conductive pillar formed on the at least part of the electrically conductive portion; wherein the conductive pillar comprises walls defined by at least the opening of the dielectric layer and an opening of a patterned layer.

CHIP STRUCTURE

A chip structure including a chip body and a plurality of conductive bumps. The chip body includes an active surface and a plurality of bump pads disposed on the active surface. The conductive bumps are disposed on the active surface of the chip body and connected to the bump pads respectively, and at least one of the conductive bumps has a trapezoid shape having one pair of parallel sides and one pair of non-parallel sides. 1. A chip structure , comprising:a chip body comprising an active surface and a plurality of bump pads disposed on the active surface;a plurality of conductive bumps disposed on the active surface of the chip body and connected to the bump pads respectively, wherein at least one of the conductive bumps has a trapezoid shape having one pair of parallel sides and one pair of non-parallel sides.2. The chip structure according to claim 1 , wherein each of the conductive bumps has a long axis claim 1 , and the long axes of the conductive bumps cross with one another at a plurality of crossing points.3. The chip structure according to claim 1 , wherein each of the parallel sides is shorter than each of the non-parallel sides.4. The chip structure according to claim 1 , wherein the conductive bumps comprises a central conductive bump having an isosceles trapezoid shape.5. The chip structure according to claim 4 , wherein the conductive bumps further comprises a plurality of non-central conductive bumps having an obtuse trapezoid shape and located on two sides of the central conductive bump.6. The chip structure according to claim 5 , wherein the non-central conductive bumps are symmetrically arranged with respect to the central conductive bump.7. The chip structure according to claim 5 , wherein the non-central conductive bumps are asymmetrically arranged with respect to the central conductive bump.8. The chip structure according to claim 1 , wherein the conductive bumps are symmetrically arranged with respect to a central line of a bonding portion ...

Chip package structure and method for forming the same

A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a bump and a dummy bump over a second surface of the first substrate. The dummy bump is close to a first corner of the first substrate, and the dummy bump is wider than the bump. The method includes bonding the first substrate to a second substrate through the bump. The dummy bump is electrically insulated from the chip and the second substrate. The method includes forming a protective layer between the first substrate and the second substrate. The protective layer surrounds the dummy bump and the bump, and the protective layer is between the dummy bump and the second substrate.

INTERCONNECT FOR ELECTRONIC DEVICE

A semiconductor die includes a substrate and an integrated circuit provided on the substrate and having contacts. An electrically conductive layer is provided on the integrated circuit and defines electrically conductive elements electrically connected to the contacts. Electrically conductive interconnects coupled with respective electrically conductive elements. The electrically conductive interconnects have at least one of different sizes or shapes from one another. 1. A semiconductor die comprising:a substrate;an integrated circuit provided on the substrate and including contacts;an electrically conductive layer provided on the integrated circuit and defining electrically conductive elements electrically connected to the contacts; andelectrically conductive interconnects coupled to respective electrically conductive elements, the electrically conductive interconnects including at least one of different sizes or shapes from one another, wherein at least one electrically conductive element is in between fingers of another electrically conductive element, and wherein at least one of the electrically conductive interconnects is electrically connected to at least two of the electrically conductive elements.2. The die recited in claim 1 , wherein at least one of the electrically conductive interconnects has a thickness extending away from the electrically conductive elements greater than a width extending perpendicular to the thickness.3. The die recited in claim 1 , wherein at least one of the electrically conductive interconnects is polygonal in shape.4. The die recited in claim 1 , wherein at least one of the electrically conductive interconnects has an aspect ratio greater than 1:1.5. The die recited in claim 1 , further comprising an insulating layer provided over the electrically conductive layer and including openings exposing the electrically conductive elements.6. The die recited in claim 5 , wherein the electrically conductive interconnects extend through the ...

SEMICONDUCTOR DEVICE ASSEMBLY WITH THROUGH-PACKAGE INTERCONNECT AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS

Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device. 1. A method of manufacturing a semiconductor device assembly , comprising: 'forming a second material that covers an outer surface of the first material; and', 'at least partially encapsulating a semiconductor device and a feature attached to the semiconductor device with a first material, wherein the feature includes a plated material;'}contacting the second material with at least a portion of the feature.2. The method of wherein contacting the second material with the portion of the feature comprises pressing the portion of the feature through the first material and penetrating the portion of the feature into the second material3. The method of claim 1 , further comprising:forming a semiconductor device package that includes the semiconductor device, the feature, and at least a portion of the first material; andforming an electrical connection with the semiconductor device package via the feature.4. The method of claim 1 , further comprising forming the feature by one or more processes that include forming a conductive standoff structure at surface of the semiconductor die.5. A semiconductor device assembly claim 1 , comprising:an encapsulant that includes an outer surface;a semiconductor device at least partially encased within the encapsulant and having an ...

ELECTRONIC DEVICE MODULE AND METHOD OF MANUFACTURING THE SAME

The electronic device module includes a sealing part sealing an electronic component therein, and an external connection terminal disposed on one surface of the sealing part. The electronic device module also includes a dummy bonding part configured on a surface of the sealing part and spaced apart from the external connection terminal. 1. A method of manufacturing an electronic device module , comprising:sealing an electronic component to form a sealing part, wherein the electronic component is mounted on a board; andforming an external connection terminal and a dummy bonding part on one surface of the sealing part.3. The method of claim 1 , wherein the forming of the external connection terminal and the dummy bonding part comprises:applying a solder paste to positions in which the external connection terminal and the dummy bonding part are to be formed on a surface of the sealing part; andmelting and hardening the solder paste.4. The method of claim 1 , wherein the forming of the external connection terminal and the dummy bonding part comprises:attaching the external connection terminal to a surface of the sealing part;forming a coupling groove at a position in which the dummy bonding part is to be formed on a surface of the sealing part; andattaching the dummy bonding part to the coupling groove.5. The method of claim 4 , wherein a thermoplastic adhesive is applied to the coupling groove to attach the dummy bonding part to the coupling groove.6. The method of claim 1 , wherein the forming of the dummy bonding part comprises:forming a coupling groove on a surface of the sealing part;forming an under bump metallization (UBM) in the coupling groove; andattaching the dummy bonding part to the UBM.7. The method of claim 2 , further comprising:forming an auxiliary pattern on one surface the sealing part, the auxiliary pattern electrically connecting the dummy bonding part and the connection conductor to each other. This application is a divisional of application Ser. ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate, a first semiconductor chip and a second semiconductor chip adjacent to each other on the substrate, and a plurality of bumps on lower surfaces of the first and second semiconductor chips. The first and second semiconductor chips have facing first side surfaces and second side surfaces opposite to the first side surfaces. The bumps are arranged at a higher density in first regions adjacent to the first side surfaces than in second regions adjacent to the second side surfaces. 120.-. (canceled)21. A semiconductor package , comprising:a substrate;at least two semiconductor chips on the substrate;a plurality of bumps on lower surfaces of respective ones of the at least two semiconductor chips, the plurality of bumps being arranged at a higher density in adjacent regions of the at least two semiconductor chips than in other regions of the at least two semiconductor chips; andat least one insulating layer between the substrate and each of the at least two semiconductor chips to fill between the plurality of bumps, the at least one insulating layer having a volume in a region between the at least two semiconductor chips that is smaller than a volume in a region outside non-adjacent side surfaces of the at least two semiconductor chips.22. The semiconductor package as claimed in claim 21 , wherein the at least one insulating layer protrudes outward from the non-adjacent side surfaces of the at least two semiconductor chips farther than from adjacent side surfaces of the at least two semiconductor chips.23. The semiconductor package as claimed in claim 22 , wherein the at least one insulating layer protrudes from other side surfaces of the at least two semiconductor chips connecting respective ones of the adjacent side surfaces and the non-adjacent side surfaces claim 22 , anda protrusion distance from the other side surfaces of the at least two semiconductor chips is greater than a protursion distance from the adjacent side ...

SEMICONDUCTOR PACKAGE WITH RIGID UNDER BUMP METALLURGY (UBM) STACK

The invention provides a semiconductor package. The semiconductor package includes a semiconductor die and a conductive pillar bump structure and a conductive plug. The semiconductor die has a die pad thereon. The conductive pillar bump structure is positioned overlying the die pad. The conductive pillar bump structure includes an under bump metallurgy (UBM) stack having a first diameter and a conductive plug on the UBM stack. The conductive plug has a second diameter that is different than the first diameter. 1. A semiconductor package , comprising:a semiconductor die having a die pad thereon; and an under bump metallurgy (UBM) stack having a first diameter; and', 'a conductive plug on the UBM stack,', 'wherein the conductive plug has a second diameter that is different than the first diameter., 'a conductive pillar bump structure overlying the die pad, wherein the conductive pillar bump structure comprises2. The semiconductor package as claimed in claim 1 , wherein the first diameter and the second diameter are along a direction that is substantially parallel to a front-side surface of the semiconductor die.3. The semiconductor package as claimed in claim 1 , wherein the first diameter is greater than the second diameter.4. The semiconductor package as claimed in claim 1 , wherein an overlapping area between the conductive plug and a top surface of the UBM stack is less than an area of the top surface of the UBM stack.5. The semiconductor package as claimed in claim 1 , wherein the conductive plug is overlying a portion of the top surface of the UBM stack.6. The semiconductor package as claimed in claim 1 , wherein an interface between the conductive plug and the UBM stack is a planar surface.7. The semiconductor package as claimed in claim 1 , wherein the UBM stack comprises:a first metal layer in contact with the die pad of the semiconductor die; anda second metal pad overlying the first metal layer and in contact with the conductive plug.8. The semiconductor ...

Method and System for Packing Optimization of Semiconductor Devices

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently. 120-. (canceled)21. An apparatus , comprising:a substrate having a first surface and a second surface opposite the first surface; anda plurality of interconnects arranged on the second surface of the substrate;wherein the plurality of interconnects include a plurality of first interconnects;wherein each first interconnect of the plurality of first interconnects includes a minor axis and a major axis;wherein the major axis of each first interconnect is greater than the minor axis of its respective first interconnect; andwherein the major axis of each first interconnect is perpendicular to a radial axis extending from a radial origin of the second surface of the substrate.22. The apparatus of claim 21 , wherein:the plurality of interconnects comprises a plurality of second interconnects;wherein each second interconnect of the plurality of second interconnects comprises a minor axis and a major axis;wherein the major axis of each second interconnect is greater than the minor axis of its respective second interconnect; andwherein the major axis of each second interconnect is perpendicular to a reference line parallel to the radial axis of the second surface.23. The apparatus of claim 21 , wherein:the plurality of interconnects define a plurality of rows of interconnects;a row from the plurality of rows extends along a non-linear edge of the substrate; andthe non-linear edge is conformal to a contour defined by the interconnects in the row.24. The apparatus of claim 21 , wherein:the plurality of interconnects define a plurality of rows of interconnects;the interconnects of the plurality of rows are horizontally spaced according to a first pitch; andthe interconnects of the plurality of rows are vertically spaced according to a second pitch that is less than the first pitch.25. The ...

SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD

A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature. 1. A semiconductor device structure , comprising:a semiconductor substrate;a dielectric layer over the semiconductor substrate;a conductive trace over the dielectric layer;a conductive feature over the conductive trace, wherein a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace; anda conductive bump over the conductive feature.2. The semiconductor device structure as claimed in claim 1 , wherein the conductive feature extends over a sidewall of the conductive trace.3. The semiconductor device structure as claimed in claim 1 , wherein a sidewall of the conductive feature is aligned with a sidewall of the conductive trace.4. The semiconductor device structure as claimed in claim 1 , further comprising:a second conductive feature over the conductive trace; anda second conductive bump over the second conductive feature.5. The semiconductor device structure as claimed in claim 4 , wherein a width of the second conductive feature is substantially equal to or larger than the maximum width of the conductive trace.6. The semiconductor device structure as claimed in claim 1 , further comprising:a substrate; anda second conductive trace over the substrate, wherein the second conductive trace bonds with the conductive bump.7. The semiconductor device structure as claimed in claim 6 , wherein the width of ...

Semiconductor device

A semiconductor device includes an electronic component, a package, a substrate and a plurality of first conductors and second conductors. The package is over the electronic component. T substrate is between the electronic component and the package. The substrate includes a first portion covered by the package, and a second portion protruding out of an edge of the package and uncovered by the package. The first conductors and second conductors are between and electrically connected to the electronic component and the substrate. A width of a second conductor of the plurality of second conductors is larger than a width of a first conductor of the plurality of first conductors, the first conductors are disposed between the second portion of the substrate and the electronic component, and the second conductors are disposed between the first portion of the substrate and the electronic component.

SEMICONDUCTOR DEVICE ASSEMBLY WITH THROUGH-PACKAGE INTERCONNECT AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS

Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device. 1. A method of manufacturing a semiconductor device assembly , comprising: forming a second material that covers an outer surface of the first material; and', 'contacting the second material with at least a portion of the feature., 'at least partially encapsulating a semiconductor device and a feature attached to the semiconductor device with a first material, wherein the feature includes a plated material;'}2. The method of wherein contacting the second material with the portion of the feature comprises pressing the portion of the feature through the first material and penetrating the portion of the feature into the second material3. The method of claim 1 , further comprising:forming a semiconductor device package that includes the semiconductor device, the feature, and at least a portion of the first material; andforming an electrical connection with the semiconductor device package via the feature.4. The method of claim 1 , further comprising forming the feature by one or more processes that include forming a conductive standoff structure at surface of the semiconductor die.5. A semiconductor device assembly claim 1 , comprising:an encapsulant that includes an outer surface;a semiconductor device at least partially encased within the encapsulant and having ...

SEMICONDUCTOR CHIP, SEMICONDUCTOR DEVICE AND MANUFACTURING PROCESS FOR MANUFACTURING THE SAME

A semiconductor device includes a substrate main body, a plurality of first bump pads, and redistribution layer (RDL). The first bump pads are disposed adjacent to a surface of the substrate main body, each of the first bump pads has a first profile from a top view, the first profile has a first width along a first direction and a second width along a second direction perpendicular to the first direction, and the first width of the first profile is greater than the second width of the first profile. The RDL is disposed adjacent to the surface of the substrate main body, and the RDL includes a first portion disposed between two first bump pads. 1. A semiconductor chip , comprising:a chip main body;at least one first pillar disposed adjacent to a surface of the chip main body, wherein the first pillar has a first profile from a bottom view, the first profile has a first width along a first direction and a second width along a second direction perpendicular to the first direction, and the first width of the first profile is greater than the second width of the first profile; andat least one second pillar disposed adjacent to the surface of the chip main body, wherein the second pillar has a second profile from a bottom view, and a shape of the first profile is different from a shape of the second profile.2. The semiconductor chip of claim 1 , wherein the at least one first pillar is a plurality of first pillars arranged along the first direction.3. The semiconductor chip of claim 1 , wherein the at least one second pillar is a plurality of second pillars arranged in an array.4. The semiconductor chip of claim 1 , wherein an area of the first profile is substantially equal to an area of the second profile.5. The semiconductor chip of claim 1 , wherein the second profile has a first width along the first direction and a second width along the second direction perpendicular to the first direction claim 1 , and the first width of the second profile is substantially equal ...

SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES, METHODS OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME

A semiconductor device includes a semiconductor layer having a first surface and a second surface, a through electrode penetrating the semiconductor layer and having a protruding portion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed on the first surface of the semiconductor layer and electrically coupled to the through electrode, a passivation pattern including a first insulation pattern that surrounds a sidewall of the protruding portion of the through electrode and extends onto the second surface of the semiconductor layer and a second insulation pattern that covers the first insulation pattern and has an etch selectivity with respect to the first insulation pattern, and a back-side bump covering an end surface of the protruding portion of the through electrode and extending onto the passivation pattern. 1. A semiconductor device comprising:a semiconductor layer having a first surface and a second surface;a through electrode penetrating the semiconductor layer and having a protruding portion that protrudes over the second surface of the semiconductor layer by a predetermined height;a front-side bump disposed over the first surface of the semiconductor layer and electrically coupled to the through electrode;a passivation pattern including a first insulation pattern that surrounds a sidewall of the protrusion of the through electrode and extends onto the second surface of the semiconductor layer and a second insulation pattern that covers the first insulation pattern and has an etch selectivity with respect to the first insulation pattern, wherein a portion of the passivation pattern under the back-side bump has a first thickness and a portion of the passivation pattern on the second surface of the semiconductor layer that does not overlap with the back-side bump has a second thickness which is less than the first thickness; anda back-side bump covering an end surface of the protruding portion of the through electrode ...

Dummy Flip Chip Bumps for Reducing Stress

A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. 1. A method comprising: bonding a first solder region to be between and joining to both of an electrical connector of the device die and a metal trace of the package component, wherein the first solder region contacts a bottom surface and sidewalls of the metal trace, and the metal trace is in a surface dielectric layer of the package component; and', 'contacting a second solder region to a bottom surface of the surface dielectric layer or a bond pad of the package component, wherein the bond pad is in the surface dielectric layer, and wherein the second solder region is joined to a dummy bump of the device die., 'bonding a package component to a device die, wherein the bonding comprises2. The method of further comprising forming the device die comprising:forming an additional dielectric layer; andforming the dummy bump over the additional dielectric layer, with an entirety of a bottom surface of the dummy bump contacting a top surface of the additional dielectric layer.3. The method of claim 2 , wherein the dummy bump is electrically disconnected from all conductive components that are lower than the top surface of the additional dielectric layer.4. The method of claim 1 , wherein after the bonding claim 1 , the dummy bump is electrically floating.5. The method of claim 1 , wherein the first solder region extends into an opening in the surface dielectric layer of the package component.6. The method of further comprising claim 5 , after the package component is bonded to the device die claim 5 , dispensing an underfill between ...

WAFER LEVEL PACKAGING OF MULTIPLE LIGHT EMITTING DIODES (LEDS) ON A SINGLE CARRIER DIE

An LED wafer includes LED dies on an LED substrate. The LED wafer and a carrier wafer are joined. The LED wafer that is joined to the carrier wafer is shaped. Wavelength conversion material is applied to the LED wafer that is shaped. Singulation is performed to provide multiple LED dies that are joined to a single carrier die. The multiple LED dies on the single carrier die are connected in series and/or in parallel by interconnection in the LED dies and/or in the single carrier die. The singulated devices may be mounted in an LED fixture to provide high light output per unit area. Related devices and fabrication methods are described.

Eutectic Electrode Structure of Flip-chip LED Chip and Flip-chip LED Chip

A flip-chip LED chip includes: a substrate; a first semiconductor layer; a light emitting layer; a second semiconductor layer; a local defect region over part of the second semiconductor layer and extending downward to the first semiconductor layer; first and second metal layers respectively over portions of the first and second semiconductor layers; an insulating layer covering the first and second metal layers, the second and first semiconductor layers in the local defect region. The insulating layer has opening structures over the first and second metal layers respectively; a eutectic electrode structure over the insulating layer with openings and including first and second eutectic layers from bottom up at a vertical direction, and including first-type and second-type electrode regions at a horizontal direction. The second eutectic layer does not overlap with the first and second metal layers at the vertical direction. 1. A flip-chip LED chip , comprising:a substrate;a first semiconductor layer over the substrate;a light-emitting layer over the first semiconductor layer;a second semiconductor layer over the light emitting layer;a local defect region over a portion of the second semiconductor layer, the local defect region extending downward to the first semiconductor layer;a first metal layer over a portion of the first semiconductor layer;a second metal layer over a portion of the second semiconductor layer;an insulating layer covering the first metal layer, the second metal layer, the second semiconductor layer and the first semiconductor layer in the local defect region, wherein the insulating layer has opening structures over the first metal layer and the second metal layer, respectively; anda eutectic electrode structure over the insulating layer with openings, wherein the eutectic electrode structure comprises a first eutectic layer and a second eutectic layer from bottom up at a vertical direction, and includes a first-type electrode region and a second- ...

Driving chip and display device

A driving chip and a display device are provided herein. The driving chip includes a substrate, a plurality of connection bumps and a plurality of buffer bumps on the substrate. Each of the connection bumps and the buffer bumps is disposed on a first substrate of the substrate. The buffer bump includes a first end face with a height a, and the connection bump has a connection bump end face with a height b, a<b. The height is a distance from a corresponding end face of the connection bump or the buffer bump to the first surface. With the buffer bumps on the driving chip, stress buffering can be achieved, which can further improve the bonding effect of the driving chip.

Illumination device

An illumination device includes a supporting base, and a light-emitting element inserted in the supporting base. The light-emitting element includes a substrate having a supporting surface and a side surface, a light-emitting chip disposed on the supporting surface, and a first wavelength conversion layer covering the light-emitting chip and only a portion of the supporting surface without covering the side surface.

Semiconductor package and method of manufacturing thereof

A semiconductor package comprises a semiconductor chip having an active surface with a conductive pad thereon; an electroplated Au—Sn alloy bump over the active surface; and a (glass) substrate comprising conductive traces electrically coupling with the electroplated Au—Sn alloy bump, wherein the electroplated Au—Sn alloy bump has a composition from about Au 0.85 Sn 0.15 to about Au 0.75 Sn 0.25 in weight percent uniformly distributed from an end in proximity to the active surface to an end in proximity to the substrate. A method of manufacturing a semiconductor package comprises forming patterns of conductive pads on an active surface of a semiconductor chip; electroplating Au—Sn alloy bump over the conductive pads; and bonding the semiconductor chip on a corresponding conductive trace on a substrate by a reflow operation or a thermal press operation.

Solderless Interconnection Structure and Method of Forming Same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion. 1. A device comprising:a substrate trace extending along a first substrate, the substrate trace having a first shape in a plan view; anda metal ladder bump extending from an integrated circuit, the metal ladder bump having a second shape in the plan view, the second shape being different from the first shape,wherein the metal ladder bump and the substrate trace are physically and electrically coupled together through direct metal-to-metal bonds, an interface between the metal ladder bump and the substrate trace being free from solder.2. The device of claim 1 , wherein the substrate trace has a first length claim 1 , the metal ladder bump has a second length claim 1 , and the first length is greater than the second length claim 1 , the first length and the second length each being measured in a direction parallel to a longitudinal axis of the substrate trace.3. The device of claim 1 , wherein the second shape is a quadrilateral.4. The device of claim 1 , wherein the second shape is a circle.5. The device of claim 1 , wherein the metal ladder bump and the substrate trace are copper claim 1 , and wherein the interface between the metal ladder bump and the substrate trace is free from intermetallic compounds.6. The device of claim 1 , wherein the substrate trace has a first end proximate the first substrate and a second end distal the first substrate claim 1 , the first end having a greater width than the second end. ...

INTEGRATED CIRCUIT CHIP, METHOD OF MANUFACTURING THE INTEGRATED CIRCUIT CHIP, AND INTEGRATED CIRCUIT PACKAGE AND DISPLAY APPARATUS INCLUDING THE INTEGRATED CIRCUIT CHIP

An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.

BUMP STRUCTURE HAVING A SIDE RECESS AND SEMICONDUCTOR STRUCTURE INCLUDING THE SAME

A bump structure includes a first end; and a second end opposite the first end. The bump structure further includes a side connected between the first end and the second end, wherein the side comprises a recess for a reflowed solder material to fill, and the recess defines a first surface adjacent to the first end and a second surface adjacent to the second end. 1. A bump structure comprising:a first end;a second end opposite the first end; anda side connected between the first end and the second end, wherein the side comprises a recess, and the recess defines a first surface adjacent to the first end and a second surface adjacent to the second end.2. The bump structure of claim 1 , wherein the first surface is substantially planar and the second surface is substantially planar.3. The bump structure of claim 2 , wherein the first surface directly contacts the second surface.4. The bump structure of claim 2 , wherein the recess further defines a third surface connecting the first surface to the second surface.5. The bump structure of claim 4 , wherein the third surface is substantially perpendicular to at least one of the first surface or the second surface.6. The bump structure of claim 4 , wherein the third surface is a curved surface.7. The bump structure of claim 4 , wherein a length of the third surface is equal to or less than about 30 microns (μm).8. The bump structure of claim 1 , wherein a shape of the first end is different from a shape of the second end.9. The bump structure of claim 1 , wherein a depth of the recess into the bump structure ranges from about 0.5 μm to about 15 μm.10. The bump structure of claim 1 , wherein a maximum distance between the first surface and the second surface ranges from about 8 μm to about 15 μm.11. A semiconductor structure comprising: a first end;', 'a second end opposite the first end; and', 'a side connected between the first end and the second end, wherein the side comprises a recess,, 'a plurality of bump structures ...

Illumination device

An illumination device includes a supporting base, and a light-emitting element inserted in the supporting base. The light-emitting element includes a substrate having a supporting surface and a side surface, a light-emitting chip disposed on the supporting surface, and a first wavelength conversion layer covering the light-emitting chip and only a portion of the supporting surface without covering the side surface.

Packaging Devices, Methods of Manufacture Thereof, and Packaging Methods

Packaging devices, methods of manufacture thereof, and packaging methods are disclosed. In some embodiments, a packaging device includes a first substrate including a post passivation interconnect (PPI) structure including a PPI pad disposed thereon, and a second substrate including a contact pad disposed thereon. A conductive bump is coupled between the PPI pad and the contact pad. A molding material is disposed over portions of the PPI structure proximate the conductive bump. A top surface of the molding material contacts the conductive bump at a height of the conductive bump having a width C, and the contact pad has a width B. A ratio R of C:B comprises about 1.0 or greater. 1. A packaging device comprising:a first substrate including a post passivation interconnect (PPI) structure including a PPI pad disposed thereon, the PPI structure being on a first side of the first substrate;a second substrate including a contact pad disposed thereon;a conductive bump coupled between the PPI pad and the contact pad, the conductive bump being a solder bump;a molding material disposed over portions of the PPI structure proximate the conductive bump, wherein a top surface of the molding material contacts the conductive bump at a height of the conductive bump comprising a width C, wherein the contact pad comprises a width B, and wherein a ratio R of C:B comprises about 1.0 or greater;a third substrate coupled to a second side of the first substrate using a plurality of controlled collapse chip connection (C4) bumps, the C4 bumps having a different size than the solder bump, the second side of the first substrate being opposite the first side of the first substrate; andan integrated circuit die coupled to the third substrate using a plurality of microbumps, the plurality of microbumps having a different size than the C4 bumps and the solder bump.2. The packaging device according to claim 1 , wherein the conductive bump comprises a stand-off height H between the contact pad and ...

Eutectic Electrode Structure of Flip-chip LED Chip and Flip-chip LED Chip

A light emitting diode includes: a light emitting structure including a first semiconductor layer, a light emitting layer, a second semiconductor layer; a first metal layer arranged on at least a portion of the first semiconductor layer and in contact with the first semiconductor layer; and an electrode layer arranged over the light emitting structure, and having a first electrode layer and a second electrode layer. The first electrode layer is electrically coupled to the first and second semiconductor layers; the second electrode layer is configured for bonding with a package substrate, and includes a first and second bonding regions; the first bonding region is electrically coupled to the first semiconductor layer; the second bonding region is electrically coupled to the second semiconductor layer; and the first metal layer is not overlapped with the first bonding region of the second bonding region in a vertical direction. 1. A light emitting diode , comprising:a light emitting structure including a first semiconductor layer, a light emitting layer arranged on at least part of the first semiconductor layer, a second semiconductor layer arranged on the light emitting layer;a first metal layer arranged on at least a portion of the first semiconductor layer and in contact with the first semiconductor layer; andan electrode layer arranged over the light emitting structure, and having a first electrode layer and a second electrode layer,wherein:the first electrode layer is electrically coupled to the first semiconductor layer and the second semiconductor layer;the second electrode layer is configured for bonding with a package substrate, and includes a first bonding region and a second bonding region;the first bonding region is electrically coupled to the first semiconductor layer;the second bonding region is electrically coupled to the second semiconductor layer; andthe first metal layer is not overlapped with the first bonding region of the second bonding region in ...

CHIP STRUCTURE

A chip structure including a chip body and a plurality of conductive bumps. The chip body includes an active surface and a plurality of bump pads disposed on the active surface. The conductive bumps are disposed on the active surface of the chip body and connected to the bump pads respectively, and at least one of the conductive bumps has a trapezoid shape having one pair of parallel sides and one pair of non-parallel sides. 1. A chip structure , comprising:a chip body comprising an active surface and a plurality of bump pads disposed on the active surface;a plurality of conductive bumps disposed on the active surface of the chip body and connected to the bump pads respectively, wherein, in a top view toward the active surface, at least one of the conductive bumps has a trapezoid shape having one pair of parallel sides and one pair of non-parallel sides, and each of the conductive bumps has a long axis, and the long axes of the conductive bumps cross with one another at a plurality of crossing points.2. The chip structure according to claim 1 , wherein each of the conductive bumps has a long axis claim 1 , and the long axes of the conductive bumps cross with one another at a plurality of crossing points.3. The chip structure according to claim 1 , wherein each of the parallel sides is shorter than each of the non-parallel sides.4. The chip structure according to claim 1 , wherein the conductive bumps comprise a central conductive bump having an isosceles trapezoid shape.5. The chip structure according to claim 4 , wherein the conductive bumps further comprise a plurality of non-central conductive bumps having an obtuse trapezoid shape and located on two sides of the central conductive bump.6. The chip structure according to claim 5 , wherein the non-central conductive bumps are symmetrically arranged with respect to the central conductive bump.7. The chip structure according to claim 5 , wherein the non-central conductive bumps are asymmetrically arranged with ...

INTERCONNECT STRUCTURE FOR A MICROELECTRONIC DEVICE

A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.

Centripetal bumping layout and method

A bumping matrix includes many bumps, wherein each bump is rotationally asymmetric in a plane of the bumping matrix. The bumps are orientated in a centripetal arrangement. Bumps in a first portion of the bumping matrix have a first pitch in a first axis and bumps in a second portion of the bumping matrix have a second pitch in the first axis. The second pitch is different from the first pitch. Bumps have an oblong shape with a longer diameter and a shorter diameter. The centripetal arrangement orients the longer diameter of the bumps is a direction radially extending from a center of the bumping matrix.

High frequency module

A high frequency module includes a power amplifier and a substrate on which the power amplifier is mounted. The power amplifier includes a first external terminal and a second external terminal formed on a mounting surface. The substrate includes a first land electrode and a second land electrode formed on one principal surface. The first external terminal is connected to the first land electrode, and the second external terminal is connected to the second land electrode. A distance from the mounting surface to a connection surface of the first external terminal is shorter than a distance from the mounting surface to a connection surface of the second external terminal, and a distance from a connection surface of the first land electrode to the one principal surface is longer than a distance from a connection surface of the second land electrode to the one principal surface.

DEFORMABLE CONDUCTIVE CONTACTS

Deformable conductive contacts are provided. A plurality of deformable contacts on a first substrate may be joined to a plurality of conductive pads on a second substrate during die level or wafer level assembly of microelectronics. Each deformable contact complies to a degree that is related to the amount of joining pressure between the first substrate and the second substrate. Since an individual contact can make the conductive coupling within a range of distances from a target pad, an array of the deformable contacts provides tolerance and compliance when there is some variation in height of the conductive elements on either side of the join. A flowable underfill may be provided to press the deformable contacts against opposing pads and to permanently join the surfaces at a fixed distance. The deformable contacts may include a wiping feature to clear their target pads for establishing improved metal-to-metal contact or a thermocompression bond. 1. A system , comprising:a plurality of deformable contacts on a first substrate;a plurality of conductive pads on a second substrate;each deformable contact to conductively couple with a corresponding conductive pad when the first substrate is joined to the second substrate;each deformable contact configured to change shape in relation to a degree of compression against each corresponding conductive pad; andat least one underfill material between the first substrate and the second substrate to deform each deformable contact against each corresponding conductive pad and to determine a closest proximity of the first substrate to the second substrate.2. The system of claim 1 , wherein each deformable contact further comprises at least a wiping surface for moving across a surface of the corresponding conductive pad while conductively coupling with the corresponding conductive pad.3. The system of claim 1 , wherein each deformable contact comprises a geometry capable of providing degrees of deformability to provide compliance ...

P-N SEPARATION METAL FILL FOR FLIP CHIP LEDS

A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer is formed in the gap followed by filling the gap with a metal. The metal is patterned to form stud bumps that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps. 119-. (canceled)20. A light-emitting device , comprising:a semiconductor structure, including a first conductivity layer, an active layer, and a second conductivity layer, the semiconductor structure having a bottom surface and a top surface;a first electrode opposing the bottom surface and electrically connected to the first conductivity layer, the first electrode having a first sidewall;a second electrode opposing the bottom surface and electrically connected to the second conductivity layer, the second electrode having a second sidewall facing the first sidewall;a dielectric layer formed on at least one of the first sidewall and the second sidewall; anda metal layer arranged to at least partially fill a gap between the first sidewall of the first electrode and the second sidewall of the second electrode, the metal layer being electrically insulated from at least one of the first sidewall and the second sidewall by the dielectric layer.21. The light-emitting device of claim 20 , wherein the metal layer substantially ...

Method and System for Packing Optimization of Semiconductor Devices

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently. 120-. (canceled)21. An apparatus , comprising:a substrate having a first surface and a second surface opposite the first surface, wherein the second surface comprises wedge-shaped regions bounded by first radial reference lines that radiate from a radial origin of the second surface and form acute central angles at the radial origin; andfirst interconnects arranged in each of the wedge-shaped regions, wherein each first interconnect includes a minor axis and a major axis greater than its respective minor axis, and wherein the major axis of each first interconnect in its respective wedge-shaped region is parallel to a second radial reference line that radiates from the radial origin and bisects the respective wedge-shaped region.22. The apparatus of claim 21 , further comprising:second interconnects, each second interconnect comprising a minor axis and a major axis greater than its respective minor axis;wherein the second surface of the substrate comprises a first perimeter edge; andwherein each second interconnect is arranged along the first perimeter edge of the second surface such that the major axis of each second interconnect is parallel to the first perimeter edge of the second surface.23. The apparatus of claim 21 , further comprising:second interconnects, each second interconnect comprising a minor axis and a major axis greater than its respective minor axis;wherein the second surface of the substrate comprises a perimeter edge with one or more corners; andwherein each second interconnect is arranged along a first corner of the one or more corners such that the major axis of each second interconnect is perpendicular to a third radial reference line that radiates from the radial origin and through the first corner of the one or more corners.24. The apparatus of claim 21 , ...

Die Features for Self-Alignment During Die Bonding

A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.

Semiconductor device

A semiconductor device includes at least one transistor disposed on or in a substrate. The transistor is a bipolar transistor including an emitter, a base, and a collector, or a field-effect transistor including a source, a gate, and a drain. At least one first bump connected to the emitter or the source is disposed on the substrate. Furthermore, at least three second bumps connected to the collector or the drain are disposed on the substrate. In plan view, a geometric center of the at least one first bump is located inside a polygon whose vertices correspond to geometric centers of the at least three second bumps.

Apparatus and methods for substantial planarization of solder bumps

Apparatus and methods for substantial planarization of solder bumps. In one embodiment, an apparatus includes a planarization member engageable with at least some of the plurality of outer surfaces to apply a planarization action on one or more of the outer surfaces to substantially planarize the plurality of outer surfaces, and a securing element to securely position the bumped device during engagement with the planarization member. Through application of “additive” and/or “subtractive” processes, the solder balls are substantially planarized. In alternate embodiments, the planarization member includes a cutting tool and the planarization action comprises a milling action; or the planarization member includes a heated platen and the planarization action comprises a thermo-mechanical deformation action; or the planarization member includes an abrasive surface and the planarization action comprises a grinding action; or the planarization member includes a chemical solution and the planarization action comprises a chemical reaction; or the planarization member includes a solder deposition device and the planarization action comprises a solder. In a further embodiment, an apparatus includes a load device to urge the at least some outer surfaces of the bumped device into engagement with the planarization member.

Semiconductor device, magnetic sensor, and magnetic sensor unit

반도체 칩과, 패드 전극과, 전극부와, 배선부를 포함하는 반도체 장치가 제공된다. 전기적인 절연 재료로 절연부가 형성되어, 적어도 상기 전극부를 상기 반도체 칩의 표면측에 노출시킨 상태에서, 상기 반도체 칩의 표면을 피복함과 함께 상기 센서 소자, 배선부 및 전극부를 밀봉한다. 전극부는, 상기 센서 소자와 상기 반도체 칩의 두께 방향으로 중첩되지 않는 위치에 배치된다. A semiconductor device including a semiconductor chip, a pad electrode, an electrode portion, and a wiring portion is provided. An insulating portion is formed of an electrical insulating material, and at least the electrode portion is exposed to the surface side of the semiconductor chip, covering the surface of the semiconductor chip and sealing the sensor element, the wiring portion, and the electrode portion. The electrode portion is disposed at a position which does not overlap in the thickness direction of the sensor element and the semiconductor chip. 반도체 칩, 패드 전극, 전극부, 배선부, 절연부 Semiconductor chip, pad electrode, electrode part, wiring part, insulation part

CHIP PACKAGE STRUCTURE

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a bump and a first dummy bump between the chip and the substrate. The bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, and the first dummy bump is wider than the bump. The chip package structure includes a first dummy solder layer under the first dummy bump and having a curved bottom surface facing and spaced apart from the substrate. 1. A chip package structure , comprising:a substrate;a chip over the substrate;a bump and a first dummy bump between the chip and the substrate, wherein the bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, and the first dummy bump is wider than the bump; anda first dummy solder layer under the first dummy bump and having a curved bottom surface facing and spaced apart from the substrate.2. The chip package structure as claimed in claim 1 , further comprising:a solder ball between the bump and the substrate, wherein the solder ball has a planar bottom surface facing the substrate.3. The chip package structure as claimed in claim 1 , wherein the first dummy bump is between the bump and a corner of the chip.4. The chip package structure as claimed in claim 1 , further comprising:an underfill layer between the chip and the substrate, wherein the underfill layer separates the first dummy solder layer from the substrate.5. The chip package structure as claimed in claim 1 , further comprising:a second dummy bump between the chip and the substrate, wherein the second dummy bump is connected to the substrate and electrically insulated from the chip; anda second dummy solder layer over the second dummy bump and electrically insulated from the chip.6. The chip package structure as claimed in claim ...

Metal-Bump Sidewall Protection

A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer.

Wiring board having solder bumps and method for manufacturing the same

半导体装置、磁传感器和磁传感器单元

本发明公开了一种半导体装置，包括半导体芯片；垫式电极；电极部分；线路部分和绝缘部分。绝缘部分由电绝缘材料形成，覆盖半导体芯片的表面且封装传感器元件、线路部分和电极部分，其状态为至少显露在半导体芯片的表面上的电极部分。电极部分设置于在半导体芯片的厚度方向上与传感器元件不重叠的位置。