Semiconductor device and a method for manufacturing a semiconductor device

According to various embodiments, a semiconductor device may include: at least one first contact pad on a front side of the semiconductor device; at least one second contact pad on the front side of the semiconductor device; a layer stack disposed at least partially over the at least one first contact pad, wherein the at least one second contact pad is at least partially free of the layer stack; wherein the layer stack includes at least an adhesion layer and a metallization layer; and wherein the metallization layer includes a metal alloy and wherein the adhesion layer is disposed between the metallization layer and the at least one first contact pad for adhering the metal alloy of the metallization layer to the at least one first contact pad.

BONDING WIRE FOR SEMICONDUCTOR DEVICE

There is provided a bonding wire that improves bonding reliability of a ball bonded part and ball formability and is suitable for on-vehicle devices. 1. A bonding wire for a semiconductor device comprising:a Cu alloy core material; anda Pd coating layer formed on a surface of the Cu alloy core material, whereinthe Cu alloy core material contains Ni,a concentration of Ni is 0.1 to 1.2 wt. % relative to the entire wire, anda thickness of the Pd coating layer is 0.015 to 0.150 □m.2. The bonding wire for a semiconductor device according to claim 1 , further comprising an Au skin layer on the Pd coating layer.3. The bonding wire for a semiconductor device according to claim 2 , wherein a thickness of the Au skin layer is 0.0005 to 0.050 □m.4. The bonding wire for a semiconductor device according to claim 1 , whereinthe Cu alloy core material further contains at least one element selected from B, In, Ca, P and Ti, anda concentration of the elements is 3 to 100 wt. ppm relative to the entire wire.5. The bonding wire for a semiconductor device according to claim 1 , whereinthe Cu alloy core material further contains Pt or Pd, anda concentration of Pt or Pd contained in the Cu alloy core material is 0.05 to 1.20 wt. %.6. The bonding wire for a semiconductor device according to claim 1 , wherein Cu is present at an outermost surface of the bonding wire. The present invention relates to a bonding wire for a semiconductor device used to connect electrodes on a semiconductor device and wiring of a circuit wiring board such as external leads.As a bonding wire for a semiconductor device which connects electrodes on a semiconductor device and external leads (hereinafter referred to as a “bonding wire”), a thin wire with a wire diameter of about 15 to 50 μm is mainly used today. For a bonding method with bonding wire, there is generally used a thermal compressive bonding technique with the aid of ultrasound, in which a general bonding device, a capillary tool used for bonding by ...

Package-On-Package Assembly With Wire Bonds To Encapsulation Surface

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer. 1. A method comprising:providing a substrate having a surface having a first region and a second region that at least partially surrounds the first region, the substrate surface having electrically conductive elements in the second region;disposing a microelectronic element overlying the substrate surface within the first region;joining metal wires to the electrically conductive elements;drawing the metal wires out of a bonding tool so that portions of the metal wires extend upward from the substrate;forming a dielectric encapsulation layer above the substrate surface, wherein the encapsulation layer covers the metal wires and the metal wires are spaced from one another by the encapsulation layer;removing a portion of the encapsulation layer to expose unencapsulated portions of the metal wires;providing an electrically conductive material on the dielectric encapsulation layer in electrical connection with the unencapsulated portions of the metal wires.2. The method of claim 1 , wherein the metal wires are a first plurality of metal wires claim 1 , the method further comprising joining ...

Stack-type semiconductor package

According to example embodiments, a stack-type semiconductor package includes a lower semiconductor package, an upper semiconductor package, connection pads, and a metal layer pattern. The lower semiconductor package includes a lower semiconductor chip on a top surface of a lower package substrate, lower lands on the lower package substrate, and an encapsulant on the top surface of the lower package substrate. The encapsulant defines via holes that expose the lower lands. The upper semiconductor package is on the encapsulant. Upper solder balls are connected to a bottom surface of the upper semiconductor package. The connection pads are on the via holes and the encapsulant. The connection pads electrically connect the lower semiconductor package to the upper semiconductor package. The metal layer pattern is between the lower package substrate and the upper semiconductor package. The metal layer pattern surrounds the connection pads and is isolated from the connection pads.

SUBSTRATE-LESS STACKABLE PACKAGE WITH WIRE-BOND INTERCONNECT

A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are unconvered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer. 1. A microelectronic package , comprising:first conductive elements, including a first trace, obtained from a same conductive layer located on a lower side of the microelectronic package;wire bond wires connected to and extending away from upper surfaces of the first conductive elements;a first microelectronic component coupled with a first attachment layer to the first trace;a first conductive via in the first attachment layer and interconnecting the first trace and a first contact structure of the first microelectronic component;a second microelectronic component coupled to the first microelectronic component with a second attachment layer;second conductive elements, including a second trace, respectively connected to upper surfaces of the wire bond wires; anda second conductive via in a dielectric layer and interconnecting the second trace and a second contact structure of the second microelectronic component.2. The microelectronic package according to claim 1 , wherein the first trace is for a first redistribution.3. The a microelectronic package according to claim 2 , wherein the second ...

BONDING WIRE FOR SEMICONDUCTOR DEVICE

The present invention provides a bonding wire which can satisfy bonding reliability, spring performance, and chip damage performance required in high-density packaging. A bonding wire contains one or more of In, Ga, and Cd for a total of 0.05 to 5 at %, and a balance being made up of Ag and incidental impurities. 1. A bonding wire for a semiconductor device containing one or more of In , Ga , and Cd for a total of 0.05 to 5 at % , and a balance being made up of Ag and incidental impurities.2. The bonding wire for a semiconductor device according to claim 1 , further containing one or more of Ni claim 1 , Cu claim 1 , Rh claim 1 , Pd claim 1 , Pt claim 1 , and Au for a total of 0.01 to 5 at %.3. The bonding wire for a semiconductor device according to claim 1 , further containing one or more of Be claim 1 , B claim 1 , P claim 1 , Ca claim 1 , Y claim 1 , La claim 1 , and Ce for a total of 10 to 300 at ppm.4. The bonding wire for a semiconductor device according to claim 1 , wherein a total atomic percentage of In claim 1 , Ga claim 1 , and Cd in a layer extending in a depth direction of 0 to 10 nm from a wire surface is equal to or larger than twice the same in a layer extending in depth direction of 20 to 30 nm from the wire surface.5. The bonding wire for a semiconductor device according to claim 1 , wherein an average grain size in a section in a direction perpendicular to a wire axis is 0.2 to 3.5 μm.6. The bonding wire for a semiconductor device according to claim 1 , wherein in measurement results obtained by measuring crystal directions in a section of the bonding wire claim 1 , the section containing a wire axis and being parallel to the wire axis claim 1 , the ratio of a crystal direction <100> having an angular difference of 15 degrees or less from a longitudinal direction of the bonding wire is between 30% and 100% claim 1 , both inclusive claim 1 , in terms of an area percentage.7. The bonding wire for a semiconductor device according to claim 1 , ...

Semiconductor package

A semiconductor package includes a carrier, a package module and a second package body. The package module is disposed on the carrier and includes a first substrate, a first electronic element, a first conductive wire and a first package body. The first substrate has a first electrical surface facing the carrier and a second electrical surface opposite to the first electrical surface. The first electronic element is disposed on the first electrical surface. The first conductive wire connects the electronic element with the first electrical surface of the first substrate. The first package body encapsulates the first electrical surface, the first electronic element and the first solder wire. The second package body encapsulates the package module and a portion of the carrier.

BONDING WIRE FOR SEMICONDUCTOR DEVICE

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof. Containing an element that provides bonding reliability in a high-temperature environment improves the bonding reliability of the ball bonded part in high temperature. Furthermore, making an orientation proportion of a crystal orientation <100> angled at 15 degrees or less to a wire longitudinal direction among crystal orientations in the wire longitudinal direction 30% or more when measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, and making an average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire 0.9 to 1.5 μm provides a strength ratio of 1.6 or less. 1. A bonding wire for a semiconductor device , the bonding wire comprising:a Cu alloy core material; anda Pd coating layer formed on a surface of the Cu alloy core material, whereinwhen measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation <100> angled at 15 degrees or less to a wire longitudinal direction has a proportion of 30% or more among crystal orientations in the wire longitudinal direction,an average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire is 0.9 μm or more and 1.5 μm or less, andthe bonding wire contains one or more elements selected from Co, Rh, Ir, Ni, Pd, Pt, Ag, Au, Zn, Al, In, Sn, P, As, Sb, Bi, Se and Te.2. The bonding wire for a semiconductor device according to claim 1 , wherein a strength ratio defined by the following Equation (1) is 1.1 or more and 1.6 or less:{'br': None, 'Strength ratio=ultimate strength/0.2% offset yield strength.\u2003\u2003(1)'}3. The bonding wire for a semiconductor device according to claim 1 ...

CHIP ARRANGEMENTS

A chip arrangement including: a chip including a chip back side; a substrate including a surface with a plating; and a zinc-based solder alloy which attaches the chip back side to the plating on the surface of the substrate, the zinc-based solder alloy including, by weight, 1% to 30% aluminum, 0.5% to 20% germanium, and 0.5% to 20% gallium, wherein a balance of the zinc-based solder alloy is zinc. 1. A chip arrangement comprising:a chip comprising a chip back side;a substrate comprising a surface with a plating; anda zinc-based solder alloy which attaches the chip back side to the plating on the surface of the substrate, the zinc-based solder alloy comprising, by weight, 1% to 30% aluminum, 0.5% to 20% germanium, and 0.5% to 20% gallium, wherein a balance of the zinc-based solder alloy is zinc.2. The chip arrangement of claim 1 , wherein the zinc-based solder alloy comprises by weight 3% to 8% aluminum.3. The chip arrangement of claim 1 , wherein the zinc-based solder alloy comprises by weight 0.5% to 4% germanium.4. The chip arrangement of claim 1 , wherein the zinc-based solder alloy comprises by weight 0.5% to 4% gallium.5. The chip arrangement of claim 1 , wherein the zinc-based solder alloy further comprises at least one from the following group of materials: silver claim 1 , gold claim 1 , nickel claim 1 , platinum claim 1 , palladium claim 1 , vanadium claim 1 , molybdenum claim 1 , tin claim 1 , copper claim 1 , arsenic claim 1 , antimony claim 1 , niobium claim 1 , tantalum claim 1 , and/or any combination thereof claim 1 , by weight 0.001% to 10% of the zinc-based solder alloy.6. The chip arrangement of claim 1 , wherein the plating comprises at least one of nickel or nickel-phosphorous.7. The chip arrangement of claim 6 , wherein the substrate comprises one or more of copper claim 6 , nickel claim 6 , silver claim 6 , or ceramic.8. The chip arrangement of claim 7 , wherein the at least one of nickel or nickel-phosphorous in the plating provides a reduced ...

Via structures having tapered profiles for embedded interconnect bridge substrates

Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

Encapsulating a Bonded Wire with Low Profile Encapsulation

Encapsulating a bonded wire with low profile encapsulation includes applying encapsulation over a bonded wire that is connected to a die on a first end and to a circuit component on a second end and truncating a shape of the encapsulation to form a truncated shape. 1. A method for encapsulating a bonded wire with low profile encapsulation , comprising:applying an encapsulation material over a bonded wire, the bonded wire being connected to a die on a first end, and the bonded wire being connected to a circuit component on a second end; andcompressing the encapsulation material, using a stamp, from a deposited shape to a truncated shape.2. The method of claim 1 , wherein compressing the encapsulation material using the stamp includes actively heating the stamp while compressing the encapsulation material.3. The method of claim 2 , wherein the truncated shape comprises a top-hat profile.4. The method of claim 2 , further comprising:subsequent to compressing the encapsulation material using the stamp, removing the stamp to allow the encapsulation material to solidify.5. The method of claim 1 , wherein the stamp includes a distance sensor to maintain a height of the truncated shape.6. The method of claim 5 , wherein maintaining the height of the truncated shape is based on a distance between the underside of the stamp and a top side of a compound disposed over the die.7. A method for encapsulating a bonded wire with low profile encapsulation claim 5 , comprising:applying an encapsulation material over a bonded wire, the bonded wire being connected to a die on a first end, and the bonded wire being connected to a circuit component on a second end;heating a stamp to compress the encapsulation material from a deposited shape to a truncated shape; andcompressing the encapsulation material, using the heated stamp, from the deposited shape to the truncated shape, wherein the truncated shape reflects a geometry of an underside of the stamp.8. The method of claim 7 , wherein ...

PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES

Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites. 1. A method of forming a semiconductor assembly , comprising:forming a conductive pedestal at a first bond-site of a support member, wherein the pedestal has a surface spaced apart from the support member;attaching the support member to a die having a second bond-site;disposing an encapsulant adjacent to the pedestal;removing at least a portion of the encapsulant to at least partially expose the surface of the pedestal; andforming a redistribution structure connected to the surface of the pedestal and the first bond-site and having a third bond-site between the first and second bond-sites and spaced apart from the die.2. The method of wherein removing at least a portion of the encapsulant comprises forming a via through the encapsulant that terminates at the surface of the pedestal.3. The method of claim 2 , further comprising disposing a conductive member in the via and coupling the conductive member to the surface of the pedestal with the conductive member exposed for an electrical connection external to the assembly.4. A method of forming a stacked semiconductor assembly claim 2 , comprising:singulating a first semiconductor assembly having a first die and a first bond-site at a periphery of the first assembly, the first assembly having a first footprint;singulating a second semiconductor assembly along a singulation line, the second semiconductor assembly having a second ...

Semiconductor devices including cobalt alloys and fabrication methods thereof

A semiconductor device includes a substrate, a conductive wiring which comprises cobalt or copper and is electrically connected to the substrate, an insulating material which electrically isolates the conductive wiring from neighboring wiring, and a first barrier layer which comprises a first cobalt alloy and is disposed between the conductive wiring and the insulating material.

WAFER LEVEL PACKAGE STRUCTURE AND METHOD OF FORMING SAME

An embodiment is a package including a first package component. The first package component including a first die attached to a first side of a first interconnect structure, a molding material surrounding the first die, and a second interconnect structure over the molding material and the first die, a first side of the second interconnect structure coupled to the first die with first electrical connectors. The first package component further includes a plurality of through molding vias (TMVs) extending through the molding material, the plurality of TMVs coupling the first interconnect structure to the second interconnect structure, and a second die attached to a second side of the second interconnect structure with second electrical connectors, the second side of the second interconnect structure being opposite the first side of the second interconnect structure. 1. A method comprising:attaching a backside surface of a first die to a first side of a first interconnect structure;forming a first through via over the first side of the first interconnect structure, the first through via being coupled to the first interconnect structure;forming first electrical connectors on an active surface of the first die, the active surface being opposite the backside surface;encapsulating the first die and the first through via with a molding material;forming a second interconnect structure over the molding material, the first electrical connectors and the first through via, the first electrical connectors and the first through via being coupled to a first side of the second interconnect structure; andattaching a second die to a second side of the second interconnect structure using second electrical connectors, the second side of the second interconnect structure being opposite the first side of the second interconnect structure.2. The method of claim 1 , wherein the first die is a logic die claim 1 , and wherein the second die is a wide input/output (I/O) die.3. The method of ...

Stack type semiconductor package

A stack type semiconductor package includes a lower semiconductor package including a lower package substrate and at least one lower semiconductor chip disposed on the lower package substrate; an upper semiconductor package including an upper package substrate larger than the lower package substrate and at least one upper semiconductor chip disposed on the upper package substrate; an inter-package connector connecting an upper surface of the lower package substrate to a lower surface of the upper package substrate; and a filler filling in between the lower package substrate and the upper package substrate while substantially surrounding the inter-package connector.

Package-on-package assembly with wire bonds to encapsulation surface

A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.

BONDING WIRE FOR SEMICONDUCTOR DEVICE

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof. Containing an element that provides bonding reliability in a high-temperature environment improves the bonding reliability of the ball bonded part in high temperature. Furthermore, making an orientation proportion of a crystal orientation <100> angled at 15 degrees or less to a wire longitudinal direction among crystal orientations in the wire longitudinal direction 30% or more when measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, and making an average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire 0.9 to 1.5 μm provides a strength ratio of 1.6 or less. 1. A bonding wire for a semiconductor device , the bonding wire comprising:a Cu alloy core material; anda Pd coating layer formed on a surface of the Cu alloy core material, whereinwhen measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation <100> angled at 15 degrees or less to a wire axis direction has a proportion of 30% or more among crystal orientations in the wire axis direction,an average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire is 0.9 μm or more and 1.5 μm or less, andthe bonding wire contains one or more elements selected from Ga and Ge, and a concentration of the elements in total is 0.011 to 1.5% by mass relative to the entire wire.2. The bonding wire for a semiconductor device according to claim 1 , wherein a strength ratio defined by the following Equation (1) is 1.1 or more and 1.6 or less:{'br': None, 'Strength ratio=ultimate strength/0.2% offset yield strength. \u2003\u2003(1)'}3. The bonding wire for a semiconductor device ...

SEMICONDUCTOR DEVICE

A semiconductor device includes: a first chip to restrict current flow in a first direction through a current path; a second chip to restrict the current flow in a second direction opposite to the first direction, through the current path; a wiring having one end connected to the first chip and the other end connected to the second chip, and provided as a part of the current path by relaying the first chip and the second chip; a lead frame having a first lead arranged and fixed with the first chip and a second lead is arranged and fixed with the second chip; and molding resin sealing the first chip, the second chip, the wiring and the lead frame. The wiring is a shunt resistor having a resistive body. The lead frame further has a sense terminal to detect a voltage drop across the resistive body. 1. A semiconductor device connected to a current path through which a current flows bidirectionally and provided as a part of the current path , the semiconductor device comprising:a first chip that has a first switching element to restrict current flow in a first direction through the current path when the first switching element is turned off;a second chip that has a second switching element to restrict the current flow in a second direction, which is opposite to the first direction, through the current path when the second switching element is turned off;a wiring that has one end connected to the first chip and another end connected to the second chip, and that is provided as a part of the current path by relaying the first chip and the second chip;a lead frame that includes a first lead arranged and fixed with the first chip and a second lead arranged and fixed with the second chip, and that provides the current path; andmolding resin that integrally seals the first chip, the second chip, the wiring and the lead frame, wherein:the wiring is a shunt resistor that has a resistive body to detect the current flowing through the current path, and that is extended in an ...

Substrate-Less Stackable Package With Wire-Bond Interconnect

A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are unconvered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer. 1. An apparatus , comprising:conductive elements of a conductive layer on a bottom side of a package;wire bond wires coupled to and extending from first upper surface portions of the conductive elements;a microelectronic element coupled to second upper surface portions of the conductive elements through conductive contact structures;a wire bond wire of the wire bond wires interconnected for electrical conductivity to a conductive contact structure of the conductive contact structures by a conductive element of the conductive elements for a redistribution on the bottom side of the package; anda dielectric layer contacting the wire bond wires and side portions of the microelectronic element to define at least one dimension of the package, the conductive layer at least partially defining the bottom side of the package.2. The apparatus according to claim 1 , wherein the redistribution is configured to provide contacts of the package for interconnects for electrical conductivity with a microelectronic structure.3. The apparatus according to claim 1 , wherein the redistribution is a lower ...

Array Formed From A Multiplicity Of Electric Integrated Circuits, and Method For Production Thereof

A method for producing an array formed from a multiplicity of electric integrated circuits, said array being intended for separation and having a conductive connection to a central contact path for bond monitoring, said method comprising the following steps: 1. A method for producing an array formed from a multiplicity of electric integrated circuits , said array being intended for separation and having a conductive connection to a central contact path for bond monitoring , said method comprising the following steps:applying conductive tracks to the array, wherein the separation region is recessed from applying said tracks, andclosing the conductive connection to the central contact path by applying individual conductive connection portions, which extend between two contact paths which enclose the separation region and are arranged adjacent thereto, formed from inert material.2. The method as claimed in claim 1 , wherein conductive connection portions are provided as wire bridges.3. The method as claimed in claim 1 , wherein the inert material is formed from at least one material from the group comprising the elements gold claim 1 , palladium claim 1 , tantalum and nickel and also comprising the alloy containing predominantly at least one of the mentioned elements.4. A method for producing an electric integrated circuit claim 1 , wherein an array formed from a multiplicity of electric integrated circuits as claimed in is initially produced claim 1 , and the array is then subjected to a separation step claim 1 , in which the individual electric integrated circuits are detached from the array along the separation region by means of sawing or breaking.5. An array formed from a multiplicity of electric integrated circuits claim 1 , comprising a conductive connection claim 1 , extending over all integrated circuits of the array claim 1 , to a central contact path for bond monitoring claim 1 , wherein a separation region is provided in each case between adjacent ...

Encapsulating a Bonded Wire with Low Profile Encapsulation

Encapsulating a bonded wire with low profile encapsulation includes applying encapsulation over a bonded wire that is connected to a die on a first end and to a circuit component on a second end and truncating a shape of the encapsulation to form a truncated shape. 1. An apparatus for encapsulating a bonded wire with low profile encapsulation , comprising:a bonded wire connected to a die on a first end and to a circuit component on a second end; andan encapsulation material disposed over said bonded wire;wherein said encapsulation comprises a truncated shape.2. The apparatus of claim 1 , wherein said truncated shape is formed by compressing said encapsulation when said encapsulation comprised a deposited shape determined by a surface tension of said encapsulated.3. The apparatus of claim 1 , wherein said truncated shape is formed by wicking said encapsulation along an underside of a guide.4. The apparatus of claim 1 , wherein said truncated shape is formed by removing a portion of said encapsulation when said encapsulation comprised a deposited shape determined by a surface tension of said encapsulated.5. The apparatus of claim 1 , wherein said die comprises an inkjet nozzle.6. The apparatus of claim 1 , wherein said encapsulation is less than a hundred microns in height.7. The apparatus of claim 1 , wherein said bonded wire is incorporated into a print head.8. The apparatus of claim 1 , wherein said truncated shape comprises a top-hat profile.9. A method for encapsulating a bonded wire with low profile encapsulation claim 1 , comprising:applying encapsulation over a bonded wire that is connected to a die on a first end and to a circuit component on a second end; andtruncating a shape of said encapsulation to form a truncated shape.10. The method of claim 9 , wherein truncating said shape includes compressing said encapsulation with a stamp.11. The method of claim 10 , wherein compressing said encapsulation with a stamp includes actively heating said stamp while ...

SEMICONDUCTOR DEVICE AND INSPECTION DEVICE

A semiconductor device includes a pair of electrodes and a conductive connection member electrically bonded to the pair of electrodes At least a portion of a perimeter of a bonding surface of at least one of the pair of electrodes and the conductive connection member includes an electromigration reducing area 1. A semiconductor device comprising:a pair of electrodes; anda conductive connection member electrically bonded to the pair of electrodes, whereinat least a portion of a perimeter of a bonding surface of at least one of the pair of electrodes and the conductive connection member comprises an electromigration reducing area.2. The semiconductor device according to claim 1 , wherein the electromigration reducing area is an area of the perimeter of the bonding surface.3. The semiconductor device according to claim 1 , wherein the electromigration reducing area is an end area on an upstream side in a current direction of the perimeter of the bonding surface of the conductive connection member.4. The semiconductor device according to claim 1 , wherein the electromigration reducing area is an area of at least a portion of the perimeter of the bonding surface of at least either of the pair of electrodes and the conductive connection member.5. The semiconductor device according to claim 1 , wherein the electromigration reducing area is an additive containing area containing an additive for reducing diffusion of the electromigration or reducing electrical conductivity of a base material of the bonding surface.6. The semiconductor device according to claim 5 , wherein a content of the additive contained in the electromigration reducing area is 0.1% or greater by mass and 20.0% or lower by mass.7. The semiconductor device according to claim 5 , wherein the additive is at least one type selected from a group comprising Al claim 5 , Cu claim 5 , Si claim 5 , Ni claim 5 , Cr claim 5 , Mg claim 5 , Au claim 5 , Ag claim 5 , Ta claim 5 , Fe claim 5 , a molybdenum-tungsten ...

PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES

Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites. 1. A method of forming a semiconductor assembly , comprising:forming a conductive pedestal at a first bond-site of a support member, wherein the pedestal has a surface spaced apart from the support member;attaching the support member to a die having a second bond-site;disposing an encapsulant adjacent to the pedestal;removing at least a portion of the encapsulant to at least partially expose the surface of the pedestal; andforming a redistribution structure connected to the surface of the pedestal and the first bond-site and having a third bond-site between the first and second bond-sites and spaced apart from the die.2. The method of wherein removing at least a portion of the encapsulant comprises forming a via through the encapsulant that terminates at the surface of the pedestal.3. The method of claim 2 , further comprising disposing a conductive member in the via and coupling the conductive member to the surface of the pedestal with the conductive member exposed for an electrical connection external to the assembly.4. A method of forming a stacked semiconductor assembly claim 2 , comprising:singulating a first semiconductor assembly having a first die and a first bond-site at a periphery of the first assembly, the first assembly having a first footprint;singulating a second semiconductor assembly along a singulation line, the second semiconductor assembly having a second ...

BONDING WIRE FOR SEMICONDUCTOR DEVICES

Provided is a bonding wire capable of reducing the occurrence of defective loops. The bonding wire includes: a core material which contains more than 50 mol % of a metal M; an intermediate layer which is formed over the surface of the core material and made of Ni, Pd, the metal M, and unavoidable impurities, and in which the concentration of the Ni is 15 to 80 mol %; and a coating layer formed over the intermediate layer and made of Ni, Pd and unavoidable impurities. The concentration of the Pd in the coating layer is 50 to 100 mol %. The metal M is Cu or Ag, and the concentration of Ni in the coating layer is lower than the concentration of Ni in the intermediate layer. 1. A bonding wire for a semiconductor device comprising:a core material containing more than 50 mol % of a metal M;an intermediate layer formed over a surface of the core material and made of Ni, Pd, the metal M, and unavoidable impurities, concentration of the Ni being 15 to 80 mol %; anda coating layer formed over the intermediate layer and made of Ni, Pd and unavoidable impurities, the concentration of the Pd being 50 to 100 mol %,wherein the metal M is Cu or Ag, and the concentration of the Ni in the coating layer is lower than the concentration of the Ni in the intermediate layer.2. The bonding wire according to claim 1 , wherein the thickness of the intermediate layer is 8 to 80 nm.3. The bonding wire according to claim 1 , whereinthe coating layer further contains Au, and the bonding wire further comprises a surface layer formed over the coating layer and made of an alloy containing Au and Pd, the concentration of the Au being 10 to 70 mol %, the sum total concentration of the Au and the Pd being 80 mol % or more,wherein the concentration of the Au in the coating layer is lower than the concentration of the Au in the surface layer.4. The bonding wire according to claim 3 , wherein the total thickness of the surface layer claim 3 , the coating layer claim 3 , and the intermediate layer is 25 ...

Flexible microelectronic systems and methods of fabricating the same

Microelectronic systems encapsulated in a stretchable/flexible material, which is skin/bio-compatible and able to withstand environmental conditions. In one embodiment of the present description, the microelectronic system includes a microelectronic device that is substantially encapsulated in a non-permeable encapsulant, such as, butyl rubbers, ethylene propylene rubbers, fluoropolymer elastomers, or combinations thereof. In another embodiment, the microelectronic system includes a microelectronic device that is substantially encapsulated in a permeable encapsulant, such as polydimethylsiloxane, wherein a non-permeable encapsulant substantially encapsulates the permeable encapsulant.

CHIP ARRANGEMENTS

A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer. 1. A chip arrangement comprising:a chip comprising a chip back side;a back side metallization on the chip back side, the back side metallization comprising a plurality of layers;a substrate comprising a surface with a metal layer;a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc;wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate.2. The chip arrangement of claim 1 , wherein the zinc-based solder alloy is represented by the chemical formula ZnAlGaMg.3. The chip arrangement of claim 1 , wherein the zinc-based solder alloy is represented by the chemical formula ZnAlGaMg.4. The chip arrangement of claim 1 , wherein the substrate is formed by a material selected from a group of materials consisting of:lead;copper;nickel;silver; anda ceramic.5. The chip arrangement of claim 1 , wherein the metal layer comprises at least one of: silver claim 1 , gold claim 1 , nickel claim 1 , platinum ...

COPPER ALLOY BONDING WIRE FOR SEMICONDUCTOR DEVICES

In a copper alloy bonding wire for semiconductor devices, the bonding longevity of a ball bonded part under high-temperature and high-humidity environments is improved. The copper alloy bonding wire for semiconductor devices includes in total 0.03% by mass or more to 3% by mass or less of at least one or more kinds of elements selected from Ni, Zn, Ga, Ge, Rh, In, Ir, and Pt (first element), with the balance Cu and inevitable impurities. The inclusion of a predetermined amount of the first element suppresses production of an intermetallic compound susceptible to corrosion under high-temperature and high-humidity environments at the wire bonding interface and improves the bonding longevity of a ball bonded part. 1. A copper alloy bonding wire for semiconductor devices , comprising in total 0.03% by mass or more to 3% by mass or less of at least one or more kinds of elements selected from Ni , Zn , Ga , Ge , In , and Ir , with the balance comprising Cu and inevitable impurities , wherein the copper alloy bonding wire is bare Cu alloy wire.3. The copper alloy bonding wire for semiconductor devices according to claim 1 , wherein an average film thickness of copper oxide on a surface of the wire is in a range of 0.0005 μm or more and 0.02 μm or less.4. The copper alloy bonding wire for semiconductor devices according to claim 1 , wherein the copper alloy bonding wire further comprises 0.0001% by mass or more and 0.050% by mass or less of each of at least one or more kinds of elements selected from Ti claim 1 , B claim 1 , Ca claim 1 , La claim 1 , As claim 1 , Te claim 1 , and Se claim 1 , with respect to the entire wire.5. The copper alloy bonding wire for semiconductor devices according to claim 1 , wherein the copper alloy bonding wire further comprises in total 0.0005% by mass or more and 0.5% by mass or less of at least one or more kinds of elements selected from Ag and Au claim 1 , with respect to the entire wire.6. The copper alloy bonding wire for semiconductor ...

BONDING WIRE FOR SEMICONDUCTOR DEVICE

The present invention provides a bonding wire for a semiconductor device suitable for cutting-edge high-density LSIs and on-vehicle LSIs by improving the formation rate of Cu—Al IMC in ball bonds. A bonding wire for a semiconductor device contains Pt of 0.1 mass % to 1.3 mass %, at least one dopant selected from a first dopant group consisting of In, Ga, and Ge, for a total of 0.05 mass % to 1.25 mass %, and a balance being made up of Cu and incidental impurities. 1. A bonding wire for a semiconductor device containing Pt of 0.1 mass % to 1.3 mass % , at least one dopant selected from a first dopant group consisting of In , Ga , and Ge , for a total of 0.05 mass % to 1.25 mass % , and a balance being made up of Cu and incidental impurities.2. The bonding wire for a semiconductor device according to claim 1 , further containing at least one dopant selected from a second dopant group of B claim 1 , P claim 1 , Ca claim 1 , La claim 1 , and Ce claim 1 , for a total of 0.0005 mass % to 0.0100 mass %.3. The bonding wire for a semiconductor device according to claim 1 , wherein a crystal orientation in a longitudinal section of the bonding wire is such that an abundance ratio of a crystal orientation <100> having an angular difference of 15 degrees or less from a longitudinal direction of the bonding wire is from 50% to 100% in area percentage.4. The bonding wire for a semiconductor device according to claim 1 , wherein breaking elongation in a tensile test of the bonding wire is 8% to 15.5%.5. The bonding wire for a semiconductor device according to claim 1 , further containing at least one element selected from a third dopant group of Au claim 1 , Pd claim 1 , and Ni claim 1 , for a total of 0.0005 mass % to 1.0 mass %. The present invention relates to a bonding wire for a semiconductor device used to connect electrodes on semiconductor devices with wiring such as external leads of a circuit wiring board.Currently, as bonding wires for a semiconductor device ( ...

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer. 1. A method for forming a microelectronic package , comprising:obtaining a substrate having first contacts on an upper surface thereof;attaching a microelectronic die having a lower surface to face the upper surface of the substrate, the microelectronic die having second contacts on an upper surface of the microelectronic die;bonding wire bonds to the first contacts including forming bases of the wire bonds during the bonding, the wire bonds having edge surfaces between the bases and corresponding end surfaces;wherein a first portion of the wire bonds is interconnected between a first portion of the first contacts and the second contacts;wherein the end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die;forming a dielectric layer above the upper surface of the substrate and between the wire bonds; andbending uppermost portions of the second portion of the wire bonds over to be parallel with an upper surface of the dielectric layer.2. The method according to claim 1 , wherein the uppermost portions have corresponding sections of the ...

BONDING WIRE FOR SEMICONDUCTOR DEVICES

The present invention has as its object the provision of a bonding wire for semiconductor devices mainly comprised of Ag, in which bonding wire for semiconductor devices, the bond reliability demanded for high density mounting is secured and simultaneously a sufficient, stable bond strength is realized at a ball bond, no neck damage occurs even in a low loop, the leaning characteristic is excellent, and the FAB shape is excellent. To solve this problem, the bonding wire for semiconductor devices according to the present invention contains one or more of Be, B, P, Ca, Y, La, and Ce in a total of 0.031 at % to obtain a 0.180 at %, further contains one or more of In, Ga, and Cd in a total of 0.05 at % to 5.00 at %, and has a balance of Ag and unavoidable impurities. Due to this, it is possible to obtain a bonding wire for semiconductor devices sufficiently forming an intermetallic compound layer at a ball bond interface to secure the bond strength of the ball bond, not causing neck damage even in a low loop, having a good leaning characteristic, and having a good FAB shape. 17-. (canceled)8. Bonding wire for semiconductor devices containing either P of 0.060 at % to 0.180 at % or one or more of Be , B , Ca , Y , La , and Ce , and P in a total of 0.060 at % to 0.180 at % , further containing one or more of In , Ga , and Cd in a total of 0.05 at % to 5.00 at % , and having a balance of Ag and unavoidable impurities.9. The bonding wire for semiconductor devices according to further containing one or more of Ni claim 8 , Cu claim 8 , Rh claim 8 , Pd claim 8 , Pt claim 8 , and Au in a total of 0.01 at % to 5.00 at %.10. The bonding wire for semiconductor devices according to wherein when defining the ratio of the total of the number of atoms of In claim 8 , Ga claim 8 , and Cd with respect to the number of atoms of the metal elements as the second element atomic ratio claim 8 , the second element atomic ratio at a region from the wire surface to 1 nm from the wire surface ...

SEMICONDUCTOR DEVICES INCLUDING COBALT ALLOYS AND FABRICATION METHODS THEREOF

A semiconductor device includes a substrate, a conductive wiring which comprises cobalt or copper and is electrically connected to the substrate, an insulating material which electrically isolates the conductive wiring from neighboring wiring, and a first barrier layer which comprises a first cobalt alloy and is disposed between the conductive wiring and the insulating material. 1. A planar transistor comprising a semiconductor device and including a source contact and a drain contact ,wherein the semiconductor device comprises:a substrate;a conductive wiring which comprises cobalt and is electrically connected to the substrate;an insulating material which electrically isolates the conductive wiring from neighboring wiring; anda first barrier layer which comprises a first cobalt alloy and is disposed between the conductive wiring and the insulating material, andwherein the source contact and the drain contact each comprise the conductive wiring and the first barrier layer of the semiconductor device.2. A 3-D V-NAND memory device comprising a semiconductor device and includinga selection gate,a word line staircase contact, anda source line contact,wherein the semiconductor device comprises:a substrate;a conductive wiring which comprises cobalt and is electrically connected to the substrate;an insulating material which electrically isolates the conductive wiring from neighboring wiring; anda first barrier layer which comprises a first cobalt alloy and is disposed between the conductive wiring and the insulating material, andwherein the selection gate, word line staircase contact, and source line contact each comprise the conductive wiring and the first barrier layer of the semiconductor device.3. A method of forming a semiconductor metallization interconnect for a semiconductor device , comprising:forming at least one cobalt alloy with a cobalt content ranging from 30% to 99%; anddepositing the at least one cobalt alloy onto source and drain regions after Local-Inter- ...

BONDING WIRE FOR SEMICONDUCTOR DEVICE

Provided is a Pd coated Cu bonding wire for a semiconductor device capable of sufficiently obtaining bonding reliability of a ball bonded portion in a high temperature environment of 175° C. or more, even when the content of sulfur in the mold resin used in the semiconductor device package increases. 1. A bonding wire for a semiconductor device , the bonding wire comprising: a Cu alloy core material; and a Pd coating layer formed on a surface of the Cu alloy core material ,wherein the bonding wire contains at least one of one or more elements selected from Ni, Rh and Ir (hereinafter referred to as “first alloy element group”), and Pd: 0.05% by mass or more, and the total content of the first alloy element group and Pd is 0.03 to 2% by mass when the content of the first alloy element group is evaluated as the content in the bonding wire, and the content of Pd is evaluated in terms of the content in the bonding wire based on the content of Pd in the Cu alloy core material; andwherein the bonding wire contains 0.002 to 3% by mass in total of one or more elements selected from Li, Sb, Fe, Cr, Co, Zn, Ca, Mg, Pt, Sc and Y; the contents of Ca and Mg in the bonding wire are 0.011% by mass or more respectively when Ca or Mg is contained; the total content of the first alloy element group and Zn in the bonding wire is 2.1% by mass or more when Zn is contained.2. The bonding wire for a semiconductor device according to claim 1 , wherein a thickness of the Pd coating layer is 0.015 to 0.150 μm.3. The bonding wire for a semiconductor device according to claim 1 , further comprising an alloy skin layer containing Au and Pd on the Pd coating layer.4. The bonding wire for a semiconductor device according to claim 3 , wherein a thickness of the alloy skin layer containing Au and Pd is 0.050 μm or less.5. The bonding wire for a semiconductor device according to claim 1 , wherein the bonding wire further contains 0.03 to 3% by mass in total of one or more elements selected from Al ...

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer. 120-. (canceled)21. A method comprising:providing a substrate having a surface having electrically conductive elements;disposing at least one microelectronic element overlying the substrate surface;joining metal wires to the electrically conductive elements;drawing the metal wires out of a bonding tool so that portions of the metal wires extend upward from the substrate, wherein a portion of a metal wire of the metal wires is bent;forming a dielectric encapsulation layer above the substrate surface, wherein the encapsulation layer covers the metal wires and the metal wires are spaced from one another by the encapsulation layer;removing a portion of the encapsulation layer to expose the portion of the metal wire, the removing including forming one or more cavities in which the portion of the metal wire is exposed;providing an electrically conductive material on the dielectric encapsulation layer in electrical connection with the portion of the metal wire.22. The method of claim 21 , wherein the metal wires at least partially surround the at least one microelectronic element.23. The ...

Apparatus with a multi-layer coating and method of forming the same

In some embodiments, a printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further comprises a plurality of conductive tracks attached to at least one surface of the substrate. The PCB further comprises a multi-layer coating deposited on the at least one surface of the substrate. The multi-layer coating (i) covers at least a portion of the plurality of conductive tracks and (ii) comprises at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical component connected by a solder joint to at least one conductive track, wherein the solder joint is soldered through the multi-layer coating such that the solder joint abuts the multi-layer coating.

Halogen-hydrocarbon polymer coating

FIELD: chemistry. SUBSTANCE: invention relates to polymer coatings, namely, to a halogen-hydrocarbon polymer coating for electric devices. A printed circuit board (PCB) includes a substrate, including an insulation material. The PCB additionally includes multitudes of electroconductive printing paths, connected to at least one substrate surface. The PCB additionally includes a multi-layered coating, precipitated on at least one substrate surface. The multilayered coating covers at least a part of a multitude of the electroconductive paths and includes at least one layer of the halogen-hydrocarbon polymer. The PCB additionally includes at least one electric component, connected by a solder connection to at least one electroconductive printing path, with the solder connection being soldered through the multilayered coating in such a way that the connection adjoins the multilayered coating. EFFECT: prevention of oxidation or corrosion of metal surfaces, capable of preventing the formation of strong solder connections or capable of reducing a service term of the said connections. 39 cl, 18 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (51) МПК H05K 1/18 H05K 3/28 H05K 3/34 C09D 4/00 C09D 185/00 C09K 15/32 (13) 2 533 162 C2 (2006.01) (2006.01) (2006.01) (2006.01) (2006.01) (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ (21)(22) Заявка: ИЗОБРЕТЕНИЯ К ПАТЕНТУ 2011110260/07, 11.08.2009 (24) Дата начала отсчета срока действия патента: 11.08.2009 Приоритет(ы): (30) Конвенционный приоритет: (72) Автор(ы): ХАМФРИЗ Марк Робсон (GB), ФЕРДИНАНДИ Фрэнк (GB), СМИТ Родни Эдвард (GB) 18.08.2008 GB 0815094.8; 18.08.2008 GB 0815095.5; 18.08.2008 GB 0815096.3 R U (73) Патентообладатель(и): СЕМБЛАНТ ЛИМИТЕД (GB) (43) Дата публикации заявки: 20.10.2012 Бюл. № 29 (56) Список документов, цитированных в отчете о поиске: US 3931454 A, 06.01.1976. US 2004/ (85) Дата начала рассмотрения заявки PCT на национальной фазе: 18.03.2011 C 2 C 2 0026775 A1, 12.02.2004. US 4693799 A ...

Printed board and method for production thereof

FIELD: electrical engineering.SUBSTANCE: invention relates to a halocarbon polymer coating for electrical devices. It is achieved by the fact that the printed circuit board (PCB) includes a substrate including insulating material, and additionally includes multiple electroconductive printed paths connected to at least one surface of the substrate. PP further includes a multilayer coating deposited on at least one surface of the substrate. Multilayer coating (i) covers at least part of multiple electroconductive printed paths and (ii) includes at least one layer of halocarbon polymer. PP further includes at least one electrical component, connected by soldered joint to at least one electroconductive printed path, soldered connection is soldered through multilayer coating so that soldered joint is adjacent to multilayer coating.EFFECT: technical result is protection from environmental conditions.21 cl, 16 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 2 685 692 C2 (51) МПК H05K 1/18 (2006.01) H05K 3/28 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ (52) СПК H05K 1/0353 (2019.02); H05K 3/282 (2019.02) (21) (22) Заявка: 2014121727, 28.05.2014 (24) Дата начала отсчета срока действия патента: 11.08.2009 (73) Патентообладатель(и): СЕМБЛАНТ ЛИМИТЕД (GB) 23.04.2019 18.08.2008 GB 0815094.8; 18.08.2008 GB 0815095.5; 18.08.2008 GB 0815096.3 Номер и дата приоритета первоначальной заявки, из которой данная заявка выделена: 2011110260 18.08.2008 (56) Список документов, цитированных в отчете о поиске: US 2004/0026775 A1, 12.02.2004. US 391453 A, 06.01.1976. US 2008/0176096 A1, 24.07.2008. RU 2032286 C1, 27.03.1995. (43) Дата публикации заявки: 10.12.2015 Бюл. № 2 6 8 5 6 9 2 Приоритет(ы): (30) Конвенционный приоритет: R U Дата регистрации: (72) Автор(ы): ХАМФРИЗ Марк Робсон (GB), ФЕРДИНАНДИ Фрэнк (GB), СМИТ Родни Эдвард (GB) 34 C 2 R U 2 6 8 5 6 9 2 C 2 (45) Опубликовано: 23.04.2019 Бюл. № 12 Адрес для переписки: 129090, Москва, ул. Б ...

Package-on-package assembly with wire bonds to encapsulation surface

PURPOSE: A package-on-package assembly with wire bonds on an encapsulation surface of encapsulation layer is provided to easily form a monolithic layer on a substrate by depositing a dielectric material on a first substrate and hardening a deposited dielectric material. CONSTITUTION: A substrate(12) has a first side(14) and a second side(16). The substrate is divided into a first area(18) and a second area(20). A microelectronic element(22) is mounted on a first side of the substrate in the first area. A conductive element(28) includes a contact or a pad(30) exposed to the first side of the substrate. A microelectronic assembly(10) includes a plurality of wire bonds(32) bonded on the pad having the conductive element.

Halo-hydrocarbon polymer coating

일부 구체예에서, 인쇄 회로 보드(PCB)는 절연재를 포함하는 기판을 포함한다. 상기 PCB는 기판의 하나 이상의 표면에 결합된 복수의 도전성 트랙을 더 포함한다. 상기 PCB는 기판의 하나 이상의 표면상에 증착된 다중층 코팅을 더 포함한다. 상기 다중층 코팅은 (i) 복수의 도전성 트랙의 적어도 일부를 커버하고, (ii) 할로-하이드로카본 폴리머로 형성된 하나 이상의 층을 포함한다. 상기 PCB는 하나 이상의 도전성 트랙에 솔더 접합에 의해 연결된 하나 이상의 전기 소자를 더 포함하며, 상기 솔더 접합은 상기 솔더 접합이 상기 다중층 코팅에 인접하도록 상기 다중층을 통해 솔더된다. In some embodiments, the printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further includes a plurality of conductive tracks coupled to at least one surface of the substrate. The PCB further comprises a multilayer coating deposited on at least one surface of the substrate. The multilayer coating includes (i) at least a portion of a plurality of conductive tracks, and (ii) at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical element connected by solder bonding to the at least one conductive track, wherein the solder joint is soldered through the multilayer so that the solder joint is adjacent the multilayer coating.

Structure and Manufacturing Method of Semiconductor Package

본 발명은 반도체 패키지의 구조 및 제조방법에 관한 것으로, 반도체패키지의 크기를 기능 저하 없이 반도체칩의 크기로 소형화하고, 고다핀을 실현하면서 경박단소화 한 새로운 형태의 칩 사이즈 패키지(Chip Size Package)로서, 반도체칩의 상면 외측으로 본드패드가 배열되는 타입이나, 반도체칩의 중앙부로 본드패드가 배열되는 타입의 모든 반도체칩을 에리어 어레이(Area Array) 형태로 반도체패키지의 입출력단자를 형성하여 전자제품에 탑재시 그 탑재되는 면적을 최소화하여 제품의 소형화를 가져올 수 있는 것이다.

Bonding wire for semiconductor device

本发明提供能够满足在高密度安装中要求的接合可靠性、弹回性能、芯片损伤性能的接合线。一种接合线，其特征在于，包含总计为0.05～5原子％的In、Ga、Cd中的1种以上，其余量包含Ag和不可避免的杂质。

Semiconductor package

본 개시의 예시적 실시예에 따른 반도체 패키지는, 제1 면 및 상기 제1 면에 대향하는 제2 면을 갖고, 상기 제1 면과 인접한 부분에서 홈을 갖는 패키지 기판으로서, 배선 패턴; 상기 배선 패턴을 둘러싸는 절연 층; 상기 홈의 저면 상에 있고, 상기 배선 패턴과 연결된 칩 연결 패드; 및 상기 제1 면 상에 있고, 상기 배선 패턴과 연결된 와이어 연결 패드;를 포함하는 상기 패키지 기판; 상기 패키지 기판의 상기 홈 상에 있고, 상기 칩 연결 패드와 연결되는 1 칩 패드를 갖는 제1 반도체 칩; 상기 패키지 기판 상에 있고, 상기 제1 반도체 칩을 둘러싸는 제1 접착 층; 및 상기 제1 접착 층 상에 있고, 상기 와이어 연결 패드와 도전성 와이어를 통해 와이어 연결 패드와 연결되는 제2 반도체 칩;를 포함한다.

Method for package-on-package assembly with wire bonds to encapsulation surface

A microelectronic assembly includes a substrate having a first and second opposed surfaces. A microelectronic element overlies the first surface and first electrically conductive elements can be exposed at at least one of the first surface or second surfaces. Some of the first conductive elements are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the substrate and the bases, each wire bond defining an edge surface extending between the base and the end surface. An encapsulation layer can extend from the first surface and fill spaces between the wire bonds, such that the wire bonds can be separated by the encapsulation layer. Unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer.

Substrate-less stackable package with wire-bond interconnect

A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are uncovered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer.

Structure for microelectronic packaging with bond elements to encapsulation surface

A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element.

An apparatus and method for laser welding of ribbons for electrical connections

An apparatus and method are provided for using laser energy in an automated bonding machine to effect laser welding of ribbons and other connectors, particularly conductive ribbons in microelectronic circuits. The apparatus and method allow bonding and connection of microelectronic circuits with discrete heating avoiding heat damage to peripheral microelectronic components. The apparatus and method also allow bonding of flexible materials and low-resistance materials, and are less dependant on substrate and terminal stability in comparison to existing bonding methods. The bonding method leads to decreased apparatus wear in comparison to existing bonding methods.

Bonding wire for semiconductor device

Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures

Contact structures exhibiting resilience or compliance for a variety of electronic components are formed by bonding a free end of a wire to a substrate, configuring the wire into a wire stem having a springable shape, severing the wire stem, and overcoating the wire stem with at least one layer of a material chosen primarily for its structural (resiliency, compliance) characteristics.

A kind of corrosion-resistant method of modifying suitable for copper wire

本发明公开了一种适用于铜丝的耐腐蚀改性方法，该改性方法先从原料铜中提取高纯铜，清洗、烘干后与镍、镓、磷钨酸钾、纳米氮化钽共同置于熔炼装置中熔化，经在线除气、脱氧、搅拌，用牵引机组离合式真空上引无氧合金铜杆，随后采用连续挤压机组生产合金铜带坯料，随后经粗拔、镀钯、精拔得到镀钯合金铜丝。利用该方法制备而成的镀钯合金铜丝具有良好的耐腐蚀性能，并且成本较低，能够满足行业的要求，具有良好的应用前景。同时，本发明还公开了该方法所制得的铜丝在集成电路中的应用。

Semiconductor package apparatus

본 발명은 반도체 패키지 장치에 관한 것으로서, 제 1 반도체 칩, 제 1 기판, 제 1 단자 및 제 1 신호 전달 매체를 포함하는 제 1 반도체 패키지; 제 2 반도체 칩, 제 2 기판, 제 2 단자 및 2 신호 전달 매체를 포함하는 제 2 반도체 패키지; 상기 제 1 단자와 제 2 단자 사이에 설치되는 적어도 하나의 패키지 연결 솔더볼; 및 상기 패키지 연결 솔더볼의 형상을 안내하는 제 1 안내면이 형성되는 제 1 솔더볼 가이드 부재;를 포함할 수 있다. A semiconductor package device comprising: a first semiconductor package including a first semiconductor chip, a first substrate, a first terminal, and a first signal transmission medium; A second semiconductor package including a second semiconductor chip, a second substrate, a second terminal, and a second signal transmission medium; At least one package-connecting solder ball installed between the first terminal and the second terminal; And a first solder ball guide member having a first guide surface for guiding the shape of the package connection solder ball.

Semiconductor device and preparation there of and bonding wire used there of

내용 없음. No content.

Electronic device having metallurgies containing copper-semiconductor compounds

본 발명의 실리콘 및 게르마늄 함유 재료는 전자 장치에서 도체의 표면에 사용된다. 본 발명에 의하면, 이들 표면에 땜납이 용제없이 접합될 수 있고 와이어가 와이어 접합될 수 있다. 이들 재료는 집적 회로 칩을 패키징하기 위한 리드프레임용 표면 피막으로 사용된다. 이들 재료는 도체 표면상으로 전사(傳寫)되거나, 무전해 또는 전기분해 증착될 수 있다. The silicon and germanium containing materials of the present invention are used on the surface of conductors in electronic devices. According to the present invention, solder can be bonded to these surfaces without solvent and wires can be wire bonded. These materials are used as surface coatings for leadframes for packaging integrated circuit chips. These materials may be transferred onto the conductor surface, or may be electrolessly or electrolytically deposited.

Semiconductor device with bonding pad

本发明提供一种具有接合垫的半导体装置。该半导体装置包括：一第一基板，包含一元件区域以及一接合区域，其中该第一基板具有一上表面以及一底部表面；一半导体元件，设置于该元件区域的该第一基板的上表面上；一第一金属间介电层，至少形成于该接合区域的该第一基板的上表面；一最底层的金属图案，设置于该第一金属间介电层之中，其中该最底层的金属图案作为接合垫；以及一开口，穿过该第一基板，且露出该最底层的金属图案。通过本发明，可以获得更佳的CMOS图像传感器的接合垫以及接合导线之间接合品质，例如提升两者的黏合度，借此，可防止接合导线剥落。

Electronic component of a high frequency current suppression type and bonding wire for the same

고주파에서 이용될 때에도 전자기 간섭이 발생하는 것을 방지하기 위하여 고주파 전류를 와전하게 억제할 수 있는 고주파 전류 억제형 전자 부품을 제공하기 위하여, 그리고 상기 전자 부품용 접합 와이어를 제공하기 위하여, 반도체 집적 회로 소자(IC)(17)는 고주파에서 이용시 고속으로 동작하고 소정 수의 단자(19)에는 단자들 자체를 통과하는 고주파 전류를 감쇠시키는 고주파 전류 억제기(21)가 제공된다. 이러한 고주파 전류 억제기(21)는 03 내지 20μm 두께를 가진 박막 필름 자기 물질이며 각각의 단자(19)의 전체 표면상에 배치되는데, 상기 단자의 전체 표면은 반도체 집적 회로 소자(IC)(17)를 장착하기 위한 인쇄회로기판(23)상에 장착될 장착 부분 및 인쇄회로기판(23)상에 배치된 도전성 패턴에 대한 접속 부분을 포함하는 에지를 커버한다. IC(17)를 인쇄회로기판(23)에 장착할 때 땜납(27)에 의하여 상부 단부가 도전성 패턴(17)과 연결될 때, 상기 장착 부분 근처는 몇십 MHz 이하인 사용 주파수 대역에서 전도성을 가진다.

Electronic component with cavity housing, in particular high-frequency power module

Die Erfindung betrifft ein elektronisches Bauteil (1) mit Hohlraumgehäuse (3), das aus drei Modulen aufgebaut ist, einem 1. Modul (8), das einen nach oben und unten offenen Gehäuserahmen (6) aufweist mit horizontal angeordneten Flachleitern (5), einem 2. Modul (9), das die Chipinsel (4) als Wärmesenke mit mindestens einem Halbleiterchip (2) aufweist, wobei das 2. Modul (9) den Boden des Hohlraumgehäuses (3) bildet und einem 3. Modul (10), das den Gehäusedeckel (7) aufweist. The invention relates to an electronic component (1) with a cavity housing (3), which is constructed from three modules, a first module (8) which has a housing frame (6) which is open at the top and bottom and has horizontally arranged flat conductors (5), a second module (9) which has the chip island (4) as a heat sink with at least one semiconductor chip (2), the second module (9) forming the bottom of the cavity housing (3) and a third module (10), which has the housing cover (7).

Semiconductor package and method for manufacturing the same

A semiconductor package and a method for manufacturing the same are provided to perform a wire bonding process on a fine finger by bonding a wire at an upper surface and a lateral surface of the finger. A substrate has a finger(111). One or more semiconductor chip having a chip pad is laminated on the substrate. A wire(160) is formed to connect electrically the finger and the chip pad to each other. One end of the wire is bonded with the finger at an upper surface of the finger and a lateral surface of the finger. A protrusion(162) is formed at one end of the wire. In a vertical projection of the substrate, a maximum width of an upper surface of the finger is smaller than a width of the protrusion. In the vertical projection of the substrate, the upper surface of the finger is positioned within a lower surface of the finger.

Bond wire for semiconductor device

Bonddraht für eine Halbleitervorrichtung, wobei der Bonddraht aufweist: ein Cu-Legierungskernmaterial; und eine Pd-Überzugschicht, die auf einer Oberfläche des Cu-Legierungskernmaterials ausgebildet ist, wobei der Bonddraht wenigstens ein Element enthält, das aus Ni, Zn, Rh, In, Ir und Pt ausgewählt ist, eine Konzentration der Elemente insgesamt relativ zu dem Gesamtdraht 0,03 Massen-% oder mehr und 2 Massen-% oder weniger beträgt, wenn Kristallorientierungen auf einem Querschnitt des Kernmaterials in einer Richtung senkrecht zu einer Drahtachse des Bonddrahts gemessen werden, eine Kristallorientierung <100> mit einem Winkel von 15 Grad oder weniger zu einer Drahtachsenrichtung einen Anteil von 50% oder mehr an Kristallorientierungen in der Drahtachsenrichtung hat, und eine mittlere Kristallkorngröße in dem Querschnitt des Kernmaterials in der Richtung senkrecht zu der Drahtachse des Bonddrahts 0,9 µm oder mehr und 1,3 µm oder weniger beträgt. Bond wire for a semiconductor device, the bond wire comprising: a Cu alloy core material; and a Pd plating layer formed on a surface of the Cu alloy core material, wherein the bonding wire contains at least one element selected from Ni, Zn, Rh, In, Ir and Pt, a total concentration of the elements relative to the total wire is 0.03 mass% or more and 2 mass% or less, when crystal orientations are measured on a cross section of the core material in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation <100> at an angle of 15 degrees or less to a wire axis direction accounts for 50% or more of crystal orientations in the wire axis direction, and an average crystal grain size in the cross section of the core material in the direction perpendicular to the wire axis of the bonding wire is 0.9 µm or more and 1.3 µm or less.

LAMINATED CONDUCTIVE TAPE FOR CONNECTION TO AN INPUT / OUTPUT INTERFACE

A DEVICE AND METHOD FOR LASER WELDING OF TAPES FOR ELECTRICAL CONNECTIONS

Metal base circuit board and its production process

A metal base circuit board is provided. The circuit board includes circuits provided on a metal plate via an insulating layer. A dent portion is provided on one side of the metal plate in such a state that the circumferential portion thereof is not opened, and insulating layers made of the same material are provided both on the space of the dent portion and on the metal plate on which the dent portion is present. The maximum depth of the dent portion may range from 10% to 50% of the thickness of the metal plate. The size of the dent portion as viewed from the vertical direction may be at least 50% of the area of the metal plate, and in a shape of the dent portion as viewed from the vertical direction, the corner may have a curvature radius of at least 2.5mm.

Electric apparatus and preparation thereof and bonding wire used thereto and preparation thereof

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Package-on-package assembly with wire bond to encapsulation surface

一种微电子组件(210)，包括具有第一表面(214)和远离第一表面(214)的第二表面(216)的衬底(212)。微电子元件(222)覆盖第一表面(214)，第一导电元件(228)暴露在第一表面(214)和第二表面(222)的一个处。第一导电元件(228)的一些与微电子元件(222)电连接。线键合(232)具有与导电元件(228)接合的基区(234)以及远离衬底(212)和基区(234)的端表面(238)，每个线键合(232)限定在基区(234)和端表面(238)之间延伸的边缘表面(237)。封装层(242)从第一表面(214)延伸并填充线键合(232)之间的空间，以便通过封装层(242)分离线键合(232)。通过未被封装层(242)覆盖的线键合的端表面(238)的至少部分限定线键合(232)的未封装部分。

halo polymeric coating

Light emitting device, light emitting device manufacturing method and backlight unit

실시예에 따른 발광 소자는 상부가 개방되도록 형성된 캐비티를 포함하며, 상기 캐비티의 측벽은 상기 캐비티의 바닥면에 대해 제1 각도로 경사진 몸체; 상기 몸체에 형성되며, 적어도 일부분이 상기 캐비티의 측벽을 따라 형성된 제1 전극 및 제2 전극; 상기 제1 전극, 상기 제2 전극 및 상기 캐비티의 바닥면 중 어느 하나 위에 탑재된 발광칩; 일단은 상기 발광칩 상면에 본딩되고, 타단은 상기 캐비티의 측벽에 형성된 상기 제1 전극 및 제2 전극 중 적어도 하나에 본딩되는 적어도 하나의 와이어; 및 상기 캐비티 내에 형성되어 상기 발광칩을 밀봉하는 몰딩부재를 포함한다.

Electronic component for high frequency attenuation and bonding wire for the component

In order to provide an electronic component of a high frequency current suppression type, which can completely suppress a high frequency current to prevent an electromagnetic interference from occurring even when it is used at a high frequency, and a bonding wire for the same, the semiconductor integrated circuit device (IC) (17) operates at a high speed in using at a high frequency band, and a predetermined number of terminals (19) are provided with a high frequency current suppressor (21) for attenuating a high frequency current passing through the terminals themselves. This high frequency current suppressor (21) is a thin film magnetic substance having a range from 0.3 to 20 ( mu m) in thickness, and is disposed on the entire surface of each terminal (19), covering a mounting portion to be mounted on a printed wiring circuit board (23) for mounting IC (17) and an edge including a connecting portion to a conductive pattern (25) disposed on the printed wiring circuit board (23). When the top end is connected with the conductive pattern (25) by means of a solder (27) in mounting the printed wiring circuit board (23) of IC (17), the vicinity of the mounting portion has conductivity in a using frequency band, which is less than a few tens MHz. <IMAGE> <IMAGE>

Method for the wafer-level integration of shape memory alloy wires

The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate.

Halo-hydrocarbon polymer coating

Method for fabricating board on chip (BOC) semiconductor package with circuit side polymer layer

A method for fabricating a BOC package includes the steps of providing a semiconductor die having planarized bumps encapsulated in a polymer layer, and providing a substrate having a plurality of conductors and an opening. The method also includes the steps of attaching the die to the substrate in a BOC configuration, wire bonding wires through the opening to the conductors and the bumps, and forming a die encapsulant on the die.

Metal-base circuit board and its manufacturing method

Method of manufacturing semiconductor apparatus

A method of manufacturing a semiconductor apparatus includes forming an electrode on a semiconductor device, forming a conductive bump on the electrode, placing an external wire on the conductive bump, and laser-welding the external wire and the conductive bump to establish electrical connection.

Semiconductor device

Metal-base circuit board and its manufacturing method

혼성 집적 회로의 고주파 동작시에 발생하는 반도체의 오동작시를 대폭 저감시켜, 열 방산성이 우수한 금속 베이스 회로 기판을 제공한다. 금속판 상에 절연층 (A, B) 을 개재시켜 형성된 회로와, 상기 회로 상에 실장되는 출력용 반도체와, 상기 출력용 반도체를 제어하고, 상기 회로 상에 형성되는 제어용 반도체로 이루어지는 혼성 집적 회로에 사용되는 금속 베이스 회로 기판으로서, 상기 제어용 반도체를 탑재하는 회로 부분 (패드 부분) 의 하부에 저정전 용량 부분을 매설하고 있는 것을 특징으로 하는 금속 베이스 회로 기판으로서, 바람직하게는 저정전 용량 부분이, 무기질 충전재를 함유하여 이루어진 수지로 이루어지며, 또한 유전율이 2～9 인 것을 특징으로 하는 상기의 금속 베이스 회로 기판. A metal base circuit board excellent in heat dissipation is provided by significantly reducing malfunction of a semiconductor generated during high frequency operation of a hybrid integrated circuit. Used in a hybrid integrated circuit comprising a circuit formed on the metal plate via insulating layers A and B, an output semiconductor mounted on the circuit, and a control semiconductor formed on the circuit by controlling the output semiconductor. A metal base circuit board, wherein a low capacitance portion is embedded below a circuit portion (pad portion) on which the control semiconductor is mounted. Preferably, the low capacitance portion is an inorganic filler. Said metal base circuit board | substrate, Comprising: It consists of resin which contains and the dielectric constant is 2-9.

Semiconductor device and its manufacture

A reliable semiconductor device is provided which comprises lower and upper IGBTs 1 and 2 preferably bonded to each other by solder, and a wire strongly connected to lower IGBT 1 . The semiconductor device comprises a lower IGBT 1 , a lower electrode layer 5 secured on lower IGBT 1 , an upper electrode layer 6 secured on lower electrode layer 5 , an upper IGBT 2 secured on upper electrode layer 6 , and a solder layer 7 which connects upper electrode layer 6 and upper IGBT 2 . Lower and upper electrode layers 5 and 6 are formed of different materials from each other, and upper electrode layer 6 has a notch 36 to partly define on an upper surface 5 a of lower electrode layer 5 a bonding region 15 exposed to the outside through notch 36 so that one end of a wire 8 is connected to bonding region 15 . Upper electrode layer 6 can be formed of one material superior in soldering, and also, lower electrode layer 5 can be formed of another material having a high adhesive strength to wire 8.

Compliant microelectronic assemblies

A microelectronic assembly includes a microelectronic element having a first surface including a central region and a peripheral region surrounding the central region, the microelectronic element including a plurality of contacts disposed in the central region. The microelectronic assembly also includes a compliant layer over the peripheral region of the first surface, the compliant layer having a bottom surface facing toward the first surface of the microelectronic element, a top surface facing upwardly away from the microelectronic element and one or more edge surfaces extending between the top and bottom surfaces. A plurality of flexible bond ribbons are disposed over the compliant layer so that the bond ribbons extend over the top surface and one or more of the edge surfaces and the bond ribbons electrically connect the contacts to conductive terminals overlying the top surface of the compliant layer.

FIXING STRUCTURE AND METHOD FOR GENERATION OF ELECTRIC CONDUCTIVE MECHANICAL CONNECTIONS

Bonding wires for semiconductor devices

Ｃｕ合金芯材と、前記Ｃｕ合金芯材の表面に形成されたＰｄ被覆層とを有する半導体装置用ボンディングワイヤにおいて、前記ボンディングワイヤが高温環境下における接続信頼性を付与する元素を含み、下記（１）式で定義する耐力比が１．１〜１．６であることを特徴とする。耐力比＝最大耐力／０．２％耐力 （１） In a bonding wire for a semiconductor device having a Cu alloy core material and a Pd coating layer formed on the surface of the Cu alloy core material, the bonding wire contains an element that provides connection reliability in a high temperature environment, 1) The yield strength ratio defined by the formula is 1.1 to 1.6. Strength ratio = Maximum strength / 0.2% strength (1)

Halo-hydrocarbon polymer coating

In some embodiments, a printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further comprises a plurality of conductive tracks attached to at least one surface of the substrate. The PCB further comprises a multi-layer coating deposited on the at least one surface of the substrate. The multi-layer coating (i) covers at least a portion of the plurality of conductive tracks and (ii) comprises at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical component connected by a solder joint to at least one conductive track, wherein the solder joint is soldered through the multi-layer coating such that the solder joint abuts the multilayer coating.

Bonding wire

(57)【要約】 【課題】本発明は絶縁性高分子材料で被覆したボンディ ングワイヤーにおいて、表面付着不純物が少なく、接合 性がよく、低コストで製造できるものを提供する。 【解決手段】絶縁性高分子材料の絶縁皮膜１が、照射硬 化によって形成されている。 【効果】加熱焼付での皮膜形成ではなく照射硬化を行う ため、ワイヤー表面へ煤が付着するという問題がなく、 表面洗浄等の工程が不必要となり、さらに加熱硬化の場 合と異なり溶剤を使用しないため、低コストで信頼性の 高いボンディングワイヤーの製造が可能となる。また皮 膜の形成を照射硬化で行うため、ボンディング時皮膜の 剥離が容易となり、接合性に優れたボンディングワイヤ ーが得られる。

Wire bonding

A method of snaking a connection between a wire and a contact pad using a wire bonding technique, wherein the wire and/or the substrate is/are coated with a composition that comprises one or more halo-hydrocarbon polymers at a thickness of from 1 nm to 2 pm. The coating may also comprise one or more monolayers of metal halide. The coatings allow bonding using metallic compositions which are susceptible to corrosion in non-inert environments containing oxygen. The removal of the coating material prior to bonding is optional. The bonding method is applicable to the formation ball/wedge and wedge/wedge bonds.

Micro-miniaturized transistor

Wiring boards, semiconductor devices and their production processes

A wiring board comprising a substrate having applied on the same side surface thereof one or more terminals for connecting a semiconductor element and one or more terminals for external connection, in which the terminals for connecting the semiconductor element and the terminals for external connection are electrically connected, by a wire, with each other in the interior of the wiring board, and a semiconductor device comprising the wiring board having packaged thereon semiconductor elements. Processes for the production of the wiring board and the semiconductor device are also disclosed.

Method for connecting leadless chip packages & articles

Leadless chip package (10) is adhesively secured to printed wiring board (14) and is electrically connected by metallic conductor ribbon or wire (40, 42, 44...) to pads (30, 32, 34, 36) on the package (10) and pads (16, 18, 20, 22...) on the printed wiring board (14) to provide secure connection.

Light emitting device and backlight unit

Disclosed are a light emitting device, a method of manufacturing the same, and a backlight unit. The light emitting device includes a body (10) including a cavity (15) to open an upper portion, in which the cavity has a sidewall (16) inclined at a first angle from a bottom surface of the cavity, first (31) and second (32) electrodes formed in the body, in which at least portions of the first and second electrodes are formed along the sidewall of the cavity, a light emitting chip over the first electrode, the second electrode, and the bottom surface of the cavity, at least one wire (40) having one end bonded to a top surface of the light emitting chip (20) and an opposite end bonded to a portion of the first and second electrodes over the sidewall of the cavity, and a molding member (50) formed in the cavity to seal the light emitting chip.

Wire bonding

A method of snaking a connection between a wire and a contact pad using a wire bonding technique, wherein the wire and/or the substrate is/are coated with a composition that comprises one or more halo-hydrocarbon polymers at a thickness of from 1 nm to 2 pm. The coating may also comprise one or more monolayers of metal halide. The coatings allow bonding using metallic compositions which are susceptible to corrosion in non-inert environments containing oxygen. The removal of the coating material prior to bonding is optional. The bonding method is applicable to the formation ball/wedge and wedge/wedge bonds.

High density package interconnect wire bond strip line and method therefor

In an example embodiment, an integrated circuit (105) is placed in a package (100), the package having signal pad connections, power connections, and ground connections. A lower strip line (110) is bonded by coupling a first ground connection (110a) of the IC (105) to a first package substrate ground connection (110b). After bonding the lower strip line, a plurality of wires (125) is bonded by a plurality of signal pads (125a) on a device die (105) being coupled to signal pad connections (125b) on the package substrate (100), the plurality of signal pads (125a) being in proximity to the first ground connection (110a) and the plurality of wires (125) maintained at a first predetermined distance from the lower strip line (110). After bonding the plurality of wires (125), an upper strip line (130) is bonded by coupling a second ground connection (130a) of the IC (105) with a second package substrate ground connection (130b), the upper strip line maintained at a second predetermined distance from the plurality of wires (125).

Staggered wirebonding configuration

Light emitting device and backlight unit

Disclosed are a light emitting device, a method of manufacturing the same, and a backlight unit. The light emitting device includes a body (10) including a cavity (15) to open an upper portion, in which the cavity has a sidewall (16) inclined at a first angle from a bottom surface of the cavity, first (31) and second (32) electrodes formed in the body, in which at least portions of the first and second electrodes are formed along the sidewall of the cavity, a light emitting chip over the first electrode, the second electrode, and the bottom surface of the cavity, at least one wire (40) having one end bonded to a top surface of the light emitting chip (20) and an opposite end bonded to a portion of the first and second electrodes over the sidewall of the cavity, and a molding member (50) formed in the cavity to seal the light emitting chip.

Method for connecting articles such as chip packages without lead wires

Package-on-package assembly with wire bond leading to sealing surface

Method for joining bonding wire, semiconductor device, and method for manufacturing semiconductor device

本发明提供接合线的接合方法、半导体装置、半导体装置的制造方法。本发明的接合线的接合方法，将具有以非贵金属为主要成分的芯材及包覆上述芯材的贵金属层的接合线经由上述贵金属层楔形接合到在半导体元件的电极上形成的凸起。

Contact Structures Comprising A Core Structure And An Overcoat

A contact structure can comprise a core structure on a substrate and over coat material on the core structure. The over coat material can be harder or have a greater yield strength than the material of the core structure. The core structure can be formed by attaching a wire to the substrate and spooling the wire out from a spool. While spooling the wire out, the spool can be moved to impart a desired shape to the wire. The wire can be severed from the spool and over coated. As an alternative, the wire need not be over coated. The substrate can be an electronic device, such as a semiconductor die.

Method of making compliant microelectronic assemblies

A method of making a compliant microelectronic assembly includes providing a microelectronic element having a first surface, the first surface having a central region and a peripheral region surrounding the central region, the microelectronic element including a plurality of contacts disposed in the central region and providing a compliant layer over the peripheral region of the first surface, the compliant layer having a bottom surface facing toward the first surface of the microelectronic element, a top surface facing upwardly away from the microelectronic element and one or more edge surfaces extending between the top and bottom surfaces. Next, flexible bond ribbons are selectively formed over the compliant layer so that the bond ribbons extend over the top surface and one or more of the edge surfaces and the bond ribbons electrically connect the contacts to conductive terminals overlying the top surface of the compliant layer.

Semiconductor element, semiconductor element fabricating method, semiconductor device, and semiconductor device fabricating method

A method of forming a bump electrode (300) on an electrode includes the steps of forming a ball bond on an IC electrode by a wire bonding apparatus, moving up a bonding capillary, moving the bonding capillary sideway and then downward, bonding an Au wire to the ball bond portion, and cutting the Au wire. The bump electrode (300) has a particular form, with a bump portion (40) having a vertex (7) at a first height above the electrode and a tail portion (50) extending from the bump portion (300) and having a vertex (52) at approximately the same height as the vertex of the bump portion (40). Both vertices have a flattened surface (31a). <IMAGE>

Apparatus and method for producing an electrically conductive and mechanical connection

Es wird eine Vorrichtung (100) mit einem Grundkörper (1) aufweisend eine Elektrode (11) und mit einem Kontaktelement (2) angegeben. Das Kontaktelement (2) ist direkt mechanisch und elektrisch leitfähig mit der Elektrode (11) verbunden, um eine elektrische Verbindung (3) zwischen dem Grundkörper (1) und dem Kontaktelement (11) zu bilden. Die elektrische und mechanische Verbindung (3) zwischen der Elektrode (11) und dem Kontaktelement ist frei von Aufschmelzbereichen der an der Verbindung (3) beteiligten Materialien der Elektrode (11) und des Kontaktelements (2). Weiterhin ist die Verbindung (3) verbindungsmaterialfrei, beispielsweise lotmaterialfrei, realisiert. The invention relates to a device (100) having a base body (1), an electrode (11) and a contact element (2). The contact element (2) is directly mechanically and electrically connected to the electrode (11) in order to form an electrical connection (3) between the base body (1) and the contact element (11). The electrical and mechanical connection (3) between the electrode (11) and the contact element is free from melting areas of the materials of the electrode (11) and the contact element (2) involved in the connection (3). Furthermore, the connection (3) is realized without connection material, for example free of solder material.

A method of manufacturing a semiconductor device, e.g. B. a transistor or a diode

With wire bonding interconnection and the few stacked package of substrate

用于制造微电子单元(10)的方法，包括：在可图案化金属元件(28＇)的导电结合表面(30＇)上形成键合引线(32)。形成的键合引线具有与第一表面接合的基底(34)和远离第一表面的端面(38)。键合引线具有在基底与端面之间延伸的边缘表面(36)。该方法还包括在导电层第一表面的至少一部分上及键合引线的一部分上形成介电封装层(42)，使得键合引线的未被封装的部分，由端面或未被封装层覆盖的边缘表面的部分中的至少一个来限定。图案化金属元件，以形成在键合引线下方并通过部分封装层而相互之间绝缘的第一导电元件(28)。

Power model

本发明涉及功率模块，该功率模块具备：具有绝缘层以及形成于前述绝缘层之上的导体电路的功率模块用基板；设置在前述功率模块用基板之上、且与前述导体电路电连接的功率器件；和用于散热由前述功率模块用基板和/或前述功率器件产生的热的导热性片材。前述导热性片材含有片状的氮化硼颗粒，并且前述导热性片材在与厚度方向正交的方向的热导率为4W/m·K以上。

Method for measurement of straightness of metallic fine wire and measuring equipment of same

提供简单且正确的评估成为焊(压)接线测平原因的蜿蜒的一种金属细线的真直性的测定方法。于垂下金属细线并自垂直方向对该金属细线拍摄，区分弧状连接线长度2～25倍的多数区间并评估由拍摄影像求取的曲线的蛇行度。影响测平的焊(压)接线的蜿蜒，由以挟持曲线的平行线的间隔予以把握成蛇行宽幅，但长周期的蜿蜒即使蛇行宽幅较大，亦不影响测平，影响测平的曲率半径较小的蜿蜒与弧状连接线长度有关而把握成于上述区间的蛇行宽幅。焊(压)接线的摄影区分配合机器的精确度而将供试焊(压)接线区分成长度方向，以于宽幅方向上已放大的影像处理成2值数据，作为连续曲线予以评估。

Method and apparatus for bonding and breaking leads to semiconductors

The second wire bond is made in a semiconductor circuit simultaneously with breaking of the wire, in such manner that a "tailless" wirebond is achieved in minimum time and with no damage to either the wire or the bonding pad. The bond is made ultrasonically, and tension is applied to the wire during the actual time that ultrasonic bonding energy is supplied to the bonding tool. Such tension is applied by a spring or its equivalent, and is so predetermined that application of the bonding energy to the bonding tool will not only create the ultrasonic bond but will also break the wire.

Semiconductor device including pre-fabricated shielding frame disposed over semiconductor die

A semiconductor device includes a pre-fabricated shielding frame mounted over a sacrificial substrate and semiconductor die. An encapsulant is deposited through an opening in the shielding frame around the semiconductor die. A first portion of the shielding frame to expose the encapsulant. Removing the first portion also leaves a second portion of the shielding frame over the semiconductor die as shielding from interference. A third portion of the shielding frame around the semiconductor die provides a conductive pillar. A first interconnect structure is formed over a first side of the encapsulant, shielding frame, and semiconductor die. The sacrificial substrate is removed. A second interconnect structure over the semiconductor die and a second side of the encapsulant. The shielding frame can be connected to low-impedance ground point through the interconnect structures or TSV in the semiconductor die to isolate the die from EMI and RFI, and other inter-device interference.

Method for manufacturing a wire made of a first metal comprising a cladding made of a second metal

本申请涉及由第一金属制成的包括由第二金属制成的包覆层的线的制造方法，所述线是由选自由铜、银、金、镍及所述金属中的一者与至少一种其它金属的合金组成的群的金属1制成，具有由不同于所述金属1且选自由镍、银、金、钌、铂、钯、铑及所述金属中的一者与至少一种其它金属的合金组成的群的金属2制成的包覆层。