Verpackung für elektronische Komponenten

HALBLEITERANORDNUNG UND VERFAHREN ZU IHRER HERSTELLUNG

Optisches Kommunikationsmodul

Es wird erwartet, ein optisches Kommunikationsmodul bereitzustellen, das die Verringerung der Leistung der Lichtkommunikation vermeiden kann, wenn eine fotoelektrische Vorrichtung vom Kantenemittertyp montiert ist. Das optische Kommunikationsmodul umfasst: eine Basis 10, wo eine konvexe erste und zweite Linse 16, 15 einteilig auf der oberen bzw. unteren Oberfläche ausgebildet sind; und eine Laserdiode 20, die mit der ersten Linse 16 auf der oberen Oberfläche so ausgerichtet ist, dass sie ein Licht in die Richtung der ersten Linse 16 sendet. Die erste Linse 16 ist so ausgelegt, dass sie das von der Laserdiode ausgesendete Licht so bricht, dass es im Wesentlichen parallel zu der oberen Oberfläche der Basis 10 wird, wobei das gebrochene Licht nach unten in Richtung der zweiten Linse 15 reflektiert wird.

Halbleiterchip, Halbleiterbauteil und Verfahren zu deren Herstellung

Halbleiterchip (1) mit einer haftvermittlungsschichtfreien Dreischichtmetallisierung (2) bestehend aus einer Aluminiumschicht (4), die direkt auf dem Halbleiterchip (1) aufgebracht ist, einer Diffusionssperrschicht (5), die direkt auf der Aluminiumschicht (4) aufgebracht ist, einer Lotschicht (6), die direkt auf die Diffusionssperrschicht (5) aufgebracht ist, wobei, die Diffusionssperrschicht (5) Ti, Ni, Pt oder Cr ist, und die Lotschicht (6) eine Diffusionslotschicht ist, die AuSn, AgSn oder CuSn aufweist, und wobei der Halbleiterchip (1) eine aktive Oberseite (16) und eine passive Rückseite (3) aufweist, und wobei alle drei Schichten in einer Prozessabfolge auf der passiven Rückseite (3) aufgesputtert sind.

Connection between sensor terminal and conductor path applied to glass plate uses conductive connection element ultrasonically welded to conductor path

Connection is provided by electrically conductive connection element (11), e.g. bonding wire, which is ultrasonically welded to conductor path (5) applied to surface of glass plate (1) and which is coupled to sensor terminal (13) mounted on glass plate. Surface (3) of glass plate is ridged at point of connection between conductor path and connection element, ultrasonic welding position lying in furrow between 2 ridges (4). An Independent claim for an application of a sensor terminal connection for a ceramic glass cooking hob surface is also included.

Ceramic-metal substrate with differential thermal expansion compensation

Production of a ceramic-metal substrate involves attaching a first metal (preferably copper) foil layer (3) onto a ceramic layer (2a) surface and then slitting the ceramic layer (2a) by material removal as far as the metal layer (3). The novelty is that: (i) slits (5) are formed in the ceramic layer (2a) at a distance (a) from two or more edges (2a') and extending along the entire length of the edges to form, at both sides of each slit (5), a first ceramic section (2a") adjacent the edge (2a') and a further ceramic section (2a"'), each slit (5) having a width (b) of at least twice the thickness (d) of the ceramic layer (2a); (ii) the metal layer (3) is bent through 180 deg in the slit regions to form two or more U-shaped contacts (7, 7'), respective arms of which form upper contact faces (8, 8'), fixed to the further ceramic sections (2a"') on the substrate top surface, and lower contact faces (9) on the substrate bottom surface, the upper and lower contact face s being parallel to one ...

Gehäuse eines integrierten Schaltkreises und Verfahren zum Bilden desselben

Eine Ausführungsform einer Gehäuse-auf-Gehäuse(PoP)-Vorrichtung umfasst eine Gehäusestruktur, einen Gehäuseträger und eine Vielzahl von Anschlüssen, die die Gehäusestruktur mit dem Gehäuseträger verbinden. Die Gehäusestruktur umfasst einen Logikchip, der mit einem Speicherchip verbunden ist, eine Formmasse, die den Speicherchip umschließt und eine Vielzahl leitfähiger Stifte, die sich durch die Formmasse hindurch erstrecken. Die Vielzahl der leitfähigen Stifte ist an Kontaktpolstern auf dem Logikchip befestigt.

Bildaufzeichnungsgerät und Lichtquelleneinheit

Arrangement of semiconductor chip in chip carrier housing has conductive coating applied to semiconductor chip on opposite side to chip carrier

The arrangement has the semiconductor chip (1) mounted on the chip carrier (2) and enclosed by a resin mass (3) or an insulation layer, before application of a conductive coating (4) to the opposite side of the semiconductor chip to the chip carrier, in the form of a conductive layer applied to the resin mass or insulation layer and connected to a metal layer (7) applied to the chip carrier, e.g. a low-pass filter layer. Also included are Independent claims for the following: (a) a chip card; (b) a chip module ...

Anordnung mit mindestens einem optoelektronischen Halbleiterbauelement

Eine Anordnung mit mindestens einem optoelektronischen Halbleiterbauelement weist eine zum Tragen des mindestens einen optoelektronischen Halbleiterbauelements geeignete Trägerelementanordnung auf. Die Anordnung weist einen aus einem Licht absorbierenden Kunststoff gebildeten Gehäusekörper auf, der an der Trägerelementanordnung angeordnet ist. Der Gehäusekörper umfasst einen erhöhten Bereich und einen zurückgesetzten Bereich. Zwischen dem erhöhten und dem zurückgesetzten Bereich ist eine schräge Flanke gebildet. Der zurückgesetzte Bereich reicht bis an das optoelektronische Halbleiterbauelement, um Reflexionen zu verringern.

INTERCONNECTING COMPONENTS

ELECTRONIC CIRCUIT BOARD FOR A TIMEPIECE

BALL BOND PROCEDURE AND DEVICE FOR THE EXECUTION OF THE SAME

INTEGRATED HEATER ELEMENT ARRAY AND DRIVE MATRIX

NITRIDE PHOSPHOR AND METHOD FOR PREPARATION THEREOF, AND LIGHT EMITTING DEVICE

To provide a phosphor containing a comparatively much red component and having high light emitting efficiency, high brightness and further high durability, the nitride phosphor is represented by the general formula L X M Y N((2/3)X+(4/3)Y):R or L X M Y O Z N((2/3)X+(4/3)Y-(2/3)Z):R (wherein L is at least one or more selected from the group II Elements consisting of Mg, Ca, Sr, Ba and Zn, M is at least one or more selected from the Group IV Elements in which Si is essential among C, Si and Ge, and R is at least one or more selected from the rare earth elements in which Eu is essential among Y, La, Ce, Px, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er and Lu.); contains the another elements.

VARIABLE-BEAM LIGHT SOURCE AND RELATED METHODS

Light sources with arrangements of multiple LEDs (or other light- emitting devices) (102) disposed at or near the focus (106,108) of a reflecting optic (104) having multiple segments facilitate varying the angular distribution of the light beam (e.g., the beam divergence) via the drive currents supplied to the LEDs (102).

HALO-HYDROCARBON POLYMER COATING

In some embodiments, a printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further comprises a plurality of conductive tracks attached to at least one surface of the substrate. The PCB further comprises a multi-layer coating deposited on the at least one surface of the substrate. The multi-layer coating (i) covers at least a portion of the plurality of conductive tracks and (ii) comprises at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical component connected by a solder joint to at least one conductive track, wherein the solder joint is soldered through the multi-layer coating such that the solder joint abuts the multilayer coating.

VERFAHREN ZUM FORTLAUFENDEN HERSTELLEN MINDESTENS EINER DRAHTVERBINDUNG IN HALBLEITER-BAUTEILEN UND VORRICHTUNG ZUR AUSFUEHRUNG DES VERFAHRENS.

Dispositif à semi-conducteur, hermétiquement fermé, et procédé de fabrication de ce dispositif

Verfahren zum Befestigen von Kontaktdrähten an Halbleiterkörpern und Einrichtung zur Ausführung des Verfahrens

With low thermal resistance bump on the lead frame for semiconductor package

Isolation of the pin, the pad or chip carrier chip package and manufacturing method thereof

Circuit device and its mfg. method

Oxynitride fluorescent material, method for producing the same, and luminescent device using the same

An oxonitride phosphor which comprises a crystal containing at least one Group II element selected from the group consisting of Be, Mg, Ca, Sr, Ba and Zn, at least one Group IV element selected from the group consisting of C, Si, Ge, Sn, Ti, Zr and Hf, and a rare earth metal as an activator R. The oxonitride phosphor is exited by an excitation light source of an ultraviolet to visible region and emits a light having a color of from a blue-green region to a yellow region.

EQUIPMENT HAS SEMICONDUCTOR

DOSEMETER HAS LIGHTING BY the BACK

CONNECTIONS FOR SEMICONDUCTOR COMPONENTS

Package with reinforced structure for an integrated circuit, and card comprising such a package

L'invention concerne la protection des circuits intégrés destinés à être montés dans des dispositifs tels que des cartes dans lesquels ils ne doivent pas faire de surépaisseur. Elle consiste a renforcer le circuit intégré (101) par au moins une armature de renforcement (107) formée d'une plaque rigide et résistante noyée dans le matériau (106) formant habituellement le boîtier du circuit intégré. Cette armature de renforcement est de préférence fabriquée à partir d'une plaquette de silicium, selon les techniques utilisées pour fabriquer les circuits intégrés. Elle permet de renforcer la protection des circuits intégrés utilisés dans les "cartes à puces" et donc d'améliorer la fiabilité de celles-ci.

Fusion cutting thin filaments for semiconductor welding

MICROCASE Of ENCAPSULATION OF JUST CIRCUITS LOGICAL FUNCTIONING IN VERY High frequency

MODULATE HAS SMART CARD

MODULATE HAS SMART CARD

MODULATE HAS SMART CARD

MODULATE HAS SMART CARD

MODULATE HAS SMART CARD

HALO-HYDROCARBON POLYMER COATING

... 일부 구체예에서, 인쇄 회로 보드(PCB)는 절연재를 포함하는 기판을 포함한다. 상기 PCB는 기판의 하나 이상의 표면에 결합된 복수의 도전성 트랙을 더 포함한다. 상기 PCB는 기판의 하나 이상의 표면상에 증착된 다중층 코팅을 더 포함한다. 상기 다중층 코팅은 (i) 복수의 도전성 트랙의 적어도 일부를 커버하고, (ii) 할로-하이드로카본 폴리머로 형성된 하나 이상의 층을 포함한다. 상기 PCB는 하나 이상의 도전성 트랙에 솔더 접합에 의해 연결된 하나 이상의 전기 소자를 더 포함하며, 상기 솔더 접합은 상기 솔더 접합이 상기 다중층 코팅에 인접하도록 상기 다중층을 통해 솔더된다.

ASSEMBLY AND SEMICONDUCTOR MODULE

... 금속, 세라믹, 반도체 중 어느 하나를 접착한 접합체의 접착성과 열전도성을 향상시킨다. 금속, 세라믹, 반도체 중 어느 하나인 제1 부재와 제2 부재를 접착한 접합체에 있어서, 상기 제1 부재의 면에 설치된 접착 부재를 개재해서 상기 제2 부재가 접착되고, 상기 접착 부재는 V2O5를 포함하는 유리와 금속 입자를 함유한다. 베이스 금속과 세라믹 기판과 금속 배선과 반도체 칩을 구비한 반도체 모듈에 있어서, 상기 베이스 금속의 면에 설치된 제1 접착 부재를 개재해서 상기 세라믹 기판이 접착되고, 상기 세라믹 기판의 면에 설치된 제2 접착 부재를 개재해서 상기 금속 배선이 접착되고, 상기 금속 배선의 면에 설치된 제3 접착 부재를 개재해서 상기 반도체 칩이 접착되고, 상기 제1 접착 부재와 제2 접착 부재와 제3 접착 부재는 V2O5를 포함하는 유리와 금속 입자를 함유한다.

Method for manufacturing liquid crystal display device

LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING THE SAME

WIRE BONDING METHOD, SEMICONDUCTOR DEVICE WIRE BONDING CAPILLARY AND BALL BUMP FORMING METHOD

SEMICONDUCTOR DEVICE TO EXTREMELY REDUCE OUTER DIMENSION OF SEMICONDUCTOR DEVICE

PURPOSE: A semiconductor device is provided to reduce the outer dimension of a semiconductor device extremely by connecting a pad electrode to a lead terminal without using an interconnection of a bonding wire. CONSTITUTION: A semiconductor device has a semiconductor chip(10A) and an outer connection medium with a plurality of connection parts, including a plurality of pad electrodes, at least one via hole, a columnar electrode and a protrusion electrode(15). The plurality pad electrodes are formed on the first main surface of the semiconductor chip. The at least one via hole penetrates the semiconductor chip. The columnar electrode is electrically connected to the pad electrode through the via hole. The protrusion electrode is electrically connected to the columnar electrode. At least one of the plurality of connection parts is extended until the connection part reaches a position in which the connection part can be connected to the protrusion electrode. © KIPO 2006 ...

CONDUCTIVE WIRE, A MANUFACTURING METHOD THEREOF, AND A SEMICONDUCTOR PACKAGE INCLUDING THE SAME, FORMING A POLYMER LAYER ON A SURFACE OF THE CONDUCTIVE WIRE

PURPOSE: A conductive wire, a manufacturing method thereof, and a semiconductor package including the same are provided to prevent electric short between conductive wires by narrowly arranging the conductive wires even through the conductive wires are mutually contacted. CONSTITUTION: A conductive wire unit(10) includes metal particles and has a line shape. An insulation layer(20) surrounds the conductive wire and is made of the polymer. A reactor layer(30) is interposed between the conductive wire unit and the insulation layer. The reactor layer has a reactor connecting the polymer with each metal particle. COPYRIGHT KIPO 2010 ...

Enhanced method of wire bonding between substrate and semiconductor chip and soldering control system

An enhanced method of wire bonding between a substrate and a semiconductor chip is provided, which includes the following steps. A substrate is provided. At least one first pad is formed on the substrate. A semiconductor chip having at least one second pad is provided on the substrate. A first solder ball and a second solder ball are formed on the first pad and the second pad, respectively. A wire is bonded between the first and second solder balls. The interface between the first solder ball and the first pad is conducted by friction stir welding to enhance the joint of the first solder ball and the first pad.

Package for semiconductor light emitting element and semiconductor light emitting device

A package for semiconductor light emitting element is described. The package includes a first metal substrate having a cup shaped recess portion, an insulating member having a first cup shaped opening, provided on the first metal substrate, and a second metal substrate having a second cup shaped opening, provided on the insulating member with being electrically insulated from the first metal substrate, having a cavity in the inner surface.

OPTOELECTRONIC SEMICONDUCTOR CHIP

Disclosed is an optoelectronic semiconductor chip (1) comprising a radiation-permeable surface (3), a metallic contact coating (2a) that is applied to the radiation-permeable surface (3), and a first series of reflecting layers (2b) which is applied to the surface of the metallic contact coating (2a) facing away from the radiation-permeable surface (3). Also disclosed is an optoelectronic component comprising such a chip.

CHIP ATTACK PROTECTION

A system for protecting a chip with an integrated circuit disposed on a first surface, the system including, disposed on the first surface, a first antenna, signal analyzer, chip controller and a signal generator which is operative to supply an outbound signal for transmission by the first antenna, a circuit arrangement, disposed on a second surface of the chip, including a shielding arrangement and a second antenna to receive the outbound signal, the circuit arrangement being operative to transmit a return signal from the second antenna to the first antenna, such that a breach in the shielding arrangement results in a change in, or cessation of, the return signal for detection by the signal analyzer, and a chip controller disposed on the first surface being operative to perform an action on the integrated circuit in response to the detection of the breach. Related apparatus and methods also included.

HYBRID SILICON/NON-SILICON ELECTRONIC DEVICE WITH HEAT SPREADER

A hybrid electronic device incorporation both Si and non-Si semiconductor components, utilizing SiC, diamond, or another highly thermally conductive materials as an underlying heat spreader. The hybrid electronic device is comprised of some combination of components fabricated in: (1) the underlying heat spreader itself; (2) a thin Si layer attached to the heat spreader via wafer bonding; and/or (3) a discrete semiconductor electronics die soldered to the heat spreader.

COMPOSITION OF A SOLDER, AND METHOD OF MANUFACTURING A SOLDER CONNECTION

The solder composition comprises particles of a thermodynamically metastable alloy. One of the elements of the alloy will form an intermetallic compound with a metal surface. The solder composition is particularly suitable for use in bumping of semiconductor devices.

SMART INTEGRATED SEMICONDUCTOR LIGHT EMITTING SYSTEM INCLUDING NITRIDE BASED LIGHT EMITTING DIODES (LED) AND APPLICATION SPECIFIC INTEGRATED CIRCUITS (ASIC)

A light emitting diode (LED) system includes a substrate, an application specific integrated circuit (ASIC) on the substrate, and at least one light emitting diode (LED) on the substrate that includes a Group-III nitride based material such as GaN, InGaN, AIGaN, AlInGaN or other (Ga, In or AI) N-based materials. The light emitting diode (LED) system can also include a polymer lens, and a phosphor layer on the lens or light emitting diode (LED) for producing white light. In addition, multiple light emitting diodes (LEOs) can be mounted on the substrate, and can have different colors for smart color control lighting. The substrate and the application specific integrated circuit (ASIC) are configured to provide an integrated LED circuit having smart functionality. In addition, the substrate is configured to compliment and expand the functions of the application specific integrated circuit (ASIC), and can also include built in integrated circuits for performing additional electrical functions ...

MICROELECTRONIC ASSEMBLY WHEREIN A WIREBOND IS IMPEDANCE CONTROLLED BY USING AN ADDITIONAL WIREBOND CONNECTED TO A REFERENCE POTENTIAL

A microelectronic assembly can include a microelectronic device, e.g., semiconductor chip (910), connected together with an interconnection element (930), e.g., substrate, the latter having signal contacts (990) and reference contacts (980). The reference contacts can be connectable to a source of reference potential such as ground or a voltage source other than ground such as a voltage source used for power. Signal conductors, e.g., signal wirebonds (965) can be connected to device contacts (912) exposed at a surface of the microelectronic device (910). Reference conductors, e.g., reference wirebonds (975) can be provided, at least one of which can be connected with two reference contacts (980) of the interconnection element (930). The reference wirebond (975) can have a run which extends at an at least substantially uniform spacing from a signal conductor, e.g., signal wirebond (965) that is connected to the microelectronic device over at least a substantial portion of the length of the ...

METHOD FOR MANUFACTURING LIQUID CRYSTAL DISPLAY DEVICE

A conventionally followed technique of manufacturing a liquid crystal display device is a method for forming various types of coatings over an entire surface of a substrate and for removing the coatings with a small region left by etching, which requires wasting a material cost and treating a large quantity of waste. A liquid crystal display device is manufactured by forming at least one or more of patterns necessary for manufacturing a liquid crystal display device by a method capable of selectively forming a pattern. A droplet discharge method capable of forming a predetermined pattern by selectively discharging a droplet of a composition prepared for a specific purpose is employed as the method capable of selectively forming a pattern.

Method for soldering surface-mount component and surface-mount component

A method for soldering a surface-mount component onto a circuit board. The melting of die-bonding solder material is prevented by using a mounting solder material when soldering a surface-mount component formed using the die-bonding solder material onto a printed circuit board. The surface-mount component, formed using (Sn—Sb)-based solder material having high melting point, the (Sn—Sb)-based solder material containing Cu but not more than a predetermined quantity of Cu constituent and a main ingredient thereof being Sn, is soldered on a board terminal portion of a circuit board using (Sn—Ag—Cu—Bi)-based solder material or (Sn—Ag—Cu—Bi—In)-based solder material as the mounting solder material and with the solder material being applied on the terminal portion. Since solidus temperature of the die-bonding solder material is 243 degrees C. and liquidus temperature of the mounting solder material is about 215 through 220 degrees C., the melting of die-bonding solder material is prevented even ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

It is an object of the present invention to provide a method of separating a thin film transistor, and circuit or a semiconductor device including the thin film transistor from a substrate by a method different from that disclosed in the patent document 1 and transposing the thin film transistor, and the circuit or the semiconductor device to a substrate having flexibility. According to the present invention, a large opening or a plurality of openings is formed at an insulating film, a conductive film connected to a thin film transistor is formed at the opening, and a peeling layer is removed, then, a layer having the thin film transistor is transposed to a substrate provided with a conductive film or the like. A thin film transistor according to the present invention has a semiconductor film which is crystallized by laser irradiation and prevents a peeling layer from exposing at laser irradiation not to be irradiated with laser light.

Plastic lead frames for semiconductor devices

A conductive plastic lead frame and method of manufacturing the same, suitable for use in IC packaging, circuit card, electronic device, and a computer system. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Package-free bonding pad structure

A package-free bonding pad structure on a silicon chip that includes a plurality of metal pads on the upper surface of the silicon chip and a passivation layer covering the upper surface of the silicon chip. The passivation layer has a plurality of open cavities directly above the metal pad areas for exposing a portion of each metal pad. Diameter of the open cavity gets smaller on approaching the upper surface of the passivation layer and grows bigger in the neighborhood of the metal pad area.

Packaging electrical components

A package for electrical components in which a circuit board holds the components. The package includes an enclosure having generally parallel, spaced apart upper and lower internal surfaces. The circuit board lies generally parallel to the lower internal surface with the electrical components held in an internal space between the circuit board and the upper internal surface. Conductive terminal pins extend from outside the enclosure into the internal space. The terminal pins are connected to the circuit board by conductive links, each link having an end attached to the periphery of the circuit board and another end projecting into the internal space. In other aspects, a resilient non-compressive encapsulant is used to fill a space within the package; an electronic component is mounted with a power-dissipating device sitting in the aperture of a circuit board, a power-dissipating surface in contact with a baseplate, and contact pads electrically connected to the circuit board; terminal ...

Apparatus and method for flat circuit assembly

A thin and flat integrated circuit assembly (10, 40) may be achieved by using a thin carrier (20) with shallow cavities (22, 24) for holding the integrated circuits (16) and/or discrete circuit components (14). The integrated circuits (16) and/or circuit components (14) may be friction fitted in the cavities (22, 24) or they may be secured therein by the use of adhesives and/or solder. Electrical connection between the integrated circuits (16) and circuit components (14) may be done with wire bonding, ribbon bonding, tape-automated bonding, lead frames, flip chip bonding, and/or conductive gluing of leads. The circuit assembly may then be accommodated into a credit card-sized packaging with standard dimensions set by the International Standards Organization.

MICROWAVE TRANSISTOR CARRIER FOR COMMON BASE CLASS A OPERATION

Low thermal impedance integrated circuit

A frontside ground plane (306) integrated circuit with backside contacts (312) plus optional passive components such as microstrip (308) and capacitors. The frontside ground plane provides direct heat dissipation from active junctions such as heterojunction and field effect transistors.

Semiconductor laser array

A semiconductor laser array according to the invention is so constructed that plural LDs are driven by the same modulating signal, and series connection of the plural LDs becomes possible. Accordingly, efficiency of modulation of the aforementioned semiconductor laser array is largely improved. After a n-InP clad layer 6, an active layer 7 and a p-InP layer 8 are successively grown on a semi-insulating substrate 5, the n-InP clad layer 6 is etched and a stripe shaped mesa is formed. Then, a p-InP current blocking layer 9 and a n-InP current blocking layer 10 are grown on the etched portion. After fabricating a p+-InP cap layer 11 thereon, the surface of the n-InP clad layer 6 is exposed by selective etching. Moreover, a channel 12 for isolating the adjacent LDs, reaching the semi-insulating layer 5, is formed by penetrating the n-InP clad layer 6. Each of the LDs is provided with a p-side electrode 13 and a n-side electrode 14 thereon, and a p-side electrode 13 of any LD is connected to ...

Capacitive isolation circuitry with improved common mode detector

An integrated circuit having voltage isolation capabilities comprising a first galvanically isolated area of the integrated circuit containing a first group of functional circuitry for processing a data stream. The first group of functional circuitry located in a substrate of the integrated circuit. Capacitive isolation circuitry located in conductive layers of the integrated circuit provides a high voltage isolation link between the first group of functional circuitry and a second group of functional circuitry connected to the integrated circuit through the capacitive isolation circuitry. The capacitive isolation circuitry includes a differential transmitter for transmitting data in a differential signal to the second group of functional circuitry via the capacitive isolation circuitry. A differential receiver receives data within the differential signal from the second group of functional circuitry via the capacitive isolation circuitry. A detector circuit within the differential receiver ...

Lamination process and structure of high layout density substrate

A lamination process and structure of a high layout density substrate is disclosed. The lamination process comprises the following steps. First of all, a plurality of laminating layers are individually formed, wherein each laminating layer has a first dielectric layer, a plurality of first vias and a patterned conducting layer. Next, a bottom layer having a second dielectric layer and a plurality of second vias is formed. Then, the laminating layers and the bottom layer are stacked. Finally, the laminating layers and the bottom layer are laminated simultaneously to form a multiplayer substrate at one time.

Integrated circuit package bond pad having plurality of conductive members

An integrated circuit package bond pad includes an insulating layer and an electrode located over the insulating layer. The electrode has a first surface configured to be bonded to external circuitry and a second surface opposite the first surface. A plurality of conductive members is located in the insulating layer, wherein ones of the plurality of conductive members contact the second surface of the electrode.

Integrated circuit device with semiconductor device components embedded in plastic housing composition

The invention relates to a semiconductor device comprising semiconductor device components embedded in plastic housing composition. The semiconductor device components partly contain copper or have copper-containing coatings and/or coating structures. The copper-containing regions of the semiconductor device components have an adhesion promoting layer with copper(II) oxide whiskers on the surfaces that are in contact with the plastic housing composition.

Galvanic Isolation Device

A galvanic isolation device includes a first integrated circuit (IC) die that has communication circuitry formed in a circuit layer below the top surface. A first conductive plate is formed on the IC die proximate the top surface, and is coupled to the communication circuitry. A dielectric isolation layer is formed over a portion of the top surface of the IC after the IC is fabricated such that the dielectric isolation layer completely covers the conductive plate. A second conductive plate is juxtaposed with the first conductive plate but separated by the dielectric isolation layer such that the first conductive plate and the second conductive plate form a capacitor. The second conductive plate is configured to be coupled to a second communication circuit.

Electronic device and method for manufacturing structure for electronic device

An electronic device including a shielded electronic element, and a method for manufacturing a shielding structure. An oxide film is formed on the surface of a silicon substrate having a [100] face. Part of the oxide film is removed to form a first window region. Silicon substrates are joined together to form an SOI substrate, which includes a buried mask having a second window region. Substrate thinning is then performed, and oxide films are formed on the two surfaces of the SOI substrate so that the first window region has a large area and includes the region above the buried second window region. Then, anisotropic etching is performed to form a cap that includes a step. Wire bonding for shielding is performed on the step.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

According to an embodiment, a separation layer and a wiring layer having an organic insulating film formed of a resin material and a metal wiring are sequentially formed on a support substrate. Regions of the organic insulating film corresponding to dicing regions are removed. Plural semiconductor chips are mounted on the wiring layer. A sealing resin layer is formed on the separation layer. The sealing resin layer is formed to cover edge surfaces of the device forming regions. The support substrate is separated from a resin sealing body having the wiring layer, the plural semiconductor chips and the sealing resin layer. The resin sealing body is cut according to the dicing regions to cingulate a structure configuring a semiconductor device.

Stacked microfeature devices and associated methods

Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.

Method and apparatus for implementing selected functionality on an integrated circuit device

A semiconductor device is disclosed that includes a die having an active surface bearing integrated circuitry, the die including a plurality of bond pads thereon connected to the integrated circuitry. At least one electrically conductive wire bond is made between first and second bond pads of the plurality of bond pads for providing external electrical connection between the two bond pads, which are not interconnected via the integrated circuitry within the die. The first bond pad can be a lead finger on the active surface and the second bond pad can be an option bond pad electrically connected to a third bond pad selected from the plurality of bond pads on the active surface via the integrated circuitry. Further, the third bond pad can connect to a fourth bond pad selected from the plurality of bond pads via a wire bond. The first bond pad can also be an internal voltage line and the second bond pad an external voltage line or the bond pads can be different internal bus within the integrated ...

Method Of Fabricating Low Profile Leaded Semiconductor Package

In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the vertical side surface of the plastic body. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed, in particular a method of fabricating a package including an exposed die pad. 1. A method of fabricating a semiconductor package including an exposed die pad , the method comprising:providing a metal piece, the metal piece having a thickness;thinning the metal piece at a location where a cantilever segment of a lead is to be formed while leaving the thickness of the metal piece unchanged in a location where the die pad is to be formed;thinning the metal piece at a location where a foot of the lead is to be formed; andsevering the metal piece between the location of the die pad and the location of the cantilever segment of the lead.2. The method of wherein thinning the metal piece at a location where a foot of the lead is to be formed and severing the metal piece between the location of the die pad and the location of the cantilever segment of the lead are performed in a single process step.3. The method of wherein thinning a metal piece at the location where the cantilever segment of a lead is to be formed comprises thinning the metal piece at a location of a gap between the die pad and the cantilever segment of the lead.4. The method of wherein thinning the metal piece at locations where the cantilever segment of the lead and the gap between the die pad and the cantilever segment of the lead are to be formed comprises:depositing a first mask layer on a first side of the metal piece;forming an opening in the first mask layer corresponding to the locations where the cantilever segment of the lead and the gap between the die pad and the ...

SEMICONDUCTOR DEVICE, SOLID-STATE IMAGE PICKUP ELEMENT, IMAGE PICKUP DEVICE, AND ELECTRONIC APPARATUS

The present disclosure relates to a semiconductor device, a solid-state image pickup element, an image pickup device, and an electronic apparatus that are enabled to reduce restrictions on materials and restrictions on device configuration. A CSP imager and a mounting substrate are connected together with a connection portion other than a solder ball. With such a configuration, restrictions on materials and restrictions on device configuration are reduced, which has conventionally occurred because it is limited to a configuration in which solder balls are used for connection. The present disclosure can be applied to image pickup devices. 1. An image pickup device , comprising:a solid-state image pickup element that captures an image; anda mounting substrate on which the solid-state image pickup element is mounted,wherein the solid-state image pickup element is mounted on the mounting substrate with a connection portion having a configuration that does not use a solder ball, andwherein part of the mounting substrate is a transparent substrate.2. The image pickup device according to claim 1 , wherein the connection portion is a wire bonding junction.3. The image pickup device according to claim 2 , wherein in a state in which a light receiving surface of the solid-state image pickup element is in contact with the transparent substrate claim 2 , the solid-state image pickup element is mounted on the mounting substrate with the connection portion including the wire bonding junction.4. The image pickup device according to claim 2 , wherein a surface facing a light receiving direction of the mounting substrate and a light receiving surface of the solid-state image pickup element are flat claim 2 , and the solid-state image pickup element is mounted on the mounting substrate with the connection portion including the wire bonding junction.5. The image pickup device according to claim 2 , wherein a wire bonding material in the wire bonding junction is a single metal material ...

Method of sensor packaging

The present invention is directed to a method of making flexible interconnect packaging, in particular, packaging for fingerprint sensor chips. The chip is mounted on a flexible substrate having conductive traces leading to a connector at an end of the substrate. Wires are used to connect contact pads with the conductive traces, and a rigid frame is mounted below the substrate and chip. The conductive traces are preferably internal within the substrate and are exposed by forming a cavity in the substrate adjacent to the chip. Also disclosed are electronic devices which incorporate the foregoing fingerprint sensing apparatus.

In-line wire bonding on a package, and method of assembling same

A wire-bonding substrate includes in-line wire bonds that are substantially of the same pitch on the die bond pads as on the substrate bond pads. A wire-bonding substrate also includes staggered bond pads on at least one of the die and the substrate. A substrate bond pad includes a first wire-bond pad and a first via that is disposed directly below the first wire-bond pad in the wire-bonding substrate. A package is also disclosed that includes a die that is coupled to the first wire-bonding pad. A computing system is also disclosed that includes the in-line wire-bonding configuration.

Semiconductor devices with package-level configurability

A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad.

Semiconductor chip assembly with post/base heat spreader and ceramic block in post

A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a post, a base and a ceramic block. The post extends upwardly from the base into an opening in the adhesive, the base extends laterally from the post and the ceramic block is embedded in the post. The semiconductor device overlaps the ceramic block, is electrically connected to the conductive trace and is thermally connected to the ceramic block. The adhesive extends between the post and the conductive trace and between the base and the conductive trace. The conductive trace provides signal routing between a pad and a terminal.

SEMICONDUCTOR PACKAGES

A semiconductor package includes a semiconductor chip and a package substrate. The package substrate includes a base layer, a first group of conductive lines disposed on a first surface of the base layer, and a second group of conductive lines disposed on a second surface of the base layer and electrically connected to respective ones of the first group of conductive lines. The package substrate further includes a plating lead line connected to one of the first group of conductive lines, opening holes located between remaining portions of the second group of conductive lines to separate the second group of conductive lines from each other.

Pillar Bump Package Technology

A semiconductor product includes a die and leadframe included in a package made of plastic or other insulating material. The die and leadframe are dimensioned so that they overlap in at least one location. One or more pillar bumps, formed from as a cylindrical conductive base topped with a solder bump are used to interconnect the leadframe and die in the region of overlap. The pillar bumps perform several purposes including: electrical connection between the leadframe and die, support for the die during packaging and conduction of heat away from the die.

INTEGRATED CIRCUIT PACKAGE SYSTEM WITH NET SPACER

An integrated circuit package system that includes forming a strip level net spacer including support bars, tie bars and paddles. Configuring the support bars, the tie bars and the paddles to form open regions and interconnecting the support bars, the tie bars and the paddles to provide structural support to vertically stacked semiconductor devices.

PACKAGE STRUCTURE

Provided is a package structure including a die, an encapsulant, a through via, a first dielectric layer, a conductive line structure, an adhesion promotion layer, a second dielectric layer and a connector. The encapsulant is formed aside the die. The through via is formed aside the die and penetrates through the encapsulant. The first dielectric layer is formed overlying the die, the encapsulant and the through via. The conductive line structure includes a pad over the first dielectric layer. The adhesion promotion layer overlays a first portion of a top surface and a sidewall of the pad and overlying the first dielectric layer. The second dielectric layer overlays the adhesion promotion layer. The connector is in contact with a second portion of the top surface of the pad. The second portion of the top surface of the pad is exposed by the adhesion promotion layer.

Method for manufacturing an electronic device comprising an irremovable module and device thus obtained

Procédé de fabrication d'un dispositif électronique comportant un module indémontable et dispositif obtenu ...

Semiconductor device with different bonding configurations

Two different switches with two different signal input schemes are fabricated by mounting the same semiconductor chip on the same lead pattern (2). Two of the leads (2a,2c) of the lead pattern (2) provide enough space for wire-bonding connections (4) to corresponding electrode pads (C1,C2) on the semiconductor chip (3) at both ends of the semiconductor chip (3). Because each of electrode pads (C1,C2) can be connected to the corresponding lead (2a,2c) at either end of the semiconductor chip (3), two sets of bonding wire connections (4) between the leads (2a,2c) and the electrode pads (C1,C2) provide two different switches with two different signal inputs scheme.

Semiconductor laser array

A semiconductor laser array according to the invention is so constructed that plural LDs are driven by the same modulating signal, and series connection of the plural LDs becomes possible. Accordingly, efficiency of modulation of the aforementioned semiconductor laser array is largely improved. After a n-InP clad layer 6, an active layer 7 and a p-InP layer 8 are successively grown on a semi-insulating substrate 5, the n-InP clad layer 6 is etched and a stripe shaped mesa is formed. Then, a p-InP current blocking layer 9 and a n-InP current blocking layer 10 are grown on the etched portion. After fabricating a p+ -InP cap layer 11 thereon, the surface of the n-InP clad layer 6 is exposed by selective etching. Moreover, a channel 12 for isolating the adjacent LDs, reaching the semi-insulating layer 5, is formed by penetrating the n-InP clad layer 6. Each of the LDs is provided with a p-side electrode 13 and a n-side electrode 14 thereon, and a p-side electrode 13 of any LD is connected to ...

半導体装置

... 【課題】簡単な構造で確実に封止樹脂と金属面との剥離を抑制できる実装構造を備えた半導体装置を提供する。【解決手段】半導体装置１０１は、半導体素子１０と、絶縁基板２１と第１金属層２２と第２金属層２３とを有する絶縁回路基板２０と、を備える。電気回路を構成しない金属ブロック１の平坦な下面が第１金属層２２に対して平行となるように接合され、第１金属層２２の表面、半導体素子１０の表面、及び金属ブロック１の表面が封止樹脂によって被覆されている。【選択図】図１ ...

LEAD WIRE BONDING DEVICE AND METHOD

PURPOSE: To realize high-speed and low-cost automated bonding by fixing a tape structure having an IC device at a predetermined position by using vacuum means between wire bonding processes. CONSTITUTION: A flexible structure having an IC device is placed on the surface of a vacuum chuck 18. The chuck 18 has a cavity 20 at its center surrounded by an outer ring which functions as a support bond shelf 30 and is surrounded by a channel 24. A vacuum source 22 is connected to the cavity 20 and the channel 24, and the structure is maintained at a predetermined position. A plurality of supports 28 are provided in the cavity 20 to fix the structure in a parallel and flat position, and prevent the tape from being pulled into the cavity 20. The vacuum source 22 sucks and fixes the tape during bonding. This realizes automated bonding at a high speed and at a low cost. COPYRIGHT: (C)1990,JPO ...

IC PACKAGE

PROBLEM TO BE SOLVED: To secure solder performance on a lead frame while reducing an amount of a noble metal or not using gold by a method wherein a synthetic layer of a super-thin thickness composed of a noble metal layer is provided on a nickel face of the lead frame. SOLUTION: A lead 13 comprises a base metal layer 20; a nickel layer 21 on the base metal layer 20; and a synthetic metal layer 22 on the nickel layer 21. The entire thickness of the synthetic metal layer 22 is 63.5 to 279.4nm, and the synthetic metal layer 22 has a palladium or soft metal strike layer 23 of a thickness 12.7 to 88.9nm in order from the nickel layer 21. Further, the nickel layer 21 of a thickness 12.7 to 127nm has a palladium-nickel alloy layer 24 which occupies 10 to 90wt%; a palladium layer 25 of a thickness 12.7 to 127nm; and a gold layer 26 of a thickness 25.4nm at maximum as an option. Thus, solder performance can be secured on a lead frame, while an amount of nobble metal can be reduced, or gold is not ...

Halbleiteranordnung und Verfahren zur Herstellung derselben

Hermetisch eingeschlossene Halbleiteranordnung

Verfahren zur Herstellung einer keramischen Leiterplatte

Verfahren zur Herstellung einer keramischen Leiterplatte, die ein keramisches Substrat (S) aufweist, das auf einer seiner Oberflächen eine Metallisierung für lötbare Anschlussflächen (LA) für Bauelemente (BE) oder für lötfähige Kontakte (LK) aufweist, wobei die Metallisierung erzeugt wird, indem – als keramisches Substrat (S) ein LTCC Panel eingesetzt wird, – zunächst ganzflächig eine Grundmetallisierung (GM) durch Abscheiden von Kupfer aus einer Lösung direkt auf das keramische Substrat (S) aufgebracht wird, indem auf der Oberfläche des Substrats (S) zunächst ganzflächig Kupfer stromlos abgeschieden und anschließend durch galvanische Abscheidung von Kupfer verstärkt wird, – die Grundmetallisierung (GM) strukturiert wird, – auf die so erhaltene strukturierte Grundmetallisierung (SM) eine Verstärkungsschicht (VS) abgeschieden wird, indem eine Nickelschicht auf der strukturierten Grundmetallisierung (SM) und darauf eine Palladiumschicht chemisch abgeschieden werden, und – abschließend auf ...

Verfahren zur Herstellung eines Halbleiterbauteils mit in Kunststoffgehäusemasse eingebetteten Halbleiterbauteilkomponenten

Verfahren zur Herstellung eines Halbleiterbauteils mit in Kunststoffgehäusemasse (2) eingebetteten Halbleiterbauteilkomponenten (3) mit folgenden Schritten: Bereitstellen der Halbleiterbauteilkomponenten (3), Aufbringen einer Haftvermittlerschicht (5) nasschemisch unmittelbar auf die Oberfläche (4) der Halbleiterbauteilkomponenten (3), wobei das nasschemische Aufbringen so ausgebildet ist, dass als Halbleiterbauteilkomponenten (3) – ein Verdrahtungssubstrat (7) mit strukturierter Metallbeschichtung (8), – ein Keramiksubstrat mit strukturierten Metalllagen, – eine Leiterplatte (9) mit strukturierter Metallbeschichtung (8), – innere Flachleiter (10), die außerhalb der Kunststoffgehäusemasse (2) in Außenflachleiter (11) als Außenkontakte übergehen, – ein Halbleiterchip und – innere Flipchip-Kontakte und/oder Bondverbindungsdrähte (14) als Verbindungselemente (13) beschichtet werden können, ohne dass das Beschichtungsverfahren jeweils geändert werden muss, wobei eine Haftvermittlerschicht ( ...

Leadframemagazin-Magazindeckel

Die Erfindung bezieht sich auf einen Leadframemagazin-Magazindeckel zum Verschließen einer Öffnung eines Leadframemagazins durch Einschieben des Magazindeckels (4) in das Leadframemagazin (1) in einer Schließrichtung (6), wobei im Bereich einer Vorderkante (10) des Magazindeckels (4) in Schließrichtung (6) des Magazindeckels (4) eine Ausnehmung (9) ausgebildet ist.

LED-Lichtquelle mit einer Vielzahl von LED-Chips und LED-Chip zur Verwendung in selbiger

Die Erfindung betrifft eine LED-Lichtquelle, auf der eine Vielzahl von LED-Chips (11) fixiert und über beispielsweise Lötverbindungen (25, 18) elektrisch in Reihe geschaltet sind. Außerdem betrifft die Erfindung zur Montage auf dem betreffenden Substrat (19) geeignete LED-Chips (11). Erfindungsgemäß ist vorgesehen, dass die Kontaktierung benachbarter LED-Chips (11) dadurch sichergestellt wird, dass diese sich in einem Bereich (15) überlappen. Hierdurch kann verhindert werden, dass, wie normalerweise üblich, zwischen den benachbarten LED-Chips Zwischenräume zu deren elektrischer Verbindung vorgesehen werden müssen. Der Vorteil der überlappenden Anordnung liegt darin, dass eine hohe Packungsdichte von LED-Chips erreicht werden kann, wodurch ein vergleichsweise homogenes Lichtfeld mit vergleichsweise hoher Intensität von der LED-Lichtquelle abgestrahlt werden kann.

Sensoranordnung zur Messung von Druck, Kraft oder Meßgrößen, die sich auf Druck oder Kraft zurückführen lassen, Verfahren zur Herstellung der Sensoranordnung, Sensorelement und Verfahren zur Herstellung des Sensorelements

Die vorliegende Erfindung betrifft eine Sensoranordnung zur Messung von Druck, Kraft oder Meßgrößen, die sich auf Druck oder Kraft zurückführen lassen, ein Verfahren zur Herstellung einer solchen Sensoranordnung sowie ein Sensorelement und ein Verfahren zur Herstellung eines Sensorelements. DOLLAR A Die erfindungsgemäße Sensoranordnung umfaßt einen Chip (1) auf Si-Basis mit sensorischen Wandlergebieten und einer ersten Vorder- und einer ersten Rückseite, der auf mindestens der ersten Rückseite eine strukturierte Oberfläche mit Dünnungsgebieten (3) aufweist, wobei die strukturierte Oberfläche auf der ersten Rückseite eine intensivere Tiefenpolierung als die erste Vorderseite aufweist, und ein Trägersubstrat (2) mit einer zweiten Vorder- und einer zweiten Rückseite, wobei die zweite Vorderseite glatt und weitgehend fugenlos ist und der Chip und das Trägersubstrat dergestalt zusammengefügt sind, daß die erste und die zweite Rückseite aneinandergrenzen. DOLLAR A Durch die vorliegende Erfindung ...

Metall-Keramik-Substrat sowie Verfahren zum Herstellen eines Metall-Keramik-Substrates

Die Erfindung betrifft ein Metall-Keramik-Substrat (2) umfassend zumindest eine Keramikschicht (6), die an zumindest einer Oberflächenseite (6.1) mit wenigstens einer Metallisierung (7) versehen ist, die zur Ausbildung von Leiterbahnen und/oder Kontakt- oder Anschlussflächen derart strukturiert ist, dass zumindest ein Metallisierungsabschnitt (7a, 7b) zum Anschluss eines Kontaktelementes (4, 5) entsteht, dass der zumindest eine Metallisierungsabschnitt (7a, 7b) zumindest einen ersten Oberflächenabschnitt (7.1a, 7.1b) zum flächigen Anschluss eines Kontaktelementes (4, 5) aufweist. Besonders vorteilhaft sind die freien Ränder (6) der Keramikschicht (6) des Metall-Keramik-Substrates (2) durch Brechen der Keramikschicht (6) eines Basissubstrates (BS) entlang mehrerer in zumindest einer Oberflächenseite (6.1, 6.2) der Keramikschicht (6) in dem von der Metallisierung (7, 8) befreiten Bereich (6) der Keramikschicht (6) eingebrachte Sollbruchlinien (6a6f) hergestellt, wobei zumindest ein Kontaktelement ...

Surface mounted led structure and packaging method of integrating functional circuits on a silicon

The present invention relates to a surface mounted LED structure of integrating functional circuits on a silicon substrate, comprising the silicon substrate and an LED chip. Said silicon substrate has an upper surface of planar structure without grooves. An oxide layer covers the upper surface of the silicon substrate, and metal electrode layers are arranged in the upper surface of the oxide layer. The upper surfaces of said metal electrode layers are arranged with metal bumps, and the LED chip is flip-chip mounted to the silicon substrate. Two conductive metal pads are arranged on the lower surface of said silicon substrate, said conductive metal pads are electrically connected to the metal electrode layers on the upper surface of the silicon substrate by a metal lead arranged on the side wall of the silicon substrate. A heat conduction metal pad is arranged on the corresponding lower, surface of the silicon substrate just below the LED chip. Peripheral functional circuits required by LED are integrated on the upper surface of said silicon substrate. The structure of the present invention has advantages of good heat dissipation effect and small volume, and direct integration of functional circuits such as protection and drive circuits etc. in the silicon substrate achieves large-scale production package of wafer level, reducing the cost of packaging and lighting fixture.

Interposer including air gap structure, methods of forming the same, semiconductor device including the interposer, and multi-chip package including the interposer

Example embodiments of the present invention relate to an interposer of a semiconductor device having an air gap structure, a semiconductor device using the interposer, a multi-chip package using the interposer and methods of forming the interposer. The interposer includes a semiconductor substrate including a void, a metal interconnect, provided within the void, thereby forming an air gap insulating the metal interconnect. The metal interconnect may be connected to a contact element, and may be maintained within the air gap using the contact element.

Semiconductor light emitting device, optical pickup unit and information recording/reproduction apparatus

A semiconductor light emitting device downsized by devising arrangement of connection pads is provided. A second light emitting device is layered on a first light emitting device. The second light emitting device has a stripe-shaped semiconductor layer formed on a second substrate on the side facing to a first substrate, a stripe-shaped p-side electrode supplying a current to the semiconductor layer, stripe-shaped opposed electrodes that are respectively arranged oppositely to respective p-side electrodes of the first light emitting device and electrically connected to the p-side electrodes of the first light emitting device, connection pads respectively and electrically connected to the respective opposed electrodes, and a connection pad electrically connected to the p-side electrode. The connection pads are arranged in parallel with the opposed electrodes.

Integrated circuit package including miniature antenna

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna.

Optical module, manufacturing method of optical module and optical communication device

An optical module includes: a substrate provided with a through hole for inserting an optical fiber from a second principal surface side of the substrate; an optical device provided on a first principal surface side of the substrate; a first electrode provided in the substrate for connecting an electric fiber from the second principal surface side; a second electrode formed on the first principal surface side of the substrate for connecting to the optical device; and a third electrode provided on a side surface of the substrate and electrically connected to the second electrode.

Light projection unit and light projection device

A light projection unit is provided that can reduce the production of a portion where the light density is excessively increased on a fluorescent member. This light projection unit includes: a light collection member that includes a light entrance surface and a light emission surface which has an area smaller than that of the light entrance surface; a fluorescent member that includes an application surface to which the laser light emitted from the light collection member is applied and that mainly emits fluorescent light from the application surface; and a light projection member that projects the fluorescent light. The light emission surface of the light collection member is arranged a predetermined distance from the application surface of the fluorescent member.

Electronic device and manufacturing thereof

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Thermally enhanced light emitting device package

A thermally enhanced light emitting device package includes a substrate, a chip attached to the substrate, an encapsulant overlaid on the chip, and a plurality of non-electrically conductive carbon nanocapsules mixed in the encapsulant to facilitate heat dissipation from the chip.

Bump-On-Leadframe Semiconductor Package With Low Thermal Resistance

In a bump-on-leadframe semiconductor package a metal bump formed on a integrated circuit die is used to facilitate the transfer of heat generated in a semiconductor substrate to a metal heat slug and then to an external mounting surface. A structure including arrays of thermal vias may be used to transfer the heat from the semiconductor substrate to the metal bump

Highly reliable photoluminescent materials having a thick and uniform titanium dioxide coating

Described herein are coated photoluminescent materials and methods for preparing such coated photoluminescent materials. More particularly, provided herein are phosphors coated with titanium dioxide, methods for preparing phosphors coated with titanium dioxide, and solid-state light emitting devices which include phosphors coated with titanium dioxide.

Anti-reflection structures for cmos image sensors

Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.

Integrated circuit package assembly and method of forming the same

An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package providing electrical signal connections between the first integrated circuit package and the second integrated circuit package. At least one support structure is disposed between the first integrated circuit package and the second integrated circuit package to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package without providing electrical signal connections.

Highly-Reliable Micro-Electromechanical System Temperature Sensor

A micro-electromechanical system-type (MEMS) sensor arrangement for wirelessly measuring temperatures is disclosed. The MEMS sensor arrangement includes a multimorph sensor, a sensor coil coupled to the multimorph sensor, and a readout coil configured to be magnetically coupled to the sensor coil to i) energize the sensor coil, and ii) provide a readout of the natural frequency of the multimorph sensor, the sensor coil and the readout coil.

Optoelectronic component and method for producing an optoelectronic component

An optoelectronic component includes a substrate, a semiconductor chip arranged on the substrate, and a light-transmissive cover, wherein the light-transmissive cover covers at least an area of the semiconductor chip facing away from the substrate, the light-transmissive cover has a hardness greater than that of silicone, and a connecting material is arranged as a potting material between the light-transmissive cover and the substrate such that those areas of the semiconductor chip not covered by the substrate are surrounded by the connecting material, and the connecting material forms a cavity seal.

Semiconductor package containing silicon-on-insulator die mounted in bump-on-leadframe manner to provide low thermal resistance

Thermal transfer from a silicon-on-insulator (SOI) die is improved by mounting the die in a bump-on-leadframe manner in a semiconductor package, with solder or other metal bumps connecting the active layer of the SOI die to metal leads used to mount the package on a printed circuit board or other support structure.

Semiconductor device package and semiconductor device

A semiconductor device package is disclosed. The package according to one example includes a base having a main surface made of a metal, a dielectric side wall having a bottom surface facing the main surface, a joining material containing silver (Ag) and joining the main surface of the base and the bottom surface of the side wall to each other, a lead made of a metal joined to an upper surface of the side wall on a side opposite to the bottom surface, and a conductive layer not containing silver (Ag). The conductive layer is provided between the bottom surface and the upper surface of the side wall at a position overlapping the lead when viewed from a normal direction of the main surface. The conductive layer is electrically connected to the joining material, extends along the bottom surface, and is exposed from a lateral surface of the side wall.

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure including first and second packages is provided. The first package includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, and a plurality of conductive wire segments. The semiconductor die has an active surface and a back surface. The insulating encapsulant encapsulates the semiconductor die. The first redistribution layer is disposed on the back surface of the semiconductor die and a bottom surface of the insulating encapsulant. The first redistribution layer has a first surface and a second surface opposite to the first surface. The second redistribution layer is disposed on the active surface of the semiconductor die. The plurality of conductive wire segments electrically connects the semiconductor die to the second redistribution layer and the first redistribution layer to the second redistribution layer. The second package is stacked on the second surface of the first redistribution layer over the first package. 1. A package structure , comprising: a semiconductor die having an active surface and a back surface;', 'an insulating encapsulant encapsulating the semiconductor die and having a top surface and a bottom surface opposite to the top surface;', 'a first redistribution layer disposed on the back surface of the semiconductor die and the bottom surface of the insulating encapsulant, the first redistribution layer having a first surface and a second surface opposite to the first surface;', 'a second redistribution layer disposed on the active surface of the semiconductor die and having a third surface;', a first segment having a first extending direction substantially perpendicular to the third surface, the diameter of the first segment is substantially uniform, and the first segment is directly connected to the second redistribution layer; and', 'a first stud bonded to the semiconductor die, wherein the first stud is directly connected to the first segment;, 'a plurality of ...

Variable-beam light source and related methods

Light sources with arrangements of multiple LEDs (or other light-emitting devices) disposed at or near the focus of a reflecting optic having multiple segments facilitate varying the angular distribution of the light beam (e.g., the beam divergence) via the drive currents supplied to the LEDs.

INTEGRATED CIRCUIT PACKAGE ASSEMBLY

An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package. The first integrated circuit package includes a first integrated circuit die mounted on a first substrate. The second integrated circuit package includes a second integrated circuit die mounted on a second substrate. The second integrated circuit package is disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package and provide electrical signal connections between the first integrated circuit die and the second integrated circuit die. A buffer layer is disposed between the first substrate and the second integrated circuit die to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package. 1. An integrated circuit package assembly , comprising:a first integrated circuit package including a first integrated circuit die mounted on a first substrate;a second integrated circuit package including a second integrated circuit die mounted on a second substrate, the second integrated circuit package being disposed under the first integrated circuit package;solder bumps disposed between the first integrated circuit package and the second integrated circuit package providing electrical signal connections between the first integrated circuit die and the second integrated circuit die; anda buffer layer disposed between the first substrate and the second integrated circuit die to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package.2. The integrated circuit package assembly of claim 1 , wherein the buffer layer is configured to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package without providing electrical connections.3. The integrated circuit package assembly of claim 2 ...

Semiconductor dies with reduced area consumption

The width of scribe lines may be reduced in semiconductor devices by applying a process technique in which trenches may be formed first from the rear side on the basis of a required width of the corresponding trenches, while subsequently it may be cut into the substrate from the front side on the basis of a reduced thickness of the corresponding saw blades, thereby also enabling a reduction of the scribe line width. Furthermore, contamination of the front side, i.e., of the metallization system, may be reduced, for instance, by performing an optional intermediate cleaning process.

Integrated Circuit Package Including Miniature Antenna

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna, each of the five sections or segments forming a pair of angles with each adjacent segment or section, wherein the smaller angle of each of the four pairs of angles between sections or segments is less than 180° (i.e., no pair of sections or segments define a longer straight segment), wherein at least two of the angles are less than 115°, wherein at least two of the angles are not equal, and wherein the curve fits inside a rectangular area the longest edge of which is shorter than one-fifth of the longest free-space operating wavelength of the antenna. 1. A wireless system comprising:a substrate;a chip mounted on the substrate;a sensor mounted on the substrate;a first antenna mounted on the substrate and enclosed in a first rectangular area that does not enclose the chip, the first antenna comprising a first conducting pattern having a perimeter, wherein the perimeter of the first conducting pattern defines a first curve comprising at least five segments, wherein: each of the at least five segments forms an angle with each adjacent segment, at least three of the segments are smaller than a tenth of a longest free-space operating wavelength of the first antenna, each angle between adjacent segments is less than 180°, and at least two of the angles between adjacent segments are less than 115°; anda second antenna mounted on the substrate and enclosed in a second rectangular area having a longer side shorter than one-fifth of a longest free-space operating ...

WIREBOND INTERCONNECT STRUCTURES FOR STACKED DIE PACKAGES

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a second die disposed on a first die, a first plurality of interconnect structures disposed on a top surface of the first die, and a second plurality of interconnect structures disposed on a top surface of the second die. Top surfaces of the first plurality of interconnect structures are coplanar with top surfaces of the plurality of the second interconnect structures. At least one of the interconnect structures of the first or the second plurality of interconnect structures comprises a sigmoid shape. 1. A microelectronic package structure comprising:a first die;a second die disposed on the first die;a first plurality of interconnect structures disposed on a first surface opposite a second surface of the first die; anda second plurality of interconnect structures disposed on a first surface of the second die, wherein top surfaces of the first plurality of interconnect structures are coplanar with top surfaces of the plurality of the second interconnect structures, and wherein at least one of the first plurality of interconnect structures or one of the second plurality of interconnect structures comprises a sigmoid shape.2. The microelectronic package structure of wherein the first and the second plurality of interconnect structures comprise wire bonded interconnect structures.3. The microelectronic package structure of wherein a length of the first die is greater than a length of the second die.4. The microelectronic package structure of wherein a third die is disposed on the first surface of the second die.5. The microelectronic package structure of wherein a third plurality of interconnect structures is disposed on a top surface of the third die.6. The microelectronic package structure of wherein a top surface of the third plurality of interconnect structures is coplanar with the top surfaces of the first and the second ...

Support structure for mems device with particle filter

Various embodiments of the present disclosure are directed towards a microphone including a support structure layer disposed between a particle filter and a microelectromechanical systems (MEMS) structure. A carrier substrate is disposed below the particle filter and has opposing sidewalls that define a carrier substrate opening. The MEMS structure overlies the carrier substrate and includes a diaphragm having opposing sidewalls that define a diaphragm opening overlying the carrier substrate opening. The particle filter is disposed between the carrier substrate and the MEMS structure. A plurality of filter openings extend through the particle filter. The support structure layer includes a support structure having one or more segments spaced laterally between the opposing sidewalls of the carrier substrate. The one or more segments of the support structure are spaced laterally between the plurality of filter openings.

Thermal and stress isolation for precision circuit

Described examples include microelectronic devices and integrated circuits with an active first circuit in a first segment of a first wafer, a second circuit in a second segment of the first wafer, and second and third wafers bonded to different surfaces of the first wafer to provide first and second cavities with surfaces spaced from the first segment. An opening extends through the first wafer between the first and second cavities to separate portions of the first and second segments and to form a sealed cavity that surrounds the first segment. A bridge segment of the first wafer supports the first segment in the sealed cavity and includes one or more conductive structures to electrically connect the first and second circuits.

NOBLE METAL-COATED SILVER WIRE FOR BALL BONDING AND METHOD FOR PRODUCING THE SAME, AND SEMICONDUCTOR DEVICE USING NOBLE METAL-COATED SILVER WIRE FOR BALL BONDING AND METHOD FOR PRODUCING THE SAME

A noble metal-coated silver bonding wire suppresses corrosion at the bonding interface under severe conditions of high temperature and high humidity, and the noble metal-coated silver bonding wire can be ball-bonded in the air. The noble metal-coated silver wire for ball bonding is a noble metal-coated silver wire including a noble metal coating layer on a core material made of pure silver or a silver alloy, wherein the wire contains at least one sulfur group element, the noble metal coating layer includes a palladium intermediate layer and a gold skin layer, the palladium content relative to the entire wire is 0.01 mass % or more and 5.0 mass % or less, the gold content relative to the entire wire is 1.0 mass % or more and 6.0 mass % or less, and the sulfur group element content relative to the entire wire is 0.1 mass ppm or more and 100 mass ppm or less. 1. A noble metal-coated silver wire for ball bonding comprising a noble metal coating layer on a core material made of pure silver or a silver alloy ,wherein the wire contains at least one sulfur group element,the noble metal coating layer comprises a palladium intermediate layer and a gold skin layer,a palladium content relative to an entire wire is 0.01 mass % or more and 5.0 mass % or less,a gold content relative to the entire wire is 1.0 mass % or more and 6.0 mass % or less, anda content of the sulfur group element relative to the entire wire is 0.1 mass ppm or more and 100 mass ppm or less.2. The noble metal-coated silver wire for ball bonding according to claim 1 , wherein the noble metal coating layer further comprises a gold intermediate layer on a core material surface of the palladium intermediate layer.3. The noble metal-coated silver wire for ball bonding according to claim 1 , wherein the core material further contains copper claim 1 , and a copper content relative to the entire wire is 0.005 mass % or more and 2.0 mass % or less.46-. (canceled)7. A semiconductor device comprising at least one ...

Package-On-Package Assembly With Wire Bonds To Encapsulation Surface

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer. 1. A method comprising:providing a substrate having a surface having a first region and a second region that at least partially surrounds the first region, the substrate surface having electrically conductive elements in the second region;disposing a microelectronic element overlying the substrate surface within the first region;joining metal wires to the electrically conductive elements;drawing the metal wires out of a bonding tool so that portions of the metal wires extend upward from the substrate;forming a dielectric encapsulation layer above the substrate surface, wherein the encapsulation layer covers the metal wires and the metal wires are spaced from one another by the encapsulation layer;removing a portion of the encapsulation layer to expose unencapsulated portions of the metal wires;providing an electrically conductive material on the dielectric encapsulation layer in electrical connection with the unencapsulated portions of the metal wires.2. The method of claim 1 , wherein the metal wires are a first plurality of metal wires claim 1 , the method further comprising joining ...

WIRE BOND CONNECTION WITH INTERMEDIATE CONTACT STRUCTURE

Techniques and mechanisms for provide interconnection with integrated circuitry. In an embodiment, a packaged device includes a substrate and one or more integrated circuit (IC) dies. A first conductive pad is formed at a first side of a first IC die, and a second conductive pad is formed at a second side of the substrate or another IC die. Wire bonding couples a wire between the first conductive pad and the second conductive pad, wherein a distal end of the wire is bonded, via a bump, to an adjoining one of the first conductive pad and the second conductive pad. A harness of the bump, which is less than a hardness of the wire, mitigates damage to the adjoining pad that might otherwise occur as a result of wire bonding stresses. In another embodiment, the wire includes copper (Cu) and the bump includes gold (Au) or silver (Ag). 122.-. (canceled)23. A packaged integrated circuit (IC) device comprising:a substrate;one or more IC dies including a first IC die, wherein a first conductive pad is formed at a first side of the first IC die, wherein the substrate or an IC die other than the first IC die includes a second side, and wherein a second conductive pad is formed at the second side;a first bump disposed on one of the first conductive pad and the second conductive pad; anda first wire coupled between the first conductive pad and the second conductive pad, wherein a distal end of the first wire is bonded via the first bump to the one of the first conductive pad and the second conductive pad, wherein a first hardness of the first wire is more than a second hardness of the first bump and wherein a third hardness of the one of the first conductive pad and the second conductive pad is more than the second hardness.24. The packaged IC device of claim 23 , wherein the first wire includes copper (Cu).25. The packaged IC device of claim 24 , wherein the first bump includes gold (Au) or silver (Ag).26. The packaged IC device of claim 25 , wherein the one of the first ...

Damaging components with defective electrical couplings

A method, in some embodiments, comprises: providing a component having first and second electrical nodes; determining that the component lacks multiple, functional electrical couplings between said first and second nodes; damaging at least part of the component as a result of said determination; and determining, as a result of said damage, that the component is defective.

Dense-pitch small-pad copper wire bonded double ic chip stack packaging piece and preparation method therefor

A dense-pitch small-pad copper wire bonded double IC chip stack package comprises a plastic package body, in which a lead frame carrier and a frame lead inner pin are arranged; the upper surface of the lead frame carrier is fixedly connected with a first IC chip; a second IC chip is stacked on the first IC chip; the upper surface of the first IC chip and the upper surface of the second IC chip are respectively provided with a plurality of pads which are arranged as two lines of pad groups in parallel; the two pad groups are respectively a first pad group and a second pad group; a metal ball is implanted on each pad; each metal ball is connected with a first copper bonding ball; and a third copper bonding wire is formed by looping and arching on a corresponding metal ball between the second IC chip and the first IC chip. The preparation process of the present invention comprises thinning, scribing, loading the chip, performing pressure welding, plastic packaging and post-curing, trimming, electroplating, printing, forming and separating, and packaging. The package and the preparation method of the invention avoid the hidden danger of open circuit of a plastic packaging punching wire caused by the crater on the pad, the short circuit of adjacent welding spots, and the easy damage of a previous wire.

OPTOELECTRONIC DEVICE

A method for producing an optoelectronic device comprises steps for providing a package with a first surface and a second surface, wherein an electrically conductive chip carrier is embedded in the package and is accessible at the first surface and at the second surface, and for applying an insulation layer on the second surface of the package by means of aerosol deposition. 1. An optoelectronic device comprising:a package with a first surface and a second surface,wherein an electrically conductive chip carrier is embedded in the package and is accessible at least in places at the first surface,wherein the electrically conductive chip carrier is electrically contactable from outside at the second surface,wherein an optoelectronic semiconductor chip is arranged on the first surface of the package,wherein an electrically conductive connection arises between the optoelectronic semiconductor chip and the chip carrier,wherein a ceramic insulation layer is arranged on the second surface of the package and wherein the insulation layer has a thickness of between 1 μm and 20 μm.2. The optoelectronic device according to claim 1 ,wherein the chip carrier is a leadframe,wherein the package consists in part of an electrically insulating material, andwherein the chip carrier is enclosed by the package on at least two sides of the chip carrier.3. The optoelectronic device according to claim 1 ,wherein a metallization is arranged on portions of the insulation layer and of the second surface.4. The optoelectronic device according to claim 1 ,wherein a first area portion of the metallization is in electrically conductive connection with the chip carrier,wherein a second area portion of the metallization is insulated relative to the chip carrier by the insulation layer,wherein the first area portion and the second area portion are insulated electrically relative to one another.5. The optoelectronic device according to claim 1 ,wherein an electrically conductive contact is embedded in ...

Led assembly

Disclosed are LED assemblies and their applications. An example LED assembly has an LED chip, a supportive structure and a transparent structure. The LED chip includes a transparent substrate, at least one LED cell, and two pads. The transparent substrate has a top surface with two terminals. The LED cell is formed on the top surface, and includes at least one light-emitting stack configured to emit light. The pad is formed on the top surface at the two terminals. The supportive structure has a transparent portion and a conductive portion. The conductive portion is connected to the transparent portion to fix the LED chip and supply electric power to at least one of the pads. The transparent structure encapsulates the LED cell.

Transistor outline housings for distributed feedback lasers

A transistor outline (TO) housing comprising a base part having a mounting area for a thermoelectric cooler, wherein the base part has at least two feedthroughs for connecting an optoelectronic component. A support extends from the upper surface of the base part, which support has at least two conductor traces arranged thereon, each of which is connected to a respective one of the feedthroughs for connecting the optoelectronic component.

Semiconductor device, embedded capacitor unit, semiconductor package, and method of manufacturing embedded capacitor unit

Jitter that becomes a problem in a semiconductor part which performs high-speed signal processing is reduced. A semiconductor device includes a heat-resistant metal plate, a capacitor part having a lower electrode, a sintered dielectric part, and an upper electrode that are formed on one or more surfaces of the heat-resistant metal plate, a semiconductor chip fixed on the capacitor part, a wire for electrically connecting a lead frame to the semiconductor chip and the upper electrode, and a mold part in which at least the capacitor part and the semiconductor chip are buried. The semiconductor chip, the electrode, the metal plate, and the like are electrically connected with each other via first, second, and third wires.

PACKAGED SEMICONDUCTOR DEVICES FOR HIGH VOLTAGE WITH DIE EDGE PROTECTION

In a described example a device includes: a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface; a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall; a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; and portions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer. 1. A device , comprising:a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface;a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall;a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; andportions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer.2. The device of claim 1 , wherein a thickness of the passivation layer is at least 10 μm.3. The device of claim 1 , wherein the passivation layer is a material that is one selected from a group consisting essentially of: silicon dioxide claim 1 , silicon nitride claim 1 , silicon oxynitride claim 1 , polyimide claim 1 , and combinations ...

Isolation of circuit elements using front side deep trench etch

An integrated circuit is formed by forming an isolation trench through at least a portion of an interconnect region, at least 40 microns deep into a substrate of the integrated circuit, leaving at least 200 microns of substrate material under the isolation trench. Dielectric material is formed in the isolation trench at a substrate temperature no greater than 320° C. to form an isolation structure which separates an isolated region of the integrated circuit from at least a portion of the substrate. The isolated region contains an isolated component. The isolated region of the integrated circuit may be a region of the substrate, and/or a region of the interconnect region. The isolated region may be a first portion of the substrate which is laterally separated from a second portion of the substrate. The isolated region may be a portion of the interconnect region above the isolation structure.

STACKED MICROFEATURE DEVICES AND ASSOCIATED METHODS

Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device. 1. A method for forming a microfeature device package , comprising:positioning a first microfeature device at least proximate to a second microfeature device, the first microfeature device having a first bond pad surface with a first bond pad, the second microfeature device having a second bond pad surface with a second bond pad and an intermediate bond pad electrically connected to the second bond pad, the first bond pad surface facing toward the second bond pad surface;coupling a wirebond between the first bond pad and a package connection site; anddisposing an electrically conductive member between the first bond pad and the intermediate bond pad.2. The method of wherein disposing an electrically conductive member includes disposing a volume of solder between the first bond pad and the intermediate bond pad.3. The method of wherein disposing an electrically conductive member includes disposing at least one of a gold stud bump claim 1 , a copper stud bump claim 1 , and a solder bump.4. The method of claim 1 , further ...

Substrate for alternative semiconductor die configurations

A method of assembling semiconductor devices with semiconductor dies of alternative different configurations uses the same substrate panel. The dies of the selected configuration are placed in an array, mounted, and connected to internal electrical contact pads on a first face of the panel using main fiducial markings and an array of subsidiary fiducial markings corresponding universally to arrays of semiconductor dies of the different alternative configurations. The pitch of the subsidiary fiducial markings is equal to the spacing between adjacent rows of the internal electrical contact pads on the panel and is a sub-multiple of the pitch of the array of dies.

Optoelectronic packages having magnetic field cancelation

A stacked optoelectronic packaged device includes a bottom die having a top surface including bottom electrical traces and a light source die coupled to ≧1 bottom electrical traces. A first cavity die is on the bottom die. An optics die is on the first cavity die and a second cavity die on the optics die. A mounting substrate is on the second cavity die including top electrical traces. A photodetector die is optically coupled to receive light from the light source. The bottom and top electrical traces are both positioned substantially symmetrically on sides of a mirror plane so that when conducting equal and opposite currents a first magnetic field emanating from the first side and a second magnetic field emanating from the second side cancel one another to provide a reduction in magnetic flux density by more than 50% at one or more die locations on the optics die.

Methods of forming leadless semiconductor packages with plated leadframes and wettable flanks

A leadless package with wettable flanks is formed by providing a substrate and plating a metal layer onto the substrate to form a contact on the substrate extending across a saw street. An encapsulant is deposited over the contact. The substrate is removed to expose the contact and encapsulant. The encapsulant and contact are singulated. In some embodiments, the substrate includes a ridge, and the contact is formed over the ridge.

Amplifier

An amplifier includes a transistor chip, a matching chip with a capacitor group having multiple MIM capacitors, each of the MIM capacitors including a lower electrode, a dielectric, and an upper electrode, a bonding wire that electrically connects the transistor chip to the upper electrode of any one of the MIM capacitors of the capacitor group and transmits a high-frequency signal, and a case that accommodates the transistor chip and the matching chip. The lower electrodes of the MIM capacitors are grounded, and capacitance values of each of the MIM capacitors of the capacitor group are different from each other.

Thermal Dissipation Through Seal Rings in 3DIC Structure

A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A heat spreader encircles the die and the interposer. A wire includes a first end bonded to one of the plurality of metal lines, and a second end bonded to the heat spreader.

LEADLESS SEMICONDUCTOR PACKAGES, LEADFRAMES THEREFOR, AND METHODS OF MAKING

A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer. 1. A method of making a semiconductor device , comprising:providing at least four semiconductor die;providing a plurality of contacts adjacent to each of the semiconductor die;providing at least four tie bars adjacent to each of the semiconductor die;depositing an encapsulant over the at least four semiconductor die and the plurality of contacts; andforming at least four trenches in a first surface of the encapsulant for a full vertical thickness of the plurality of contacts to expose the plurality of contacts.2. The method of claim 1 , further including forming a conductive layer over the flank of the contact for the full vertical thickness of the contact.3. The method of claim 1 , further including forming a second trench in the first surface of the encapsulant between the semiconductor die and the contact.4. The method of claim 1 , further including disposing a die pad under the semiconductor die claim 1 , wherein the at least four tie bars extend from the second surface of the encapsulant to the die pad.5. The method of claim 1 , further including forming a bond wire extending from the first surface or the second surface of the encapsulant.6. The method of claim 1 , wherein a depth of the second trench into the encapsulant is approximately equal to half of a ...

INTEGRATED CIRCUIT PACKAGE ASSEMBLY

An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package. The first integrated circuit package includes a first integrated circuit die mounted on a first substrate. The second integrated circuit package includes a second integrated circuit die mounted on a second substrate. The second integrated circuit package is disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package and provide electrical signal connections between the first integrated circuit die and the second integrated circuit die. A buffer layer is disposed between the first substrate and the second integrated circuit die to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package. 1. An integrated circuit package assembly , comprising:a first integrated circuit package including a first die disposed over a first substrate, a second die disposed over the first die, and a third die disposed over the second die;wherein the substrate has outermost sidewalls spaced apart by a substrate width, the first die has outermost sidewalls spaced apart by a first die width that is less than the substrate width, the second die has outermost sidewalls spaced apart by a second die width that is less than the first die width, and the third die has outermost sidewalls spaced apart by a third die width that is greater than the second die width;a molding compound disposed over the first substrate, the first die, the second die, and the third die, wherein a wire bond extends through the molding compound from an upper surface of the first die to an upper surface of the first substrate;a second integrated circuit package including a second integrated circuit die mounted on a second substrate, the second integrated circuit package being disposed under the first integrated circuit package; andsolder ...

Package structure and method of forming the same

A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a dielectric layer, a first redistribution layer (RDL) and a second RDL. The encapsulant laterally encapsulates the die. The dielectric layer is located on the encapsulant and the die. The first RDL penetrates through the dielectric layer to connect to the die. The second RDL is located on the first RDL and the dielectric layer. The second RDL and the first RDL share a common seed layer.

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a first polymer material layer, a second polymer material layer and a first redistribution layer. The encapsulant encapsulates sidewalls of the die. The first polymer material layer is on the encapsulant and the die. The second polymer material layer is on the first polymer material layer. The first redistribution layer is embedded in the first polymer material layer and the second polymer material layer and electrically connected to the die. The first redistribution layer has a top surface substantially coplanar with a top surface of the second polymer material layer, and a portion of a top surface of the first polymer material layer is in contact with the first redistribution layer. 1. A package structure , comprising:a die;an encapsulant encapsulating sidewalls of the die;a first polymer material layer on the encapsulant and the die;a second polymer material layer on the first polymer material layer; anda first redistribution layer embedded in the first polymer material layer and the second polymer material layer and electrically connected to the die,wherein the first redistribution layer has a top surface substantially coplanar with a top surface of the second polymer material layer, and a portion of a top surface of the first polymer material layer is in contact with the first redistribution layer.2. The package structure of claim 1 , wherein the first redistribution layer comprises:a via penetrating through the second polymer material layer and the first polymer material layer to connect to the die; anda trace connected to the via and embedded in the second polymer material layer and in contact with the portion of the top surface of the first polymer material layer.3. The package structure of claim 2 , wherein the trace has a thickness substantially equal to a thickness of the second polymer material layer.4. The package structure of claim 2 ...

DUAL HEAD CAPILLARY DESIGN FOR VERTICAL WIRE BOND

Embodiments disclosed herein include wire bonds and tools for forming wire bonds. In an embodiment, a wire bond may comprise a first attachment ball, and a first wire having a first portion contacting the first attachment ball and a second portion. In an embodiment, the wire bond may further comprise a second attachment ball, and a second wire having a first portion contacting the second attachment ball and a second portion. In an embodiment, the second portion of the first wire is connected to the second portion of the second wire. 1. A wire bond , comprising:a first attachment ball;a first wire having a first portion contacting the first attachment ball and a second portion;a second attachment ball; anda second wire having a first portion contacting the second attachment ball and a second portion, wherein the second portion of the first wire is connected to the second portion of the second wire.2. The wire bond of claim 1 , wherein lateral sidewalls of the second portions are bonded together.3. The wire bond of claim 1 , wherein the first wire and the second wire are substantially equal in length.4. The wire bond of claim 1 , wherein the first attachment ball is aligned with the second attachment ball.5. The wire bond of claim 1 , wherein the first attachment ball is not aligned with the second attachment ball.6. The wire bond of claim 5 , wherein the first wire is a different length than the second wire.7. The wire bond of claim 1 , wherein the first attachment ball is coupled to a first substrate.8. The wire bond of claim 7 , wherein the second attachment ball is coupled to a second substrate.9. The wire bond of claim 8 , wherein the first substrate is oriented face-to-face with respect to the second substrate.10. The wire bond of claim 8 , wherein the first substrate is a die and wherein the second substrate is a package substrate.11. The wire bond of claim 8 , wherein the first substrate is a die and wherein the second substrate is a die.12. An electronic ...

Leadless semiconductor packages, leadframes therefor, and methods of making

A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.

Low Profile Leaded Semiconductor Package

In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the vertical side surface of the plastic body. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed. 1. A method of fabricating a semiconductor package comprising:thinning a metal piece at locations where a die pad and a cantilever segment of a lead are to be formed;thinning the metal piece at a location where a foot of the lead is to be formed; andsevering the metal piece between the location of the die pad and the location of the cantilever segment of the lead.2. The method of wherein thinning the metal piece at a location where a foot of the lead is to be formed and severing the metal piece between the location of the die pad and the location of the cantilever segment of the lead are performed in a single process step.3. The method of wherein thinning a metal piece at locations where a die pad and a cantilever segment of a lead are to be formed comprises thinning the metal piece at a location of a gap between the die pad and the cantilever segment of the lead.4. The method of wherein thinning the metal piece at locations where the die pad claim 3 , the cantilever segment of the lead claim 3 , and the gap between the die pad and the cantilever segment of the lead are to be formed comprises depositing a first mask layer on a first side of the metal piece claim 3 , forming an opening in the first mask layer corresponding to the locations where the die pad claim 3 , the cantilever segment of the lead claim 3 , and the gap between the die pad and the cantilever segment of the lead are to be formed claim 3 , and partially etching the metal piece through the first opening in the first mask layer.5. The method of wherein thinning the metal ...

INTEGRATED CIRCUIT DEVICE

An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure, a first internal bonding wire, and a second internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The third bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the third bonding pad structure via the first internal bonding wire. The third bonding pad structure is electrically coupled to the second bonding pad structure via the second internal bonding wire. 1. An integrated circuit device , comprising:a semiconductor substrate;a first bonding pad structure, disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate;a second bonding pad structure, disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate;a third bonding pad structure, disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate;a first internal bonding wire, wherein the first bonding pad structure is electrically coupled to the third bonding pad structure via the first internal bonding wire; anda second internal bonding wire, wherein the third bonding pad structure is electrically coupled to the second bonding pad structure via the second internal bonding wire.2. The integrated circuit device as claimed in claim 1 , further comprising:an external bonding wire, wherein the second bonding pad structure is electrically coupled to a package lead via the external bonding wire.3. The integrated circuit device as claimed ...

SEMICONDUCTOR DEVICES WITH PACKAGE-LEVEL CONFIGURABILITY

A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad. 1. A semiconductor die , comprising:a first contact pad electrically coupled to a first circuit on the semiconductor die including at least one active circuit element;a second contact pad electrically coupled to a second circuit on the semiconductor die including only passive circuit elements; anda single solder ball in both direct physical and electrical contact with each of the first contact pad and the second contact pad.2. The semiconductor die of claim 1 , wherein the first circuit is a driver circuit.3. The semiconductor die of claim 1 , wherein the second circuit includes one or more capacitors to provide electrostatic discharge (ESD) protection.4. The semiconductor die of claim 1 , further comprising a NAND memory array.5. The semiconductor die of claim 1 , further comprising a wirebond directly coupled to the single solder ball.6. The semiconductor die of claim 1 , wherein the first contact pad is separated from the second contact pad by a region of non-conductive material.7. The semiconductor die of claim 6 , wherein the single solder ball bridges the region ...

Light emitting element mounting substrate and light emitting device

Object: To provide a light emitting element mounting substrate capable of exhibiting high brightness and high light emission efficiency over an extended period of time, and a light emitting device constituted by mounting a light emitting element on this light emitting element mounting substrate. Resolution means: A light emitting element mounting substrate, including a substrate made from a ceramic; a metal layer provided on the substrate that includes gold or silver as a primary component; and a resin layer provided covering at least a portion of the metal layer. The resin layer includes platinum, and at least one type of oxide of magnesium, calcium, and copper is present on a surface of the metal layer.

Encapsulating a Bonded Wire with Low Profile Encapsulation

Encapsulating a bonded wire with low profile encapsulation includes applying encapsulation over a bonded wire that is connected to a die on a first end and to a circuit component on a second end and truncating a shape of the encapsulation to form a truncated shape. 1. A method for encapsulating a bonded wire with low profile encapsulation , comprising:applying an encapsulation material over a bonded wire, the bonded wire being connected to a die on a first end, and the bonded wire being connected to a circuit component on a second end; andcompressing the encapsulation material, using a stamp, from a deposited shape to a truncated shape.2. The method of claim 1 , wherein compressing the encapsulation material using the stamp includes actively heating the stamp while compressing the encapsulation material.3. The method of claim 2 , wherein the truncated shape comprises a top-hat profile.4. The method of claim 2 , further comprising:subsequent to compressing the encapsulation material using the stamp, removing the stamp to allow the encapsulation material to solidify.5. The method of claim 1 , wherein the stamp includes a distance sensor to maintain a height of the truncated shape.6. The method of claim 5 , wherein maintaining the height of the truncated shape is based on a distance between the underside of the stamp and a top side of a compound disposed over the die.7. A method for encapsulating a bonded wire with low profile encapsulation claim 5 , comprising:applying an encapsulation material over a bonded wire, the bonded wire being connected to a die on a first end, and the bonded wire being connected to a circuit component on a second end;heating a stamp to compress the encapsulation material from a deposited shape to a truncated shape; andcompressing the encapsulation material, using the heated stamp, from the deposited shape to the truncated shape, wherein the truncated shape reflects a geometry of an underside of the stamp.8. The method of claim 7 , wherein ...

LIGHT-EMITTING DEVICE AND LIGHT-EMITTING MODULE USING THE SAME

A light-emitting device and a light-emitting module using the same are provided. The light-emitting device includes a substrate module and a light-emitting component. The substrate module includes a substrate, a first conductive layer, an insulation layer and a second conductive layer. The substrate has an upper surface. The insulation layer is formed on the upper surface of the substrate, separates the substrate and the first conductive layer and has an opening. The second conductive layer connects to the upper surface of the substrate and is separated from the first conductive layer. The light-emitting component is disposed on the substrate module and electrically connected to the first conductive layer and the second conductive layer. 1. A light-emitting component , comprising:a semiconductor structure comprising a first semiconductor layer, a second semiconductor layer and a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer;a first insulation layer disposed over the semiconductor structure, the first insulation layer having a first opening exposing a portion of the first semiconductor layer and a second opening exposing the second semiconductor layer, wherein the first insulation layer comprises a single insulation layer or an insulation structure formed of multiple stacked insulation layers with different refractivities;a first electrode layer and a second electrode layer disposed on the first insulation layer, wherein the first electrode layer is electrically connected to the first semiconductor via the first opening and the second electrode layer is electrically connected to the second semiconductor via the second opening; anda pad layer disposed on the first insulation layer and located between the first electrode layer and the second electrode layer, wherein the pad layer is physically and electrically isolated from the first electrode layer and the second electrode layer.2. The light-emitting component ...

Package-On-Package with Cavity in Interposer

A package includes an interposer, which includes a core dielectric material, a through-opening extending from a top surface to a bottom surface of the core dielectric material, a conductive pipe penetrating through the core dielectric material, and a device die in the through-opening. The device die includes electrical connectors. A top package is disposed over the interposer. A first solder region bonds the top package to the conductive pipe, wherein the first solder region extends into a region encircled by the conductive pipe. A package substrate is underlying the interposer. A second solder region bonds the package substrate to the interposer. 1. A package comprising:a package substrate;a device die over and bonded to the package substrate; a core dielectric material; and', 'a conductive pipe penetrating through the core dielectric material;, 'an interposer over the package substrate, the interposer comprisinga first solder region extending into a region encircled by the conductive pipe; anda second solder region bonding the package substrate to the interposer.2. The package of claim 1 , wherein the device die extends into the interposer to bond to the package substrate.3. The package of claim 2 , wherein the device die extends into a through-opening in the interposer claim 2 , and the device die is spaced apart from inner edges of the interposer.4. The package of further comprising a dielectric film between the interposer and the package substrate claim 1 , wherein the second solder region extends into the dielectric film.5. The package of claim 4 , wherein the dielectric film comprises curved sidewalls contacting sidewalls of the second solder region.6. The package of claim 4 , wherein the interposer further comprises a metal pad claim 4 , and the metal pad extends into the dielectric film.7. The package of claim 1 , wherein the interposer further comprises a metal pad contacting a bottom end of the conductive pipe claim 1 , and the first solder region ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls. 1. A semiconductor package , comprising:a package substrate;a processor chip mounted on a first region of the package substrate;a plurality of memory chips mounted on a second region of the package substrate, the second region of the package substrate being spaced apart from the first region of the package substrate;a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate; anda plurality of first bonding wires that connect the plurality of memory chips to the signal transmission device, upper pads in an upper surface portion of the signal transmission device, the upper pads connected to the plurality of first bonding wires;', 'penetrating electrodes in a main body portion of the signal transmission device, the penetrating electrodes connected to the upper pads; and', 'lower pads in a lower surface portion of the signal transmission device, the lower pads connected to the penetrating electrodes and connected to the package substrate via bonding balls., 'wherein the signal ...

SEMICONDUCTOR DEVICES WITH PACKAGE-LEVEL CONFIGURABILITY

A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad. 1. A semiconductor device assembly , comprising:a substrate; a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and', 'a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements;, 'a die coupled to the substrate, the die includingwherein the substrate includes a substrate contact electrically coupled to both the first contact pad and the second contact pad on the die by a single wirebond and a solder ball in electrical contact with the wirebond, the first contact pad and the second contact pad, andwherein the first die further includes a third contact pad electrically coupled to a third circuit on the first die including only passive circuit elements, and wherein the substrate contact is electrically coupled to the third contact pad on the first die by the wirebond, and wherein the solder ball is further in electrical contact with the third contact pad.2. The semiconductor device assembly of claim 1 , wherein the die is a first die claim 1 , further ...

SEMICONDUCTOR DEVICES WITH PACKAGE-LEVEL CONFIGURABILITY

A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad. 1. A semiconductor device assembly , comprising:a substrate; a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and', 'a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements;, 'a die coupled to the substrate, the die includingwherein the substrate includes a substrate contact electrically coupled to both the first contact pad and the second contact pad on the die by a single wirebond and a single solder ball in electrical contact with each of the wirebond, the first contact pad and the second contact pad.2. The semiconductor device assembly of claim 1 , wherein the die is a first die claim 1 , further comprising: a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and', 'a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements;, 'a second die includingwherein the substrate contact is electrically coupled to ...

INTEGRATED CIRCUIT PACKAGE ASSEMBLY

An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package. The first integrated circuit package includes a first integrated circuit die mounted on a first substrate. The second integrated circuit package includes a second integrated circuit die mounted on a second substrate. The second integrated circuit package is disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package and provide electrical signal connections between the first integrated circuit die and the second integrated circuit die. A buffer layer is disposed between the first substrate and the second integrated circuit die to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package. 1. An integrated circuit package assembly , comprising:a first integrated circuit package including a first substrate, and a first die disposed over the first substrate;a molding compound disposed over the first substrate and the first die, wherein a wire bond extends through the molding compound;a second integrated circuit package including a second substrate and a single die, wherein the first integrated circuit package is disposed over the second integrated circuit package and the single die is disposed over the second substrate and beneath the first integrated circuit package; andsolder bumps disposed between a lowermost surface of the first integrated circuit package and an upper surface of the second integrated circuit package, the second integrated circuit package providing electrical signal connections between the first die and the single die;wherein the solder bumps have a height extending between the lowermost surface of first integrated circuit package and the upper surface of the second integrated circuit package, and wherein the solder bumps extend past outer sidewalls of the single die ...

Flexible packages including chips

A flexible package may be provided. The flexible package may include a flexible molding member including a top surface. The flexible package may include a first chip within the flexible molding member, and including a first top surface. The flexible package may include a second chip within the flexible molding member, and including a second top surface. The first top surface may face away from the top surface of the flexible molding member and the second top surface may face towards the top surface of the flexible molding member.

Current sensors and methods

Embodiments relate to current sensors and methods. In an embodiment, a current sensor comprises a leadframe; a semiconductor die coupled to the leadframe; a conductor comprising a metal layer on the semiconductor die, the conductor comprising at least one bridge portion and at least two slots, a first slot having a first tip and a second slot having a second tip, a distance between the first and second tips defining a width of one of the at least one bridge portion, wherein the conductor is separated from the leadframe by at least a thickness of the semiconductor die, and the thickness is about 0.2 millimeters (mm) to about 0.7 mm; and at least one magnetic sensor element arranged on the die relative to and spaced apart from the one of the at least one bridge portion and more proximate the conductor than the leadframe.

PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES

Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites. 1. A method of forming a semiconductor assembly , comprising:forming a conductive pedestal at a first bond-site of a support member, wherein the pedestal has a surface spaced apart from the support member;attaching the support member to a die having a second bond-site;disposing an encapsulant adjacent to the pedestal;removing at least a portion of the encapsulant to at least partially expose the surface of the pedestal; andforming a redistribution structure connected to the surface of the pedestal and the first bond-site and having a third bond-site between the first and second bond-sites and spaced apart from the die.2. The method of wherein removing at least a portion of the encapsulant comprises forming a via through the encapsulant that terminates at the surface of the pedestal.3. The method of claim 2 , further comprising disposing a conductive member in the via and coupling the conductive member to the surface of the pedestal with the conductive member exposed for an electrical connection external to the assembly.4. A method of forming a stacked semiconductor assembly claim 2 , comprising:singulating a first semiconductor assembly having a first die and a first bond-site at a periphery of the first assembly, the first assembly having a first footprint;singulating a second semiconductor assembly along a singulation line, the second semiconductor assembly having a second ...

Flat No-Lead Packages with Electroplated Edges

A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals. A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the hack side of the terminals each include a contact region which lacks the plating layer.

METHOD THEREOF OF PACKAGE STRUCTURE

A method of fabricating a package structure including at least the following steps is provided. A carrier is provided. A first package is formed on the carrier. The first package is formed by at least the following steps. A first redistribution layer is formed on the carrier, wherein the first redistribution layer has a first surface and a second surface opposite to the first surface. A semiconductor die is bonded on the first surface of the first redistribution layer. The semiconductor die is electrically connected to the first redistribution layer through a plurality of conductive wires. An insulating material is formed to encapsulate the semiconductor die and the plurality of conductive wires. A thinning process is performed to obtain an insulating encapsulant by reducing a thickness of the insulating material until a portion of each of the conductive wires is removed to form a plurality of conductive wire segments, wherein the semiconductor die is electrically insulated from the first redistribution layer after the thinning process. A second redistribution layer is formed on a top surface of the insulating encapsulant, and over the semiconductor die. The second redistribution layer is electrically connected to the first redistribution layer and to the semiconductor die by the plurality of conductive wire segments. 1. A method of fabricating a package structure , comprising:providing a carrier; forming a first redistribution layer on the carrier, wherein the first redistribution layer has a first surface and a second surface opposite to the first surface;', 'bonding a semiconductor die on the first surface of the first redistribution layer;', 'electrically connecting the semiconductor die to the first redistribution layer through a plurality of conductive wires;', 'forming an insulating material encapsulating the semiconductor die and the plurality of conductive wires;', 'performing a thinning process to obtain an insulating encapsulant by reducing a thickness of ...

SEMICONDUCTOR DEVICES WITH PACKAGE-LEVEL CONFIGURABILITY

A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad. 1. A semiconductor device assembly , comprising:a substrate; a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element,', 'a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and', 'a third contact pad electrically coupled to a third circuit on the die including only passive circuit elements;, 'a die coupled to the substrate, the die includingwherein the substrate includes a substrate contact electrically coupled to both the first contact pad and the second contact pad on the die.2. The semiconductor device assembly of claim 1 , wherein the first circuit is a driver circuit.3. The semiconductor device assembly of claim 1 , wherein each of the second circuit and the third circuit includes one or more capacitors to provide electrostatic discharge (ESD) protection.4. The semiconductor device assembly of claim 1 , wherein the die is a NAND memory die.5. The semiconductor device assembly of claim 1 , wherein the substrate contact is electrically ...

Manufacturing method of semiconductor device

In a manufacturing method of a semiconductor device according to an embodiment, a plurality of semiconductor packages each including a semiconductor chip mounted on a wiring board and a sealing resin layer as objects to be processed, and a tray including a plurality of housing parts are prepared. A depressed portion having a non-penetrating shape or a penetrating shape is formed in the housing part. The semiconductor packages are disposed in the plural housing parts respectively. By sputtering a metal material on the semiconductor package housed in the tray, a conductive shield layer is formed.

Isolation of circuit elements using front side deep trench etch

An integrated circuit is formed by forming an isolation trench through at least a portion of an interconnect region, at least 40 microns deep into a substrate of the integrated circuit, leaving at least 200 microns of substrate material under the isolation trench. Dielectric material is formed in the isolation trench at a substrate temperature no greater than 320° C. to form an isolation structure which separates an isolated region of the integrated circuit from at least a portion of the substrate. The isolated region contains an isolated component. The isolated region of the integrated circuit may be a region of the substrate, and/or a region of the interconnect region. The isolated region may be a first portion of the substrate which is laterally separated from a second portion of the substrate. The isolated region may be a portion of the interconnect region above the isolation structure.

Light Coupling Device and Methods of Forming Same

An embodiment is a semiconductor device comprising an optical device over a first substrate, a vertical waveguide on a top surface of the optical device, the vertical waveguide having a first refractive index, and a capping layer over the vertical waveguide, the capping layer configured to be a lens for the vertical waveguide and the capping layer having a second refractive index.

Emi shielding for discrete integrated circuit packages

A method is disclosed for manufacturing a discrete package for housing at least one integrated circuit die with electromagnetic interference shielding. The method may utilize a lead frame with a central die paddle and outwardly extending leads. The die paddle may have a top surface and an opposing bottom surface. The method may also have at least one integrated circuit die with a top surface and an opposing bottom surface. The integrated circuit die may be attached to the top surface of the die paddle. At least one conductive material bond may be established between the lead frame and the integrated circuit die. A dielectric material over mold may encapsulate the integrated circuit die and lead frame. A second dielectric material over mold may encapsulate the integrated circuit die and the lead frame. Further, a conductive coating may encapsulate the top and side surfaces of the package.

System and method of sensing current in a power semiconductor device

A current sensor to be connected in series with a power semiconductor device between a voltage supply terminal and ground. The current sensor includes a first terminal to be coupled to the power semiconductor device, a second terminal to be coupled to one of the voltage supply terminal and ground, and a current mirror. The current mirror includes a first MOSFET and a second MOSFET each having a source, a drain, and a gate. The source of the first MOSFET is connected to the source of the second MOSFET and to the second terminal, the drain of the first MOSFET is connected to the first terminal, and the gate of the first MOSFET is connected to the gate of the second MOSFET.

Semiconductor module and semiconductor module manufacturing method

A semiconductor module includes block-shaped first and second lower base members provided by bonding of flat lower surfaces on an insulated circuit board and having bottomed first and second hole portions open in upper surfaces in upper portions of the first and second lower base members, tubular first and second upper slide support members inserted in the first and second hole portions in a state where at least a part of outside surfaces is in contact with inside walls of the first and second hole portions, first and second pins inserted in contact with the insides of the first and second upper slide support members, and a sealing resin sealing the first and second pins except for the upper portions of the first and second pins.

Semiconductor device and method of manufacturing the same

Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

Leadframe, Semiconductor Package Including a Leadframe and Method for Producing a Leadframe

A lead frame includes a die pad and a lead finger with an inner portion which is configured to be electrically connected to contact pads of a die and with an outer portion which has an attach portion. The attach portion is configured to be soldered to an external solder pad, wherein the attach portion has a width, a length and a thickness. An opening extends through the thickness of the attach portion.

Package-on-package assembly with wire bonds to encapsulation surface

A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.

Semiconductor package and method of manufacturing the semiconductor package

In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices is stacked on the package substrate and spaced apart from the first semiconductor device, the electrostatic discharge structure being interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

To enhance the reliability of a semiconductor device. A semiconductor device is provided that includes a semiconductor element having a first pad, a frame member having a second pad, a connection member that contains at least one of copper and silver and connects the first pad and the second pad, and a sealing portion that is formed of resin composition containing no sulfur and seals the semiconductor element, the frame member, and the connection member, wherein arithmetic mean roughness of an upper surface of the first pad is equal to or greater than 0.02 μm. Arithmetic mean roughness of an upper surface of the second pad may be greater than the arithmetic mean roughness of the first pad. Sulfur content contained in the resin composition may be less than NHion content contained in the resin composition. 1. A semiconductor device comprising:a semiconductor element having a first pad;a frame member having a second pad;a connection member that contains at least one of copper and silver and connects the first pad and the second pad; anda sealing portion that is formed of resin composition containing no sulfur and seals the semiconductor element, the frame member, and the connection member,wherein arithmetic mean roughness of an upper surface of the first pad is equal to or greater than 0.02 μm.2. The semiconductor device according to claim 1 ,wherein arithmetic mean roughness of an upper surface of the second pad is greater than the arithmetic mean roughness of the upper surface of the first pad.3. A semiconductor device comprising:a semiconductor element having a first pad;a frame member having a second pad;a connection member that contains at least one of copper and silver and connects the first pad and the second pad; anda sealing portion that is formed of resin composition containing no sulfur and seals the semiconductor element, the frame member, and the connection member,wherein arithmetic mean roughness of an upper surface of the second pad is greater than ...

Articles and methods for rapid manufacturing of solid state light sources

Rapid manufacturing processes and designs based on solid luminescent elements form solid state light sources. Direct attach, as well as other LED types, are embedded or affixed to the solid luminescent elements to form low cost solid state light sources.

Robust Integrated Circuit Package

The base of an integrated circuit package comprises a first side, and a second side opposing the first side. The base further comprises, a base mounting section, a die mounting section, and a recessed section. The recessed section comprises a recess between the die mounting section and the base mounting section. The base further comprises an opening extending through the base from the first side to the second side. At least a portion of the recess intersects with the opening.

Organic Lighting Device and Lighting Equipment

An organic luminous means and an illumination device comprising such a luminous means are specified. An optical display apparatus, emergency lighting, motor vehicle interior lighting, an item of furniture, a construction material, a glazing and a display comprising such a luminous means and, respectively, comprising an illumination device having such a luminous means are furthermore specified.

Semiconductor device and manufacturing method thereof

A semiconductor device according to an embodiment includes a metal part including a first surface and a second surface on an opposite side to the first surface. A semiconductor chip is mounted on the first surface of the metal part and is electrically connected to the metal part. A terminal part includes a third surface being in contact with the second surface of the metal part, a fourth surface on an opposite side to the third surface, and side surfaces between the third surface and the fourth surface. A resin is provided on the second surface of the metal part and the side surfaces of the terminal part.

Semiconductor device

A semiconductor device capable of suppressing the calorific value at the central portion of a wire bonding area is provided. A semiconductor device includes a plurality of IGBT cells in a cell area. An emitter electrode serves as a current path when a plurality of IGBT cells are in conductive state, and is formed to cover a plurality of IGBT cells. A wire is bonded to the emitter electrode. A dummy cell which does not perform a bipolar operation, is formed at least below a central portion of a wire bonding area which is an area at which the wire and the emitter electrode are bonded.

SEMICONDUCTOR PACKAGE STRUCTURE WITH HEAT SINK AND METHOD PREPARING THE SAME

The present disclosure provides a chip package structure having a heat sink and a method making the same. The method includes: bonding a chip to a top surface of a package substrate and forming a heat-conducting lead having an arc-shape and placed on the chip in a vertical direction, a first end of the heat-conducting lead is connected with a surface of the chip, and a second end is connected with a solder ball; forming a plastic package material layer that protects the chip and the heat-conducting lead; forming a heat-conducting adhesive layer on the surface of the plastic package material layer, where the heat-conducting adhesive layer is connected with the solder ball on the second end of the heat-conducting lead; and forming a heat dissipation layer on a surface of the heat-conducting adhesive layer. With the present disclosure, the heat dissipation efficiency of the chip is effectively improved. 1. A method for making a chip package structure having a heat sink , comprising:providing a package substrate and a chip;bonding the chip to a top surface of the package substrate;forming a heat-conducting lead on the chip, wherein the heat-conducting lead comprises an arc-shaped vertical wire having a first end and a second end opposite to the first end, wherein the first end is connected with a surface of the chip through a wire bonding bump and the second end is connected with a solder ball;disposing a plastic package material layer that packages the chip and the heat-conducting lead, wherein a surface of the plastic package material layer exposes the solder ball on the second end of the heat-conducting lead;forming a heat-conducting adhesive layer on the surface of the plastic package material layer, wherein the heat-conducting adhesive layer is in contact with the solder ball on the second end of the heat-conducting lead; andforming a heat dissipation layer on a surface of the heat-conducting adhesive layer.2. The method for making the chip package structure having ...

PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES

Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites. 1. A method of forming a semiconductor assembly , comprising:forming a conductive pedestal at a first bond-site of a support member, wherein the pedestal has a surface spaced apart from the support member;attaching the support member to a die having a second bond-site;disposing an encapsulant adjacent to the pedestal;removing at least a portion of the encapsulant to at least partially expose the surface of the pedestal; andforming a redistribution structure connected to the surface of the pedestal and the first bond-site and having a third bond-site between the first and second bond-sites and spaced apart from the die.2. The method of wherein removing at least a portion of the encapsulant comprises forming a via through the encapsulant that terminates at the surface of the pedestal.3. The method of claim 2 , further comprising disposing a conductive member in the via and coupling the conductive member to the surface of the pedestal with the conductive member exposed for an electrical connection external to the assembly.4. A method of forming a stacked semiconductor assembly claim 2 , comprising:singulating a first semiconductor assembly having a first die and a first bond-site at a periphery of the first assembly, the first assembly having a first footprint;singulating a second semiconductor assembly along a singulation line, the second semiconductor assembly having a second ...

SEMICONDUCTOR DEVICE, SOLID-STATE IMAGE PICKUP ELEMENT, IMAGE PICKUP DEVICE, AND ELECTRONIC APPARATUS

The present disclosure relates to a semiconductor device, a solid-state image pickup element, an image pickup device, and an electronic apparatus that are enabled to reduce restrictions on materials and restrictions on device configuration. A CSP imager and a mounting substrate are connected together with a connection portion other than a solder ball. With such a configuration, restrictions on materials and restrictions on device configuration are reduced, which has conventionally occurred because it is limited to a configuration in which solder balls are used for connection. The present disclosure can be applied to image pickup devices.

METHOD OF PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR COMPONENT, OPTOELECTRONIC SEMICONDUCTOR COMPONENT, AND TEMPORARY CARRIER

A method of producing an optoelectronic semiconductor component includes providing a carrier including two metal layers, wherein the metal layers are detachable from one another, securing an optoelectronic semiconductor chip on the first metal layer of the carrier, and mechanically detaching the second metal layer from the first metal layer. 115-. (canceled)16. A method of producing an optoelectronic semiconductor component comprising:providing a carrier comprising two metal layers, wherein the metal layers are detachable from one another,securing an optoelectronic semiconductor chip on the first metal layer of the carrier, andmechanically detaching the second metal layer from the first metal layer.17. The method according to claim 16 , wherein the metal layers comprise copper or consist of copper.18. The method according to claim 16 , wherein the carrier comprises an intermediate layer claim 16 , optionally a chromium layer claim 16 , between the two metal layers.19. The method according to claim 16 , further comprising:applying a photoresist on the first metal layer,patterning the photoresist such that regions composed of the photoresist comprising a predefined cross section are present on the first metal layer,electrolytically applying a further metal on the free regions of the first metal layer, wherein the further metal comprises a greater thickness than the photoresist and partly projects laterally beyond regions of the photoresist, andremoving the photoresist, wherein a body composed of the further metal arises, said body comprising a laterally projecting upper edge region.20. The method according to claim 19 , wherein the electrolytically applied metal is copper or nickel.21. The method according to claim 19 , wherein the electrolytically applied metal comprises a thickness of 20 to 60 μm.22. The method according to claim 16 , wherein applying a chromium layer on a metal layer, wherein the metal layer comprises a thickness of 30 to 200 μm,', 'applying a ...

Integrated circuit package with printed circuit layer

An integrated circuit (IC) package including an IC die and a conductive ink printed circuit layer electrically connected to the IC die.

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant and a RDL structure, the encapsulant encapsulate sidewalls of the die. The RDL structure is disposed on the die and the encapsulant. The RDL structure includes a first dielectric structure and a first redistribution layer. The first dielectric structure includes a first dielectric material layer and a second dielectric material layer on the first dielectric material layer. The first redistribution layer is embedded in the first dielectric structure and electrically connected to the die, the redistribution layer comprises a first seed layer and a first conductive layer disposed on the first seed layer. A topmost surface of the first seed layer and a topmost surface of the first conductive layer are substantially level with a top surface of the second dielectric material layer. 1. A package structure , comprising:a die;an encapsulant, encapsulating sidewalls of the die; and a first dielectric structure comprising a first dielectric material layer and a second dielectric material layer on the first dielectric material layer; and', 'a first redistribution layer, embedded in the first dielectric structure and electrically connected to the die, the redistribution layer comprises a first seed layer and a first conductive layer disposed on the first seed layer,', 'wherein a topmost surface of the first seed layer and a topmost surface of the first conductive layer are substantially level with a top surface of the second dielectric material layer., 'a redistribution layer (RDL) structure, disposed on the die and the encapsulant, wherein the RDL structure comprises2. The package structure of claim 1 , wherein the first conductive layer is surrounded by the first seed layer and separated from the first dielectric structure.3. The package structure of claim 1 , wherein the first redistribution layer comprises:a via, penetrating through the first dielectric ...

Integrated circuit device

An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, and an internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the second bonding pad structure via the internal bonding wire. The integrated circuit device having a better electrical performance is provided by eliminating internal resistance drop in power supply trails or ground trails, and improving signal integrity of the integrated circuit device.

Semiconductor dies with recesses, associated leadframes, and associated systems and methods

Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one embodiment includes a semiconductor die having a first surface and a second surface facing opposite from the first surface, with the first surface having a die recess. The system can further include a support paddle carrying the semiconductor die, with at least part of the support paddle being received in the die recess. In particular embodiments, the support paddle can form a portion of a leadframe. In other particular embodiments, the support paddle can include a paddle surface that faces toward the semiconductor die and has an opening extending through the paddle surface and through the support paddle.

Methods for Making Multi-Die Package With Bridge Layer

A device is provided. The device includes a bridge layer over a first substrate. A first connector electrically connecting the bridge layer to the first substrate. A first die is coupled to the bridge layer and the first substrate, and a second die is coupled to the bridge layer. 1. A device , comprising:a first substrate comprising a plurality of first contacts extending along a first surface of the first substrate;a bridge overlying the first substrate, the bridge comprising a plurality of second contacts extending along a second surface of the bridge, second contacts of the plurality of second contacts being positioned along one or more edges of the second surface of the bridge, and the second surface of the bridge facing away from the first surface of the first substrate;a plurality of electrical connectors, wherein the plurality of electrical connectors electrically connect the plurality of second contacts to the plurality of first contacts, and each of the plurality of electrical connectors extends along a sidewall of the bridge;a first die overlying the bridge, wherein a perimeter of the first die is within a perimeter of the bridge in a plan view; anda second die overlying the bridge, wherein the second die partially overlaps the bridge and extends beyond the bridge in the plan view.2. The device according to claim 1 , wherein the first die comprises a plurality of blocks claim 1 , and each of the plurality of blocks comprises a respective plurality of third contacts.3. The device according to claim 2 , wherein the second die is connected to the respective plurality of third contacts of each of the plurality of blocks of the first die by a plurality of redistribution layers of the bridge.4. The device according to claim 1 , wherein each of the plurality of electrical connectors is a conductive bump that contacts the sidewall of the bridge.5. The device according to claim 4 , wherein a height of the plurality of electrical connectors over the first substrate ...

Module Comprising a Semiconductor Chip

A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element.

SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE ARRAY, AND IMAGE FORMATION APPARATUS

A semiconductor device includes a first semiconductor chip including a first upper surface and a first electrode pad provided on the first upper surface; a circuit component including a second upper surface disposed at a position lower than the first upper surface and a second electrode pad provided on the second upper surface, the circuit component being juxtaposed to the first semiconductor chip; an insulation member provided on the first upper surface and located closer to the second electrode pad than the first electrode pad is; and a wire extending from the first electrode pad to the second electrode pad and passing above the insulation member. 1. A semiconductor device comprising:a first semiconductor chip including a first upper surface and a first electrode pad provided on the first upper surface;a circuit component including a second upper surface disposed at a position lower than the first upper surface and a second electrode pad provided on the second upper surface, the circuit component being juxtaposed to the first semiconductor chip;an insulation member provided on the first upper surface and located closer to the second electrode pad than the first electrode pad is; anda wire extending from the first electrode pad to the second electrode pad while passing above the insulation member.2. The semiconductor device according to claim 1 , wherein an end portion of the insulation member on the side of the circuit component overlaps an end portion of the first upper surface on the side of circuit component.3. The semiconductor device according to claim 1 , wherein an end portion of the insulation member on the side of circuit component is located between an end portion of the first upper surface on the side of the circuit component and the first electrode pad.4. The semiconductor device according to claim 1 , wherein an end portion of the insulation member on the side of the circuit component protrudes outward from an end portion of the first upper surface on ...

Universal Surface-Mount Semiconductor Package

A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly coplanar feet that protrude from a plastic body, facilitating mounting the packages on printed circuit boards using wave-soldering techniques.

Integrated circuit package including miniature antenna

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna, each of the five sections or segments forming a pair of angles with each adjacent segment or section, wherein the smaller angle of each of the four pairs of angles between sections or segments is less than 180° (i.e., no pair of sections or segments define a longer straight segment), wherein at least two of the angles are less than 115°, wherein at least two of the angles are not equal, and wherein the curve fits inside a rectangular area the longest edge of which is shorter than one-fifth of the longest free-space operating wavelength of the antenna.

Flat No-Lead Packages with Electroplated Edges

A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals. 1. A packaged semiconductor flat no-lead device (packaged semiconductor device) , comprising:a flat no-lead lead frame having a semiconductor die including bond pads thereon mounted on a die pad of said lead frame with bond wires between said bond pads and terminals of said lead frame, and plastic encapsulation except on a back side of said lead frame to expose said die pad to provide an exposed thermal die pad and to expose a back side of said terminals and side walls of said terminals;a stack of plating layers on said back side and on said exposed side walls of said terminals, said stack of plating layers includes nickel, palladium, and gold;wherein said exposed thermal pad and said back side of said terminals each include a contact region which lacks said stack of plating layers.2. The packaged semiconductor device of claim 1 , wherein said plastic encapsulation is at a first width on a top portion of said packaged semiconductor device and at a second width at a bottom of said packaged semiconductor device claim 1 , andwherein said first width is greater than said second width to provide a side wall step along an edge of said plastic encapsulation.3. The packaged semiconductor device of claim 1 , wherein said lead frame includes a quad-flat no-lead (QFN) or a dual-flat no-lead (DFN).4. The packaged semiconductor device of claim 1 , wherein said lead frame includes copper or a copper alloy.5. The packaged semiconductor device of claim 1 , wherein said contact region is 0.8 mil (0.0206 mm) to 5 mil (0.127 mm) in diameter. This application is a Divisional of Ser. No. 15/438,533 filed Feb. 21, 2017, which is a Continuation of Ser. No. 15/162,807 filed May 24, 2016, that is now U.S. Pat. No. 9,576,886 (granted ...

LED ASSEMBLY

This disclosure discloses an LED assembly. The LED assembly includes a transparent mount with a top surface and a bottom surface opposite to the top surface, an LED chip arranged on the top surface, an electrode plate, a first phosphor layer having a first phosphor, and a second phosphor layer having a second phosphor, wherein the transparent mount and the electrode plate substantially have a same width. The electrode plate is arranged on an edge of the top surface and electrically connected to the LED chip. 1. An LED assembly , comprising:a substrate comprising a first top surface;a mount disposed on the first top surface and having a first inner side surface and a second inner side surface facing the first inner side surface;a plurality of LED chips disposed on the first top surface in an arrangement between the first inner side surface and the second inner side surface, and comprising a second top surface;an electrode plate formed on the mount, electrically connected to the plurality of LED chips, and comprising a third top surface;a phosphor layer covering the plurality of LED chips, the mount, and the electrode plate, wherein the third top surface is higher than the second top surface in an elevation based on the first top surface.2. The LED assembly of claim 1 , wherein the electrode plate electrically connected to the plurality of LED chips by a plurality of bonding wires.3. The LED assembly of claim 2 , wherein the phosphor layer covers the plurality of bonding wires.4. The LED assembly of claim 1 , further comprising a glue layer formed between the substrate and the mount.5. The LED assembly of claim 1 , further comprising an adhesive layer formed between the substrate and the plurality of LED chips.6. The LED assembly of claim 1 , wherein the phosphor layer comprises a curve surface.7. The LED assembly of claim 1 , wherein the first inner side surface and the second inner side surface are substantially perpendicular to the substrate.8. The LED assembly of ...

Integrated Circuit Package Including Miniature Antenna

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna, each of the five sections or segments forming a pair of angles with each adjacent segment or section, wherein the smaller angle of each of the four pairs of angles between sections or segments is less than 180° (i.e., no pair of sections or segments define a longer straight segment), wherein at least two of the angles are less than 115°, wherein at least two of the angles are not equal, and wherein the curve fits inside a rectangular area the longest edge of which is shorter than one-fifth of the longest free-space operating wavelength of the antenna.

Chip package and method for forming the same

A chip package including a first device substrate is provided. The first device substrate is attached to a first surface of a second device substrate. A third device substrate is attached to a second surface of the second device substrate opposite to the first surface. An insulating layer covers the first, second and third device substrates and has at least one opening therein. At least one bump is disposed under a bottom of the opening. A redistribution layer is disposed on the insulating layer and electrically connected to the bump through the opening. A method for forming the chip package is also provided.

OPTOELECTRONIC COMPONENT

The invention relates to an optoelectronic component () comprising a semiconductor layer sequence () having an active layer (), wherein the active layer () is designed to produce or absorb electromagnetic radiation in intended operation. Furthermore, the component () comprises a first contact structure () and a second structure (), by means of which the semiconductor layer sequence () can be electrically contacted in intended operation. In operation, a voltage is applied to the contact structures (), wherein an operation-related voltage difference ΔUbet between the contact structures () arises. When the voltage difference is increased, a first arc-over occurs in or on the component () between the two contact structures (). A spark gap () between the contact structures (), which arises in the event of the first arc-over, passes predominantly through a surrounding medium in the form of gas or vacuum and/or through a potting. The first arc-over occurs at a voltage difference of 2·ΔUbet at the earliest. 1. An optoelectronic component , comprising:a semiconductor layer sequence with an active layer, wherein the active layer is set up to generate or absorb electromagnetic radiation during normal operation,a first contact structure and a second contact structure via which the semiconductor layer sequence is electrically contacted during normal operation, wherein{'sub': 'bet', 'during operation, the contact structures are subjected to a voltage and an operational voltage difference ΔUbetween the contact structures occurs,'}a first electrical flashover is formed in or on the component between the two contact structures when the voltage difference is increased,a spark gap produced between the contact structures during the first flashover runs predominantly through a surrounding medium in the form of gas or vacuum and/or through a potting around the component,{'sub': 'bet', 'the first flashover occurs at the earliest at a voltage difference of 2·ΔU.'}2. An optoelectronic ...