Leistungshalbleiterchip mit zwei Metallschichten auf einer Fläche

Ein Halbleiterchip beinhaltet eine Leistungstransistorschaltung mit mehreren aktiven Transistorzellen. Eine erste Lastelektrode und eine Steuerelektrode sind auf einer ersten Fläche des Halbleiterchips angeordnet, wobei die erste Lastelektrode eine erste Metallschicht beinhaltet. Eine zweite Lastelektrode ist auf einer zweiten Fläche des Halbleiterchips angeordnet. Eine zweite Metallschicht ist über der ersten Metallschicht angeordnet, wobei die zweite Metallschicht elektrisch gegenüber der Leistungstransistorschaltung isoliert ist und die zweite Metallschicht über einen Bereich der Leistungstransistorschaltung angeordnet ist, der mindestens eine der mehreren aktiven Transistorzellen umfasst.

PROCEDURE FOR THE WIRE BONDING OF A MICROELECTRONIC SEMICONDUCTOR CHIP

Semiconductor device

WIRE BONDING METHOD, WIRE BONDING APPARATUS AND SEMICONDUCTOR DEVICE PRODUCED BY THE SAME

SEMICONDUCTOR CHIP AND METHOD FOR FABRICATING THE SAME

A semiconductor chip includes a silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said metallization structure and over said first and second dielectric layers, an opening in said passivation layer exposing a pad of said metallization structure, a polymer bump over said passivation layer, wherein said polymer bump has a thickness of between 5 and 25 micrometers, an adhesion/barrier layer on said pad exposed by said opening, over said passivation layer and on a top surface and a portion of sidewall(s) of said polymer bump, a seed layer on said adhesion/barrier layer; and a third metal layer on said seed layer.

Method for fabricating semiconductor package with circuit side polymer layer

A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a circuit side having a pattern of die contacts, planarized wire bonding contacts bonded to the die contacts, and a planarized polymer layer on the circuit side configured as stress defect barrier. A method for fabricating the package includes the steps of forming bumps on the die, encapsulating the bumps in a polymer layer, and then planarizing the polymer layer and the bumps to form the planarized wire bonding contacts. The method also includes the steps of attaching and wire bonding the die to the substrate, and then forming the die encapsulant on the die.

Integrated circuit package bond pad having plurality of conductive members

An integrated circuit package bond pad includes an insulating layer and an electrode located over the insulating layer. The electrode has a first surface configured to be bonded to external circuitry and a second surface opposite the first surface. A plurality of conductive members is located in the insulating layer, wherein ones of the plurality of conductive members contact the second surface of the electrode.

Etching platinum-containing thin film using protective cap layer

A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.

Structure and method for bond pads of copper-metallized integrated circuits

A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of first barrier metal, deposited on the non-oxidized copper surface, having a copper diffusion coefficient of less than 1x10E-23 cm2/s at 250° C. and a thickness from about 0.5 to 1.5 mum. It further comprises a layer of second barrier metal on the layer of first barrier metal, having a diffusion coefficient of the first barrier metal of less than 1x10E-14 cm2/s at 250° C. and a thickness of less than 1.5 mum. It finally comprises an outermost layer of bondable metal, onto which a metal wire is bonded for metallurgical connection. The first barrier metal is selected from a group consisting of nickel, cobalt, chromium, molybdenum, titanium, tungsten, and alloys thereof. The second barrier metal is selected from a group consisting of palladium, cobalt, platinum and osmium. The outermost ...

SENSOR PACKAGE

A sensor package is disclosed. One embodiment provides a sensor device having a carrier, a semiconductor sensor mounted on the carrier and an active surface. Contact elements are electrically connecting the carrier with the semiconductor sensor. A protective layer made of an inorganic material covers at least the active surface and the contact elements.

A COMMON BALL-LIMITING METALLURGY FOR I/O SITES

본 발명은 C4(controlled-collapse chip connections)와 같은 솔더 범프 플립 칩 접속 및 와이어본드 모두에 적합한 공통 입력-출력(I/O) 영역을 형성하는 프로세스에 관한 것이다. 본 발명은 상호접속 재료로서 구리를 사용하는 반도체 칩에 특히 적합한데, 이러한 칩을 제조하는데 사용된 연성 유전체는 결합력으로 인해 손상되기 쉽다. 본 발명은 패드의 상부면 상에 귀금속(26)을 갖는 영역을 제공하는 한편 금속 상호 접속부의 높은 도전율을 유지하도록 확산 장벽(22)을 제공함으로써 손상의 위험을 감소시킨다. 기판(20) 내에 형성된 피처(21) 내에 금속층을 선택적으로 증착시키는 방법을 제공함으로써, 기판(20) 내에 I/O 영역을 형성하는 프로세스 단계가 감소된다. 본 발명의 I/O 영역은 와이어본드 또는 솔더 범프 접속에 사용될 수도 있기 때문에, 칩 상호접속에 대한 유연성을 증가시키며, 또한 프로세스 비용을 저감한다. The present invention relates to a process for forming a common input-output (I / O) region suitable for both solder bump flip chip connections and wirebonds, such as controlled-collapse chip connections (C4). The present invention is particularly suitable for semiconductor chips that use copper as the interconnect material, where the flexible dielectric used to make such chips is susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing an area with precious metals 26 on the top surface of the pad while providing a diffusion barrier 22 to maintain high conductivity of the metal interconnects. By providing a method for selectively depositing a metal layer in a feature 21 formed in the substrate 20, the process step of forming an I / O region in the substrate 20 is reduced. Since the I / O region of the present invention may be used for wirebond or solder bump connections, it increases flexibility for chip interconnection and also reduces process costs.

Layer structure for electrical contacting of semiconductor components

A layer structure for the electrical contacting of a semiconductor component having integrated circuit elements and integrated connecting lines for the circuit elements, which is suitable in particular for use in a chemically aggressive environment and at high temperatures, i.e., in so-called “harsh environments,” and is simple to implement. This layer structure includes at least one noble metal layer, in which at least one bonding island is formed, the noble metal layer being electrically insulated from the substrate of the semiconductor component by at least one dielectric layer, and having at least one ohmic contact between the noble metal layer and an integrated connecting line. The noble metal layer is applied directly on the ohmic contact layer.

Compound semiconductor device and manufacturing method thereof

A pad electrode of a field effect transistor is formed solely of a pad metal layer without providing a gate metal layer. A high concentration impurity region is provided below the pad electrode, and the pad electrode is directly contacted to a substrate. Predetermined isolation is ensured by the high concentration impurity region. Accordingly, in a structure not requiring a nitride film as similar to the related art, it is possible to avoid defects upon wire boding attributing to hardening of the gate metal layer. Therefore, in the case of a buried gate electrode structure for enhancing characteristics of the field effect transistor, it is possible to enhance reliability and yields.

Method of fabricating gold bumps on IC's and power chips

A method for depositing gold bumps on metallized pads of semiconductor chips uses a commercially available thermocompression or thermosonic gold wire bonder. The method includes the steps of depositing a gold ball with an attached wire on the metallized pad, and removing the wire so that a gold bump remains on the pad.

LED leadframe or LED substrate, semiconductor device, and method for manufacturing LED leadframe or LED substrate

An LED leadframe or LED substrate includes a main body portion having a mounting surface for mounting an LED element thereover. A reflection metal layer serving as a reflection layer for reflecting light from the LED element is disposed over the mounting surface of the main body portion. The reflection metal layer comprises an alloy of platinum and silver or an alloy of gold and silver. The reflection metal layer efficiently reflects light emitted from the LED element and suppresses corrosion due to the presence of a gas, thereby capable of maintaining reflection characteristics of light from the LED element.

Semiconductor device has multilayer wiring structure buried in insulating layer, and at least one pad electrode connected to multilayer wiring and covered with protective layer

A semiconductor device has semiconductor substrate covered with an insulating layer; a multilayer wiring structure buried in the insulating layer; and at least one pad electrode connected to the multilayer wiring. The pad electrode is covered with a protective layer having at least one opening exposing the surface of the pad electrode. A semiconductor device comprises semiconductor substrate (1); an insulating layer (2,7,10,14,18,22); a multilayer wiring structure buried in the insulating layer; at least one pad electrode (26) connected to the multilayer wiring; and a protective layer (27) covering the pad electrode and has at least one opening (29) exposing the surface of the pad electrode. The wiring structure comprises multilayer wiring film (9,13,17,21,25) and at least one via hole (8,11,15,19,23) for connecting the wiring film layers. A surface of the insulating layer contacts with a metal layer consisting of precious metal and alloys containing precious metal. Independent claims are ...

Method for preparing a conductive pad for electrical connection and conductive pad formed

CONTACTING STRUCTURE OF AN INTEGRATED ACHIEVEMENT CIRCUIT

SEMICONDUCTOR CHIP AND MANUFACTURING METHOD FOR THE SAME

PURPOSE: To provide a semiconductor chip in which a pad for external connection is hardly corroded regardless of the connection condition of a wire. CONSTITUTION: An opening 17B is made in a surface protection film 16 around the periphery of a master chip 1 so that an inner wiring 15 is partly exposed over the surface protection film 16, and an outer connection pad 15B is formed thereby. A wire connection part 12 using the same oxidation resistant metallic material as a bump BM is formed projecting over the external connection pad 15B so as to connect a bonding wire. © KIPO & JPO 2002 ...

SEMICONDUCTOR DEVICE INCLUDING VOLTAGE CONVERTER CIRCUIT, AND METHOD OF MAKING THE SEMICONDUCTOR DEVICE

Leadframe or substrate for LED, semiconductor device, and method for manufacturing leadframe or substrate for LED

A leadframe or a substrate (10) for an LED is provided with a main body section (11) having the placing surface (11a), on which the LED element (21) is placed. On the placing surface (11a) of the main body section (11), a reflecting metal layer (12) that functions as a reflecting layer for reflecting light emitted from the LED element (21) is provided. The reflecting metal layer (12) is composed of an alloy of platinum and silver or an alloy of gold and silver. With the reflecting metal layer (12), the light emitted from the LED element (21) is efficiently reflected, and the characteristics of reflecting the light emitted from the LED element (21) can be maintained by suppressing corrosion due to a gas.

Wire bonding process for copper-metallized integrated circuits

A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of barrier metal that resists copper diffusion, deposited on the non-oxidized copper surface in a thickness such that the barrier layer reduces the diffusion of copper at 250° C. by more than 80% compared with the absence of the barrier metal. The structure further comprises an outermost bondable layer which reduces the diffusion of the barrier metal at 250° C. by more than 80% compared with the absence of the bondable metal. Finally, a metal wire is bonded to the outermost layer for metallurgical connection. The barrier metal is selected from a group consisting of nickel, cobalt, chromium, molybdenum, titanium, tungsten, and alloys thereof. The outermost bondable metal layer is selected from a group consisting of gold, platinum, and silver.

Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion

A semiconductor device including a contact pad and circuit metallization on the surface of an integrated circuit (IC) chip comprises a stack of protection layers over the surface of the chip. The stack consists of a first inorganic layer (303, preferably silicon nitride) on the chip surface, followed by a polymer layer (306, preferably benzocyclobutene) on the first inorganic layer (303), and finally an outermost second inorganic layer (310, preferably silicon dioxide) on the polymer layer (303). A window (301a) in the stack of layers exposes the metallization (301) of the IC. A patterned seed metal layer (307, preferably copper) is on the metallization (301) in the window and on the second inorganic layer (310) around the window. A buffer metal layer (308, preferably copper) is positioned on the seed metal layer (307). A metal reflow element (309) is attached to the buffer metal (308).

Semiconductor device having a multilayer wiring structure and pad electrodes protected from corrosion, and method for fabricating the same

The present invention provides a semiconductor device which can prevent the oxidization of the surfaces of pad electrodes to enhance the connecting strength between the pad electrodes and external terminals. The semiconductor device according to the present invention comprises pad electrodes for use in connecting external electrodes and a multilayer wiring structure connected to the pad electrodes, wherein one surface of an insulating layer covering the pad electrodes and having openings over the pad electrodes for exposing the surfaces of the pad electrodes is in contact with a metal layer formed from one selected from precious metals and alloys containing the precious metals as main components.

Kontaktierungsstruktur einer integrierten Leistungsschaltung

Integrated circuit chip using top post-passivation technology and bottom structure technology

Circuitry component structure and method for forming the same

INTEGRATED CIRCUIT CHIP USING TOP POST-PASSIVATION TECHNOLOGY AND BOTTOM STRUCTURE TECHNOLOGY

COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Post passivation structure for a semiconductor device and packaging process for same

A post passivation rerouting support structure comprises a relatively thin support layer above the passivation layer to support the RDL, and a relatively thick support layer for fine pitch interconnects extending from the RDL and terminating as contact structures at the surface of the thick support layer, for a next level packaging structure. The thick support layer is planarized before defining the contact structures. The thick support layer may be formed after the conducting posts have been formed, or the thick support layer is formed before forming the conducting posts in vias formed in the thick support layer. An encapsulating layer may be provided above the thick support layer, which top surface is planarized before defining the contact structures. The encapsulating layer and the further support layer may be the same layer.

Semiconductor device

There is provided a semiconductor device having excellent moisture resistance and high temperature storage properties. The semiconductor device includes a lead frame that has a die pad and an inner lead, as a substrate, a semiconductor element that is mounted on the die pad, an electrode pad that is provided in the semiconductor element, a copper wire that connects the inner lead provided on the substrate and the electrode pad, and an encapsulant resin that encapsulates the semiconductor element and the copper wire. A region of the electrode pad disposed within a range of at least equal to or less than 3 m from a junction surface with the copper wire in a depth direction includes a metal, which is less likely to be ionized than aluminum, as a main component, and a content of sulfur in the copper wire is equal to or more than 15 ppm and equal to or less than 100 ppm with respect to a total amount of the copper wire.

SEMICONDUCTOR CHIP EQUIPPED WITH JUNCTION INTEGRATION ON ACTIVE CIRCUIT AND ENHANCED IN HEAT-RESISTANT PROPERTIES

(57)【要約】 【課題】 能動回路の上に集積された接合を有し製造が 容易な熱的に増強された半導体チップを提供する。 【解決手段】 集積回路チップ２００は、下にある薄膜 電気的相互接続体２０４ａ〜２０４ｎよりも少なくとも １桁大きい熱コンダクタンスを有する電力分配線路２５ １、２５２の金属ネットワークを有する。これらの線路 はチップの表面の上に沈着され、そして能動ＩＣ部品２ ０２、２０３の真上に配置され、および線路の下の選定 された能動部品に垂直に電気的におよび熱的に接続され る。導電体２７１、２７２は、これらの線路を外側の電 源に接続するように動作することができる。電気的に機 能しない付加的な伝導体２７１、２７２が線路上に分布 され、前記能動部品および線路から熱流を取り去るため の温度勾配を大きくするように動作することができる。

Verfahren zum Drahtbonden

Leistungshalbleiterchip mit zwei Metallschichten auf einer Fläche

Ein Halbleiterchip beinhaltet eine Leistungstransistorschaltung mit mehreren aktiven Transistorzellen. Eine erste Lastelektrode und eine Steuerelektrode sind auf einer ersten Fläche des Halbleiterchips angeordnet, wobei die erste Lastelektrode eine erste Metallschicht beinhaltet. Eine zweite Lastelektrode ist auf einer zweiten Fläche des Halbleiterchips angeordnet. Eine zweite Metallschicht ist über der ersten Metallschicht angeordnet, wobei die zweite Metallschicht elektrisch gegenüber der Leistungstransistorschaltung isoliert ist und die zweite Metallschicht über einen Bereich der Leistungstransistorschaltung angeordnet ist, der mindestens eine der mehreren aktiven Transistorzellen umfasst.

CHIP PACKAGES

Chip assemblies are disclosed that include a semiconductor substrate, multiple devices in and on the semiconductor substrate, a first metallization structure over the semiconductor substrate, and a passivation layer over the first metallization structure. First and second openings in the passivation layer expose first and second contact pads of the first metallization structure. A first metal post is positioned over the passivation layer and over the first contact pad. A second metal post is positioned over the passivation layer and over the second contact pad. A polymer layer is positioned over the passivation layer and encloses the first and second metal posts. A second metallization structure is positioned on the polymer layer, on the top surface of the first metal post and on the top surface of second metal post. The second metallization structure includes an electroplated metal. Related fabrication methods are also described.

SUBMOUNT, ENCAPSULATED SEMICONDUCTOR ELEMENT, AND METHODS OF MANUFACTURING THE SAME

The present invention provides a submount which includes a semiconductor element and which can be easily connected to an IC on a main substrate. The submount in one embodiment of the present invention includes: a substrate; electrodes; the semiconductor element; Au wires; and gold bumps. The electrodes, the semiconductor element, the Au wires, and the gold bumps are encapsulated on the substrate by a resin. The gold bumps are formed on the electrodes and the Au wires by ball bonding and are cut by dicing such that side surfaces of the gold bumps are exposed. The exposed surfaces function as side surface electrodes of the submount.

Wire bonding method, wire bonding apparatus and semiconductor device produced by the same

A wire bonding method for joining a metal wire with a bonding pad disposed on a semiconductor element by using a load and supersonic wave vibration, comprising: during interval of time from contact of the metal wire with the bonding pad to application of the supersonic wave vibration, continuously applying a first bonding load and a second bonding load which is lower than the first bonding load; and after application of the supersonic wave vibration, continuously applying a third bonding load of a size of about 50% of the load of the second bonding load and a fourth bonding load which is lower than the first bonding load and higher than the third bonding load. The reliability of the fine wire bonding joint is improved remarkably, whereby a high quality semiconductor device can be produced at a low cost.

Method of reducing process steps in metal line protective structure formation

A method of forming a protective structure on a top metal line on an interconnect structure is disclosed. The method includes providing a plate opening in the passivation layer on the top metal line and forming a protective plate in the plate opening on the top metal line.

Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion

A semiconductor device including a contact pad and circuit metallization on the surface of an integrated circuit (IC) chip comprises a stack of protection layers over the surface of the chip. The stack consists of a first inorganic layer ( 303 , preferably silicon nitride) on the chip surface, followed by a polymer layer ( 306 , preferably benzocyclobutene) on the first inorganic layer ( 303 ), and finally an outermost second inorganic layer ( 310 , preferably silicon dioxide) on the polymer layer ( 303 ). A window ( 301 a) in the stack of layers exposes the metallization ( 301 ) of the IC. A patterned seed metal layer ( 307 , preferably copper) is on the metallization ( 301 ) in the window and on the second inorganic layer ( 310 ) around the window. A buffer metal layer ( 308 , preferably copper) is positioned on the seed metal layer ( 307 ). A metal reflow element ( 309 ) is attached to the buffer metal ( 308 ).

Metal pad or metal bump over pad exposed by passivation layer

A circuitry component comprising a semiconductor substrate, a pad over said semiconductor substrate, a tantalum-containing layer on a side wall and a bottom surface of said pad, a passivation layer over said semiconductor substrate, an opening in said passivation layer exposing said pad, a titanium-containing layer over said pad exposed by said opening, and a gold layer over said titanium-containing layer.

Verfahren zum Drahtbonden

Method for preparing a conductive pad for electrical connection and conductive pad formed

Wirebond structure and method of wire bonding a microelectronic die

A WIREBOND STRUCTURE AND METHOD TO CONNECT TO A MICROELECTRONIC DIE

Semiconductor light emitting device

Circuit structure and fabrication method thereof

The present invention proposes a circuit structure and a fabrication method thereof. The circuit structure of the present invention comprises: a semiconductor substrate; a first metallic post, formed on the semiconductor substrate, and 20 to 300microns high with the ratio of the maximum horizontal dimension thereof to the height thereof less than 4; a second metallic post, formed on the semiconductor substrate, and 20 to 300microns high with the ratio of the maximum horizontal dimension thereof to the height thereof less than 4; an insulation layer, formed on the semiconductor substrate, and covering the first and second metallic posts; a first bump, formed on the first metallic post or the insulation layer; and a second bump, formed on the second post or the insulation layer, wherein the distance between the center of the first bump and the center of the second bump is 10 to 250microns. The present invention overcomes the drawbacks of the prior art, by providing post passivation structures ...

Thermally enhanced semiconductor chip having integrated bonds over active circuits

An integrated circuit (IC) chip has a metal network of electrical power distribution lines which have a thermal conductance at least an order of magnitude greater than underlying thin film electrical interconnects. These lines are deposited on the surface of the chip (FIG. 2), located directly over active IC components, and electrically and thermally connected vertically to selected active components below the lines. Electrical conductors are operable to connect the lines to an outside source, and additional electrically non-functional conductors are distributed on the lines, operable to steepen the thermal gradient for thermal flux away from said active components and lines.

Stacked semiconductor package with circuit side polymer layer

A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a circuit side having a pattern of die contacts, planarized wire bonding contacts bonded to the die contacts, and a planarized polymer layer on the circuit side configured as stress defect barrier. A method for fabricating the package includes the steps of forming bumps on the die, encapsulating the bumps in a polymer layer, and then planarizing the polymer layer and the bumps to form the planarized wire bonding contacts. The method also includes the steps of attaching and wire bonding the die to the substrate, and then forming the die encapsulant on the die.

Wire bonding apparatus

A wire bonding method for joining a metal wire with a bonding pad disposed on a semiconductor element by using a load and supersonic wave vibration, comprising: during interval of time from contact of the metal wire with the bonding pad to application of the supersonic wave vibration, continuously applying a first bonding load and a second bonding load which is lower than the first bonding load; and after application of the supersonic wave vibration, continuously applying a third bonding load of a size of about 50% of the load of the second bonding load and a fourth bonding load which is lower than the first bonding load and higher than the third bonding load. The reliability of the fine wire bonding joint is improved remarkably, whereby a high quality semiconductor device cna be produced at a low cost.

Elektronische Anordnung und ihre Herstellung

Die Erfindung bezieht sich auf eine elektronische Anordnung (100) und ihre Herstellung. Eine Ausführungsform stellt einen Träger (11) und mehrere Kontaktelemente (12, 13) bereit. Der Träger (11) definiert eine erste Ebene (14). An dem Träger (11) ist ein Leistungs-Halbleiterchip (15) angebracht. Aus einem elektrisch isolierenden Material ist ein Körper (16) gebildet, der den Leistungs-Halbleiterchip (15) überdeckt. Der Körper (16) definiert eine zu der ersten Ebene (14) parallele zweite Ebene (17) und sich von der ersten Ebene (14) zu der zweiten Ebene (17) erstreckende Seitenflächen. Mindestens eines der mehreren Kontaktelemente (12) besitzt in einer zu der ersten Ebene (14) orthogonalen Richtung einen Querschnitt, der länger als 60% des Abstands zwischen der ersten Ebene (14) und der zweiten Ebene (17) ist.

A conductive pad for electrical connection of an integrated circuit chip

A copper pad surface 14 of an IC chip is first prepared, e.g. cleaned by an acid solution, a protection layer 16 of a phosphorus or boron-containing metal alloy is then deposited on the copper pad surface, and then an adhesion layer 18 of a noble metal is deposited on top of the protection layer. The protection layer 16 may be a single layer, or two or more layers intimately joined together formed of a phosphorus or boron-containing metal alloy such as Ni-P, Co-P, Co- W-P, Co-Sn-P, Ni-W-P, Co-B, Ni-B, Co-Sn-B, Co-W-B and Ni-W-B. A suitable thickness for the protection layer is between about 1,000 Ñ and about 10,000 Ñ, and preferably between about 3,000 Ñ and about 7,000 Ñ. The adhesion layer 18 can be formed of a noble metal such as Au, Pt, Pd and Ag to a thickness between about 500 Ñ and about 4,000 Ñ, and preferably between about 1,000 Ñ and about 2,000 Ñ. A nucleation layer of Pd may be deposited between the copper conductive pad surface 14 and the protection layer 16 prior to the electroless deposition of the protection layer. An additional noble metal layer may be deposited on top of the adhesion layer 18 by an electroless Au deposition process to increase the thickness of the final noble metal layer to about 2,000 Ñ 12,000 Ñ, and preferably between about 4,000 Ñ and about 6,000 Ñ. The pad is suitable for a wireband or solder bump connection

METHOD FOR OBTAINING METAL TO METAL CONTACT BETWEEN A METAL SURFACE AND A BONDING PAD.

Semiconductor switch circuit device and making method therefor

METHOD FOR OBTAINING METAL TO METAL CONTACT BETWEEN A METAL SURFACE AND A BONDING PAD.

A method for obtaining metal-to-metal contact between a bonding surface of a metallic bonding area and a second metal surface is disclosed. The method comprises the steps of : - coating said bonding surface of said metallic bonding area with a chemical composition that forms a self-assembled monolayer on said bonding surface of said metallic bonding area, and - bonding said second metal surface on said coated bonding surface through said self–assembled monolayer. The combination of the coating step and the bonding step result in a metal to metal contact between the bonding surface of he metallic bonding area and the second metal surface. The metallic bonding area can be a semiconductor bond pad, e.g. of a semiconductor device.

Multi-chip semiconductor packages and assembly thereof

Semiconductor packages and method of fabricating them are described. In one embodiment, the semiconductor package includes a substrate having a first and a second die attach pad. A first die is disposed over the first die attach pad. A second die is disposed over the second die attach pad. A third die is disposed between the first and the second die. The third die having a first, a second, and a third portion such that the first portion is disposed above a portion of the first die, the second portion is disposed above a portion of the second die, and the third portion is disposed above an area between the first die and the second die.

DIE ATTACH PADDLE FOR MOUNTING INTEGRATED CIRCUIT DIE

An electrical package for an integrated circuit die which comprises a die-attach paddle for mounting the integrated circuit die. The die-attach paddle has at least one down-set area located on a periphery of the die-attach paddle. The down-set area has an upper surface and a lower surface, with the upper surface configured to electrically couple a first end of a first electrically conductive lead wire. A second end of the first electrically conductive lead wire is bonded to the integrated circuit die. The upper surface is further configured to electrically couple a first end of a second electrically conductive lead wire and a second end of the second electrically conductive lead wire is bonded to a lead finger of the electrical package.

Semiconductor switching circuit device and manufacturing method thereof

Posts are disposed at the surroundings of an FET and a shield metal supported by the posts is placed above the FET to create a void between the FET and the shield metal. Since the separation between the FET and the shield metal is small, the resin does not enter the void. A resin layer cover the shield metal. The shield metal is connected to an electrode pad that receives a DC control signal. Although high frequency signals that are applied to the FET may leak between the source and drain electrodes of the FET through the resin layer covering the FET even when the FET is switched off, the void and the shield metal prevent such signal leakage.

Circuitry component

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, CMP DEVICE AND METHOD

PURPOSE: To protect the pad electrodes of a highly integrated semiconductor device against surface oxidation so as to provide the semiconductor device which is high in bonding strength to outer terminals. CONSTITUTION: A semiconductor device is equipped with a pad electrode connected to an outer electrode and a multiplayer wiring structure connected to the pad electrode, where an insulating film provided with an opening to make the surface of the pad electrode exposed is formed covering the pad electrode, and the one surface of the insulating film is brought into contact with a metal surface of noble metal material selected out of noble metal and metal which contains the noble metal as a main component. © KIPO & JPO 2002 ...

Sealing and protecting integrated circuit bonding pads

A metal structure (600) for a bonding pad on integrated circuit wafers, which have interconnecting metallization (101) protected by an insulating layer (102) and selectively exposed by windows in the insulating layer. The structure comprises a patterned seed metal layer (104) positioned on the interconnecting metallization exposed by the window so that the seed metal establishes ohmic contact to the metallization as well as a practically impenetrable seal of the interface between the seed metal and the insulating layer. Further, a metal stud (301) is formed on the seed metal and aligned with the window. The metal stud is conformally covered by a barrier metal layer (501) and an outermost bondable metal layer (502).

Semiconductor device sealed with molded resin

A semiconductor device has an active layer formed on a semiconductor substrate with different types of junctions, a source region, a drain region, a T-shaped gate electrode in which the cross-sectional area of the upper surface is larger than that of the lower surface, a first dielectric layer covering at least the exposed surface of the active layer, and the gate electrode, and a second dielectric layer enclosing the first dielectric layer. In the device, when the specific inductive capacities of the first and second dielectric layers are ε(1) and ε(2) respectively ε(1)<ε(2) and the water absorption ratio of the first dielectric layer is greater than the water absorption ratio of the second dielectric layer.

ELECTRONIC DEVICE AND MANUFACTURING THEREOF

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Method of improving interconnect of semiconductor devices by utilizing a flattened ball bond

A method of forming a semiconductor device assembly comprising forming a wire bump on at least one bond pad on the active surface of a semiconductor device and connecting one end of a wire to the wire bump using a wire bond. The wire bump may be flattened before connecting one end of a wire thereto.

Power Semiconductor Chip Having Two Metal Layers on One Face

A semiconductor chip includes a power transistor circuit with a plurality of active transistor cells. A first load electrode and a control electrode are arranged on a first face of the semiconductor chip, wherein the first load electrode includes a first metal layer. A second load electrode is arranged on a second face of the semiconductor chip. A second metal layer is arranged over the first metal layer, wherein the second metal layer is electrically insulated from the power transistor circuit and the second metal layer is arranged over an area of the power transistor circuit that comprises at least one of the plurality of active transistor cells.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To reduce an impact to a circuit structure under a bonding pad when wire bonding. SOLUTION: A first step of dripping conductive resin material liquid onto a laminate 22 of a semiconductor substrate 10 having a semiconductor element formed thereon, conductive layers 12 and 16 electrically connected to the semiconductor element, and an insulating layer 14 provided between the conductive layers from above the laminate to form a conductive resin layer 26 on the laminate; a second step of heating the conductive resin layer to obtain a cured impact buffer layer 28 as a bonding pad 30; and a third step of forming a bonding wire on an upper side of the impact buffer layer 28 are used in a semiconductor device manufacturing process. COPYRIGHT: (C)2003,JPO ...

WIRE BONDING PROCESS FOR COPPER-METALLIZED INTEGRATED CIRCUITS

집적회로의 상호접속 구리 배선에 전기적 와이어/리본 접속을 가능하게 해주는 튼튼하고 신뢰성 있으며 저비용인 금속 구조물과 그 프로세스에 관한 것이다. 구조물은 배리어 층이 구리의 확산을 배리어 금속이 존재하지 않을 때와 비교하여 250℃에서 80% 이상 감소시키도록 조정된 두께로 비산화 구리 표면에 피착되어 구리 확산을 저지하는 배리어 금속층을 포함한다. 구조물은 또한 배리어 금속의 확산을 본딩가능한 금속이 존재하지 않을 때와 비교하여 250℃에서 80% 이상 감소시키는 본딩가능한 최외부 층을 더 포함한다. 마지막으로 금속 와이어를 금속적 접속을 위해 최외부 층에 본딩한다. 배리어 금속은 니켈, 코발트, 크롬, 몰리브덴, 티타늄, 텅스텐 및 이들의 합금으로 구성되는 그룹에서 선택한다. 본딩가능한 최외부 금속층은 금, 백금 및 은으로 구성되는 그룹에서 선택한다. 집적회로, 상호접속 구리 배선, 배리어 금속층, 본딩가능한 최외부 금속층, 본딩 패드

Circuitry component and method for forming the same

METHOD OF WIRE BONDING A MICROELECTRONIC DIE

A wirebond structure includes a copper pad formed on or in a surface of a microelectronic die. A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable contact between the bond wire and the copper pad in at least one of an oxidizing environment and an environment with temperature up to at least about 350°C.

I/o sites for probe test and wire bond

반도체 장치

... 내습성 및 고온 보관 특성이 우수한 반도체 장치를 제공한다. 반도체 장치는, 기판으로서, 다이 패드부와 이너 리드부를 갖는 리드 프레임을 구비하고, 다이 패드부에 탑재된 반도체 소자와, 반도체 소자에 형성된 전극 패드와, 기판에 형성된 이너 리드부와 전극 패드를 접속시키는 구리 와이어와, 반도체 소자 및 구리 와이어를 봉지하는 봉지 수지를 갖는다. 구리 와이어와의 접합면으로부터 깊이 방향으로 적어도 3 ㎛ 이하의 범위에 있어서의 전극 패드의 영역이, 알루미늄보다 이온화 경향이 작은 금속을 주성분으로서 함유하고, 구리 와이어 중의 황 함유량이 구리 와이어 전체에 대해 15 ppm 이상 100 ppm 이하이다.

Die attach paddle for mounting integrated circuit die

An electrical package for an integrated circuit die which comprises a die-attach paddle for mounting the integrated circuit die. The die-attach paddle has at least one down-set area located on a periphery of the die-attach paddle. The down-set area has an upper surface and a lower surface, with the upper surface configured to electrically couple a first end of a first electrically conductive lead wire. A second end of the first electrically conductive lead wire is bonded to the integrated circuit die. The upper surface is further configured to electrically couple a first end of a second electrically conductive lead wire and a second end of the second electrically conductive lead wire is bonded to a lead finger of the electrical package.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A semiconductor device includes a substrate; a metal layer formed on the substrate; an insulating layer, which is formed on the metal layer and is provided with a via-hole through it; and a bonding pad formed above the via-hole. The bonding pad comprises an inner portion arranged in the via-hole and an outer portion arranged above the via-hole. The boding pad is made of a conductive resin having a shock absorbing characteristic.

Discrete semiconductor device having polymer resin as insulator and method for making the same

Disclosed is a discrete semiconductor device comprising a Si body having an emitter region, a base region and a collector region, an SiO2 layer disposed on the surface of the body, a polyimide resin having a thickness of 5 mu disposed on the SiO2 layer, electrodes penetrating through the SiO2 layer and the polyimide resin thereby contacting the emitter region and the base region, respectively and extending on the surface of the polyimide resin, whereby it becomes easy to bond a wire connected to an external electrode with the electrodes.

Thermally enhanced semiconductor chip having integrated bonds over active circuits

An integrated circuit (IC) chip has a metal network of electrical power distribution lines which have a thermal conductance at least an order of magnitude greater than underlying thin film electrical interconnects. These lines are deposited on the surface of the chip (FIG. 2), located directly over active IC components, and electrically and thermally connected vertically to selected active components below the lines. Electrical conductors are operable to connect the lines to an outside source, and additional electrically non-functional conductors are distributed on the lines, operable to steepen the thermal gradient for thermal flux away from said active components and lines.

INTEGRATED CIRCUIT CHIP USING TOP POST-PASSIVATION TECHNOLOGY AND BOTTOM STRUCTURE TECHNOLOGY

Method for preparing a conductive pad for electrical connection and conductive pad formed

Semiconductor device

Circuitry component and method for forming the same

A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and second metallic posts have a height of between 20 and 300 microns, with the ratio of the maximum horizontal dimension thereof to the height thereof being less than 4. The distance between the center of the first bump and the center of the second bump is between 10 and 250 microns.

SEMICONDUCTOR DEVICE

PURPOSE: To provide a highly reliable resin sealed semiconductor device being used in ultrahigh frequency band in which deterioration of the characteristics of a chip, e.g. noise characteristics, is suppressed at low cost. CONSTITUTION: The semiconductor device comprises a current channel, a source region, and a drain region formed on a semiconductor substrate having a heterojunction, a gate electrode 5 having such cross-section as the area of upper face part is larger than that of lower face part, a first dielectric film 7 covering at least the current channel and the gate electrode 5, and a second dielectric film 8 surrounding the first dielectric film 7, wherein the first dielectric film has a permittivity lower than that of the second dielectric film and a hygroscopicity lower than that of the second dielectric film. COPYRIGHT: (C)1995,JPO ...

Multichip-Halbleitergehäuse und deren Zusammenbau

Es werden Halbleitergehäuse und Verfahren zu ihrer Herstellung beschrieben. In einer Ausführungsform enthält das Halbleitergehäuse ein Substrat mit einem ersten und einem zweiten Die-Attach-Pad. Ein erstes Mikroplättchen wird über dem ersten Die-Attach-Pad angeordnet. Ein zweites Mikroplättchen wird über dem zweiten Die-Attach-Pad angeordnet. Ein drittes Mikroplättchen wird zwischen dem ersten und dem zweiten Mikroplättchen angeordnet. Das dritte Mikroplättchen hat einen ersten, einen zweiten und einen dritten Teil derart, dass der erste Teil über einem Teil des ersten Mikroplättchens angeordnet ist, der zweite Teil über einem Teil des zweiten Mikroplättchens angeordnet ist, und der dritte Teil über einem Bereich zwischen dem ersten Mikroplättchen und dem zweiten Mikroplättchen angeordnet ist.

Halbleiter-Bauelement mit einem Kontaktclip mit Vorsprüngen und Herstellung davon

Ein Halbleiter-Bauelement enthält einen Systemträger mit einem Die-Pad und einer ersten Zuleitung, einen Halbleiterchip mit einer ersten Elektrode und einen Kontaktclip mit einem ersten Kontaktbereich und einem zweiten Kontaktbereich. Der Halbleiterchip wird über dem Die-Pad platziert. Der erste Kontaktbereich wird über der ersten Zuleitung platziert, und der zweite Kontaktbereich wird über der ersten Elektrode des Halbleiterchips platziert. Mehrere Vorsprünge erstrecken sich von dem ersten und zweiten Kontaktbereich aus und jeder der Vorsprünge weist eine Höhe von mindestens 5 mm auf.

Halbleiterchip, Vorrichtung mit einem Leistungshalbleiterchip, Halbbrückenschaltung und Verfahren zum Herstellen der Vorrichtung

Halbleiterchip (10), umfassend: ein Halbleitersubstrat (13); eine Leistungstransistorschaltung, die in das Halbleitersubstrat (13) integriert ist und mehrere aktive Transistorzellen (14) umfasst; eine erste Lastelektrode (15) und eine Steuerelektrode (16), die beide auf einer ersten Fläche des Halbleitersubstrats (13) angeordnet sind, wobei die erste Lastelektrode (15) eine erste Metallschicht (18) umfasst, die einen ersten Abschnitt (21) mit einer ersten Dicke (d1) und einen zweiten Abschnitt (22) mit einer zweiten Dicke (d2) aufweist, wobei die erste Dicke (d1) kleiner ist als die zweite Dicke (d2) und eine Differenz zwischen der ersten Dicke (d1) und der zweiten Dicke (d2) zwischen 3 μm (Mikrometer) und 8 μm (Mikrometer) beträgt; eine zweite Lastelektrode (17), die auf einer zweiten der ersten Fläche gegenüberliegenden Fläche des Halbleitersubstrats (13) angeordnet ist; und eine zweite Metallschicht (19), die über einer von dem Halbleitersubstrat (13) weg weisenden Oberfläche des ersten ...

Compound semiconductor device and manufacturing method thereof

Chip packages

Chip assemblies are disclosed that include a semiconductor substrate, multiple devices in and on the semiconductor substrate, a first metallization structure over the semiconductor substrate, and a passivation layer over the first metallization structure. First and second openings in the passivation layer expose first and second contact pads of the first metallization structure. A first metal post is positioned over the passivation layer and over the first contact pad. A second metal post is positioned over the passivation layer and over the second contact pad. A polymer layer is positioned over the passivation layer and encloses the first and second metal posts. A second metallization structure is positioned on the polymer layer, on the top surface of the first metal post and on the top surface of second metal post. The second metallization structure includes an electroplated metal. Related fabrication methods are also described.

BONDING WIRE FOR HIGH SPEED SIGNAL

[Document Namel :Abstract of Disclosure '-itie of Invention] 2onding Wire for High Speed Sighal [Onlect] To provide a bonding wire of an Ag -Pd -Au -based al. y for high speed signal lines\" which is free from a. rigid silver sulfide (2).12-,NS) film though. an unstable silver sulfide laybr might be forme& on a surface of the bending' wire, and. is capable of sending ultrahigh frequency signals of a stable band of several GHz or the like, [Solving Means] A ternary' alloy including 2.5 to 4.0 mass% of palladium (Pd) and 1.5 to 2.5 mass% of gold. (Au), with thC' balance being silver (P.g) having purity of 99.99 mass% Or More, Wherein a cross-section CL:: the bonding wire includes a. surface film and a tore material, the surface inciudes a continimulsly cast summace..'rhich. a diameter is reduced after continuous casting and a surface segregation layer, and the surface segregation. layer inclubes an. alic region. where a content of the silver (Ag) is gradually- increased and a content of the gbid (Au) is gradually reduced. as compared to the core material. [Selected DrawinJ. 1.

I/O SITES FOR PROBE TEST AND WIRE BOND

A method of forming an input-output (I/0) structure is described, wherein a substrate having copper conductive feature (20) exposed at the bottom of a recess (25) in a first dielectric layer (10) is covered by a first conductive barrier (102) that is selectively formed in the recess (25). A second dielectric (105), preferably an organic polymer such as polyimide, is formed over the substrate surface and a second recess (27) is formed in the second dielectric (105) so that at least a portion of the first conductive barrier (102) is exposed. A second conductive barrier (107) is conformally deposited, followed by conformal deposition of a seed layer (109), where both are deposited under a vacuum to ensure adhesion of the seed layer (109) to the second conductive barrier (107). The seed layer (107) is selectively removed external to the recess (27), followed by plating of a nickel-containing metal (113) and then a noble metal (115), which will plate on the remaining portion of the seed layer ...

Semiconductor device and production method thereof

A method of producing a semiconductor device, comprising: a first plasma processing step of processing a surface of a resin layer laid on a semiconductor element and containing silicon, with a first plasma generated from a gas containing oxygen and fluorine, thereby forming an oxide film; and an electrode pad forming step of forming an electrode pad of a metal on the oxide film.

Post passivation structure for a semiconductor device and packaging process for same

A post passivation rerouting support structure comprises a relatively thin support layer above the passivation layer to support the RDL, and a relatively thick support layer for fine pitch interconnects extending from the RDL and terminating as contact structures at the surface of the thick support layer, for a next level packaging structure. The thick support layer is planarized before defining the contact structures. The thick support layer may be formed after the conducting posts have been formed, or the thick support layer is formed before forming the conducting posts in vias formed in the thick support layer. An encapsulating layer may be provided above the thick support layer, which top surface is planarized before defining the contact structures. The encapsulating layer and the further support layer may be the same layer.

Wire-bond process flow for copper metal-six, structures achieved thereby, and testing method

The present invention relates to a device that includes a low-ohmic test. The device includes a metallization copper pad such as metal-six, a metal first film such as Ni that is disposed above the metallization copper pad, and a metal second film such as Au that is disposed above the metal first film. The present invention also relates to a wire-bonding process, and to a method of pulling a first wire bond and making a second wire bond.

ELECTRONIC DEVICE AND MANUFACTURING THEREOF

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Circuitry component and method for forming the same

Base station and sealing after a semiconductor element and a method of manufacturing thereof

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME AND APPARATUS FOR CHEMICAL MECHANICAL POLISHING AND METHOD OF CHEMICAL MECHANICAL POLISHING

고집적화된 반도체 장치의 패드 전극의 표면 산화를 방지하고 외부 단자와의 접속 강도가 높은 반도체 장치를 제공한다. 외부 전극과 접속하기 위한 패드 전극과, 상기 패드 전극에 접속된 다층 배선 구조를 포함한 반도체 장치에 있어서, 상기 패드 전극을 덮고 상기 패드 전극 상에 개구부를 포함하고 상기 패드 전극의 표면을 노출시킨 절연막의 일면이 귀금속 및 상기 귀금속을 주성분으로 하는 금속으로부터 선택되는 하나의 귀금속 재료로 이루어지는 금속면과 접한다.

SEMICONDUCTOR PACKAGE USING A SILVER OR SILVER ALLOY WIRE TO INCREASE A COUPLING PROPERTY BETWEEN THE SILVER WIRE AND A JEWELRY PAD

PURPOSE: A semiconductor package is provided to lower an electrical conductivity of the semiconductor package by using a silver or silver alloy, instead of gold, to form a wire. CONSTITUTION: A semiconductor package includes a package substrate(105), a semiconductor chip(110), and at least one wire(130). The semiconductor chip is attached to the package substrate and includes at least one pad, which is made of a noble metal. The wire is bonded to electrically couple the pad with the package substrate. The wire is made of silver or a silver alloy. The pad is made of an element selected from the group consisting of Pd, Pt, Au, Ni, and Cu. The wire contains silver at a concentration higher than 95 w%. The wire contains palladium at a concentration lower than 5 w%. © KIPO 2008 ...

Semiconductor package having multi-channel and related electronic system

Method of improving interconnect of semiconductor devices by using a flattened ball bond

A method of forming a semiconductor device assembly comprising forming a wire bump on at least one bond pad on the active surface of a semiconductor device and connecting one end of a wire to the wire bump using a wire bond. The wire bump may be flattened before connecting one end of a wire thereto.

Semiconductor package having a stacked structure

A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.

Semiconductor device and method of manufacturing the semiconductor device

Disclosed are: a semiconductor device that comprises a semiconductor element to which a plurality of wires are bonded, wherein bonding strength of the wires is high and sufficient bonding reliability is achieved; and a method for manufacturing the semiconductor device. Specifically disclosed is a semiconductor device which is characterized by comprising a first wire that has one end bonded onto an electrode and the other end bonded to a second bonding point that is out of the electrode, and a second wire that has one end bonded onto the first wire on the electrode and the other end bonded to a third bonding point that is out of the electrode. The semiconductor device is also characterized in that the bonded portion of the first-mentioned end of the second wire covers at least apart of the upper surface and the lateral surface of the first wire.

Semiconductor package having a multi-channel and a related electronic system

A substrate including internal interconnections, first and second finger electrodes, and having first to fourth quadrants. External terminals are formed on the substrate and connected to the first and second finger electrodes via the internal interconnections. A first tower including first semiconductor chips is formed on the substrate. First conductive wires are formed between the first semiconductor chips and the first finger electrodes. A second tower including second semiconductor chips is formed on the substrate. Second conductive wires are formed between the second semiconductor chips and the second finger electrodes. The external terminals include a first group connected to the first finger electrodes and configuring a channel, and a second group connected to the second finger electrodes, and configuring another channel. The first finger electrodes are formed on the third quadrant, and the second finger electrodes are formed on the first quadrant.

Chip package and method for forming the same

A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is located in the sensing region or device region and includes a plurality of sensing units. A plurality of first openings is located in the chip and correspondingly exposes the sensing units. A plurality of conductive extending portions is disposed in the first openings and is electrically connected to the sensing units, wherein the conductive extending portions extend from the first openings onto the upper surface of the chip. A method for forming the chip package is also provided.

Method for preparing a conductive pad for electrical connection and conductive pad formed

향상된 확산 장벽 및 접착 특성을 갖는 전기 접속용 구리 패드면을 제공하기 위한 방법이 제공된다. 이 방법에서, 우선 산성 용액에서 세정된 구리 패드면이 제공된다. 그 다음, 인 또는 붕소-함유 금속 합금으로 된 보호층이 구리 패드면 상에 피착되고, 귀금속의 접착층이 보호층의 상부상에 피착된다. 보호층은 단일층일 수도 있고, Ni-P, Co-P, Co-W-P, Co-Sn-P, Ni-W-P, Co-B, Ni-B, Co-Sn-B, Co-W-B, 및 Ni-W-B와 같이 인 또는 붕소-함유 급속 합금으로 형성된 서로 밀접하게 결합된 2개 이상의 층들일 수도 있다. 보호층에 대한 적절한 두께는 약 1000Å 내지 10000Å이며, 양호하게는 약 3000Å내지 7000Å이다. 접착층은, 두께가 약 500Å 내지 약 4000Å정도이고 양호하게는 1000Å 내지 2000Å정도인 Au, Pt, Pd, 및 Ag와 같은 귀금속으로 형성될 수 있다. 대안으로, 보호층의 무전해 피착 이전에 Pd로 된 핵형성층이 구리 도전 패드면과 보호층 사이에 피착된다. 대안으로, 무전해 Au 피착 공정에 의해 접착층의 상부에 추가적인 귀금속층이 피착되어 최종 귀금속층의 두께를 약 2000Å 내지 12000Å정도, 양호하게는, 약 4000Å 내지 6000Å정도로 증가시킨다. 본 발명은, 구리 패드면, 인 또는 붕소-함유 금속 합금으로된 보호층, 및 보호층의 상부에 피착된 귀금속의 접착층을 포함하며 그 상부에 전기 접속부를 형성하기 위한 도전 패드도 역시 공개한다. 나아가, 본 발명은 접착층의 상부에 일체로 형성된 전기 접속부, 즉, 와이어접합 또는 땜납 범프를 갖는 도전 패드를 포함하는 전기 구조물에도 역시 관련되어 있다. A method is provided for providing a copper pad face for electrical connection with improved diffusion barrier and adhesive properties. In this method, a copper pad face which is first cleaned in an acidic solution is provided. A protective layer of phosphorus or boron-containing metal alloy is then deposited on the copper pad face, and an adhesive layer of noble metal is deposited on top of the protective layer. The protective layer may be a single layer, and Ni-P, Co-P, Co-WP, Co-Sn-P, Ni-WP, Co-B, Ni-B, Co-Sn-B, Co-WB, and Ni It may be two or more layers closely bonded to each other formed of a phosphorus or boron-containing rapid alloy such as -WB. Suitable thicknesses for the protective layer are about 1000 kPa to 10000 kPa, preferably about 3000 kPa to 7000 kPa. The adhesive layer may be formed of precious metals such as Au, Pt, Pd, and Ag, having a thickness of about 500 kPa to about 4000 kPa and preferably of about 1000 kPa to 2000 kPa. Alternatively, a nucleation layer of Pd is deposited between the copper conductive pad surface and the protective layer prior to electroless deposition of the protective layer. Alternatively, an ...

Semiconductor Package Having Spin Stacked Structure

기판과 기판에 적층되는 제 1 반도체 칩 및 제 1 반도체 칩에 적층되는 제 2 반도체 칩을 갖는 반도체 패키지들을 제공한다. 여기서, 제 2 반도체 칩은 회전되어 제 1 반도체 칩 상에 적층되는 반도체 패키지를 제공한다. 나아가, 그러한 반도체 패키지들을 구비하는 각종 전자 시스템들을 제공한다.

Plate-shaped body and method for manufacturing semiconductor device

Electronic device having contact elements with a specified cross section and manufacturing thereof

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Manufacturing electronic device having contact elements with a specified cross section

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

I/O sites for probe test and wire bond

本发明公开了形成输入－输出(I/O)结构的方法，其中通过在凹槽(25)中选择性形成的第一导电阻挡层(102)覆盖具有在第一介质层(10)中的凹槽(25)的底部暴露的铜导电部分(20)的衬底。在衬底表面上形成第二介质(105)，优选有机聚合物例如聚酰亚胺，并且在第二介质(105)中形成第二凹槽(27)以使第一导电阻挡层(102)的至少一部分暴露。保形沉积第二导电阻挡层(107)，之后保形沉积籽晶层(109)，二者均在真空下沉积以确保籽晶层(109)与第二导电阻挡层(107)的附着。选择性除去凹槽(27)外部的籽晶层(107)，之后镀覆含镍金属(113)和随后镀覆贵金属(115)，其将在凹槽(27)中的籽晶层(107)的剩余部分上，而不在第二导电阻挡层(107)镀覆。通过低偏置功率RIE从暴露的场区域除去第二导电阻挡层(107)。本发明提供了形成用于探针测试和布线接合的I/O结构的低成本方法，而不损坏下面的器件和降低芯片的面积。

Structure and method for copper plating layer integrated circuit welding spot

一种坚固、可靠并且低成本金属结构和方法,其使电丝/带连接到集成电路的互连铜镀层。该结构含,沉积在氧化铜表面的、250铜扩散系数小于1×10E－23cm 2 /S并且厚约0.5－1.5μm的第一阻挡金属层。其在第一阻挡金属层上进一步包括第二阻挡金属层,该第二阻挡金属层250时具有少于1×10E－14cm 2 /s的第一阻挡金属扩散系数,并且厚度小于1.5μm。其最终包括可焊接金属的最外层,在该层上,焊接金属丝供冶金学连接。第一阻挡金属选自镍、钴、铬、钼、钛、钨及其合金。第二阻挡金属选自钯、钴、铂和锇。最外金属层选自金、铂和银。

Method for fabricating board on chip (BOC) semiconductor package with circuit side polymer layer

A method for fabricating a BOC package includes the steps of providing a semiconductor die having planarized bumps encapsulated in a polymer layer, and providing a substrate having a plurality of conductors and an opening. The method also includes the steps of attaching the die to the substrate in a BOC configuration, wire bonding wires through the opening to the conductors and the bumps, and forming a die encapsulant on the die.

Semiconductor device and its manufacture, chemical-mechanical grinding device and method

提供防止高集成化的半导体器件的焊盘电极的表面氧化,与外部端子的连接强度高的半导体器件。一种半导体器件,配有用于连接外部电极的焊盘电极和与该焊盘电极连接的多层布线结构,覆盖该焊盘电极、在该焊盘电极上有开口部并使该焊盘电极的表面露出的绝缘膜的单面与贵金属和从以该贵金属为主要成分的金属中选择的一种贵金属材料组成的金属面连接。

Sensor package

A sensor package is disclosed. One embodiment provides a sensor device having a carrier, a semiconductor sensor mounted on the carrier and an active surface. Contact elements are electrically connecting the carrier with the semiconductor sensor. A protective layer made of an inorganic material covers at least the active surface and the contact elements.

Structure and method for bond pads of copper-metallized integrated circuits

A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of first barrier metal, deposited on the non-oxidized copper surface, having a copper diffusion coefficient of less than 1×10E-23 cm 2 /s at 250° C. and a thickness from about 0.5 to 1.5 μm. It further comprises a layer of second barrier metal on the layer of first barrier metal, having a diffusion coefficient of the first barrier metal of less than 1×10E-14 cm 2 /s at 250° C. and a thickness of less than 1.5 μm. It finally comprises an outermost layer of bondable metal, onto which a metal wire is bonded for metallurgical connection. The first barrier metal is selected from a group consisting of nickel, cobalt, chromium, molybdenum, titanium, tungsten, and alloys thereof. The second barrier metal is selected from a group consisting of palladium, cobalt, platinum and osmium. The outermost metal layer is selected from a group consisting of gold, platinum, and silver.

Micromechanical device contact terminals free of particle generation

A microelectronic mechanical structure (MEMS) comprising a semiconductor chip having an integrated circuit including a plurality of micromechanical components, and a plurality of conductive routing lines integral with the chip; the routing lines having contact terminals of oxide-free metal; and the terminals having a layer of barrier metal on the oxide-free metal and an outermost layer of noble metal, whereby damage-free testing of the circuit is possible using test probe needles. The barrier metal is selected from a group consisting of nickel, cobalt, chromium, molybdenum, titanium, tungsten, tantalum, palladium, platinum, rhodium, rhenium, osmium, vanadium, iron, ruthenium, niobium, iridium, zirconium, hafnium, copper, and alloys thereof. Alloys of these metals may contain phosphorus or boron. The outermost layer is a noble metal which is bondable or solderable, and is selected from a group consisting of gold, platinum, palladium, silver, rhodium, and copper. Alloys of these metals may contain phosphorus or boron.

Etching platinum-containing thin film using protective cap layer

【課題】保護キャップ層を用いたプラチナ含有薄膜のエッチング方法を提供する。【解決手段】マイクロ電子デバイス（２００）の基板（２０２）上にプラチナ含有層（２２０）を形成し、キャップ層（２３２）が、キャップ層とプラチナ含有層との間の界面にプラチナ酸化物がないように、プラチナ含有層上に形成される。キャップ層は、プラチナ含有層もエッチングするエッチャント中でエッチング可能であり、プラチナ酸化物がプラチナ含有層上に生じる前に、プラチナ含有層上に形成される。或いは、プラチナ含有層上のプラチナ酸化物は、キャップ層を形成する前に除去される。プラチナ含有層は、プラチナシリサイド（２２６）を形成するために用いられ、ウェットエッチャントをブロックするために、プラチナ含有層の頂部表面の一部の上にハードマスク又はマスキングプラチナ酸化物（２６４）を形成することによってパターニングされる。【選択図】図２Ｅ

Integrated circuit chip using top post-passivation technology and bottom structure technology

Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.

Circuit structure for integrating power distributed function of circuit and lead frame to chip surface

一种安装在引线框上的集成电路芯片,具有沉积在芯片表面上的功率分布线网络,使它们直接位于电路的有源元件之上;以及导电且垂直地连接到分布线之下的所选有源元件的分布线,还有连接到引线框的线段的导体,由此节省电路功率分布线和导体衬垫所消耗的硅地盘量,增加电路设计灵活性和组装制造能力,减少线段的输入/输出数目。

Integrated circuit chip using top post-passivation technology and bottom structure technology

Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.

Semiconductor device with double nickel-plated leadframe

A leadframe for use in the assembly of integrated circuit (IC) chips, which has first and second surfaces and a base metal structure ( 606 ) with an adherent layer ( 607 ) of nickel having a rough, non-reflecting surface covering the base metal. This rough nickel enhances adhesion to molding compounds. An adherent layer ( 608 ) of smooth, reflective nickel selectively covers the first surface of the leadframe in areas intended for attachment of bonding wires and the IC chip. This smooth nickel facilitates the use of vision systems. A first adherent metal layer ( 609 ) is deposited in selected areas of the first leadframe surface for wire bond attachment, and a second adherent metal layer ( 610 ) is deposited to provide attachment to external parts.

Power semiconductor chip having two metal layers on one face

本发明涉及在一个面上具有两层金属层的功率半导体芯片。该半导体芯片包括具有多个有源晶体管元件的功率晶体管电路。第一负载电极和控制电极布置在半导体芯片的第一面上，其中，第一负载电极包括第一金属层。第二负载电极布置在半导体芯片的第二面上。第二金属层布置在第一金属层上方，其中第二金属层与功率晶体管电路电绝缘，第二金属层布置在功率晶体管电路的包括多个有源晶体管元件中的至少一个的区域的上方。

Wire bonding system for semiconductor component

The component contains a semiconductor element (1) coupled to a connecting frame (4) by a chip bonding material, and a metal wire (3a) connecting the frame to the semiconductor element. A bonding point between a contact spot (2) on the element a metal wire has a number of island-shaped bonding points, and a strip-shaped coupling point, surrounding the bonding point. Preferably the frame is of Cu as its main component, while the main component of the chip bonding material. The main component of the metal wire is Au, and that of the contact spot is Al.

Localized alloying for improved bond reliability

In some embodiments a method of forming a gold-aluminum electrical interconnect is described. The method may include interposing a diffusion retardant layer between the gold and the aluminum ( 1002 ), the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material; bringing into contact the diffusion retardant layer, the gold, and the aluminum ( 1004 ); forming alloys of gold and the diffusion retardant material in regions containing the material ( 1006 ) and forming gold-aluminum intermetallic compounds in regions substantially devoid of the material ( 1008 ); and forming a continuous electrically conducting path between the aluminum and the gold ( 1010 ). In some embodiments, a structure useful in a gold-aluminum interconnect is provided. The structure may include an aluminum alloy bond pad ( 530 ) and a diffusion retardant layer ( 520 ) in contact with the bond pad, the diffusion retardant layer including regions ( 522 ) containing and regions ( 524 ) substantially devoid of a diffusion retardant material. The structure may include a gold free air ball ( 714 ) in contact with the diffusion retardant layer.

Circuit structure integrating the power distribution functions of circuits and leadframes into the chip surface

An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. The network relocates most of the conventional power distribution interconnections from the circuit level to the newly created surface network, thus saving substantial amounts of silicon real estate and permitting shrinkage of the IC area. The network is electrically connected to selected active components by metal-filled vias; since these vias can easily be redesigned to other locations, IC designers gain a new degree of design freedom. The network relocates most of the bond pads dedicated to power supply from the conventional alignment along the chip periphery onto the newly created bondable lines, saving substantial additional amounts of silicon real estate, and freeing the bonding machines from their extremely tight connector placement and attachment rules to much more relaxed bonding programs. The network is deposited and patterned in wafer processing as a sequence of metal layers specifically suited for providing power current and electrical ground potential. The network has attachable outermost metal surface and is laid out so that network portions form pads convenient for attaching balls of bonding wires or solder.

Method of improving interconnect of semiconductor devices by utilizing a flattened ball bond

A method of forming a semiconductor device assembly comprising forming a wire bump on at least one bond pad on the active surface of a semiconductor device and connecting one end of a wire to the wire bump using a wire bond. The wire bump may be flattened before connecting one end of a wire thereto.

Semiconductor device and manufacturing method thereof

Device including a semiconductor chip and wires

Ein Bauelement beinhaltet einen Träger, einen ersten Halbleiterchip, der über dem Träger angeordnet ist, und ein erstes elektrisch leitendes Element, das über dem Träger angeordnet ist. Das Bauelement beinhaltet weiter einen ersten Draht, der elektrisch an das erste elektrisch leitende Element gekoppelt ist, und einen zweiten Draht, der elektrisch an das erste elektrisch leitende Element und an den ersten Halbleiterchip gekoppelt ist. Das erste elektrisch leitende Element ist ausgestaltet, um ein elektrisches Signal zwischen dem ersten Draht und dem zweiten Draht weiterzuleiten. A device includes a carrier, a first semiconductor chip disposed over the carrier, and a first electrically conductive element disposed over the carrier. The device further includes a first wire electrically coupled to the first electrically conductive element and a second wire electrically coupled to the first electrically conductive element and the first semiconductor chip. The first electrically conductive element is configured to pass an electrical signal between the first wire and the second wire.

LED lead frame or substrate, semiconductor device and LED lead frame or the manufacture method of substrate

一种LED用引线框或基板（10），具备：具有载置LED元件（21）的载置面（11a）的主体部（11）。在主体部（11）的载置面（11a）上，设置有作为用于反射来自LED元件（21）的光的反射层发挥功能的反射用金属层（12）。反射用金属层12包含铂与银的合金、或者金与银的合金。通过反射用金属层12，可高效率地反射来自LED元件（21）的光，并且抑制气体所引起的腐蚀，维持来自LED元件（21）的光的反射特性。

Semiconductor device with a contact clip with projections and manufacture thereof

Halbleiter-Bauelement, das Folgendes umfasst: einen Systemträger (10), der ein Die-Pad (11) und eine erste Zuleitung (12) umfasst; einen Halbleiterchip (15), der eine erste Elektrode (16) umfasst, wobei der Halbleiterchip (15) über dem Die-Pad (11) platziert ist; einen Kontaktclip (25), der einen ersten Kontaktbereich (26) und einen zweiten Kontaktbereich (27) umfasst, wobei der erste Kontaktbereich (26) über der ersten Zuleitung (12) platziert ist und der zweite Kontaktbereich (27) über der ersten Elektrode (16) des Halbleiterchips (15) platziert ist, wobei mehrere Vorsprünge (28) sich von dem ersten Kontaktbereich (26) und dem zweiten Kontaktbereich (27) erstrecken und jeder der Vorsprünge (28) eine Höhe von mindestens 5 μm aufweist; und eine erste Schicht aus Lotmaterial (32) zwischen dem ersten Kontaktbereich (26) des Kontaktclips (25) und der ersten Zuleitung (12), wobei Abschnitte der ersten Schicht aus Lotmaterial (32) intermetallische Phasen (50) aufweisen, die nur in Bereichen zwischen den Vorsprüngen (28) des Kontaktclips (25) und der ersten Zuleitung (12) angeordnet sind und wobei die intermetallischen Phasen (50) eine höhere Schmelztemperatur aufweisen als die Bereiche des Lotmaterials (32) zwischen den Vorsprüngen (28) des Kontaktclips (25), in denen das Lotmaterial (32) keine intermetallische Phasen aufweist. A semiconductor device comprising: a leadframe (10) including a die pad (11) and a first lead (12); a semiconductor chip (15) including a first electrode (16), the semiconductor chip (15) being placed over the die pad (11); a contact clip (25) comprising a first contact region (26) and a second contact region (27), wherein the first contact region (26) is placed over the first lead (12) and the second contact region (27) over the first electrode (27) 16) of the semiconductor chip (15), wherein a plurality of protrusions (28) extend from the first contact region (26) and the second contact region (27) and each of the protrusions (28) has a height ...

Circuit structure and fabrication method thereof

A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and second metallic posts have a height of between 20 and 300 microns, with the ratio of the maximum horizontal dimension thereof to the height thereof being less than 4. The distance between the center of the first bump and the center of the second bump is between 10 and 250 microns. Figure 12D

Semiconductor device and method for manufacturing same

Disclosed are: a semiconductor device that comprises a semiconductor element to which a plurality of wires are bonded, wherein bonding strength of the wires is high and sufficient bonding reliability is achieved; and a method for manufacturing the semiconductor device. Specifically disclosed is a semiconductor device which is characterized by comprising a first wire that has one end bonded onto an electrode and the other end bonded to a second bonding point that is out of the electrode, and a second wire that has one end bonded onto the first wire on the electrode and the other end bonded to a third bonding point that is out of the electrode. The semiconductor device is also characterized in that the bonded portion of the first-mentioned end of the second wire covers at least a part of the upper surface and the lateral surface of the first wire.

Chip package

A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal pad region and extends from the upper surface toward the lower surface along the sidewall. The shallow recess structure has at least a first recess and a second recess under the first recess. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A first end of a wire is located in the shallow recess structure and is electrically connected to the redistribution layer. A second end of the wire is used for external electrical connection. A method for forming the chip package is also provided.

Board for manufacturing a BGA and method of manufacturing semiconductor device using thereof

Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion

A semiconductor device including a contact pad and circuit metallization on the surface of an integrated circuit (IC) chip comprises a stack of protection layers over the surface of the chip. The stack consists of a first inorganic layer ( 303, preferably silicon nitride) on the chip surface, followed by a polymer layer ( 306 , preferably benzocyclobutene) on the first inorganic layer ( 303 ), and finally an outermost second inorganic layer ( 310 , preferably silicon dioxide) on the polymer layer ( 303 ). A window ( 301 a ) in the stack of layers exposes the metallization ( 301 ) of the IC. A patterned seed metal layer ( 307 , preferably copper) is on the metallization ( 301 ) in the window and on the second inorganic layer ( 310 ) around the window. A buffer metal layer ( 308 , preferably copper) is positioned on the seed metal layer ( 307 ). A metal reflow element ( 309 ) is attached to the buffer metal ( 308 ).

Etching platinum-containing thin films with protective cap layers

Compound semiconductor device

Layer structure for electrical contacting of semiconductor components

A layer structure for the electrical contacting of a semiconductor component having integrated circuit elements and integrated connecting lines for the circuit elements, which is suitable in particular for use in a chemically aggressive environment and at high temperatures, i.e., in so-called “harsh environments,” and is simple to implement. This layer structure includes at least one noble metal layer, in which at least one bonding island is formed, the noble metal layer being electrically insulated from the substrate of the semiconductor component by at least one dielectric layer, and having at least one ohmic contact between the noble metal layer and an integrated connecting line. The noble metal layer is applied directly on the ohmic contact layer.

Layer structure for electrical contacting of semiconductor devices

Es wird ein Schichtaufbau zur elektrischen Kontaktierung eines Halbleiterbauelements mit integrierten Schaltungselementen und integrierten Anschlussleitungen für die Schaltungselemente vorgeschlagen, der sich besonders für den Einsatz in einer chemisch aggressiven Umgebung und bei hohen Temperaturen, also in sogenannten „harsh-environments”, eignet und dabei einfach zu realisieren ist. Dieser Schichtaufbau umfasst mindestens eine Edelmetallschicht (6), in der mindestens eine Bondinsel (61) ausgebildet ist, wobei die Edelmetallschicht (6) durch mindestens eine dielektrische Schicht (3, 4) gegen das Substrat (1) des Halbleiterbauelements elektrisch isoliert ist, und mindestens einen ohmschen Kontakt (5) zwischen der Edelmetallschicht (6) und einer integrierten Anschlussleitung (2). Erfindungsgemäß ist die Edelmetallschicht (6) unmittelbar auf die ohmsche Kontaktschicht (5) aufgebracht. It is proposed a layer structure for electrically contacting a semiconductor device with integrated circuit elements and integrated connection lines for the circuit elements, which is particularly suitable for use in a chemically aggressive environment and at high temperatures, ie in so-called "harsh environments", and easy to realize is. This layer structure comprises at least one noble metal layer (6) in which at least one bonding pad (61) is formed, wherein the noble metal layer (6) is electrically insulated from the substrate (1) of the semiconductor device by at least one dielectric layer (3, 4) at least one ohmic contact (5) between the noble metal layer (6) and an integrated connecting line (2). According to the invention, the noble metal layer (6) is applied directly to the ohmic contact layer (5).

Etching platinum-containing thin film using protective cap layer

A microelectronic device (200) is formed by forming a platinum-containing layer (220) on a substrate (202) of the microelectronic device (200). A cap layer (232) is formed on the platinum-containing layer (220) so that an interface between the cap layer (232) and the platinum-containing layer (220) is free of platinum oxide. The cap layer (232) is etchable in an etch solution which also etches the platinum-containing layer (220). The cap layer (232) may be formed on the platinum-containing layer (220) before platinum oxide forms on the platinum-containing layer (220). Alternatively, platinum oxide on the platinum-containing layer (220) may be removed before forming the cap layer (232). The platinum-containing layer (220) may be used to form platinum silicide (226). The platinum-containing layer (220) may be patterned by forming a hard mask or masking platinum oxide (264) on a portion of the top surface of the platinum-containing layer (220) to block the wet etchant.

Method of reducing process steps in metal line protective structure formation

Lead carrier with thermally fused package components

A lead carrier provides support for a semiconductor device during manufacture. The lead carrier includes a temporary support member with multiple package sites. Each package site includes a die attach pad surrounded by a plurality of terminal pads. The pads are formed of a fusible fixing material on a lower portion. A chip is mounted upon the die attach pad and wire bonds extend from the chip to the terminal pads. The pads, chip and wire bonds are all encapsulated within a mold compound. The temporary support member can be heated above a melting temperature of the fusible fixing material and peeled away and then the individual package sites can be isolated from each other to provide completed packages including multiple surface mount joints for mounting within an electronics system board.

Device including semiconductor chip and wire

本发明的各实施方式总体上涉及包括半导体芯片和接线的器件。具体地，涉及一种器件，包括载体、布置在所述载体之上的第一半导体芯片和布置在所述载体之上的第一导电元件。该器件进一步包括电耦合至所述第一导电元件的第一接线以及电耦合至所述第一导电元件和所述第一半导体芯片的第二接线。所述第一导电元件被配置为在所述第一接线与所述第二接线之间转发电信号。

Use top post-passivation technology and the IC chip of bottom structure technology

本申请涉及使用顶部后钝化技术和底部结构技术的集成电路芯片。本发明揭示集成电路芯片和芯片封装，其包含所述集成电路芯片的顶部处的过钝化方案和所述集成电路芯片的底部处的底部方案，所述过钝化方案和底部方案使用顶部后钝化技术和底部结构技术。所述集成电路芯片可通过所述过钝化方案或所述底部方案连接到外部电路或结构，例如球栅格阵列(BGA)衬底、印刷电路板、半导体芯片、金属衬底、玻璃衬底或陶瓷衬底。还描述相关的制造技术。

Semiconductor component support and semiconductor device

本发明提供半导体元件安装构件以及半导体装置，半导体元件安装构件包括供半导体元件安装的金属的元件安装部，所述元件安装部包括在俯视下一部分形成切口的金属区域，所述金属区域的切口包含第一区域与第二区域，该第二区域与所述第一区域连续且位于比所述第一区域靠外侧的位置，该第二区域比所述第一区域的宽度宽，所述第一区域的至少一部分位于半导体元件的安装侧主表面的正下方。

LAYER STRUCTURE FOR ELECTRICAL CONNECTION OF SEMICONDUCTIVE COMPONENTS

Localized alloying for improved bond reliability

Methods of forming gold-aluminum electrical interconnects are described. The method may include interposing a diffusion retardant layer between the gold and the aluminum, the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material; bringing into contact the diffusion retardant layer, the gold, and the aluminum; forming alloys of gold and the diffusion retardant material in regions containing the material and forming gold-aluminum intermetallic compounds in regions substantially devoid of the material; and forming a continuous electrically conducting path between the aluminum and the gold. A structure for gold-aluminum interconnect is provided. The structure may include an aluminum alloy bond pad and a diffusion retardant layer in contact with the bond pad, the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material. The structure may include a gold free air ball in contact with the diffusion retardant layer.

Etching platinum-containing thin film using protective cap layer

A microelectronic device includes a substrate a platinum-containing layer over the substrate. The platinum-containing layer includes a first segment and a second segment adjacent to the first segment, and has a first surface and a second surface opposite the first surface closer to the substrate than the first surface. A first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface. A width of the first segment along the first surface is less than twice a thickness of the first segment, and the second spacing is less than twice the thickness of the first segment.

Semiconductor chip structure

A semiconductor chip structure includes a semiconductor substrate, an circuit structure, a passivation layer, a first adhesion/barrier layer, a metal cap and a metal layer. The semiconductor substrate has multiple electric devices located on a surface layer of a surface of the substrate. The circuit structure had multiple circuit layers electrically connecting with each other and electrically connecting with the electric devices. One of the circuit layers has multiple pads. The passivation layer is located on the circuit structure and has multiple openings penetrating through the passivation layer. The openings expose the pads. The first adhesion/barrier layer is over the pads and the passivation layer. The metal cap is located on the first adhesion/barrier layer and the passivation layer. The metal layer is on the metal layer.

Semiconductor switch circuit device and making method therefor

一种半导体开关电路装置及其制造方法。在以往的化合物半导体开关电路装置中，高频信号会通过模制树脂而泄漏，从而引起隔离恶化。本发明的半导体开关电路装置在FET的周围设置支柱，在FET上设置由支柱支承的屏蔽金属。由于FET和屏蔽金属的间隔距离小，故当进行通常的树脂模制时，树脂不会进入该空间，FET之上形成中空。也就是说，FET和树脂由屏蔽金属屏蔽，FET的IN-OUT之间由介电常数高的空气屏蔽，所以可防止高频信号的泄漏。

Method of making a passivated wire bonded semiconductor device

A semiconductive device is described in which electrical contact is made with the semiconductor surface through a rupture in an overlying frangible dielectric coating. Contact is achieved by forming an electrode pad on the semiconductor surface, coating the surface of the semiconductor and the electrode pad with a frangible layer of dielectric, forming a terminal connector contact pad on the dielectric coating over the electrode pad, rupturing the dielectric layer to communicate the pads, and bonding a terminal lead to the connector contact pad. In a preferred embodiment, the rupturing and bonding steps are simultaneously achieved by compression bonding a terminal wire to the connector contact pad.

Wirebond structure and method to connect to a microelectronic die

A wirebond structure includes a copper pad formed on or in a surface of a microelectronic die. A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable contact between the bond wire and the copper pad in at least one of an oxidizing environment and an environment with temperatures up to at least about 350° C.

Bonding wire for high-speed signal line

An object is to provide a bonding wire for a high-speed signal line, formed by an Ag—Pd—Pt three-element alloy or an Ag—Pd—Pt ternary alloy, that is able to transmit a stable super-high frequency signal in a several GHz band, and that does not have a strong silver sulfide (Ag 2 S) film even when an unstable silver sulfide layer is formed on the surface of the bonding wire. Provided is the bonding wire for the high-speed signal line formed by a three-element alloy containing 0.8 to 2.5 mass % of palladium (Pd), 0.1 to 0.7 mass % of platinum (Pt), and a balance being silver (Ag) with purity of 99.99 mass % or more, or a ternary alloy obtained by adding a trace element to the three-element alloy, in which cross section of the bonding wire is formed by a skin film and a core, and in which a surface segregation layer containing highly-concentrated silver (Ag) is present in the skin film of the silver alloy.

Etching platinum-containing thin film using protective cap layer

A microelectronic device includes a substrate a platinum-containing layer over the substrate. The platinum-containing layer includes a first segment and a second segment adjacent to the first segment, and has a first surface and a second surface opposite the first surface closer to the substrate than the first surface. A first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface. A width of the first segment along the first surface is less than twice a thickness of the first segment, and the second spacing is less than twice the thickness of the first segment.

使用保护盖层蚀刻含铂薄膜

本申请题为“使用保护盖层蚀刻含铂薄膜”。一种微电子器件(200)是通过在该微电子器件(200)的衬底(202)上形成含铂层(220)来形成的。盖层(232)在含铂层(220)上形成，使得盖层(232)和含铂层(220)之间的界面不含氧化铂。盖层(232)在蚀刻含铂层(220)的蚀刻溶液中也是可蚀刻的。可替代地，含铂层(200)上的氧化铂可以在形成盖层(232)之前被去除。含铂层(220)可以用于形成硅化铂(226)。可以通过在含铂层(220)的顶部表面的一部分上形成硬掩模或掩模氧化铂(264)以阻挡湿蚀刻剂来图案化含铂层(220)。

Etching platinum-containing thin film using protective cap layer

Method for manufacturing a metal pad structure of a die, a method for manufacturing a bond pad of a chip, a die arrangement and a chip arrangement

A method for manufacturing a metal pad structure of a die is provided, the method including: forming a metal pad between encapsulation material of the die, wherein the metal pad and the encapsulation material are separated from each other by a gap; and forming additional material in the gap to narrow at least a part of the gap.

Kontaktierungsstruktur einer integrierten leistungsschaltung

Elektronische Anordnung und Verfahren zu ihrer Herstellung

Anordnung (100 - 1200), aufweisend:- einen Träger (11) und mehrere Kontaktelemente (12, 13), wobei der Träger (11) eine erste Ebene (14) definiert, wobei der Träger (11) elektrisch mit einem ersten Kontaktelement (11) der mehreren Kontaktelemente gekoppelt ist und wobei der Träger (11) mit dem ersten Kontaktelement (11) integral ist,- einen an den Träger (11) angebrachten Leistungs-Halbleiterchip (15), und- einen aus einem elektrisch isolierenden Material gebildeten Körper (16), der den Leistungs-Halbleiterchip (15) bedeckt, wobei der Körper (16) eine zu der ersten Ebene (14) parallele zweite Ebene (17) und sich von der ersten Ebene (14) zu der zweiten Ebene (17) erstreckende Seitenflächen (18, 19) definiert, wobei- mindestens eines der mehreren Kontaktelemente (12) sich in einer zu der ersten Ebene (14) orthogonalen Richtung erstreckt und in der orthogonalen Richtung eine Höhe aufweist, die länger als 60% des Abstands zwischen der ersten Ebene (14) und der zweiten Ebene (17) ist, wobei der sich in der orthogonalen Richtung erstreckende Teil des einen der mehreren Kontaktelemente (12) von dem Körper (16) kontaktiert wird und eine freiliegende Oberfläche aufweist, die mit einer freiliegenden Seitenfläche des Körpers (16) ausgerichtet ist, wobei der Leistungs-Halbleiterchip (15) eine erste Elektrode (30) aufweist, die an den Träger (11) angebracht ist, wobei der Leistungs-Halbleiterchip (15) eine zweite Elektrode (32) aufweist, die elektrisch mit einem zweiten Kontaktelement (12) der mehreren Kontaktelemente gekoppelt ist, wobei die erste Elektrode (30) auf einer ersten Hauptoberfläche (31) des Leistungs-Halbleiterchips (15) angeordnet ist und die zweite Elektrode (32) auf einer der ersten Hauptoberfläche (31) gegenüberliegenden zweiten Hauptoberfläche (33) des Leistungs-Halbleiterchips (15) angeordnet ist.

Multichip-Halbleitergehäuse und deren Zusammenbau

Halbleitergehäuse, umfassend:ein Substrat (10), das einen ersten (11) und einen zweiten (13) und einen dritten (12) Die-Attach-Pad umfasst, die getrennt voneinander angeordnet sind, wobei das dritte Die-Attach-Pad (12) ein inneres Die-Attach-Pad ist, das zwischen dem ersten Die-Attach-Pad (11) und dem zweiten Die-Attach-Pad (13) angeordnet ist;ein erstes Mikroplättchen (30) über dem ersten Die-Attach-Pad (11) angeordnet, wobei das erste Mikroplättchen (30) über einem ersten Teil des ersten Die-Attach-Pads (11) und über einem ersten Teil des dritten Die-Attach-Pads (12) angeordnet ist;ein zweites Mikroplättchen (30) über dem zweiten Die-Attach-Pad (13) angeordnet, wobei das zweite Mikroplättchen (30) über einem zweiten Teil des dritten Die-Attach-Pads (12) und über einem ersten Teil des zweiten Die-Attach-Pads (13) angeordnet ist;ein drittes Mikroplättchen (50) zwischen dem ersten (30) und dem zweiten (30) Mikroplättchen angeordnet, einen ersten Teil des dritten Mikroplättchens (50) über einem ersten Teil des ersten Mikroplättchens (30) angeordnet, einen zweiten Teil des dritten Mikroplättchens (50) über einem ersten Teil des zweiten Mikroplättchens (30) angeordnet, und einen dritten Teil des dritten Mikroplättchens (50) über einem ersten Bereich zwischen dem ersten Mikroplättchen (30) und dem zweiten Mikroplättchen (30) angeordnet.

Wirebond contact structure and method of wire bonding a microelectronic die

A wirebond structure includes a copper pad formed on or in a surface of a microelectronic die. A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable contact between the bond wire and the copper pad in at least one of an oxidizing environment and an environment with temperatures up to at least about 350° C.

Wirebond structure and method of wire bonding a microelectronic die

A wirebond structure includes a copper pad formed on or in a surface of a microelectronic die. A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable contact between the bond wire and the copper pad in at least one of an oxidizing environment and an environment with temperature up to at least about 350°C.

导线结合结构和微电子电路芯片及其连接方法

一种导线结合结构和微电子电路芯片及其连接方法，包括形成在微电子电路芯片的表面上或者表面中的铜焊盘。包括与该铜焊盘接触的导电层，且结合导线结合到该导电层。该导电层由一种单一材料形成，以在氧化环境和具有达到至少大约350℃的温度的环境的至少一种环境中在结合导线和铜焊盘之间提供稳定的接触。

High-speed signal line with bonding wire

고속 신호용 본딩 와이어

<과제> 본딩 와이어의 표면에 불안정한 황화은층을 형성해도, 강고한 황화은(Ag 2 S)막이 없고, 안정한 수GHz대 등의 초고주파 신호를 보낼 수가 있는 Ag－Pd－Au기 합금의 고속 신호선용 본딩 와이어를 제공하는 것을 목적으로 한다. <해결 수단> 팔라듐(Pd)을 2.5~4.0질량%, 금(Au)을 1.5~2.5질량% 및 잔부가 순도 99.99질량% 이상의 은(Ag)으로 이루어지는 3원 합금으로서, 그 본딩 와이어의 단면은 표피막과 심재로 이루어지고, 그 표피막은 연속 주조 후에 축경된 연주면과 표면 편석층으로 이루어지고, 그 표면 편석층은, 심재보다도 은(Ag)의 함유량이 점증하고 또 금(Au)의 함유량이 점감하고 있는 합금 영역으로 이루어지는 것을 특징으로 하는 고속 신호선용 본딩 와이어이다.

Chip package and method for fabricating the same

高速信号線用ボンディングワイヤ

【課題】安定した数ＧＨｚ帯等の超高周波信号を送ることができるＡｇ−Ｐｄ−Ｐｔ三元合金又はＡｇ−Ｐｄ−Ｐｔ三元系合金の高速信号線用ボンディングワイヤの提供。 【解決手段】パラジウムを０．８〜２．５質量％、白金が０．１〜０．７質量％及び残部が純度９９．９９質量％以上の銀からなる三元合金又はこの三元合金に微量元素が添加された三元系合金であって、そのボンディングワイヤの断面は表皮膜と芯材とからなり、その銀合金の表皮膜には銀が高濃度の表面偏析層が存在することを特徴とする高速信号線用ボンディングワイヤである。 【効果】銀の高濃度の表面偏析層と銀合金の耐硫化性によりボンディングワイヤの表面に不安定な硫化銀層を形成しても、強固な硫化銀（Ａｇ ２ Ｓ）膜が形成されず、表面に偏析した高純度銀層により数ＧＨｚ等の超高周波信号を送ることができる。 【選択図】図１

高速信号线用接合线

本发明的目的在于提供一种Ag-Pd-Pt三元合金或Ag-Pd-Pt三元系合金的高速信号线用接合线，即使在该接合线的表面形成不稳定的硫化银层时，仍无坚固的硫化银(Ag 2 S)膜，并可传送稳定的数千兆赫频带等的超高频信号。该高速信号线用接合线是由0.8～2.5质量%的钯(Pd)、0.1～0.7质量%的铂(Pt)、及剩余部分为纯度99.99质量%以上的银(Ag)所构成的三元合金、或于该三元合金中添加微量元素所构成的三元系合金，该接合线的剖面是由表皮膜与芯材构成，该银合金的表皮膜中存在具有高浓度银(Ag)的表面偏析层。

高速信號線用接合線

本發明之目的在於提供一種Ag-Pd-Pt三元合金或Ag-Pd-Pt三元系合金的高速信號線用接合線，即使在該接合線的表面形成不穩定的硫化銀層時，仍無堅固的硫化銀(Ag2S)膜，並可傳送穩定的數千兆赫頻帶等的超高頻信號。該高速信號線用接合線係由0.8~2.5質量%的鈀(Pd)、0.1~0.7質量%的鉑(Pt)、及剩餘部分為純度99.99質量%以上的銀(Ag)所構成的三元合金、或於該三元合金中添加微量元素所構成的三元系合金，其特徵為：該接合線的剖面係由表皮膜與芯材構成，該銀合金的表皮膜中存在具有高濃度銀(Ag)的表面偏析層。

高速信号线用接合线

本发明的目的在于提供一种Ag‑Pd‑Pt三元合金或Ag‑Pd‑Pt三元系合金的高速信号线用接合线，即使在该接合线的表面形成不稳定的硫化银层时，仍无坚固的硫化银(Ag 2 S)膜，并可传送稳定的数千兆赫频带等的超高频信号。该高速信号线用接合线是由0.8～2.5质量%的钯(Pd)、0.1～0.7质量%的铂(Pt)、及剩余部分为纯度99.99质量%以上的银(Ag)所构成的三元合金、或于该三元合金中添加微量元素所构成的三元系合金，该接合线的剖面是由表皮膜与芯材构成，该银合金的表皮膜中存在具有高浓度银(Ag)的表面偏析层。

고속 신호선용 본딩 와이어

<과제> 본딩 와이어의 표면에 불안정한 황화은층을 형성해도, 강고한 황화은(Ag 2 S)막이 없고, 안정한 수GHz대 등의 초고주파 신호를 보낼 수가 있는 Ag－Pd－Pt 3원 합금 또는 Ag－Pd－Pt를 기본으로 하는 합금의 고속 신호선용 본딩 와이어를 제공하는 것을 목적으로 한다. <해결수단> 팔라듐(Pd)을 0.8~2.5질량%, 백금(Pt)이 0.1~0.7질량% 및 잔부가 순도 99.99질량% 이상의 은(Ag)으로 이루어지는 3원 합금 또는 이 3원 합금에 미량 원소가 첨가된 합금으로서, 그 본딩 와이어의 단면은 표피막과 심재로 이루어지고, 그 은합금의 표피막에는 은(Ag)이 고농도인 표면 편석층이 존재하는 것을 특징으로 하는 고속 신호선용 본딩 와이어이다.

Wire-bond process flow for copper metal-six, structures achieved thereby, and testing method

The present invention relates to a device that includes a low-ohmic test. The device includes a metallization copper pad such as metal-six, a metal first film such as Ni that is disposed above the metallization copper pad, and a metal second film such as Au that is disposed above the metal first film. The present invention also relates to a wire-bonding process, and to a method of pulling a first wire bond and making a second wire bond.

Sealing and protecting integrated circuit bonding pads

Ein Verfahren zum Herstellen einer Metallpadstruktur eines Die, ein Verfahren zum Herstellen eines Bondpads eines Chips, einer Die-Anordnung und einer Chipanordnung

Es wird ein Verfahren (400) zum Herstellen einer Metallpadstruktur eines Die bereitgestellt, wobei das Verfahren Folgendes beinhaltet: Ausbilden eines Metallpads zwischen Kapselungsmaterial des Die, wobei das Metallpad und das Kapselungsmaterial durch einen Spalt voneinander getrennt sind (410); und Ausbilden von zusätzlichem Material in dem Spalt, um mindestens einen Teil des Spalts zu verengen (420).

Sealing and protecting integrated circuit bonding pads

高速信号线用接合线

本发明的目的是提供一种银-钯-金(Ag-Pd-Au)基合金的高速信号线用接合线，其即使在接合线表面形成不稳定的硫化银层时，仍无坚固的硫化银(Ag 2 S)膜，并可传输稳定的数千兆赫(giga Hertz，GHz)带等的超高频信号。本发明的解决方法是提供一种高速信号线用接合线，其是由钯(Pd)2.5～4.0质量%、金(Au)1.5～2.5质量%及剩余部分为纯度99.99质量%以上的银(Ag)所构成的三元合金，该接合线剖面是由表皮膜与芯材所构成，该表皮膜是由在连续铸造后所缩径的连续铸造面与表面偏析层所构成，该表面偏析层是由较芯材含量渐增的银(Ag)且含量渐减的金(Au)的合金区域所构成。

高速信号线用接合线

本发明的目的是提供一种银‑钯‑金(Ag‑Pd‑Au)基合金的高速信号线用接合线，其即使在接合线表面形成不稳定的硫化银层时，仍无坚固的硫化银(Ag 2 S)膜，并可传输稳定的数千兆赫(giga Hertz，GHz)带等的超高频信号。本发明的解决方法是提供一种高速信号线用接合线，其是由钯(Pd)2.5～4.0质量%、金(Au)1.5～2.5质量%及剩余部分为纯度99.99质量%以上的银(Ag)所构成的三元合金，该接合线剖面是由表皮膜与芯材所构成，该表皮膜是由在连续铸造后所缩径的连续铸造面与表面偏析层所构成，该表面偏析层是由较芯材含量渐增的银(Ag)且含量渐减的金(Au)的合金区域所构成。

전압 변환기 회로를 포함하는 반도체 디바이스, 및 그 반도체 디바이스의 제조 방법

반도체 디바이스는 제 1 본딩 패드, 제 2 본딩 패드, 제 1 및 제 2 본딩 패드들 중 선택된 하나에 본딩되는 와이어, 제 1 본딩 패드에 전기적으로 접속되는 전력 공급 라인, 상기 제 2 본딩 패드에 연결되는 전압 변환기 회로를 포함하고, 상기 와이어 및 상기 제 2 본딩 패드를 통해 상기 전압 변환기 회로에 의해 수신되는 전압과는 상이한 내부 전력 전압을 생성하고 상기 내부 전력 전압을 상기 전력 공급 라인에 공급하기 위하여 상기 와이어가 상기 제 2 본딩 패드에 본딩될 때, 상기 전압 변환기 회로가 활성화되고, 상기 전력 공급 라인이 상기 와이어 및 상기 제 1 본딩 패드를 통하여 전력 전압을 수신하는 것을 허용하기 위하여 상기 와이어가 상기 제 1 본딩 패드에 접속될 때, 상기 전압 변환기 회로가 비활성화된다.

サブマウントおよび封止済み半導体素子ならびにこれらの作製方法

メイン基板上のＩＣと容易に接続することができる、半導体素子（１０４）を備えたサブマウント（１００）を提供すること。本発明の一実施形態に係るサブマウント（１００）は、基板（１０１）と、電極（１０２），（１０３）と、半導体素子（１０４）と、Ａｕワイヤ（１０５）と、金バンプ（１０６），（１０７）とから構成される。電極（１０２），（１０３）と、半導体素子（１０４）と、Ａｕワイヤ（１０５）と、金バンプ（１０６），（１０７）とは、樹脂（１０８）により基板（１０１）上で封止される。金バンプ（１０７）は、電極（１０３）上かつＡｕワイヤ（１０５）上にボールボンディングにより形成された後、ダイシングにより切断されて側面が露出する。露出した面が、サブマウント（１００）の側面電極として機能することとなる。

銅電極集積回路のためのワイヤ・ボンデイング構造及びその方法

(57)【要約】 （修正有） 【課題】 集積回路の銅相互接続電極に電気的なワイヤ ／リボン接着を可能にする頑健で、信頼性の高い、そし て低コストの金属構造及び方法を提供する。 【解決手段】 本発明の構造は、無酸化銅１０３表面上 に堆積された銅拡散に抵抗する障壁金属の層１０５で、 その厚さが障壁金属が存在しない場合に比較して２５０ ℃において８０パーセント以上の銅の拡散を減少する障 壁層１０５を有する。この構造はさらに最外の接着可能 金属層１０６を有し、この接着可能金属層が存在しない 場合に比較して２５０℃において８０パーセント以上の 障壁金属の拡散を減少する。最後に、金属ワイヤ１１０ が最外層に接着されて、金属的接着を行なう。障壁金属 は、ニッケル、コバルト、クロム、モリブデン、チタ ン、タングステン、及びこれらの合金から成るグループ から選択される。最外層の接着可能金属は、金、白金、 及び銀から成るグループから選択される。

半导体发光元件

在现有的实现了使被焊盘电极覆盖的部分不发光、提高光的取出效率的半导体发光元件中，产生了如下问题：在焊盘电极中，容易混入构成线状电极的材料，由于Au线的接合力不足而容易产生损坏等。本发明提供了一种半导体发光元件，在元件(1)的最表面半导体层(1a)的表面，具有焊盘电极(3)，在最表面半导体层和焊盘电极之间进行肖特基接合，在网状地覆盖除焊盘电极占据的部分之外的表面的线状电极(2)和最表面半导体层之间，进行欧姆接合，焊盘电极和线状电极在一部分接触，进行欧姆接合，在线状电极和焊盘电极的接触部，焊盘电极的层结构中的势垒金属层(3b)覆盖线状电极的层结构中的上部以及侧面的一部分或全部，从而使线状电极的构件不混入焊盘电极，来解决课题。

Die attach paddle for mounting integrated circuit die

An electrical package for an integrated circuit die which comprises a die-attach paddle for mounting the integrated circuit die. The die-attach paddle has at least one down-set area located on a periphery of the die-attach paddle. The down-set area has an upper surface and a lower surface, with the upper surface configured to electrically couple a first end of a first electrically conductive lead wire. A second end of the first electrically conductive lead wire is bonded to the integrated circuit die. The upper surface is further configured to electrically couple a first end of a second electrically conductive lead wire and a second end of the second electrically conductive lead wire is bonded to a lead finger of the electrical package.

Compound semiconductor device and method of manufacturing the same

Etching platinum-containing thin film using protective cap layer

A microelectronic device includes a substrate a platinum-containing layer over the substrate. The platinum-containing layer includes a first segment and a second segment adjacent to the first segment, and has a first surface and a second surface opposite the first surface closer to the substrate than the first surface. A first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface. A width of the first segment along the first surface is less than twice a thickness of the first segment, and the second spacing is less than twice the thickness of the first segment.

Chemical compound semiconductor device and manufacturing process therefor

Submount, encapsulated semiconductor element, and methods of manufacturing the same

The present invention provides a submount which includes a semiconductor element and which can be easily connected to an IC on a main substrate. The submount in one embodiment of the present invention includes: a substrate; electrodes; the semiconductor element; Au wires; and gold bumps. The electrodes, the semiconductor element, the Au wires, and the gold bumps are encapsulated on the substrate by a resin. The gold bumps are formed on the electrodes and the Au wires by ball bonding and are cut by dicing such that side surfaces of the gold bumps are exposed. The exposed surfaces function as side surface electrodes of the submount.

Verfahren zum drahtbonden eines mikroelektronischen halbleiterchips