Combinable electrode needle base structure

Provided is a combinable electrode needle base structure in which a base to which electrode needles are coupled can be used in a combined or separated state to use the electrode needles according to the size and location of a lesion. In the combinable electrode needle structure, electrode needles are connected to the front side of an electrode needle base, and receive RF waves from RF (radio frequency) generator. The electrode needle base is divided into dividable bases to which the electrode needles are respectively coupled. When a lesion to be cauterized is large or cauterization should be concentrated, the dividable bases are combined and then used, and when a lesion is small or lesions are scattered, the dividable bases may be separated and then used.

Circuit board, semiconductor package having the same, and method of manufacturing the circuit board

A circuit board may include an insulation plate having at least one slot. A first conductive pattern may be on the insulation plate. A plug may be on a sidewall of the slot, and may be electrically connected to the conductive pattern.

Semiconductor package with improved ball land structure

A semiconductor package has ball lands each configured to have a composite structure of SMD type and NSMD type. One peripheral portion of the ball land is covered with a mask layer, thus forming the SMD type, whereas the other peripheral portion is exposed through an opening area of the mask layer, thus forming the NSMD type. In one embodiment, the first peripheral portion is disposed to face a central point of a ball-mounting surface of a substrate, and the second peripheral portion is disposed to face the opposite direction to the central point. The composite structure of the ball lands provides more stable and enhanced connections between connection balls, such as solder balls, and the ball-mounting surface.

Multi-chip package having a logic chip disposed in a package substrate opening and connecting to an interposer

A multi-chip package may include a package substrate, a connecting substrate, a plurality of semiconductor chips and a logic chip. The package substrate may have an opening. The connecting substrate may be arranged on an upper surface of the package substrate. The semiconductor chips may be stacked on an upper surface of the connecting substrate. The semiconductor chips may be electrically connected with the connecting substrate. The logic chip may be arranged in the opening. The logic chip may be electrically connected between the connecting substrate and the package substrate. Thus, the logic chip may not act as to increase a width of the multi-chip package.

INTEGRATED CIRCUIT PACKAGES HAVING REDISTRIBUTION STRUCTURES

A semiconductor package includes a semiconductor chip stack disposed between first and second leads near first and second sides of the package and including a plurality of semiconductor chips, and a redistribution structure disposed on the semiconductor chip stack. At least one semiconductor chip of the semiconductor chip stack includes a plurality of first chip pads disposed near or closer to a third side of the package. The redistribution structure includes a first redistribution pad disposed near or closer to the first side and electrically connected to the first lead, a second redistribution pad disposed near or closer to the second side and electrically connected to the second lead, and a third redistribution pad disposed near or closer to the third side and electrically connected to a first one of the first chip pads and the first redistribution pad. 1. A semiconductor package having a first side , a second side , and a third side perpendicular to the first and second sides , the semiconductor package comprising:a first lead adjacent the first side;a second lead adjacent the second side;a semiconductor chip stack between the first and second leads and including a plurality of semiconductor chips; anda redistribution structure on the semiconductor chip stack, a first redistribution pad adjacent the first side and electrically connected to the first lead;', 'a second redistribution pad adjacent the second side and electrically connected to the second lead; and', 'a third redistribution pad adjacent the third side and electrically connected to a first one of the first chip pads and the first redistribution pad., 'wherein at least one semiconductor chip of the semiconductor chip stack includes a plurality of first chip pads disposed near the third side, and wherein the redistribution structure includes2. The semiconductor package of claim 1 , wherein the first lead includes a first inner lead having one end passing beneath the semiconductor chip stack and ...

Semiconductor package with improved ball land structure

A semiconductor package has ball lands each configured to have a composite structure of SMD type and NSMD type. One peripheral portion of the ball land is covered with a mask layer, thus forming the SMD type, whereas the other peripheral portion is exposed through an opening area of the mask layer, thus forming the NSMD type. In one embodiment, the first peripheral portion is disposed to face a central point of a ball-mounting surface of a substrate, and the second peripheral portion is disposed to face the opposite direction to the central point. The composite structure of the ball lands provides more stable and enhanced connections between connection balls, such as solder balls, and the ball-mounting surface.

Multi-channel package and electronic system including the same

A multi-channel package has at least four channels and includes a package substrate having a first surface and a second surface, semiconductor chips mounted on the first surface of the package substrate, and external connection terminals disposed on the second surface of the package substrate and electrically connected to the semiconductor chips by the at least four channels. Each channel is dedicated to one or a group of the chips. An electronic system includes a main board, at least one such multi-channel package mounted on the main board, and a controller package that is mounted on the main board, has 4n channels (wherein n>=2) and controls the at least one multi-channel package.

Wound Healing Device, Method for Making the Same and Method for Treating a Wound

A wound healing device includes a mat of aligned nanofibers of polyaniline, o-aminobenzenesulfonic acid copolymer, polyvinyl alcohol and chitsosan oligossacaride. Method for fabricating the mat and treating wounds are also disclosed. 1. A wound healing device for promoting enhanced healing of a wound comprises:a mat of aligned conductive nanofibers polyaniline and o-aminobenzenesulfonic acid copolymer, vinyl alcohol and chitosan oligossacaride.2. A wound healing device for promoting enhanced healing of a wound according to in which said nanofibers have a thickness in the order of 100 nanometers.3. A wound healing device for promoting enhanced healing of a wound according to in which said nanofibers have an average thickness of between 100 and 1 claim 2 ,000 nm.4. A wound healing device for promoting enhanced healing of a wound according to in which said nanofibers have been fabricated by an electro spinning technique.5. A method for preparing a nanofiber wound healing device comprising the steps ofproviding a mass of aniline, o-aminobenzenesulfonic acid PVA and chitosan oligossacaride (COS);chemically perimerizing the aniline and o-aminobenzenesulfonic acid using ammonium persulfate as an oxidant and maintaining the oxicant/monomer ratio at 1 to form a PAni-co-PABSA copolymer;preparing a PVA solution in double distilled water at 80° C. under magnetic stirring for 2 hours;cooling the PVA solution to room temperature;dissolving chitosan oligossacaride powder in double distilled water under magnetic stirring for 1 hour at room temperature and adding the PVA solution and the PAni-co-PABSA copolymer to form PAni-co-PABSA/PVA/COS blend solution; andelectro spinning the PAni-co-PABSA/PVA/COS blend solution at high voltage power and collect fibers on an electrically grounded aluminum foil to form a nanofiber mat.6. A method for preparing a nonofiber would healing device according to in which the PAni-co-PABSA/PVA/COS blend solution is from a needle tip and electrospinning ...

Semiconductor device

Provided is a semiconductor device having as many input/output pads as possible using a chip having a small number of input/output pads. The semiconductor device includes a substrate including first and second extending input/output pads, a first memory structure disposed on the substrate and including first connecting input/output pads, a second memory structure disposed on the first memory structure and including second connecting input/output pads, and a wiring structure formed on lateral surfaces of the first and second memory structures and connecting the first and second connecting input/output pads and the first and second extending input/output pads, respectively; wherein the wiring structure includes a first wiring connecting the first connecting input/output pads and the first extending input/output pad and a second wiring connecting the first connecting input/output pads and the second extending input/output pad, and the second wiring is offset relative to the first wiring.

Semiconductor package having a stacked structure

A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.

COMBINABLE ELECTRODE NEEDLE BASE STRUCTURE

Provided is a combinable electrode needle base structure in which a base to which electrode needles are coupled can be used in a combined or separated state to use the electrode needles according to the size and location of a lesion. In the combinable electrode needle structure, electrode needles are connected to the front side of an electrode needle base, and receive RF waves from RF (radio frequency) generator. The electrode needle base is divided into dividable bases to which the electrode needles are respectively coupled. When a lesion to be cauterized is large or cauterization should be concentrated, the dividable bases are combined and then used, and when a lesion is small or lesions are scattered, the dividable bases may be separated and then used.

Stacked structure using semiconductor devices and semiconductor device package including the same

This invention provides a semiconductor device. The semiconductor device includes a bonding pad array comprising: a signal bonding pad, a control pin bonding pad and at least one stacking bonding pad on an active surface. At least one stacking bonding pad is adjacent to the control pin bonding pad. This invention also provides a stacked structure of semiconductor devices and/or a semiconductor device package including the semiconductor device.

Bump land structure of circuit substrate for semiconductor package

A bump land structure of a circuit substrate for a semiconductor package may have a combination of an SMD type bump land structure and an NSMD type bump land structure. A lower portion of a solder mask and a lower layer of a bump land may form the SMD type bump land structure. An upper portion of a solder mask and an upper layer of a bump land may form the NSMD type bump land structure.

Semiconductor package having a stacked structure

A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.

METHODS OF PREPARING ELECTROCATALYSTS FOR FUEL CELLS IN CORE-SHELL STRUCTURE AND ELECTROCATALYSTS

Provided are a method of preparing an electrocatalyst for fuel cells in a core-shell structure, an electrocatalyst for fuel cells having a core-shell structure, and a fuel cell including the electrocatalyst for fuel cells. The method may be useful in forming a core and a shell layer without performing a subsequent process such as chemical treatment or heat treatment and forming a core support in which core particles having a nanosize diameter are homogeneously supported, followed by selectively forming shell layers on surfaces of the core particles in the support. Also, the electrocatalyst for fuel cells has a high catalyst-supporting amount and excellent catalyst activity and electrochemical property. 1. A method of preparing an electrocatalyst for fuel cells , the method comprising:preparing a core support in which core particles having a nanosize diameter are supported through out a support by a reaction of the support and metal precursors for forming core particles in an ether-based solvent; andselectively forming shell layers on surfaces of the core particles by a reaction of the core support and metal precursors for forming shell layers in the presence of an ester-based reducing agent.2. The method according to claim 1 , wherein an amine-based reducing agent is further used in the preparation of the core support.3. The method according to claim 1 , wherein the metal precursors for forming core particles are metal compounds comprising at least one selected from the group consisting of palladium claim 1 , copper claim 1 , gold and iridium.4. The method according to claim 1 , wherein the metal precursors for forming shell layers comprise at least one selected from the group consisting of platinum claim 1 , iridium and gold.5. The method according to claim 1 , wherein the ether-based solvent is benzyl ether.6. The method according to claim 1 , wherein the ester-based reducing agent is Hanztsch ester or a derivative thereof.7. The method according to claim 3 , ...

ELECTROLYTE MEMBRANE FOR FUEL CELL INCLUDING BLEND OF POLYMERS WITH DIFFERENT DEGREES OF SULFONATION, AND MEMBRANE-ELECTRODE ASSEMBLY AND FUEL CELL INCLUDING THE SAME

Disclosed herein is an electrolyte membrane for a fuel cell. The electrolyte membrane includes a blend of polymers with different degrees of sulfonation. The electrolyte membrane can exhibit excellent effects such as improved long-term cell performance and good long-term dimensional stability while at the same time solving the problems of conventional hydrocarbon electrolyte membranes. Further disclosed are a membrane-electrode assembly and a fuel cell including the electrolyte membrane. 1. An electrolyte membrane for a fuel cell comprising a blend of two or more sulfonated polymers of the same kind or different kinds with different degrees of sulfonation.2. The electrolyte membrane according to claim 1 , wherein the two or more sulfonated polymers are each independently a sulfonated hydrocarbon polymer selected from poly(ether sulfone)s claim 1 , poly(thiosulfone)s claim 1 , poly(ether ether ketone)s claim 1 , polyimides claim 1 , polystyrenes claim 1 , polyphosphazenes claim 1 , and random or block copolymers of the aforementioned polymers.3. The electrolyte membrane according to claim 2 , wherein each of the two or more sulfonated polymers is prepared by sulfonation of a non-sulfonated or low-sulfonated polymer or by polymerization of one or more sulfonated monomers.4. The electrolyte membrane according to claim 3 , wherein the difference in average degree of sulfonation between the two or more sulfonated polymers is larger than the maximum of the standard deviations of the individual degrees of sulfonation of the two or more sulfonated polymers.5. The electrolyte membrane according to claim 4 , wherein the average degrees of sulfonation of the two or more sulfonated polymers are different from each other by at least 5 to 40%.6. The electrolyte membrane according to claim 5 , wherein each of the two or more sulfonated polymers is a block copolymer prepared by condensation of one or more monomers having a sulfonic acid group and one or more monomers having no ...

MULTI-CHANNEL PACKAGE AND ELECTRONIC SYSTEM INCLUDING THE SAME

A multi-channel package has at least four channels and includes a package substrate having a first surface and a second surface, semiconductor chips mounted on the first surface of the package substrate, and external connection terminals disposed on the second surface of the package substrate and electrically connected to the semiconductor chips by the at least four channels. Each channel is dedicated to one or a group of the chips. An electronic system includes a main board, at least one such multi-channel package mounted on the main board, and a controller package that is mounted on the main board, has 4n channels (wherein n≧2) and controls the at least one multi-channel package. 1. A multi-channel package having at least four channels , and comprising:a package substrate having a first surface and a second surface;4n semiconductor chips mounted to the package substrate on the first surface thereof, wherein n is a positive integer; anda plurality of external connection terminals on the second surface of the package substrate, andwherein each of the channels constitutes a discrete path in the package associated with and along which signals are transmitted to/from a respective one or group of the semiconductor chips in the package, and each of the channels is discrete and independent from the other channels in the package such that each of the chips can transmit/receive signals to/from the external connection terminals via only one of the channels amongst the at least four channels.2. The multi-channel package of claim 1 , wherein at least one of the semiconductor chips associated with each of the channels has a plurality of chip pads claim 1 ,the external connection terminals include groups of external connection terminals, the number of groups of the external connection terminals being the same as the number of terminals,the package substrate has groups of bonding pads on the first surface of the package substrate, each of the groups of bonding pads constituting a ...

CORE-SHELL STRUCTURED ELECTROCATALYSTS FOR FUEL CELLS AND PRODUCTION METHOD THEREOF

Disclosed is a method for producing a core-shell structured electrocatalyst for a fuel cell. The method includes uniformly supporting nano-sized core particles on a support to obtain a core support, and selectively forming a shell layer only on the surface of the core particles of the core support. According to the method, the core and the shell layer can be formed without the need for a post-treatment process, such as chemical treatment and heat treatment. Further disclosed is a core-shell structured electrocatalyst for a fuel cell produced by the method. The core-shell structured electrocatalyst has a large amount of supported catalyst and exhibits superior catalytic activity and excellent electrochemical properties. Further disclosed is a fuel cell including the core-shell structured electrocatalyst. 1. A method for preparing core nanoparticles supported on a support for a core-shell structured electrocatalyst , comprising(a) reacting a support with a precursor of at least one core-forming metal in an ether-based solvent.2. The method according to claim 1 , wherein the reaction in step (a) is carried out at 80 to 120° C.3. The method according to claim 1 , wherein the core is composed of an alloy of Pd and Cu claim 1 , and step (a) is carried out at room temperature.4. The method according to claim 1 , wherein the ether-based solvent is selected from benzyl ether claim 1 , phenyl ether claim 1 , dimethoxytetraglycol claim 1 , furan-based aromatic ethers claim 1 , and mixtures of two or more thereof.5. A method for producing a core-shell structured electrocatalyst for a fuel cell claim 1 , comprising(a) reacting a support with a precursor of at least one core-forming metal in an ether-based solvent to obtain core nanoparticles supported on the support, and(b) reducing a precursor of at least one shell-forming metal using an ester-based reducing agent in a solution in which the core nanoparticles supported on the support are dipped or dispersed.7. The method ...

INTACT METHOD OF EVALUATING UNIT CELLS IN A FUEL CELL STACK AND A DEVICE USING THE SAME

Disclosed are a method and an apparatus for an intact evaluation of the unit cells in a fuel cell stack. Since the degradation of the unit cells can be detected intactly, i.e. without disassembly of the stack, the time required for the detection and analysis thereof can be greatly reduced. 2. The apparatus according to claim 1 , wherein Cand Iare obtained from at least two ΔV/Δtvalues and at least two Ivalues in a zone where Ihas a positive value.3. The apparatus according to claim 2 , wherein the apparatus for evaluating the degradation of unit cells in a fuel cell stack further comprises: a fuel supplier for supplying fuel to an anode of the fuel cell; and an oxidant supplier for supplying oxidant to a cathode of the fuel cell.4. The apparatus according to claim 3 , wherein the number of the voltage measuring device is from 1 to n.5. The apparatus according to claim 4 , wherein the number of the voltage measuring device is from 1 to (n−1) claim 4 , and the voltage measuring device further comprises a connection terminal switching means allowing at least one of the voltage measuring device to measure voltage multiple times by switching a connection terminal from a measured separator to a separator to be measured.6. The apparatus according to claim 5 , wherein the voltage measuring device further comprises a sequence input means allowing to input the sequence of voltage measurement of the separators.7. A degradation detecting system for a vehicle comprising the apparatus for evaluating the degradation according to .87. The degradation detecting system for a vehicle according to claim claim 1 , wherein the degradation detecting system for a vehicle further comprises a warning display means warning when at least part or all of the measured physical property values are below predetermined values.9. The degradation detecting system for a vehicle according to claim 8 , wherein the degradation detecting system for a vehicle further comprises a means stopping current flow ...

EMI SHIELDED SEMICONDUCTOR PACKAGE AND EMI SHIELDED SUBSTRATE MODULE

An EMI shielded semiconductor package includes a semiconductor package and an EMI shield layer formed on at least a part of a surface of the EMI shielded semiconductor package. The EMI shield layer includes a matrix layer; a metal layer positioned on the matrix layer; and a first seed particle positioned in an interface between the matrix layer and the metal layer. Unlike a conventional shielding process that is performed for a device level, a shielding process may be performed for a mounting substrate level, and thus the semiconductor package and the substrate module may be manufactured with high-productivity at low costs in a short period of time. 1. An electromagnetic interference (EMI) shielded semiconductor package comprising:a semiconductor package; andan EMI shield layer on at least a part of a surface of the EMI shielded semiconductor package, a matrix layer;', 'a metal layer on the matrix layer; and', 'a first seed particle in an interface between the matrix layer and the metal layer., 'wherein the EMI shield layer includes,'}2. The EMI shielded semiconductor package of claim 1 , wherein the first seed particle includes a core particle and a surface modifying layer coated on at least a part of the core particle.3. The EMI shielded semiconductor package of claim 2 , wherein the surface modifying layer is between the core particle and the matrix layer.4. The EMI shielded semiconductor package of claim 2 , wherein the surface modifying layer includes at least one of a polymer containing a thiol (—SH) group claim 2 , a silane-based compound containing an alkoxy group with 1 to 10 carbon atoms claim 2 , acetylacetone and a mixture thereof.5. The EMI shielded semiconductor package of claim 2 , wherein the core particle is at least one of a metal and metal oxide.6. The EMI shielded semiconductor package of claim 2 , further comprising:a second seed particle in the matrix layer.7. The EMI shielded semiconductor package of claim 6 , wherein the second seed particle ...

Multi-chip package

A multi-chip package may include a package substrate, a connecting substrate, a plurality of semiconductor chips and a logic chip. The package substrate may have an opening. The connecting substrate may be arranged on an upper surface of the package substrate. The semiconductor chips may be stacked on an upper surface of the connecting substrate. The semiconductor chips may be electrically connected with the connecting substrate. The logic chip may be arranged in the opening. The logic chip may be electrically connected between the connecting substrate and the package substrate. Thus, the logic chip may not act as to increase a width of the multi-chip package.

CORE-SHELL STRUCTURED ELECTROCATALYSTS FOR FUEL CELLS AND PRODUCTION METHOD THEREOF

Disclosed is a method for producing a core-shell structured electrocatalyst for a fuel cell. The method includes uniformly supporting nano-sized core particles on a support to obtain a core support, and selectively forming a shell layer only on the surface of the core particles of the core support. According to the method, the core and the shell layer can be formed without the need for a post-treatment process, such as chemical treatment and heat treatment. Further disclosed is a core-shell structured electrocatalyst for a fuel cell produced by the method. The core-shell structured electrocatalyst has a large amount of supported catalyst and exhibits superior catalytic activity and excellent electrochemical properties. Further disclosed is a fuel cell including the core-shell structured electrocatalyst. 1. A method for preparing core nanoparticles supported on a support for a core-shell structured electrocatalyst , comprising(a) reacting a support with a precursor of at least one core-forming metal in an ether-based solvent.2. The method according to claim 1 , wherein the reaction in step (a) is carried out at 80 to 120° C.3. The method according to claim 1 , wherein the core is composed of an alloy of Pd and Cu claim 1 , and step (a) is carried out at room temperature.4. The method according claim 1 , wherein the ether-based solvent is selected from benzyl ether claim 1 , phenyl ether claim 1 , dimethoxytetraglycol claim 1 , furan-based aromatic ethers claim 1 , and mixtures of two or more thereof.5. A method for producing a core-shell structured electrocatalyst for a fuel cell claim 1 , comprising(a) reacting a support with a precursor of at least one core-forming metal in an ether-based solvent to obtain core nanoparticles supported on the support, and(b) reducing a precursor of at least one shell-forming metal using an ester-based reducing agent in a solution in which the core nanoparticles supported on the support are dipped or dispersed.7. The method according ...

ULTRAL-LOW LOADING OF Pt-DECORATED Ni ELECTROCATALYST, MANUFACTURING METHOD OF THE SAME AND ANION EXCHANGE MEMBRANE WATER ELECTROLYZER USING THE SAME

Provided is an electrocatalyst for anion exchange membrane water electrolysis, including a carbonaceous material, and nickel electrodeposited on the carbonaceous material, wherein nickel is partially substituted with platinum and the substitution with platinum provides increased hydrogen evolution activity as compared to the same electrocatalyst before substitution with platinum. Also provided are a method for preparing the electrocatalyst and an anion exchange membrane water electrolyzer using the same. The nickel electrocatalyst coated with an ultralow loading amount of platinum for anion exchange membrane water electrolysis shows excellent hydrogen evolution activity and has a small thickness of catalyst, thereby providing high mass transfer and high catalyst availability. In addition, the electrocatalyst uses a particle-type electrode to facilitate emission of hydrogen bubbles generated during hydrogen evolution reaction and oxygen bubbles generated during oxygen evolution reaction, and requires low cost for preparation to provide high cost-efficiency. 1. An electrocatalyst for an anion exchange membrane water electrolysis , comprising: a carbonaceous material; and a nickel electrodeposited on the carbonaceous material , wherein the nickel is partially substituted with a platinum and the substitution with the platinum provides an increased hydrogen evolution activity as compared to the same electrocatalyst before substitution with the platinum.2. The electrocatalyst according to claim 1 , wherein a surface of the nickel is coated with the platinum.3. The electrocatalyst according to claim 2 , wherein the nickel is nickel particles having a particle shape and the surface of nickel particles is partially or totally coated with platinum.4. The electrocatalyst according to claim 1 , wherein the platinum is included in a loading amount of 1.0-2.3 μg/cm.5. The electrocatalyst according to claim 1 , wherein the platinum is distributed on the surface of nickel in the ...

SEMICONDUCTOR PACKAGES HAVING IMPROVED THERMAL DISCHARGE AND ELECTROMAGNETIC SHIELDING CHARACTERISTICS

A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole. 1. A semiconductor package , comprising:a first semiconductor chip on a wiring substrate, the first semiconductor chip electrically connected to the wiring substrate;an intermediate layer on the first semiconductor chip, the intermediate layer covering an entire surface of the first semiconductor chip;a second semiconductor chip on the intermediate layer, the second semiconductor chip electrically connected to the wiring substrate;a mold layer on the wiring substrate, the mold layer covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces at least partially defining a mold via hole that exposes a portion of a surface of the intermediate layer;an electromagnetic shielding layer on the one or more inner surfaces of the mold layer, the electromagnetic shielding layer further on one or more outer surfaces of the mold layer; anda thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.2. The semiconductor package of claim 1 , whereinthe ...

Electronic device including semiconductor device package

An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls. 1. A semiconductor package , comprising:a package substrate;a processor chip mounted on a first region of the package substrate;a plurality of memory chips mounted on a second region of the package substrate, the second region of the package substrate being spaced apart from the first region of the package substrate;a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate; anda plurality of first bonding wires that connect the plurality of memory chips to the signal transmission device, upper pads in an upper surface portion of the signal transmission device, the upper pads connected to the plurality of first bonding wires;', 'penetrating electrodes in a main body portion of the signal transmission device, the penetrating electrodes connected to the upper pads; and', 'lower pads in a lower surface portion of the signal transmission device, the lower pads connected to the penetrating electrodes and connected to the package substrate via bonding balls., 'wherein the signal ...

SEMICONDUCTOR PACKAGE

A semiconductor package including a mounting board, a first semiconductor chip on the mounting board, the first semiconductor chip having a first peripheral area, a second peripheral area, and a central area between the first and second peripheral areas, the central area having penetrating electrodes formed therein, a second semiconductor chip on the first peripheral area, the second semiconductor chip including a second pad on a top surface thereof, a third semiconductor chip on the second peripheral area, the third semiconductor chip including a third pad on a top surface thereof, and conductive wirings extending from the second and third pads, respectively, the conductive wirings electrically connected to the penetrating electrodes, respectively, may be provided. 1. A semiconductor package , comprising:a mounting board;a first semiconductor chip on the mounting board, the first semiconductor chip having a first peripheral area, a second peripheral area, and a central area between the first and second peripheral areas, the central area including penetrating electrodes and first pads, the penetrating electrodes penetrating the central area, the first pads on and electrically connected to the penetrating electrodes, respectively;a second semiconductor chip on the first peripheral area, the second semiconductor chip including a second pad on a top surface thereof;a third semiconductor chip on the second peripheral area, the third semiconductor chip including a third pad on a top surface thereof;conductive wirings extending from the second and third pads, respectively, the conductive wirings electrically connected to the penetrating electrodes, respectively.a plurality of first heat dissipation terminals being between the mounting board and the first peripheral area of the first semiconductor chip, the plurality of first heat dissipation terminals not being in connection with the penetrating electrodes; anda plurality of second heat dissipation terminals being between ...

Semiconductor package

A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, a heat emission member on the lower semiconductor chip, the heat emission member having a horizontal unit and a vertical unit connected to the horizontal unit, a first semiconductor chip stack and a second semiconductor chip stack on the horizontal unit, and a molding member that surrounds the lower semiconductor chip, the first and second semiconductor chip stacks, and the heat emission member. The vertical unit may be arranged between the first semiconductor chip stack and the second semiconductor chip stack, and an upper surface of the vertical unit may be exposed in the molding member.

SEMICONDUCTOR DEVICE

Provided is a semiconductor device having as many input/output pads as possible using a chip having a small number of input/output pads. The semiconductor device includes a substrate including first and second extending input/output pads, a first memory structure disposed on the substrate and including first connecting input/output pads, a second memory structure disposed on the first memory structure and including second connecting input/output pads, and a wiring structure formed on lateral surfaces of the first and second memory structures and connecting the first and second connecting input/output pads and the first and second extending input/output pads, respectively; wherein the wiring structure includes a first wiring connecting the first connecting input/output pads and the first extending input/output pad and a second wiring connecting the first connecting input/output pads and the second extending input/output pad, and the second wiring is offset relative to the first wiring. 1. A semiconductor device comprising:a substrate including first and second extending input/output pads;a first memory structure disposed on the substrate and including first connecting input/output pads;a second memory structure disposed on the first memory structure and including second connecting input/output pads; anda wiring structure formed on lateral surfaces of the first and second memory structures and connecting the first and second connecting input/output pads and the first and second extending input/output pads, respectively,wherein the wiring structure includes a first wiring connecting the first connecting input/output pads and the first extending input/output pad and a second wiring connecting the first connecting input/output pads and the second extending input/output pad, and the second wiring is offset relative to the first wiring.2. The semiconductor device of claim 1 , wherein the first memory structure includes a plurality of memory chips.3. The semiconductor ...

Semiconductor device package

An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.

Semiconductor packages having improved thermal discharge and electromagnetic shielding characteristics

A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.

Rubber liquid spray lid having embedded pumping device

Disclosed is a rubber liquid spray lid having an embedded pumping device comprising a rubber lid serving as a pushing member and having a plurality of first air inlet holes and a pumping force generation variable space therein, a first valve received in a first valve groove formed in the rubber lid for allowing liquid in the pumping force generation variable space to be sprayed outside, and a middle valve connected to the first valve and installed in a center portion of a lower part of the rubber lid for allowing liquid in a liquid vessel to be transferred from the liquid vessel to the pumping force generation variable space and for preventing the liquid in the pumping force generation variable space from flowing back into the liquid vessel, wherein the middle valve comprises a connecting and fixing part connected to a first end of a pipe having a second end dipped in liquid in the liquid vessel, a cover part provided to the circumferential outer surface of the connecting and fixing part, and a stepped platform having a plurality of second air inlet holes connected to the first air inlet holes and an elevated portion for providing a second valve installation groove therein, so that a second valve is installed in the second valve installation groove.

Liquid container with simple structure

Disclosed is a liquid container having a pumping device with a simple structure. The liquid container has a container portion for containing liquid, a first valve installed on the opening of the container portion, a pressing portion installed on the first valve, and a second valve installed on the pressing portion. The first valve allows outflow of the liquid in the container portion, and prevents inflow of the liquid into the container portion. The pressing portion forms a pressing space on the outer , side of the first valve, and is made of soft material. The second valve allows outflow of the liquid in the pressing space, and prevents inflow of the liquid into the pressing portion. The first valve and the second valve have a protrusion protruding outward and formed with slits. The protrusion is made of soft material so. that the slits are opened and closed elastically. As the pumping device and the liquid container is constituted by a small number of parts, the manufacturing cost is low, the manufacturing process becomes simple, and the breakdown of the product is rare.

Cholesterol in blood-lowering composition and its complex, and method for preparing them

The present invention relates to a composition and complex for reducing the cholesterol in the blood, particularly LDL cholesterol, and for curing the cholesteremia or some of heart diseases, as well as to a method for manufacturing those compositions and complex substances, wherein complexes or mixed compositions consisting of phyto-sterols, naturally occurring plant sterols, and tannins, as the main components, are used as pharmaceutical preparations, medicinal injections, food additives or the like to effectuate innovative reduction in the cholesterol value in the blood. Particularly, the complexes and mixed compositions according to the invention have the merit of convenience in that direct addition to the foodstuffs can produce the action of reducing the cholesterol value without doing any harm on human body.

Unit cell of honeycomb-type solid oxide fuel cell, stack using the unit cell and method manufacturing the unit cell and stack

Disclosed is a unit cell of a honeycomb-type solid oxide fuel cell (SOFC) having a plurality of channels. The channels include cathode channels and anode channels. The cathode channels and anode channels are set up alternately in the unit cell. A collector is installed inside each of the cathode channels and the anode channels, and a packing material is packed into the channels having the collector. Disclosed also is a stack including the unit cells and methods for manufacturing the unit cell and the stack.

Method for preparing membrane-electrode assembly, membrane-electrode assembly prepared therefrom and fuel cell comprising the same

Provided is a method for producing a membrane-electrode assembly for a full cell, comprising: preparing catalyst ink slurry from a catalyst, an ion conductive polymer and a solvent; applying the catalyst ink slurry onto a support film, followed by vacuum drying; and transferring the support film to either surface or both surfaces of an electrolyte membrane to form a catalyst layer on the electrolyte membrane. A membrane-electrode assembly obtained by the method and a fuel cell including the membrane-electrode assembly are also provided. The method provides a membrane-electrode assembly having increased porosity, and thus the membrane-electrode assembly shows significantly reduced mass transfer resistance. Therefore, the output density and the quality of the fuel cell including the membrane-electrode assembly prepared therefrom can be improved.

Semiconductor package and method for fabricating the same

A semiconductor package and method of fabricating the same are provided. The semiconductor package includes a first semiconductor chip including first and second surfaces opposite to each other; connection terminals on the first surface of the first semiconductor chip; a first dielectric layer on the second surface of the first semiconductor chip; a second semiconductor chip on the first dielectric layer and including a third surface opposite to the second surface and a fourth surface opposite to the third surface; a second dielectric layer on the third surface of the second semiconductor chip and in contact with the first dielectric layer; a third semiconductor chip on the fourth surface of the second semiconductor chip; and a first adhesive layer between the second semiconductor chip and the third semiconductor chip, the first dielectric layer and the second dielectric layer including no wirings.

Method for preparing membrane-electrode assembly, membrane-electrode assembly prepared therefrom and fuel cell comprising the same

Provided is a method for producing a membrane-electrode assembly for a full cell, comprising: preparing catalyst ink slurry from a catalyst, an ion conductive polymer and a solvent; applying the catalyst ink slurry onto a support film, followed by vacuum drying; and transferring the support film to either surface or both surfaces of an electrolyte membrane to form a catalyst layer on the electrolyte membrane. A membrane-electrode assembly obtained by the method and a fuel cell including the membrane-electrode assembly are also provided. The method provides a membrane-electrode assembly having increased porosity, and thus the membrane-electrode assembly shows significantly reduced mass transfer resistance. Therefore, the output density and the quality of the fuel cell including the membrane-electrode assembly prepared therefrom can be improved.

Low resistivity copper conductor line, liquid crystal display device having the same and method for forming the same

A method for forming a low resistivity copper conductor line includes forming a silver material layer on silicon material, and forming a copper material layer on the silver material layer using an electroplating process.

Semiconductor Packages Having Improved Thermal Discharge And Electromagnetic Shielding Characteristics

Hard-Handover unterstützendes paketvermitteltes Funkkommunikationssystem sowie Verfahren für Hard-Handover

Packet switched radio communication system supporting hard handover and method for hard handover

Semiconductor package including processor chip and memory chip

A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.

ハードハンドオーバーを支援するパケットスイッチング無線通信システム及びハードハンドオーバー方法

【課題】ハードハンドオーバーを支援するパケットスイッチング無線通信システムとして、Ａｌｗａｙｓ＿ｏｎ技術をターゲットパケットデータサービスノードと支援パケットデータサービスノード間のリンクに適用する。 【解決手段】支援ＰＤＳＮは、サービス領域内のＭＳに一時ＩＰアドレスを割り当て、ダイレクトリンクを介して隣接したＰＤＳＮへハンドオーバー情報及び一時ＩＰアドレスを伝送する。ターゲットＰＤＳＮは、サービス領域内に移動したＭＳからの一時ＩＰアドレスに関する登録要請を受信すれば、一時ＩＰアドレスをＩＰプールに一時的に登録する。ターゲットＰＤＳＮは、一時的に登録されたＩＰアドレスにおいてＭＳに関するダウンリンクフレームデータをダイレクトリンクを介して支援ＰＤＳＮから受信する。ＭＳへのデータ送受信が完了すれば、ターゲットＰＤＳＮによって新しい一時ＩＰアドレスが付与される。 【選択図】図３

Pd-y alloy catalyst, method for preparing the same, and fuel cell comprising the catalyst

Disclosed are a platinum (Pt)-free, palladium (Pd)-yttrium (Y) alloy catalyst having superior oxygen reduction reaction activity and stability, a method for preparing the same, and a fuel cell including the catalyst. Since the Pt-free Pd-Y catalyst is inexpensive, it may be usefully applicable for fuel cells, particularly polymer electrolyte membrane fuel cells.

Intact method of evaluating unit cells in a fuel cell stack and a device using the same

Disclosed are a method and an apparatus for an intact evaluation of the unit cells in a fuel cell stack. Since the degradation of the unit cells can be detected intactly, i.e. without disassembly of the stack, the time required for the detection and analysis thereof can be greatly reduced.