Semiconductor device and method of forming an embedded sop fan-out package

POWER AMPLIFIER MODULES INCLUDING RELATED SYSTEMS, DEVICES, AND METHODS

CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP PACKAGE

A chip package is provided, the chip package including: a carrier including at least one cavity; a chip disposed at least partially within the at least one cavity; at least one intermediate layer disposed over at least one side wall of the chip; wherein the at least one intermediate layer is configured to thermally conduct heat from the chip to the carrier.

PROCEDURE FOR APPLYING AN SI OR A GE OF CONTAINING MATERIAL ON A SURFACE FROM CU OR NI

Package structure

Semiconductor packaging structure and packaging technology thereof

The present invention discloses a semiconductor packaging structure with built-in electronic elements and packaging technology thereof. By means of more than two structural modules formed in advance, the electric elements can be assembled on the structural modules after conjoining so as to obtain the semiconductor packaging structure. By means of the structural modules formed in advance, it is possible to simplify the packaging technology of the semiconductor packaging structure and provide a great technology flexibility. Thereby, it is possible to shorten assembling time interval of the semiconductor packaging structure and improve finished product yield.

Power amplifier modules including related systems, devices, and methods

A power amplifier module includes a power amplifier including a GaAs bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3x1016 cm-3 at a junction with the base, the collector also having at least a first grading in which doping concentration increases away from the base; and an RF transmission line driven by the power amplifier, the RF transmission line including a conductive layer and finish plating on the conductive layer, the finish plating including a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer including nickel and having a thickness that is less than about the skin depth of nickel at 0.9 GHz. Other embodiments of the module are provided along with related methods and components thereof.

TIN-BASED WIREBOND STRUCTURES

Tin-based wirebond structures and wirebonds formed thereon. In some embodiments, an electronic package includes a semiconductor die located over a substrate and a wire configured to couple a terminal of the semiconductor die to a bond pad on the substrate. A wire bond between the wire and the bond pad may include an amount of tin originated from a layer of tin alloy formed on the bond pad. In other embodiments, a wirebond structure may include a conductive layer and a layer of tin alloy located over a portion of the conductive layer. The layer of tin alloy may provide a wirebonding contact surface configured to receive a bond wire.

ELECTRONIC DEVICES HAVING METALLURGIES CONTAINING COPPER-SEMICONDUCTOR COMPOUNDS

Thin integrated circuit chip-on-board assembly

An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface, where the first surface of the insulating layer is less than 10 microns below an upper plane of the integrated circuit assembly. An active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the active layer and formed on the second surface of the insulating layer, and is also electrically connected to a printed circuit board.

POWER AMPLIFIER MODULES WITH BONDING PADS AND RELATED SYSTEMS, DEVICES, AND METHODS

One aspect of this disclosure is a power amplifier module that includes a power amplifier die, a first bonding pad on a conductive trace, and a second bonding pad on a conductive trace. The die includes an on-die passive device and a power amplifier. The first bonding pad is electrically connected to the on-die passive device by a first wire bond. The second bonding pad is in a conductive path between the first bonding pad and a radio frequency output of the power amplifier module. The second bonding pad includes a nickel layer having a thickness that is less than 0.5 um, a palladium layer over the nickel layer, and a gold layer over the palladium layer and bonded to a second wire bond that is electrically connected to an output of the power amplifier. Other embodiments of the module are provided along with related methods and components thereof.

계조를 갖는 쌍극성 트랜지스터 및 관련된 시스템, 장치, 및 방법을 포함하는 전력 증폭기 모듈

본 기재의 일 특징은, 전력 증폭기와 수동 컴포넌트를 포함하는 제1 다이 - 전력 증폭기는 콜렉터, 콜렉터에 인접한 베이스, 및 에미터를 갖는 쌍극성 트랜지스터를 포함하고, 콜렉터는 베이스와의 인터페이스에서 적어도 약 3x10 16 cm -3 의 도핑 농도를 가지며, 콜렉터는 또한, 베이스로부터 멀어질수록 도핑 농도가 증가하는 계조를 가짐 - ; 및 제1 다이의 수동 컴포넌트의 전기적 속성의 표시(indication)에 적어도 부분적으로 기초하여 바이어스 신호를 생성하고 바이어스 신호를 전력 증폭기에 제공하도록 구성된 바이어스 회로를 포함하는 제2 다이를 포함하는 전력 증폭기 모듈이다. 모듈의 다른 실시예들이 그의 관련된 방법들 및 컴포넌트들과 함께 제공된다. One feature of the present disclosure is that the first die-to-power amplifier comprising a power amplifier and a passive component includes a collector, a base adjacent to the collector, and a bipolar transistor having an emitter, A doping concentration of 3 x 10 16 cm -3 , and the collector also has a gradation that the doping concentration increases as the distance from the base increases; And a second die comprising a bias circuit configured to generate a bias signal based at least in part on an indication of an electrical property of the passive component of the first die and to provide a bias signal to the power amplifier . Other embodiments of the module are provided with its associated methods and components.

Wire bonding method for copper wire and support plate pad, and structure

PACKAGE-ON-PACKAGE (POP) STRUCTURE AND METHOD

Power amplifier modules

Multi-chip semiconductor packages and assembly thereof

Semiconductor packages and method of fabricating them are described. In one embodiment, the semiconductor package includes a substrate having a first and a second die attach pad. A first die is disposed over the first die attach pad. A second die is disposed over the second die attach pad. A third die is disposed between the first and the second die. The third die having a first, a second, and a third portion such that the first portion is disposed above a portion of the first die, the second portion is disposed above a portion of the second die, and the third portion is disposed above an area between the first die and the second die.

Method for manufacturing electronic devices

An embodiment for manufacturing electronic devices is proposed. The embodiment includes the following phases: a) forming a plurality of chips in a semiconductor material wafer including a main surface; each chip includes respective integrated electronic components and respective contact pads facing the main surface; said contact pads are electrically coupled to the integrated electronic components; b) attaching at least one conductive ribbon to at least one contact pad of each chip; c) covering the main surface of the semiconductor material wafer and the at least one conductive ribbon with a layer of plastic material; d) lapping an exposed surface of the layer of plastic material to remove a portion of the plastic material layer at least to uncover portions of the at least one conductive ribbon, and e) sectioning the semiconductor material wafer to separate the chips.

BIFET 및 고조파 종단 및 관련된 시스템, 장치, 및 방법을 갖는 전력 증폭기 모듈

... 본 기재의 일 특징은, 무선 주파수(RF) 신호를 증폭하도록 구성된 전력 증폭기를 포함하는 전력 증폭기 다이 - 전력 증폭기는 이종접합 쌍극성 트랜지스터(HBT) 및 p-타입 전계 효과 트랜지스터(PFET)를 포함하고, PFET 은 HBT의 콜렉터의 층과 실질적으로 동일한 재료를 포함하는 반도체 세그먼트를 포함하고, 반도체 세그먼트는 PFET의 채널에 대응함 - ; 전력 증폭기의 출력에 전기적으로 접속되고 RF 신호의 기본 주파수에서 임피던스 정합을 제공하도록 구성된 부하선; 및 전력 증폭기의 출력에 전기적으로 접속되고 RF 신호의 고조파 주파수에 대응하는 위상에서 종단하도록 구성된 고조파 종단 회로를 포함하는 전력 증폭기 모듈이다. 모듈의 다른 실시예들이 그의 관련된 방법들 및 컴포넌트들과 함께 제공된다.

LIGHT EMITTING DEVICE, METHOD FOR FABRICATING THE LIGHT EMITTING DEVICE AND BACKLIGHT UNIT

실시예에 따른 발광 소자는 상부가 개방되도록 형성된 캐비티를 포함하며, 상기 캐비티의 측벽은 상기 캐비티의 바닥면에 대해 제1 각도로 경사진 몸체; 상기 몸체에 형성되며, 적어도 일부분이 상기 캐비티의 측벽을 따라 형성된 제1 전극 및 제2 전극; 상기 제1 전극, 상기 제2 전극 및 상기 캐비티의 바닥면 중 어느 하나 위에 탑재된 발광칩; 일단은 상기 발광칩 상면에 본딩되고, 타단은 상기 캐비티의 측벽에 형성된 상기 제1 전극 및 제2 전극 중 적어도 하나에 본딩되는 적어도 하나의 와이어; 및 상기 캐비티 내에 형성되어 상기 발광칩을 밀봉하는 몰딩부재를 포함한다.

Semiconductor device including an insulating film and insulating pillars and manufacturing method of the semiconductor device

A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.

ELECTRONIC DEVICES HAVING METALLURGIES CONTAINING COPPER-SEMICONDUCTOR COMPOUNDS

Silicon and germanium containing materials are used as a surface of conductors in electronic devices. Solder can be fluxlessly bonded and wires can be wire bonded to these surfaces. These materials are used as a surface coating for lead frames for packaging integrated circuit chips. These materials can be decal transferred onto conductor surfaces or electrolessly or electrolytically disposed thereon.

Nitride semiconductor device

本发明的氮化物半导体装置具备：在氮化物半导体层之上形成的第1电极布线层以及第2电极布线层、在第1电极布线层以及第2电极布线层之上形成且具有第1开口部的第1绝缘膜、在第1绝缘膜之上形成且经由第1开口部而与第1电极布线层以及第2电极布线层分别连接的第1布线层(17a)以及第2布线层(17b)、在第1布线层以及第2布线层之上形成且具有第2开口部的第2绝缘膜(18)、和在第2绝缘膜之上形成且经由第2开口部而与第1布线层以及第2布线层分别连接的第1焊盘层(22a)以及第2焊盘层(22b)。

METODO PARA DEPOSICAO SOBRE UMA SUPERFICIE DE UM MATERIAL E ESTRUTURA PARA PROVISAO DE INTERCONEXAO ELETRICA A UMA MICROPLAQUETA SEMICONDUTORA QUE O UTILIZA

Power amplifier modules including related systems, devices, and methods

A power amplifier module includes a power amplifier including a GaAs bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3x1016cm-3at a junction with the base, the collector also having at least a first grading in which doping concentration increases away from the base; and an RF transmission line driven by the power amplifier, the RF transmission line including a conductive layer and finish plating on the conductive layer, the finish plating including a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer including nickel and having a thickness that is less than about the skin depth of nickel at 0.9 GHz. Other embodiments of the module are provided along with related methods and components thereof.

Multichip-Halbleitergehäuse und deren Zusammenbau

Es werden Halbleitergehäuse und Verfahren zu ihrer Herstellung beschrieben. In einer Ausführungsform enthält das Halbleitergehäuse ein Substrat mit einem ersten und einem zweiten Die-Attach-Pad. Ein erstes Mikroplättchen wird über dem ersten Die-Attach-Pad angeordnet. Ein zweites Mikroplättchen wird über dem zweiten Die-Attach-Pad angeordnet. Ein drittes Mikroplättchen wird zwischen dem ersten und dem zweiten Mikroplättchen angeordnet. Das dritte Mikroplättchen hat einen ersten, einen zweiten und einen dritten Teil derart, dass der erste Teil über einem Teil des ersten Mikroplättchens angeordnet ist, der zweite Teil über einem Teil des zweiten Mikroplättchens angeordnet ist, und der dritte Teil über einem Bereich zwischen dem ersten Mikroplättchen und dem zweiten Mikroplättchen angeordnet ist.

Contain relevant system, device and method of power amplifier module

PACKAGE-ON-PACKAGE (POP) STRUCTURE AND METHOD

Package on-package (PoP) structure including stud bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

In package package and its forming method

ELECTRONIC DEVICES HAVING METALLURGIES CONTAINING COPPER-SEMICONDUCTOR COMPOUNDS

Power amplifier modules

本發明揭示一種功率放大器模組，其包括：一功率放大器，其包括一GaAs雙極電晶體，該GaAs雙極電晶體具有一集極、鄰接該集極之一基極、及一射極，該集極在與該基極之一接面處具有至少約3×10 16 cm -3 之一摻雜濃度，該集極亦具有其中摻雜濃度隨遠離該基極而增加之至少一第一分級；及一RF傳輸線，其由該功率放大器驅動，該RF傳輸線包括一導電層及該導電層上之表面處理鍍層，該表面處理鍍層包括一金層、接近該金層之一鈀層及接近該鈀層之一擴散障壁層，該擴散障壁層包括鎳且具有約小於鎳在0.9 GHz下之集膚深度之一厚度。本發明亦提供該模組之其他實施例連同其相關方法及組件。

Power amplifier modules

Power amplifier modules

Package on-Package (PoP) structure including stud bulbs and method

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Chipbaugruppe und Verfahren zur Herstellung einer Chipbaugruppe

Chipbaugruppe, die Folgendes aufweist:einen Träger, der wenigstens einen Hohlraum aufweist, wobei der wenigstens eine Hohlraum Hohlraumseitenwände und eine Hohlraumbodenwand aufweist;einen Chip, der wenigstens teilweise innerhalb des wenigstens einen Hohlraums angeordnet ist, wobei eine Chiprückseite des Chips der Hohlraumbodenwand zugewandt ist;wenigstens eine Zwischenschicht, die über wenigstens einer Seitenwand des Chips angeordnet ist;wobei die wenigstens eine Zwischenschicht zum Leiten von Wärme von dem Chip zu dem Träger konfiguriert ist;wobei die wenigstens eine Zwischenschicht Folgendes aufweist:eine erste Metallschicht, die über der Chiprückseite und über der wenigstens einen Seitenwand gebildet ist, wobei die erste Metallschicht wenigstens einen Teil einer Chiprückseiten-Metallisierungsschicht bildet; undeine Einzelchip-Befestigungsschicht, die über der Chiprückseite und über der wenigstens einen Seitenwand über der ersten Metallschicht gebildet ist, wobei die Einzelchip-Befestigungsschicht ...

Light emitting device, method for manufacturing the same, and backlight unit

Disclosed are a light emitting device, a method of manufacturing the same, and a backlight unit. The light emitting device includes a body including a cavity to open an upper portion, in which the cavity has a sidewall inclined at a first angle with respect to a bottom surface of the cavity, first and second electrodes formed in the body, in which at least portions of the first and second electrodes are formed along the sidewall of the cavity, a light emitting chip over the first electrode, the second electrode, and the bottom surface of the cavity, at least one wire having one end bonded to a top surface of the light emitting chip and an opposite end bonded to a portion of the first and second electrodes over the sidewall of the cavity, and a molding member formed in the cavity to seal the light emitting chip.

Power amplifier modules

A power amplifier module includes a power amplifier including a GaAs bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3x1016 cm-3 at a junction with the base, the collector also having at least a first grading in which doping concentration increases away from the base; and an RF transmission line driven by the power amplifier, the RF transmission line including a conductive layer and finish plating on the conductive layer, the finish plating including a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer including nickel and having a thickness that is less than about the skin depth of nickel at 0.9 GHz. Other embodiments of the module are provided along with related methods and components thereof.

Halbleitervorrichtungen und Halbleiterverarbeitungsverfahren

Verschiedene Ausführungsformen stellen eine Halbleitervorrichtung (310) bereit, die eine letzte Metallschicht (312), die eine Oberseite (328) und wenigstens eine Seitenwand (322) besitzt; und eine Passivierungsschicht (313), die wenigstens über einem Teil der Oberseite (328) und/oder der wenigstens einen Seitenwand (322) der letzten Metallschicht (312) angeordnet ist, aufweist; wobei die Passivierungsschicht (313) eine im Wesentlichen gleichmäßige Dicke besitzt.

Power amplifier modules

A power amplifier module includes a power amplifier including a GaAs bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3x1016 cm-3at a junction with the base, the collector also having at least a first grading in which doping concentration increases away from the base; and an RF transmission line driven by the power amplifier, the RF transmission line including a conductive layer and finish plating on the conductive layer, the finish plating including a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer including nickel and having a thickness that is less than about the skin depth of nickel at 0.9 GHz. Other embodiments of the module are provided along with related methods and components thereof.

Verfahren zum Aufbringen eines Si oder Ge enthaltenden Materials auf eine Oberfläche aus Cu oder Ni

CHIPBAUGRUPPE UND VERFAHREN ZUR HERSTELLUNG EINER CHIPBAUGRUPPE

Es wird eine Chipbaugruppe bereitgestellt, wobei die Chipbaugruppe Folgendes enthält: einen Träger, der wenigstens einen Hohlraum enthält; einen Chip, der wenigstens teilweise innerhalb des wenigstens einen Hohlraums angeordnet ist; wenigstens eine Zwischenschicht, die über wenigstens einer Seitenwand des Chips angeordnet ist; wobei die wenigstens eine Zwischenschicht zum Leiten von Wärme von dem Chip zu dem Träger konfiguriert ist.

Power amplifier modules including related systems, devices, and methods

A power amplifier module includes a power amplifier including a GaAs bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3×1016 cm3 at a junction with the base, the collector also having at least a first grading in which doping concentration increases away from the base; and an RF transmission line driven by the power amplifier, the RF transmission line including a conductive layer and finish plating on the conductive layer, the finish plating including a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer including nickel and having a thickness that is less than about the skin depth of nickel at 0.9 GHz. Other embodiments of the module are provided along with related methods and components thereof.

POWER AMPLIFIER MODULES INCLUDING TRANSISTOR WITH GRADING AND SEMICONDUCTOR RESISTOR

One aspect of this disclosure is a power amplifier module that includes a power amplifier on a substrate and a semiconductor resistor on the substrate. The power amplifier includes a bipolar transistor having a collector, a base, and an emitter. The collector has a doping concentration of at least 3×1016 cm−3 at an interface with the base. The collector also has at least a first grading in which doping concentration increases away from the base. The semiconductor resistor includes a resistive layer that that includes the same material as a layer of the bipolar transistor. Other embodiments of the module are provided along with related methods and components thereof.

Verfahren zum Aufbringen eines Si oder Ge enthaltenden Materials auf eine Oberfläche aus Cu oder Ni

와이어 본드 패드 및 관련된 시스템, 장치, 및 방법을 포함하는 전력 증폭기 모듈

... 본 기재의 일 특징은 전력 증폭기, 전력 증폭기에 전기적으로 접속된 와이어 본드 패드 - 와이어 본드 패드는 0.5μm보다 작은 두께를 갖는 니켈층, 니켈층 상의 팔라듐층, 및 팔라듐층 상의 금층을 포함함 - , 및 도금된 부분과 도금된 부분을 둘러싸는 도금되지 않은 부분을 갖는 상부 표면을 갖는 도전성 트레이스 - 와이어 본드 패드는 도금된 부분 상에 배치됨 - 를 포함하는 전력 증폭기 모듈이다. 모듈의 다른 실시예들이 그의 관련된 방법들 및 컴포넌트들과 함께 제공된다.

Embedded component substrate, semiconductor package structure using the same and fabrication methods thereof

An embedded electronic component semiconductor package structure and a packaging process thereof are provided. By providing two or more preformed building blocks, the electronic component can be assembled to the joined building blocks to obtain the embedded component semiconductor package structure.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN EMBEDDED SOP FANOUTPACKAGE

Partially patterned lead frames and methods of making and using the same in semiconductor packaging

A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.

Chipgehäuse und Verfahren zum Bilden desselben

Ausführungsformen stellen bereit ein Verfahren zum Bilden eines Chipgehäuses. Das Verfahren kann aufweisen das Befestigen mindestens eines Chips (203, 503, 805, 911) über einem Träger (201, 501, 801, 901), der Chip aufweisend eine Mehrzahl an Chip-Pads (205) auf einer Oberfläche des Chips (203, 503, 805, 911) gegenüberliegend zu dem Träger (201, 501, 801, 901); das Abscheiden einer ersten Haftschicht (207, 307) über dem Träger (201, 501, 801, 901); und den Chip-Pads (205) des Chips (203, 503, 805, 911), die erste Haftschicht (209, 309) aufweisend Zinn oder Indium; das Abscheiden einer zweiten Haftschicht (209, 309) über der ersten Haftschicht (207, 307), die zweite Haftschicht (209, 309) aufweisend ein Silan-organisches Material; und Abscheiden einer Laminierungsschicht (211, 311) oder einer Verkapselungsschicht (211, 311, 509, 809, 915) über der zweiten Haftschicht (209, 309) und dem Chip (203, 503, 805, 911).

Semiconductor packaging structure and packaging technology thereof

POWER AMPLIFIER MODULES

Power amplifier modules including tantalum nitride terminated through wafer via and related systems, devices, and methods

One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to amplify a radio frequency (RF) signal and tantalum nitride terminated through wafer via. The power amplifier includes a heterojunction bipolar transistor and a p-type field effect transistor, in which a semiconductor portion of the p-type field effect transistor corresponds to a channel includes the same type of semiconductor material as a collector layer of the heterojunction bipolar transistor. A metal layer in the tantalum nitride terminated through wafer via is included in an electrical connection between the power amplifier on a front side of a substrate and a conductive layer on a back side of the substrate. Other embodiments of the module are provided along with related methods and components thereof.

Package-in-Packages und Verfahren zu ihrer Herstellung

Gemäß einer Ausführungsform der vorliegenden Erfindung enthält ein Halbleiter-Bauelement einen Leadframe, der mehrere Leads und ein Die-Paddle aufweist, sowie ein Halbleiter-Modul, das an dem Die-Paddle des Leadframe angebracht ist. Das Halbleiter-Modul enthält einen ersten Halbleiter-Chip, der in einem ersten Kapselungsmaterial angeordnet ist. Das Halbleiter-Modul weist mehrere Kontaktpads auf, die mit dem ersten Halbleiter-Chip verbunden sind. Das Halbleiter-Bauelement enthält weiterhin mehrere Verbindungen, welche die mehreren Kontaktpads mit den mehreren Leads verbinden, und ein zweites Kapselungsmaterial, das auf dem Halbleiter-Modul und dem Leadframe angeordnet ist.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Power amplifier modules with harmonic termination circuit and related systems, devices, and methods

One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to provide a radio frequency signal at an output, an output matching network coupled to the output of the power amplifier and configured to provide impedance matching at a fundamental frequency of the radio frequency signal, and a harmonic termination circuit coupled to the output of the power amplifier. The power amplifier is included on a power amplifier die. The output matching network can include a first circuit element electrically connected to an output of the power amplifier by way of a pad on a top surface of a conductive trace, in which the top surface has an unplated portion between the pad the power amplifier die. The harmonic termination circuit can include a second circuit element. The first and second circuit elements can have separate electrical connections to the power amplifier die. Other embodiments of the module are provided along with related methods and components thereof.

SEMICONDUCTOR DEVICE

Light emitting device, method for manufacturing the same, and backlight unit

Disclosed are a light emitting device, a method of manufacturing the same, and a backlight unit. The light emitting device includes a body including a cavity to open an upper portion, in which the cavity has a sidewall inclined at a first angle with respect to a bottom surface of the cavity, first and second electrodes formed in the body, in which at least portions of the first and second electrodes are formed along the sidewall of the cavity, a light emitting chip over the first electrode, the second electrode, and the bottom surface of the cavity, at least one wire having one end bonded to a top surface of the light emitting chip and an opposite end bonded to a portion of the first and second electrodes over the sidewall of the cavity, and a molding member formed in the cavity to seal the light emitting chip.

METHOD OF CONNECTING A CONNECTING WIRE TO A CONTACT OF AN INTEGRATED CIRCUIT

L'invention concerne un circuit intégré (1) comprenant un substrat à semi-conducteur (2), qui présente des zones électriquement actives auxquelles une tension électrique peut être appliquée par l'intermédiaire de contacts de connexion (3). Les contacts de connexion (3) comportent une couche de connexion en cuivre. Sur chaque contact de connexion (3), il est prévu un fil de connexion (7) et dans une zone située entre le fil de connexion (7) et le contact de connexion (3), il est prévu une couche de plomb de soudure (6) consistant principalement en un composé de métal de soudage.

Partially patterned lead frames and methods of making and using the same in semiconductor packaging

A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.

Power amplifier modules

A power amplifier module includes a power amplifier including a GaAs bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3x1016 cm-3at a junction with the base, the collector also having at least a first grading in which doping concentration increases away from the base; and an RF transmission line driven by the power amplifier, the RF transmission line including a conductive layer and finish plating on the conductive layer, the finish plating including a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer including nickel and having a thickness that is less than about the skin depth of nickel at 0.9 GHz. Other embodiments of the module are provided along with related methods and components thereof.

THIN INTEGRATED CIRCUIT CHIP-ON-BOARD ASSEMBLY AND METHOD OF MAKING

An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface, where the first surface of the insulating layer is less than 10 microns below an upper plane of the integrated circuit assembly. An active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the active layer and formed on the second surface of the insulating layer, and is also electrically connected to a printed circuit board. A method of fabricating an integrated circuit assembly includes coupling a handle wafer to the active layer of a semiconductor-on-insulator wafer, removing the substrate of the semiconductor-on-insulator, forming a bond pad connecting to the active layer on the exposed insulator surface, bonding the bond pad to a printed circuit board using a solder bump, and removing the handle wafer.

Ultra-Thin Semiconductor Package

Semiconductor packages with a reduced-height die pad and associated methods for making and using these semiconductor packages are described. The semiconductor packages include a lead frame with die pad of reduced height so the die pad has a height that is less than that of the lead frame. The semiconductor packages may comprise an isolated and/or a fused lead finger with a portion of an upper surface of the isolated lead finger that is removed to form a concavity to which one or more bond wires may be bonded. The upper surface of the isolated lead finger may be removed so the isolated lead finger has a height that is less than the height of the lead frame. And a perimeter of a bottom surface of the fused lead finger may be removed. Other embodiments are described.

Chipgehäuse und Verfahren zum Bilden desselben

전력 증폭기와 전송 라인을 포함하는 전력 증폭기 모듈 및 관련된 시스템, 장치, 및 방법

... 본 기재의 일 특징은 전력 증폭기, 전력 증폭기에 전기적으로 접속된 와이어 본드 패드 - 와이어 본드 패드는 0.5μm보다 작은 두께를 갖는 니켈층, 니켈층 상의 팔라듐층, 및 팔라듐층 상의 금층을 포함함 - , 및 도금된 부분과 도금된 부분을 둘러싸는 도금되지 않은 부분을 갖는 상부 표면을 갖는 도전성 트레이스 - 와이어 본드 패드는 도금된 부분 상에 배치됨 - 를 포함하는 전력 증폭기 모듈이다. 모듈의 다른 실시예들이 그의 관련된 방법들 및 컴포넌트들과 함께 제공된다.

Power amplifier modules including bipolar transistor with grading and related systems, devices, and methods

One aspect of this disclosure is a power amplifier module that includes a first die including a power amplifier and a passive component, the power amplifier including a bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3×10 16 cm −3 at an interface with the base, the collector also having a grading in which doping concentration increases away from the base; and a second die including a bias circuit configured to generate a bias signal based at least partly on an indication of an electrical property of the passive component of the first die and to provide the bias signal to the power amplifier. Other embodiments of the module are provided along with related methods and components thereof.

Semiconductor device and method of forming an embedded sop fan-out package

A semiconductor device includes a ball grid array (BGA) package including first bumps. A first semiconductor die is mounted to the BGA package between the first bumps. The BGA package and first semiconductor die are mounted to a carrier. A first encapsulant is deposited over the carrier and around the BGA package and first semiconductor die. The carrier is removed to expose the first bumps and first semiconductor die. An interconnect structure is electrically connected to the first bumps and first semiconductor die. The BGA package further includes a substrate and a second semiconductor die mounted, and electrically connected, to the substrate. A second encapsulant is deposited over the second semiconductor die and substrate. The first bumps are formed over the substrate opposite the second semiconductor die. A warpage balance layer is formed over the BGA package.

Semiconductor device and manufacturing method of semiconductor device

A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.

계조를 갖는 쌍극성 트랜지스터 및 관련된 시스템, 장치, 및 방법을 포함하는 전력 증폭기 모듈

... 본 기재의 일 특징은, 전력 증폭기와 수동 컴포넌트를 포함하는 제1 다이 - 전력 증폭기는 콜렉터, 콜렉터에 인접한 베이스, 및 에미터를 갖는 쌍극성 트랜지스터를 포함하고, 콜렉터는 베이스와의 인터페이스에서 적어도 약 3x1016 cm-3의 도핑 농도를 가지며, 콜렉터는 또한, 베이스로부터 멀어질수록 도핑 농도가 증가하는 계조를 가짐 - ; 및 제1 다이의 수동 컴포넌트의 전기적 속성의 표시(indication)에 적어도 부분적으로 기초하여 바이어스 신호를 생성하고 바이어스 신호를 전력 증폭기에 제공하도록 구성된 바이어스 회로를 포함하는 제2 다이를 포함하는 전력 증폭기 모듈이다. 모듈의 다른 실시예들이 그의 관련된 방법들 및 컴포넌트들과 함께 제공된다.

SEMICONDUCTOR DEVICES AND PROCESSING METHODS

Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed over at least part of at least one of the top side and the at least one sidewall of the final metal layer; wherein the passivation layer has a substantially uniform thickness.

POWER AMPLIFIER MODULES INCLUDING RELATED SYSTEMS, DEVICES, AND METHODS

... 전력 증폭기 모듈은, 콜렉터, 콜렉터에 인접한 베이스, 및 에미터를 갖는 GaAs 쌍극성 트랜지스터를 포함하는 전력 증폭기 - 콜렉터는 베이스와의 접합부에서 적어도 약 3x1016 cm-3의 도핑 농도를 가지며, 콜렉터는 또한, 베이스로부터 멀어질수록 도핑 농도가 증가하는 적어도 제1 계조를 가짐 - ; 및 전력 증폭기에 의해 구동되는 RF 전송 라인을 포함하고, RF 전송 라인은 도전층과 도전층 상의 마무리 도금을 포함하고, 마무리 도금은 금층, 금층에 근접한 팔라듐층, 및 팔라듐층에 근접한 확산 장벽층을 포함하며, 확산 장벽층은 니켈을 포함하고 0.9 GHz에서 대략 니켈의 표피 깊이보다 작은 두께를 갖는다. 모듈의 다른 실시예들이 그의 관련된 방법들 및 컴포넌트들과 함께 제공된다.

Package-On-Package (PoP) Structure Including Stud Bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first surface of a first package;a second pad on a second surface of a second package;a metallic element interposed between the first pad and the second pad, the metallic element comprising a base portion and an elongated portion, the base portion being coupled to the first pad, the elongated portion extending from the base portion toward the second pad, wherein a width of the base portion is greater than a width of the elongated portion;a solder connector in contact with the elongated portion and electrically coupled to the second pad; andan inter-metallic compound (IMC) between the elongated portion and the solder connector.2. The device of claim 1 , wherein the first package comprises a first substrate and a first integrated circuit die attached to the first substrate claim 1 , wherein the second package comprises a second substrate and a second integrated circuit die attached to the second substrate.3. The device of claim 2 , wherein the metallic element is laterally adjacent the first integrated circuit die with the first integrated circuit die and the metallic element being interposed between the first substrate and the second substrate.4. The device of claim 3 , wherein the metallic element extends closer to the second substrate than the first integrated circuit die.5. The device of claim 1 , wherein a height of the metallic element is between about 20 micrometers and about 200 ...

Semiconductor device and method of forming an embedded SOP fan-out package

A semiconductor device includes a ball grid array (BGA) package including first bumps. A first semiconductor die is mounted to the BGA package between the first bumps. The BGA package and first semiconductor die are mounted to a carrier. A first encapsulant is deposited over the carrier and around the BGA package and first semiconductor die. The carrier is removed to expose the first bumps and first semiconductor die. An interconnect structure is electrically connected to the first bumps and first semiconductor die. The BGA package further includes a substrate and a second semiconductor die mounted, and electrically connected, to the substrate. A second encapsulant is deposited over the second semiconductor die and substrate. The first bumps are formed over the substrate opposite the second semiconductor die. A warpage balance layer is formed over the BGA package.

Multi-chip Semiconductor Packages and Assembly Thereof

Semiconductor packages and method of fabricating them are described. In one embodiment, the semiconductor package includes a substrate having a first and a second die attach pad. A first die is disposed over the first die attach pad. A second die is disposed over the second die attach pad. A third die is disposed between the first and the second die. The third die having a first, a second, and a third portion such that the first portion is disposed above a portion of the first die, the second portion is disposed above a portion of the second die, and the third portion is disposed above an area between the first die and the second die.

INTEGRATED CIRCUIT ASSEMBLY AND METHOD OF MAKING

An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface. A first active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the first active layer and formed on the second surface of the insulating layer. A substrate having a first surface and a second surface, with a second active layer formed in the first surface, is provided such that the first active layer is coupled to the second surface of the substrate.

Semiconductor device and manufacturing method of semiconductor device

A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.

Package structure

Package-On-Package (PoP) structures and methods of forming PoP structures are disclosed. According to an embodiment, a structure comprises a first substrate, stud bulbs, a die, a second substrate, and electric connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Power amplifier modules

A power amplifier module includes a power amplifier including a GaAs bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3x1016 cm-3 at a junction with the base, the collector also having at least a first grading in which doping concentration increases away from the base; and an RF transmission line driven by the power amplifier, the RF transmission line including a conductive layer and finish plating on the conductive layer, the finish plating including a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer including nickel and having a thickness that is less than about the skin depth of nickel at 0.9 GHz. Other embodiments of the module are provided along with related methods and components thereof.

Bonding pads for integrated circuits having copper interconnect metallization

A device having a thin metallic coating, such as tin which forms strong bonds to copper is provided on the bond pads of an integrated circuit having copper metallization; surface oxidation of the coating is self limiting and the oxides are readily removed, further the coated bond pad forms intermetallics at low temperatures making it both solderable and compatible with wire bonding. A low cost process for forming tin coated copper bonding pads is provided by electroless plating.

Semiconductor device

Provided is a small and thin semiconductor device while preventing contamination of a wire bonding terminal caused by creeping-up of a die bond. The semiconductor device includes: a first semiconductor chip having a main surface formed with electrodes; an extension part extended outward from a side end surface of the first semiconductor chip; a rewiring layer formed from the main surface of the first semiconductor chip to a first surface of the extension part; a connection terminal provided on the rewiring layer of the extension part; a die bond that fixes the first semiconductor chip and the extension part to a substrate; and in the extension part, a step outside the connection terminal.

パワーアンプモジュールを含む関連するシステム、デバイス、および方法

Semiconductor device with improved bonding

A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.

Partially patterned lead frames and methods of making and using the same in semiconductor packaging

A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.

Power amplifier modules including related systems, devices, and methods

A power amplifier module includes a power amplifier including a GaAs bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3x1016 cm-3 at a junction with the base, the collector also having at least a first grading in which doping concentration increases away from the base; and an RF transmission line driven by the power amplifier, the RF transmission line including a conductive layer and finish plating on the conductive layer, the finish plating including a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer including nickel and having a thickness that is less than about the skin depth of nickel at 0.9 GHz. Other embodiments of the module are provided along with related methods and components thereof.

Semiconductor device and mfg. method for same

Integrated Circuit Assembly and Method of Making

An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface. A first active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the first active layer and formed on the second surface of the insulating layer. A substrate having a first surface and a second surface, with a second active layer formed in the first surface, is provided such that the first active layer is coupled to the second surface of the substrate.

SEMICONDUCTOR DEVICE WITH INDUCTOR AND FLIP-CHIP

Semiconductor devices comprising a flip-chip having vias to connect front and back surfaces and a bondwire connected to the via or the back surface. Provision is made for packaging the flip-chip with a package substrate. Further aspects of the invention provide for inductance within the semiconductor device.

Package-on-package (PoP) structure including stud bulbs and method

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Power amplifier modules including related systems, devices, and methods

Package-On-Package (PoP) Structure Including Stud Bulbs and Method

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Package-on-package (PoP) structure including stud bulbs

Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures are provided. A structure may include a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Power amplifier modules

Semiconductor devices and processing methods

Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed over at least part of at least one of the top side and the at least one sidewall of the final metal layer; wherein the passivation layer has a substantially uniform thickness.

Solderability Improvement Method for Leaded Semiconductor Package

A microelectronic device package that includes a microelectronic device encapsulated within a packaging material. The microelectronic device package also includes a lead attached to a portion of the microelectronic device extending through the packaging material. The lead has a break portion and a non-break portion on a tip of the lead.

Power amplifier modules with power amplifier and transmission line and related systems, devices, and methods

One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to amplify a radio frequency (RF) signal and an RF transmission line electrically coupled to an output of the power amplifier. The power amplifier includes a heterojunction bipolar transistor and a p-type field effect transistor, in which a semiconductor portion of the p-type field effect transistor corresponds to a channel includes the same type of semiconductor material as a collector layer of the heterojunction bipolar transistor. The RF transmission line includes a nickel layer with a thickness that is less than 0.5 um, a conductive layer under the nickel layer, a palladium layer over the nickel layer, and a gold layer over the palladium layer. Other embodiments of the module are provided along with related methods and components thereof.

Package-On-Package (PoP) Structure Including Stud Bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first surface of a first substrate;a second pad on a second surface of a second substrate;a metallic element interposed between the first pad and the second pad, the metallic element electrically coupled to the first pad, the metallic element comprising a base portion and an elongated portion extending from the base portion toward the second pad;a solder connector in contact with the elongated portion and electrically coupled to the second pad; andan inter-metallic compound (IMC) between the elongated portion and the solder connector.2. The device of claim 1 , further comprising a protection layer extending over the base portion and the elongated portion.3. The device of claim 1 , further comprising a die attached to the first substrate adjacent the metallic element.4. The device of claim 3 , wherein a height of the metallic element from the first substrate is greater than a height of the die from the first substrate.5. The device of claim 1 , wherein the metallic element comprises a copper wire.6. The device of claim 1 , wherein the base portion and the elongated portion comprises a single continuous element.7. A device comprising:a first substrate having a first pad;a second substrate having a second pad;a first connector interposed between the first pad and the second pad, the first connector having a first wide portion and a second elongated portion, the first wide portion being ...

Form the semiconductor devices and method of embedded SOP fan-out packages

本发明涉及形成嵌入式SoP扇出型封装的半导体器件和方法。一种半导体器件，包括球栅阵列（BGA）封装，球栅阵列（BGA）封装包括第一凸块。在第一凸块之间将第一半导体管芯安装至BGA封装。将BGA封装和第一半导体管芯安装至载体。将第一密封剂沉积在载体之上以及BGA封装和第一半导体管芯周围。移除载体，以暴露第一凸块和第一半导体管芯。将互连结构电连接至第一凸块和第一半导体管芯。BGA封装还包括衬底和第二半导体管芯，第二半导体管芯被安装且电连接至衬底。将第二密封剂沉积在第二半导体管芯和衬底之上。在衬底之上与第二半导体管芯相对地形成第一凸块。在BGA封装之上形成翘曲平衡层。

Electronic device having metallurgies containing copper-semiconductor compounds

본 발명의 실리콘 및 게르마늄 함유 재료는 전자 장치에서 도체의 표면에 사용된다. 본 발명에 의하면, 이들 표면에 땜납이 용제없이 접합될 수 있고 와이어가 와이어 접합될 수 있다. 이들 재료는 집적 회로 칩을 패키징하기 위한 리드프레임용 표면 피막으로 사용된다. 이들 재료는 도체 표면상으로 전사(傳寫)되거나, 무전해 또는 전기분해 증착될 수 있다. The silicon and germanium containing materials of the present invention are used on the surface of conductors in electronic devices. According to the present invention, solder can be bonded to these surfaces without solvent and wires can be wire bonded. These materials are used as surface coatings for leadframes for packaging integrated circuit chips. These materials may be transferred onto the conductor surface, or may be electrolessly or electrolytically deposited.

Power amplifier modules with bonding pads and related systems, devices, and methods

One aspect of this disclosure is a power amplifier module that includes a power amplifier die, a first bonding pad on a conductive trace, and a second bonding pad on a conductive trace. The die includes an on-die passive device and a power amplifier. The first bonding pad is electrically connected to the on-die passive device by a first wire bond. The second bonding pad is in a conductive path between the first bonding pad and a radio frequency output of the power amplifier module. The second bonding pad includes a nickel layer having a thickness that is less than 0.5 um, a palladium layer over the nickel layer, and a gold layer over the palladium layer and bonded to a second wire bond that is electrically connected to an output of the power amplifier. Other embodiments of the module are provided along with related methods and components thereof.

Semiconductor device and manufacturing method of semiconductor device

A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.

Power amplifier modules with bifet and harmonic termination and related systems, devices, and methods

본 기재의 일 특징은, 무선 주파수(RF) 신호를 증폭하도록 구성된 전력 증폭기를 포함하는 전력 증폭기 다이 - 전력 증폭기는 이종접합 쌍극성 트랜지스터(HBT) 및 p-타입 전계 효과 트랜지스터(PFET)를 포함하고, PFET 은 HBT의 콜렉터의 층과 실질적으로 동일한 재료를 포함하는 반도체 세그먼트를 포함하고, 반도체 세그먼트는 PFET의 채널에 대응함 - ; 전력 증폭기의 출력에 전기적으로 접속되고 RF 신호의 기본 주파수에서 임피던스 정합을 제공하도록 구성된 부하선; 및 전력 증폭기의 출력에 전기적으로 접속되고 RF 신호의 고조파 주파수에 대응하는 위상에서 종단하도록 구성된 고조파 종단 회로를 포함하는 전력 증폭기 모듈이다. 모듈의 다른 실시예들이 그의 관련된 방법들 및 컴포넌트들과 함께 제공된다.

Power amplifier modules including wire bond pad and related systems, devices, and methods

One aspect of this disclosure is a power amplifier module that includes a power amplifier; a wire bond pad electrically connected to the power amplifier, the wire bond pad including a nickel layer having a thickness that is less than 0.5 um, a palladium layer over the nickel layer, and a gold layer over the palladium layer; and a conductive trace having a top surface with a plated portion and an unplated portion surrounding the plated portion, the wire bond pad being disposed over the plated portion. Other embodiments of the module are provided along with related methods and components thereof.

Light emitting device and backlight unit

Disclosed are a light emitting device, a method of manufacturing the same, and a backlight unit. The light emitting device includes a body (10) including a cavity (15) to open an upper portion, in which the cavity has a sidewall (16) inclined at a first angle from a bottom surface of the cavity, first (31) and second (32) electrodes formed in the body, in which at least portions of the first and second electrodes are formed along the sidewall of the cavity, a light emitting chip over the first electrode, the second electrode, and the bottom surface of the cavity, at least one wire (40) having one end bonded to a top surface of the light emitting chip (20) and an opposite end bonded to a portion of the first and second electrodes over the sidewall of the cavity, and a molding member (50) formed in the cavity to seal the light emitting chip.

Light emitting device and backlight unit

Disclosed are a light emitting device, a method of manufacturing the same, and a backlight unit. The light emitting device includes a body (10) including a cavity (15) to open an upper portion, in which the cavity has a sidewall (16) inclined at a first angle from a bottom surface of the cavity, first (31) and second (32) electrodes formed in the body, in which at least portions of the first and second electrodes are formed along the sidewall of the cavity, a light emitting chip over the first electrode, the second electrode, and the bottom surface of the cavity, at least one wire (40) having one end bonded to a top surface of the light emitting chip (20) and an opposite end bonded to a portion of the first and second electrodes over the sidewall of the cavity, and a molding member (50) formed in the cavity to seal the light emitting chip.

Power amplifier systems with control interface and bias circuit

One aspect of this disclosure is a power amplifier system that includes a control interface, a power amplifier, a passive component, and a bias circuit. The power amplifier and the passive component can be on a first die. The bias circuit can be on a second die. The control interface can operate as a serial interface or as a general purpose input/output interface. The power amplifier can be controllable based at least partly on an output signal from the control interface. The bias circuit can generate a bias signal based at least partly on an indication of the electrical property of the passive component. Other embodiments of the system are provided along with related methods and components thereof.

Power amplifier modules including related systems and devices

Chip package and method of forming the same

本发明涉及芯片封装及形成芯片封装的方法。实施例提供了一种形成芯片封装的方法。方法可以包括：在载体上附着至少一个芯片，该芯片包括与载体相对的芯片表面上的多个芯片焊盘；在载体和芯片的芯片焊盘上沉积第一粘合层，第一粘合层包括锡或铟；在第一粘合层上沉积第二粘合层，第二粘合层包括硅烷有机材料；以及在第二粘合层和芯片上沉积层压层或密封层。

Package-on-package (PoP) structure and method

本发明涉及堆叠封装(PoP)的结构和形成PoP结构的方法。根据一个实施例，结构包括第一衬底、螺柱球、管芯、第二衬底和电连接件。螺柱球与第一衬底的第一表面相接合。管芯附接至第一衬底的第一表面。电连接件与第二衬底连接，以及对应的电连接件与对应的螺柱球相连。

Related systems, devices, and methods including power amplifier modules

Semiconductor devices and processing methods

Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed over at least part of at least one of the top side and the at least one sidewall of the final metal layer; wherein the passivation layer has a substantially uniform thickness.

Partially patterned lead frames and methods of making and using the same in semiconductor packaging

A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.

Multichip-Halbleitergehäuse und deren Zusammenbau

Halbleitergehäuse, umfassend:ein Substrat (10), das einen ersten (11) und einen zweiten (13) und einen dritten (12) Die-Attach-Pad umfasst, die getrennt voneinander angeordnet sind, wobei das dritte Die-Attach-Pad (12) ein inneres Die-Attach-Pad ist, das zwischen dem ersten Die-Attach-Pad (11) und dem zweiten Die-Attach-Pad (13) angeordnet ist;ein erstes Mikroplättchen (30) über dem ersten Die-Attach-Pad (11) angeordnet, wobei das erste Mikroplättchen (30) über einem ersten Teil des ersten Die-Attach-Pads (11) und über einem ersten Teil des dritten Die-Attach-Pads (12) angeordnet ist;ein zweites Mikroplättchen (30) über dem zweiten Die-Attach-Pad (13) angeordnet, wobei das zweite Mikroplättchen (30) über einem zweiten Teil des dritten Die-Attach-Pads (12) und über einem ersten Teil des zweiten Die-Attach-Pads (13) angeordnet ist;ein drittes Mikroplättchen (50) zwischen dem ersten (30) und dem zweiten (30) Mikroplättchen angeordnet, einen ersten Teil des dritten Mikroplättchens (50) über einem ersten Teil des ersten Mikroplättchens (30) angeordnet, einen zweiten Teil des dritten Mikroplättchens (50) über einem ersten Teil des zweiten Mikroplättchens (30) angeordnet, und einen dritten Teil des dritten Mikroplättchens (50) über einem ersten Bereich zwischen dem ersten Mikroplättchen (30) und dem zweiten Mikroplättchen (30) angeordnet.

Nitride semiconductor device

A nitride semiconductor device includes first electrode interconnect layers and second electrode interconnect layers formed over a nitride semiconductor layer, a first insulating film formed on the first and second electrode interconnect layers and including first openings, first interconnect layers and second interconnect layers formed on the first insulating film and respectively connected to the first electrode interconnect layers and the second electrode interconnection layers through the first openings, a second insulating film formed on the first and second interconnect layers and including second openings, and a first pad layer and a second pad layer formed on the second insulating film and respectively connected to the first interconnect layers and the second interconnect layers through the second openings.

窒化物半導体装置

窒化物半導体装置は、窒化物半導体層の上に形成された第１の電極配線層及び第２の電極配線層と、第１の電極配線層及び第２の電極配線層の上に形成され、第１の開口部を有する第１の絶縁膜と、第１の絶縁膜の上に形成され、第１の開口部を介して第１の電極配線層及び第２の電極配線層と各々接続する第１の配線層(17a)及び第２の配線層(17b)と、第１の配線層及び第２の配線層の上に形成され、第２の開口部を有する第２の絶縁膜(18)と、第２の絶縁膜の上に形成され、第２の開口部を介して第１の配線層及び第２の配線層と各々接続する第１のパッド層(22a)及び第２のパッド層(22b)とを備えている。

氮化物半导体装置

本发明的氮化物半导体装置具备：在氮化物半导体层之上形成的第1电极布线层以及第2电极布线层、在第1电极布线层以及第2电极布线层之上形成且具有第1开口部的第1绝缘膜、在第1绝缘膜之上形成且经由第1开口部而与第1电极布线层以及第2电极布线层分别连接的第1布线层(17a)以及第2布线层(17b)、在第1布线层以及第2布线层之上形成且具有第2开口部的第2绝缘膜(18)、和在第2绝缘膜之上形成且经由第2开口部而与第1布线层以及第2布线层分别连接的第1焊盘层(22a)以及第2焊盘层(22b)。

Verfahren zum aufbringen eines si oder ge enthaltenden materials auf eine oberfläche aus cu oder ni

Solderability improvement method for leaded semiconductor package

A microelectronic device package (100) that includes a microelectronic device (106) encapsulated within a packaging material (102). The microelectronic device package also includes a lead (104) attached to a portion of the microelectronic device extending through the packaging material. The lead has a break portion and a non-break portion on a tip of the lead.

Halbleitervorrichtungen und Halbleiterverarbeitungsverfahren

Halbleitervorrichtung (310), die Folgendes aufweist:eine letzte Metallschicht (312), die eine Oberseite (328) und wenigstens eine Seitenwand (332) enthält;eine mittels eines Atomlagenabscheidungsprozesses gebildete erste Passivierungsschicht (313), die wenigstens über einem Teil der Oberseite (328) und/oder der wenigstens einen Seitenwand (332) der letzten Metallschicht (312) angeordnet ist;eine zweite Passivierungsschicht (322), die die erste Passivierungsschicht (313) wenigstens teilweise umgibt;ein Loch (638) zum Kontaktieren der letzten Metallschicht (312) durch die zweite Passivierungsschicht (322) aber nicht durch die erste Passivierungsschicht (313), so dass die Oberfläche der ersten Passivierungsschicht (313) teilweise offen liegt;wobei die erste Passivierungsschicht (313) eine im Wesentlichen gleichmäßige Dicke besitzt und die Dicke kleiner oder gleich 100 nm aufweist, undwobei die letzte Metallschicht (312) eine Metall-Kontaktanschlussfläche aufweist.

Solderability improvement method for leaded semiconductor package

Solderability improvement method for leaded semiconductor package

A microelectronic device package (100) that includes a microelectronic device (106) encapsulated within a packaging material (102). The microelectronic device package also includes a lead (104) attached to a portion of the microelectronic device extending through the packaging material. The lead has a break portion and a non-break portion on a tip of the lead.

Partially patterned lead frames and methods of making and using the same in semiconductor packaging

A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.

芯片封装和用于制作芯片封装的方法

芯片封装和用于制作芯片封装的方法。提供一种芯片封装，所述芯片封装包括：包括至少一个腔体的载体；至少部分地设置在至少一个腔体内的芯片；设置在芯片的至少一个侧壁上的至少一个中间层；其中至少一个中间层被配置为将来自芯片的热量热传导到载体。

Power amplifier modules with bifet and harmonic termination and related systems, devices, and methods

One aspect of this disclosure is a power amplifier module that includes a power amplifier die including a power amplifier configured to amplify a radio frequency (RF) signal, the power amplifier including a heterojunction bipolar transistor (HBT) and a p-type field effect transistor (PFET), the PFET including a semiconductor segment that includes substantially the same material as a layer of a collector of the HBT, the semiconductor segment corresponding to a channel of the PFET; a load line electrically connected to an output of the power amplifier and configured to provide impedance matching at a fundamental frequency of the RF signal; and a harmonic termination circuit electrically connected to the output of the power amplifier and configured to terminate at a phase corresponding to a harmonic frequency of the RF signal. Other embodiments of the module are provided along with related methods and components thereof.

Integrated circuit assembly and method of making

A first wafer is provided that includes an insulating layer, a first active layer, and a handle layer. The insulating layer has a first surface and a second surface. The first active layer contacts the first surface of the insulating layer. The handle layer contacts the second surface of the insulating layer. A second wafer is provided that includes a substrate and a second active layer. The substrate has a first surface and a second surface. The second active layer contacts the first surface of the substrate. The second wafer is bonded to the first wafer by physically connecting the first active layer to the second surface of the substrate. The handle layer is removed. A metal bond pad is formed on the second surface of the insulating layer. The metal bond pad is electrically connected to the first active layer.