SEMICONDUCTOR DEVICE AND METHOD OF FORMING SUPPORTING LAYER OVERSEMICONDUCTOR DIE IN THIN FAN-OUTWAFER LEVEL CHIP SCALE PACKAGE

Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded wlcsp

Semiconductor device and method of forming an embedded sop fan-out package

Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.

Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers

A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.

Semiconductor device having wire studs as vertical interconnect in FO-WLP

A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate.

Sеmiсоnduсtоr dеviсе аnd mеthоd оf fоrming а vеrtiсаl intеrсоnnесt struсturе fоr 3-D FО-WLСSР

А sеmiсоnduсtоr dеviсе is mаdе bу fоrming а first соnduсtivе lауеr оvеr а саrriеr. Тhе first соnduсtivе lауеr hаs а first аrеа еlесtriсаllу isоlаtеd frоm а sесоnd аrеа оf thе first соnduсtivе lауеr. А соnduсtivе pillаr is fоrmеd оvеr thе first аrеа оf thе first соnduсtivе lауеr. А sеmiсоnduсtоr diе оr соmpоnеnt is mоuntеd tо thе sесоnd аrеа оf thе first соnduсtivе lауеr. А first еnсаpsulаnt is dеpоsitеd оvеr thе sеmiсоnduсtоr diе аnd аrоund thе соnduсtivе pillаr. А first intеrсоnnесt struсturе is fоrmеd оvеr thе first еnсаpsulаnt. Тhе first intеrсоnnесt struсturе is еlесtriсаllу соnnесtеd tо thе соnduсtivе pillаr. Тhе саrriеr is rеmоvеd. А pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd. Тhе rеmаining pоrtiоn оf thе first соnduсtivе lауеr inсludеs аn intеrсоnnесt linе аnd UВМ pаd. А sесоnd intеrсоnnесt struсturе is fоrmеd оvеr а rеmаining pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd.

Sеmiсоnduсtоr dеviсе аnd mеthоd оf fоrming а vеrtiсаl intеrсоnnесt struсturе fоr 3-D FО-WLСSР

А sеmiсоnduсtоr dеviсе is mаdе bу fоrming а first соnduсtivе lауеr оvеr а саrriеr. Тhе first соnduсtivе lауеr hаs а first аrеа еlесtriсаllу isоlаtеd frоm а sесоnd аrеа оf thе first соnduсtivе lауеr. А соnduсtivе pillаr is fоrmеd оvеr thе first аrеа оf thе first соnduсtivе lауеr. А sеmiсоnduсtоr diе оr соmpоnеnt is mоuntеd tо thе sесоnd аrеа оf thе first соnduсtivе lауеr. А first еnсаpsulаnt is dеpоsitеd оvеr thе sеmiсоnduсtоr diе аnd аrоund thе соnduсtivе pillаr. А first intеrсоnnесt struсturе is fоrmеd оvеr thе first еnсаpsulаnt. Тhе first intеrсоnnесt struсturе is еlесtriсаllу соnnесtеd tо thе соnduсtivе pillаr. Тhе саrriеr is rеmоvеd. А pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd. Тhе rеmаining pоrtiоn оf thе first соnduсtivе lауеr inсludеs аn intеrсоnnесt linе аnd UВМ pаd. А sесоnd intеrсоnnесt struсturе is fоrmеd оvеr а rеmаining pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE STRUCTURE AROUND SEMICONDUCTOR DIE FOR LOCALIZED PLANARIZATION OF INSULATING LAYER

Abstract SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE STRUCTURE AROUND SEMICONDUCTOR DIE FOR LOCALIZED PLANARIZATION OF INSULATING LAYERA semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed ...

SEMICONDUCTOR DEVICE AND METHOD OF FORMING DUAL-SIDEDINTERCONNECT STRUCTURES IN FO-WLCSP

SEMICONDUCTOR DEVICE AND METHOD OF FORMING EMBEDDED CONDUCTIVE LAYER FOR POWER/GROUND PLANES IN FO-EWLB

Semiconductor device and method of forming conductive vias through interconnect structures and encapsulant of wlcsp

Semiconductor device and method of forming sacrifical protective layer to protect semiconductor die edge during singulation

Semiconductor device and method of controlling warpage in reconstituted wafer

A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality of semiconductor die is disposed over a portion of the substrate while leaving an open area of the substrate devoid of the semiconductor die. The open area of the substrate devoid of the semiconductor die includes a central area or interstitial locations among the semiconductor die. The semiconductor die are disposed around a perimeter of the substrate. An encapsulant is deposited over the semiconductor die and substrate. The substrate is removed and an interconnect structure is formed over the semiconductor die. By leaving the predetermined areas of the substrate devoid of semiconductor die, the warping effect of any mismatch between the CTE of the semiconductor die and the CTE of the encapsulant on the reconstituted wafer after removal of the substrate is reduced.

Method of forming stress relief layer between die and interconnect structure

A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.

Semiconductor Device and Method of Providing Electrostatic Discharge Protection for Integrated Passive Devices

A semiconductor device has an integrated passive device (IPD) formed on a substrate. The IPD can be a metal-insulator-metal capacitor or an inductor formed as a coiled conductive layer. A signal interconnect structure is formed on the front side or backside of the substrate. The signal interconnect structure is electrically connected to the IPD. A thin film ZnO layer is formed on the substrate as a part of an electrostatic discharge (ESD) protection structure. The thin film ZnO layer has a non-linear resistance as a function of a voltage applied to the layer. A conductive layer is formed on the substrate. The thin film ZnO layer is electrically connected between the signal interconnect structure and conductive layer to provide an ESD path to protect the IPD from an ESD transient. A ground interconnect structure is formed on the substrate and electrically connects the conductive layer to a ground point.

Semiconductor Device and Method of Forming RDL over Contact Pad with High Alignment Tolerance or Reduced Interconnect Pitch

A semiconductor device has a semiconductor die with an active surface. A first conductive layer is formed over the active surface. A first insulating layer is formed over the active surface. A second insulating layer is formed over the first insulating layer and first conductive layer. A portion of the second insulating layer is removed over the first conductive layer so that no portion of the second insulating layer overlies the first conductive layer. A second conductive layer is formed over the first conductive layer and first and second insulating layers. The second conductive layer extends over the first conductive layer up to the first insulating layer. Alternatively, the second conductive layer extends across the first conductive layer up to the first insulating layer on opposite sides of the first conductive layer. A third insulating layer is formed over the second conductive layer and first and second insulating layers.

Semiconductor device and method of placing semiconductor die on a temporary carrier using fiducial patterns

A semiconductor device has an adhesive layer depositing over a temporary carrier. A plurality of fiduciary patterns is formed over the adhesive layer. A repassivation layer is formed over semiconductor die. The repassivation layer may be a plurality of discrete regions. Alignment slots are formed in the repassivation layer. The fiducial patterns and alignment slots have slanted sidewalls. Leading with the repassivation layer, the semiconductor die is placed onto the carrier so that the alignment slots envelope and lock to the fiducial patterns. Alternatively, a die without the repassivation layer is placed between the fiducial patterns. An encapsulant is deposited over the semiconductor die while the die remain locked to the fiducial patterns. The carrier, adhesive layer, and fiducial patterns are removed after depositing the encapsulant. An interconnect structure is formed over the repassivation layer to electrically connect to contact pads on the semiconductor die.

Integrated circuit package system with post-passivation interconnection and integration

An integrated circuit package system including: providing an integrated circuit die, forming a first layer over the integrated circuit die, forming a bridge on and in the first layer, forming a second layer on the first layer, and forming bump pads on and in the second layer, the bump pads connected to ends of the bridge.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING BUILD-UP INTERCONNECTSTRUCTURES OVER CARRIER FOR TESTING AT INTERIM STAGES

SEMICONDUCTOR METHOD AND DEVICE OF FORMING A FAN-OUTPOP DEVICE WITH PWB VERTICAL INTERCONNECT UNITS

Semiconductor device and method of forming embedded conductive layer for power/ground planes in fo-ewlb

SEMICONDUCTOR DEVICE AND METHOD OFCONTROLLING WARPAGE IN RECONSTITUTED WAFER

Integrated circuit system for bonding

An integrated circuit system provides a precursor for an integrated wire bond and flip chip structure. The precursor has a plurality of contact pads thereon. A layer of titanium is deposited on the precursor. A layer of nickel-vanadium is deposited on the layer of titanium. A layer of copper is deposited on the layer of nickel-vanadium. A mask is formed on at least a portion of the layer of copper. Portions of the layers of copper and nickel-vanadium not protected by the mask are removed to expose portions of the layer of titanium. The exposed portions of the layer of titanium are etched with an etching solution consisting of an etchant, a viscosity modifier, and an oxidizer.

Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors

A semiconductor device is made by forming a plurality of conductive pillars vertically over a temporary carrier. A conformal insulating layer is formed over the conductive pillars. A conformal conductive layer is formed over the conformal insulating layer. A first conductive pillar, conformal insulating layer, and conformal conductive layer constitute a vertically oriented integrated capacitor. A semiconductor die or component is mounted over the carrier. An encapsulant is deposited over the semiconductor die or component and around the conformal conductive layer. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure includes an integrated passive device. The first interconnect structure is electrically connected to the semiconductor die or component and vertically oriented integrated capacitor. The carrier is removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first side of the encapsulant ...

Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During Singulation

A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant. 1. A semiconductor device , comprising:a semiconductor wafer including a plurality of semiconductor die separated by a saw street;a first insulating layer including a non-planar surface formed over the semiconductor wafer;a protective layer including a planar surface formed over the first insulating layer; andan encapsulant deposited over the semiconductor die.2. The semiconductor device of claim 1 , further including a trench formed in the protective layer over the saw street.3. The semiconductor device of claim 2 , further including a conductive layer formed over the trench between adjacent semiconductor die.4. The semiconductor device of claim 1 , further including a trench comprising a plurality of notches formed in the protective layer over the saw street.5. The semiconductor device of claim 1 , wherein the encapsulant is planarized with a surface of the semiconductor die.6. The semiconductor device of claim 1 , further including an interconnect structure formed over the semiconductor die and encapsulant.7. A ...

Semiconductor device and method of forming thermally conductive layer between semiconductor die and build-up interconnect structure

A semiconductor device has a thermally conductive layer with a plurality of openings formed over a temporary carrier. The thermally conductive layer includes electrically non-conductive material. A semiconductor die has a plurality of bumps formed over contact pads on the die. The semiconductor die is mounted over the thermally conductive layer so that the bumps are disposed at least partially within the openings in the thermally conductive layer. An encapsulant is deposited over the die and thermally conductive layer. The temporary carrier is removed to expose the bumps. A first interconnect structure is formed over the encapsulant, semiconductor die, and bumps. The bumps are electrically connected to the first interconnect structure. A heat sink or shielding layer can be formed over the semiconductor die. A second interconnect structure can be formed over the encapsulant and electrically connected to the first interconnect structure through conductive vias formed in the encapsulant.

Semiconductor device and method of forming protection and support structure for conductive interconnect structure

A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

Encapsulant interposer system with integrated passive devices and manufacturing method therefor

A method of manufacturing a semiconductor package system including: forming a leadframe having a passive device; encapsulating the passive device to form an encapsulant interposer; attaching a first die to the encapsulant interposer; forming a substrate interposer having a second die; and stacking the encapsulant interposer over the substrate interposer.

Sеmiсоnduсtоr dеviсе аnd mеthоd оf fоrming а vеrtiсаl intеrсоnnесt struсturе fоr 3-D FО-WLСSР

А sеmiсоnduсtоr dеviсе is mаdе bу fоrming а first соnduсtivе lауеr оvеr а саrriеr. Тhе first соnduсtivе lауеr hаs а first аrеа еlесtriсаllу isоlаtеd frоm а sесоnd аrеа оf thе first соnduсtivе lауеr. А соnduсtivе pillаr is fоrmеd оvеr thе first аrеа оf thе first соnduсtivе lауеr. А sеmiсоnduсtоr diе оr соmpоnеnt is mоuntеd tо thе sесоnd аrеа оf thе first соnduсtivе lауеr. А first еnсаpsulаnt is dеpоsitеd оvеr thе sеmiсоnduсtоr diе аnd аrоund thе соnduсtivе pillаr. А first intеrсоnnесt struсturе is fоrmеd оvеr thе first еnсаpsulаnt. Тhе first intеrсоnnесt struсturе is еlесtriсаllу соnnесtеd tо thе соnduсtivе pillаr. Тhе саrriеr is rеmоvеd. А pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd. Тhе rеmаining pоrtiоn оf thе first соnduсtivе lауеr inсludеs аn intеrсоnnесt linе аnd UВМ pаd. А sесоnd intеrсоnnесt struсturе is fоrmеd оvеr а rеmаining pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING ENCAPSULATED WAFER LEVEL CHIP SCALE PACKAGE (EWLCSP)

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SEMICONDUCTOR PACKAGE HAVING BUILD-UP INTERCONNECT STRUCTURE OVER SEMICONDUCTOR DIE WITH DIFFERENT CTE INSULATING LAYERS

Abstract SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SEMICONDUCTORPACKAGE HAVING BUILDUP INTERCONNECT STRUCTURE OVER SEMICONDUCTOR DIE WITH DIFFERENT CTE INSULATING LAYERSA semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different ...

Semiconductor device and method of forming embedded conductive layer for power/ground planes in fo-ewlb

Semiconductor Device and Method of Forming Conductive Vias Through Interconnect Structures and Encapsulant of WLCSP

A semiconductor device has a semiconductor die mounted over the carrier. An encapsulant is deposited over the carrier and semiconductor die. The carrier is removed. A first interconnect structure is formed over the encapsulant and a first surface of the die. A second interconnect structure is formed over the encapsulant and a second surface of the die. A first protective layer is formed over the first interconnect structure and second protective layer is formed over the second interconnect structure prior to forming the vias. A plurality of vias is formed through the second interconnect structure, encapsulant, and first interconnect structure. A first conductive layer is formed in the vias to electrically connect the first interconnect structure and second interconnect structure. An insulating layer is formed over the first interconnect structure and second interconnect structure and into the vias. A discrete semiconductor component can be mounted to the first interconnect structure.

Semiconductor device having electrical devices mounted to IPD structure and method of shielding electromagnetic interference

A semiconductor device has an IPD structure formed over a substrate. First and second electrical devices are mounted to a first surface of the IPD structure. An encapsulant is deposited over the first and second electrical devices and IPD structure. A shielding layer is formed over the encapsulant and electrically connected to a conductive channel in the IPD structure. The conductive channel is connected to ground potential to isolate the first and second electrical devices from external interference. A recess can be formed in the encapsulant material between the first and second electrical devices. The shielding layer extends into the recess. An interconnect structure is formed on a second surface of the IPD structure. The interconnect structure is electrically connected to the first and second electrical devices and IPD structure. A shielding cage can be formed over the first electrical device prior to depositing encapsulant.

Semiconductor Device and Method of Forming UBM Fixed Relative to Interconnect Structure for Alignment of Semiconductor Die

A semiconductor device is made by forming a first conductive layer over a temporary carrier. A UBM layer is formed over the temporary carrier and fixed in position relative to the first conductive layer. A conductive pillar is formed over the first conductive layer. A semiconductor die is mounted to the UBM layer to align the die relative to the conductive pillar. An encapsulant is deposited over the die and around the conductive pillar. The UBM layer prevents shifting of the semiconductor die while depositing the encapsulant. The temporary carrier is removed. A first interconnect structure is formed over a first surface of the encapsulant. A second interconnect structure is formed over a second surface of the encapsulant. The first and second interconnect structures are electrically connected through the conductive pillar. The first or second interconnect structure includes an integrated passive device electrically connected to the conductive pillar.

Semiconductor device and method of making embedded wafer level chip scale packages

A semiconductor device includes a carrier and a plurality of semiconductor die disposed over the carrier. An encapsulant is deposited over the semiconductor die. A composite layer is formed over the encapsulant to form a panel. The carrier is removed. A conductive layer is formed over the panel. An insulating layer is formed over the conductive layer. The carrier includes a glass layer, a second composite layer formed over the glass layer, and an interface layer formed over the glass layer. The composite layer and encapsulant are selected to tune a coefficient of thermal expansion of the panel. The panel includes panel blocks comprising an opening separating the panel blocks. The encapsulant or insulating material is deposited in the opening. A plurality of support members are disposed around the panel blocks. An interconnect structure is formed over the conductive layer.

Semiconductor Device and Method of Forming Repassivation Layer with Reduced Opening to Contact Pad of Semiconductor Die

A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer.

Semiconductor device and method of forming no-flow underfill material around vertical interconnect structure

Semiconductor device and method of forming insulating layer around semiconductor die

A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.

Semiconductor device and method of forming embedded conductive layer for power/ground planes in Fo-eWLB

A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to VSS and forms a ground plane. A second portion of the first conductive layer is electrically connected to VDD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.

Semiconductor device and method of forming low profile fan-out package with vertical interconnection units

A semiconductor device includes a semiconductor die. A first interconnect structure is disposed over a peripheral region of the semiconductor die. A semiconductor component is disposed over the semiconductor die. The semiconductor component includes a second interconnect structure. The semiconductor component is disposed over the semiconductor die to align the second interconnect structure with the first interconnect structure. The first interconnect structure includes a plurality of interconnection units disposed around first and second adjacent sides of the semiconductor die to form an L-shape border of the interconnection units around the semiconductor die. A third interconnect structure is formed over the semiconductor die perpendicular to the first interconnect structure. An insulating layer is formed over the semiconductor die and first interconnect structure. A plurality of vias is formed through the insulating layer and into the first interconnect structure with the second interconnect ...

Semiconductor Device and Method of Forming Sacrificial Adhesive Over Contact Pads of Semiconductor Die

A semiconductor wafer contains a plurality of semiconductor die each having a plurality of contact pads. A sacrificial adhesive is deposited over the contact pads. Alternatively, the sacrificial adhesive is deposited over the carrier. An underfill material can be formed between the contact pads. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier such that the sacrificial adhesive is disposed between the contact pads and temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and sacrificial adhesive is removed to leave a via over the contact pads. An interconnect structure is formed over the encapsulant. The interconnect structure includes a conductive layer which extends into the via for electrical connection to the contact pads. The semiconductor die is offset from the interconnect structure by a height of the sacrificial adhesive.

Sеmiсоnduсtоr dеviсе аnd mеthоd оf fоrming а vеrtiсаl intеrсоnnесt struсturе fоr 3-D FО-WLСSР

А sеmiсоnduсtоr dеviсе is mаdе bу fоrming а first соnduсtivе lауеr оvеr а саrriеr. Тhе first соnduсtivе lауеr hаs а first аrеа еlесtriсаllу isоlаtеd frоm а sесоnd аrеа оf thе first соnduсtivе lауеr. А соnduсtivе pillаr is fоrmеd оvеr thе first аrеа оf thе first соnduсtivе lауеr. А sеmiсоnduсtоr diе оr соmpоnеnt is mоuntеd tо thе sесоnd аrеа оf thе first соnduсtivе lауеr. А first еnсаpsulаnt is dеpоsitеd оvеr thе sеmiсоnduсtоr diе аnd аrоund thе соnduсtivе pillаr. А first intеrсоnnесt struсturе is fоrmеd оvеr thе first еnсаpsulаnt. Тhе first intеrсоnnесt struсturе is еlесtriсаllу соnnесtеd tо thе соnduсtivе pillаr. Тhе саrriеr is rеmоvеd. А pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd. Тhе rеmаining pоrtiоn оf thе first соnduсtivе lауеr inсludеs аn intеrсоnnесt linе аnd UВМ pаd. А sесоnd intеrсоnnесt struсturе is fоrmеd оvеr а rеmаining pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd.

Sеmiсоnduсtоr dеviсе аnd mеthоd оf fоrming а vеrtiсаl intеrсоnnесt struсturе fоr 3-D FО-WLСSР

А sеmiсоnduсtоr dеviсе is mаdе bу fоrming а first соnduсtivе lауеr оvеr а саrriеr. Тhе first соnduсtivе lауеr hаs а first аrеа еlесtriсаllу isоlаtеd frоm а sесоnd аrеа оf thе first соnduсtivе lауеr. А соnduсtivе pillаr is fоrmеd оvеr thе first аrеа оf thе first соnduсtivе lауеr. А sеmiсоnduсtоr diе оr соmpоnеnt is mоuntеd tо thе sесоnd аrеа оf thе first соnduсtivе lауеr. А first еnсаpsulаnt is dеpоsitеd оvеr thе sеmiсоnduсtоr diе аnd аrоund thе соnduсtivе pillаr. А first intеrсоnnесt struсturе is fоrmеd оvеr thе first еnсаpsulаnt. Тhе first intеrсоnnесt struсturе is еlесtriсаllу соnnесtеd tо thе соnduсtivе pillаr. Тhе саrriеr is rеmоvеd. А pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd. Тhе rеmаining pоrtiоn оf thе first соnduсtivе lауеr inсludеs аn intеrсоnnесt linе аnd UВМ pаd. А sесоnd intеrсоnnесt struсturе is fоrmеd оvеr а rеmаining pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd.

Sеmiсоnduсtоr dеviсе аnd mеthоd оf fоrming а vеrtiсаl intеrсоnnесt struсturе fоr 3-D FО-WLСSР

А sеmiсоnduсtоr dеviсе is mаdе bу fоrming а first соnduсtivе lауеr оvеr а саrriеr. Тhе first соnduсtivе lауеr hаs а first аrеа еlесtriсаllу isоlаtеd frоm а sесоnd аrеа оf thе first соnduсtivе lауеr. А соnduсtivе pillаr is fоrmеd оvеr thе first аrеа оf thе first соnduсtivе lауеr. А sеmiсоnduсtоr diе оr соmpоnеnt is mоuntеd tо thе sесоnd аrеа оf thе first соnduсtivе lауеr. А first еnсаpsulаnt is dеpоsitеd оvеr thе sеmiсоnduсtоr diе аnd аrоund thе соnduсtivе pillаr. А first intеrсоnnесt struсturе is fоrmеd оvеr thе first еnсаpsulаnt. Тhе first intеrсоnnесt struсturе is еlесtriсаllу соnnесtеd tо thе соnduсtivе pillаr. Тhе саrriеr is rеmоvеd. А pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd. Тhе rеmаining pоrtiоn оf thе first соnduсtivе lауеr inсludеs аn intеrсоnnесt linе аnd UВМ pаd. А sесоnd intеrсоnnесt struсturе is fоrmеd оvеr а rеmаining pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd.

SEMICONDUCTOR DEVICE AND METHOD OF FORMINGCAVITY IN PCB CONTAINING ENCAPSULANT OR DUMMY DIEHAVING CTE SIMILAR TO CTE OF LARGE ARRAY WLCSP

Abstract SEMICONDUCTOR DEVICE AND METHOD OF FORMING CAVITY IN PCB CONTAINING ENCAPSULANT OR DUMMY DIE HAVING CTE SIMILAR TO CTE OF LARGE ARRAY WLCSPA semiconductor device has a PCB with a cavity formed in a first surface of the PCB. A stress compensating structure, such as an encapsulant or dummy die, is disposed in the cavity. An insulating layer is formed over the PCB and stress compensating structure. A portion of the insulating layer is removed to expose the stress compensating structure. A conductive layer is formed over the stress compensating structure. A solder masking layer is formed over the conductive layer with openings to the conductive layer. A semiconductor package is mounted over the cavity. The semiconductor package is a large array WLCSP.Bumps electrically connect the semiconductor package and conductive layer. The semiconductor package is electrically connected to the conductive layer. The CTE of the stress compensating structure is selected substantially similar to or ...

Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package

A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer an includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers ( m). The thickness of the semiconductor die is at least 1 m less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer.

Semiconductor Device and Method of Forming Supporting Layer Over Semiconductor Die in Thin Fan-Out Wafer Level Chip Scale Package

A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer and includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers (μm). The thickness of the semiconductor die is at least 1 μm less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer.

Semiconductor Device and Method of Forming Bump Structure with Multi-Layer UBM Around Bump Formation Area

A semiconductor wafer has a first conductive layer formed over its active surface. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A UBM layer is formed around a bump formation area over the second conductive layer. The UBM layer can be two stacked metal layers or three stacked metal layers. The second conductive layer is exposed in the bump formation area. A second insulating layer is formed over the UBM layer and second conductive layer. A portion of the second insulating layer is removed over the bump formation area and a portion of the UBM layer. A bump is formed over the second conductive layer in the bump formation area. The bump contacts the UBM layer to seal a contact interface between the bump and second conductive layer.

Semiconductor device and method of forming RDL over contact pad with high alignment tolerance or reduced interconnect pitch

A semiconductor device has a semiconductor die with an active surface. A first conductive layer is formed over the active surface. A first insulating layer is formed over the active surface. A second insulating layer is formed over the first insulating layer and first conductive layer. A portion of the second insulating layer is removed over the first conductive layer so that no portion of the second insulating layer overlies the first conductive layer. A second conductive layer is formed over the first conductive layer and first and second insulating layers. The second conductive layer extends over the first conductive layer up to the first insulating layer. Alternatively, the second conductive layer extends across the first conductive layer up to the first insulating layer on opposite sides of the first conductive layer. A third insulating layer is formed over the second conductive layer and first and second insulating layers.

Sеmiсоnduсtоr dеviсе аnd mеthоd оf fоrming а vеrtiсаl intеrсоnnесt struсturе fоr 3-D FО-WLСSР

А sеmiсоnduсtоr dеviсе is mаdе bу fоrming а first соnduсtivе lауеr оvеr а саrriеr. Тhе first соnduсtivе lауеr hаs а first аrеа еlесtriсаllу isоlаtеd frоm а sесоnd аrеа оf thе first соnduсtivе lауеr. А соnduсtivе pillаr is fоrmеd оvеr thе first аrеа оf thе first соnduсtivе lауеr. А sеmiсоnduсtоr diе оr соmpоnеnt is mоuntеd tо thе sесоnd аrеа оf thе first соnduсtivе lауеr. А first еnсаpsulаnt is dеpоsitеd оvеr thе sеmiсоnduсtоr diе аnd аrоund thе соnduсtivе pillаr. А first intеrсоnnесt struсturе is fоrmеd оvеr thе first еnсаpsulаnt. Тhе first intеrсоnnесt struсturе is еlесtriсаllу соnnесtеd tо thе соnduсtivе pillаr. Тhе саrriеr is rеmоvеd. А pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd. Тhе rеmаining pоrtiоn оf thе first соnduсtivе lауеr inсludеs аn intеrсоnnесt linе аnd UВМ pаd. А sесоnd intеrсоnnесt struсturе is fоrmеd оvеr а rеmаining pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd.

Sеmiсоnduсtоr dеviсе аnd mеthоd оf fоrming а vеrtiсаl intеrсоnnесt struсturе fоr 3-D FО-WLСSР

А sеmiсоnduсtоr dеviсе is mаdе bу fоrming а first соnduсtivе lауеr оvеr а саrriеr. Тhе first соnduсtivе lауеr hаs а first аrеа еlесtriсаllу isоlаtеd frоm а sесоnd аrеа оf thе first соnduсtivе lауеr. А соnduсtivе pillаr is fоrmеd оvеr thе first аrеа оf thе first соnduсtivе lауеr. А sеmiсоnduсtоr diе оr соmpоnеnt is mоuntеd tо thе sесоnd аrеа оf thе first соnduсtivе lауеr. А first еnсаpsulаnt is dеpоsitеd оvеr thе sеmiсоnduсtоr diе аnd аrоund thе соnduсtivе pillаr. А first intеrсоnnесt struсturе is fоrmеd оvеr thе first еnсаpsulаnt. Тhе first intеrсоnnесt struсturе is еlесtriсаllу соnnесtеd tо thе соnduсtivе pillаr. Тhе саrriеr is rеmоvеd. А pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd. Тhе rеmаining pоrtiоn оf thе first соnduсtivе lауеr inсludеs аn intеrсоnnесt linе аnd UВМ pаd. А sесоnd intеrсоnnесt struсturе is fоrmеd оvеr а rеmаining pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd.

Sеmiсоnduсtоr dеviсе аnd mеthоd оf fоrming а vеrtiсаl intеrсоnnесt struсturе fоr 3-D FО-WLСSР

А sеmiсоnduсtоr dеviсе is mаdе bу fоrming а first соnduсtivе lауеr оvеr а саrriеr. Тhе first соnduсtivе lауеr hаs а first аrеа еlесtriсаllу isоlаtеd frоm а sесоnd аrеа оf thе first соnduсtivе lауеr. А соnduсtivе pillаr is fоrmеd оvеr thе first аrеа оf thе first соnduсtivе lауеr. А sеmiсоnduсtоr diе оr соmpоnеnt is mоuntеd tо thе sесоnd аrеа оf thе first соnduсtivе lауеr. А first еnсаpsulаnt is dеpоsitеd оvеr thе sеmiсоnduсtоr diе аnd аrоund thе соnduсtivе pillаr. А first intеrсоnnесt struсturе is fоrmеd оvеr thе first еnсаpsulаnt. Тhе first intеrсоnnесt struсturе is еlесtriсаllу соnnесtеd tо thе соnduсtivе pillаr. Тhе саrriеr is rеmоvеd. А pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd. Тhе rеmаining pоrtiоn оf thе first соnduсtivе lауеr inсludеs аn intеrсоnnесt linе аnd UВМ pаd. А sесоnd intеrсоnnесt struсturе is fоrmеd оvеr а rеmаining pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd.

Semiconductor Device and Method of Forming FO-WLCSP with Discrete Semiconductor Components Mounted Under and Over Semiconductor Die

A semiconductor die has first and second discrete semiconductor components mounted over a plurality of wettable contact pads formed on a carrier. Conductive pillars are formed over the wettable contact pads. A semiconductor die is mounted to the conductive pillars over the first discrete components. The conductive pillars provide vertical stand-off of the semiconductor die as headroom for the first discrete components. The second discrete components are disposed outside a footprint of the semiconductor die. Conductive TSV can be formed through the semiconductor die. An encapsulant is deposited over the semiconductor die and first and second discrete components. The wettable contact pads reduce die and discrete component shifting during encapsulation. A portion of a back surface of the semiconductor die is removed to reduce package thickness. An interconnect structure is formed over the encapsulant and semiconductor die. Third discrete semiconductor components can be mounted over the semiconductor ...

Semiconductor Device and Method of Forming Compliant Stress Relief Buffer Around Large Array WLCSP

A semiconductor device has a stress relief buffer mounted to a temporary substrate in locations designated for bump formation. The stress relief buffer can be a multi-layer composite material such as a first compliant layer, a silicon layer formed over the first compliant layer, and a second compliant layer formed over the silicon layer. A semiconductor die is also mounted to the temporary substrate. The stress relief buffer can be thinner than the semiconductor die. An encapsulant is deposited between the semiconductor die and stress relief buffer. The temporary substrate is removed. An interconnect structure is formed over the semiconductor die, encapsulant, and stress relief buffer. The interconnect structure is electrically connected to the semiconductor die. A stiffener layer can be formed over the stress relief buffer and encapsulant. A circuit layer containing active devices, passive devices, conductive layers, and dielectric layers can be formed within the stress relief buffer.

Semiconductor Device and Method of Balancing Surfaces of an Embedded PCB Unit with a Dummy Copper Pattern

A semiconductor device has a substrate. A conductive via is formed through the substrate. A plurality of first contact pads is formed over a first surface of the substrate. A plurality of second contact pads is formed over a second surface of the substrate. A dummy pattern is formed over the second surface of the substrate. An indentation is formed in a sidewall of the substrate. An opening is formed through the substrate. An encapsulant is deposited in the opening. An insulating layer is formed over second surface of the substrate. A dummy opening is formed in the insulating layer. A semiconductor die is disposed adjacent to the substrate. An encapsulant is deposited over the semiconductor die and substrate. The first surface of the substrate includes a width that is greater than a width of the second surface of the substrate.

Method for building up a fan-out RDL structure with fine pitch line-width and line-spacing

A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first insulating layer is formed over a first surface of the encapsulant and an active surface of the semiconductor die. A second insulating layer is formed over a second surface of the encapsulant opposite the first surface. A conductive layer is formed over the first insulating layer. The conductive layer includes a line-pitch or line-spacing of less than 5 μm. The active surface of the semiconductor die is recessed within the encapsulant. A third insulating layer is formed over the semiconductor die including a surface of the third insulating layer coplanar with a surface of the encapsulant. The second insulating layer is formed prior to forming the conductive layer. A trench is formed in the first insulating layer. The conductive layer is formed within the trench.

Sеmiсоnduсtоr dеviсе аnd mеthоd оf fоrming а vеrtiсаl intеrсоnnесt struсturе fоr 3-D FО-WLСSР

А sеmiсоnduсtоr dеviсе is mаdе bу fоrming а first соnduсtivе lауеr оvеr а саrriеr. Тhе first соnduсtivе lауеr hаs а first аrеа еlесtriсаllу isоlаtеd frоm а sесоnd аrеа оf thе first соnduсtivе lауеr. А соnduсtivе pillаr is fоrmеd оvеr thе first аrеа оf thе first соnduсtivе lауеr. А sеmiсоnduсtоr diе оr соmpоnеnt is mоuntеd tо thе sесоnd аrеа оf thе first соnduсtivе lауеr. А first еnсаpsulаnt is dеpоsitеd оvеr thе sеmiсоnduсtоr diе аnd аrоund thе соnduсtivе pillаr. А first intеrсоnnесt struсturе is fоrmеd оvеr thе first еnсаpsulаnt. Тhе first intеrсоnnесt struсturе is еlесtriсаllу соnnесtеd tо thе соnduсtivе pillаr. Тhе саrriеr is rеmоvеd. А pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd. Тhе rеmаining pоrtiоn оf thе first соnduсtivе lауеr inсludеs аn intеrсоnnесt linе аnd UВМ pаd. А sесоnd intеrсоnnесt struсturе is fоrmеd оvеr а rеmаining pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd.

Semiconductor method and device of forming a fan-out pop device with PWB vertical interconnect units

A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.

Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (ewlb-mlp)

A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than l millimeter. The opening includes a tapered sidewall formed by laser direct ablation.

Semiconductor device and method of forming the device using sacrificial carrier

SEMICONDUCTOR DEVICE HAVING BALANCED BAND-PASS FILTER IMPLEMENTED WITH LC RESONATORS

Semiconductor device and method of forming conductive vias through interconnect structures and encapsulant of WLCSP

A semiconductor device has a semiconductor die mounted over the carrier. An encapsulant is deposited over the carrier and semiconductor die. The carrier is removed. A first interconnect structure is formed over the encapsulant and a first surface of the die. A second interconnect structure is formed over the encapsulant and a second surface of the die. A first protective layer is formed over the first interconnect structure and second protective layer is formed over the second interconnect structure prior to forming the vias. A plurality of vias is formed through the second interconnect structure, encapsulant, and first interconnect structure. A first conductive layer is formed in the vias to electrically connect the first interconnect structure and second interconnect structure. An insulating layer is formed over the first interconnect structure and second interconnect structure and into the vias. A discrete semiconductor component can be mounted to the first interconnect structure.

Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD)

A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.

System-in-package having integrated passive devices and method therefor

A method of manufacturing a semiconductor device involves providing a substrate, forming a first passivation layer over the substrate, and forming an integrated passive circuit over the substrate. The integrated passive circuit can include inductors, capacitors, and resistors. A second passivation layer is formed over the integrated passive circuit. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive circuit. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive circuit. A metal layer can be formed over the molding compound or first passivation layer for shielding.

Semiconductor package and method of reducing electromagnetic interference between devices

A wafer level semiconductor package has a substrate and an RF module and baseband module coupled to the substrate with solder bumps. An underfill material is disposed under the RF module and baseband module. A first shielding layer is applied to a first surface of the substrate. A seed layer is deposited on the substrate and RF module and baseband module. A second shielding layer is plated over the seed layer, except over the contact pads on the substrate. The second shielding layer can be made from copper, gold, nickel, or aluminum. The first and second shielding layers substantially cover the wafer level semiconductor package to isolate the baseband module from electromagnetic interference generated by the RF module. The first and second shielding layers are grounded through the substrate.

Sеmiсоnduсtоr dеviсе аnd mеthоd оf fоrming а vеrtiсаl intеrсоnnесt struсturе fоr 3-D FО-WLСSР

А sеmiсоnduсtоr dеviсе is mаdе bу fоrming а first соnduсtivе lауеr оvеr а саrriеr. Тhе first соnduсtivе lауеr hаs а first аrеа еlесtriсаllу isоlаtеd frоm а sесоnd аrеа оf thе first соnduсtivе lауеr. А соnduсtivе pillаr is fоrmеd оvеr thе first аrеа оf thе first соnduсtivе lауеr. А sеmiсоnduсtоr diе оr соmpоnеnt is mоuntеd tо thе sесоnd аrеа оf thе first соnduсtivе lауеr. А first еnсаpsulаnt is dеpоsitеd оvеr thе sеmiсоnduсtоr diе аnd аrоund thе соnduсtivе pillаr. А first intеrсоnnесt struсturе is fоrmеd оvеr thе first еnсаpsulаnt. Тhе first intеrсоnnесt struсturе is еlесtriсаllу соnnесtеd tо thе соnduсtivе pillаr. Тhе саrriеr is rеmоvеd. А pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd. Тhе rеmаining pоrtiоn оf thе first соnduсtivе lауеr inсludеs аn intеrсоnnесt linе аnd UВМ pаd. А sесоnd intеrсоnnесt struсturе is fоrmеd оvеr а rеmаining pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd.

SEMICONDUCTOR DEVICE FORMING A CONTACT PAD AND A SEMICONDUCTOR DEVICE FABRICATING METHOD WHICH USES SACRIFICIAL CARRIER

PURPOSE: A semiconductor device and a semiconductor device fabricating method which uses sacrificial carrier are provided to achieve the exact location and arrangement about the essential interconnection structures by forming a contact pad on the sacrificial carrier. CONSTITUTION: A photoresist layer is deposited on a metal carrier. Semiconductor dies(36, 40) are mounted on a contact pad(34) on the metal carrier by solder bumps(38, 42). The contact pad is made of copper, tin, nickel, gold or silver. A molding compound(44) is formed around the semiconductor die. A process carrier(50) is mounted on the semiconductor die backside by an adhesive layer(48). A conductive layer(46) is electrically connected to the contact pad. An insulating layer(51) is formed on the molding compound and the conductive layer. © KIPO 2009 ...

Semiconductor device and method of forming fine pitch RDL over semiconductor die in fan-out package

A semiconductor device has a first conductive layer including a plurality of conductive traces. The first conductive layer is formed over a substrate. The conductive traces are formed with a narrow pitch. A first semiconductor die and second semiconductor die are disposed over the first conductive layer. A first encapsulant is deposited over the first and second semiconductor die. The substrate is removed. A second encapsulant is deposited over the first encapsulant. A build-up interconnect structure is formed over the first conductive layer and second encapsulant. The build-up interconnect structure includes a second conductive layer. A first passive device is disposed in the first encapsulant. A second passive device is disposed in the second encapsulant. A vertical interconnect unit is disposed in the second encapsulant. A third conductive layer is formed over second encapsulant and electrically connected to the build-up interconnect structure via the vertical interconnect unit.

Semiconductor package and method of reducing electromagnetic interference between devices

Semiconductor device and method of forming adhesive material to secure semiconductor die to carrier in WLCSP

A semiconductor device is made by providing a temporary carrier and providing a semiconductor die having a plurality of bumps formed on its active surface. An adhesive material is deposited as a plurality of islands or bumps on the carrier or active surface of the semiconductor die. The adhesive layer can also be deposited as a continuous layer over the carrier or active surface of the die. The semiconductor die is mounted to the carrier. An encapsulant is deposited over the die and carrier. The adhesive material holds the semiconductor die in place to the carrier while depositing the encapsulant. An interconnect structure is formed over the active surface of the die. The interconnect structure is electrically connected to the bumps of the semiconductor die. The adhesive material can be removed prior to forming the interconnect structure, or the interconnect structure can be formed over the adhesive material.

Integrated circuit system having different-size solder bumps and different-size bonding pads

An integrated circuit solder bumping system provides a substrate and forms a redistribution layer on the substrate. An insulation layer is formed on the redistribution layer. The insulation layer has a plurality of openings therethrough. A first UBM layer of titanium is deposited on the insulation layer and in the openings therethrough. A second UBM layer of chromium/copper alloy is deposited on the first UBM layer. A third UBM layer of copper is deposited on the second UBM layer. UBM pads of at least two different sizes are formed from the UBM layers. Solder paste is printed over at least some of the UBM pads. The solder paste is reflowed to form at least smaller solder bumps on at least some of the UBM pads. Bigger solder bumps are formed on at least some of the UBM pads.

Semiconductor Device and Method of Forming MEMS Package

A microelectromechanical system (MEMS) semiconductor device has a first and second semiconductor die. A first semiconductor die is embedded within an encapsulant together with a modular interconnect unit. Alternatively, the first semiconductor die is embedded within a substrate. A second semiconductor die, such as a MEMS die, is disposed over the first semiconductor die and electrically connected to the first semiconductor die through an interconnect structure. In another embodiment, the first semiconductor die is flip chip mounted to the substrate, and the second semiconductor die is wire bonded to the substrate adjacent to the first semiconductor die. In another embodiment, first and second semiconductor die are embedded in an encapsulant and are electrically connected through a build-up interconnect structure. A lid is disposed over the semiconductor die. In a MEMS microphone embodiment, the lid, substrate, or interconnect structure includes an opening over a surface of the MEMS die.

Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process

A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer is formed over the substrate and intermediate conduction layer. An adhesive layer is formed over the passivation layer. A barrier layer is formed over the adhesive layer. A wetting layer is formed over the barrier layer. The barrier layer and wetting layer in a first region are removed, while the barrier layer, wetting layer, and adhesive layer in a second region are maintained. The adhesive layer over the passivation layer in the first region are maintained until the solder bumps are formed. By keeping the adhesive layer over the passivation layer until after formation of the solder bumps, less cracking occurs in the passivation layer. 1. A semiconductor device , comprising:a substrate having a plurality of semiconductor devices formed on a surface of the substrate;a contact pad formed over the substrate in electrical contact with the semiconductor devices;a redistribution layer (RDL) formed over the substrate in electrical contact with the contact pad;a passivation layer formed over the substrate and RDL, wherein a portion of the passivation layer is removed to expose the RDL;an adhesive layer formed over the passivation layer and the exposed RDL;a barrier layer formed over a first portion of the adhesive layer which is over the exposed RDL, the barrier layer not being formed over a second portion of the adhesive layer;a wetting layer formed over the barrier layer which is over the first portion of the adhesive layer, the wetting layer not being formed over the second portion of the adhesive layer; anda bump formed over the wetting layer and barrier layer.2. The semiconductor device of claim 1 , wherein the first portion of the adhesive layer is removed after the bump is formed.3. The semiconductor device of claim 1 , wherein the wetting layer ...

Encapsulant interposer system with integrated passive devices and manufacturing method therefor

A method of manufacturing a semiconductor package system includes: forming a leadframe having a passive device; encapsulating the passive device to form an encapsulant interposer; attaching a first die to the encapsulant interposer; forming a substrate interposer having a second die; and stacking the encapsulant interposer over the substrate interposer.

SEMICONDUCTOR DEVICE AND A METHOD FOR FORMING A PASSIVE CIRCUIT ELEMENT WITH THROUGH SILICON VIA TO BACKSIDE INTERCONNECT STRUCTURES, CAPABLE OF IMPROVING THE RELIABILITY OF HIGH INTEGRATED CIRCUIT

PURPOSE: A semiconductor device and a method for forming a passive circuit element are provided to perform a reactive circuit of a semiconductor without an external element. CONSTITUTION: In a semiconductor device and a method for forming a passive circuit element, an analog circuit is formed on a substrate(30). A penetration substrate via is formed in the substrate, and an under bump metallization is formed on the backside of the substrate. A solder material is deposited on a under bump metallization layer, and a reflow to the solder material is performed and the solder bump is formed. At that time, the analog circuit is electrically connected with the solder bump through the penetration substrate via. © KIPO 2009 ...

SEMICONDUCTOR DEVICE WITH THREE-DIMENSIONAL VERTICALLY ORIENTED INTEGRATED CAPACITORS

Abstract SEMICONDUCTOR DEVICE WITH THREEDIMENSIONAL VERTICALLYORIENTED INTEGRATED CAPACITORSA semiconductor device includes conductive pillars disposed vertically over a seed layer, a conformal insulating layer formed over the conductive pillars, and a conformal conductive layer formed over the conformal insulating layer. A first conductive pillar, the conformal insulating layer, and the conformal conductive layer constitute a vertically oriented integrated capacitor. The semiconductor device further includes a semiconductor die or component mounted over the seed layer, an encapsulant deposited over the semiconductor die or component and around the conformal conductive layer, and a first interconnect structure formed over a first side of the encapsulant. The first interconnect structure is electrically connected to a second conductive pillar, and includes an integrated passive device. The semiconductor device further includes a second interconnect structure formed over a second side of ...

Semiconductor device and method of forming ipd structure using smooth conductive layer and bottom-side conductive layer

Semiconductor device and method of controlling warpage in reconstituted wafer

Semiconductor device and method of forming MEMS package

A microelectromechanical system (MEMS) semiconductor device has a first and second semiconductor die. A first semiconductor die is embedded within an encapsulant together with a modular interconnect unit. Alternatively, the first semiconductor die is embedded within a substrate. A second semiconductor die, such as a MEMS die, is disposed over the first semiconductor die and electrically connected to the first semiconductor die through an interconnect structure. In another embodiment, the first semiconductor die is flip chip mounted to the substrate, and the second semiconductor die is wire bonded to the substrate adjacent to the first semiconductor die. In another embodiment, first and second semiconductor die are embedded in an encapsulant and are electrically connected through a build-up interconnect structure. A lid is disposed over the semiconductor die. In a MEMS microphone embodiment, the lid, substrate, or interconnect structure includes an opening over a surface of the MEMS die.

Double-sided semiconductor package and dual-mold method of making same

A semiconductor device comprises a first conductive layer formed on a carrier over an insulating layer. A portion of the insulating layer is removed prior to forming the first conductive layer. A first semiconductor die is disposed over the first conductive layer. A discrete electrical component is disposed over the first conductive layer adjacent to the first semiconductor die. A first encapsulant is deposited over the first conductive layer and first semiconductor layer. A conductive pillar is formed through the first encapsulant between the first conductive layer and second conductive layer. A second encapsulant is deposited around the first encapsulant, first conductive layer, and first semiconductor die. A second conductive layer is formed over the first semiconductor die, first encapsulant, and second encapsulant opposite the first conductive layer. The carrier is removed after forming the second conductive layer. A semiconductor package is mounted to the first conductive layer.

Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors

A semiconductor device includes conductive pillars disposed vertically over a seed layer, a conformal insulating layer formed over the conductive pillars, and a conformal conductive layer formed over the conformal insulating layer. A first conductive pillar, the conformal insulating layer, and the conformal conductive layer constitute a vertically oriented integrated capacitor. The semiconductor device further includes a semiconductor die or component mounted over the seed layer, an encapsulant deposited over the semiconductor die or component and around the conformal conductive layer, and a first interconnect structure formed over a first side of the encapsulant. The first interconnect structure is electrically connected to a second conductive pillar, and includes an integrated passive device. The semiconductor device further includes a second interconnect structure formed over a second side of the encapsulant opposite the first side of the encapsulant.

Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compound

A semiconductor device is made with a conductive via formed through a top-side of the substrate. The conductive via extends vertically through less than a thickness of the substrate. An integrated passive device (IPD) is formed over the substrate. A plurality of first conductive pillars is formed over the first IPD. A first semiconductor die is mounted over the substrate. An encapsulant is formed around the first conductive pillars and first semiconductor die. A second IPD is formed over the encapsulant. An interconnect structure is formed over the second IPD. The interconnect structure operates as a heat sink. A portion of a back-side of the substrate is removed to expose the first conductive via. A second semiconductor die is mounted to the back-side of the substrate. The second semiconductor die is electrically connected to the first IPD and first semiconductor die through the conductive via.

Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units

A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.

Semiconductor device and method of forming micro-vias partially through insulating material over bump interconnect conductive layer for stress relief

A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A plurality of first micro-vias can be formed in the first insulating layer. A conductive layer is formed in the first micro-openings and over the first insulating layer. A second insulating layer is formed over the first insulating layer and conductive layer. A portion of the second insulating layer is removed to expose the conductive layer and form a plurality of second micro-openings in the second insulating layer over the conductive layer. The second micro-openings can be micro-vias, micro-via ring, or micro-via slots. Removing the portion of the second insulating layer leaves an island of the second insulating layer over the conductive layer. A bump is formed over the conductive layer. A third insulating layer is formed in the second micro-openings over the bump. The second micro-openings provide stress relief.

Semiconductor Device and Method of Providing Common Voltage Bus and Wire Bondable Redistribution

A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer including a plurality of contact pads formed over a surface of the semiconductor wafer;forming a first insulating layer over the semiconductor wafer;forming a first multilayer metallization pattern over the first insulating layer electrically connected to two or more of the contact pads;forming a common bus over the first multilayer metallization pattern;forming a second insulating layer over the first insulating layer and common bus; andforming a plurality of bumps over the common bus.2. The method of claim 1 , further including forming a plurality of conductive pillars over the common bus.3. The method of claim 2 , further including forming a second multilayer metallization pattern over the common bus prior to forming the conductive pillars.4. The method of claim 1 , wherein forming the first multilayer metallization pattern includes:forming an adhesion layer over the first insulating layer;forming a barrier layer over the adhesion layer; andforming a seed layer over the barrier layer.5. The method ...

Semiconductor Device and Method of Forming IPD on Molded Substrate

A semiconductor device is made by depositing an encapsulant material between first and second plates of a chase mold to form a molded substrate. A first conductive layer is formed over the molded substrate. A resistive layer is formed over the first conductive layer. A first insulating layer is formed over the resistive layer. A second insulating layer is formed over the first insulating layer, resistive layer, first conductive layer, and molded substrate. A second conductive layer is formed over the first insulating layer, resistive layer, and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. The first conductive layer, resistive layer, first insulating layer, and second conductive layer constitute a MIM capacitor. The second conductive layer is wound to exhibit inductive properties. 1. A method of making a semiconductor device , comprising:forming a substrate including a molding compound;forming a first conductive layer over the substrate;forming a first insulating layer over the first conductive layer;forming a second conductive layer over the first insulating layer and first conductive layer as a capacitor; andforming an interconnect structure electrically connected to the second conductive layer.2. The method of claim 1 , further including forming a resistive layer over the first conductive layer.3. The method of claim 1 , wherein forming the interconnect structure includes forming a bump or bond wire electrically connected to the capacitor.4. The method of claim 1 , wherein forming the substrate includes depositing an encapsulant between first and second plates of a chase mold.5. The method of claim 4 , further including:applying a first releasable layer over the first plate; andapplying a second releasable layer over the second plate.6. The method of claim 1 , further including forming a third conductive layer over the substrate claim 1 , ...

Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die

A semiconductor device has a TSV semiconductor wafer with a cavity formed in a first surface of the wafer. A second cavity can be formed in a second surface of the wafer. A plurality of semiconductor die is mounted within the cavities. The semiconductor die can be mounted side-by-side and/or stacked within the cavity. Conductive TSV can be formed through the die. An encapsulant is deposited within the cavity over the die. A CTE of the die is similar to a CTE of the encapsulant. A first interconnect structure is formed over a first surface of the encapsulant and wafer. A second interconnect structure is formed over a second surface of the encapsulant and wafer. The first and second interconnect structure are electrically connected to the TSV wafer. A second semiconductor die can be mounted over the first interconnect structure with encapsulant deposited over the second die.

Sеmiсоnduсtоr dеviсе аnd mеthоd оf fоrming а vеrtiсаl intеrсоnnесt struсturе fоr 3-D FО-WLСSР

А sеmiсоnduсtоr dеviсе is mаdе bу fоrming а first соnduсtivе lауеr оvеr а саrriеr. Тhе first соnduсtivе lауеr hаs а first аrеа еlесtriсаllу isоlаtеd frоm а sесоnd аrеа оf thе first соnduсtivе lауеr. А соnduсtivе pillаr is fоrmеd оvеr thе first аrеа оf thе first соnduсtivе lауеr. А sеmiсоnduсtоr diе оr соmpоnеnt is mоuntеd tо thе sесоnd аrеа оf thе first соnduсtivе lауеr. А first еnсаpsulаnt is dеpоsitеd оvеr thе sеmiсоnduсtоr diе аnd аrоund thе соnduсtivе pillаr. А first intеrсоnnесt struсturе is fоrmеd оvеr thе first еnсаpsulаnt. Тhе first intеrсоnnесt struсturе is еlесtriсаllу соnnесtеd tо thе соnduсtivе pillаr. Тhе саrriеr is rеmоvеd. А pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd. Тhе rеmаining pоrtiоn оf thе first соnduсtivе lауеr inсludеs аn intеrсоnnесt linе аnd UВМ pаd. А sесоnd intеrсоnnесt struсturе is fоrmеd оvеr а rеmаining pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd.

SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING COMMON VOLTAGE BUS AND WIRE BONDABLE REDISTRIBUTION TO ACHIEVE MINIATURIZATION

PURPOSE: A semiconductor device and the method for providing the common voltage bus and wire bondable redistribution are provided to obtain the reliable package and low cost by providing the single conductive structure in which the common voltage bus is connected. CONSTITUTION: The semiconductor wafer(100) comprises the plural semiconductor dies. The touch pad(102) is formed in the surface of wafer. The passivation(104) layer is formed on the wafer. The stress buffer layer(106) is formed on the passivation layer. The stress buffer layer is patterned to expose the touch pad. The metal layer is fusioned on the stress buffer layer. The metal layer is the common voltage bus for the touch pad and electrical contact. The metal layer is mounted on the seed layer. The solder bump or the other interconnection structures is formed in the metal layer. © KIPO 2009 ...

SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING COMMON VOLTAGE BUS AND WIRE BONDABLE REDISTRIBUTION

AbstractSEMICONDUCTOR DEVICE AND METHOD OF PROVIDING COMMON VOLTAGE BUS AND WIRE BONDABLE REDISTRIBUTIONA semiconductor wafer contains a plurality ofsemiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads.A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.(Fig. 5b ...

Semiconductor device and method of forming ipd in fan-out wafer level chip scale package

Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package

A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer and includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers (μm). The thickness of the semiconductor die is at least 1 μm less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer.

Semiconductor interconnect structure with stacked vias separated by signal line and method therefor

A semiconductor device is made by forming a first conductive layer over a substrate, forming a first passivation layer over the first conductive layer, forming a first via in the first passivation layer to expose the first conductive layer, forming a second conductive layer over the first passivation layer and within the first via to electrically connect to the first conductive layer, forming a second passivation layer over the second conductive layer, and forming a second via in the second passivation layer to expose the second conductive layer. The second via is smaller than the first via. The second via is either physically separate from or disposed over the first via. The second conductive layer within the second via has a flat surface which is wider than the second via. An under bump metallization is formed in the second via and electrically connected to the second conductive layer.

SEMICONDUCTOR PACKAGE AND A METHOD OF MANUFACTURE THEREOF WHICH CAN REDUCE THE ELECTROMAGNETIC INTERFERENCE BETWEEN THE SEMICONDUCTOR DEVICES

PURPOSE: A semiconductor package and a method of manufacture thereof are provided to cover the substrate to the first and the second shielding layer and to block the electromagnetic interference. CONSTITUTION: The first shield layer(18) is adhered to the first side of substrate. The RF module(24) is mounted on the first area on the second side of substrate through a plurality of solder bumps. The baseband module(26) is mounted on the second part on the second side of substrate through a plurality of solder bumps. The second shielding layer(30) covers the second side of substrate, the RF module and baseband module. The first and second shielding layers cover the wafer level semiconductor package. The baseband module is isolated from the electromagnetic interference generated by RF module. © KIPO 2009 ...

SEMICONDUCTOR DEVICE AND METHOD OF USING SUBSTRATE HAVING BASE ANDCONDUCTIVE POSTS TO FORM VERTICAL INTERCONNECT STRUCTURE INEMBEDDED DIE PACKAGE

SEMICONDUCTOR DEVICE AND METHOD OF USING SUBSTRATE HAVING BASE AND CONDUCTIVE POSTS TO FORM VERTICAL INTERCONNECT STRUCTURE IN EMBEDDED DIE PACKAGE

Semiconductor Device and Method of Forming Compliant Stress Relief Buffer Around Large Array WLCSP

A semiconductor device has a stress relief buffer mounted to a temporary substrate in locations designated for bump formation. The stress relief buffer can be a multi-layer composite material such as a first compliant layer, a silicon layer formed over the first compliant layer, and a second compliant layer formed over the silicon layer. A semiconductor die is also mounted to the temporary substrate. The stress relief buffer can be thinner than the semiconductor die. An encapsulant is deposited between the semiconductor die and stress relief buffer. The temporary substrate is removed. An interconnect structure is formed over the semiconductor die, encapsulant, and stress relief buffer. The interconnect structure is electrically connected to the semiconductor die. A stiffener layer can be formed over the stress relief buffer and encapsulant. A circuit layer containing active devices, passive devices, conductive layers, and dielectric layers can be formed within the stress relief buffer. 1. A semiconductor device , comprising:a semiconductor die;a stress relief buffer disposed partially around the semiconductor die in a location designated for bump formation;an encapsulant deposited between the stress relief buffer and semiconductor die; andan interconnect structure formed over the semiconductor die and stress relief buffer, the interconnect structure including a plurality of bumps formed over the stress relief buffer and electrically connected to the semiconductor die.2. The semiconductor device of claim 1 , wherein the stress relief buffer includes a multi-layer composite material.3. The semiconductor device of claim 1 , wherein the stress relief buffer includes:forming a first compliant layer;forming a silicon layer over the first compliant layer; andforming a second compliant layer over the silicon layer.4. The semiconductor device of claim 1 , further including a stiffener layer formed over the stress relief buffer and encapsulant.5. The semiconductor device of ...

Method for manufacture of integrated circuit package system with protected conductive layers for pads

A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer.

Solder Bump With Inner Core Pillar in Semiconductor Package

A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer having a plurality of active or passive devices formed on the semiconductor wafer;forming a first conductive layer over the semiconductor wafer electrically connected to the active or passive devices;forming an insulation layer over the first conductive layer and semiconductor wafer;removing a portion of the insulating layer to expose the first conductive layer;forming a second conductive layer over the first conductive layer and insulation layer;forming a third conductive layer over the second conductive layer;forming a fourth conductive layer over the third conductive layer;forming a core pillar having a hollow interior region over the fourth conductive layer and centered over first conductive layer, the core pillar having a width less than a width of the exposed first conductive layer;forming a fifth conductive layer over the fourth conductive layer and core pillar and into the hollow interior region;forming a sixth conductive layer over the fifth conductive layer and core pillar and into ...

Semiconductor Device and Method of Forming Stress Relief Layer Between Die and Interconnect Structure

A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar. 1. A semiconductor device , comprising:a semiconductor die;a plurality of conductive pillars formed around the semiconductor die;a conductive layer formed over the conductive pillars and vertically offset from the semiconductor die;a stress relief insulating layer formed over the semiconductor die and the conductive layer, the stress relief insulating layer having a first thickness over the semiconductor die and a second thickness less than the first thickness over the conductive layer;an encapsulant deposited over the semiconductor die and around the conductive pillars;a first interconnect structure formed over the stress relief insulating layer; anda second interconnect structure formed over the encapsulant opposite the stress relief insulating layer.2. The semiconductor device of claim 1 , wherein the second interconnect structure includes an integrated passive device.3. The semiconductor device of claim 1 , wherein a back surface of the semiconductor die opposite an active surface of the semiconductor die is coplanar with a ...

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Semiconductor Device and Method of Forming FO-WLCSP with Discrete Semiconductor Components Mounted Under and Over Semiconductor Die

A semiconductor die has first and second discrete semiconductor components mounted over a plurality of wettable contact pads formed on a carrier. Conductive pillars are formed over the wettable contact pads. A semiconductor die is mounted to the conductive pillars over the first discrete components. The conductive pillars provide vertical stand-off of the semiconductor die as headroom for the first discrete components. The second discrete components are disposed outside a footprint of the semiconductor die. Conductive TSV can be formed through the semiconductor die. An encapsulant is deposited over the semiconductor die and first and second discrete components. The wettable contact pads reduce die and discrete component shifting during encapsulation. A portion of a back surface of the semiconductor die is removed to reduce package thickness. An interconnect structure is formed over the encapsulant and semiconductor die. Third discrete semiconductor components can be mounted over the semiconductor die. 1. A method of making a semiconductor device , comprising:providing a carrier;forming a plurality of wettable contact pads over the carrier;mounting a plurality of first discrete semiconductor components over the wettable contact pads;mounting a plurality of second discrete semiconductor components over the wettable contact pads;forming a plurality of conductive pillars over the wettable contact pads;mounting a semiconductor die to the conductive pillars over the first discrete semiconductor components with the second discrete semiconductor components disposed outside a footprint of the semiconductor die;depositing an encapsulant over the semiconductor die and first and second discrete semiconductor components;removing a portion of a back surface of the semiconductor die opposite the conductive pillars;removing the carrier; andforming a first interconnect structure over the encapsulant and semiconductor die.2. The method of claim 1 , wherein the wettable contact pads ...

Semiconductor Device and Method of Forming TSV Semiconductor Wafer with Embedded Semiconductor Die

A semiconductor device has a TSV semiconductor wafer with a cavity formed in a first surface of the wafer. A second cavity can be formed in a second surface of the wafer. A plurality of semiconductor die is mounted within the cavities. The semiconductor die can be mounted side-by-side and/or stacked within the cavity. Conductive TSV can be formed through the die. An encapsulant is deposited within the cavity over the die. A CTE of the die is similar to a CTE of the encapsulant. A first interconnect structure is formed over a first surface of the encapsulant and wafer. A second interconnect structure is formed over a second surface of the encapsulant and wafer. The first and second interconnect structure are electrically connected to the TSV wafer. A second semiconductor die can be mounted over the first interconnect structure with encapsulant deposited over the second die. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer having a plurality of conductive through silicon vias (TSV) formed through the semiconductor wafer;mounting the semiconductor wafer to a carrier;forming a cavity in the semiconductor wafer between the conductive TSV;mounting a plurality of semiconductor die within the cavity of the semiconductor wafer;depositing an encapsulant within the cavity over the semiconductor die;forming a first interconnect structure over a first surface of the encapsulant and semiconductor wafer;removing the carrier; andforming a second interconnect structure over a second surface of the encapsulant and semiconductor wafer opposite the first surface, the first and second interconnect structures being electrically connected to the conductive TSV.2. The method of claim 1 , wherein a coefficient of thermal expansion of the semiconductor wafer is similar to a coefficient of thermal expansion of the encapsulant.3. The method of claim 1 , wherein a coefficient of thermal expansion of the semiconductor die is similar to a coefficient of ...

Semiconductor Device and Method of Forming Prefabricated EMI Shielding Frame with Cavities Containing Penetrable Material Over Semiconductor Die

A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame. 1. A semiconductor device , comprising:a first semiconductor die;a shielding frame mounted over the first semiconductor die, the shielding frame having a plate and a body integrated with and extending from the plate to define a cavity;an encapsulant deposited in the cavity;a plurality of openings formed in the shielding frame to enable excess encapsulant to escape; andan interconnect structure formed over the first semiconductor die.2. The semiconductor device of claim 1 , further including a conductive via formed through the encapsulant.3. The semiconductor device of claim 1 , further including a bump formed over the first semiconductor die to electrically connect the first semiconductor die to the interconnect structure.4. The semiconductor device of claim 1 , further including a heat sink mounted over the shielding frame.5. The semiconductor device of claim 1 , further including a second semiconductor die mounted over the first semiconductor die.6. The semiconductor device of claim 1 , further including a second semiconductor die mounted adjacent to the ...

Semiconductor Device and Method of Forming Prefabricated EMI Shielding Frame with Cavities Containing Penetrable Material Over Semiconductor Die

A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame.

Semiconductor Device and Method of Forming Insulating Layer Disposed Over The Semiconductor Die For Stress Relief

A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer having a plurality of semiconductor die;forming a first conductive layer over a surface of the semiconductor die;forming a first insulating layer over the semiconductor wafer and first conductive layer;singulating the semiconductor wafer to separate the semiconductor die;providing a carrier;mounting the semiconductor die to the carrier;depositing an encapsulant over the semiconductor die and carrier;removing the carrier; andforming an interconnect structure over the semiconductor die and encapsulant, wherein the interconnect structure is electrically connected to the first conductive layer and the first insulating layer provides stress relief during formation of the interconnect structure.2. The method of claim 1 , wherein forming the interconnect structure includes:forming a second insulating layer over the semiconductor die and encapsulant;forming a second conductive layer over the second insulating layer; ...

Semiconductor Device and Method of Forming an Inductor Within Interconnect Layer Vertically Separated from Semiconductor Die

A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer.

Semiconductor Device and Method of Forming Openings Through Insulating Layer Over Encapsulant for Enhanced Adhesion of Interconnect Structure

A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over a portion of the encapsulant within an interconnect site outside a footprint of the semiconductor die. An opening is formed through the first insulating layer within the interconnect site to expose the encapsulant. The opening can be ring-shaped or vias around the interconnect site and within a central region of the interconnect site to expose the encapsulant. A first conductive layer is formed over the first insulating layer to follow a contour of the first insulating layer. A second conductive layer is formed over the first conductive layer and exposed encapsulant. A second insulating layer is formed over the second conductive layer. A bump is formed over the second conductive layer in the interconnect site. 1. A method of making a semiconductor device , comprising:providing a carrier;mounting a semiconductor die to the carrier;depositing an encapsulant over the semiconductor die and carrier;removing the carrier;forming a first insulating layer over a portion of the encapsulant within an interconnect site outside a footprint of the semiconductor die;removing a portion of the first insulating layer within the interconnect site to expose the encapsulant;forming a first conductive layer over the first insulating layer and exposed encapsulant;forming a second insulating layer over the first conductive layer; andforming a bump over the first conductive layer in the interconnect site.2. The method of claim 1 , wherein removing the portion of the first insulating layer leaves a ring-shaped opening in the first insulating layer to expose the encapsulant.3. The method of claim 1 , wherein removing the portion of the first insulating layer leaves a plurality of openings in the first insulating layer at 90 degree increments around the interconnect site to expose the encapsulant ...

Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution Layer

A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die.

Semiconductor Device and Method of Forming Three-Dimensional Vertically Oriented Integrated Capacitors

A semiconductor device includes conductive pillars disposed vertically over a seed layer, a conformal insulating layer formed over the conductive pillars, and a conformal conductive layer formed over the conformal insulating layer. A first conductive pillar, the conformal insulating layer, and the conformal conductive layer constitute a vertically oriented integrated capacitor. The semiconductor device further includes a semiconductor die or component mounted over the seed layer, an encapsulant deposited over the semiconductor die or component and around the conformal conductive layer, and a first interconnect structure formed over a first side of the encapsulant. The first interconnect structure is electrically connected to a second conductive pillar, and includes an integrated passive device. The semiconductor device further includes a second interconnect structure formed over a second side of the encapsulant opposite the first side of the encapsulant. 1. A method of making a semiconductor device , comprising:forming a plurality of first vertical conductive structures within the semiconductor device;forming an insulating layer over the first vertical conductive structures; andforming a conductive layer over the insulating layer and first vertical conductive structures as a vertically oriented capacitor, the conductive layer extending beyond a footprint of the first vertical interconnect structures.2. The method of claim 1 , further including:providing a semiconductor die within the semiconductor device; anddepositing an encapsulant over the semiconductor die and vertically oriented capacitor.3. The method of claim 2 , further including:forming a first interconnect structure over a first surface of the encapsulant;forming a second interconnect structure over a second surface of the encapsulant opposite the first surface of the encapsulant; andforming a plurality of second vertical conductive structures between the first interconnect structure and second ...

Semiconductor Package with Semiconductor Core Structure and Method of Forming Same

A semiconductor device includes an IPD structure, a first semiconductor die mounted to the IPD structure with a flipchip interconnect, and a plurality of first conductive posts that are disposed adjacent to the first semiconductor die. The semiconductor device further includes a first molding compound that is disposed over the first conductive posts and first semiconductor die, a core structure bonded to the first conductive posts over the first semiconductor die, and a plurality of conductive TSVs disposed in the core structure. The semiconductor device further includes a plurality of second conductive posts that are disposed over the core structure, a second semiconductor die mounted over the core structure, and a second molding compound disposed over the second conductive posts and the second semiconductor die. The second semiconductor die is electrically connected to the core structure. 1. A method of making a semiconductor device , comprising:forming an integrated passive device (IPD) structure within the semiconductor device, the IPD structure including an inductor;mounting a first semiconductor die over the IPD structure and disposed away from the inductor;depositing a first encapsulant over the first semiconductor die and IPD structure with a thickness of the first encapsulant over the inductor being greater than 50 micrometers; andmounting a semiconductor core over a surface of the first encapsulant opposite the IPD structure.2. The method of claim 1 , further including mounting a second semiconductor die over the semiconductor core.3. The method of claim 2 , further including depositing a second encapsulant over the second semiconductor die and semiconductor core.4. The method of claim 3 , further including:forming a first interconnect structure over the second encapsulant; andforming a second interconnect structure over the IPD structure.5. The method of claim 1 , further including forming a plurality of conductive posts through the first encapsulant ...

Semiconductor Device and Method of Forming No-Flow Underfill Material Around Vertical Interconnect Structure

A semiconductor device is made by forming a conductive layer over a first sacrificial carrier. A solder bump is formed over the conductive layer. A no-flow underfill material is deposited over the first carrier, conductive layer, and solder bump. A semiconductor die or component is compressed into the no-flow underfill material to electrically contact the conductive layer. A surface of the no-flow underfill material and first solder bump is planarized. A first interconnect structure is formed over a first surface of the no-flow underfill material. The first interconnect structure is electrically connected to the solder bump. A second sacrificial carrier is mounted over the first interconnect structure. A second interconnect structure is formed over a second side of the no-flow underfill material. The second interconnect structure is electrically connected to the first solder bump. The semiconductor devices can be stacked and electrically connected through the solder bump. 1. A semiconductor device , comprising:a first semiconductor die;a vertical interconnect structure disposed outside the first semiconductor die;a conductive layer electrically connecting the first semiconductor die to the vertical interconnect structure;an insulating material disposed around the first semiconductor die and vertical interconnect structure with the insulating material, first semiconductor die, and vertical interconnect structure having a planar surface;a first interconnect structure formed over the planar surface; anda second interconnect structure formed over the conductive layer and insulating material opposite the first interconnect structure.2. The semiconductor device of claim 1 , wherein the insulating material includes a no-flow underfill material or encapsulant.3. The semiconductor device of claim 1 , wherein the first interconnect structure or second interconnect structure includes an integrated passive device.4. The semiconductor device of claim 1 , further including a ...

Semiconductor Device and Method of Forming Vertical Interconnect Structure in Substrate for IPD and Baseband Circuit Separated by High-Resistivity Molding Compound

A semiconductor device is made with a conductive via formed through a top-side of the substrate. The conductive via extends vertically through less than a thickness of the substrate. An integrated passive device (IPD) is formed over the substrate. A plurality of first conductive pillars is formed over the first IPD. A first semiconductor die is mounted over the substrate. An encapsulant is formed around the first conductive pillars and first semiconductor die. A second IPD is formed over the encapsulant. An interconnect structure is formed over the second IPD. The interconnect structure operates as a heat sink. A portion of a back-side of the substrate is removed to expose the first conductive via. A second semiconductor die is mounted to the back-side of the substrate. The second semiconductor die is electrically connected to the first IPD and first semiconductor die through the conductive via. 1. A semiconductor device , comprising:a substrate;a plurality of conductive vias formed in the substrate;a first semiconductor die mounted over the substrate;an integrated passive device (IPD) structure formed over the substrate and disposed away from the first semiconductor die;an encapsulant deposited over the first semiconductor die and IPD structure;a first interconnect structure formed over a surface of the encapsulant opposite the IPD structure;a plurality of vertical conductive structures formed through the encapsulant between the IPD structure and first interconnect structure; anda second interconnect structure formed over a surface of the substrate opposite the IPD structure and electrically connected to the conductive vias.2. The semiconductor device of claim 1 , wherein the IPD structure includes a capacitor.3. The semiconductor device of claim 1 , wherein a thickness of the encapsulant over the IPD structure is at least 50 micrometers.4. The semiconductor device of claim 1 , wherein the first interconnect structure includes an inductor.5. The semiconductor ...

INTEGRATED CIRCUIT PACKAGE SYSTEM WITH POST-PASSIVATION INTERCONNECTION AND INTEGRATION

An integrated circuit package system including: providing an integrated circuit die, forming a first layer over the integrated circuit die, forming a bridge on and in the first layer, forming a second layer on the first layer, and forming bump pads on and in the second layer, the bump pads connected to ends of the bridge. 1. A method of manufacturing an integrated circuit package system comprising:providing an integrated circuit die with a bond pad;forming a first layer over the integrated circuit die;forming a bridge directly on the first layer;forming a second layer on the first layer;forming a redistribution layer between the bond pad and the bridge, the redistribution layer contacting the bridge; andforming a bump pad remote from the redistribution layer and in contact with the bridge and directly on and in the second layer.2. The method as claimed in wherein:providing the integrated circuit die provides the integrated circuit die with adjacent bond pads; andforming the bridge includes forming another bridge connected at the ends to the adjacent bond pads.3. The method as claimed in wherein:providing the integrated circuit die provides the integrated circuit die with integral adjacent bond pads; andforming the bump pads forms the bump pads individually connected to the integral adjacent bond pads.4. The method as claimed in wherein forming the bump pads includes forming a bump pad as a stand alone bump pad.5. The method as claimed in wherein:forming the bump pads includes forming a bump pad; andconnecting an interconnect to the bump pad.6. An integrated circuit package system comprising:an integrated circuit die with a bond pad;a first layer over the integrated circuit die;a bridge in contact with a redistribution layer, the redistribution layer between the bond pad and the bridge, and the bridge directly on the first layer;a second layer on the first layer; anda bump pad remote from the redistribution layer and in contact with the bridge and directly on and in ...

Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier

A semiconductor device includes a first semiconductor die or component having a plurality of bumps, and a plurality of first and second contact pads. In one embodiment, the first and second contact pads include wettable contact pads. The bumps are mounted directly to a first surface of the first contact pads to align the first semiconductor die or component. An encapsulant is deposited over the first semiconductor die or component. An interconnect structure is formed over the encapsulant and is connected to a second surface of the first and second contact pads opposite the first surface of the first contact pads. A plurality of vias is formed through the encapsulant and extends to a first surface of the second contact pads. A conductive material is deposited in the vias to form a plurality of conductive vias that are aligned by the second contact pads to reduce interconnect pitch.

Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die Having Pre-Applied Protective Layer

A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;forming a protective layer over a surface of the semiconductor die;forming a conductive layer around the semiconductor die;forming a plurality of vias through the protective layer extending to contact pads formed on the surface of the semiconductor die;depositing an encapsulant over the semiconductor die and conductive layer; andforming an interconnect structure over the protective layer and electrically connected to the conductive layer, the interconnect structure extending into the vias to electrically connect to the contact pads on the semiconductor die.2. The method of claim 1 , wherein forming the interconnect structure includes:forming a first redistribution layer (RDL) over the protective layer and extending into the vias to electrically connect to the contact pads on the semiconductor die; andforming a first insulating layer over the first RDL.3. The method of claim 2 , further including:forming a second ...

Semiconductor Device and Method of Embedding Bumps Formed on Semiconductor Die into Penetrable Adhesive Layer to Reduce Die Shifting During Encapsulation

A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the first semiconductor die. A penetrable adhesive layer is formed over a temporary carrier. The adhesive layer can include a plurality of slots. The semiconductor die is mounted to the carrier by embedding the bumps into the penetrable adhesive layer. The semiconductor die and interconnect structure can be separated by a gap. An encapsulant is deposited over the first semiconductor die. The bumps embedded into the penetrable adhesive layer reduce shifting of the first semiconductor die while depositing the encapsulant. The carrier is removed. An interconnect structure is formed over the semiconductor die. The interconnect structure is electrically connected to the bumps. A thermally conductive bump is formed over the semiconductor die, and a heat sink is mounted to the interconnect structure and thermally connected to the thermally conductive bump. 1. A semiconductor device , comprising:a first semiconductor die including a plurality of bumps formed over a surface of the first semiconductor die;a penetrable adhesive layer disposed over the first semiconductor die with the bumps at least partially disposed in the penetrable adhesive layer;an encapsulant deposited over the first semiconductor die; andan interconnect structure formed over the first semiconductor die and electrically connected to the bumps.2. The semiconductor device of claim 1 , wherein the bumps are at least partially disposed in the penetrable adhesive layer reduce shifting of the first semiconductor die.3. The semiconductor device of claim 1 , wherein the interconnect structure includes:a conductive layer; andan insulating layer formed around the conductive layer.4. The semiconductor device of claim 1 , further including a gap between the surface of the first semiconductor die and the penetrable adhesive layer.5. The semiconductor device of claim 1 , further including a plurality of electrically ...

Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die having Pre-Applied Protective Layer

A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;providing a first insulating layer;depositing an encapsulant around the semiconductor die;forming an opening in the first insulating layer using a laser, the opening extending to the semiconductor die disposed over the first insulating layer; andforming a first conductive layer within the opening and over the first insulating layer and electrically connected to the semiconductor die.2. The method of claim 1 , further including:forming a via through the encapsulant using the laser; andforming a conductive material within the via.3. The method of claim 1 , further including disposing a semiconductor component within the encapsulant outside a footprint of the semiconductor die.4. The method of claim 1 , further including forming an interconnect structure over the semiconductor die and encapsulant.5. The method of claim 4 , wherein forming the interconnect structure includes:forming a second insulating layer over the ...

Semiconductor Device and Method of Forming an IPD over a High-Resistivity Encapsulant Separated from other IPDS and Baseband Circuit

A semiconductor device has a first conductive layer formed over a sacrificial substrate. A first integrated passive device (IPD) is formed in a first region over the first conductive layer. A conductive pillar is formed over the first conductive layer. A high-resistivity encapsulant greater than 1.0 kohm-cm is formed over the first IPD to a top surface of the conductive pillar. A second IPD is formed over the encapsulant. The first encapsulant has a thickness of at least 50 micrometers to vertically separate the first and second IPDs. An insulating layer is formed over the second IPD. The sacrificial substrate is removed and a second semiconductor die is disposed on the first conductive layer. A first semiconductor die is formed in a second region over the substrate. A second encapsulant is formed over the second semiconductor die and a thermally conductive layer is formed over the second encapsulant. 1. A semiconductor device , comprising:a first integrated passive device (IPD) formed in a first region over the semiconductor device;a conductive pillar extending above the first IPD;a semiconductor die disposed in a second region of the semiconductor device laterally offset from the first IPD;a first encapsulant deposited over the first IPD and semiconductor die; anda second IPD formed over the first encapsulant opposite the first IPD to reduce inter-device interference between the first IPD and second IPD.2. The semiconductor device of claim 1 , wherein the first IPD and second IPD include a resistor claim 1 , capacitor claim 1 , or inductor.3. The semiconductor device of claim 1 , further including a semiconductor component disposed over a surface of the semiconductor device opposite the second IPD.4. The semiconductor device of claim 3 , further including a second encapsulant formed over the semiconductor component.5. The semiconductor device of claim 1 , wherein the first encapsulant includes a resistivity greater than 1.0 kohm-cm.6. The semiconductor device of ...

Semiconductor Device and Method for Forming Passive Circuit Elements With Through Silicon Vias to Backside Interconnect Structures

A semiconductor wafer contains a substrate having a plurality of active devices formed thereon. An analog circuit is formed on the substrate. The analog circuit can be an inductor, metal-insulator-metal capacitor, or resistor. The inductor is made with copper. A through substrate via (TSV) is formed in the substrate. A conductive material is deposited in the TSV in electrical contact with the analog circuit. An under bump metallization layer is formed on a backside of the substrate in electrical contact with the TSV. A solder material is deposited on the UBM layer. The solder material is reflowed to form a solder bump. A wire bond is formed on a top surface of the substrate. A redistribution layer is formed between the TSV and UBM. The analog circuit electrically connects through the TSV to the solder bump on the back side of the substrate.

Method of Forming an Inductor on a Semiconductor Wafer

A semiconductor device has a substrate with an inductor formed on its surface. First and second contact pads are formed on the substrate. A passivation layer is formed over the substrate and first and second contact pads. A protective layer is formed over the passivation layer. The protective layer is removed over the first contact pad, but not from the second contact pad. A conductive layer is formed over the first contact pad. The conductive layer is coiled on the surface of the substrate to produce inductive properties. The formation of the conductive layer involves use of a wet etchant. The second contact pad is protected from the wet etchant by the protective layer. The protective layer is removed from the second contact pad after forming the conductive layer over the first contact pad. An external connection is formed on the second contact pad. 1. A semiconductor device , comprising:a substrate;a first conductive layer formed over the substrate;a first insulating layer formed over the substrate, the first insulating layer including a first opening over a first portion of the first conductive layer and a second opening over a second portion of the first conductive layer;a protective layer formed over the second portion of the first conductive layer while the first portion of the first conductive layer remains exposed;a second conductive layer formed over the first portion of the first conductive layer and first insulating layer while the protective layer protects the second portion of the first conductive layer; anda second insulating layer formed over the second conductive layer and first insulating layer.2. The semiconductor device of claim 1 , further including an interconnect structure formed over and electrically connected to the second portion of the first conductive layer.3. The semiconductor device of claim 2 , wherein the interconnect structure includes a wire bond claim 2 , bump claim 2 , or conductive via.4. The semiconductor device of claim 1 , ...

Semiconductor Device with Solder Bump Formed on High Topography Plated Cu Pads

A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer.

Solder Bump with Inner Core Pillar in Semiconductor Package

A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.

Semiconductor Device and Method of Forming Repassivation Layer with Reduced Opening to Contact Pad of Semiconductor Die

A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer. 1. A semiconductor device , comprising:a semiconductor wafer including a plurality of semiconductor die;a first conductive layer formed over the semiconductor die;an insulating layer formed over the semiconductor die and first conductive layer;a passivation layer formed over the insulating layer and first conductive layer; anda conductive via formed through the passivation layer and extending to the first conductive layer.2. The semiconductor device of claim 1 , further including an interconnect structure formed over the passivation layer.3. The semiconductor device of claim 1 , further including an opening formed in the insulating layer.4. The semiconductor device of claim 3 , wherein a width of the opening is greater than a width of the conductive via.5. The semiconductor device of claim 3 , wherein the passivation layer extends through the opening and to the first conductive layer.6. The semiconductor device of claim 1 , further including a second conductive layer disposed between the passivation layer and insulating layer. ...

Semiconductor Device and Method of Forming Protection and Support Structure for Conductive Interconnect Structure

A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer having a plurality of contact pads;forming a first insulating layer over the semiconductor wafer and contact pads;removing a portion of the first insulating layer to expose a first portion of the contact pads, while leaving a second portion of the contact pads covered by the first insulating layer;forming an under bump metallization layer over the contact pads and the first insulating layer;forming a plurality of bumps over the under bump metallization layer;forming a second insulating layer over the semiconductor wafer to cover the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps; andremoving a portion of the second insulating layer covering the upper surface of the bumps, while maintaining coverage of the second insulating layer over the sidewall of the bumps and the sidewall of the under bump metallization layer to provide structural support for the bumps and prevent growth of inter-metallic compounds.2. The method of claim 1 , wherein removing the portion of the ...

Semiconductor Device and Method of Forming Protection and Support Structure for Conductive Interconnect Structure

A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer having a plurality of contact pads;forming a first insulating layer over the semiconductor wafer and contact pads;removing a portion of the first insulating layer to expose a first portion of the contact pads, while leaving a second portion of the contact pads covered by the first insulating layer;forming an under bump metallization layer over the contact pads and the first insulating layer;forming a plurality of bumps over the under bump metallization layer;forming a second insulating layer over the semiconductor wafer to cover the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps; andremoving a portion of the second insulating layer covering the upper surface of the bumps, while maintaining coverage of the second insulating layer over the sidewall of the bumps and the sidewall of the under bump metallization layer to provide structural support for the bumps and prevent growth of inter-metallic compounds.2. The method of claim 1 , wherein removing the portion of the ...

Semiconductor Device and Method of Forming Semiconductor Package Using Panel Form Carrier

A semiconductor device has a first insulating layer formed over a carrier. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer. Vias are formed through the second insulating layer. A second conductive layer is formed over the second insulating layer and extends into the vias. A semiconductor die is mounted to the second conductive layer. A bond wire is formed between a contact pad on the semiconductor die and the second conductive layer. The second conductive layer extends to a mounting site of the semiconductor die to minimize the bond wire span. An encapsulant is deposited over the semiconductor die. A portion of the first insulating layer is removed to expose the second conductive layer. A portion of the first conductive layer is removed to electrically isolate remaining portions of the first conductive layer. 1. A method of making a semiconductor device , comprising:providing a carrier;forming an insulating layer over the carrier;forming a first conductive layer over the insulating layer;forming a second conductive layer over the first conductive layer;mounting a first semiconductor die to the first conductive layer;forming a bond wire between a contact pad on the first semiconductor die and the second conductive layer;depositing a first encapsulant over the first semiconductor die and carrier;removing the carrier;removing a portion of the insulating layer to expose the second conductive layer; andremoving a portion of the first conductive layer to electrically isolate remaining portions of the first conductive layer.2. The method of claim 1 , wherein the second conductive layer extends to a mounting site of the first semiconductor die.3. The method of claim 1 , further including depositing a second encapsulant over the first encapsulant.4. The method of claim 1 , further including retaining a portion of the first conductive layer over the semiconductor die for heat dissipation.5 ...

Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP

A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.

Semiconductor Device and Method of Forming Interconnect Substration for FO-WLCSP

A semiconductor device has a first encapsulant deposited over a first carrier. A plurality of conductive vias is formed through the first encapsulant to provide an interconnect substrate. A first semiconductor die is mounted over a second carrier. The interconnect substrate is mounted over the second carrier adjacent to the first semiconductor die. A second semiconductor die is mounted over the second carrier adjacent to the interconnect substrate. A second encapsulant is deposited over the first and second semiconductor die, interconnect substrate, and second carrier. A first interconnect structure is formed over a first surface of the second encapsulant and electrically connected to the conductive vias. A second interconnect structure is formed over a second surface of the second encapsulant and electrically connected to the conductive vias to make the Fo-WLCSP stackable. Additional semiconductor die can be mounted over the first and second semiconductor die in a PoP arrangement. 1. A method of making a semiconductor device , comprising:providing a first carrier;depositing a first encapsulant over the first carrier;forming a plurality of conductive vias through the first encapsulant to form an interconnect substrate;providing a second carrier;mounting first and second semiconductor die over the second carrier;mounting the interconnect substrate over the second carrier adjacent to the first and second semiconductor die;depositing a second encapsulant over the first and second semiconductor die, interconnect substrate, and second carrier;forming a first interconnect structure over a first surface of the second encapsulant and electrically connected to the conductive vias of the interconnect substrate;removing the second carrier; andforming a second interconnect structure over a second surface of the second encapsulant opposite the first surface of the second encapsulant and electrically connected to the conductive vias of the interconnect substrate.2. The method of ...

SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF

A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer having a plurality of semiconductor die;forming a first conductive layer over a surface of the semiconductor die;forming a first insulating layer over the semiconductor wafer and first conductive layer;singulating the semiconductor wafer to separate the semiconductor die;providing a carrier;mounting the semiconductor die to the carrier;depositing an encapsulant over the semiconductor die and carrier;removing the carrier; andforming an interconnect structure over the semiconductor die and encapsulant, wherein the interconnect structure is electrically connected to the first conductive layer and the first insulating layer provides stress relief during formation of the interconnect structure.2. The method of claim 1 , wherein forming the interconnect structure includes:forming a second insulating layer over the semiconductor die and encapsulant;forming a second conductive layer over the second insulating layer; ...

Semiconductor Device and Method of Laser-Marking Laminate Layer Formed Over EWLB With Tape Applied to Opposite Surface

A semiconductor device has a semiconductor die with a plurality of bumps formed on contact pads disposed over its active surface. An encapsulant is formed over the semiconductor die. An interconnect structure is formed over the semiconductor die and encapsulant. The semiconductor die is mounted to a translucent tape with the bumps embedded in the translucent tape. The translucent tape has layers of polyolefin, acrylic, and polyethylene terephthalate. A back surface of the semiconductor die undergoes backgrinding to reduce die thickness. The tape undergoes UV curing. A laminate layer is formed over the back surface of the semiconductor die. The laminate layer undergoes oven curing. The laminate layer is laser-marked while the tape remains applied to the bumps. The tape is removed after laser-marking the laminate layer. Alternately, the tape can be removed prior to laser-marking. The tape reduces die warpage during laser-marking.

Semiconductor Device and Method for Forming Semiconductor Package Having Build-Up Interconnect Structure Over Semiconductor Die with Different CTE Insulating Layers

A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture. 1. A semiconductor device , comprising:a semiconductor die;an encapsulant deposited over a first surface of the semiconductor die and around a peripheral region of the semiconductor die;a first insulating layer formed over the encapsulant and a second surface of the semiconductor die opposite the first surface of the semiconductor die with multiple dwell curing cycles to enhance adhesion to the semiconductor die and encapsulant;a first conductive layer formed over the first insulating layer; anda second insulating layer formed over the first insulating layer and first conductive layer with multiple dwell curing cycles to enhance adhesion to the first insulating layer and first conductive layer.2. The semiconductor device of claim 1 , wherein the multiple dwell curing cycles include a first dwell step with a first temperature for a first time period claim 1 , second dwell step with a second temperature for a second time period claim 1 , and third dwell step with a third temperature for a third time period.3. The semiconductor device of claim ...

Semiconductor Device and Method of Forming Insulating Layer Around Semiconductor Die

A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die. 1. A semiconductor device , comprising:a plurality of semiconductor die;a first insulating layer formed over the semiconductor die;an encapsulant deposited around the semiconductor die;a second insulating layer formed over the encapsulant and semiconductor die;a conductive layer formed over the second insulating layer; anda third insulating layer formed over the second insulating layer and conductive layer.2. The semiconductor device of claim 1 , further including a channel in the second insulating layer around the semiconductor die.3. The semiconductor device of claim 1 , further including a net pattern in the second insulating layer around the semiconductor die.4. The semiconductor device of claim 1 , wherein the second insulating layer covers the encapsulant around the semiconductor die.5. The semiconductor device of claim 1 , further including an interconnect structure formed over the third insulating layer and electrically connected to the conductive layer.6. The semiconductor device of claim 1 , wherein the plurality of semiconductor die is singulated through the ...

Semiconductor Device and Method of Forming Thick Encapsulant for Stiffness with Recesses for Stress Relief in FO-WLCSP

A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device. 1. A method of making a semiconductor device , comprising:providing a carrier;providing a semiconductor die;mounting the semiconductor die to the carrier;depositing an encapsulant over the semiconductor die and carrier;forming a plurality of channels in the encapsulant;removing the carrier;forming an interconnect structure over the semiconductor die and encapsulant; andremoving a portion of the encapsulant and channels after forming the interconnect structure to reduce thickness of the semiconductor device.2. The method of claim 1 , wherein a thickness of the encapsulant provides sufficient stiffness to reduce warpage while the channels provide stress relief during formation of the interconnect structure.3. The method of claim 1 , further including forming the channels in perpendicular directions.4. The method of claim 1 , wherein forming the channels includes removing a portion of the encapsulant.5. The method of claim 1 , wherein forming the channels includes:depositing the encapsulant over the semiconductor die;providing a ...

Semiconductor Device and Method of Forming Vertical Interconnect Structure with Conductive Micro Via Array for 3-D FO-WLCSP

A semiconductor device has a semiconductor die. An encapsulant is formed over the semiconductor die. A conductive micro via array is formed over the encapsulant outside a footprint of the semiconductor die. A first through-mold-hole having a step-through-hole structure is formed through the encapsulant to expose the conductive micro via array. In one embodiment, forming the conductive micro via array further includes forming an insulating layer over the encapsulant and the semiconductor die, forming a micro via array through the insulating layer outside the footprint of the semiconductor die, and forming a conductive layer over the insulating layer. In another embodiment, forming the conductive micro via array further includes forming a conductive ring. In another embodiment, an insulating layer is formed over the semiconductor die for structural support, a build-up interconnect structure is formed over the semiconductor die, and a conductive interconnect structure is formed within the first through-mold-hole. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;forming an encapsulant over the semiconductor die;forming a conductive micro via array over the encapsulant outside a footprint of the semiconductor die; andforming a first through-mold-hole (TMH) having a step-through-hole structure through the encapsulant to expose the conductive micro via array.2. The method of claim 1 , wherein forming the conductive micro via array further includes:forming an insulating layer over the encapsulant and the semiconductor die;forming a micro via array through the insulating layer outside the footprint of the semiconductor die; andforming a conductive layer over the insulating layer.3. The method of claim 1 , wherein forming the conductive micro via array further includes forming a conductive ring.4. The method of claim 1 , wherein forming the first TMH further includes:forming a second TMH partially through the encapsulant to a recessed ...

Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD)

A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first conductive layer over the substrate;forming a first insulating layer over the substrate and first conductive layer;forming a second insulating layer over the first insulating layer;forming a first opening through the second insulating layer to the first insulating layer; andforming a second conductive layer within the first opening over the first insulating layer and separated from the first conductive layer by the first insulating layer.2. The method of claim 1 , further including:forming a second opening through the first and second insulating layers; andforming a third conductive layer within the second opening.3. The method of claim 1 , wherein the second conductive layer claim 1 , first insulating layer claim 1 , and first conductive layer operate as a capacitor.4. The method of claim 1 , further including disposing a resistive layer between the first conductive layer and first insulating layer.5. The method of claim 1 , further including forming an interconnect structure over the second insulating layer.6. The ...

Semiconductor Device and Method of Making Integrated Passive Devices

A semiconductor device has integrated passive circuit elements. A first substrate is formed on a backside of the semiconductor device. The passive circuit element is formed over the insulating layer. The passive circuit element can be an inductor, capacitor, or resistor. A passivation layer is formed over the passive circuit element. A carrier is attached to the passivation layer. The first substrate is removed. A non-silicon substrate is formed over the insulating layer on the backside of the semiconductor device. The non-silicon substrate is made with glass, molding compound, epoxy, polymer, or polymer composite. An adhesive layer is formed between the non-silicon substrate and insulating layer. A via is formed between the insulating layer and first passivation layer. The carrier is removed. An under bump metallization is formed over the passivation layer in electrical contact with the passive circuit element. A solder bump is formed on the under bump metallization. 1. A semiconductor device , comprising:a first substrate;an integrated passive device disposed over the first substrate;a first insulating layer disposed over the integrated passive device and first substrate;a conductive layer formed over the first insulating layer;a second insulating layer formed over the first insulating layer and conductive layer; anda second substrate disposed over the second insulating layer.2. The semiconductor device of claim 1 , wherein the first substrate includes silicon material.3. The semiconductor device of claim 1 , wherein the first substrate includes non-silicon material.4. The semiconductor device of claim 1 , wherein the first substrate is made with a material selected from the group consisting of glass claim 1 , molding compound claim 1 , epoxy claim 1 , polymer claim 1 , and polymer composite.5. The semiconductor device of claim 1 , wherein a portion of the conductive layer is wound to exhibit an inductive property.6. The semiconductor device of claim 1 , wherein ...

Semiconductor Device and Method of Forming Insulating Layer Disposed Over The Semiconductor Die For Stress Relief

A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;forming a first conductive layer over the semiconductor die;depositing an encapsulant around the semiconductor die;forming a first insulating layer over the semiconductor die; andforming an interconnect structure over the first insulating layer and encapsulant, wherein the first insulating layer provides stress relief for the interconnect structure.2. The method of claim 1 , further including:forming a channel in the semiconductor die; andforming the first insulating layer into the channel.3. The method of claim 1 , further including:forming a channel in the encapsulant; andforming the first insulating layer into the channel.4. The method of claim 1 , further including forming a second insulating layer over the semiconductor die prior to forming the first insulating layer.5. The method of claim 1 , further including removing a portion of the first insulating layer by laser direct ablation.6. The method of claim 1 , ...

Semiconductor Device and Method of Forming an Inductor on Polymer Matrix Composite Substrate

A semiconductor device has a first insulating layer formed over a first surface of a polymer matrix composite substrate. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. The second conductive layer is wound to exhibit inductive properties. A third conductive layer is formed between the first conductive layer and second conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. A fourth insulating layer can be formed over a second surface of the polymer matrix composite substrate. Alternatively, the fourth insulating layer can be formed over the first insulating layer prior to forming the first conductive layer. 1. A method of making a semiconductor device , comprising:forming a polymer matrix composite substrate;forming a first insulating layer over a first surface of the polymer matrix composite substrate;forming a first conductive layer over the first insulating layer;forming a second insulating layer over the first insulating layer and first conductive layer;forming a second conductive layer over the second insulating layer and first conductive layer;forming a third insulating layer over the second insulating layer and second conductive layer;removing a portion of the third insulating layer to expose the second conductive layer; andforming a bump over the second conductive layer.2. The method of claim 1 , wherein forming the polymer matrix composite substrate includes:providing a chase mold having first and second plates;applying a first releasable layer over the first plate;forming a metal carrier over the second plate;applying a second releasable layer over the metal carrier; anddepositing an encapsulant material between the first and second plates ...

Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP

A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;depositing an encapsulant over a first surface of the semiconductor die and around the semiconductor die;forming a first insulating layer over a second surface of the semiconductor die opposite the first surface;forming a first conductive layer over the first insulating layer;forming an opening in the encapsulant to expose the first conductive layer; anddepositing a conductive material within the opening.2. The method of claim 1 , further including:forming a second insulating layer over the first conductive layer and first insulating layer;forming a second conductive layer over the first conductive layer and first insulating layer; andforming a third insulating layer over the second conductive layer and second insulating layer.3. The method of claim 2 , wherein the first claim 2 , second claim 2 , or third insulating layer includes a composite material comprising a polymer and a woven glass fiber.4. The method of claim 1 , ...

Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-up Interconnect Structure

A semiconductor device is made by forming an interconnect structure over a substrate. A semiconductor die is mounted to the interconnect structure. The semiconductor die is electrically connected to the interconnect structure. A ground pad is formed over the interconnect structure. An encapsulant is formed over the semiconductor die and interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the interconnect structure to isolate the semiconductor die with respect to inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. A backside interconnect structure is formed over the interconnect structure, opposite the semiconductor die. 1. A method of making a semiconductor device , comprising:providing a first interconnect structure including a ground pad;disposing a semiconductor die over the first interconnect structure; andforming a shielding layer over the semiconductor die and first interconnect structure to isolate the semiconductor die with respect to inter-device interference, the shielding layer being electrically coupled to the ground pad.2. The method of claim 1 , further including depositing an encapsulant over the semiconductor die and first interconnect structure.3. The method of claim 1 , further including disposing a shielding cage over the semiconductor die to isolate the semiconductor die with respect to inter-device interference.4. The method of claim 1 , further including forming a second interconnect structure between the semiconductor die and shielding layer.5. The method of claim 1 , further including forming a second interconnect structure between the first interconnect structure and shielding layer.6. The method of claim 1 , wherein the ground pad includes an ...

Semiconductor Device and Method for Forming a Low Profile Embedded Wafer Level Ball Grid Array Molded Laser Package (EWLP-MLP)

A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;depositing an encapsulant over and around the semiconductor die;forming an interconnect structure over a first surface of the encapsulant;forming an opening from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure; andforming a bump recessed within the opening and disposed over the surface of the interconnect structure.2. The method of claim 1 , further including:providing a semiconductor package; anddisposing the semiconductor package over the second surface of the encapsulant and electrically connecting the semiconductor package to the bump.3. The method of claim 2 , further including forming a plurality of interconnect structures over the semiconductor package to electrically connect the semiconductor package to the bump.4. The method of claim 2 , wherein the semiconductor package includes a memory device.5. The method of claim 2 , wherein the semiconductor device includes a ...

Semiconductor Device and Method for Forming Semiconductor Package Having Build-Up Interconnect Structure Over Semiconductor Die with Different CTE Insulating Layers

A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.

Semiconductor Device and Method for Forming Openings and Trenches in Insulating Layer by First LDA and Second LDA for RDL Formation

A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;depositing an encapsulant over the semiconductor die;forming a first insulating layer over the semiconductor die and encapsulant;removing a first portion of the first insulating layer by a first laser direct ablation to form a plurality of openings in the first insulating layer;removing a second portion of the first insulating layer by a second laser direct ablation to form a plurality of trenches in the first insulating layer;forming a conductive layer in the openings and trenches of the first insulating layer;forming a second insulating layer over the conductive layer; andforming a plurality of bumps over the conductive layer.2. The method of claim 1 , further including removing a portion of the second insulating layer by a third laser direct ablation.3. The method of claim 1 , further including forming the openings partially through the first insulating layer or into the encapsulant.4. The method of claim 1 , further including forming a third insulating layer over the semiconductor die. ...

Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units

A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die. 1. A method of making a semiconductor device , comprising:providing a carrier with a die attach area;mounting a first semiconductor die to the die attach area;mounting a modular interconnect unit over the carrier in a peripheral region around the first semiconductor die;depositing a first encapsulant over the carrier, first semiconductor die, and modular interconnect unit;removing a portion of the first encapsulant to expose the first semiconductor die and modular interconnect unit;removing the carrier; andforming an interconnect structure over the first semiconductor die and modular interconnect unit.2. The method of claim 1 , wherein the modular interconnect unit includes a core with a vertical interconnect structure formed through the core and overlapping the core by 0-200 micrometers.3. The method of claim 2 , wherein the vertical interconnect structure includes an opening filled with a conductive paste or polymer plug.4. The method of claim 1 , wherein the modular interconnect unit is offset from the semiconductor die and ...

Semiconductor Device and Method of Forming Micro-Vias Partially through Insulating Material over Bump Interconnect Conductive Layer for Stress Relief

A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A plurality of first micro-vias can be formed in the first insulating layer. A conductive layer is formed in the first micro-openings and over the first insulating layer. A second insulating layer is formed over the first insulating layer and conductive layer. A portion of the second insulating layer is removed to expose the conductive layer and form a plurality of second micro-openings in the second insulating layer over the conductive layer. The second micro-openings can be micro-vias, micro-via ring, or micro-via slots. Removing the portion of the second insulating layer leaves an island of the second insulating layer over the conductive layer. A bump is formed over the conductive layer. A third insulating layer is formed in the second micro-openings over the bump. The second micro-openings provide stress relief. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;forming a first insulating layer over the semiconductor die;forming a conductive layer over the first insulating layer;forming a second insulating layer over the first insulating layer and conductive layer;removing a portion of the second insulating layer to expose the conductive layer and form a plurality of first micro-vias in the second insulating layer over the conductive layer; andforming a bump over the conductive layer, wherein the first micro-vias provide stress relief.2. The method of claim 1 , wherein removing the portion of the second insulating layer leaves an island of the second insulating layer over the conductive layer.3. The method of claim 1 , further including forming a third insulating layer in the first micro-vias over the bump.4. The method of claim 1 , further including:forming a plurality of second micro-vias in the first insulating layer; andforming the conductive layer over the second micro-vias.5. The method of claim 1 , wherein a ...

Semiconductor Device and Method of Forming a Robust Fan-Out Package including Vertical Interconnects and Mechanical Support Layer

A semiconductor device has a semiconductor die. An encapsulant is deposited around the semiconductor die. An interconnect structure having a conductive bump is formed over the encapsulant and semiconductor die. A mechanical support layer is formed over the interconnect structure and around the conductive bump. The mechanical support layer is formed over a corner of the semiconductor die and over a corner of the interconnect structure. An opening is formed through the encapsulant that extends to the interconnect structure. A conductive material is deposited within the opening to form a conductive through encapsulant via (TEV) that is electrically connected to the interconnect structure. A semiconductor device is mounted to the TEV and over the semiconductor die to form a package-on-package (PoP) device. A warpage balance layer is formed over the encapsulant opposite the interconnect structure.

Semiconductor Device and Method of Forming RDL Wider than Contact Pad Along First Axis and Narrower than Contact Pad along Second Axis

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first conductive layer over the substrate;forming a first insulating layer over the substrate; andforming a second conductive layer over the first conductive layer, the second conductive layer including a width that is less than a width of the first conductive layer along a first axis and a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis.2. The method of claim 1 , further including forming a second insulating layer over the second conductive layer and first insulating layer.3. The method of claim 1 , further including forming a second insulating layer over the substrate prior to forming the first insulating layer.4. The method of claim 1 , wherein the width of the second conductive layer is greater than the width of the first conductive layer along the second axis by 10-20 micrometers.5. The method of claim 1 , wherein the width of the first conductive layer is greater than the width of the second conductive layer along the first axis by 10-20 micrometers.6. The method ...

Semiconductor Method and Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units

A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die. 1. A method of making a semiconductor device , comprising:providing a carrier with a die attach area;mounting a semiconductor die to the die attach area;mounting a modular interconnect unit over the carrier in a peripheral region around the semiconductor die;depositing an encapsulant over the carrier, semiconductor die, and modular interconnect unit;removing a portion of the encapsulant to expose the semiconductor die and modular interconnect unit;removing the carrier; andforming an interconnect structure over the semiconductor die and modular interconnect unit.2. The method of claim 1 , wherein the modular interconnect unit includes a core with a vertical interconnect structure formed through the core and overlapping the core by 0-200 micrometers.3. The method of claim 2 , wherein the vertical interconnect structure includes an opening filled with a conductive paste or polymer plug.4. The method of claim 1 , wherein the modular interconnect unit is offset from the semiconductor die.5. The method of claim 1 , wherein the ...

System-In-Package Having Integrated Passive Devices and Method Therefor

A semiconductor device has a substrate, first passivation layer formed over the substrate, and integrated passive device formed over the substrate. The integrated passive device can include an inductor, capacitor, and resistor. A second passivation layer is formed over the integrated passive device. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive device. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive device. A metal layer can be formed over the molding compound or first passivation layer for shielding. 1. A method of making a semiconductor device , comprising:providing a substrate;disposing a first semiconductor die over the substrate including an active surface oriented toward the substrate;forming an interconnect structure between the first semiconductor die and substrate, wherein the interconnect structure includes a conductive layer which extends outside a footprint of the first semiconductor die; anddisposing a second semiconductor die over the substrate.2. The method of claim 1 , further including depositing an underfill material between the interconnect structure and the substrate.3. The method of claim 1 , further including depositing an encapsulant over the first semiconductor die.4. The method of claim 1 , wherein the second semiconductor die overlaps with the footprint of the first semiconductor die.5. The method of claim 1 , wherein the second semiconductor die includes a radio frequency integrated circuit or a memory integrated circuit.6. The method of claim 1 , further including forming a plurality of bumps on the interconnect ...

Semiconductor Method and Device of Forming a Fan-Out Device with PWB Vertical Interconnect Units

A semiconductor device has a modular interconnect unit or interconnect structure disposed in a peripheral region of the semiconductor die. An encapsulant is deposited over the semiconductor die and interconnect structure. A first insulating layer is formed over the semiconductor die and interconnect structure. A plurality of openings is formed in the first insulating layer over the interconnect structure. The openings have a pitch of 40 micrometers. The openings include a circular shape, ring shape, cross shape, or lattice shape. A conductive layer is deposited over the first insulating layer. The conductive layer includes a planar surface. A second insulating layer is formed over the conductive layer. A portion of the encapsulant is removed to expose the semiconductor die and the interconnect structure. The modular interconnect unit includes a vertical interconnect structure. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.

Semiconductor Device and Method of Forming TSV Semiconductor Wafer with Embedded Semiconductor Die

A semiconductor device has a TSV semiconductor wafer with a cavity formed in a first surface of the wafer. A second cavity can be formed in a second surface of the wafer. A plurality of semiconductor die is mounted within the cavities. The semiconductor die can be mounted side-by-side and/or stacked within the cavity. Conductive TSV can be formed through the die. An encapsulant is deposited within the cavity over the die. A CTE of the die is similar to a CTE of the encapsulant. A first interconnect structure is formed over a first surface of the encapsulant and wafer. A second interconnect structure is formed over a second surface of the encapsulant and wafer. The first and second interconnect structure are electrically connected to the TSV wafer. A second semiconductor die can be mounted over the first interconnect structure with encapsulant deposited over the second die.

Semiconductor Device and Method of Forming Interposer with Opening to Contain Semiconductor Die

A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die. 1. A method of making a semiconductor device , comprising:providing a carrier;forming an interface layer over the carrier;disposing a first substrate over the carrier;disposing a second substrate over the carrier;disposing a first semiconductor die over the first and second substrates electrically connected to the first and second substrates;depositing an encapsulant over the first semiconductor die and over the first and second substrates; andremoving the carrier and interface layer.2. The method of claim 1 , further including forming a plurality of bumps over the first and second substrates.3. The method of claim 1 , wherein disposing the first and second substrates includes simultaneously disposing the first and second substrates over the carrier.4. The method of claim 1 , further including forming an electrical connection between the first and second substrates.5. The method of claim 1 , further including forming an interconnect structure over a surface of the first substrate opposite the first semiconductor die.6. The method of claim 1 , further including ...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUBSTRATE AND METHOD OF MANUFACTURE THEREOF

An integrated circuit packaging system and method of manufacture thereof includes: a substrate having a top insulation layer and a top conductive layer; an inter-react layer on the substrate; an integrated circuit die on the substrate; a package body on the inter-react layer and the integrated circuit die; and a top solder bump on the top conductive layer, the top solder bump in a 3D via formed through the package body, the inter-react layer, and the top insulation layer for exposing the top conductive layer in the 3D via. 1. A method of manufacture of an integrated circuit packaging system comprising:providing an integrated circuit die;encapsulating in a package body the integrated circuit die;applying an inter-react layer on the package body;forming a substrate on the inter-react layer, the substrate having a top insulation layer and a top conductive layer;forming a 3D via through the package body, the inter-react layer, and the top insulation layer for exposing the top conductive layer in the 3D via; anddepositing a top solder bump in the 3D via on the top conductive layer.2. The method as claimed in further comprising applying a warpage balance layer on a top surface of the package body and the integrated circuit die.3. The method as claimed in wherein forming the 3D via through the package body claim 1 , the inter-react layer claim 1 , and the top insulation layer for exposing the top conductive layer in the 3D via includes:forming a recess in the package body with an IR laser; andforming a hole through a remaining portion of the package body, the inter-react layer, and the top insulation layer with a UV laser for exposing the top conductive layer.4. The method as claimed in further comprising attaching bottom connectors to the substrate.5. The method as claimed in wherein forming the 3D via includes forming the 3D via with a sidewall having a stepped multi-slope shape.6. A method of manufacture of an integrated circuit packaging system comprising:providing an ...

Semiconductor Device and Method of Forming an Embedded SOP Fan-Out Package

A semiconductor device includes a ball grid array (BGA) package including first bumps. A first semiconductor die is mounted to the BGA package between the first bumps. The BGA package and first semiconductor die are mounted to a carrier. A first encapsulant is deposited over the carrier and around the BGA package and first semiconductor die. The carrier is removed to expose the first bumps and first semiconductor die. An interconnect structure is electrically connected to the first bumps and first semiconductor die. The BGA package further includes a substrate and a second semiconductor die mounted, and electrically connected, to the substrate. A second encapsulant is deposited over the second semiconductor die and substrate. The first bumps are formed over the substrate opposite the second semiconductor die. A warpage balance layer is formed over the BGA package. 1. A method of making a semiconductor device , comprising:providing a ball grid array (BGA) package including first bumps;disposing a first semiconductor die over the BGA package between the first bumps;disposing the BGA package and first semiconductor die over a carrier;depositing a first encapsulant over the carrier and around the BGA package and first semiconductor die;removing the carrier to expose the first bumps and first semiconductor die; andforming a fan-out interconnect structure over and electrically connected to the first bumps and first semiconductor die.2. The method of claim 1 , wherein providing the BGA package further includes:providing a substrate;disposing a second semiconductor die over the substrate;electrically connecting the second semiconductor die to the substrate;depositing a second encapsulant over the second semiconductor die and substrate; andforming the first bumps over the substrate opposite the second semiconductor die.3. The method of claim 1 , wherein the first semiconductor die includes a height less than a height of the first bumps.4. The method of claim 1 , further ...

Semiconductor Device Having Balanced Band-Pass Filter Implemented with LC Resonators

A band-pass filter has a plurality of frequency band channels each including a first inductor having a first terminal coupled to a first balanced port and a second terminal coupled to a second balanced port. A first capacitor is coupled between the first and second terminals of the first inductor. A second inductor has a first terminal coupled to a first unbalanced port and a second terminal coupled to a second unbalanced port. The second inductor is disposed within a first distance of the first inductor to induce magnetic coupling. A second capacitor is coupled between the first and second terminals of the second inductor. A third inductor is disposed within a second distance of the first inductor and within a third distance of the second inductor to induce magnetic coupling. A second capacitor is coupled between first and second terminals of the third inductor. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first inductor over the substrate;forming a second inductor over the substrate; andforming a third inductor over the substrate adjacent to the first inductor and second inductor to induce magnetic coupling between the first, second, and third inductors, wherein the first inductor and second inductor are substantially coplanar.2. The method of claim 1 , further including:providing a first capacitor coupled between first and second end terminals of the first inductor; andproviding a second capacitor coupled between first and second end terminals of the second inductor.3. The method of claim 1 , further including providing a capacitor coupled between first and second end terminals of the third inductor.4. The method of claim 1 , further including forming the first inductor adjacent to and non-overlapping with the second inductor.5. The method of claim 1 , further including forming the third inductor non-overlapping with the first inductor and second inductor.6. The method of claim 1 , further including forming the third ...

Semiconductor Device and Method of Forming Vertical Interconnect Structure with Conductive Micro Via Array for 3-D FO-WLCSP

A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. A conductive micro via array is formed outside a footprint of the semiconductor die and over the semiconductor die and encapsulant. A first through-mold-hole (TMH) is formed including a step-through-hole structure through the encapsulant to expose the conductive micro via array. An insulating layer is formed over the semiconductor die and the encapsulant. A micro via array is formed through the insulating layer and outside the footprint of the semiconductor die. A conductive layer is formed over the insulating layer. A conductive ring is formed comprising the conductive micro via array. A second TMH is formed partially through the encapsulant to a recessed surface of the encapsulant. A third TMH is formed through the encapsulant and extending from the recessed surface of the encapsulant to the conductive micro via array. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;depositing an encapsulant over the semiconductor die;forming a conductive micro via array outside a footprint of the semiconductor die and over the semiconductor die and encapsulant; andforming a first through-mold-hole (TMH) through the encapsulant to expose the conductive micro via array.2. The method of claim 1 , wherein forming the conductive micro via array includes:forming an insulating layer over the semiconductor die and the encapsulant;forming a micro via array through the insulating layer and outside the footprint of the semiconductor die; andforming a conductive layer over the insulating layer.3. The method of claim 1 , further including forming a conductive ring comprising the conductive micro via array.4. The method of claim 1 , further including:forming a second TMH partially through the encapsulant to a recessed surface of the encapsulant; andforming a third TMH through the encapsulant within a footprint of the second TMH having a cross- ...

Semiconductor Device and Method of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units

A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters. 1. A method of making a semiconductor device , comprising:providing a semiconductor package including a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die;providing an interposer;disposing the interposer over the semiconductor package;providing a second semiconductor die; anddisposing the second semiconductor die over the interposer opposite the semiconductor package.2. The method of claim 1 , further including forming an interconnect structure between the interposer and the modular interconnect unit.3. The method of claim 2 , wherein the interconnect structure includes a conductive pillar or stud bump.4. The method of claim 1 , further including forming the modular interconnect unit of the semiconductor package by:providing a core substrate; andforming a plurality of vertical interconnects through the core substrate.5. The method of claim 4 , further including exposing the ...

Semiconductor Device and Method of Forming Thick Encapsulant for Stiffness with Recesses for Stress Relief in FO-WLCSP

A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device. 1. A method of making a semiconductor device , comprising:providing a first semiconductor die;depositing an encapsulant over the semiconductor die;forming a recess in the encapsulant;forming an interconnect structure over the semiconductor die; andremoving a first portion of the encapsulant.2. The method of claim 1 , wherein forming the recess further includes removing a second portion of the encapsulant while leaving the first portion of the encapsulant.3. The method of claim 1 , further including:disposing a support structure within the recess prior to forming the interconnect structure; andremoving the support structure after forming the interconnect structure.4. The method of claim 1 , further including forming the recess over the first semiconductor die and outside a footprint of the semiconductor die.5. The method of claim 1 , further including:providing a second semiconductor die; andforming the recess over the first and second semiconductor die.6. The method of claim 1 , further including disposing a support member ...

Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over Carrier for Testing at Interim Stages

A semiconductor device has a first interconnect structure formed over the carrier. A semiconductor die is disposed over the first interconnect structure after testing the first interconnect structure to be known good. The semiconductor die in a known good die. A vertical interconnect structure, such as a bump or stud bump, is formed over the first interconnect structure. A discrete semiconductor device is disposed over the first interconnect structure or the second interconnect structure. An encapsulant is deposited over the semiconductor die, first interconnect structure, and vertical interconnect structure. A portion of the encapsulant is removed to expose the vertical interconnect structure. A second interconnect structure is formed over the encapsulant and electrically connected to the vertical interconnect structure. The first interconnect structure or the second interconnect structure includes an insulating layer with an embedded glass cloth, glass cross, filler, or fiber. 1. A method of making a semiconductor device , comprising:providing a carrier;forming a first interconnect structure over the carrier;testing the first interconnect structure;disposing a semiconductor die over the first interconnect structure after testing the first interconnect structure;forming a vertical interconnect structure over the first interconnect structure;depositing an encapsulant over the semiconductor die, first interconnect structure, and vertical interconnect structure; andforming a second interconnect structure over the encapsulant and electrically coupled to the vertical interconnect structure.2. The method of claim 1 , further including disposing a discrete semiconductor device over the first interconnect structure or the second interconnect structure.3. The method of claim 1 , further including removing a portion of the encapsulant to expose the vertical interconnect structure.4. The method of claim 1 , wherein the first interconnect structure or second interconnect ...

Semiconductor Device and Method of Forming Dual-Sided Interconnect Structures in FO-WLCSP

A semiconductor device has a substrate with first and second conductive layers formed over first and second opposing surfaces of the substrate. A plurality of bumps is formed over the substrate. A semiconductor die is mounted to the substrate between the bumps. An encapsulant is deposited over the substrate and semiconductor die. A portion of the bumps extends out from the encapsulant. A portion of the encapsulant is removed to expose the substrate. An interconnect structure is formed over the encapsulant and semiconductor die and electrically coupled to the bumps. A portion of the substrate can be removed to expose the first or second conductive layer. A portion of the substrate can be removed to expose the bumps. The substrate can be removed and a protection layer formed over the encapsulant and semiconductor die. A semiconductor package is disposed over the substrate and electrically connected to the substrate. 1. A method of making a semiconductor device , comprising:providing a substrate including first and second conductive layers formed over first and second opposing surfaces of the substrate;forming a plurality of bumps over the substrate;mounting a semiconductor die to the substrate between the bumps;depositing an encapsulant over the substrate and semiconductor die; andforming an interconnect structure over the encapsulant and semiconductor die and electrically coupled to the bumps.2. The method of claim 1 , further including:forming a first insulating layer over the first surface of the substrate and the first conductive layer; andforming a second insulating layer over the second surface of the substrate and the second conductive layer.3. The method of claim 2 , further including removing a portion of the first insulating layer or second insulating layer by laser direct ablation.4. The method of claim 1 , further including removing a portion of the encapsulant to expose the substrate.5. The method of claim 1 , wherein a portion of the bumps extends out ...

Semiconductor Device and Method of Forming Dual-Sided Interconnect Structures in Fo-WLCSP

A semiconductor device has a substrate including first and second conductive layers formed over first and second opposing surfaces of the substrate. A plurality of wire studs or stud bumps is formed over the substrate. A semiconductor die is mounted to the substrate between the wire studs. A first encapsulant is deposited around the semiconductor die. A first interconnect structure is formed over the semiconductor die and first encapsulant. A second encapsulant is deposited over the substrate, semiconductor die, and first interconnect structure. The second encapsulant can be formed over a portion of the semiconductor die and side surface of the substrate. A portion of the second encapsulant is removed to expose the substrate and first interconnect structure. A second interconnect structure is formed over the second encapsulant and first interconnect structure and electrically coupled to the wire studs. A discrete semiconductor device can be formed on the interconnect structure. 1. A method of making a semiconductor device , comprising:providing a substrate including first and second conductive layers formed over first and second opposing surfaces of the substrate;forming a plurality of wire studs over the substrate;mounting a semiconductor die to the substrate between the wire studs;forming a first interconnect structure over the semiconductor die;depositing a first encapsulant over the substrate, semiconductor die, and first interconnect structure; andforming a second interconnect structure over the first encapsulant and first interconnect structure and electrically coupled to the wire studs.2. The method of claim 1 , further including:forming a second encapsulant around the semiconductor die; andforming the first interconnect structure over the semiconductor die and second encapsulant.3. The method of claim 1 , further including removing a portion of the first encapsulant to expose the first interconnect structure.4. The method of claim 1 , further including ...

Semiconductor Device and Method of Forming Wire Studs as Vertical Interconnect in FO-WLP

A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate. 1. A method of making a semiconductor device , comprising:providing a substrate;disposing a semiconductor die over a first surface of the substrate;attaching a wire stud to the first surface of the substrate;depositing an encapsulant over the substrate, semiconductor die, and wire stud; andforming an interconnect structure over the encapsulant and electrically connected to the wire stud.2. The method of claim 1 , further including removing a portion of the encapsulant to expose the wire stud.3. The method of claim 1 , further including removing a portion of the encapsulant to expose the substrate.4. The method of claim 1 , further including removing a portion of the encapsulant by laser direct ablation.5. The method of claim 1 , further including forming a bonding pad over a second surface of the substrate opposite the first surface of the substrate.6. The method of claim 1 , further including disposing a semiconductor package over the semiconductor die and electrically connected to the substrate.7. A method of making a semiconductor device claim 1 , comprising:providing a ...

Semiconductor Device and Method of Forming FO-WLCSP with Multiple Encapsulants

A semiconductor device has a first semiconductor die including TSVs mounted to a carrier with a thermally releasable layer. A first encapsulant having a first coefficient of thermal expansion CTE is deposited over the first semiconductor die. The first encapsulant includes an elevated portion in a periphery of the first encapsulant that reduces warpage. A surface of the TSVs is exposed. A second semiconductor die is mounted to the surface of the TSVs and forms a gap between the first and second semiconductor die. A second encapsulant having a second CTE is deposited over the first and second semiconductor die and within the gap. The first CTE is greater than the second CTE. In one embodiment, the first and second encapsulants are formed in a chase mold. An interconnect structure is formed over the first and second semiconductor die.

Semiconductor Device and Method of Using Substrate Having Base and Conductive Posts to Form Vertical Interconnect Structure in Embedded Die Package

A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. The substrate can be a wafer-shape, panel, or singulated form. The conductive posts can have a circular, rectangular, tapered, or narrowing intermediate shape. A semiconductor die is disposed through an opening in the base between the conductive posts. The semiconductor die extends above the conductive posts or is disposed below the conductive posts. An encapsulant is deposited over the semiconductor die and around the conductive posts. The base and a portion of the encapsulant is removed to electrically isolate the conductive posts. An interconnect structure is formed over the semiconductor die, encapsulant, and conductive posts. An insulating layer is formed over the semiconductor die, encapsulant, and conductive posts. A semiconductor package is disposed over the semiconductor die and electrically connected to the conductive posts. 1. A method of making a semiconductor device , comprising:providing a substrate including a base and a plurality of conductive posts extending from the base;disposing a semiconductor die through an opening in the base between the conductive posts;depositing an encapsulant over the semiconductor die and around the conductive posts; andremoving the base to electrically isolate the conductive posts.2. The method of claim 1 , further including forming an interconnect structure over the semiconductor die claim 1 , encapsulant claim 1 , and conductive posts.3. The method of claim 1 , further including forming an insulating layer over the semiconductor die claim 1 , encapsulant claim 1 , and conductive posts.4. The method of claim 1 , wherein the base of the substrate includes a notch.5. The method of claim 1 , wherein the semiconductor die extends above the conductive posts.6. The method of claim 1 , further including disposing the semiconductor die below the conductive posts.7. A method of making a semiconductor device claim ...

Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution Layer

A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;forming a first inductor over the semiconductor die; andforming a second inductor over the first inductor.2. The method of claim 1 , wherein a portion of the first inductor is coupled to the semiconductor die.3. The method of claim 1 , further including forming the first and second inductors within a footprint of the semiconductor die.4. The method of claim 1 , further including forming an insulating layer over the semiconductor die with a first thickness outside a footprint of the semiconductor die and a second thickness greater than the first thickness over the footprint of the semiconductor die.5. The method of claim 1 , further including forming the second inductor to align with the first inductor.6. The method of claim 1 , further including disposing an encapsulant over the semiconductor die.7. A method of making a semiconductor device claim 1 , comprising:providing a substrate;disposing a first conductive layer over the substrate to form a passive device; andforming a second conductive ...

Semiconductor Device with Protective Structure Around Semiconductor Die for Localized Planarization of Insulating Layer

A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die. 1. A semiconductor device , comprising:a semiconductor die;a conductive layer formed over a surface of the semiconductor die;a protective pattern formed over the surface of the semiconductor die and separated from the conductive layer; anda first insulating layer formed over the surface of the semiconductor die, wherein the protective pattern maintains the first insulating layer between the conductive layer and protective pattern.2. The semiconductor device of claim 1 , further including an exposed portion of the conductive layer claim 1 , wherein the protective pattern reduces erosion of the first insulating layer adjacent to the conductive layer.3. The semiconductor device of claim 1 , wherein the protective pattern includes a metal layer.4. The semiconductor device of claim 1 , wherein the protective pattern is segmented.5. The semiconductor device of claim 1 , further including an encapsulant formed over the semiconductor die.6. The semiconductor device of claim 1 , further including a second insulating layer formed over the surface of the semiconductor die with an opening to the ...

Semiconductor Device and Method of Forming Supporting Layer Over Semiconductor Die in Thin Fan-Out Wafer Level Chip Scale Package

A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer an includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers (μm). The thickness of the semiconductor die is at least 1 μm less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;forming an encapsulant around the semiconductor die;forming a build-up interconnect structure over a first surface of the semiconductor die and encapsulant;forming a first supporting layer over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure; andforming a second supporting layer over the first supporting layer.2. The method of claim 1 , further including forming the second supporting layer to comprise a fiber enhanced polymer composite material including a footprint comprising an area greater than an area of a footprint of the semiconductor die.3. The method of claim 1 , further including forming the first supporting layer to comprise a footprint including an area equal to an area of a footprint of the semiconductor die and further include a coefficient of thermal expansion less than 10 ppm/K.4. The method of claim 1 , further including forming the first supporting layer to ...

Semiconductor Device and Method of Depositing Encapsulant Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSP

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer including a plurality of semiconductor die;forming an insulating layer over the semiconductor wafer;removing a portion of the insulating layer to expose a portion of an active surface of the semiconductor die;singulating the semiconductor wafer to separate the semiconductor die; anddepositing an encapsulant over the semiconductor die to cover a side of the semiconductor die and the exposed portion of the active surface of the semiconductor die.2. The method of claim 1 , further including:providing a carrier;disposing the semiconductor die over the carrier with the active surface of the semiconductor die offset from the carrier;depositing the encapsulant over the semiconductor die and carrier to cover the side of the semiconductor die and the exposed portion of the active surface of the semiconductor die; andremoving the carrier.3. The method of claim 1 , further including forming a conductive layer over a contact pad on the active surface of the semiconductor die.4. The ...

Semiconductor Device and Method of Forming Low Profile 3D Fan-Out Package

A semiconductor device includes a substrate having an insulating layer and a conductive layer embedded in the insulating layer. The conductive layer is patterned to form conductive pads or conductive pillars. The substrate includes a first encapsulant formed over the conductive layer. A first opening is formed through insulating layer and first encapsulant using a stamping process or laser direct ablation. The substrate is separated into individual units, which are mounted to a carrier. A semiconductor die is disposed in the first opening in the substrate. A second encapsulant is deposited over the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and substrate. An opening is formed through the second encapsulant and through the insulating layer to expose the conductive layer. A bump is formed in the second opening over the conductive layer outside a footprint of the semiconductor die. 1. A method of making a semiconductor device , comprising:providing a substrate including a first insulating layer and a conductive layer embedded in the first insulating layer and a first opening extending completely through the substrate;disposing a first semiconductor die within the first opening of the substrate;depositing an encapsulant over the first semiconductor die and substrate; andforming a second opening through the encapsulant and substrate extending to the conductive layer.2. The method of claim 1 , further including forming an interconnect structure over the first semiconductor die and substrate.3. The method of claim 1 , further including forming a bump within the second opening over the conductive layer.4. The method of claim 1 , further including removing a portion of the first semiconductor die and encapsulant.5. The method of claim 1 , wherein providing the substrate further includes:forming a bump over the conductive layer; andforming the first insulating layer over the conductive layer and the bump.6. The method of ...

Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate

A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first interconnect structure over the substrate;disposing a first semiconductor die over the first interconnect structure;disposing the substrate over a carrier with the first semiconductor die oriented away from the carrier;depositing an encapsulant over the carrier, substrate, and first semiconductor die;forming a second interconnect structure over the encapsulant and semiconductor die; andremoving the substrate to expose the first interconnect structure after forming the second interconnect structure.2. The method of claim 1 , further including forming a conductive column over the first interconnect structure.3. The method of claim 2 , wherein the conductive column extends from the first interconnect structure to the second interconnect structure ...

Semiconductor Device and Method of Forming Encapsulated Wafer Level Chip Scale Package (EWLCSP)

A semiconductor device has a semiconductor die and an encapsulant around the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The fan-in interconnect structure includes an insulating layer and a conductive layer formed over the semiconductor die. The conductive layer remains within a footprint of the semiconductor die. A portion of encapsulant is removed from over the semiconductor die. A backside protection layer is formed over a non-active surface of the semiconductor die after depositing the encapsulant. The backside protection layer is formed by screen printing or lamination. The backside protection layer includes an opaque, transparent, or translucent material. The backside protection layer is marked for alignment using a laser. A reconstituted panel including the semiconductor die is singulated through the encapsulant to leave encapsulant disposed over a sidewall of the semiconductor die. 1. A semiconductor device , comprising:a semiconductor die;an encapsulant deposited around the semiconductor die, wherein the encapsulant is disposed on a side surface of the semiconductor die;a first insulating layer formed over a first surface of the semiconductor die; anda fan-in interconnect structure formed over the semiconductor die and first insulating layer.2. The semiconductor device of claim 1 , wherein a thickness of the encapsulant disposed over a side surface of the semiconductor die is less than 100 micrometers.3. The semiconductor device of claim 1 , wherein the fan-in interconnect structure includes:a conductive layer formed over the semiconductor die and first insulating layer; anda second insulating layer formed over the conductive layer, and terminating within a footprint of the semiconductor die.4. The semiconductor device of claim 3 , wherein the conductive layer and second insulating layer are offset inwards from the side surface of the ...

Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During Singulation

A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;forming a protective layer over the semiconductor die;removing the protective layer; andforming an interconnect structure over the semiconductor die.2. The method of claim 1 , further including forming an insulating layer including a non-planar surface over the semiconductor die.3. The method of claim 1 , further including depositing an encapsulant over the semiconductor die.4. The method of claim 3 , further including forming a first cavity in the encapsulant around the semiconductor die.5. The method of claim 4 , further including disposing an insulating layer in the first cavity.6. The method of claim 5 , further including forming a second cavity in the insulating layer.7. A method of making a semiconductor device claim 5 , comprising:providing a semiconductor die;forming a protective layer over the semiconductor die;depositing an encapsulant over the semiconductor die; andforming a first cavity in the encapsulant adjacent ...

Semiconductor Device and Method of Depositing Encapsulant Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSP

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface. 1. A method of making a semiconductor device , comprising:providing a substrate;disposing a semiconductor die over the substrate;depositing a first encapsulant over the substrate and semiconductor die; andsingulating the first encapsulant.2. The method of claim 1 , further including:depositing a second encapsulant over the semiconductor die; andsingulating the second encapsulant and substrate prior to depositing the first encapsulant.3. The method of claim 2 , further including depositing the second encapsulant between the semiconductor die and substrate.4. The method of claim 1 , further including removing a portion of the first encapsulant to form a recess in the first encapsulant adjacent to the substrate prior to singulating the first encapsulant.5. The method of claim 4 , further including removing the portion of the first encapsulant using laser direct ablation (LDA).6. The method of claim 1 , further including depositing a mold underfill between the semiconductor die and substrate.7. The method of claim 1 , further including disposing an interconnect ...

Semiconductor Device and Method of Forming Wafer-Level Interconnect Structures with Advanced Dielectric Characteristics

A semiconductor device has a build-up interconnect structure including a first insulating layer with a first material and a second insulating layer with a second material. A first conductive layer is formed over the first insulating layer, and the second insulating layer is formed over the first conductive layer. An optional third insulating layer has the second material and is formed over the second insulating layer. A fourth insulating layer has the first material and is formed over the third insulating layer. The second, third, and fourth insulating layers are cured sequentially or simultaneously. The first material includes a greater tensile strength, elastic modulus, and CTE than the second material. The build-up interconnect structure is formed over a semiconductor wafer or semiconductor die in a reconstituted panel. Alternatively, the build-up interconnect structure is formed over a carrier and a semiconductor die is mounted over the build-up interconnect structure. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;depositing an encapsulant over the semiconductor die;forming a first insulating layer including a first material over the semiconductor die and encapsulant;forming a first conductive layer over the first insulating layer;forming a second insulating layer including a second material over the first insulating layer and first conductive layer, the second material different from the first material; andforming a third insulating layer including the first material over the second insulating layer.2. The method of claim 1 , further including:disposing a modular interconnect unit adjacent to the semiconductor die; andforming the first insulating layer over the modular interconnect unit.3. The method of claim 1 , further including curing the second insulating layer prior to forming the third insulating layer.4. The method of claim 1 , further including:forming a second conductive layer over the second insulating layer; ...

Antenna in Embedded Wafer-Level Ball-Grid Array Package

A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant. 1. A method of making a semiconductor device , comprising:providing a substrate;forming an antenna over the substrate;forming a ground plane over the substrate opposite the antenna;disposing a semiconductor die adjacent to the substrate; anddepositing an encapsulant over the substrate and semiconductor die.2. The method of claim 1 , further including:providing a dummy die;forming a conductive layer on the dummy die; anddisposing the dummy die over the semiconductor die prior to depositing the encapsulant.3. The method of claim 2 , further including removing the dummy die by backgrinding the dummy die and encapsulant.4. The method of claim 1 , further including forming a conductive layer to electrically couple the antenna to the semiconductor die.5. The method of claim 1 , further including forming the ground plane and the antenna over the substrate prior to depositing the encapsulant.6. The method of claim 1 , further including forming a conductive bump on the ground plane.7. The method of claim 1 , wherein the substrate includes a conductive via between the antenna and semiconductor die.8. A method of making ...

Semiconductor Device and Method of Forming PoP Semiconductor Device with RDL Over Top Package

A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.

Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units

A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a plurality of conductive vias through the substrate;forming a plurality of bumps over the substrate;disposing a first semiconductor die over the substrate;depositing an encapsulant over the first semiconductor die and the bumps;removing a portion of the encapsulant to expose the bumps; anddisposing a second semiconductor die over the first semiconductor die.2. The method of claim 1 , further including forming a conductive layer and an insulating layer over the substrate.3. The method of claim 1 , further including removing a portion of the substrate to expose the conductive vias.4. The method of claim 1 , wherein a height of the bumps is less than a height of the first semiconductor die.5. The method of claim 1 , further including disposing a third semiconductor die over the substrate between the bumps.6. The method of claim 1 , wherein removing the portion of the encapsulant includes:removing a first portion of the encapsulant from ...

Semiconductor Device and Method of Forming Thermal Lid for Balancing Warpage and Thermal Management

A semiconductor device has a first semiconductor die and an encapsulant deposited over the first semiconductor die. An interconnect structure is formed over the first semiconductor die and encapsulant. A thermal interface material is formed over the first semiconductor die and encapsulant. A stiffening layer is formed over the first semiconductor die and an edge portion of the encapsulant. Alternatively, an insulating layer is formed adjacent to the first semiconductor die and a stiffening layer is formed over the insulating layer. The stiffening layer includes metal, ferrite, ceramic, or semiconductor material. A heat spreader is disposed over the first semiconductor die and a central portion of the encapsulant. Openings are formed in the heat spreader. A recess is formed in the heat spreader along an edge of the heat spreader. A coefficient of thermal expansion (CTE) of the stiffening layer is less than a CTE of the heat spreader. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;depositing an encapsulant over the semiconductor die;forming a stiffening layer over the semiconductor die and encapsulant; andforming a heat spreader over the semiconductor die.2. The method of claim 1 , further including forming the stiffening layer over an edge portion of the encapsulant.3. The method of claim 1 , further including forming the heat spreader over a central portion of the encapsulant.4. The method of claim 1 , further including forming an interconnect structure over the semiconductor die and encapsulant.5. The method of claim 1 , further including forming a recess in the heat spreader claim 1 , the recess disposed along an edge of the heat spreader.6. The method of claim 1 , further including:forming an opening in the stiffening layer; anddisposing the heat spreader within the opening in the stiffening layer.7. A method of making a semiconductor device claim 1 , comprising:providing a first semiconductor die;depositing an encapsulant ...

Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP

A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

Semiconductor Device and Method of Forming Through Mold Hole with Alignment and Dimension Control

A semiconductor device includes a semiconductor die and an encapsulant formed over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A plurality of conductive vias is formed through the first insulating layer. A conductive pad is formed over the encapsulant. An interconnect structure is formed over the semiconductor die and encapsulant. A first opening is formed in the encapsulant to expose the conductive vias. The conductive vias form a conductive via array. The conductive via array is inspected through the first opening to measure a dimension of the first opening and determine a position of the first opening. The semiconductor device is adjusted based on a position of the conductive via array. A conductive material is formed in the first opening over the conductive via array. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;depositing an encapsulant over a first surface of the semiconductor die and around the semiconductor die;forming a first insulating layer over a second surface of the semiconductor die opposite the first surface;forming a plurality of conductive vias through the first insulating layer; andforming a first opening in the encapsulant to expose the conductive vias.2. The method of claim 1 , further including forming an interconnect structure over the semiconductor die and encapsulant.3. The method of claim 1 , further including forming a conductive bump within the first opening.4. The method of claim 1 , further including:inspecting the conductive vias through the first opening; andadjusting the semiconductor device based on a position of the conductive vias.5. The method of claim 1 , further including inspecting the conductive vias through the first opening to measure a dimension of the first opening.6. The method of claim 1 , further including determining a position of the ...

Antenna In Embedded Wafer-Level Ball-Grid Array Package

A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;depositing an encapsulant over the semiconductor die;forming a first conductive layer including an antenna over a first surface of the encapsulant; andforming a second conductive layer including a ground plane over a second surface of the encapsulant, wherein the antenna is located within a footprint of the ground plane.2. The method of claim 1 , further including:disposing a dummy die on the semiconductor die; anddepositing the encapsulant over the dummy die.3. The method of claim 1 , further including disposing a conductive via adjacent to the semiconductor die.4. The method of claim 3 , further including coupling the antenna to the semiconductor die through the conductive via.5. The method of claim 3 , further including forming the antenna with the conductive via between the antenna and semiconductor die.6. The method of claim 1 , further including forming a third conductive layer over the second surface of the encapsulant.7. A method of making a semiconductor device claim 1 , comprising:providing a semiconductor die; ...

Semiconductor Device and Method of Forming Microelectromechanical Systems (MEMS) Package

A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure. 1. A method of making a semiconductor device , comprising:providing a first semiconductor die;disposing a modular interconnect structure adjacent to the first semiconductor die;depositing a first encapsulant between the first semiconductor die and modular interconnect structure; anddisposing a second semiconductor die including a microelectromechanical device over the first semiconductor die.2. The method of claim 1 , further including disposing the second semiconductor die over the first semiconductor die with an exposed back surface of the second semiconductor die oriented away from the first semiconductor die.3. The method of claim 1 , further including depositing a second encapsulant over the second semiconductor die prior to disposing the second semiconductor die over the first semiconductor die.4. The method of claim 3 , further including forming a build-up interconnect structure over the second semiconductor die and ...

Semiconductor Device and Method for Forming Openings and Trenches in Insulating Layer by First LDA and Second LDA for RDL Formation

A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.

Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die Having Pre-Applied Protective Layer

A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units

A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die. 1. A semiconductor device , comprising:a substrate including a conductive via formed through the substrate;a modular interconnect unit including a vertical interconnect structure disposed over the substrate;a first semiconductor die disposed over the substrate adjacent to the modular interconnect unit; andan encapsulant deposited around the first semiconductor die and over modular interconnect unit with an opening in the encapsulant extending to the modular interconnect unit.2. The semiconductor device of claim 1 , further including a second semiconductor die disposed over the first semiconductor die with a bump of the second semiconductor die within the opening of the encapsulant to contact the vertical interconnect structure.3. The semiconductor device of claim 1 , further including a first interconnect structure disposed between the substrate and modular interconnect unit.4. The semiconductor device of claim 3 , further including a second interconnect structure disposed between the first interconnect structure and ...

Double-Sided Semiconductor Package and Dual-Mold Method of Making Same

A semiconductor device comprises a first conductive layer formed on a carrier over an insulating layer. A portion of the insulating layer is removed prior to forming the first conductive layer. A first semiconductor die is disposed over the first conductive layer. A discrete electrical component is disposed over the first conductive layer adjacent to the first semiconductor die. A first encapsulant is deposited over the first conductive layer and first semiconductor layer. A conductive pillar is formed through the first encapsulant between the first conductive layer and second conductive layer. A second encapsulant is deposited around the first encapsulant, first conductive layer, and first semiconductor die. A second conductive layer is formed over the first semiconductor die, first encapsulant, and second encapsulant opposite the first conductive layer. The carrier is removed after forming the second conductive layer. A semiconductor package is mounted to the first conductive layer. 1. A semiconductor device , comprising:a first conductive layer;a semiconductor die disposed over the first conductive layer;a conductive pillar formed over the first conductive layer;a first encapsulant deposited over the first conductive layer and semiconductor die;a second encapsulant deposited around the first encapsulant, first conductive layer, and semiconductor die; anda second conductive layer formed over the semiconductor die, first encapsulant, and second encapsulant opposite the first conductive layer, wherein the conductive pillar extends through the first encapsulant between the first conductive layer and second conductive layer.2. The semiconductor device of claim 1 , wherein the first conductive layer is formed over a carrier.3. The semiconductor device of claim 1 , wherein the first conductive layer is formed over an insulating layer.4. The semiconductor device of claim 3 , wherein the insulating layer includes an opening and the first conductive layer extends into the ...

Semiconductor Device with Encapsulant Deposited Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSP

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;forming a redistribution layer over the semiconductor die; anddepositing an encapsulant over the semiconductor die and redistribution layer after forming the redistribution layer.2. The method of claim 1 , further including depositing the encapsulant over a side surface of the semiconductor die.3. The method of claim 1 , further including depositing the encapsulant over a back surface of the semiconductor die.4. The method of claim 1 , further including disposing a solder bump on the redistribution layer after depositing the encapsulant.5. The method of claim 1 , further including:disposing the semiconductor die on a carrier with the redistribution layer oriented toward the carrier; anddepositing the encapsulant over the semiconductor die and carrier.6. The method of claim 1 , further including singulating through the encapsulant to form a wafer-level chip scale package including the semiconductor die.7. A method of making a semiconductor device claim 1 , comprising:providing ...

Semiconductor Device and Method of Forming Dual Fan-Out Semiconductor Package

A semiconductor device has a semiconductor die with a first encapsulant disposed over the semiconductor die. A first build-up interconnect structure is formed over the semiconductor die and first encapsulant. The first build-up interconnect structure has a first conductive layer. The first conductive layer includes a plurality of first conductive traces. A second encapsulant is disposed over the semiconductor die and the first build-up interconnect structure. A second build-up interconnect structure is formed over the first build-up interconnect structure and the second encapsulant. The second build-up interconnect structure has a second conductive layer. The second conductive layer includes a plurality of second conductive traces. A distance between the second conductive traces is greater than a distance between the first conductive traces. A passive device is disposed within the first encapsulant and/or the second encapsulant. A plurality of conductive vias is disposed in the first encapsulant and/or the second encapsulant. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;disposing a first encapsulant over the semiconductor die;forming a first conductive layer including a plurality of first conductive traces over the semiconductor die and the first encapsulant;disposing a second encapsulant over the semiconductor die; andforming a second conductive layer including a plurality of second conductive traces over the first conductive layer and the second encapsulant, wherein a distance between the second conductive traces is greater than a distance between the first conductive traces.2. The method of claim 1 , further including disposing a plurality of conductive vias adjacent to the semiconductor die.3. The method of claim 1 , further including disposing a passive device adjacent to the semiconductor die.4. The method of claim 1 , further including disposing a plurality of conductive vias adjacent to the first encapsulant.5. The ...

Semiconductor Device and Method of Controlling Warpage in Reconstituted Wafer

A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality of semiconductor die is disposed over a portion of the substrate while leaving an open area of the substrate devoid of the semiconductor die. The open area of the substrate devoid of the semiconductor die includes a central area or interstitial locations among the semiconductor die. The semiconductor die are disposed around a perimeter of the substrate. An encapsulant is deposited over the semiconductor die and substrate. The substrate is removed and an interconnect structure is formed over the semiconductor die. By leaving the predetermined areas of the substrate devoid of semiconductor die, the warping effect of any mismatch between the CTE of the semiconductor die and the CTE of the encapsulant on the reconstituted wafer after removal of the substrate is reduced. 1. A method of making a semiconductor device , comprising:providing a plurality of semiconductor die;providing a substrate;disposing the semiconductor die over a portion of the substrate while leaving a predetermined area of the substrate devoid of the semiconductor die; anddepositing an encapsulant over the semiconductor die and substrate.2. The method of claim 1 , wherein the predetermined area of the substrate devoid of the semiconductor die includes a central area of the substrate.3. The method of claim 1 , wherein the predetermined area of the substrate devoid of the semiconductor die includes interstitial locations among the semiconductor die.4. The method of claim 1 , further including disposing a stiffening layer over the substrate.5. The method of claim 1 , wherein the substrate includes a circular shape or rectangular shape.6. The method of claim 1 , further including:removing the substrate; andforming an interconnect structure over the semiconductor die.7. A method of making a semiconductor device claim 1 , comprising:providing a ...

Semiconductor Device and Method of Forming Low Profile Fan-Out Package with Vertical Interconnection Units

A semiconductor device includes a semiconductor die. A first interconnect structure is disposed over a peripheral region of the semiconductor die. A semiconductor component is disposed over the semiconductor die. The semiconductor component includes a second interconnect structure. The semiconductor component is disposed over the semiconductor die to align the second interconnect structure with the first interconnect structure. The first interconnect structure includes a plurality of interconnection units disposed around first and second adjacent sides of the semiconductor die to form an L-shape border of the interconnection units around the semiconductor die. A third interconnect structure is formed over the semiconductor die perpendicular to the first interconnect structure. An insulating layer is formed over the semiconductor die and first interconnect structure. A plurality of vias is formed through the insulating layer and into the first interconnect structure with the second interconnect structure disposed within the vias. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;disposing a first modular interconnect structure along a peripheral region of the semiconductor die;providing a semiconductor component including a second interconnect structure formed over the semiconductor component; anddisposing the semiconductor component over the semiconductor die to align the second interconnect structure with the first modular interconnect structure.2. The method of claim 1 , further including forming the first modular interconnect structure in an L-shape along first and second adjacent sides of the semiconductor die.3. The method of claim 1 , further including forming the first modular interconnect structure along first and second opposite sides of the semiconductor die.4. The method of claim 1 , further including prefabricating the first modular interconnection structure.5. The method of claim 1 , further including:forming an ...

Semiconductor Device and Method of Forming Repassivation Layer for Robust Low Cost Fan-Out Semiconductor Package

A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metallization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 μm larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;forming a plurality of compliant islands over the semiconductor die; andforming a plurality of interconnect structures over the semiconductor die with each of the interconnect structures aligned with one of the compliant islands.2. The method of claim 1 , further including:forming an insulating layer over the compliant islands; andforming the interconnect structures over the insulating layer.3. The method of claim 2 , further including:forming a conductive layer on the insulating layer; andforming the plurality of interconnect structures on the conductive layer.4. The method of claim 3 , further including:forming an opening in the insulating layer and through one of the compliant islands to expose a contact pad of the semiconductor die; andforming the conductive layer extending into the opening.5. The method of claim 1 , further including:depositing an encapsulant around the semiconductor die; andforming a compliant layer to completely cover an interface between the semiconductor die and encapsulant.6. The method of claim 5 , ...