Stitch bump stacking design for overall package size reduction for multiple stack

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

Packaging Integrated Circuits

An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

Semiconductor package device with a heat dissipation structure and the packaging method thereof

The present invention provide a heat dissipation structure on the active surface of the die to increase the performance of the heat conduction in longitude direction of the semiconductor package device, so that the heat dissipating performance can be improved when the semiconductor package device is associated with the exterior heat dissipation mechanism.

Semiconductor device and method of manufacturing the semiconductor device

Disclosed are: a semiconductor device that comprises a semiconductor element to which a plurality of wires are bonded, wherein bonding strength of the wires is high and sufficient bonding reliability is achieved; and a method for manufacturing the semiconductor device. Specifically disclosed is a semiconductor device which is characterized by comprising a first wire that has one end bonded onto an electrode and the other end bonded to a second bonding point that is out of the electrode, and a second wire that has one end bonded onto the first wire on the electrode and the other end bonded to a third bonding point that is out of the electrode. The semiconductor device is also characterized in that the bonded portion of the first-mentioned end of the second wire covers at least apart of the upper surface and the lateral surface of the first wire.

Manufacturing method of semiconductor device, and semiconductor device

To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.

Method for Producing a Metal Layer on a Substrate and Device

A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation.

Method of manufacturing semiconductor device

Provided is a technology of suppressing, in forming an initial ball by using an easily oxidizable conductive wire and pressing the initial ball onto a pad to form a press-bonded ball, an initial ball from having a shape defect, thereby reducing damage to the pad. To achieve this, a ball formation unit is equipped with a gas outlet portion for discharging an antioxidant gas and a discharging path through this gas outlet portion is placed in a direction different from a direction of introducing the antioxidant gas into a ball formation portion. Such a structure widens a region for discharging the antioxidant gas, making it possible to prevent a gas flow supplied from the side of one side surface of the ball formation portion from being reflected by the other side surface facing with the one side surface and thereby forming a turbulent flow.

Ribbon bonding tools and methods of using the same

A ribbon bonding tool including a body portion is provided. The body portion includes a tip portion. The tip portion includes a working surface between a front edge of the tip portion and a back edge of the tip portion. The working surface includes a region defining at least one of a plurality of recesses and a plurality of protrusions. The working surface also defines at least one of ( 1 ) a first planar portion between the region and the front edge of the tip portion, and ( 2 ) a second planar portion between the region and the back edge of the tip portion.

Wire bonding method in circuit device

A wire bonding method in a circuit device mounted on a lead frame, the wire bonding method including: counting a stop time if an operation of a capillary stops; removing a contaminated free air ball (FAB) formed on an end of the capillary if the stop time exceeds a reference time; forming a new FAB; and restarting a wire bonding process.

Lead frame with grooved lead finger

A lead finger of a lead frame has a number of channels or grooves in a portion of its top surface that provide a locking mechanism for securing a bond wire to the lead finger. The bond wire may be attached to the lead finger by stitch bonding.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Power MOSFET Having Selectively Silvered Pads for Clip and Bond Wire Attach

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

SEMICONDUCTOR DEVICE

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film. 1. A semiconductor device comprising:an interlayer insulating film formed on a semiconductor substrate;an uppermost layer wiring made of copper and formed on the interlayer insulating film;a passivation film formed on the uppermost layer wiring and selectively exposing a top surface of the uppermost layer wiring as an electrode pad; anda bonding wire made of copper and bonded directly to the electrode pad.2. The semiconductor device according to claim 1 , wherein the bonding wire is stitch bonded directly to the electrode pad.3. The semiconductor device according to claim 1 , wherein the bonding wire is bonded to the electrode pad by a stud bump.4. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is no less than 10 μm.5. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is 10 μm to 15 μm.6. The semiconductor device according to claim 1 , further comprising a lower layer wiring covered with the interlayer insulating film claim 1 , whereinthe uppermost layer wiring includes a protrusion extending inside the interlayer insulating film,the lower layer wiring is electrically connected to the electrode pad via a pathway including the protrusion.7. The ...

PROCESS FOR ELECTRICALLY CONNECTING CONTACT SURFACES OF ELECTRONIC COMPONENTS

A process for electrically connecting contact surfaces of electronic components by capillary wedge bonding a round wire of 8 to 80 μm to the contact surface of a first electronic component, forming a wire loop, and stitch bonding the wire to the contact surface of a second electronic component, wherein the wire comprises a wire core having a silver or silver-based wire core with a double-layered coating comprised of a 1 to 50 nm thick inner layer of nickel or palladium and an adjacent 5 to 200 nm thick outer layer of gold. 1. A process for electrically connecting a contact surface of a first electronic component with a contact surface of a second electronic component comprising the subsequent steps:(1) capillary wedge bonding a wire having a circular cross-section with an average diameter in the range of 8 to 80 μm to the contact surface of the first electronic component,(2) raising the capillary wedge bonded wire to form a wire loop between the capillary wedge bond formed in step (1) and the contact surface of the second electronic component, and(3) stitch bonding the wire to the contact surface of the second electronic component,wherein the capillary wedge bonding of step (1) is carried out with a ceramic capillary having a lower face angle within the range of from zero to 4 degrees,wherein the wire comprises a wire core with a surface, the wire core having a double-layered coating superimposed on its surface,wherein the wire core consists of a material selected from the group consisting of pure silver, doped silver with a silver content of >99.5 wt.-% and silver alloys with a silver content of at least 89 wt.-%, andwherein the double-layered coating comprises a 1 to 50 nm thick inner layer of nickel or palladium and an adjacent 5 to 200 nm thick outer layer of gold.2. The process of claim 1 , (a′) an ultrasonic energy in a range of 50 to 100 mA,', '(b′) a force in a range of 10 to 30 g,', '(c′) a constant velocity in a range of 0.3 to 0.7 μm/s,', '(d′) a contact ...

ON-BONDER AUTOMATIC OVERHANG DIE OPTIMIZATION TOOL FOR WIRE BONDING AND RELATED METHODS

A method of providing a z-axis force profile applied to a plurality of bonding locations during a wire bonding operation is provided. The method includes: (a) determining a z-axis force profile for each of a plurality of bonding locations on an unsupported portion of at least one reference semiconductor device; and (b) applying the z-axis force profile during subsequent bonding of a subject semiconductor device. Methods of: determining a maximum bond force applied to a bonding location during formation of a wire bond; and determining a z-axis constant velocity profile for formation of a wire bond, are also provided. 1. A method of providing a z-axis force profile applied to a plurality of bonding locations during a wire bonding operation , the method comprising the steps of:(a) determining a z-axis force profile for each of a plurality of bonding locations on an unsupported portion of at least one reference semiconductor device; and(b) applying the z-axis force profile during subsequent bonding of a subject semiconductor device.2. The method of wherein step (a) includes measuring a z-axis oscillation at each of the plurality of bonding locations to determine the z-axis force profile for each of the plurality of bonding locations.3. The method of wherein step (a) further includes measuring the z-axis oscillation at each of the plurality of bonding locations at a plurality of z-axis force values to determine the z-axis force profile for each of the plurality of bonding locations.4. The method of wherein the z-axis oscillation is measured using a z-axis encoder of a bond head assembly of a wire bonding machine.5. The method of where the z-axis oscillation is measured in connection with an iterative process such that the z-axis force profile determined for each of the bonding locations at step (a) results in an acceptable z-axis deflection profile for each of the bonding locations.6. The method of where a maximum deflection value included in the z-axis deflection ...

Wire bond pad design for compact stacked-die package

Systems, methods, and devices for 3D packaging. In some embodiments, a semiconductor package includes a first die and a second die. The first die includes a first bonding pad on a top of the first die and near a first edge of the first die. The second die includes a second bonding pad on a top of the second die and near a second edge of the second die. A pillar is located on the second bonding pad. The first die is mounted on top of the second die such that the first edge is parallel to the second edge and offset from the second edge such that the pillar is exposed. A wire is bonded to a bonding surface of the pillar and bonded to a bonding surface of the first bonding pad.

METHODS OF FORMING WIRE INTERCONNECT STRUCTURES

A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to another location; (c) pressing a portion of the length of wire against the other location using the wire bonding tool; (d) moving the wire bonding tool, and the pressed portion of the length of wire, to a position above the wire bond; and (e) separating the length of wire from a wire supply at the pressed portion, thereby providing a wire interconnect structure bonded to the bonding location. 1. A method of forming a wire interconnect structure , the method comprising the steps of:(a) forming a wire bond at a bonding location on a substrate using a wire bonding tool;(b) extending a length of wire, continuous with the wire bond, to another location;(c) pressing a portion of the continuous length of wire against the other location using the wire bonding tool;(d) moving the wire bonding tool, and the pressed portion of the length of wire, to a position above the wire bond; and(e) separating the continuous length of wire from a wire supply at the pressed portion, thereby providing a wire interconnect structure bonded to the bonding location.2. The method of wherein the pressing step partially cuts the portion of the length of wire to form a partially cut portion of the continuous length of wire.3. The method of further comprising a step of forming a free air ball that is used to form the wire bond in step (a).4. The method of wherein a bonding force and ultrasonic energy are used in forming the wire bond.5. The method of wherein a bond force is used in the pressing step (c).6. The method of wherein ultrasonic energy is not used with the bond force in the pressing step (c).7. The method of further comprising the step of:(d1) extending an additional length of wire from the bonding tool, and above the pressed portion of the continuous length of wire ...

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR

A semiconductor device includes a semiconductor chip, a lead arranged on a side portion of the semiconductor chip, and a wire, whose one end and another end are bonded to the semiconductor chip and the lead respectively, having a ball portion and a stitch portion wedged in side elevational view on the semiconductor chip and the lead respectively. An angle of approach of the wire to the lead is not less than 50°, and the length of the stitch portion is not less than 33 μm. 1. A semiconductor device , comprising:a semiconductor chip;leads arranged around the semiconductor chip;wires bonded to the semiconductor chip and the leads;an island to which the semiconductor chip is bonded;a chip bonding material interposed between the semiconductor chip and the island to bond the semiconductor chip and the island to each other; anda package covering a part of the island and the leads, whereinin a plan view, the island has a quadrangular shape having four sides that are each skewed relative to respective outer sides of the package,the island includes hanging portions which in the plan view, extend from respective corner portions of the island toward the respective outer sides of the package,in the plan view, each respective lead of the leads has an opposing side opposed to and parallel to a nearest side of the four sides of the island which is nearest to the respective lead out of the four sides of the island, the opposing side located outside an outer perimeter of the semiconductor chip in the plan view, andin the plan view, a first hanging portion of the hanging portions is opposed to and parallel to a first side of the respective lead, a second hanging portion of the hanging portions is opposed to and parallel to a second side of the respective lead, the nearest side of the island is bridged between the first hanging portion and the second hanging portion, and the opposing side of the respective lead is bridged between the first side and the second side.2. The semiconductor ...

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR

A semiconductor device includes a semiconductor chip, a lead arranged on a side portion of the semiconductor chip, and a wire, whose one end and another end are bonded to the semiconductor chip and the lead respectively, having a ball portion and a stitch portion wedged in side elevational view on the semiconductor chip and the lead respectively. An angle of approach of the wire to the lead is not less than 50°, and the length of the stitch portion is not less than 33 μm. 1. A semiconductor device , comprising:a semiconductor chip;leads arranged around the semiconductor chip;wires bonded to the semiconductor chip and the leads;an island to which the semiconductor chip is bonded;a chip bonding material interposed between the semiconductor chip and the island to bond the semiconductor chip and the island to each other; anda package covering a part of the island and the leads, whereinin a plan view, the island has a quadrangular shape having four sides that are each skewed relative to respective outer sides of the package,the island includes hanging portions which in the plan view, extend from respective corner portions of the island toward the respective outer sides of the package,in the plan view, each respective lead of the leads has an opposing side opposed to a nearest side of the four sides of the island which is nearest to the respective lead out of the four sides of the island, andin the plan view, a first hanging portion of the hanging portions is opposed to a first side of the respective lead, a second hanging portion of the hanging portions is opposed to a second side of the respective lead, the nearest side of the island is bridged between the first hanging portion and the second hanging portion, and the opposing side of the respective lead is bridged between the first side and the second side.2. The semiconductor device according to claim 1 , wherein in the plan view claim 1 , each of the hanging portions extends toward a respective center of centers of ...

Quad flat no lead package and production method thereof

The present invention discloses a quad flat no lead package and a production method thereof. The quad flat no lead package comprises a lead frame carrier consisting of a carrier pit and three circles of leads arranged around the carrier pit, wherein the three circles of leads respectively consist of a plurality of leads that are disconnected mutually; an IC chip is adhered in the carrier pit; and an inner lead chemical nickel and porpezite plated layer is plated on all the leads; the inner lead chemical nickel and porpezite plated layer is arranged in the same direction as the IC chip; the IC chip is connected with the inner lead chemical nickel and porpezite plated layer through a bonding wire; and the IC chip, the ends of all the leads plated with the inner lead chemical plating nickel and palladium metal layers and the bonding wire are all packaged in a plastic package. The quad flat no lead package is manufactured through the following steps of: thinning and scribing a wafer; manufacturing a lead frame; loading the chip; performing pressure welding and plastic packaging; performing post-curing; printing; electroplating; separating the leads; separating a product; and testing/braiding. According to the package, the problems of few leads, long welding wire, high welding cost and limited frequency application during single-face packaging of the existing normal quad flat no lead package are solved.

METHOD OF MANUFACTURING MULTI-CHIP PACKAGE

A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps. 130.-. (canceled)31. A method of manufacturing a multi-chip package , the method comprising:stacking a first group of semiconductor chips on a package substrate including a first substrate pad;forming first stud bumps on bonding pads of the first group of semiconductor chips except for a lowermost semiconductor chip in the first group of semiconductor chips;downwardly extending a first conductive wire from a bonding pad of the lowermost semiconductor chip in the first group of semiconductor chips to connect the first conductive wire with the first substrate pad; andupwardly extending a second conductive wire from the bonding pad of the lowermost semiconductor chip in the first group of semiconductor chips to sequentially connect the second conductive wire with the first stud bumps,wherein the second conductive wire is a single wire continuously extending from the lowermost semiconductor chip to the first stud bumps in a steplike shape.32. The method as claimed in claim 31 , wherein stacking the first group of semiconductor chips includes stacking the first group of semiconductor chips in a steplike shape to expose the bonding pads.33. The method as claimed in claim 31 , wherein downwardly extending the first conductive wire from the bonding pad of the ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

To improve the reliability of a semiconductor device. 110-. (canceled)11. A method of manufacturing a semiconductor device , the method comprising:(a) preparing a semiconductor substrate which includes a plurality of wiring layers and a pad formed on an uppermost wiring layer of the plurality of wiring layers;(b) forming a surface protection film which includes an opening on the pad and is made of an inorganic insulating film;(c) forming a rewiring, which is electrically connected to the pad via the opening, on the surface protection film;(d) forming a pad electrode on the rewiring; and(e) forming a ball at a tip end of a wire, and connecting the ball to the pad electrode while applying ultrasonic vibration to the ball in a first direction,wherein the rewiring includes a pad electrode mounting portion on which the pad electrode is mounted, a connection portion which is connected to the pad, and an extended wiring portion that couples the pad electrode mounting portion and the connection portion, andthe pad electrode mounting portion has a rectangular shape with long sides and short sides.12. The method of manufacturing the semiconductor device according to claim 11 ,wherein the first direction is a direction along the long side.13. The method of manufacturing the semiconductor device according to claim 12 ,wherein the pad electrode covers a front surface of the pad electrode mounting portion, and extends to a side wall of the pad electrode mounting portion.14. The method of manufacturing the semiconductor device according to claim 11 ,wherein the first direction is a direction along the short side.15. The method of manufacturing the semiconductor device according to claim 11 ,wherein the pad electrode mounting portion includes a fin portion which extends from the long side or the short side to an outer side of the pad electrode mounting portion. The present application claims priority from Japanese Patent Application No. 2015-029409 filed on Feb. 18, 2015, the ...

Manufacturing method of package-on-package structure

A manufacturing method of a POP structure including at least the following steps is provided. A first package structure is formed and a second package structure is formed on the first package structure. The first package structure includes a circuit carrier and a die disposed on the circuit carrier. Forming the first package structure includes providing a conductive interposer on the circuit carrier, encapsulating the conductive interposer by an encapsulant and removing a portion of the encapsulant and the plate of the conductive interposer. The conductive interposer includes a plate, a plurality of conductive pillars and a conductive protrusion respectively extending from the plate to the circuit carrier and the die. The conductive protrusion disposed on the die, and the conductive pillars are electrically connected to the circuit carrier. The second package structure is electrically connected to the first package structure through the conductive interposer.

Package structure and manufacturing method thereof

A package structure and a manufacturing method thereof are provided. The package structure includes a circuit carrier, a substrate, a die, a plurality of conductive wires and an encapsulant. The substrate is disposed on the circuit carrier and includes a plurality of openings. The die is disposed between the circuit carrier and the substrate. The conductive wires go through the openings of the substrate to electrically connect between the substrate and the circuit carrier. The encapsulant is disposed on the circuit carrier and encapsulates the die, the substrate and the conductive wires.

Chip package structure and manufacturing method thereof

A chip package structure including a substrate, a first chip, a frame, a plurality of first conductive connectors, a first encapsulant, and a package is provided. The first chip is disposed on the substrate. The first chip has an active surface and a back surface opposite to the active surface, and the active surface faces the substrate. The frame is disposed on the back surface of the first chip and the frame has a plurality of openings. The first conductive connectors are disposed on the substrate and the first conductive connectors are disposed in correspondence to the openings. The first encapsulant is disposed between the substrate and the frame and encapsulates the first chip. The package is disposed on the frame and is electrically connected to the substrate via the first conductive connectors.

Semiconductor packages and methods of manufacturing the same

A semiconductor package comprises a board including a board pad, a plurality of semiconductor chips mounted on the board, the semiconductor chips including chip pads. Bumps are disposed on the chip pads, respectively, and a wire is disposed between the chip pads and the bumps. The wire electrically connects the chip pads of the plurality of semiconductor chips and the board pad to each other.

Methods of forming wire interconnect structures

A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to another location; (c) pressing a portion of the length of wire against the other location using the wire bonding tool; (d) moving the wire bonding tool, and the pressed portion of the length of wire, to a position above the wire bond; and (e) separating the length of wire from a wire supply at the pressed portion, thereby providing a wire interconnect structure bonded to the bonding location.

Wire bonding assembly and method

A method of wire bonding a die to a lead frame comprising mounting the die on a die attachment pad portion of a leadframe and supporting the leadframe on a support plate having a vacuum hole therein filled with porous material.

Semiconductor device

A semiconductor device includes a semiconductor element having first and second main surfaces spaced apart in a thickness direction. The semiconductor element includes a metal underlying layer on the first main surface, a bonding pad on the metal underlying layer with a wire bonded to the pad, and an insulative protection layer formed on the first main surface and surrounding the bonding pad. The bonding pad includes first and second conductive layers. The first conductive layer covers the metal underlying layer and is made of a metal having a lower ionization tendency than the metal underlying layer. The second conductive layer covers the first conductive layer and is made of a metal having a lower ionization tendency than the first conductive layer. The first and second conductive layers have respective peripheries held in close contact with the protection layer and covering a part of the protection layer.

Method of manufacturing semiconductor device

As one embodiment, a method of manufacturing a semiconductor device includes the following steps. That is, the method of manufacturing a semiconductor device includes a first step of applying ultrasonic waves to a ball portion of a first wire in contact with a first electrode of the semiconductor chip while pressing the ball portion with a first load. In addition, the method of manufacturing a semiconductor device includes a step of, after the first step, applying the ultrasonic waves to the ball portion while pressing the ball portion with a second load larger than the first load, thereby bonding the ball portion and the first electrode.

Bond pad having a trench and method for forming

A conductive structure is formed in a last metal layer of an integrated circuit. Passivation material is patterned over a portion of the conductive structure. A first trench is patterned around a selected portion of the passivation material. The selected portion represents a bond region of a wire bond to be formed above the passivation material. A portion of the passivation material completely covers a bottom of the trench. A layer of conductive material is conformally deposited over the passivation material. The conformal depositing resulting in a second trench forming in the conductive material over the first trench in the passivation material. The second trench is positioned to contain at least a portion of a splash of the conductive material when the wire bond is subsequently formed.

Semiconductor device

A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.

Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device

The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor element having first and second main surfaces spaced apart in a thickness direction. The semiconductor element includes a metal underlying layer on the first main surface, a bonding pad on the metal underlying layer with a wire bonded to the pad, and an insulative protection layer formed on the first main surface and surrounding the bonding pad. The bonding pad includes first and second conductive layers. The first conductive layer covers the metal underlying layer and is made of a metal having a lower ionization tendency than the metal underlying layer. The second conductive layer covers the first conductive layer and is made of a metal having a lower ionization tendency than the first conductive layer. The first and second conductive layers have respective peripheries held in close contact with the protection layer and covering a part of the protection layer. 124-. (canceled)25. A semiconductor device comprising:a semiconductor element including a first main surface and a second main surface that are spaced apart from each other in a thickness direction; anda wire,wherein the semiconductor element includes: a metal underlying layer formed on the first main surface; a bonding pad formed on the metal underlying layer and to which the wire is bonded; and an insulative protection layer formed on the first main surface and surrounding the bonding pad as viewed in the thickness direction,the bonding pad includes: a first conductive layer covering the metal underlying layer and made of a metal having a lower ionization tendency than the metal underlying layer; and a second conductive layer covering the first conductive layer and made of a metal having a lower ionization tendency than the first conductive layer,the first conductive layer and the second conductive layer have peripheries, respectively, that are in close contact with the protection layer and cover a part of the protection layer,the protection layer includes a ...

SEMICONDUCTOR DEVICE

A semiconductor device includes two or more semiconductor elements, a lead with island portions on which the semiconductor elements are mounted, a heat dissipation member for dissipating heat from the island portions, a bonding layer bonding the island portions and the heat dissipation member, and a sealing resin covering the semiconductor elements, the island portions and a part of the heat dissipation member. The bonding layer includes mutually spaced individual regions provided for the island portions, respectively. 120-. (canceled)21. A semiconductor device comprising:a semiconductor element;a lead on which the semiconductor element is mounted; anda wire electrically connected to the semiconductor element,wherein the wire includes a first bonding portion, a second bonding portion and a reinforcing bonding portion, the second bonding portion gradually reducing in thickness from a boundary provided by a stepped portion, the reinforcing bonding portion overlapping with at least a part of the second bonding portion and exposing the stepped portion.22. The semiconductor device according to claim 21 , wherein the reinforcing bonding portion includes a disk portion held in contact with the second bonding portion.23. The semiconductor device according to claim 22 , wherein the reinforcing bonding portion includes a columnar portion that is formed on the disk portion claim 22 , smaller in diameter than the disk portion and concentric with the disk portion.24. The semiconductor device according to claim 23 , wherein the reinforcing bonding portion includes a peak portion formed on the columnar portion.25. The semiconductor device according to claim 21 , further comprising a circular trace that is formed by a pressed capillary and located close to the second bonding portion.26. The semiconductor device according to claim 25 , wherein a part of the circular trace is exposed from the reinforcing bonding portion.27. The semiconductor device according to claim 26 , wherein the ...

Led package structure and manufacturing method thereof

A manufacturing method of an LED package structure includes the steps of providing a base; disposing an LED chip on the base; electrically connecting the base and the LED chip by at least one metal wire, wherein the metal wire has an apex, and a height between the apex and a top surface of the LED chip is defined as a loop height; adhering a first phosphor sheet to the LED chip by a B-stage resin of the first phosphor sheet, wherein the first phosphor sheet covers the top surface, the side surface, and the electrode of the LED chip, the thickness of the first phosphor sheet is smaller than the loop height, and the apex of the metal wire is exposed from the first phosphor sheet; and disposing an encapsulation resin in the base to encapsulate the LED chip, the metal wire, and the first phosphor sheet.

Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device

The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.

ELECTRONIC DEVICE

An electronic device includes an electronic element, and a wire bonded to the electronic element. The electronic element includes a bonding pad to which the wire is bonded. The main component of the bonding pad is Al. A metal is mixed in the wire, and the mixed metal is one of Pt, Pd and Au.

WIRE BONDING METHOD AND WIRE BONDING DEVICE

Provided is a wire bonding method capable of suppressing the occurrence of wire breakage. One aspect of the present invention provides a wire bonding method for bringing a capillary and a wire inserted through the capillary into pressure contact with a second bonding point of a lead placed on an XY stage to bond the wire to the lead, including moving the XY stage in a state in which the capillary is in pressure contact with the lead to move the capillary along a movement locus including a plurality of arc portions. 1. A wire bonding method for bringing a capillary and a wire inserted through the capillary into pressure contact with a lead placed on an XY stage to bond the wire to the lead , comprising moving the XY stage in a state in which the capillary is in pressure contact with the lead to move the capillary along a movement locus including a plurality of arc portions.2. The wire bonding method according to claim 1 , wherein the capillary is moved along a movement locus having no crossing portion.3. The wire bonding method according to claim 1 , wherein lengths of the plurality of arc portions are set such that an arc portion located closer to an end point of the movement locus is longer.4. The wire bonding method according to claim 1 , whereinthe plurality of arc portions are disposed such that, of adjacent arc portions, a beginning of an arc portion located closer to an end point of the movement locus is in proximity to a terminal of an arc portion located closer to a start point of the movement locus,the movement locus includes a connected portion connecting the beginning of the arc portion located closer to the end point and the terminal of the arc portion located closer to the start point, andthe movement locus has a zig-zag shape formed by the plurality of arc portions and connected portions connecting the arc portions.5. A wire bonding device claim 1 , comprising:an XY stage for placing a lead thereon;a mechanism for moving the XY stage in an X direction; ...

SEMICONDUCTOR DEVICE AND BALL BONDER

In order to inhibit forming cracks under a pad opening during ball bonding without increasing a chip size, a protective film includes a pad opening that exposes a part of a topmost layer metal film. A second metal film provided under the pad opening has a ring shape that defines a rectangular opening under the pad opening. The opening edge of the opening in the second metal film extends inwardly beyond the edge of the overlying pad opening. 1. In combination: a semiconductor device having a pad opening; and a ball bonder for bonding a wire to the semiconductor device in the pad opening;wherein the semiconductor device comprises:a semiconductor substrate;a first insulating film formed on a surface of the semiconductor substrate;a first metal film formed on the first insulating film;a second insulating film formed on the first metal film;a first part of a second metal film formed on the second insulating film;first vias formed in the second insulating film to connect the first metal film and the first part of the second metal film;a third insulating film formed on the first part of the second metal film;a topmost layer metal film formed on the third insulating film;second vias formed in the third insulating film to connect the first part of the second metal film and the topmost layer metal film; anda protective film formed on the topmost layer metal film and having a pad opening formed therein to expose a part of a surface of the topmost layer metal film,the first metal film being connected to the semiconductor substrate through contacts formed in the first insulating film under the topmost layer metal film,the first part of the second metal film having a ring shape defining an opening that is rectangular in plan view under the pad opening,an edge of the first part of the second metal film that defines the opening being located inside the pad opening in plan view, andall of the second vias that connect the first part of the second meal film and the topmost layer metal ...

WIRE BONDING METHOD AND WIRE BONDING APPARATUS

A wire bonding method comprises: preparing a wire bonding apparatus; a step of forming a free air ball; a first height measuring step of measuring the height of a first electrode by detecting whether the free air ball is grounded to the first electrode; a second height measuring step of measuring the height of a second electrode by detecting whether the free air ball is grounded to the second electrode; a first bonding step of controlling the height of a bonding tool based on the measurement result in the first height measuring step, and bonding the free air ball to the first electrode; and a second bonding step of controlling the height of the bonding tool based on the measurement result in the second height measuring step, and bonding a wire to the second electrode to connect the first and the second electrodes. Thus, electrodes can be correctly bonded. 1. A wire bonding method , comprising:a step of preparing a wire bonding apparatus comprising a bonding tool and a bonding stage, wherein the bonding tool is configured to allow a wire to be inserted, and the bonding stage fixes and holds a workpiece comprising a first electrode and a second electrode;a ball forming step of forming a free air ball at a front end of a wire inserted in the bonding tool;a first height measuring step of measuring a height of the first electrode by detecting whether the free air ball is grounded to the first electrode;a second height measuring step of measuring a height of the second electrode by detecting whether the free air ball is grounded to the second electrode;a first bonding step of bonding the free air ball to the first electrode by controlling a height of the bonding tool based on a measurement result of the first height measuring step; anda second bonding step of bonding the wire to the second electrode by controlling a height of the bonding tool based on a measurement result of the second height measuring step to connect the first electrode and the second electrode.2. The ...

Binding wire and semiconductor package structure using the same

A semiconductor package structure includes a substrate, and a package preform. The substrate includes a plurality of conductive tracing wires. The package preform includes a semiconductor chip and a plurality of binding wires. The semiconductor chip includes a plurality of welding spots, and the welding spots are electrically connected with corresponding conductive tracing wires by the binding wires. Each binding wire comprises a carbon nanotube composite wire, the carbon nanotube composite wire includes a carbon nanotube wire and a metal layer. The carbon nanotube wire consists of a plurality of carbon nanotubes spirally arranged along an axial direction an axial direction of the carbon nanotube wire.

SYSTEMS AND METHODS FOR OPTIMIZING LOOPING PARAMETERS AND LOOPING TRAJECTORIES IN THE FORMATION OF WIRE LOOPS

A method of forming a wire loop in connection with a semiconductor package is provided. The method includes the steps of: (1) providing package data related to the semiconductor package to a wire bonding machine; (2) providing at least one looping control value related to a desired wire loop to the wire bonding machine, the at least one looping control value including at least a loop height value related to the desired wire loop; (3) deriving looping parameters, using an algorithm, for forming the desired wire loop; (4) forming a first wire loop on the wire bonding machine using the looping parameters derived in step (3); (5) measuring actual looping control values of the first wire loop formed in step (4) corresponding to the at least one looping control value; and (6) comparing the actual looping control values measured in step (5) to the at least one looping control value provided in step (2). 1. A method of forming a wire loop in connection with a semiconductor package , the method comprising the steps of:(1) providing package data related to the semiconductor package to a wire bonding machine;(2) providing at least one looping control value related to a desired wire loop to the wire bonding machine, the at least one looping control value including at least a loop height value related to the desired wire loop;(3) deriving looping parameters, using an algorithm, for forming the desired wire loop;(4) forming a first wire loop on the wire bonding machine using the looping parameters derived in step (3);(5) measuring actual looping control values of the first wire loop formed in step (4) corresponding to the at least one looping control value; and(6) comparing the actual looping control values measured in step (5) to the at least one looping control value provided in step (2).2. The method of wherein the package data provided in step (1) includes at least one of (a) CAD data related to the semiconductor package and (b) package data derived using an online teaching ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

In an SOP1 having a semiconductor chip and another semiconductor chip, in wire coupling between the chips, a withstand voltage can be secured by setting an inter-wire distance between a wire in a first wire group that is closest to a second wire group and a wire in the second wire group that is closest to the first wire group to be larger than an inter-wire distance between any wires in the first wire group and the second wire group, which makes it possible to attain improvement of reliability of the SOP1. 118-. (canceled)19. A method for manufacturing a semiconductor device , comprising:a) preparing a lead frame that includes a first chip mounting part supported by a first suspension lead, a second chip mounting part supported by a second suspension lead, a plurality of first leads that are arranged adjacent to the first chip mounting part, and a plurality of second leads that are arranged adjacent to the second chip mounting part;b) mounting a first semiconductor chip over the first chip mounting part and mounting a second semiconductor chip over the second chip mounting part;c) electrically coupling some of a plurality of pads of the first semiconductor chip and some of a plurality of pads of the second semiconductor chip with a plurality of wires, respectively;d) electrically coupling some of the pads of the first semiconductor chip and the first leads with a plurality of wires, respectively;e) electrically coupling some of the pads of the second semiconductor chip and the second leads with a plurality of wires, respectively;f) forming a sealing body that seals the first and second semiconductor chips, parts of the first and second suspension leads, the first and second chip mounting parts, parts of the first leads and the second leads, and a plurality of wires, and has a first side extending in a first direction and a second side extending in a second direction that is a direction substantially perpendicular to the first direction; andg) cutting off the first ...

LED PACKAGE STRUCTURE

An LED package structure includes a base, an LED chip disposed on the base, at least one metal wire, a phosphor sheet, and an encapsulation resin disposed in the base and encapsulating the LED chip, the metal wire, and the phosphor sheet. The LED chip has at least one electrode thereon. The metal wire has an apex and a loop height being defined by the apex. The metal wire is electrically connected to the electrode and the base. The phosphor sheet includes a B-stage resin and a plurality of phosphor powders mixed therewith. The phosphor sheet is adhered to the LED chip by the B-stage resin capable of viscosity and covers the top surface, the side surface, and the electrode of the LED chip. A thickness of the phosphor sheet is smaller than the loop height, and the apex of the metal wire is exposed from the phosphor sheet. 1. An LED package structure , comprising:a base;an LED chip having at least one electrode thereon and being disposed on the base, the LED chip including a top surface, a bottom surface, and a side surface arranged between the top surface and the bottom surface;at least one metal wire having an apex and a loop height being defined by the apex, two opposite ends of the at least one metal wire being respectively and electrically connected to the at least one electrode of the LED chip and the base;a first phosphor sheet including a B-stage resin and a plurality of phosphor powders being mixed therewith, the first phosphor sheet being adhered to the LED chip by the B-stage resin capable of viscosity and covering the top surface, the side surface, and the at least one electrode of the LED chip, wherein a thickness of the first phosphor sheet is smaller than the loop height, and the apex of the at least one metal wire is exposed from the first phosphor sheet; andan encapsulation resin disposed in the base and encapsulating the LED chip, the at least one metal wire, and the first phosphor sheet.2. The LED package structure as claimed in claim 1 , wherein the ...

Semiconductor device and method of manufacturing the same

Disclosed is a semiconductor device that is capable of handling multiple different high-frequency contactless communication modes and that is formed by a multi-chip structure. A first semiconductor chip, which performs interface control of high-frequency contactless communication and data processing of communications data, is mounted on a wiring board; and a second semiconductor chip, which performs another data processing of the communication data, is mounted on the first semiconductor chip. In this case, transmission pads in the first semiconductor chip are arranged at positions farther from a periphery of the chip than those of receiving pads, and the second semiconductor chip is mounted by being biased on the first semiconductor chip so as to keep away the transmission pads.

Electrical interconnections for semiconductor devices and methods for forming the same

An electrical interconnection includes a wire loop having a first end bonded to a first bonding site using a first bonding portion, and a second end bonded to a second bonding site using a second bonding portion. The second bonding portion includes a folded portion having a wire that extends from the second end of the wire loop and is folded on the second bonding site. The folded portion includes a first folded portion connected to the second end of the wire loop and extending toward the first bonding site, a second folded portion provided on the first folded portion, and a tail protruding from a portion of the second folded portion. An interface is formed between the first and second folded portions. A top surface of the second folded portion includes an inclined surface recessed toward the first folded portion.

Semiconductor device

In order to prevent a crack from developing in an interlayer insulating film formed under a bonding pad due to impact, the bonding pad is formed so that small diameter metal plugs ( 14 a ) and large diameter metal plugs ( 14 b ) are arranged between a first metal film ( 12 ) and a second metal film ( 15 ) as an uppermost layer, and recessed portions ( 17 ) are formed in a surface of the second metal film ( 15 ) above the large diameter metal plugs 14 b.

METHODS OF FORMING WIRE INTERCONNECT STRUCTURES

A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to another location; (c) pressing a portion of the length of wire against the other location using the wire bonding tool; (d) moving the wire bonding tool, and the pressed portion of the length of wire, to a position above the wire bond; and (e) separating the length of wire from a wire supply at the pressed portion, thereby providing a wire interconnect structure bonded to the bonding location. 1. A method of forming a wire interconnect structure , the method comprising the steps of:(a) forming a wire bond at a bonding location on a substrate using a wire bonding tool;(b) extending a length of wire, continuous with the wire bond, to another location;(c) pressing a portion of the continuous length of wire against the other location using the wire bonding tool;(d) moving the wire bonding tool, and the pressed portion of the length of wire, to a position above the wire bond; and(e) separating the continuous length of wire from a wire supply at the pressed portion, thereby providing a wire interconnect structure bonded to the bonding location.2. The method of wherein the pressing step partially cuts the portion of the length of wire to form a partially cut portion of the continuous length of wire.3. The method of further comprising a step of forming a free air ball that is used to form the wire bond in step (a).4. The method of wherein a bonding force and ultrasonic energy are used in forming the wire bond.5. The method of wherein a bond force is used in the pressing step (c).6. The method of wherein ultrasonic energy is not used with the bond force in the pressing step (c).7. The method of further comprising the step of:(d1) extending an additional length of wire from the bonding tool, and above the pressed portion of the continuous length of wire ...

Semiconductor device

A semiconductor device includes a semiconductor element, a substrate, a lead, and a sealing resin member. The semiconductor element has a first electrode and a second electrode located on opposite sides in the thickness direction. The substrate has an insulating base and a conductive plate. The base has first and second surfaces located on opposite sides in the thickness direction. The conductive plate is bonded to the first surface of the base and electrically connected to the second electrode of the semiconductor element. The lead has an island electrically connected to the first electrode. The sealing resin member covers at least the semiconductor element.

METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND WIRE-BONDING APPARATUS

A method of manufacturing a semiconductor device is provided. A bonding tool with a wire tail extending out of the tip thereof is lowered to bring the tip of the wire tail into contact with a bonding surface of the semiconductor device. Next, the bonding tool in a direction intersecting with the axial direction of the bonding tool (Z direction) is moved to bend the wire tail with the tip of the wire tail in contact with the bonding surface. Then the bonding tool is lowered to form the wire tail into a predetermined shape such that the tip of the wire tail points upward. And then, a wire looping step, a second bonding step and a wire cutting step are performed. This allows the wire tail to be formed easily and efficiently into a predetermined shape. 1. A semiconductor device manufacturing method of a semiconductor device having a wire loop for connection between a first bonding point and a second bonding point , the method comprising:a wire tail contacting step of lowering a bonding tool with a wire tail extending out of a tip of the bonding tool to bring a tip of the wire tail into contact with a bonding surface of the semiconductor device;a wire tail bending step of moving the bonding tool in a direction intersecting with an axial direction of the bonding tool to bend the wire tail with the tip of the wire tail in contact with the bonding surface;a first bonding step of lowering the bonding tool to compress a portion of the wire tail at the first bonding point and to form the wire tail into a predetermined shape such that the tip of the wire tail points upward;a wire looping step of moving the bonding tool while paying out a wire to cause the wire to extend in a predetermined shape;a second bonding step of lowering the bonding tool to compress a portion of the wire at the second bonding point; anda wire cutting step of cutting the wire to cause a portion of the wire to extend out of the tip of the bonding tool.2. The semiconductor device manufacturing method ...

SEMICONDUCTOR DEVICE

A semiconductor device includes two or more semiconductor elements, a lead with island portions on which the semiconductor elements are mounted, a heat dissipation member for dissipating heat from the island portions, a bonding layer bonding the island portions and the heat dissipation member, and a sealing resin covering the semiconductor elements, the island portions and a part of the heat dissipation member. The bonding layer includes mutually spaced individual regions provided for the island portions, respectively. 120-. (canceled)21. A semiconductor device comprising:a first island:a first semiconductor element, a second semiconductor element, a third semiconductor element, a fourth semiconductor element, a fifth semiconductor element and a sixth semiconductor element mounted on the first island and spaced apart from each other in plan view, the second semiconductor element overlapping with the first semiconductor element as viewed in a first direction, the third semiconductor element overlapping with the first semiconductor element as viewed in a second direction perpendicular to the first direction, the fourth semiconductor element overlapping with the third semiconductor element as viewed in the first direction, the fifth semiconductor element overlapping with the third semiconductor element as viewed in the second direction, the sixth semiconductor element overlapping with the fifth semiconductor element as viewed in the first direction;a second island spaced apart from the first island;a first control IC mounted on the second island for driving the first semiconductor element, the third semiconductor element and the fifth semiconductor element;a first terminal, a second terminal and a third terminal spaced from each other and spaced from the first island and the second island in plan view;a first wire connecting the first semiconductor element to the second semiconductor element;a second wire connecting the first wire to the first terminal;a third wire ...

QFN Device Having A Mechanism That Enables An Inspectable Solder Joint When Attached To A PWB And Method Of Making Same

An apparatus and method for providing an artificial standoff to the bottom of leads on a QFN device sufficient to provide a gap that changes the fluid dynamics of solder flow and create a unique capillary effect that drives solder up the of leads of a UN device when it is attached to a printed wiring board (PWB).

SEMICONDUCTOR DEVICE

A semiconductor device includes two or more semiconductor elements, a lead with island portions on which the semiconductor elements are mounted, a heat dissipation member for dissipating heat from the island portions, a bonding layer bonding the island portions and the heat dissipation member, and a sealing resin covering the semiconductor elements, the island portions and a part of the heat dissipation member. The bonding layer includes mutually spaced individual regions provided for the island portions, respectively. 120-. (canceled)21. A semiconductor device , comprising:a first island part,a first semiconductor chip mounted on the first island part,a second island part,a second semiconductor chip mounted on the second island part,a third island part,a third semiconductor chip mounted on the third island part,a fourth island part,a fourth semiconductor chip mounted on the forth island part,a fifth semiconductor chip mounted on the forth island part,a sixth semiconductor chip mounted on the forth island part,a fifth island part,a first driving semiconductor chip mounted on the fifth island part and connected to each of the first to third semiconductor chips,a sixth island part,a second driving semiconductor chip mounted on the sixth island part and connected to each of the fourth to sixth semiconductor chips,a first lead terminal connected to the first semiconductor chip by a first wire,a second lead terminal connected to the second semiconductor chip by a second wire,a third lead terminal connected to the third semiconductor chip by a third wire,a fourth lead terminal connected to the fourth semiconductor chip by a fourth wire,a fifth lead terminal connected to the fifth semiconductor chip by a fifth wire,a sixth lead terminal connected to the sixth semiconductor chip by a sixth wire, anda seventh lead terminal extending from the fourth island part,wherein the first to sixth semiconductor chips are arranged in a first direction in a row,the first lead terminal is ...

Wedge tool, bonding device, and bonding inspection method

It is an object to enable a non-destructive inspection of reliability of a bonding part and enabling an accurate inspection. A wedge tool includes: a groove which is formed along a direction of an ultrasonic vibration in a tip portion and in which a bonding wire is disposed in a wedge bonding; a first planar surface and a second planar surface disposed on both sides of the groove; and at least one convex portion formed away from the groove in at least one of the first planar surface and the second planar surface, wherein the bonding wire comes in contact with the convex portion by a deformation of the bonding wire in a bonding part of the bonding wire and a bonded object bonded to each other by a wedge bonding.

SEMICONDUCTOR DEVICE HAVING AN ELECTRICAL CONNECTION BETWEEN SEMICONDUCTOR CHIPS ESTABLISHED BY WIRE BONDING, AND METHOD FOR MANUFACTURING THE SAME

A method for manufacturing a semiconductor device includes (i) a step of preparing a first semiconductor chip having a first electrode pad thereon and a second semiconductor chip having a second electrode pad thereon and larger in thickness than the first semiconductor chip, the second electrode pad being larger in size than the first electrode pad, (ii) a step of mounting the first semiconductor chip and the second semiconductor chip on the same planarized surface of a substrate having a uniform thickness, (iii) a step of bonding a ball formed by heating and melting a bonding wire to the second electrode pad, (iv) a step of first-bonding the bonding wire to the first electrode pad, and (v) a step of second-bonding the bonding wire to the ball. 1. A semiconductor device comprising:a first semiconductor chip having a first electrode pad thereon;a second semiconductor chip having a second electrode pad thereon and being larger in thickness than the first semiconductor chip, the second electrode pad being larger in size than the first electrode pad;a ball bonded to the second electrode pad; anda bonding wire including a first bonding portion bonded to the first electrode pad and a second bonding portion bonded to the ball,wherein the thinner first semiconductor chip comprises a compound semiconductor substrate and the thicker second semiconductor chip comprises a silicon semiconductor substrate.2. The semiconductor device according to claim 1 , whereinthe bonding wire includesa first portion that connects a first position higher than a position of the ball to the first electrode pad when viewed in a direction perpendicular to a planarized surface of a substrate, anda second portion that connects the first position to the second electrode pad; andthe bonding wire bends at the first position, the bonding wire and an imaginary line connecting the first portion and the second portion being in a substantially triangular shape when viewed in a direction perpendicular to the ...

Electronic component and electronic device

FIELD: electricity. SUBSTANCE: device comprises a body containing an electronic device, at that the body includes base body, cover body and frame body, moreover frame body has the first and second sections. The second section is longer than the first one, and thickness of the first section is less than length of this first section in the above direction, at that base body and frame body feature higher specific conductivity than specific conductivity of the cover body. EFFECT: improved efficiency in heat removal from the electronic device. 20 cl, 25 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 2 573 252 C2 (51) МПК H05K 7/20 (2006.01) G03B 17/02 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ (21)(22) Заявка: ИЗОБРЕТЕНИЯ К ПАТЕНТУ 2013116880/08, 12.04.2013 (24) Дата начала отсчета срока действия патента: 12.04.2013 Приоритет(ы): (30) Конвенционный приоритет: (43) Дата публикации заявки: 20.10.2014 Бюл. № 29 (54) ЭЛЕКТРОННЫЙ КОМПОНЕНТ И ЭЛЕКТРОННОЕ УСТРОЙСТВО (57) Реферат: Изобретение относится к устройствам для участок. Второй участок имеет более большую переноса тепла, созданного в электронном длину, чем длина первого участка, а толщина устройстве. Техническим результатом является первого участка меньше, чем длина первого повышение эффективности отвода тепла от участка в упомянутом направлении, причем тело электронного устройства. Устройство содержит основания и тело рамки имеют более высокую корпус, который вмещает электронное удельную теплопроводность, чем удельная устройство, при этом корпус включает в себя тело теплопроводность тела крышки. 3 н. и 17 з.п. фоснования, тело крышки и тело рамки, причем лы, 25 ил. тело рамки имеет первый участок и второй R U 2 5 7 3 2 5 2 Адрес для переписки: 129090, Москва, ул. Б. Спасская, 25, строение 3, ООО "Юридическая фирма Городисский и Партнеры" Стр.: 1 C 2 C 2 (56) Список документов, цитированных в отчете о поиске: US 2008/0292308 A1, 27.11.2008. RU 2 198 949 C2, 20.02.2003. RU 108 263 U1, 10.09. ...

Wire bonding method

ワイヤボンデイング方法

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

空气张力装置

一种空气张力装置，其具有插通管(4)、支撑体(6)以及压缩气体供给装置(7)，所述插通管(4)具有可插通引线接合用金属线(2)的插通孔(3)；所述支撑体(6)插入并支撑该插通管(4)；所述压缩气体供给装置(7)通过设在插通管(4)上的气体导入通路(18)对插通孔(3)供给压缩气体；插通孔(3)由第一插通孔(10)以及第二插通孔(11)构成，所述第二插通孔(11)位于第一插通孔(10)的下方，并具有比第一插通孔(10)的孔径更小的细孔部(17)；细孔部(17)的孔径为0.100～0.070mm，且第一插通孔(10)的孔径与细孔部(17)的孔径之比为3.00以上小于6.00。据此可防止金属线(2)的损伤，且赋予规定的适当张力。

ワイヤボンディング方法

Insolubilizing material and insolubilizing method

ワイヤボンデイング方法

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Semiconductor device

반도체장치(X1)는, 반도체 칩(3)과, 이 반도체 칩(3)의 한 쪽의 극에 접속된 제1리드(1)와, 상기 반도체 칩(3)의 다른 쪽의 극에 접속된 제2리드(2)와, 상기 반도체 칩(3)과 제1리드(1)의 내부단자(10) 및 제2리드(2)의 내부단자(20)를 봉입하는 수지패키지(4)를 포함하고 있다. 상기 수지패키지(4)는, 제1∼제4의 측면(41∼44)과, 상면(47)과, 저면(45)을 가진다. 상기 제1 및 제2리드(1, 2)의 각각은, 상기 수지패키지(4)의 제1의 측면(41) 및 저면(45)을 따라 뻗은 절곡된 적어도 1개의 외부단자(11, 21)를 가지고 있다. The semiconductor device X1 includes a semiconductor chip 3, a first lead 1 connected to one pole of the semiconductor chip 3, and a pole connected to the other pole of the semiconductor chip 3. And a resin package 4 encapsulating the second lead 2, the semiconductor chip 3, the inner terminal 10 of the first lead 1, and the inner terminal 20 of the second lead 2. Doing. The resin package 4 has first to fourth side surfaces 41 to 44, an upper surface 47, and a bottom surface 45. Each of the first and second leads 1 and 2 may be bent at least one external terminal 11 and 21 extending along the first side 41 and the bottom 45 of the resin package 4. Have

电子部件和电子装置

本发明提供一种电子部件和电子装置。具体地，一种封装包括：电子器件固定到的基本体、面对电子器件的盖体、和包围电子器件与盖体之间的空间以及电子器件中的至少一个的框架体。框架体具有在从框架体的内边缘向框架体的外边缘的X方向上、相对于基本体的外边缘位于框架体的内边缘侧处的第一部分和相对于基本体的外边缘位于框架体的外边缘侧处的第二部分。

Method for manufacturing a semiconductor chip

본 발명은 반도체장치 및 그 제조방법에 관한 것으로서, 반도체장치는 제 1 및 제 2 반도체 칩(14, 16)을 포함하고, 제 1 반도체 칩(14)의 표면에는 복수의 제 1 전극이 형성되고, 제 2 반도체 칩(16)의 표면에도 또 복수의 제 2 전극이 형성되며, 각각의 표면이 대향하고, 이것에 의해 복수의 제 1 전극과 복수의 제 2 전극이 각각 접속되고, 각각의 표면에는 또한 회로소자가 형성되고, 이 회로소자는 제 1 반도체 칩 및 제 2 반도체 칩에 의해 피복되어 감추어지며, 제 1 반도체 칩(14) 및 제 2 반도체 칩(16)의 접속부분은 방습성이 우수한 합성수지로 패키지(26)로 되며, 제 1 반도체 칩(14) 및 제 2 반도체 칩(16)의 전체가 밀착성이 우수한 제 2 합성수지로 패키지(22)된 것을 특징으로 한다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, wherein the semiconductor device includes first and second semiconductor chips 14 and 16, and a plurality of first electrodes are formed on a surface of the first semiconductor chip 14. In addition, a plurality of second electrodes are formed on the surface of the second semiconductor chip 16, and the surfaces thereof face each other, whereby the plurality of first electrodes and the plurality of second electrodes are connected to each other, and the respective surfaces thereof. In addition, a circuit element is formed, and the circuit element is covered and concealed by the first semiconductor chip and the second semiconductor chip, and the connection portions of the first semiconductor chip 14 and the second semiconductor chip 16 are excellent in moisture resistance. The package 26 is made of synthetic resin, and the entirety of the first semiconductor chip 14 and the second semiconductor chip 16 is packaged with the second synthetic resin having excellent adhesion.

Semiconductor device and manufacture therof

(57)【要約】 【課題】 積層メッキ構造を有するインナーリードにワ イヤーボンディングする際の積層メッキ層における剥が れを防止する。 【解決手段】 ニッケル，パラジウム及び金の積層メッ キ層を有するリードフレーム１のダイパッド部２上に半 導体チップ３をボンディングする。その後、半導体チッ プ３の電極パッド４上に、金線からなる金属細線６をボ ンディングツール２０を介して荷重約６０（ｇ）で押圧 し、出力が約５５（ｍＷ）の超音波を印加しながら第１ ボンディング工程を行う。次に、金属細線６をインナー リード部５に荷重１５０〜２５０（ｇ）で押圧し、出力 が０〜２０（ｍＷ）の超音波を印加して、第２ボンディ ング工程を行う。第２ボンディング工程で、大きな押圧 荷重とわずかの超音波出力とによって、積層メッキ層の 特性に適合したボンディングが行われ、金メッキ層の剥 がれも生じず短時間で強固な接合が行われる。

Assembling of semiconductor device

Wire bonding apparatus

ワイヤボンデイング方法

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Semiconductor device and method for manufacturing thereof

본 발명은 반도체장치 및 그 제조방법에 관한 것으로서, 반도체장치는 제 1 및 제 2 반도체 칩(14, 16)을 포함하고, 제 1 반도체 칩(14)의 표면에는 복수의 제 1 전극이 형성되고, 제 2 반도체 칩(16)의 표면에도 또 복수의 제 2 전극이 형성되며, 각각의 표면이 대향하고, 이것에 의해 복수의 제 1 전극과 복수의 제 2 전극이 각각 접속되고, 각각의 표면에는 또한 회로소자가 형성되고, 이 회로소자는 제 1 반도체 칩 및 제 2 반도체 칩에 의해 덮여 감추어지며, 제 1 반도체 칩(14) 및 제 2 반도체 칩(16)의 접속부분은 방습성이 우수한 합성수지로 패키지(26)되며, 제 1 반도체 칩(14) 및 제 2 반도체 칩(16)의 전체가 밀착성이 우수한 제 2 합성수지로 패키지(22)된 것을 특징으로 한다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, wherein the semiconductor device includes first and second semiconductor chips 14 and 16, and a plurality of first electrodes are formed on a surface of the first semiconductor chip 14. In addition, a plurality of second electrodes are formed on the surface of the second semiconductor chip 16, and the surfaces thereof face each other, whereby the plurality of first electrodes and the plurality of second electrodes are connected to each other, and the respective surfaces thereof. In addition, a circuit element is formed, and the circuit element is covered and concealed by the first semiconductor chip and the second semiconductor chip, and the connection portions of the first semiconductor chip 14 and the second semiconductor chip 16 are synthetic resins having excellent moisture resistance. The furnace package 26 is characterized in that the whole of the first semiconductor chip 14 and the second semiconductor chip 16 is packaged with a second synthetic resin excellent in adhesion.

Method of making a low-profile wire connection for stacked dies

A stacked dies include a substrate, a lower chip and an upper chip. A plurality of upper wires have the bent portion at the bonding pad of the substrate to reduce the height and increase the strength of the wire so as to increase the reliability of the product and to increase the space between the lower wire and the upper wire for reduction cross talk. A method of making low profile upper wire connection comprising steps of: after an upper wire is connected to a first bonding point, a capillary is moved straight up a first distance, and then the capilairy is moved away from a second bonding point thus making a first reverse action to bend the wire in an appropriate angle so as to form the first bent point. The capillary is again raised a second distance and moved downward a second reverse action to bend the upper wire by an appropriate angle so as to form the second bent point. The capillary is raised a third distance and then the capillary is moved away the second bonding point thus making an action to bend the wire in an appropriate angle so as to form the third bent point. The capillary is further raised a fourth distance. The capillary is raised to the second bonding point to extend the length of two wire ends which is enough to make a wire loop, amd then the capillary is moved down to the second bonding point where the bonding is performed.

Bonding method of insulating wire

내용 없음. No content.

Wire bonding apparatus and method for producing semiconductor device

打线装置(10)具备：毛细管(28)，其供导线(30)通插；未连判断电路(36)，其向接合对象物与处于夹紧状态的导线(30)之间施加既定的电信号，且依据其的回应来判断接合对象物与导线(30)之间的未连及导线(30)是否切断；圆环状的突出长度检测环40，其与毛细管(28)同轴地配置；及突出长度判断电路(38)，其根据向突出长度检测环(40)与导线(30)之间施加既定的检查电压时的导通的有无的检测以及向其间施加既定的检查高电压时的放电火花的有无的检测，来判断自毛细管(28)之前端突出的导线尾部的突出长度是否适当。

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Optical transmitting set packaging part and device and correlation technique with improved wire bonding

本发明公开了具有改进的引线接合的光发射器封装件和装置及相关方法。在一个实施例中，光发射器封装件可包括通过焊线电连接至电元件的至少一个发光二极管（LED）芯片。所述焊线可通过改进的引线接合参数，诸如约150℃或更低的温度、约100ms或更少的接合时间、约1700mW或更小的功率以及约100克力（gf）或更小的力或其组合来提供。

Wire bonding apparatus and method

Wire bonder, wire bonding method and computer­readable medium having a program for the same

본 발명은 와이어 본더, 와이어 본딩 방법 및 프로그램 및 이들에 사용하는 본딩 툴에 관한 것으로서, 본딩 툴을 외면으로부터 가열함으로써 반도체 칩 상의 패드에 압착되는 와이어의 접합면 온도를 고온으로 가열하는 것을 목적으로 한다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wire bonder, a wire bonding method and a program, and a bonding tool used therein, wherein an object of the present invention is to heat a bonding surface temperature of a wire compressed to a pad on a semiconductor chip to a high temperature by heating the bonding tool from an outer surface thereof. . 캐필러리(16)의 선단 부분과 외측면은 다이아몬드층(39)에 의해 덮여 있고, 외면에는 히터(31)가 부착되어 있다. 내부는 테이퍼공(43)을 갖는 알루미나 세라믹스부(41)이다. 캐필러리(16)의 선단에는 다이아몬드층(39)에 의해 형성되어 와이어 가열부를 구성하는 페이스부(47)와 이너 챔퍼부(49)가 형성되어 있다. 히터(31)로부터의 열은 다이아몬드층(39)에 의해 구성된 열공급로에 의해 와이어 가열부에 전달되어 와이어(12)와 패드(3)와의 접합면(53)을 가열한다. The tip portion and the outer surface of the capillary 16 are covered by the diamond layer 39, and the heater 31 is attached to the outer surface. The inside is an alumina ceramics portion 41 having a tapered hole 43. At the distal end of the capillary 16, a face portion 47 and an inner chamfer portion 49 formed by the diamond layer 39 to constitute the wire heating portion are formed. Heat from the heater 31 is transferred to the wire heating portion by a heat supply path constituted by the diamond layer 39 to heat the joint surface 53 between the wire 12 and the pad 3. 와이어 본딩, 본더, 본딩 툴, 캐필러리, 다이아몬드, 접합면, 히터 Wire Bonding, Bonders, Bonding Tools, Capillaries, Diamonds, Bonding Surfaces, Heaters

Method for manufacturing high-frequency circuit module

Wire bonding method and semiconductor package by the same

본 발명에 따르면, 와이어 본딩 방법 및 그에 의한 반도체 패키지가 개시된다. 상기 와이어 본딩 방법은, 와이어를 장착한 본딩헤드가 이동하면서 1차 본딩면 및 2차 본딩면 사이를 전기적으로 연결하는 와이어 본딩 방법에 있어서, 본딩헤드가 하강하면서 와이어 일단에 형성된 용융볼을 1차 본딩면에 대해 융착하는 1차 본딩 단계, 본딩헤드가, 1차 본딩된 와이어 일단에서 이어진 와이어를 고정하고 이동하면서 용융볼에 인접한 와이어의 열 영향 영역(Heat Affected Zone)에 소정의 굴곡을 형성하는 열영향부 변형 단계 및 본딩헤드가 2차 본딩면으로 이동하여서 와이어의 타단을 2차 본딩면에 대해 부착하는 2차 본딩 단계를 포함한다. 개시된 와이어 본딩 방법 및 그에 의한 반도체 패키지에 의하면, 반도체 칩과 리드 사이를 연결하는 와이어의 루프 높이를 소정 범위로 제한할 수 있고, 특히 멀티 칩 패키지에 있어서 와이어 사이의 단락 현상이 방지된다. According to the present invention, there is disclosed a wire bonding method and a semiconductor package thereby. The wire bonding method is a wire bonding method for electrically connecting a first bonding surface and a second bonding surface while a bonding head on which a wire is mounted is moved. The first bonding step of fusion to the bonding surface, the bonding head to form a predetermined bend in the heat affected zone (Heat Affected Zone) of the wire adjacent to the molten ball while fixing and moving the wire connected from one end of the primary bonded wire A heat affected zone deforming step and a secondary bonding step in which the bonding head moves to the secondary bonding surface to attach the other end of the wire to the secondary bonding surface. According to the disclosed wire bonding method and the semiconductor package thereby, the loop height of the wire connecting the semiconductor chip and the lead can be limited to a predetermined range, and in particular, a short circuit between the wires is prevented in a multi-chip package.

Manufacturing method of semiconductor device

Device having resin package and method of producing the same

一种元件，它包含以下部分：芯片(111)；封装芯片的树脂封壳(112，151，314)，该树脂封壳的安装面上设有树脂凸部(117，154，318)，树脂凸部上设有相应的金属膜(113，155，315)。芯片的电极焊盘与金属膜由连接部分(118，101，163，245，313，343，342)电连接，每个所述树脂凸部都被所述金属膜整体地覆盖。

Semiconductor device and manufacture thereof

Oilless compressor

(57)【要約】 【課題】 ボンディングワイヤの側面部とリードとの圧 着部位の信頼性を向上させる。 【解決手段】 リードフレーム４のタブ４ａに搭載され た半導体ペレット３のボンディングパッド３ａとリード ４ｂとの間にボンディングワイヤ１３を架設するワイヤ ボンディングにおいて、リード４ｂに対するボンディン グワイヤ１３の接合予定部位１３ｂに対して、ボンディ ングに先立って第２の放電電極１７との間で放電を行わ せることで局部的な加熱による焼き鈍しを施すことによ り、ボンディング温度を高くしたり、線径を必要以上に 太くしたり、ボンディングワイヤ１３の純度を必要以上 に高くする等の対策を必要とすることなく、リード４ｂ に対するボンディングワイヤ１３の圧着部位の面積や接 合強度を大きくして、圧着部位の亀裂や断線の発生を回 避する。

Wire bonding apparatus and method for producing semiconductor device

와이어 본딩 장치(10)는 와이어(30)를 삽입통과시키는 캐필러리(28)와, 본딩 대상물과 클램프 상태의 와이어(30) 사이에 소정의 전기 신호를 인가하고, 그 응답 에 기초하여 본딩 대상물과 와이어(30) 사이의 불착과 와이어(30)가 절단된 것인지 아닌지를 판정하는 불착 판정 회로(36)와, 캐필러리(28)와 동축에 배치되는 둥근 고리 형상의 돌출길이 검출 링(40)과, 돌출길이 검출 링(40)과 와이어(30) 사이에 소정의 검사 전압을 인가했을 때의 도통의 유무의 검출 및 그 사이에 소정의 검사 고전압을 인가 했을 때의 방전 스파크의 유무의 검출에 기초하여, 캐필러리(28)의 선단으로부터 돌출하는 와이어 테일의 돌출길이의 적절/부적절을 판정하는 돌출길이 판정 회로(38)를 구비한다. The wire bonding apparatus 10 includes a capillary 28 for inserting the wire 30 and a wire 30 for applying a predetermined electric signal between the object to be bonded and the clamped wire 30, A determination circuit 36 for determining whether or not the wire 30 is disconnected from the wire 30 and whether or not the wire 30 has been cut off, and a rounded protruding length detection ring 40 The detection of the presence or absence of conduction when a predetermined inspection voltage is applied between the protruding length detecting ring 40 and the wire 30 and the detection of the presence or absence of a discharge spark when a predetermined inspection high voltage is applied therebetween And a protrusion length determination circuit 38 that determines the proper / improper length of the protrusion of the wire tail protruding from the tip end of the capillary 28. [

Method and apparatus for enabling conventional wire bonding to copper-based bond pad features

본 발명에 따른 방법은 표면에서 산화물을 제거하는 단계와, 그 후에, 산화물제거의 5초이내에 표면에서 부동화층의 도포를 개시하는 단계를 포함하는 바, 상기 표면은 구리표면으로 될 수 있으며, 본드패드표면을 추가로 구비하고, 산화물의 제거는 구연산 혹은 염산을 함유한 용매를 도포하는 단계를 추가로 포함하며, 부동화층의 도포는 아졸계 화합물을 포함한 용매를 도포하는 단계를 추가로 포함하되, BTA를 추가로 포함할 수 있는 한편, 상기 방법은 도포가 개시된 후에 35초내에 부동화층을 완전히 도포하는 단계를 추가로 포함할 수 있다.

Wire bonder

(57)【要約】 【課題】 ワイヤボンダにおいて、ウェッジ側のボンデ ィング不良に起因して不良品が多発することを未然に防 止する。 【解決手段】 ボンディング作業時に、検査用の電圧を ワイヤに印加しておき、セカンドボンディングを行った 後（Ｓ５）、ワイヤとリードフレーム間の電圧を測定す る（Ｓ６）。測定値が正常な場合の電圧と一致しない場 合には（Ｓ７でＮＯ）、ワイヤがリードフレームから剥 がれたり又は切れたりしたと判断し、ボンディング作業 を停止させる（Ｓ１４）。また、ワイヤクランプを閉作 動させた後（Ｓ８）、ワイヤとリードフレーム間の電圧 を測定し（Ｓ９）、測定値が正常な場合の電圧と一致し ない場合には（Ｓ１０でＮＯ）、ワイヤクランプが閉じ た後にワイヤがリードフレームから剥がれたと判断し、 ボンディング作業を停止させる（Ｓ１４）。

Semiconductor device

How to connect electronic components

PROBLEM TO BE SOLVED: To prevent a bonding wire from coming out of a bonding tool, when the bonding tool vibrates in a method for connecting a power device to the terminals of a wiring board through wedge bonding, even if the initial pressure applied to the tool is reduced by a method where frictional force between the bonding wire and bonding tool is increased. SOLUTION: After a bonding wire 20 supported by the wedge parts of a bonding tool 10 is pressed against the groove part of a jig 30 with a groove made of a material harder than the wire 20 so as to increase a contact area M1 between the wire 20 and the tool 10, the wire 20 is pressed against a power device 1 and made to vibrate under pressure applied by the tool 10 to connect the wire 20 to the power device 1. Then the wire 20 is layed out to the terminal of a wiring board and connected to the terminal through wedge bonding.

IPM packaging method and bonding method in IPM package

本发明提供了一种IPM的封装方法以及IPM封装中的键合方法，对IGBT芯片与电路板之间直径相对较粗的第一引线采用频率相对较低的超声波进行第一冷超声波键合，对驱动芯片与电路板之间的直径相对较细的第二引线采用频率相对较高的超声波进行第二冷超声波键合。好处在于：相对于金铜线热超声波键合，利用冷超声波键合无需加热，可以避免高温加热导致的承载IGBT芯片及驱动芯片的绝缘基板与基岛分离，以及避免分离过程中绝缘基板撕裂导致的绝缘性能变差，进而避免IPM耐压性差及散热不良等问题，提高IPM良率和性能。

Semiconductor device and manufacturing method thereof

Semiconductor device and manufacturing method thereof

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device obtained by cutting apart a semiconductor wafer having semiconductor elements formed in units of a chip, wherein heat-dissipating properties can be appropriately ensured in response to a structure. <P>SOLUTION: A second semiconductor element 20 and a first semiconductor element 10 are sequentially laminated and mounted on an island 30, and both the semiconductor elements 10, 20 are adhered with adhesives 70. Further, both the semiconductor elements 10, 20 are electrically connected to a lead 40 by a bonding wire 70, and these are sealed with a mold resin 60. Here, the first semiconductor element 10 of an upper stage is configured as an aggregate of a plurality of (two or more) units of a chip T cut apart from a semiconductor wafer 200. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Wire bonding equipment

Connecting method of body and discharge electrode used for said method

structure of semiconductor package

본 발명은 히트싱크가 부착되는 리드프레임 패키지의 구조를 개선하여 와이어 본딩시 리드핑거의 와이어 본딩영역에서의 에너지 소산을 줄일 수 있도록 하므로써 와이어 본딩 불량을 방지할 수 있도록 한 것이다. The present invention improves the structure of the lead frame package to which the heat sink is attached, thereby reducing the energy dissipation in the wire bonding area of the lead finger during wire bonding, thereby preventing wire bonding defects. 이를 위해, 본 발명은 히트싱크(4)와, 상기 히트싱크(4) 상부면 중앙에 부착되는 반도체칩(7)과, 상기 반도체칩(7) 주위에 배치되며 와이어 본딩영역(9)을 구비한 리드핑거(1)와, 상기 리드핑거(1)가 히트싱크(4)에 부착되도록 리드핑거(1)와 히트싱크(4) 사이에 개재되는 접착제(adhesive)(2)와, 상기 반도체칩(7)의 본딩패드(10)와 상기 리드핑거(1)의 와이어 본딩영역(9)을 전기적으로 연결하는 와이어(6)를 포함하여서 된 반도체 패키지에 있어서; 상기 리드핑거(1)의 와이어 본딩영역(9)을 제외한 부분의 하부면을 하프 에칭하고, 상기 리드핑거(1) 하부면의 하프 에칭된 영역 내측에만 접착제(adhesive)(2)가 부착되도록 하여 상기 리드핑거(1)의 와이어 본딩영역(9)과 히트싱크(4) 사이에는 접착제(adhesive)(2)가 개재되지 않도록 한 것을 특징으로 하는 반도체 패키지 구조가 제공된다. To this end, the present invention includes a heat sink 4, a semiconductor chip 7 attached to the center of the upper surface of the heat sink 4, and a wire bonding area 9 disposed around the semiconductor chip 7; A lead finger 1, an adhesive 2 interposed between the lead finger 1 and the heat sink 4 so that the lead finger 1 is attached to the heat sink 4, and the semiconductor chip A semiconductor package comprising a wire (6) electrically connecting a bonding pad (10) of (7) and a wire bonding region (9) of the lead finger (1); Half-etch the lower surface of the lead finger 1 except the wire bonding region 9, and attach the adhesive 2 only to the inside of the half-etched region of the lower surface of the lead finger 1 A semiconductor package structure is provided in which an adhesive 2 is not interposed between the wire bonding region 9 of the lead finger 1 and the heat sink 4.

Wire bonding device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Reflective sensor

一种半导体器件X2包括，半导体芯片3，和连接该半导体芯片的一个电极的第1引线1，和连接所述半导体芯片3的另一个电极的第2引线2，和封入所述半导体芯片3、第1引线1的内部端子10及第2引线2的内部端子20的树脂封装4。所述树脂封装4有第1～第4侧面41～44、上面47、底面45。所述第1及第2引线1，2各自具有沿所述树脂封装4的第1侧面41及底面45被延伸的至少一个外部端子11，12。

Wire bonding apparatus

와이어 본딩시 가해지는 힘을 감소시켜, 본딩 패드의 손상 및 층간 절연막의 붕괴를 방지할 수 있는 와이어 본딩 장치를 개시한다. 개시된 본 발명의 와이어 본딩 장치를 이용하는 와이어 본딩 방법은, 캐필러리로부터 돌출된 와이어 선단에 접착 볼을 형성한다. 다음, 상기 접착 볼의 접착면을 디스크 형태로 변형시킨 다음, 상기 디스크 형태의 접착면을 갖는 접착 볼을 상기 본딩 패드에 본딩시킨다. Disclosed is a wire bonding apparatus capable of reducing the force applied during wire bonding, thereby preventing damage to the bonding pad and collapse of the interlayer insulating film. The wire bonding method using the disclosed wire bonding apparatus forms an adhesive ball at the tip of the wire protruding from the capillary. Next, the adhesive surface of the adhesive ball is deformed into a disk shape, and then the adhesive ball having the adhesive surface in the disk shape is bonded to the bonding pad. 와이어 본딩, 접착 볼, 디스크, 저유전, 본딩 패드, 플레이트 Wire Bonding, Adhesive Balls, Disc, Low Dielectric, Bonding Pads, Plates

Leadframe Semiconductor Integrated Circuit Device Using the Same and Method of and Process for Fabricating the Two

리이드프레임 및 그것을 사용한 반도체 집적회로장치와 그 제조방법에 관한 것으로서, 리이드프레임의 표준화 및 LSI패키지의 리플로균열 내성의 향상을 실현하기 위해서, 다이패드의 외형치수를 그 위에 탑재되는 반도체칩의 외형치수보다 작게 하는 것에 의해 반도체칩과 수지의 접착면적을 크게 하고, 또 반도체칩의 외형치수에 띠라서 리이드의 선단을 적절한 길이로 절단하는 것에 의해 외형치수가 다른 각종 반도체칩을 다이패드상에 탑재가능하게 하였다. The present invention relates to a lead frame, a semiconductor integrated circuit device using the same, and a method for manufacturing the same, wherein the shape of a semiconductor chip is mounted on the die pad in order to realize the standardization of the lead frame and the improvement of the resistance to reflow cracking of the LSI package. Various semiconductor chips with different external dimensions are mounted on the die pad by reducing the adhesion area between the semiconductor chip and the resin by making them smaller than the dimensions and cutting the ends of the leads into appropriate lengths according to the external dimensions of the semiconductor chips. Made it possible. 이렇게 하는 것에 의해, 리플로균열 내성이 향상된 LSI패키지를 제공할 수 있고, LSI패키지의 소량다품종화에 대응한 리이드프레임을 제공할 수 있으므로 LSI패키지의 제조코스트를 저감할 수 있다는 효과가 얻어진다. By doing so, it is possible to provide an LSI package with improved reflow crack resistance, and to provide a lead frame corresponding to a small variety of LSI packages, so that the production cost of the LSI package can be reduced. 리이드프레임, 반도체칩, 다이패드, 서스펜션리이드, 리이드, 접착제. Lead frames, semiconductor chips, die pads, suspension leads, leads, adhesives.

Patent JPH0412621B2

PURPOSE:To obtain an aluminum alloy wire having high bonding strength and high corrosion-resisting property by a method wherein the second noble element having no solubility for Al and the third element having solubility for Al are contained in Al. CONSTITUTION:In order to improve the corrosion-resisting property of a corrosion-resisting Al alloy wire, the second noble element having no substantial solubility for Al is contained in Al. The second element consists of one or two kinds selected from the group of Au, Ni and Pd. Also, the third element having solubility for Al is added for the purpose of increasing the degree of hardness of a ball without impairing the corrosion-resisting property of the corrosion- resisting Al alloy wire. Said third element is the element which is selected from the group of Cu, Mg, Ti and Zr. As a result, the corrosion-resisting Al alloy wire having the hardness of Hv30 or above in the ball hardness in normal temperature can be obtained. Accordingly, high bonding strength and a high corrosion-resisting property can be obtained.