CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

A chip package is provided. The chip package comprises a semiconductor chip, an isolation layer, a redistributing metal layer, and a bonding pad. The semiconductor chip has a first conducting pad disposed on a lower surface, and a first hole corresponding to the first conducting pad. The first hole and the isolation layer extend from an upper surface to the lower surface to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has a redistributing metal line corresponding to the first conducting pad, the redistributing metal line is connected to the first conducting pad through the opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the first conducting pad to the bonding pad. A method thereof is also provided. 1. A chip package , comprising:a semiconductor chip with an upper surface and a lower surface, the semiconductor chip having at least one first conducting pad disposed on the lower surface, and a first hole corresponding to the first conducting pad on the lower surface, the first hole extending from the upper surface to the lower surface to expose the first conducting pad;an isolation layer extending from the upper surface to the lower surface, part of the isolation layer positioned in the first hole, wherein the isolation layer has at least one opening to expose the first conducting pad;a redistributing metal layer disposed on the isolation layer and having at least one redistributing metal line corresponding to the first conducting pad, and the redistributing metal line electrically connecting to the first conducting pad through the opening; andat least one bonding pad disposed on the isolation layer and positioned at a side of the semiconductor chip,wherein the redistributing metal line extends to the bonding pad to electrically connect the bonding pad positioned at the ...

Chip package and manufacturing method thereof

本發明提供一種晶片封裝體，包含半導體晶片、絕緣層、重佈局金屬層以及焊接墊。半導體晶片具有第一導電墊設置於下表面，以及第一凹部對應第一導電墊設置，第一凹部與絕緣層均自上表面朝下表面延伸。第一凹部暴露出第一導電墊。部分絕緣層位於第一凹部中且具有開口以暴露出第一導電墊。重佈局金屬層具有對應第一導電墊之重佈局金屬線路，重佈局金屬線路透過開口與第一導電墊連接。焊接墊配置於絕緣層上且位於半導體晶片之一側。重佈局金屬線路延伸至焊接墊，使配置於半導體晶片之下表面之第一導電墊，電性連接於該側之焊接墊。

Chip Package And Manufacturing Method Thereof

本发明提供一种晶片封装体及其制造方法，该晶片封装体包括半导体晶片、绝缘层、重布局金属层以及焊接垫。半导体晶片具有第一导电垫设置于下表面、以及第一凹部对应第一导电垫而设置，第一凹部与绝缘层均自上表面朝下表面延伸。第一凹部暴露出第一导电垫。部分绝缘层位于第一凹部中且具有开口以暴露出第一导电垫。重布局金属层具有对应第一导电垫的重布局金属线路，重布局金属线路通过开口与第一导电垫连接。焊接垫配置于绝缘层上且位于半导体晶片的一侧。重布局金属线路延伸至焊接垫，使配置于半导体晶片的下表面的第一导电垫，电性连接于该侧的焊接垫。本发明可有效缩减或免除现有技术所必须具有的打线间距，以使半导体晶片发挥更高的效能。

Low-radian bonding method for bonding wires of large-sized chip

Chip package and manufacturing method thereof

Chip package and method of manufacturing the same

本发明提供一种晶片封装体及其制造方法，该晶片封装体包括半导体晶片、绝缘层、重布局金属层以及焊接垫。半导体晶片具有第一导电垫设置于下表面、以及第一凹部对应第一导电垫而设置，第一凹部与绝缘层均自上表面朝下表面延伸。第一凹部暴露出第一导电垫。部分绝缘层位于第一凹部中且具有开口以暴露出第一导电垫。重布局金属层具有对应第一导电垫的重布局金属线路，重布局金属线路通过开口与第一导电垫连接。焊接垫配置于绝缘层上且位于半导体晶片的一侧。重布局金属线路延伸至焊接垫，使配置于半导体晶片的下表面的第一导电垫，电性连接于该侧的焊接垫。本发明可有效缩减或免除现有技术所必须具有的打线间距，以使半导体晶片发挥更高的效能。

Chip package and manufacturing method thereof

A chip package is provided. The chip package comprises a semiconductor chip, an isolation layer, a redistributing metal layer, and a bonding pad. The semiconductor chip has a first conducting pad disposed on a lower surface, and a first hole corresponding to the first conducting pad. The first hole and the isolation layer extend from an upper surface to the lower surface to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has a redistributing metal line corresponding to the first conducting pad, the redistributing metal line is connected to the first conducting pad through the opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the first conducting pad to the bonding pad. A method thereof is also provided.

Fingerprint sensing chip packaging method and fingerprint sensing chip package

A fingerprint sensing chip packaging method and package are provided. The method includes: providing a cover plate, providing a fingerprint sensing chip, where a fingerprint sensing region and contact pads at periphery of the region are arranged on a front surface of the chip, electrically connecting the contact pads to a back surface of the chip, forming a first conductive structure electrically connected to the contact pads on the back surface of the chip, laminating the front surface of the chip with a back surface of the cover plate, providing a flexible printed circuit, where a second conductive structure is arranged on a back surface of the circuit and an opening is arranged in the circuit, laminating a front surface of the circuit with the back surface of the cover plate, and electrically connecting the first conductive structure to the second conductive structure.

METHODS OF FORMING WIRE INTERCONNECT STRUCTURES

A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to another location; (c) pressing a portion of the length of wire against the other location using the wire bonding tool; (d) moving the wire bonding tool, and the pressed portion of the length of wire, to a position above the wire bond; and (e) separating the length of wire from a wire supply at the pressed portion, thereby providing a wire interconnect structure bonded to the bonding location. 1. A method of forming a wire interconnect structure , the method comprising the steps of:(a) forming a wire bond at a bonding location on a substrate using a wire bonding tool;(b) extending a length of wire, continuous with the wire bond, to another location;(c) pressing a portion of the continuous length of wire against the other location using the wire bonding tool;(d) moving the wire bonding tool, and the pressed portion of the length of wire, to a position above the wire bond; and(e) separating the continuous length of wire from a wire supply at the pressed portion, thereby providing a wire interconnect structure bonded to the bonding location.2. The method of wherein the pressing step partially cuts the portion of the length of wire to form a partially cut portion of the continuous length of wire.3. The method of further comprising a step of forming a free air ball that is used to form the wire bond in step (a).4. The method of wherein a bonding force and ultrasonic energy are used in forming the wire bond.5. The method of wherein a bond force is used in the pressing step (c).6. The method of wherein ultrasonic energy is not used with the bond force in the pressing step (c).7. The method of further comprising the step of:(d1) extending an additional length of wire from the bonding tool, and above the pressed portion of the continuous length of wire ...

Semiconductor Devices and Methods for Forming a Semiconductor Device

A semiconductor device includes an electrically conductive contact pad structure. Moreover, the semiconductor device includes a bond structure. The bond structure is in contact with the electrically conductive contact pad structure at least at an enclosed interface region. Additionally, the semiconductor device includes a degradation prevention structure laterally surrounding the enclosed interface region. The degradation prevention structure is vertically located between a portion of the bond structure and a portion of the electrically conductive contact pad structure.

Semiconductor device

Provided here are: an electrically-conductive semiconductor substrate with which a semiconductor circuit is formed; an insulating film deposited on a major surface of the electrically-conductive semi-conductor substrate; and a bonding pad having fixing parts fixed onto the insulating film, side wall parts rising up from the fixing parts, and an electrode part connected to the side wall parts and disposed in parallel to the major surface; wherein the electrode part forms, together with the insulating film, a gap region therebetween, and portions of the electrode part where it is connected to the side wall parts are configured to have at least one of: a positional relationship in which they sandwich therebetween a central portion of the electrode part in its bonding region to be bonded to a bonding wire; and a positional relationship in which they surround the central portion.

Method for fabricating an electronic device

The method for fabricating a device includes the following successive steps: providing a first substrate made from silicon of (100), (110) or (111) orientation, from a material of III-IV type or from a material of II-VI type, provided with at least one salient metal pad, and providing a second substrate; fixing the first substrate with the second substrate, the at least one metal pad forming a blocking means preventing movement beyond a threshold position; and performing an anneal of the metal pad so as to melt the metal pad and eliminate the blocking means.

Semiconductor packages and methods of manufacturing the same

A semiconductor package comprises a board including a board pad, a plurality of semiconductor chips mounted on the board, the semiconductor chips including chip pads. Bumps are disposed on the chip pads, respectively, and a wire is disposed between the chip pads and the bumps. The wire electrically connects the chip pads of the plurality of semiconductor chips and the board pad to each other.

Methods of forming wire interconnect structures

A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to another location; (c) pressing a portion of the length of wire against the other location using the wire bonding tool; (d) moving the wire bonding tool, and the pressed portion of the length of wire, to a position above the wire bond; and (e) separating the length of wire from a wire supply at the pressed portion, thereby providing a wire interconnect structure bonded to the bonding location.

SHORT TAIL RECOVERY TECHNIQUES IN WIRE BONDING OPERATIONS

A method of operating a wire bonding machine is provided. The method includes: detecting a short tail condition after formation of a wire bond formed using a wire bonding tool; providing a bond head assembly of a wire bonding machine at an xy location of the wire bonding machine, the bond head assembly carrying the wire bonding tool; lowering the bond head assembly toward a contact surface at the xy location with a wire clamp of the wire bonding machine closed; opening the wire clamp; decelerating the bond head assembly as it is lowered toward the contact surface such that a portion of a wire extends below a tip of the wire bonding tool; closing the wire clamp; and performing a test to determine if an end of the portion of the wire extending below the tip of the bonding tool is in contact with the contact surface. 1. A method of operating a wire bonding machine , the method comprising the steps of:(a) detecting a short tail condition after formation of a wire bond, the wire bond being formed using a wire bonding tool;(b) providing a bond head assembly of a wire bonding machine at an xy location of the wire bonding machine, the bond head assembly carrying the wire bonding tool;(c) lowering the bond head assembly toward a contact surface at the xy location with a wire clamp of the wire bonding machine closed;(d) opening the wire clamp;(e) decelerating the bond head assembly as it is lowered toward the contact surface such that a portion of a wire extends below a tip of the wire bonding tool;(f) closing the wire clamp; and(g) performing a test to determine if an end of the portion of the wire extending below the tip of the bonding tool is in contact with the contact surface.2. The method of wherein the wire bond includes a second bond of a wire loop.3. The method of wherein the wire bond includes a free air ball bond configured to be bonded as a conductive bump.4. The method of wherein an electronic flame off device of the wire bonding machine is operated to direct an ...

Method of Manufacturing Semiconductor Device

A method of manufacturing a semiconductor device which improves the reliability of a semiconductor device. The method of manufacturing the semiconductor device includes the step of connecting a ball portion formed at the tip of a wire with a pad (electrode pad) of a semiconductor chip. The pad is comprised of an aluminum-based material and has a trench in its portion to be connected with the ball portion. The ball portion is comprised of a harder material than gold. The step of connecting the ball portion includes the step of applying ultrasonic waves to the ball portion. 1. A method of manufacturing semiconductor device comprising the steps of:(a) providing a semiconductor chip including a front surface, a protective film formed on the front surface, and a first electrode pad exposed from the protective film in an opening formed in the protective film; and(b) after the step (a), connecting a ball portion formed at a tip of a wire with the first electrode pad,wherein the first electrode pad is comprised of an aluminum-based material,wherein a trench is formed on a portion of the first electrode pad exposed from the protective film,wherein the ball portion is comprised of a harder material than gold, and (b1) contacting the ball portion with the first electrode pad such that the ball portion overlaps the trench of the first electrode pad,', '(b2) after the step (b1), applying a load to the ball portion, and pressing the ball portion in a thickness direction of the first electrode pad, and', '(b3) after the step (b2), applying ultrasonic waves to the ball portion., 'wherein the step (b) comprises the following steps2. The method of manufacturing of the semiconductor device according to claim 1 ,wherein at the step (b3), the ultrasonic waves which oscillate in a first direction along the front surface of the semiconductor chip are applied, andwherein the trench of the first electrode pad has a first portion extending along a second direction crossing the first ...

Methods of forming wire interconnect structures

A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to another location; (c) pressing a portion of the length of wire against the other location using the wire bonding tool; (d) moving the wire bonding tool, and the pressed portion of the length of wire, to a position above the wire bond; and (e) separating the length of wire from a wire supply at the pressed portion, thereby providing a wire interconnect structure bonded to the bonding location.

Method for inserting a wire into a groove of a semiconductor chip, and piece of equipment for implementing such a method

A method for inserting a wire into a longitudinal groove of a semiconductor chip for the assembly thereof, the groove containing a pad made of a bonding material having a set melting point, the method comprises: in a positioning step, placing a longitudinal section of the wire along the groove, in forced abutment against the pad; and, in an insertion step, exposing a zone containing at least one portion of the pad to a processing temperature higher than the melting point of the bonding material and for a sufficient time to make the pad at least partially melt, and causing the wire to be inserted into the groove. The present disclosure also relates to a piece of equipment allowing the insertion method to be implemented.

Light emitting device

発光装置（１０）は、基板（１００）、発光素子（１０２）、端子（１１２，１３２）、及び保護膜（１４０）を備えている。発光素子（１０２）は基板（１００）に形成されており、有機層（１２０）を有している。端子（１１２，１３２）は基板（１００）に形成されており、発光素子（１０２）に接続している。保護膜（１４０）は発光素子（１０２）及び端子（１１２，１３２）を覆っている。そして、端子（１１２，１３２）の表面には、導電繊維が位置している。例えば、端子（１１２，１３２）の表面は、導電繊維を含む導電繊維層（１５０）で形成されている。 The light emitting device (10) includes a substrate (100), a light emitting element (102), terminals (112, 132), and a protective film (140). The light emitting element (102) is formed on the substrate (100) and has an organic layer (120). The terminals (112, 132) are formed on the substrate (100) and are connected to the light emitting element (102). The protective film (140) covers the light emitting element (102) and the terminals (112, 132). And the conductive fiber is located in the surface of a terminal (112,132). For example, the surface of the terminal (112, 132) is formed of a conductive fiber layer (150) containing conductive fibers.

METHOD FOR MAKING AN ELECTRONIC DEVICE

METHOD FOR PRODUCING AN ELECTRONIC DEVICE

Le procédé de fabrication d'un dispositif comporte les étapes successives suivantes : - fournir un premier substrat (1) en silicium d'orientation (100), (110) ou (111) en matériau de type III-IV ou en matériau de type II-VI, muni d'au moins un plot métallique (2) en saillie et fournir un deuxième substrat (3) ; - fixer le premier substrat (1) avec le deuxième substrat (3), le au moins un plot métallique (2) formant un moyen de blocage qui interdit un déplacement au-delà d'une position seuil ; - réaliser un recuit du plot métallique (2) de manière à fondre le plot métallique (2) et supprimer le moyen de blocage. The method of manufacturing a device comprises the following successive steps: - providing a first substrate (1) of orientation silicon (100), (110) or (111) of type III-IV material or of type material II-VI, provided with at least one protruding metal stud (2) and provide a second substrate (3); - Fixing the first substrate (1) with the second substrate (3), the at least one metal stud (2) forming a locking means which prevents movement beyond a threshold position; - Annealing the metal pad (2) so as to melt the metal pad (2) and remove the blocking means.

METHOD OF INSERTING A WIRE INTO A GROOVE OF A SEMICONDUCTOR CHIP, AND EQUIPMENT FOR IMPLEMENTING SUCH A METHOD

L'invention porte sur un procédé d'insertion d'un fil (7a, 7b) dans une rainure longitudinale d'une puce de semi-conducteur (1) en vue de leur assemblage, la rainure contenant un plot (6a, 6b) constitué d'un matériau de liaison présentant une température de fusion déterminée, le procédé comprenant : - dans une étape de mise en place, disposer une section longitudinale du fil (7a, 7b) le long de la rainure, en butée forcée contre le plot (6a, 6b) ; - dans une étape d'insertion, exposer une zone contenant au moins une partie du plot (6a, 6b) à une température de traitement supérieure à la température de fusion du matériau de liaison et pendant une durée suffisante pour faire fondre au moins en partie le plot (6a, 6b), et provoquer l'insertion du fil (7a, 7b) dans la rainure. L'invention porte également sur un équipement permettant de mettre en œuvre le procédé d'insertion. The invention relates to a method for inserting a wire (7a, 7b) into a longitudinal groove of a semiconductor chip (1) for their assembly, the groove containing a pad (6a, 6b) consisting of a bonding material having a determined melting temperature, the method comprising: - in a positioning step, arranging a longitudinal section of the wire (7a, 7b) along the groove, in forced abutment against the stud (6a, 6b); - in an insertion step, exposing an area containing at least part of the pad (6a, 6b) to a treatment temperature above the melting temperature of the bonding material and for a time sufficient to melt at least in part the pad (6a, 6b), and cause the insertion of the wire (7a, 7b) in the groove. The invention also relates to equipment for carrying out the insertion method.

METHOD FOR CONTACTING SEMICONDUCTOR COMPONENTS AND ELECTRICAL CONNECTION USED THEREWITH

CONNECTION BY EMBOITEMENT OF TWO INSERTS WELDED.

La présente invention concerne un dispositif de connexion entre deux composants (1, 1') comprenant un insert conducteur creux (2), dans lequel est emboîté un autre insert conducteur (3), la connexion électrique entre les deux inserts étant assurés à l'aide d'un élément de soudure (4), ainsi qu'un procédé d'hybridation entre deux composants dotés de tels inserts. The present invention relates to a connection device between two components (1, 1 ') comprising a hollow conductive insert (2), in which is inserted another conductive insert (3), the electrical connection between the two inserts being provided to the using a welding element (4), as well as a hybridization process between two components with such inserts.

CONNECTION BY EMBOITEMENT OF TWO INSERTS WELDED.

The device has a hollow conductive male insert (2) into which a conductive female insert (3) is fitted, where an electrical connection between the two inserts is provided by a soldering element (4). The hollow conductive male insert has an annular cross-section that is round, oval or parallelepiped, where length or diameter (D) of one of the inserts is much greater than distance between walls of the two inserts. An adhesive is deposited between the inserts before fitting the inserts on a surface of components (1). An independent claim is also included for a method for assuring hybridization of two components.

METHOD FOR PRODUCING AN INTEGRATED CIRCUIT CHIP AND AN INTEGRATED CIRCUIT CHIP

Le procédé de fabrication du dispositif comporte la fourniture d'un premier empilement comportant: ○ un premier substrat (1) comportant au moins une surface principale munie d'au moins une première zone de contact électrique (6a), ○ un deuxième substrat muni d'une entretoise (4) saillante, Le premier substrat (1) est assemblé avec le deuxième substrat de manière à définir au moins une première rainure latérale (3a) comportant la première zone de contact électrique (6a), la première rainure latérale (3a) étant délimitée par le premier substrat (1), le deuxième substrat et l'entretoise (4). Lors de l'assemblage du deuxième substrat avec le premier substrat (1) le premier substrat (1) comporte au moins une première protubérance (8a) agencée pour former une butée et limiter le déplacement de l'entretoise (4) par rapport au premier substrat (1) selon au moins une première direction (X) passant par la première rainure latérale (3a) et l'entretoise (4) et une deuxième direction (Y) parallèle à l'axe longitudinal de la première rainure (3a) et perpendiculaire à la première direction (X). The manufacturing method of the device comprises the provision of a first stack comprising: a first substrate (1) comprising at least one main surface provided with at least a first electrical contact zone (6a), a second substrate provided with a protruding spacer (4), the first substrate (1) is assembled with the second substrate so as to define at least one first lateral groove (3a) having the first electrical contact zone (6a), the first lateral groove (3a) ) being delimited by the first substrate (1), the second substrate and the spacer (4). During the assembly of the second substrate with the first substrate (1) the first substrate (1) comprises at least a first protrusion (8a) arranged to form a stop and limit the displacement of the spacer (4) relative to the first substrate (1) in at least a first direction (X) passing through the first lateral groove ...

Method and apparatus for manufacturing transistors

METHOD FOR PRODUCING AN INTEGRATED CIRCUIT CHIP AND INTEGRATED CIRCUIT CHIP.

Le procédé de fabrication du dispositif comporte la fourniture d'un premier empilement comportant: ○ un premier substrat (1) comportant au moins une surface principale munie d'au moins une première zone de contact électrique (6a), ○ un deuxième substrat muni d'une entretoise (4) saillante, Le premier substrat (1) est assemblé avec le deuxième substrat de manière à définir au moins une première rainure latérale (3a) comportant la première zone de contact électrique (6a), la première rainure latérale (3a) étant délimitée par le premier substrat (1), le deuxième substrat et l'entretoise (4). Lors de l'assemblage du deuxième substrat avec le premier substrat (1) le premier substrat (1) comporte au moins une première protubérance (8a) agencée pour former une butée et limiter le déplacement de l'entretoise (4) par rapport au premier substrat (1) selon au moins une première direction (X) passant par la première rainure latérale (3a) et l'entretoise (4) et une deuxième direction (Y) parallèle à l'axe longitudinal de la première rainure (3a) et perpendiculaire à la première direction (X). The method of manufacturing the device comprises the provision of a first stack comprising: ○ a first substrate (1) comprising at least one main surface provided with at least a first electrical contact area (6a), ○ a second substrate provided with 'a protruding spacer (4), The first substrate (1) is assembled with the second substrate so as to define at least a first lateral groove (3a) comprising the first electrical contact zone (6a), the first lateral groove (3a ) being delimited by the first substrate (1), the second substrate and the spacer (4). When assembling the second substrate with the first substrate (1) the first substrate (1) comprises at least a first protuberance (8a) arranged to form a stop and limit the movement of the spacer (4) relative to the first substrate (1) in at least a first direction (X) passing through the first lateral ...

Roughened bonding pad and bonding wire surfaces for low pressure wire bonding

An intermediate semiconductor structure and method for low-pressure wire bonding that reduces the propensity of dielectric material to mechanical failure due to any wire bonding stresses. Roughened surfaces such as metal pillars or metal dendrites are provided on a bonding pad, bonding wire or both. These roughened surfaces increase reactivity between the bond wire and the bond pad to form strong bonds. This increased activity as a result of the roughened bonding pad and/or wire surfaces reduce the amount of pressure, temperature and energy required for wire bonding, which in turn, avoids damage to the bonding pad as well as the semiconductor substrate.

Lead frame with notched lead ends

A lead frames has a forked top portion which has a recessed portion adjusted for receipt of a wire so that the wire is so caught by the forked top portion as to prevent the wire from being largely carried. Even if the density of the wires is high, the wires are not carried by the flow of the molten resin so that the wires are kept from contact with each other thereby avoiding short circuits. At the corners, the distance of the adjacent two wires is narrower than the other positions. Notwithstanding, the wires at the corners are also prevented by the forked top portion of the lead frame from being largely carried by the flow of the molten resin so that the wires are kept from contact with each other thereby avoiding short circuit.

Semiconductor device and the method for forming semiconductor device

一种半导体装置包括导电接触焊盘结构。此外，所述半导体装置包括结合结构。所述结合结构至少在封闭的界面区域处与导电接触焊盘结构接触。附加地，半导体装置包括侧向包围所述封闭的界面区域的劣化防止结构。所述劣化防止结构垂直方向上位于所述结合结构的一部分与所述导电接触焊盘结构的一部分之间。

Semiconductor device and manufacturing method thereof

A method of making a semiconductor device comprises the steps of coating a first face of an insulative board (1) with a thermally plastic resin (2), bonding at least one semiconductor element (3) onto the thermally plastic resin (2), piercing the thermally plastic resin (2) and the insulative board (1) with at least one capillary that holds a metal wire (4), forming a metal ball (4b) and pulling out the capillary from the insulative board (1) and the thermally plastic resin (2), pressing the capillary onto an electrode (3a) of the semiconductor element (3) and cutting off an extra wire, and attaching at least one metal bump (6) to the second face of the insulative board (1) so as to be connected to the metal ball (4a).

METHOD FOR CONTACTING SEMICONDUCTOR COMPONENTS AND ELECTRICAL CONNECTION MADE THEREBY

L'INVENTION CONCERNE UN PROCEDE POUR CONTACTER DES COMPOSANTS A SEMICONDUCTEURS 4 AVEC UN FIL DE CONTACT 6. L'EXTREMITE DU FIL DE CONTACT 6, QUI EST ELOIGNEE DU COMPOSANT A SEMICONDUCTEURS 4, EST FIXEE A UN SUPPORT DE RACCORDEMENT 2, PAR UN ECRASEMENT PAR FORMES COMPLEMENTAIRES, PAR SERRAGE OU PAR MATAGE. APPLICATION AU CONTACTAGE DE DIODES LUMINESCENTES, DE DISPOSITIFS D'AFFICHAGE, DE PHOTODIODES, ET D'AUTRES DISPOSITIFS SIMILAIRES.

Fabrication of electrical devices

Methods for inserting wires into grooves of semiconductor chips, and parts of apparatus for carrying out such methods

Light emitting apparatus

A light emitting apparatus (10) is provided with a substrate (100), a light emitting element (102), terminals (112, 132), and a protection film (140). The light emitting element (102) is formed on the substrate (100), and has an organic layer (120). The terminals (112, 132) are formed on the substrate (100), and are connected to the light emitting element (102). The light emitting element (102) and the terminals (112, 132) are covered with the protection film (140). On each of the surfaces of the terminals (112, 132), a conductive fiber is positioned. For instance, each of the surfaces of the terminals (112, 132) is formed of a conductive fiber layer (150) containing the conductive fiber.

The exposed encapsulating structure of the more lateral leads of high density and its production method

本发明公开了一种高密度多侧面引脚外露的封装结构及其生产方法。封装结构包括本体，基岛和引脚；所述基岛和所述引脚设于所述本体的底部，且所述引脚的底面裸露于所述本体的底面，且所述引脚向所述本体的多个侧面延伸并伸出所述本体之外；所述本体包括设于所述基岛并与所述引脚连接的集成电路，以及用于封装所述集成电路、所述基岛和所述引脚的塑封体；所述塑封体的底面和所述引脚的底面，处于同一水平面；所述引脚包括与所述基岛隔离的第一引脚。本发明方案可减小封装结构的厚度、体积，减少封装内阻和热阻，提高产品性能及其可靠性，同时增大了应用范围。

Connection between two soldered inserts and method of manufacturing the same

La présente invention concerne un dispositif de connexion entre deux composants (1, 1') comprenant un insert conducteur creux (2), dans lequel est emboîté un autre insert conducteur (3), la connexion électrique entre les deux inserts étant assurés à l'aide d'un élément de soudure (4), ainsi qu'un procédé d'hybridation entre deux composants dotés de tels inserts. The present invention relates to a connection device between two components (1, 1 ') comprising a hollow conductive insert (2), in which is inserted another conductive insert (3), the electrical connection between the two inserts being provided to the using a welding element (4), as well as a hybridization process between two components with such inserts.

IC (integrated circuit) encapsulation with non-horizontal die pads and corresponding lead frames

本发明涉及具有非水平管芯垫及相应引线框的IC封装。多构件集成电路(IC)封装具有基础构件(例如，插入器)限定IC封装的基底，多个管芯垫从基底延伸出去且成为IC封装的侧壁，一个或多个IC管芯，每个均安装在管芯之一的内表面上，并且键合丝线将IC管芯电连接到另一个IC封装组件上，例如插入器或另一个管芯上。通过安装管芯至非水平侧壁上，IC封装可提供相比于含有管芯堆叠的传统3D IC封装更有效的散热性能。

Method and device for fabricating an assembly of at least two microelectronic chips

The method enables an assembly of chips, initially formed on a wafer, to be formed. Each chip comprises two parallel main faces joined by side faces. At least one of the side faces comprises at least one groove for housing a thread element. The wafer is first of all stuck onto a flexible film and the chips are then cut. The film is then deformed to space the chips apart from one another and to make the grooves accessible. A daisy chain is then formed joining the chips via at least one thread element, each chip being inserted in the daisy chain by inserting the thread in the groove of said chip and then removing the chip from the deformable film.

Electronic circuit arrangement and method of manufacturing the same

The present invention relates to an electronic circuit arrangement ( 10 ) comprising: a substrate ( 12 ) having a first surface ( 12 a ) and a second surface ( 12 b ), an electronic circuit, an electrical connection part ( 16 ) for providing an electrical connection to the electronic circuit and being arranged on the first surface ( 12 a ), and at least one electrical wire ( 18 ). The electrical wire ( 18 ) comprises at least one conductive core ( 20 ) and an isolation ( 22 ) surrounding the conductive core ( 20 ). An end portion ( 18 a ) of the electrical wire ( 18 ) is an isolation-free portion for allowing access to the conductive core ( 20 ), wherein the end portion ( 18 a ) of the electrical wire ( 18 ) is connected to the electrical connection part ( 16 ). At least one through-hole ( 24 ) extending from the first surface ( 12 a ) to the second surface ( 12 b ) is provided in the substrate ( 12 ), wherein the electrical wire ( 18 ) is arranged through the through-hole ( 24 ).

Method for bonding a wire to a metal layer

1294770 Soldering HITACHI Ltd 22 Dec 1970 [29 Dec 1969] 60892/70 Heading B3R [Also in Division H1] In connecting a wire to a metal layer on a substrate the wire is guided through the passage of a capillary tube and a portion of the wire extending from the tube is pressed against the layer by the tube, the tube is heated to a temperature not lower than the melting point of the layer but lower than the melting point of the wire whereby the portion of the wire is pressed into the metal layer while metal of the layer is melted and the layer is then cooled to bond the wire to the layer, the tool being then moved away. An electrode 2, Fig. la, printed on a ceramic substrate 1 of a semi-conductor device carries a lead-tin solder layer 3 and a silver wire 5 is guided through the passage of a capillary tube 4. A head 6 is formed on the wire by burning in a hydrogen flame. The tube 4 is heated by resistance means to a temperature not lower than the melting point of the solder 3, e.g. to 300‹ C. and the substrate 1 may be heated say to 100‹ C., the tube 4 is lowered to press the head 6 against the solder and heat conducted to the head 6 from the tube melts the solder in contact therewith and the head becomes buried in the solder. A gas is then directed from a jet on to the melted solder to solidify the solder and then the tool is moved upward over the wire. The wire may be connected to a solder layer forming an electrode on a semi-conductor substrate or on a junction type transistor. The tool after being moved upwardly over the wire may be then moved towards another part of the layer 3 without cutting the wire so that a hook shaped part 9, Fig. 2a, is similarly fixed in the solder layer and cooled by gas from nozzle 7. The upright portion of the wire is then burned through by a hydrogen flame to form a balled ends on the wire.

System having semiconductor die mounted in die-receiving area having different shape than die

Electronic systems utilizing a plurality of integrated circuit packages having at least some large gaps between edges of a semiconductor die and the inner ends of package conductors defining a die-receiving area, one or more bond wire support structure are disposed in the gap, thereby causing a long bond wire to behave as two or more shorter bond wires. The bond wires are tacked to a top surface of the support structure by various alternative means. Alternatively, a "jumper" structure having conductive traces of graduated length can be disposed in the die-receiving area between the die and the edges of the die-receiving area, providing an intermediate connection between the die and the leads of the package, thereby permitting short bond wires to be used in lieu of long bond wires.

Method of bonding gold or gold alloy wire to lead tin solder

A compression bond is formed between a gold or gold alloy wire and lead/tin solder by forming a head on the wire and forcing the head into a pad of the solder by thermosonic, or thermocompression, or ultrasonic compression bonding techniques. This forms a gold/tin intermetallic compound which in turn forms the bond. The head of the wire is maintained out of contact with any underlying surface, and surrounded by the solder.

Semiconductor device, method for fabricating the semiconductor device, lead frame and method for producing the lead frame

A semiconductor device includes a semiconductor element, a resin package sealing the semiconductor element, resin projections protruding downward from a mounting surface of the resin package, metallic film portions provided to the resin projections, and connecting members electrically connecting the semiconductor elements to the metallic film parts. Outer circumference surfaces of the resin package are upright surfaces defined by cutting.

Patent DE3028570C2

Patent JPS5753953A

Methods of forming wire interconnect structures

一種形成一導線互連結構的方法包含以下步驟：(a)利用一導線接合工具形成一導線接合於一基板上之一接合位置處；(b)使與該導線接合接續之一段導線延伸至另一位置；(c)利用該導線接合工具將該段導線之一部分壓抵於該另一位置上；(d)將該導線接合工具、以及該段導線之該被壓抵部分移動至該導線接合上方之一位置；以及(e)使該段導線在該被壓抵部分處自一導線供應源分離，藉此提供接合至該接合位置之一導線互連結構。

Semiconductor device

Method for manufacturing an electronic device, and electronic device

The method for manufacturing the device comprises supplying a first stack comprising: ° a first substrate (1) comprising at least one main surface provided with at least one first electrical contact zone (6a); ° a second substrate provided with a projecting spacer (4). The first substrate (1) is assembled with the second substrate so as to define at least one first lateral groove (3a) comprising the first electrical contact zone (6a), the first lateral groove (3a) being delimited by the first substrate (1), the second substrate and the spacer (4). When assembling the second substrate with the first substrate (1), the first substrate (1) comprises at least one first protrusion (8a) arranged to form a stop and to limit the movement of the spacer (4) relative to the first substrate (1) in at least one first direction (X) passing through the first lateral groove (3a) and the spacer (4) and one second direction (Y) parallel to the longitudinal axis of the first groove (3a) and perpendicular to the first direction (X).

Multi-pitch leads

In some examples, a system comprises a die having multiple electrical connectors extending from a surface of the die and a lead coupled to the multiple electrical connectors. The lead comprises a first conductive member; a first non-solder metal plating stacked on the first conductive member; an electroplated layer stacked on the first non-solder metal plating; a second non-solder metal plating stacked on the electroplated layer; and a second conductive member stacked on the second non-solder metal plating, the second conductive member being thinner than the first conductive member. The system also comprises a molding to at least partially encapsulate the die and the lead.

半导体组件及其制造方法

本发明提供了一种半导体组件及其制造方法。半导体组件包括基板和焊盘。焊盘位于基板上并且具有上表面和狭槽，其中，狭槽相对于上表面向内凹进。本发明中在焊盘上包括狭槽，可以使得在焊接过程中容纳焊盘部分的变形和/或减小或释放焊盘的应力，可以缩小相邻两个焊盘之间的间距。

Method and arrangement for assembly of microchips into a separate substrate

Method and arrangement for assembling one or more microchips (415; 615; 715; 815; 915; 1015) into one or more holes (422; 722), respectively, in a substrate surface (421; 721) of a separate receiving substrate (420; 720; 820; 1020). The holes (422; 722) of the substrate is for microchip insertion out-of-plane in relation to said substrate surface. Each of said microchips is provided with a ferromagnetic layer (213; 613) of ferromagnetic material. The microchips are placed (503) on said substrate surface (421; 721) and it is applied and moved (504) one or more magnetic fields affecting said ferromagnetic layer (213; 613) of each microchip such that the microchips thereby become out-of-plane oriented in relation to said substrate surface (421; 721) and move over the substrate surface (421; 721) until assembled into said holes (422; 722).

用于将配线插入到半导体芯片的沟槽中的方法以及用于实现该方法的设备

本发明涉及一种用于将配线(7a、7b)插入半导体芯片(1)的纵向沟槽中以进行其组装的方法，所述沟槽包含垫(6a、6b)，所述垫由具有设定熔点的结合材料制成，所述方法包括：在定位步骤中，沿着所述沟槽将所述配线(7a、7b)的纵向区段放置成与所述垫(6a、6b)强制邻接；以及在插入步骤中，将包含所述垫(6a、6b)的至少一部分的区域暴露于高于所述结合材料的所述熔点的处理温度并且达足够的时间以使所述垫(6a、6b)至少部分熔化，并使所述配线(7a、7b)插入到所述沟槽中。本发明还涉及容许实施所述插入方法的设备。

Semiconductor device package and method for packaging the same

A semiconductor device package includes a first semiconductor device; a second semiconductor device; and a first redistribution layer disposed on the first semiconductor device and having a side wall defining an opening that exposes the first semiconductor device. The side wall of the first redistribution layer has an average surface roughness (Ra) in a range up to 2 micrometers (μm).

System for inserting a wire into a semiconductor chip

A system for inserting a wire into a semiconductor chip system includes positioning members for deploying and moving a length of the wire between a first end and a second end of a workspace. A handling device of the system is configured to handle the semiconductor chip, and is capable of placing the chip in an insertion position in which a groove of the chip is placed opposite the wire. A positioning member of the system is configured to arrange a longitudinal section of the wire along the groove, in forced abutment against a pad of the chip made of a bonding material having a melting point. A heating member of the system is configured to heat a zone comprising the pad to a processing temperature above the melting point to melt the pad and provoke insertion of the wire into the groove.

半导体封装件和制造半导体封装件的方法

本发明提供一种半导体封装件和制造半导体封装件的方法。该半导体封装件包括：包括板焊盘的板；安装在板上的多个半导体芯片，半导体芯片包括芯片焊盘。突起分别设置在芯片焊盘上，引线设置在芯片焊盘和突起之间。引线将多个半导体芯片的芯片焊盘和板焊盘彼此电连接。

半導體裝置

具備：導電性半導體基板(2)，形成有半導體電路；絕緣膜(3)，沉積在導電性半導體基板(2)的主要表面；以及連接墊(4)，具有固定部(4s)、側壁部(4w)與電極部(4j)，固定部(4s)固定於絕緣膜(3)，側壁部(4w)從固定部(4s)豎立，電極部(4j)連接於側壁部(4w)並相對於上述主要表面平行配置；其中電極部(4j)與絕緣膜(3)之間形成空隙部(4g)；且電極部(4j)連接於側壁部(4w)的部分處於至少以下任一項的位置關係而構成：夾置電極部(4j)與連接線(5)的接合區域的(R5)中央部；以及圍繞中央部。

반도체 장치

반도체 회로가 형성된 도전성 반도체 기판(2)과, 도전성 반도체 기판(2)의 주면에 퇴적된 절연막(3)과, 절연막(3)에 고정된 고정부(4s)와, 고정부(4s)로부터 올라가는 측벽부(4w)와, 측벽부(4w)에 이어지고, 주면에 대해서 평행하게 배치된 전극부(4j)를 갖는 본딩 패드(4)를 구비하고, 전극부(4j)는, 절연막(3)과의 사이에 공극부(4g)를 형성하고, 또한, 측벽부(4w)에 이어지는 부분이, 본딩 와이어(5)와의 접합 영역(R5)의 중앙부를 사이에 두는 것, 및 중앙부를 둘러싸는 것 중 적어도 어느 하나의 위치 관계에 있도록 구성했다.

Semiconductor device including bond pad with fixing parts fixed onto insulating film

Provided here are: an electrically-conductive semiconductor substrate with which a semiconductor circuit is formed; an insulating film deposited on a major surface of the electrically-conductive semi-conductor substrate; and a bonding pad having fixing parts fixed onto the insulating film, side wall parts rising up from the fixing parts, and an electrode part connected to the side wall parts and disposed in parallel to the major surface; wherein the electrode part forms, together with the insulating film, a gap region therebetween, and portions of the electrode part where it is connected to the side wall parts are configured to have at least one of: a positional relationship in which they sandwich therebetween a central portion of the electrode part in its bonding region to be bonded to a bonding wire; and a positional relationship in which they surround the central portion.

Halbleiterbauelemente und Verfahren zum Bilden eines Halbleiterbauelements

Ein Halbleiterbauelement (100, 200, 300, 400, 500, 600, 700, 800), umfassend:eine elektrisch leitfähige Kontaktanschlussflächenstruktur (110);eine Bondstruktur (150), die zumindest an einer umschlossenen Schnittstellenregion (160) in Kontakt mit der elektrisch leitfähigen Kontaktanschlussflächenstruktur (110) ist; undeine Verschlechterungs-Präventionsstruktur (140), die die umschlossene Schnittstellenregion (160) lateral umgibt, wobei die Verschlechterungs-Präventionsstruktur (14) vertikal zwischen einem Abschnitt der Bondstruktur (150) und einem Abschnitt der elektrisch leitfähigen Kontaktanschlussflächenstruktur (110) angeordnet ist,wobei die Bondstruktur (150) zusätzlich an einer Peripherie-Schnittstellenregion in Kontakt mit der elektrisch leitfähigen Kontaktanschlussflächenstruktur (110) ist,wobei die Peripherie-Schnittstellenregion die Verschlechterungs-Präventionsstruktur (140) lateral umgibt.

半导体器件的制造方法

本发明涉及半导体器件的制造方法，其提高半导体器件的可靠性。半导体器件的制造方法包括连接在线的顶端形成的球部与半导体芯片的焊盘(电极焊盘)的步骤。焊盘包含铝基材料，并且在其要与球部连接的部分中具有沟槽。球部包含比金硬的材料。连接球部的步骤包括向球部施加超声波的步骤。

半导体装置

本发明构成为具备：导电性半导体基板(2)，形成有半导体电路；绝缘膜(3)，堆积于导电性半导体基板(2)的主面；以及接合焊盘(4)，具有固定于绝缘膜(3)的固定部(4s)、从固定部(4s)立起的侧壁部(4w)、以及与侧壁部(4w)相连并配置为相对于主面平行的电极部(4j)，电极部(4j)在与绝缘膜(3)之间形成空隙部(4g)，并且与侧壁部(4w)相连的部分处于夹住与接合线(5)接合的接合区域(R5)的中央部、和包围中央部中的至少任意一个位置关系。

Procede de fabrication d’une puce a circuit integre et puce a circuit integre

La fabrication d'une puce à circuit intégré utilise un empilement comportant: ○ un premier substrat (1) muni d'une surface principale et une protubérance (6) en saillie de la surface principale, ○ un deuxième substrat (2) comportant une surface principale, ○ une entretoise (4) séparant les premier et deuxième substrats (1, 2) pour définir une rainure latérale (3a) délimitée par les premier et deuxième substrats (1) et l'entretoise (4), la protubérance (6) faisant saillie dans la rainure latérale (3a). Un élément filaire définissant au moins une cavité est installé dans la rainure latérale (3a). La protubérance (6) forme une butée empêchant la sortie de l'élément filaire. La protubérance (6) est agencée à distance de l'entretoise (4) pour partiellement refermer la rainure latérale (3a). La protubérance (6) s'introduit dans la cavité de l'élément filaire de sorte que l'élément filaire s'installe dans la rainure latérale (3a) par rotation autour de la protubérance (6).

Wire bonded semiconductor device and method of manufacturing the same

A method of packaging a semiconductor device includes: bonding a ball (304) at an end of a bond wire (302) to a bond pad (204) of a semiconductor device die (200) in an aperture of a shielding layer (206) of the semiconductor device; and sealing the part of the bond pad (204) exposed by the aperture of the shielding layer (206) by deforming the ball (304) of the bond wire (302) to fill the aperture of the shielding layer (206). The aperture of the shielding layer (206) includes an edge wall, and exposes a part of the bond pad (204). The shielding layer (206) covers a remaining part of the bond pad (204). The aperture of the shielding layer (206) is completely filled with the ball (304) of the bond wire (302), thereby deforming the edge wall of the shielding layer (206).

功率半导体接触结构及其生产方法

一种用于功率半导体模块的功率半导体接触结构，该功率半导体接触结构具有至少一个衬底(1)以及作为电极的金属模制本体(2)，该衬底和金属模制本体通过基本上无中断的烧结层(3a)而一者烧结在另一者顶上，该烧结层具有多个具有变化的厚度的区域。该金属模制本体(2)在此采取挠性接触膜(5)的形式，该挠性接触膜的厚度使得此接触膜通过其面向该烧结层(3a)的这侧(4)基本上覆盖整个表面积地烧结到该烧结层的这些具有变化的厚度的区域上。还描述了一种用于在功率半导体模块中形成具有衬底和金属模制本体的功率半导体接触结构的方法。形成该功率半导体接触结构是如下进行的：首先向金属模制本体(2)或该衬底施加具有局部变化的厚度的烧结材料层，然后通过使用该烧结材料层的连接导通特性将接触膜(5)与衬底(1)烧结在一起，接触膜(5)被制成为发展其区别性形式以便应对烧结材料层(3a)的变化的厚度。

功率半导体接触结构及其生产方法

一种用于功率半导体模块的功率半导体接触结构，该功率半导体接触结构具有至少一个衬底(1)以及作为电极的金属模制本体(2)，该衬底和金属模制本体通过基本上无中断的烧结层(3a)而一者烧结在另一者顶上，该烧结层具有多个具有变化的厚度的区域。该金属模制本体(2)在此采取挠性接触膜(5)的形式，该挠性接触膜的厚度使得此接触膜通过其面向该烧结层(3a)的这侧(4)基本上覆盖整个表面积地烧结到该烧结层的这些具有变化的厚度的区域上。还描述了一种用于在功率半导体模块中形成具有衬底和金属模制本体的功率半导体接触结构的方法。形成该功率半导体接触结构是如下进行的：首先向金属模制本体(2)或该衬底施加具有局部变化的厚度的烧结材料层，然后通过使用该烧结材料层的连接导通特性将接触膜(5)与衬底(1)烧结在一起，接触膜(5)被制成为发展其区别性形式以便应对烧结材料层(3a)的变化的厚度。

Multi-pitch leads

In some examples, a system comprises a die having multiple electrical connectors extending from a surface of the die and a lead coupled to the multiple electrical connectors. The lead comprises a first conductive member; a first non-solder metal plating stacked on the first conductive member; an electroplated layer stacked on the first non-solder metal plating; a second non-solder metal plating stacked on the electroplated layer; and a second conductive member stacked on the second non-solder metal plating, the second conductive member being thinner than the first conductive member. The system also comprises a molding to at least partially encapsulate the die and the lead.

Self-locking wire bond structure and method of making the same

A complimentary self-locking wire bond structure and technique is introduced, where the bonding force is focused at the tip of the bond wire and a barb-type construction is utilized to enhance the durability and reduce the insertion forces. The end of wire bond has an “arrowhead” or similar functioning fastener such that the force is focused to a point that pierces the bond pad in a local area. The bond pad may be self-healing, such that the bond pad is made to close over and seal or lock the barb into the underpad layer below the pad, while making electrical contact with the wire bond at the bond pad surface. The bond pad may have a cushioning layer or cavity below it to dampen the piecing force of the pointed barb. A thin metal pad may also be formed over the compliant underpad layer for force absorption.

Methods for forming semiconductor devices with stepped bond pads

A method for forming a semiconductor structure includes forming a bond pad over a last metal layer of the semiconductor structure wherein the bond pad includes a wire bond region; and recessing the wire bond region such that the wire bond region has a first thickness and a region of the bond pad outside the wire bond region has a second thickness that is greater than the first thickness.

Textured bond pads

In some examples, a package comprises a semiconductor die and a bond pad formed upon the semiconductor die. The bond pad has a protrusion on a top surface of the bond pad. The package also comprises a metal contact and a bond wire coupled to the protrusion and to the metal contact.

Verfahren und vorrichtung zur herstellung eines montageverbunds aus mindestens zwei elektronischen mikrochips

半导体设备封装和其封装方法

本公开提供一种半导体设备封装和其封装方法。其中，该半导体设备封装包含第一半导体设备；第二半导体设备；以及第一重新分布层，其安置在所述第一半导体设备上且具有限定暴露所述第一半导体设备的开口的侧壁。所述第一重新分布层的所述侧壁具有高达2微米(μm)范围内的平均表面粗糙度(Ra)。

芯片封装结构及其制作方法

本发明提供一种芯片封装结构，包括一芯片、一无源元件以及至少两条金属线。芯片的第一焊垫、第二焊垫与接垫设置于集成电路上，且第二焊垫以及接垫系与集成电路分隔开。各第二焊垫分别电性连接至相对应的接垫中的一者。无源元件设置于芯片上，且包括两个电极。各电极分别电性连接至与黏着于相对应的接垫中的一者。各金属线设置于芯片上，其一端分别与相对应的第二焊垫中的一者连接，另一端分别与第一焊垫中的一者连接。

Semiconductor component and manufacturing method thereof

A semiconductor component is provided. The semiconductor component includes a substrate and a pad. The pad has an upper surface and a slot, wherein the slot is recessed with respect to the upper surface.

半導體元件及其製造方法

本發明提供了一種半導體元件及其製造方法。半導體元件包括基板和焊盤。焊盤位於基板上並且具有上表面和狹槽，其中，狹槽相對于上表面向內凹進。本發明中在焊盤上包括狹槽，可以使得在焊接過程中容納焊盤部分的變形和/或減小或釋放焊盤的應力，可以縮小相鄰兩個焊盤之間的間距。

Semiconductor component and manufacturing method thereof

A semiconductor component is provided. The semiconductor component includes a substrate (110) and a pad (120). The pad (120) has an upper surface and a slot (120r), wherein the slot (120r) is recessed with respect to the upper surface of the pad (120). The slot (120r) can receive deformed pad material resulting from the wire connecting process. The slot (120r) can thereby prevent the pad (120) from cracking or touching adjacent pads due to over-deformation or cause damage to the passivation layer (130).

System and method for increasing the strength of a bond made by a small diameter wire in ball bonding

A system and method is disclosed for increasing the strength of a bond made by a small diameter wire in ball bonding. In one embodiment of the invention a structure for receiving a ball bond comprises substrate material that has portions that form a substrate cavity and a wire bond pad that covers and fills the substrate cavity. The wire bond pad also has portions that form a wire bond cavity for receiving the ball bond. The ball is wirebonded to the sides and bottom of the wire bond cavity. The sides of the wire bond cavity provide additional strength to the bond to resist shear and tensile forces that may act on the wire.

键合焊盘上的钝化材料的图案及其制造方法

本发明的实施例涉及键合焊盘上的钝化材料的图案及其制造方法。一种方法包括在电子组件上形成焊盘。该焊盘包括导电材料。该方法进一步包括在导电材料的表面上提供钝化材料，以及从该表面去除钝化材料以暴露导电材料的部分从而形成包括导电材料和钝化材料的键合焊盘。

Semiconductor device and method for packaging

A method of packaging a semiconductor device includes: bonding a ball at an end of a bond wire to a bond pad of a semiconductor device die in an aperture of a shielding layer of the semiconductor device; and sealing the part of the bond pad exposed by the aperture of the shielding layer by deforming the ball of the bond wire to fill the aperture of the shielding layer. The aperture of the shielding layer includes an edge wall, and exposes a part of the bond pad. The shielding layer covers a remaining part of the bond pad. The aperture of the shielding layer is completely filled with the ball of the bond wire, thereby deforming the edge wall of the shielding layer.

半导体器件、封装结构及封装结构的制备方法

本公开提供一种半导体器件、封装结构及封装结构的制备方法，涉及半导体封装技术领域。该封装结构包括芯片组、导电膜层、引线和封装层，其中：芯片组，包括沿垂直方向叠层设置的多个芯片单元，且各芯片单元至少一端形成有凹槽；导电膜层，随形贴合于凹槽表面；引线，一端连接于导电膜层，另一端延伸至芯片单元外侧；封装层，至少设于各芯片单元之间，用于将各芯片固定连接。本公开的封装结构可减小封装结构的尺寸，提高存储容量。

形成键合焊盘的方法和键合焊盘

本发明涉及形成键合焊盘的方法和键合焊盘。各种实施例提供形成键合焊盘的方法，其中所述方法包括提供原键合焊盘，并且在原键合焊盘的接触表面处形成下凹结构，其中所述下凹结构包括关于接触表面倾斜的侧壁。

在線接合操作中之短尾恢復技術

提供一種線材接合機的操作方法。該方法包括：在線材接合部形成之後檢測短尾情況；將線材接合機的接合頭組件設置在線材接合機的xy位置處；使接合頭組件朝向位於xy位置處的接觸表面下降；打開線材夾；使接合頭元件減速，從而使得線材的一部分延伸到線材接合工具的末端下方；閉合線材夾；以及執行測試，以確認線材延伸到線材接合工具的末端下方的端部是否與接觸表面接觸。

Textured bond pads

In some examples, a package comprises a semiconductor die and a bond pad formed upon the semiconductor die. The bond pad has a protrusion on a top surface of the bond pad. The package also comprises a metal contact and a bond wire coupled to the protrusion and to the metal contact.

Textured bond pads

In some examples, a package comprises a semiconductor die and a bond pad formed upon the semiconductor die. The bond pad has a protrusion on a top surface of the bond pad. The package also comprises a metal contact and a bond wire coupled to the protrusion and to the metal contact.

Textured Bond Pads

In some examples, a package comprises a semiconductor die and a bond pad formed upon the semiconductor die. The bond pad has a protrusion on a top surface of the bond pad. The package also comprises a metal contact and a bond wire coupled to the protrusion and to the metal contact.

在封装之间具有插头-插座型线连接的半导体封装上封装

一种半导体封装上封装包括下部封装、叠置在所述下部封装上的上部封装、结合至所述下部封装的上部和所述上部封装的下部中的任何一者的插头线以及结合至所述下部封装的上部和所述上部封装的下部中的任何一者的插座线。将所述插头线插入到所述插座线内，从而使所述上部和下部封装电连接。

Power semiconductor contact structure and method for the production thereof

A power semiconductor contact structure for power semiconductor modules, which has at least one substrate (1) and a metal moulded body (2) as an electrode, which are sintered one on top of the other by means of a substantially uninterrupted sintering layer (3a) with regions of varying thickness. The metal moulded body (2) takes the form here of a flexible contacting film (5) of such a thickness that this contacting film is sintered with its side (4) facing the sintering layer (3a) onto the regions of varying thickness of the sintering layer substantially over the full surface area. A description is also given of a method for forming a power semiconductor contact structure in a power semiconductor module that has a substrate and a metal moulded body. The forming of the power semiconductor contact structure is performed firstly by applying a layer of sintering material of locally varying thickness to either the metal moulded body (2) or the substrate, followed by sintering together the contacting film (5) with the substrate (1) by using the properties of the layer of sintering material that are conductive to connection, the contacting film (5) being made to develop its distinct form to correspond to the varying thickness of the layer of sintering material (3a).

在封装之间具有插头-插座型线连接的半导体封装上封装

一种半导体封装上封装，包括下部封装、叠置在所述下部封装上的上部封装、结合至所述下部封装的上部和所述上部封装的下部中的任何一者的插头线以及结合至所述下部封装的上部和所述上部封装的下部中的任何一者的插座线。将所述插头线插入到所述插座线内，从而使所述上部和下部封装电连接。

System and method for increasing the strength of a bond made by a small diameter wire in a ball bonding

A system and method is disclosed for increasing the strength of a bond made by a small diameter wire in ball bonding. In one embodiment of the invention a structure for receiving a ball bond comprises substrate material that has portions that form a substrate cavity and a wire bond pad that covers and fills the substrate cavity. The wire bond pad also has portions that form a wire bond cavity for receiving the ball bond. The ball is wirebonded to the sides and bottom of the wire bond cavity. The sides of the wire bond cavity provide additional strength to the bond to resist shear and tensile forces that may act on the wire.

System und Methode zur Erhöhung der Festigkeit einer Ball-Bondverbindung mit geringem Durchmesser

System and method for increasing the strength of a bond made by a small diameter wire in a ball bonding

System and method for increasing the strength of a bond made by a small diameter wire in ball bonding

A system and method is disclosed for increasing the strength of a bond made by a small diameter wire in ball bonding. In one embodiment of the invention a structure for receiving a ball bond comprises substrate material that has portions that form a substrate cavity and a wire bond pad that covers and fills the substrate cavity. The wire bond pad also has portions that form a wire bond cavity for receiving the ball bond. The ball is wirebonded to the sides and bottom of the wire bond cavity. The sides of the wire bond cavity provide additional strength to the bond to resist shear and tensile forces that may act on the wire.

半导体结构及其制备方法

本发明涉及一种半导体结构及其制备方法；包括：支撑层，包括焊盘区域；所述支撑层的焊盘区域内形成有若干个凹槽；焊垫，位于所述支撑层上，且至少位于所述焊盘区域内，所述焊垫部分嵌入所述凹槽内。上述半导体结构中通过在焊垫下方形成焊盘区域内具有若干个凹槽的支撑层，在焊线键合工艺时即使焊垫平坦且大部分焊垫在键合压力的作用下会被排挤开来，但由于焊垫下方为具有凹槽的支撑层，焊线底部会部分区域陷入凹槽内，使得焊线与焊垫的接触面为凸凹不平状，增大焊线与焊垫的接着性，降低焊线脱落的风险。

半導体装置の製造方法

【課題】半導体装置の信頼性を向上させる。【解決手段】半導体装置の製造方法は、半導体チップＣＨＰのパッド（電極パッド）ＰＤに、ワイヤＢＷの先端に形成されたボール部ＢＷｂを接続する工程を含む。また、パッドＰＤは、アルミニウムを主成分とする材料から成り、かつ、ボール部ＢＷｂを接続する部分に溝ＴＲ１が形成されている。また、ボール部ＢＷｂは、金よりも硬い材料から成る。また、ボール部ＢＷｂを接続する工程は、ボール部ＢＷｂに対して超音波を印加する工程を含む。【選択図】図１０

Copper bonding wire, wire bonding structure and method for processing and bonding a wire

高密度管脚qfn的封装结构与方法

本发明提供一种高密度管脚QFN的封装结构，属于半导体封装技术领域，包括引线框架结构，所述引线框架结构包括引线框架单元；其中，所述引线框架单元包括位于中部的芯片结合部以及围绕所述芯片结合部分布的四组管脚结合部阵列，在所述管脚结合部阵列的管脚结合部中嵌入有至少一个半切割道绝缘件，所述半切割道绝缘件位于管脚半切线上，并将一个管脚结合部分隔为至少两个管脚结合部。利用本发明，能够有效增加管脚密度，从而提高封装结构的集成度。

在線接合操作中之短尾恢復技術

提供一種線材接合機的操作方法。該方法包括：在線材接合部形成之後檢測短尾情況；將線材接合機的接合頭組件設置在線材接合機的xy位置處；使接合頭組件朝向位於xy位置處的接觸表面下降；打開線材夾；使接合頭元件減速，從而使得線材的一部分延伸到線材接合工具的末端下方；閉合線材夾；以及執行測試，以確認線材延伸到線材接合工具的末端下方的端部是否與接觸表面接觸。

形成导线互连结构的方法

一种形成一导线互连结构的方法包含以下步骤：(a)利用一导线接合工具形成一导线接合于一基板上之一接合位置处；(b)使与该导线接合接续之一段导线延伸至另一位置；(c)利用该导线接合工具将该段导线之一部分压抵于该另一位置上；(d)将该导线接合工具、以及该段导线之该被压抵部分移动至该导线接合上方之一位置；以及(e)使该段导线在该被压抵部分处自一导线供应源分离，藉此提供接合至该接合位置之一导线互连结构。

와이어 상호접속 구조를 형성하는 방법

와이어 상호접속 구조를 형성하는 방법은 (a) 와이어 본딩 툴을 사용해서 기판상의 본딩 장소에서 와이어 본드를 형성하는 단계; (b) 와이어의 길이를, 와이어 본드와 연속해서 다른 장소로 연장하는 단계; (c) 와이어의 길이의 일부분을 와이어 본딩 툴을 이용해서 다른 장소에 대해서 프레싱하는 단계; (d) 와이어 본딩 툴과 와이어 길이의 프레스된 부분을 와이어 본드 상부 위치로 이동하는 단계; 및 (e) 와이어의 길이를 프레스된 부분에서 와이어 공급원으로부터 분리하는 단계를 포함함으로써, 본딩 장소에 본딩된 와이어 상호접속 구조를 제공한다.