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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 12106. Отображено 100.
05-01-2012 дата публикации

Double molded chip scale package

Номер: US20120001322A1
Автор: Luke England, Yong Liu
Принадлежит: Fairchild Semiconductor Corp

Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure. With such a configuration, the second molding layer helps control warpage during the manufacturing process and no printed circuit board (PCB) substrate is needed when the package is used in an electronic device since the signal routing is performed by the second interconnect structure. Other embodiments are described.

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Номер записи: 1
05-01-2012 дата публикации

Method for manufacture of integrated circuit package system with protected conductive layers for pads

Номер: US20120003830A1
Автор: Haijing Cao, Qing Zhang, Yaojian Lin
Принадлежит: Individual

A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer.

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Номер записи: 2
12-01-2012 дата публикации

Resin-Encapsulated Semiconductor Device

Номер: US20120007247A1
Автор: Motoharu Haga, Shoji Yasunaga, Yasumasa Kasuya
Принадлежит: ROHM CO LTD

A resin-sealed semiconductor device includes a semiconductor chip including a silicon substrate; a die pad on which the semiconductor chip is secured via a solder layer; a sealing resin layer sealing the semiconductor chip; and lead terminals connected electrically with the semiconductor chip. One end portion of the lead terminals is covered by the sealing resin layer. The die pad and the lead terminals are formed of copper and a copper alloy, and the die pad is formed with a thickness larger than a thickness of the lead terminals, which is a thickness of 0.25 mm or more.

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Номер записи: 3
26-01-2012 дата публикации

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

Номер: US20120018904A1
Автор: Jianmin Fang, KANG Chen, Xia Feng, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

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Номер записи: 4
02-02-2012 дата публикации

Laminated semiconductor substrate, laminated chip package and method of manufacturing the same

Номер: US20120025354A1
Автор: Atsushi Iijima, Hiroyuki Ito, Yoshitaka Sasaki
Принадлежит: Headway Technologies Inc, SAE Magnetics HK Ltd

In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have an electromagnetic shielding layer formed using a ferromagnetic body. The electromagnetic shielding layer is formed in a shielding region except the extending zone. The extending zone is set a part which the wiring electrode crosses, in a peripheral edge part of the device region.

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Номер записи: 5
02-02-2012 дата публикации

Semiconductor device and method of designing a wiring of a semiconductor device

Номер: US20120025377A1
Автор: Hideaki Ikuma, Shoji Seta, Yukihito Oowaki
Принадлежит: Toshiba Corp

A semiconductor device has an LSI chip including a semiconductor substrate, an LSI core section provided at a center portion of the semiconductor substrate and serving as a multilayered wiring layer of the semiconductor substrate, a first rewiring layer provided adjacent to an outer periphery of the LSI core section on the semiconductor substrate and including a plurality of wiring layers, a first pad electrode disposed at an outer periphery of the first rewiring layer, and an insulation layer covering the first pad electrode. The semiconductor device includes a second rewiring layer provided on the LSI chip and including a rewiring connected to the first pad electrode. The semiconductor device includes a plurality of ball electrodes provided on the second rewiring layer. The first rewiring layer is electrically connected to the LSI core section and the first pad electrode.

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Номер записи: 6
09-02-2012 дата публикации

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

Номер: US20120032298A1
Автор: Hideki Fujii, Kenji Furuya, Yuichi Miyagawa
Принадлежит: Renesas Electronics Corp

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

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Номер записи: 7
09-02-2012 дата публикации

Semiconductor device

Номер: US20120032325A1
Автор: Osamu Miyata, Shingo Higuchi
Принадлежит: ROHM CO LTD

There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

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Номер записи: 8
15-03-2012 дата публикации

Semiconductor device having pad structure with stress buffer layer

Номер: US20120061823A1
Автор: Chao-Wen Shih, Shang-Yun Hou, Shin-puu Jeng, Tzu-Wei Chiu, Tzuan-Horng LIU, Wei-Cheng Wu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

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Номер записи: 9
19-04-2012 дата публикации

Microelectronic assemblies having compliancy and methods therefor

Номер: US20120091582A1
Автор: Belgacem Haba, David Ovrutsky, Guilian Gao, Vage Oganesian
Принадлежит: Tessera LLC

A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.

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Номер записи: 10
26-04-2012 дата публикации

Bond pad for wafer and package for cmos imager

Номер: US20120098105A1
Автор: James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Richard L. Rassel
Принадлежит: International Business Machines Corp

An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.

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Номер записи: 11
03-05-2012 дата публикации

Method for manufacturing semiconductor device

Номер: US20120108013A1
Автор: Atsushi Fujisawa, Hiroshi Fujii
Принадлежит: Renesas Electronics Corp

In QFN packages for vehicles which are required to have high reliability, the side surface of leads is mostly covered with lead-to-lead resin protrusions, which prevent smooth formation of solder fillets during reflow mounting. When the lead-to-lead protrusions are mechanically removed using a punching die, there is a high possibility of causing cracks of the main body of the package or terminal deformation. When a spacing is provided between the punching die and the main body of the package in order to avoid such damages, a resin residue is produced to hinder complete removal of this lead-to-lead resin protrusion. The present invention provides a method for manufacturing semiconductor device of a QFN type package using multiple leadframes having a dam bar for tying external end portions of a plurality of leads. This method includes a step of removing a sealing resin filled between the circumference of a mold cavity and the dam bar by using laser and then carrying out surface treatment, for example, solder plating.

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Номер записи: 12
31-05-2012 дата публикации

Semiconductor device

Номер: US20120133058A1
Автор: Kunihiro Komiya
Принадлежит: ROHM CO LTD

The semiconductor device has the CSP structure, and includes: a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps are arranged in two rows along the periphery of the semiconductor device. The electrode pads are arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring is extended from an electrode pad, and is connected to any one of the outermost solder bumps or any one of the inner solder bumps.

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Номер записи: 13
21-06-2012 дата публикации

Packaged semiconductor chips with array

Номер: US20120153443A1
Автор: Andrey Grinman, Charles Rosenstein, David Ovrutsky, Vage Oganesian
Принадлежит: Tessera LLC

A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

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Номер записи: 14
21-06-2012 дата публикации

Integrated millimeter wave transceiver

Номер: US20120154238A1
Автор: Jean-François Carpentier, Patrice Garcia, Pierre Busson, Pierre Dautriche, Sebastien Pruvost
Принадлежит: STMICROELECTRONICS SA

A millimeter wave transceiver including a plate forming an interposer having its upper surface supporting an interconnection network and having its lower surface intended to be assembled on a printed circuit board by bumps; an integrated circuit chip assembled on the upper surface of the interposer; antennas made of tracks formed on the upper surface of the interposer; and reflectors on the upper surface of the printed circuit board in front of each of the antennas, the effective distance between each antenna and the reflector plate being on the order of one quarter of the wavelength, taking into account the dielectric constants of the interposed materials.

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Номер записи: 15
26-07-2012 дата публикации

Semiconductor Device and Method of Forming Shielding Layer Around Back Surface and Sides of Semiconductor Wafer Containing IPD Structure

Номер: US20120187531A1
Автор: ByungHoon Ahn, Gwang Kim, HyunTai Kim, YongTaek Lee
Принадлежит: Stats Chippac Pte Ltd

A semiconductor wafer has an insulating layer over a first surface of the substrate. An IPD structure is formed over the insulating layer. The IPD structure includes a MIM capacitor and inductor. A conductive via is formed through a portion of the IPD structure and partially through the substrate. The conductive via can be formed in first and second portions. The first portion is formed partially through the substrate and second portion is formed through a portion of the IPD structure. A first via is formed through a second surface of the substrate to the conductive via. A shielding layer is formed over the second surface of the substrate wafer. The shielding layer extends into the first via to the conductive via. The shielding layer is electrically connected through the conductive via to an external ground point. The semiconductor wafer is singulated through the conductive via.

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Номер записи: 16
23-08-2012 дата публикации

Device mounting board and method of manufacturing the same, semiconductor module, and mobile device

Номер: US20120211269A1
Автор: Kouichi Saitou, Toshiya Shimizu
Принадлежит: Sanyo Electric Co Ltd

A device mounting board includes: an insulating resin layer; a wiring layer formed on one of the principal surfaces of the insulating resin layer; a protection layer covering the insulating resin layer and the wiring layer; a protruding electrode electrically connected to the wiring layer, the protruding electrode protruding from the wiring layer toward the insulating resin layer and penetrating through the insulating resin layer; a wiring-layer-side convex portion protruding from the wiring layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer; and a resin-layer-side convex portion protruding from the protection layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer.

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Номер записи: 17
30-08-2012 дата публикации

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

Номер: US20120217629A1
Автор: Daesik Choi, Joonyoung Choi, SungWon Cho
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

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Номер записи: 18
25-10-2012 дата публикации

Wafer Level Chip Scale Package Method Using Clip Array

Номер: US20120267787A1
Автор: Yuping Gong
Принадлежит: Alpha and Omega Semiconductor Cayman Ltd

A method for wafer level chip scale package comprises providing a wafer with semiconductor chips formed thereon, forming a groove alongside each chip, providing a wafer size clip array with a plurality of clip contact areas each extending to a down set connecting bar, connecting the plurality of clip contact areas to a plurality of the electrodes disposed on a top surface of the chips with down set connecting bars disposed inside the grooves, encapsulating top of wafer in molding compound, thinning the bottom portion of the wafer and dicing the thin wafer into single chip packages. The chip has source and gate electrodes on a top surface connected to a first and second clip contact areas extending to a first a second down set connecting bars respectively, with the bottom surfaces of the down set connecting bars substantially coplanar to a drain electrode located at the chip bottom surface.

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Номер записи: 19
29-11-2012 дата публикации

Stacked wafer level package having a reduced size

Номер: US20120299169A1
Автор: Jong Hoon Kim, Min Suk Suh, Seung Hyun Lee, Seung Taek Yang, Tae Min Kang
Принадлежит: SK hynix Inc

A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.

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Номер записи: 20
13-12-2012 дата публикации

Semiconductor package, electrical and electronic apparatus including the semiconductor package, and method of manufacturing the semiconductor package

Номер: US20120313244A1
Автор: Ji-Seok HONG, Jong-Gi Lee, Sang-Wook Park
Принадлежит: Individual

In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring.

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Номер записи: 21
13-12-2012 дата публикации

Layered chip package and method of manufacturing same

Номер: US20120313260A1
Автор: Atsushi Iijima, Hiroshi Ikejima, Hiroyuki Ito, Yoshitaka Sasaki
Принадлежит: Headway Technologies Inc, SAE Magnetics HK Ltd

A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

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Номер записи: 22
27-12-2012 дата публикации

Low profile package and method

Номер: US20120326300A1
Автор: Anindya Poddar, Ashok S. Prabhu, Hau T. Nguyen, Tao Feng, Will K. Wong
Принадлежит: National Semiconductor Corp

In a method aspect, a multiplicity of ICs are attached to routing on a structurally supportive carrier (such as a wafer). The dice are encapsulated and then both the dice and the encapsulant layer are thinned with the carrier in place. A second routing layer is formed over the first encapsulant layer and conductive vias are provided to electrically couple the first and second routing layers as desired. External I/O contacts (e.g. solder bumps) are provided to facilitate electrical connection of the second routing layer (or a subsequent routing layer in stacked packages) to external devices. A contact encapsulant layer is then formed over the first encapsulant layer and the second routing layer in a manner that embeds the external I/O contacts at least partially therein. After the contact encapsulant layer has been formed, the carrier itself may be thinned significantly and singulated to provide a number of very low profile packages. The described approach can also be used to form stacked multi-chip packages.

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Номер записи: 23
07-03-2013 дата публикации

Thermally Enhanced Structure for Multi-Chip Device

Номер: US20130056871A1
Автор: Chen-Hua Yu, Chih-Hang Tung, Tung-Liang Shao
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.

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Номер записи: 24
21-03-2013 дата публикации

Solder cap bump in semiconductor package and method of manufacturing the same

Номер: US20130069231A1
Автор: Geng-Shin Shen
Принадлежит: CHIPMOS TECHNOLOGIES INC

A semiconductor package with improved height uniformity of solder cap bumps therein is disclosed. In one embodiment, the semiconductor package includes a semiconductor substrate comprising a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer formed on top of the pads, wherein a plurality of pad openings are created to expose at least a portion of the pads; a plurality of solder cap bumps formed at the pad openings of the passivation layer; and a carrier substrate having a plurality of bond pads electrically connected to the solder caps of the solder cap bumps on the semiconductor substrate. The solder cap bump includes a solder cap on top of a conductive pillar, and a patternable layer can be coated and patterned on a top surface of the conductive pillar to define an area for the solder ball to be deposited. The deposited solder ball can be reflowed to form the solder cap.

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Номер записи: 25
11-04-2013 дата публикации

Methods of Packaging Semiconductor Devices and Structures Thereof

Номер: US20130087916A1
Автор: Jing-Cheng Lin, Jui-Pin Hung, Tsan-Hua Tung, Yi-Hang Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

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Номер записи: 26
18-04-2013 дата публикации

Wafer level packaging method of encapsulating the bottom and side of a semiconductor chip

Номер: US20130095612A1
Автор: Lei Duan, Ping Huang, Ruisheng Wu, Yi Chen, Yuping Gong
Принадлежит: ALPHA AND OMEGA SEMICONDUCTOR INC

A chip-scale packaging method, with bottom and side of a semiconductor chip encapsulated, includes the following steps: attaching backside of a thinned semiconductor wafer to a dicing tape; separating individual chips by cutting from front side of the wafer at scribe line but not cut through the dicing tape; flipping and attaching the wafer onto a top surface of a double-sided tape, then removing the dicing tape; attaching bottom surface of the double-sided tape on a supporting plate; filling the space between adjacent chips and covering the whole wafer backside with a molding material; flipping the whole structure and remove the supporting plate; placing solder balls at corresponding positions on electrodes of each chip and performing backflow treatment; finally separating individual chip packages by cutting through molding material at the space between adjacent chip packages with molding material encapsulating the bottom and side of each individual semiconductor chip.

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Номер записи: 27
09-05-2013 дата публикации

System in package process flow

Номер: US20130113115A1
Автор: Chien-Hsiun Lee, Tsung-Ding Wang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.

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Номер записи: 28
30-05-2013 дата публикации

Wafer level chip scale package

Номер: US20130134502A1
Автор: Yan Xun Xue, Yueh-Se Ho
Принадлежит: ALPHA AND OMEGA SEMICONDUCTOR INC

A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.

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Номер записи: 29
11-07-2013 дата публикации

Semiconductor package

Номер: US20130175702A1
Автор: Tae-Je Cho, Yun-seok Choi
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package includes a first semiconductor package, a second semiconductor package, and a package-connecting member. The first semiconductor package includes a first substrate, a chip stacking portion disposed on the first substrate and including a plurality of first semiconductor chips, and a first sealant for surrounding the chip stacking portion on the first substrate. The second semiconductor package includes a second substrate, at least one second semiconductor chip disposed on the second substrate, and a second sealant for surrounding the second semiconductor chip on the second substrate. The package-connecting member electrically connects the first semiconductor package and the second semiconductor package. The plurality of first semiconductor chips include a first chip including through silicon vias (TSVs) and a second chip electrically connected to the first chip via the TSVs, and the chip stacking portion includes an internal sealant for filling a space between the first chip and the second chip and extending to a side of the second chip.

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Номер записи: 30
22-08-2013 дата публикации

Package-in-Package Using Through-Hole Via Die on Saw Streets

Номер: US20130214385A1
Автор: Byung Tai Do, Heap Hoe Kuan, Seng Guan Chow
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.

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Номер записи: 31
22-08-2013 дата публикации

Film for forming protective layer

Номер: US20130217187A1
Автор: Naohide Takamoto, Takashi Oda, Takeshi Matsumura
Принадлежит: Nitto Denko Corp

The present invention aims to provide a film for forming a protective layer that is capable of preventing cracks in a low dielectric material layer of a semiconductor wafer while suppressing an increase in the number of steps in the manufacture of a semiconductor device. This object is achieved by a film for forming a protective layer on a bumped wafer in which a low dielectric material layer is formed, including a support base, an adhesive layer, and a thermosetting resin layer, laminated in this order, wherein the melt viscosity of the thermosetting resin layer is 1×10 2 Pa·S or more and 2×10 4 Pa·S or less, and the shear modulus of the adhesive layer is 1×10 3 Pa or more and 2×10 6 Pa or less, when the thermosetting resin layer has a temperature in a range of 50 to 120° C.

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Номер записи: 32
12-09-2013 дата публикации

Semiconductor device bonding with stress relief connection pads

Номер: US20130234327A1
Автор: Hiroshi Okumura, Masaki Kasai
Принадлежит: ROHM CO LTD

An inventive semiconductor device includes: a semiconductor chip; an internal pad provided on a surface of the semiconductor chip for electrical connection; a surface protective film covering the surface of the semiconductor chip and having a pad opening from which the internal pad is exposed; a stress relief layer provided on the surface protective film and having an opening portion through which the internal pad exposed from the pad opening is exposed; a connection pad including an anchor buried in the pad opening and the opening portion and connected to the internal pad, and a projection provided integrally with the anchor as projecting on the stress relief layer, the projection having a width greater than an opening width of the opening portion; and a metal ball provided for external electrical connection as covering the projection of the connection pad.

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Номер записи: 33
19-09-2013 дата публикации

Fully molded fan-out

Номер: US20130244376A1
Автор: Christopher M. Scanlan
Принадлежит: DECA Technologies Inc

A method for manufacturing a device package may include constructing a spacer element coupled with a surface of a semiconductor die unit, where the spacer element is configured to create a gap between the semiconductor die unit and a surface of a carrier, and encapsulating the semiconductor die unit within a mold compound, where the encapsulating includes introducing the mold compound into the gap.

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Номер записи: 34
03-10-2013 дата публикации

Package including an underfill material in a portion of an area between the package and a substrate or another package

Номер: US20130258578A1
Автор: Myung Jin Yim, Nanette Quevedo, Richard Strode
Принадлежит: Micron Technology Inc

Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having a substrate or a first package, and a second package coupled to the substrate or the first package, wherein the second package includes at least one die and an underfill material disposed in a portion, but not an entirety, of an area between the package and the substrate or the first package. Other embodiments may be described and claimed.

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Номер записи: 35
17-10-2013 дата публикации

Device with pillar-shaped components

Номер: US20130270697A1
Автор: Osamu Koike
Принадлежит: Lapis Semiconductor Co Ltd

A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to any of the substrate and the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part to the top part to connect the bottom part and the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, the ring-like projection part being formed in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.

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Номер записи: 36
14-11-2013 дата публикации

Semiconductor Die Connection System and Method

Номер: US20130299976A1
Автор: Chen-Hua Yu, Ming-Fa Chen, Sen-Bor Jan
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.

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Номер записи: 37
14-11-2013 дата публикации

Plated terminals with routing interconnections semiconductor device

Номер: US20130299979A1
Автор: Saravuth Sirinorakul
Принадлежит: UTAC Thai Ltd

A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of interconnection routings disposed within the semiconductor package. At least one interconnection routing is electrically coupled with a terminal and extends planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes one or more additional intermediary layers. Each intermediary layer includes a via layer and an associated routing layer. The associated routing layer includes associated routings. At least one associated routing is electrically coupled with a terminal and extends planarly therefrom. Each via layer couples two routing layers. The semiconductor package also includes a locking mechanism for fastening a package compound with the interconnection routings and the terminals.

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Номер записи: 38
28-11-2013 дата публикации

Semiconductor device having wafer-level chip size package

Номер: US20130313703A1
Автор: Kiyonori Watanabe
Принадлежит: Oki Semiconductor Co Ltd

A semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. The surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is included on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer is included as having openings exposing part of the conductive pattern. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The thickness of the protective layer, which may function as a package of the semiconductor device, is thus reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes.

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Номер записи: 39
12-12-2013 дата публикации

Package-on-package assembly with wire bond vias

Номер: US20130328219A1
Автор: Ellis Chau, Philip Damberg, Reynaldo Co, Roseann Alatorre, Se Young Yang, Wei-Shun Wang
Принадлежит: Invensas LLC

A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer.

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Номер записи: 40
23-01-2014 дата публикации

Wafer-level device packaging

Номер: US20140021596A1
Автор: Dan Yang, Pui Chung Law, Yat Kit Tsui
Принадлежит: Hong Kong Applied Science and Technology Research Institute ASTRI

The present invention relates to a semiconductor device packaged at the wafer level such that an entire packaged device is formed prior to separation of individual devices. The semiconductor device package includes a semiconductor chip having one or more bonding pads associated with the chip and a protective layer bonded over the semiconductor chip. An insulation layer is positioned on at least side edges and a lower surface of the semiconductor chip. Interconnection/bump metallization is positioned adjacent one or more side edges of the semiconductor chip and is electrically connected to at least one bonding pad. A compact image sensor package can be formed that is vertically integrated with a digital signal processor and memory chip along with lenses and a protective cover.

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Номер записи: 41
23-01-2014 дата публикации

Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias

Номер: US20140021635A1
Автор: Eng Huat Goh, Hoay Tien Teoh
Принадлежит: Intel Corp

A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.

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Номер записи: 42
06-02-2014 дата публикации

Semiconductor package and method of fabricating the same

Номер: US20140038354A1
Автор: Min gi HONG
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Disclosed are semiconductor packages and methods of fabricating the same. A method may include preparing a wiring board including a mounting region and a molding region surrounding the mounting region; forming a through-hole penetrating through the wiring board at the mounting region; mounting a semiconductor chip on the mounting region of the wiring board by a flip chip bonding method; and forming a molding covering the molding region of the wiring board and the semiconductor chip and filling the through-hole and a space between the semiconductor chip and the wiring board. The wiring board may have a first surface on which the semiconductor chip is mounted, and a second surface opposite to the first surface. A portion of the molding filling the through-hole has a surface coplanar with the second surface of the wiring board.

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Номер записи: 43
13-02-2014 дата публикации

Semiconductor device

Номер: US20140042635A1
Автор: Kenji Nagasaki
Принадлежит: Lapis Semiconductor Co Ltd

One wiring width of upper and lower wiring paths formed facing each other sandwiching an interlayer insulating film is large, and another wiring width is small; and the wiring widths of mutually adjacent wiring paths are formed to be large and small in alternating fashion on the same wiring layer.

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Номер записи: 44
27-02-2014 дата публикации

Method of manufacturing semiconductor device

Номер: US20140054759A1
Автор: Hiroyoshi Taya, Tadatoshi Danno, Yoshiharu Shimizu
Принадлежит: Renesas Electronics Corp

A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.

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Номер записи: 45
27-02-2014 дата публикации

Methods and Apparatus of Packaging Semiconductor Devices

Номер: US20140057431A1
Автор: Chia-Wei Tu, Fu-Ying Huang, Hsien-Wei Chen, Ming-Song Sheu, Tsung-Fu Tsai, Yian-Liang Kuo
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

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Номер записи: 46
06-03-2014 дата публикации

Semiconductor Device and Method of Forming Thick Encapsulant for Stiffness with Recesses for Stress Relief in FO-WLCSP

Номер: US20140061944A1
Автор: Caparas Jose Alvin, Chen Kang, Lin Yaojian, Omandam Glenn
Принадлежит: STATS CHIPPAC, LTD.

A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device. 1. A method of making a semiconductor device , comprising:providing a first semiconductor die;depositing an encapsulant over the semiconductor die;forming a recess in the encapsulant;forming an interconnect structure over the semiconductor die; andremoving a first portion of the encapsulant.2. The method of claim 1 , wherein forming the recess further includes removing a second portion of the encapsulant while leaving the first portion of the encapsulant.3. The method of claim 1 , further including:disposing a support structure within the recess prior to forming the interconnect structure; andremoving the support structure after forming the interconnect structure.4. The method of claim 1 , further including forming the recess over the first semiconductor die and outside a footprint of the semiconductor die.5. The method of claim 1 , further including:providing a second semiconductor die; andforming the recess over the first and second semiconductor die.6. The method of claim 1 , further including disposing a support member ...

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Номер записи: 47
13-03-2014 дата публикации

Integrated circuit including an environmental sensor

Номер: US20140070337A1
Автор: Martien Kengen, Willem Frederik Adrianus Besling
Принадлежит: NXP BV

An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate including at least one environmental sensor. The integrated circuit also includes a cap layer located on a major surface of the substrate. The integrated circuit further includes at least one elongate channel for allowing access of said sensor to an environment surrounding the integrated circuit.

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Номер записи: 48
13-03-2014 дата публикации

Manufacturing method of semiconductor device and semiconductor device

Номер: US20140070389A1
Автор: Naoko Taniguchi, Yoshiharu Kaneda
Принадлежит: Renesas Electronics Corp

To enhance the reliability of a semiconductor device. The semiconductor device includes die pads, over which a first semiconductor chip and a second semiconductor chip are mounted respectively, a plurality of support pins that support each of the die pads, a plurality of inner leads and outer leads arranged around the die pads, a plurality of wires that electrically couple the semiconductor chips to the inner leads, and a sealing body that seals the semiconductor chips, the inner leads, and the wires. Each of the die pads is supported by three support pins integrally formed together with the die pad, and each of second support pins of each pair of the three support pins is arranged between the inner leads adjacent to each other.

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Номер записи: 49
13-03-2014 дата публикации

Semiconductor device with front and back side resin layers having different thermal expansion coefficient and elasticity modulus

Номер: US20140070413A1
Автор: Masaki Kasai, Osamu Miyata
Принадлежит: ROHM CO LTD

Disclosed are a semiconductor device wherein warping of a semiconductor chip due to a sudden temperature change can be prevented without increasing the thickness, and a semiconductor device assembly. The semiconductor device comprises a semiconductor chip, a front side resin layer formed on the front surface of the semiconductor chip by using a first resin material, and a back side resin layer formed on the back surface of the semiconductor chip by using a second resin material having a higher thermal expansion coefficient than the first resin material. The back side resin layer is formed thinner than the front side resin layer.

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Номер записи: 50
13-03-2014 дата публикации

Semiconductor device including bottom surface wiring and manufacturing method of the semiconductor device

Номер: US20140073129A1
Автор: Osamu Kato
Принадлежит: Lapis Semiconductor Co Ltd

Disclosed herein is a semiconductor device including a semiconductor substrate, a wiring layer formed above the semiconductor substrate, a through-hole electrode extending from the bottom surface of the semiconductor substrate to the wiring layer, a bottom surface wiring provided, at the bottom surface of the semiconductor substrate such that the bottom surface wiring is connected to the through-hole electrode, and an external terminal connected to the bottom surface wiring. The bottom surface wiring has a greater film thickness than a film thickness of the through-hole electrode at least a portion of the bottom surface wiring including a connection part between the bottom surface wiring and the external terminal.

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Номер записи: 51
03-04-2014 дата публикации

Semiconductor device and manufacturing method of the same

Номер: US20140091472A1
Автор: Kazuo Shimokawa, Kyoko HONMA
Принадлежит: Toshiba Corp

A semiconductor element includes a plurality of electrodes on a main surface, a sealing resin covering at least a part of a side surface of the semiconductor element, and a first insulating layer formed on the main surface of the semiconductor element, a part of the side surface of the semiconductor element, and the sealing resin. The first insulating layer has first openings formed therein to allow the plural electrodes on the main surface to be exposed through the first openings, and a fillet provided on a part of the side surface. The semiconductor element further includes a wiring layer formed in the first openings in such a manner as to be electrically connected to the plural electrodes, and also formed on the first insulating layer, and a second insulating layer having second openings formed on the first insulating layer and the wiring layer.

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Номер записи: 52
01-01-2015 дата публикации

WAFER LEVEL CHIP SCALE PACKAGE WITH EXPOSED THICK BOTTOM METAL

Номер: US20150001686A1
Автор: Xue Yan Xun
Принадлежит:

A method for forming a wafer level chip scale (WLCS) package device with a thick bottom metal comprising the step of attaching a lead frame comprising a plurality of thick bottom metals onto a back metal layer of a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip, each thick bottom metal is aligned to a central portion of each chip; a plurality of back side cutting grooves are formed along the scribe lines and filled with a package material, the package material are cut through thus forming a plurality of singulated WLCS package devices. 1. A wafer level chip scale (WLCS) package device with a thick bottom metal comprising:a semiconductor chip including a plurality of bonding pads formed on a front surface each having a plurality of metal interconnecting structures formed thereon;a bottom metal layer covering at a back surface opposite the front surface of the semiconductor chip;a thick bottom metal different from the bottom metal layer attached on the bottom metal layer through a conductive bonding layer, said thick bottom metal having a thick central portion extending within an area of the semiconductor chip and a thin portion extending substantially to a sidewall of the semiconductor chip;a top package layer covering the front surface of the chip and surrounding a sidewall of each metal interconnecting structure; anda package body surrounding at least a bottom portion of the semiconductor chip sidewall adjacent to the back surface and a sidewall of the thick bottom metal.2. The WLCS package device of claim 1 , wherein the package body further surrounds the entire sidewall of the semiconductor chip and a sidewall of the top package layer.3. The WLCS package device of claim 1 , wherein the bonding pads comprise a first bonding pad and a second bonding pad and the semiconductor chip further comprises a through via aligning with the second bonding pad and penetrating through the ...

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Номер записи: 53
01-01-2015 дата публикации

Semiconductor Device and Method of Forming an Interposer Including a Beveled Edge

Номер: US20150001741A1
Автор: Lee Koo Hong, Lee Tae Keun
Принадлежит:

A semiconductor device includes a first substrate. The first substrate may be a wafer-level interposer or a die-level interposer. A portion of the first substrate is removed to form a beveled edge. The beveled edge may be formed during singulation of the first substrate. A second substrate is disposed over the first substrate. The beveled edge is oriented towards the second substrate. A semiconductor die is disposed over the second substrate. The first and second substrates are disposed within a cavity of a mold. An encapsulant is deposited within the cavity over a first surface of the first substrate between the first and second substrates. The beveled edge reduces encapsulant flow onto a second surface of the first substrate opposite the first surface. The second surface of the first substrate remains free from the encapsulant. The first substrate is singulated before or after the encapsulant is deposited. 1. A method of making a semiconductor device , comprising:providing a first substrate;removing a portion of the first substrate to form a beveled edge; anddepositing an encapsulant over a first surface of the first substrate, wherein the beveled edge reduces encapsulant flow onto a second surface of the first substrate opposite the first surface.2. The method of claim 1 , further including:disposing a second substrate over the first substrate prior to depositing the encapsulant; anddisposing a semiconductor die over the second substrate.3. The method of claim 1 , further including singulating the first substrate after depositing the encapsulant.4. The method of claim 1 , further including singulating the first substrate before depositing the encapsulant.5. The method of claim 1 , further including forming the beveled edge during singulation of the first substrate.6. The method of claim 1 , further including:disposing the first substrate in a mold; anddepositing the encapsulant within the mold.7. A method of making a semiconductor device claim 1 , comprising: ...

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Номер записи: 54
06-01-2022 дата публикации

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20220005749A1
Автор: HO CHUNG-HSIUNG, LI CHI-HSUEH
Принадлежит:

A semiconductor package includes a molding compound, a chip and a conductive pad, wherein the chip is electrically connected to the conductive pad and both are encapsulated in the molding compound. An anchor flange is formed around a top surface of the conductive pad by over plating. When the conductive pad is embedded in the molding compound, the anchor flange engages the molding compound to prevent the conductive pad from separation. Bottoms of a chip and the conductive pad are exposed from the molding compound for electrically soldering to a circuit board. 1. A semiconductor package comprising:a molding compound having a top surface and a bottom surface;a chip encapsulated in the molding compound and having a bottom on which a solder layer is formed, the solder layer being exposed from the bottom surface of the molding compound; and a bottom exposed from the bottom surface of the molding compound;', 'a perpendicular side surface; and', 'an anchor flange formed around a top surface of the conductive pad to engage the molding compound., 'a conductive pad encapsulated in the molding compound and electrically connected to the chip and having'}2. The semiconductor package as claimed in claim 1 , wherein the top surface of the conductive pad is substantially co-planar with a top surface of the chip.3. The semiconductor package as claimed in claim 1 , wherein the conductive pad is formed by multiple layers of metal material electroplated on a carrier.4. The semiconductor package as claimed in claim 3 , wherein the metal material comprises aurum claim 3 , nickel claim 3 , copper or a combination thereof; andthe metal material at the bottom of the conductive pad is exposed from the bottom surface of the molding compound.5. The semiconductor package as claimed in claim 3 , wherein the chip is electrically connected to the top surface of the conductive pad via a redistribution layer.6. The semiconductor package as claimed in claim 1 , wherein the solder layer on the bottom ...

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Номер записи: 55
05-01-2017 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20170004981A1
Автор: Sakamoto Ken
Принадлежит: Mitsubishi Electric Corporation

It is an object to provide a method for manufacturing a semiconductor device which can reduce degradation in package strength and a manufacturing cost, and promote miniaturization of a package. A method for manufacturing a semiconductor device includes steps of (a) preparing a lead frame having a die pad on which a semiconductor element is mounted, (b) placing a first resin which is granular in a mold, (c) placing the lead frame in the mold in such a manner that the first resin comes into contact with a lower side of the die pad, (d) filling the mold with a second resin on an upper side of the first resin in the mold, and (e) curing the first resin and the second resin, to mold the first resin and the second resin. 1. A method for manufacturing a semiconductor device , comprising the steps of:(a) preparing a lead frame having a die pad on which a semiconductor element is mounted;(b) placing a first resin which is granular in a mold;(c) placing said lead frame in said mold in such a manner that said first resin comes into contact with a lower side of said die pad;(d) filling said mold with a second resin on an upper side of said first resin in said mold; and(e) curing said first resin and said second resin, to mold said first resin and said second resin.2. The method for manufacturing a semiconductor device according to claim 1 , whereinsaid step (b) includes a step of placing said first resin which is powdery or fragmentary in the mold.3. The method for manufacturing a semiconductor device according to claim 1 , whereinsaid mold includes a side gate for injecting said second resin sideways relative to said semiconductor element,said step (d) includes a step of injecting said second resin from said side gate of said mold to fill said mold, andsaid step (e) includes a step of molding said first resin and said second resin with said first resin being compressed by said second resin.4. The method for manufacturing a semiconductor device according to claim 1 , ...

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Номер записи: 56
05-01-2017 дата публикации

METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE HAVING A MULTI-LAYER ENCAPSULATED CONDUCTIVE SUBSTRATE AND STRUCTURE

Номер: US20170005029A1
Автор: Bang Won Bae, Chung Ji Young, Kim Byong Jin, Kim Gi Jeong
Принадлежит: AMKOR TECHNOLOGY, INC.

In one embodiment, a semiconductor package includes a multi-layer encapsulated conductive substrate having a fine pitch. The multi-layer encapsulated conductive substrate includes a conductive leads spaced apart from each other, a first encapsulant disposed between the leads, a first conductive layer electrically connected to the plurality of leads, conductive pillars disposed on the first conductive layer, a second encapsulant encapsulating the first conductive layer and the conductive pillars, and a second conductive layer electrically connected to the conductive pillars and exposed in the second encapsulant. A semiconductor die is electrically connected to the second patterned conductive layer. A third encapsulant covers at least the semiconductor die. 1. A semiconductor package comprising: a plurality of leads spaced apart from each other;', 'a first encapsulant disposed between the plurality of leads;', 'a first conductive layer electrically connected to the plurality of leads;', 'conductive pillars disposed on the first conductive layer;', 'a second encapsulant encapsulating the first conductive layer and the conductive pillars; and', 'a second conductive layer electrically connected to the conductive pillars and disposed adjacent the second encapsulant;, 'a multi-layer encapsulated conductive substrate comprisinga semiconductor die electrically coupled to the second conductive layer; anda third encapsulant encapsulating at least the semiconductor die.2. The semiconductor package of claim 1 , wherein a bottom surface of the first encapsulant protrudes to a bottom portion of the multi-layer encapsulated conductive substrate more than bottom surfaces of the plurality of leads.3. The semiconductor package of further comprising:solder structures attached to the bottom surfaces of the plurality of leads.4. The semiconductor package of claim 1 , wherein bottom surfaces of the plurality of leads protrude to a bottom portion of the multi-layer encapsulated conductive ...

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Номер записи: 57
05-01-2017 дата публикации

Flat No-Leads Package With Improved Contact Pins

Номер: US20170005030A1
Автор: Kenganantanon Ekgachai, Kitnarong Rangsun, Punyapor Prachit
Принадлежит: MICROCHIP TECHNOLOGY INCORPORATED

According to an embodiment of the present disclosure, a leadframe for an integrated circuit (IC) device may comprise a center support structure for mounting an IC chip, a plurality of pins extending from the center support structure, and a bar connecting the plurality of pins remote from the center support structure. Each pin of the plurality of pins may include a dimple. 19-. (canceled)10. A method for manufacturing an integrated circuit (IC) device in a flat no-leads package , the method comprising:mounting an IC chip onto a center support structure of a leadframe, the leadframe including:the center support structure;a plurality of pins extending from the center support structure; anda bar connecting the plurality of pins remote from the center support structure;wherein each pin of the plurality of pins includes a dimple;bonding the IC chip to at least some of the plurality of pins;encapsulating the leadframe and bonded IC chip creating an IC package; andcutting the IC package free from the bar by sawing through the encapsulated lead frame at a set of cutting lines intersecting the dimples of the plurality of pins, exposing an end face of each of the plurality of pins and leaving a portion of the dimples that extends from the bottom surface of the IC package to a side surface with the exposed end faces of the pins.11. A method according to claim 10 , further comprising:performing an isolation cut to isolate individual pins of the IC package without separating the IC package from the lead frame; andperforming a circuit test of the isolated individual pins after the isolation cut.12. A method according to claim 10 , further comprising bonding the IC chip to at least some of the plurality of pins using wire bonding.13. A method according to claim 10 , further comprising plating the exposed portion of the plurality of pins claim 10 , including the dimples claim 10 , on a bottom surface of the IC package before cutting the IC package free from the bar.14. A method for ...

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Номер записи: 58
05-01-2017 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Номер: US20170005044A1
Автор: ISHIDO Kiminori, IWASAKI Toshihiro, TAMAKAWA Michiaki
Принадлежит:

The present invention is to provide a semiconductor device in which an insulating material layer contains no reinforced fibers such as a glass cloth or a nonwoven cloth and which enables miniaturization of metal thin-film wiring layers, a reduction in the diameter of metal vias, and a reduction in interlayer thickness. The semiconductor device includes an insulating material layer including one or more semiconductor elements sealed with an insulating material containing no reinforced fibers, a plurality of metal thin-film wiring layers, metal vias that electrically connect the metal thin-film wiring layers together and electrodes of the semiconductor elements and the metal thin-film wiring layers together, and a warpage adjustment layer arranged on one principal surface of the insulating material layer to offset warpage of the insulating material layer to reduce warpage of the semiconductor device. 1. A semiconductor device including:an insulating material layer including one or more semiconductor elements sealed with an insulating material containing no reinforced fibers, a plurality of metal thin-film wiring layers, and metal vias that electrically connect the metal thin-film wiring layers together and electrodes of the semiconductor elements and the metal thin-film wiring layers together; anda warpage adjustment layer arranged on one principal surface of the insulating material layer to offset warpage of the insulating material layer to reduce warpage of the semiconductor device.2. The semiconductor device according to claim 1 , in which the semiconductor elements are mounted claim 1 , via an adhesive claim 1 , on a back side of the surface of the insulating material layer on which an external terminal is mounted claim 1 , the semiconductor elements being mounted such that element circuit surfaces of the semiconductor elements face upward.3. The semiconductor device according to claim 1 , in which the warpage adjustment layer is a layer made of an insulating ...

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Номер записи: 59
05-01-2017 дата публикации

Semiconductor Package System and Method

Номер: US20170005049A1
Автор: Cheng Ming-Da, Huang Hui-Min, Lin Chih-Wei, Liu Chung-Shi, Tsai Tsai-Tsung, Yu Chen-Hua
Принадлежит:

A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die. 1. A semiconductor device comprising:a semiconductor die with a first sidewall;a first protective layer over the semiconductor die, wherein a second sidewall of the first protective layer is recessed from the first sidewall of the semiconductor die;an opening through the first protective layer;an encapsulant covering the first sidewall and the second sidewall, wherein the encapsulant has a top surface that is planar with the first protective layer; anda conductive material filling the opening and extending over the encapsulant.2. The semiconductor device of claim 1 , further comprising a second protective layer over the conductive material.3. The semiconductor device of claim 2 , further comprising an underbump metallization extending through the second protective layer to make electrical contact with the conductive material.4. The semiconductor device of claim 2 , wherein the second protective layer has a third sidewall aligned with a fourth sidewall of the encapsulant.5. The semiconductor device of claim 1 , further comprising a through via extending through the encapsulant and in electrical connection with the conductive material.6. The semiconductor device of claim 1 , wherein the conductive material is in physical contact with the encapsulant.7. The semiconductor device of claim 6 , wherein the conductive material is copper.8. A semiconductor device comprising:a protective material overlying a first surface of a semiconductor die, the protective material having a second surface facing away from the first surface;an encapsulant encapsulating the ...

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Номер записи: 60
05-01-2017 дата публикации

SEMICONDUCTOR ELEMENT, MANUFACTURING METHOD OF SEMICONDUCTOR ELEMENT, AND ELECTRONIC APPARATUS

Номер: US20170005128A1
Автор: Sasaki Naoto
Принадлежит:

The present disclosure relates to a semiconductor element, a manufacturing method of a semiconductor element, and an electronic apparatus, which enable suppression of crack occurrences and leaks. 1. A semiconductor element , comprising:a through silicon via (TSV) formed in a substrate;a side wall film formed in a side wall portion of the TSV and having good coverage; andan insulating film formed in a layer under a metal wiring except for a via portion of the TSV,wherein the insulating film is of a film type in which a coefficient of thermal expansion has a value between a coefficient of thermal expansion for the substrate and a coefficient of thermal expansion for the metal wiring.2. The semiconductor element according to claim 1 ,wherein the insulating film is laminated to the side wall film in the side wall portion of the TSV.3. The semiconductor element according to claim 1 ,wherein the side wall film is a plasma oxide film.4. The semiconductor element according to claim 1 ,wherein the side wall film is formed on a whole surface and thereafter completely removed on a field by etch back.5. The semiconductor element according to claim 1 ,wherein the insulating film includes films of a plurality of film types laminated.6. The semiconductor element according to claim 1 ,wherein the substrate under the metal wiring is slit to form a slit, and the insulating film is embedded in the slit.7. The semiconductor element according to claim 1 ,wherein the semiconductor element has a chip size package (CSP) structure.8. The semiconductor element according to claim 1 ,wherein the semiconductor element is a solid-state imaging element.9. A manufacturing method of a semiconductor element claim 1 , comprising:forming, by a manufacturing apparatus, a side wall film having good coverage, on a side wall portion of a through silicon via (TSV) formed in a substrate; andforming, by the manufacturing apparatus, an insulating film in a layer under a metal wiring except for a via portion ...

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Номер записи: 61
07-01-2016 дата публикации

WAFER LEVEL PACKAGING METHOD AND INTEGRATED ELECTRONIC PACKAGE

Номер: US20160005628A1
Автор: Vincent Michael B., Yap Weng F.
Принадлежит:

A wafer level packaging method entails providing electronic devices and providing a platform structure having cavities extending through the platform structure. The platform structure is mounted to a temporary support. One or more electronic devices are placed in the cavities with an active side of each electronic device facing the temporary support. The platform structure and the electronic devices are encapsulated in an encapsulation material to produce a panel assembly. Redistribution layers may be formed over the panel assembly, after which the panel assembly may be separated into a plurality of integrated electronic packages. The platform structure may be formed from a semiconductor material, and platform segments within each package provide a fan-out region for conductive interconnects, as well as provide a platform for a metallization layer and/or for forming through silicon vias. 1. A method comprising:providing a platform structure having a plurality of cavities extending through a thickness of said platform structure, said cavities being sized to accept electronic devices, wherein said platform structure comprises a semiconductor material;mounting said platform structure to a temporary support;placing said electronic devices in said cavities of said platform structure; andencapsulating said platform structure and said electronic devices in an encapsulation material to produce a panel assembly containing said electronic devices and said platform structure.2. The method of wherein said providing comprises providing said platform structure with said cavities having a curvilinear shape.3. The method of wherein said providing comprises forming said platform structure from said semiconductor material having a first coefficient of thermal expansion (CTE) that is less than a second CTE of said encapsulation material.4. The method of wherein said providing comprises forming said platform structure from a material having a particle size of no greater than five ...

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Номер записи: 62
07-01-2016 дата публикации

Electronic component and method for dissipating heat from a semiconductor die

Номер: US20160005673A1
Автор: Marcus Pawley, Martin Standing
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

In an embodiment, an electronic component includes a dielectric core layer having a thickness, at least one semiconductor die embedded in the dielectric core layer and electrically coupled to at least one contact pad arranged on a first side of the dielectric core layer, and a heat dissipation layer arranged on a second side of the dielectric core layer and thermally coupled to the semiconductor die. The semiconductor die has a thickness that is substantially equal to, or greater than, or equal to the thickness of the dielectric core layer. The heat dissipation layer includes a material with a substantially isotropic thermal conductivity.

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Номер записи: 63
07-01-2016 дата публикации

INTEGRATED CIRCUIT ASSEMBLY AND INTEGRATED CIRCUIT PACKAGING STRUCTURE

Номер: US20160005674A1
Автор: WU Ya Tzu, Yang Yu Lin
Принадлежит:

An integrated circuit packaging structure includes a chip, an electrical bump, a heat dissipation bump, a lead frame, and a sealant. The chip includes an active surface and an electronic component that is formed by using a semiconductor process. The electrical bump is electrically connected to the electronic component through the active surface. The heat dissipation bump is connected to the active surface. The lead frame is electrically connected to the electrical bump. The sealant covers the chip, the lead frame, and the electrical bump, wherein the heat dissipation bump and a part of the lead frame are exposed without being covered. The height of the heat dissipation bump relative to the active surface is unequal to that of the electrical bump relative to the active surface. 1. An integrated circuit assembly , comprising:a chip, including an active surface and an electronic component that is formed by using a semiconductor process;a heat conductor, formed by using the semiconductor process, and protruding on the active surface;an electrical conductor, formed by using the semiconductor process, and protruding on the active surface;an electrical bump, electrically connected to the active surface via the electrical conductor, so as to be electrically connected to the electronic component through the active surface; anda heat dissipation bump, connected to the active surface via the heat conductor, so as to be connected to the active surface;wherein, through the height difference formed by the heat conductor and the electrical conductor, the height of the heat dissipation bump relative to the active surface is higher than that of the electrical bump relative to the active surface.2. (canceled)3. (canceled)4. (canceled)5. The integrated circuit assembly as claimed in claim 1 , wherein the volume of the heat dissipation bump is greater than that of the electrical bump.6. (canceled)7. The integrated circuit assembly as claimed in claim 1 , wherein materials of the heat ...

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Номер записи: 64
07-01-2016 дата публикации

SEMICONDUCTOR PACKAGES HAVING RESIDUAL STRESS LAYERS AND METHODS OF FABRICATING THE SAME

Номер: US20160005698A1
Автор: Kim Youngbae
Принадлежит:

A semiconductor package is provided. The semiconductor includes a lower package and an upper package stacked on the lower package. The lower package includes a package substrate, a semiconductor chip, a mold layer and a residential stress layer. The package substrate has upper and lower surfaces. The semiconductor chip is disposed on the upper surface of the package substrate. The mold layer encapsulates the semiconductor chip. The residual stress layer is disposed on the semiconductor chip. The residual stress layer includes a plastically deformed surface. The residual stress layer has a residual stress to counterbalance warpage of the lower package. 1. A semiconductor package comprising a lower package and an upper package stacked on the lower package , wherein the lower package includes:a package substrate having upper and lower surfaces;a semiconductor chip disposed on the upper surface of the package substrate;a mold layer encapsulating the semiconductor chip; anda residual stress layer disposed on the semiconductor chip, wherein the residual stress layer includes a plastically deformed surface,wherein the residual stress layer has a residual stress to counterbalance warpage of the lower package.2. The semiconductor package of claim 1 , wherein the semiconductor chip includes an exposed surface not covered by the mold layer claim 1 , and the residual stress layer is in contact with the exposed surface of the semiconductor chip.3. The semiconductor package of claim 2 , wherein the plastically deformed surface of the residual stress includes a plurality of first dents.4. The semiconductor package of claim 3 , wherein the plastically deformed surface of the residual stress layer has first roughness claim 3 , and an upper surface of the mold layer has second roughness less than the first roughness.5. The semiconductor package of claim 3 , wherein the upper surface of the mold layer includes a plurality of second dents.6. The semiconductor package of claim 5 , ...

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Номер записи: 65
07-01-2016 дата публикации

Fan-Out Package and Methods of Forming Thereof

Номер: US20160005702A1
Автор: Huang Cheng-Lin, Lin Jing-Cheng, LIU Nai-Wei, SHIH Wan-Ting
Принадлежит:

An embodiment is a package including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound and the chip and has a first opening exposing the contact pad. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer fills the first opening. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer and has a second opening over the first opening. A second metallization layer is formed overlying the second dielectric layer and formed in the second opening. 1. A package comprising:a chip comprising a substrate and a contact pad on the substrate;a molding compound laterally encapsulating the chip;a first dielectric layer overlying the molding compound and the chip and having a first opening exposing the contact pad;a first metallization layer overlying the first dielectric layer, wherein the first metallization layer fills the first opening and laterally extends over the molding compound;a second dielectric layer overlying the first metallization layer and the first dielectric layer and having a second opening over the first opening; anda second metallization layer overlying the second dielectric layer and electrically coupled to the first metallization layer through the second opening and laterally extends over the molding compound.2. The package of claim 1 , wherein the second metallization layer is formed in the second opening and physically contacts the first metallization layer.3. The package of claim 1 , wherein the second metallization layer lines a sidewall and a bottom of the second opening.4. The package of claim 1 , wherein the first metallization layer comprises a first seed layer and a first conductive layer formed on the first seed layer.5. The package of claim 4 , wherein the first seed layer comprises titanium and the first conductive layer comprises copper.6. The package ...

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Номер записи: 66
07-01-2016 дата публикации

Structure and Method of Batch-Packaging Low Pin Count Embedded Semiconductor Chips

Номер: US20160005705A1
Автор: Mutsumi Masumoto
Принадлежит: Texas Instruments Inc

A method for fabricating packaged semiconductor devices in panel format. A flat panel sheet dimensioned for a set of contiguous chips includes a stiff substrate of an insulating plate, and a tape having a surface layer of a first adhesive releasable at elevated temperatures, a core base film, and a bottom layer with a second adhesive attached to the substrate. Attaching a set onto the first adhesive layer, the chip terminals having terminals with metal bumps facing away from the first adhesive layer. Laminating low CTE insulating material to fill gaps between the bumps and to form an insulating frame surrounding the set. Grinding lamination material to expose the bumps. Plasma-cleaning assembly, sputtering uniform metal layer across assembly, optionally plating metal layer, and patterning metal layer to form rerouting traces and extended contact pads.

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Номер записи: 67
05-01-2017 дата публикации

DEVICES AND METHODS RELATED TO HIGH POWER DIODE SWITCHES WITH LOW DC POWER CONSUMPTION

Номер: US20170005693A1
Автор: MORESCHI Stephen Richard, PUENTE Richard Mark, Zhang Shuping
Принадлежит:

Devices and methods are disclosed, related to high power diode switches. In some embodiments, a radio-frequency switch circuit can include a first switchable path implemented between a pole and a first throw, the first switchable path including one or more PIN diodes, and a second switchable path implemented between the pole and a second throw, the second switchable path including one or more PIN diodes. The radio-frequency switch circuit can further include a switchable shunt path implemented between the second throw and a ground, the switchable shunt path including at least one shunt PIN diode and a capacitance between the second throw and the at least one shunt PIN diode. The pole can be an antenna port, and the first and second throws can be transmit and receive ports, respectively. 1. A radio-frequency switch circuit comprising:a first switchable path implemented between a pole and a first throw, the first switchable path including one or more PIN diodes;a second switchable path implemented between the pole and a second throw, the second switchable path including one or more PIN diodes; anda switchable shunt path implemented between the second throw and a ground, the switchable shunt path including at least one shunt PIN diode and a capacitance between the second throw and the at least one shunt PIN diode.2. The radio-frequency switch circuit of wherein the pole is an antenna port.3. The radio-frequency switch circuit of wherein the first throw is a transmit port configured to receive an amplified radio-frequency signal.4. The radio-frequency switch circuit of further comprising an additional switchable shunt path implemented between the transmit port and a ground.5. The radio-frequency switch circuit of wherein the additional switchable shunt path includes at least one shunt PIN diode.6. The radio-frequency switch circuit of further comprising a transmit bias port electrically connected to a node between the first throw and the one or more PIN diodes of the ...

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Номер записи: 68
04-01-2018 дата публикации

Packing method for semiconductor device

Номер: US20180005845A1
Автор: Hiroaki Tanoue, Kei Goto
Принадлежит: Renesas Electronics Corp

A packing method for a semiconductor device includes a step of preparing the semiconductor device that has a sealing body having a principal surface and a plurality of leads, and a step of preparing a base carrier tape that has a peripheral portion, a step portion, and a pocket portion. The method further includes a step of placing the semiconductor device in the pocket portion, a step of bonding a cover tape to the step portion in such a manner that the sealing body is pressed against the base carrier tape, and a step of winding the base carrier tape with the semiconductor device placed therein and with the cover tape bonded thereto, around a tape reel. The base carrier tape includes a principal surface of the peripheral portion, a principal surface of the step portion, and a principal surface of the pocket portion.

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Номер записи: 69
07-01-2021 дата публикации

Integrated circuit packages and methods of forming same

Номер: US20210005464A1
Автор: Jing-Cheng Lin, Li-Hui Cheng, Po-Hao Tsai
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An integrated circuit package and a method of forming the same are provided. A method includes forming a conductive column over a carrier. An integrated circuit die is attached to the carrier, the integrated circuit die being disposed adjacent the conductive column. An encapsulant is formed around the conductive column and the integrated circuit die. The carrier is removed to expose a first surface of the conductive column and a second surface of the encapsulant. A polymer material is formed over the first surface and the second surface. The polymer material is cured to form an annular-shaped structure. An inner edge of the annular-shaped structure overlaps the first surface in a plan view. An outer edge of the annular-shaped structure overlaps the second surface in the plan view.

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Номер записи: 70
04-01-2018 дата публикации

WAFER LEVEL CHIP SCALE PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20180005912A1
Автор: Chen Bo, Lu Ming-Chen, Oh Cheow Khoon, Sui Xiaoming, Xue Vincent
Принадлежит: Alpha and Omega Semiconductor (Cayman) Ltd.

A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The stack comprises a protective tape and a molding compound. A portion of a first interface surface between the molding compound and the protective tape is curved. The manufacturing method comprises the steps of forming a semiconductor structure; attaching the semiconductor structure on a dummy wafer; performing a first dicing process using a first cutting tool; depositing a molding compound; removing the dummy wafer; performing a second dicing process with a second cutting tool. A first aperture of the first cutting tool is larger than a second aperture of the second cutting tool. The portion of the first interface surface being curved reduces the possibility of generation of cracks in the WLCSP structure. 1. A wafer level chip scale package (WLCSP) structure comprising:a semiconductor die; a protective tape; and', 'a molding compound;, 'a stack comprisingwherein the semiconductor die is packaged in between the protective tape and the molding compound; andwherein a portion of a first interface surface between the molding compound and the protective tape is curved.2. The WLCSP structure of claim 1 , wherein a portion of a second interface surface between the molding compound and the semiconductor die is curved.3. The WLCSP structure of further comprising:a connection member electrically connected to the semiconductor die;wherein a top surface of the connection member exposes from the molding compound so as to electrically connect the semiconductor die to external components.4. The WLCSP structure of claim 3 , wherein the connection member comprises a metal pillar and a solder bump claim 3 , the metal pillar being electrically connected to the semiconductor die claim 3 , and the solder bump being stacked on a top surface of the metal pillar.5. The WLCSP structure of claim 4 , wherein the semiconductor die ...

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Номер записи: 71
04-01-2018 дата публикации

PACKAGED SEMICONDUCTOR DEVICE HAVING A LEAD FRAME AND INNER AND OUTER LEADS AND METHOD FOR FORMING

Номер: US20180005925A1
Автор: Foong Chee Seng
Принадлежит:

A method of making a packaged integrated circuit device includes forming a lead frame with leads that have an inner portion and an outer portion, the inner portion of the lead is between a periphery of a die pad and extends to one end of openings around the die pad. The outer portion of the leads are separated along their length almost up to an opposite end of the openings. Leads in a first subset of the leads alternate with leads in a second subset of the leads. The inner portion of the first subset of the leads is bent. The die pad, the inner portion of the leads, and only a first portion of the openings adjacent the inner portion of the leads are encapsulated. A second portion of the openings and the output portions of the leads form a dam bar for the encapsulating material. 1. A method of making a packaged integrated circuit device comprising:forming a plurality of openings in a sheet of material;forming a die pad of a lead frame in the sheet of material; the leads have an inner portion and an outer portion, the inner portion of the lead is between a periphery of the die pad and extends to one end of the openings,', 'the outer portion of the leads are separated along their length almost up to an opposite end of the openings,', 'leads in a first subset of the leads alternate with leads in a second subset of the leads around the periphery of the die pad;, 'forming leads in the sheet of material, wherein'}bending the inner portion of the first subset of the leads;encapsulating, with encapsulating material, the die pad, the inner portion of the leads, and only a first portion of the openings adjacent the inner portion of the leads, wherein a second portion of the openings and the output portions of the leads form a dam bar for the encapsulating material.2. The method of wherein the periphery of the die pad is surrounded by the inner portion of the leads.3. The method of further comprising:removing the encapsulating material in the second portion of the openings.4. ...

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Номер записи: 72
04-01-2018 дата публикации

Planar integrated circuit package interconnects

Номер: US20180005928A1
Автор: Robert L. Sankman, Sanka Ganesan
Принадлежит: Intel Corp

Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.

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Номер записи: 73
04-01-2018 дата публикации

PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20180005955A1
Автор: Chen Hsien-Wei, Hsieh Cheng-Hsien, Hsu Li-Han, WU Chi-Hsi, WU Wei-Cheng, Yeh Der-Chyang
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A package structure and method for forming the same are provided. The package structure includes a substrate and a package layer formed over the substrate. The package structure further includes an alignment structure formed over the package layer, and the alignment structure includes a first alignment mark formed in a trench, and the trench has a step-shaped structure. 1. A package structure , comprising:a substrate;a package layer formed over the substrate; andan alignment structure formed over the package layer, wherein the alignment structure comprises a first alignment mark formed in a trench, and the trench has a step-shaped structure.2. The package structure as claimed in claim 1 , further comprising:a plurality of semiconductor dies formed over the substrate; anda package layer adjacent to the semiconductor dies.3. The package structure as claimed in claim 1 , further comprising:a scribe line between adjacent semiconductor dies, wherein the alignment structure is formed over the scribe line.4. The package structure as claimed in claim 1 , wherein each of the semiconductor dies comprises a plurality of sub-dies with a gap region between the sub-dies claim 1 , and the alignment structure is formed over the gap region.5. The package structure as claimed in claim 1 , wherein the trench has an ellipse-shaped or circle-shaped top-view profile.6. The package structure as claimed in claim 1 , further comprising:a first dielectric layer formed over the package layer, wherein the first dielectric layer comprises a first opening with an ellipse-shaped or circle-shaped top-view profile.7. The package structure as claimed in claim 1 , wherein the alignment structure comprises a second alignment mark formed over the package layer claim 1 , and the first alignment mark and the second alignment mark are in the same level.8. The package structure as claimed in claim 1 , further comprising:a first dielectric layer formed over the package layer, wherein the second alignment ...

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Номер записи: 74
04-01-2018 дата публикации

SHIELDED PACKAGE WITH INTEGRATED ANTENNA

Номер: US20180005957A1
Автор: DURNAN Gregory J., Vincent Michael B.
Принадлежит:

A semiconductor structure includes a packaged semiconductor device having at least one device, a conductive pillar, an encapsulant over the at least one device and surrounding the conductive pillar, wherein the conductive pillar extends from a first major surface to a second major surface of the encapsulant, and is exposed at the second major surface and the at least one device is exposed at the first major surface. The packaged device also includes a conductive shield layer on the second major surface of the encapsulant and on minor surfaces of the encapsulant and an isolation region at the second major surface of the encapsulant between the encapsulant and the conductive pillar such that the conductive shield layer is electrically isolated from the conductive pillar. The semiconductor structure also includes a radio-frequency connection structure over and in electrical contact with the conductive pillar at the second major surface of the encapsulant. 1. A semiconductor structure , comprising: at least one device,', 'a conductive pillar, and', 'an encapsulant over the at least one device and surrounding the conductive pillar, wherein the conductive pillar extends from a first major surface of the encapsulant to a second major surface of the encapsulant, opposite the first major surface, and is exposed at the second major surface of the encapsulant and the at least one device is exposed at the first major surface of the encapsulant,', 'a conductive shield layer on the second major surface of the encapsulant and on minor surfaces of the encapsulant, and', 'an isolation region configured to electrically isolate that the conductive shield layer from the conductive pillar; and, 'a packaged semiconductor device havinga radio-frequency (RF) connection structure over and in electrical contact with the conductive pillar at the second major surface of the encapsulant.2. The semiconductor structure of claim 1 , wherein the packaged semiconductor device comprises at least one ...

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Номер записи: 75
04-01-2018 дата публикации

INTERFACE STRUCTURES FOR PACKAGED CIRCUITRY AND METHOD OF PROVIDING SAME

Номер: US20180005972A1
Автор: Hossain MD Altaf, LEE Cliff C.
Принадлежит:

Techniques and mechanisms for determining an accessibility of circuit functionality via interface structures of a microelectronic device. In an embodiment, a packaged microelectronic device includes a substrate having interconnect structures formed therein. The interconnect structures variously couple one or more integrated circuit (IC) dies of the packaged microelectronic device to respective conductors (or “contact lands”) at a side of the substrate. Access to some functionality of the one or more IC dies via certain ones the contact lands—the access during an operational mode of the packaged microelectronic device—may be selectively disabled based on testing which evaluates performance characteristics of the packaged microelectronic device. In another embodiment, some of the contact lands are covered with an insulator material to prevent deposition of solder on such contact lands. 1. A microelectronic device comprising:a substrate including a first side and a second side;contact lands disposed at the first side, the contact lands including first contact lands and second contact lands;one or more integrated circuit (IC) dies coupled to the substrate via the second side, wherein each of the contact lands is coupled to a respective interconnect structure extending at least partially through the substrate;a package mold disposed on the second side and the one or more IC dies; 'any solder ball of the device is disposed on a contact land other than the each contact land to prevent a respective functionality of a circuit component.', 'solder balls each disposed on a respective one of the second contact lands, wherein, for each contact land of the first contact lands2. The microelectronic device of claim 1 , wherein claim 1 , of the first contact lands and the second contact lands claim 1 , only the second contact lands have respective solder balls disposed thereon.3. The microelectronic device of claim 2 , wherein respective surfaces of one or more of the first contact ...

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Номер записи: 76
04-01-2018 дата публикации

Methods of Forming Multi-Die Package Structures Including Redistribution Layers

Номер: US20180005984A1
Автор: Lee Chien-Hsun, WANG Tsung-Ding, Yee Kuo-Chung, Yu Chen-Hua
Принадлежит:

A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding material. A through via is formed over the first redistribution layer. A package component is on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate. 1. A semiconductor device , comprising:a first die disposed on a first surface of a redistribution structure;a second die disposed on the first surface of the redistribution structure;a molding material extending between the first die and the second die;a heat dissipation lid connected to the first surface of the redistribution structure, the first die and the second die being disposed in an inner cavity of the heat dissipation lid;a package connected to a second surface of the redistribution structure, the second surface of the redistribution structure being opposite to the first surface of the redistribution structure, the package comprising a plurality of package dies, and the package underlying each of the first die and the second die in part; anda plurality of first connectors connected to the second surface of the redistribution structure.2. The semiconductor device according to claim 1 , wherein a first connector of the plurality of first connectors has a first surface that is farthest from the redistribution structure claim 1 , the package has a first surface that is farthest from the redistribution structure ...

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Номер записи: 77
07-01-2021 дата публикации

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

Номер: US20210005562A1
Автор: Chen Shuo-Mao, Hsu Feng-Cheng, Jeng Shin-Puu
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A package structure includes a first dielectric layer, a first semiconductor device over the first dielectric layer, a first redistribution line in the first dielectric layer, a second dielectric layer over the first semiconductor device, a second semiconductor device over the second dielectric layer, a second redistribution line in the second dielectric layer, a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line, a conductive ball over the conductive through-via and electrically connected to the second redistribution line, and a molding material. The molding material surrounds the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material. 1. A package structure , comprising:a first dielectric layer;a first semiconductor device over the first dielectric layer;a first redistribution line in the first dielectric layer;a second dielectric layer over the first semiconductor device;a second semiconductor device over the second dielectric layer;a second redistribution line in the second dielectric layer;a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line;a conductive ball over the conductive through-via and electrically connected to the second redistribution line; anda molding material surrounding the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material.2. The package structure of claim 1 , wherein a bottom of the conductive ball is lower than the top of the molding material.3. The package structure of claim 1 , wherein the molding material has a portion vertically overlapping the first semiconductor device.4. The package structure of claim 1 , wherein the top of the molding material is higher than a top of the first semiconductor ...

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Номер записи: 78
07-01-2021 дата публикации

Process Control for Package Formation

Номер: US20210005595A1
Автор: Hsien-Wei Chen, Ming-Fa Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method includes bonding a first and a second device die to a third device die, forming a plurality of gap-filling layers extending between the first and the second device dies, and performing a first etching process to etch a first dielectric layer in the plurality of gap-filling layers to form an opening. A first etch stop layer in the plurality of gap-filling layers is used to stop the first etching process. The opening is then extended through the first etch stop layer. A second etching process is performed to extend the opening through a second dielectric layer underlying the first etch stop layer. The second etching process stops on a second etch stop layer in the plurality of gap-filling layers. The method further includes extending the opening through the second etch stop layer, and filling the opening with a conductive material to form a through-via.

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Номер записи: 79
02-01-2020 дата публикации

INTEGRATED FAN-OUT PACKAGES AND METHODS OF FORMING THE SAME

Номер: US20200006136A1
Автор: Lee Long Hua, Lin Jing-Cheng, Lu Szu-Wei, Shih Ying-Ching, Wu Chih-Wei
Принадлежит:

A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material. 1. A method of forming a semiconductor device , the method comprising:forming a conductive pillar over a first side of a carrier;attaching a backside of a die to the first side of the carrier;forming a molding material over the first side of the carrier around the die and around the conductive pillar;forming a redistribution structure over the die, the conductive pillar, and the molding material;removing the carrier, wherein after removing the carrier, a first end of the conductive pillar distal to the redistribution structure is exposed;forming a heat sink on the backside of the die; andbonding a semiconductor package to the first end of the conductive pillar, the heat sink being between the semiconductor package and the die.2. The method of claim 1 , wherein forming the heat sink comprises depositing a thermally conductive material on the backside of the die.3. The method of claim 2 , wherein the thermally conductive material has a thermal conductivity between about 100 watts per meter-kelvin (W/(m-k)) and about 400 W/(m-k).4. The method of claim 3 , wherein the thermally conductive material has a heat capacity of about 1700 joules per gram per degree Celsius (J/(g ° C.)) or larger.5. The method of claim 2 , wherein the backside of the die is attached to the first side of the carrier by an adhesive layer claim 2 , wherein forming the heat sink comprises:after removing the carrier, removing the adhesive layer to form a recess in the molding material, the recess exposing the backside of the die; andforming the thermally ...

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Номер записи: 80
02-01-2020 дата публикации

Rotatable Architecture for Multi-Chip Package (MCP)

Номер: US20200006175A1
Автор: Hossain Altaf, Nalamalpu Ankireddy, Subbareddy Dheeraj
Принадлежит:

A multi-chip packaged device may include a first integrated circuit die with a first integrated circuit, such that the first integrated circuit may include a first plurality of ports disposed on a first side and a second plurality of ports disposed on a second side of the first integrated circuit die. The multi-chip packaged device may also include a second integrated circuit die, such that the second integrated circuit may include a third plurality of ports disposed on a third side of the second integrated circuit die. The first integrated circuit may communicate with the first side of the second integrated circuit when placed adjacent to the first side and communicate with the second side of the first integrated circuit die when placed adjacent to the second side. 1. A multi-chip packaged device , comprising: a first plurality of ports disposed on a first side of the first integrated circuit die; and', 'a second plurality of ports disposed on a second side of the first integrated circuit die; and, 'a first integrated circuit die comprisinga second integrated circuit die comprising a third plurality of ports disposed on a first side of the second integrated circuit die, wherein the second integrated circuit die is configured to communicate with the first integrated circuit via the third plurality of ports and the first plurality of ports when the first side of the first integrated circuit die is placed adjacent to the first side of the second integrated circuit die, and wherein the second integrated circuit die is configured to communicate with the first integrated circuit die via the third plurality of ports and the second plurality of ports when the second side of the first integrated circuit die is placed adjacent to the first side of the second integrated circuit die.2. The multi-chip packaged device of claim 1 , wherein the third plurality of ports is configured to enable the second integrated circuit die to communicate with either the first plurality of ports ...

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Номер записи: 81
02-01-2020 дата публикации

Chip package structure with molding layer and method for forming the same

Номер: US20200006176A1
Автор: Meng-Liang Lin, Meng-Wei Chou, Po-Hao Tsai, Po-Yao Chuang, Shin-puu Jeng, Techi WONG
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method for forming a chip package structure is provided. The method includes disposing a chip over a redistribution structure. The method includes forming a molding layer over the redistribution structure adjacent to the chip. The method includes partially removing the molding layer to form a trench in the molding layer, and the trench is spaced apart from the chip.

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Номер записи: 82
02-01-2020 дата публикации

Semiconductor Device and Method of Forming Encapsulated Wafer Level Chip Scale Package (EWLCSP)

Номер: US20200006177A1
Автор: Lin Yaojian, Strothmann Thomas J., Yoon Seung Wook
Принадлежит: STATS ChipPAC Pte. Ltd.

A semiconductor device has a semiconductor die and an encapsulant around the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The fan-in interconnect structure includes an insulating layer and a conductive layer formed over the semiconductor die. The conductive layer remains within a footprint of the semiconductor die. A portion of encapsulant is removed from over the semiconductor die. A backside protection layer is formed over a non-active surface of the semiconductor die after depositing the encapsulant. The backside protection layer is formed by screen printing or lamination. The backside protection layer includes an opaque, transparent, or translucent material. The backside protection layer is marked for alignment using a laser. A reconstituted panel including the semiconductor die is singulated through the encapsulant to leave encapsulant disposed over a sidewall of the semiconductor die. 1. A semiconductor device , comprising:a semiconductor die;an encapsulant deposited around the semiconductor die, wherein the encapsulant is disposed on a side surface of the semiconductor die;a first insulating layer formed over a first surface of the semiconductor die; anda fan-in interconnect structure formed over the semiconductor die and first insulating layer.2. The semiconductor device of claim 1 , wherein a thickness of the encapsulant disposed over a side surface of the semiconductor die is less than 100 micrometers.3. The semiconductor device of claim 1 , wherein the fan-in interconnect structure includes:a conductive layer formed over the semiconductor die and first insulating layer; anda second insulating layer formed over the conductive layer, and terminating within a footprint of the semiconductor die.4. The semiconductor device of claim 3 , wherein the conductive layer and second insulating layer are offset inwards from the side surface of the ...

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Номер записи: 83
02-01-2020 дата публикации

Method of Manufacture of a Semiconductor Device

Номер: US20200006178A1
Автор: Huang Kuan-Yu, HUANG Sung-Hui, Kuo Li-Chung, Lee Long Hua, Li Pai Yuan, Shih Ying-Ching, Wu Chih-Wei
Принадлежит:

In order to prevent cracks from occurring at the corners of semiconductor dies after the semiconductor dies have been bonded to other substrates, an opening is formed adjacent to the corners of the semiconductor dies, and the openings are filled and overfilled with a buffer material that has physical properties that are between the physical properties of the semiconductor die and an underfill material that is placed adjacent to the buffer material. 1. A device comprising:a semiconductor device with an opening located at a corner of the semiconductor device;a buffer material located at least partially within the opening, wherein the buffer material does not extend across the semiconductor device;a substrate bonded to the semiconductor device; andan underfill material located between the semiconductor device and the substrate, wherein the buffer material has a first property with a value located between a value of the semiconductor device and a value of the underfill material.2. The device of claim 1 , wherein the buffer material has a first sidewall that is aligned with a second sidewall of the semiconductor device.3. The device of claim 1 , wherein the buffer material has a rounded surface facing away from the semiconductor device.4. The device of claim 1 , wherein the value is a coefficient of thermal expansion.5. The device of claim 1 , wherein the value is a Young's modulus.6. The device of claim 1 , wherein the buffer material comprises epoxy.7. A device comprising:a first semiconductor device comprising a top surface and a sidewall, wherein the top surface and the sidewall are connected by a first surface that is misaligned from the top surface and the sidewall;a buffer material in physical contact with the top surface and covering the first surface, wherein a second surface of the buffer material is aligned with the sidewall; andan underfill material in physical contact with the top surface and the buffer material.8. The device of claim 7 , wherein the buffer ...

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Номер записи: 84
02-01-2020 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20200006206A1
Автор: Toyokazu Shibata
Принадлежит: Toshiba Corp

According to embodiments, there is a semiconductor device comprising: a first die pad; a first inner lead arranged inside a molded resin; a second die pad; and a second inner lead arranged inside the resin, wherein a part of the first inner lead and a part of the second inner lead are adhered and electrically connected to each other, a first semiconductor chip mounted on the first die pad is electrically connected to a second semiconductor chip mounted on the second die pad via the first inner lead and the second inner lead, and an end face of one end of the first inner lead and the second inner lead that are adhered to each other is exposed to a side surface of the resin.

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Номер записи: 85
02-01-2020 дата публикации

Planarizing RDLS in RDL-First Processes Through CMP Process

Номер: US20200006209A1
Автор: Hu Yu-Hsiang, Kuo Hung-Jui, Wang Po-Han, Yu Chen-Hua
Принадлежит:

A method includes forming a buffer dielectric layer over a carrier, and forming a first dielectric layer and a first redistribution line over the buffer dielectric layer. The first redistribution line is in the first dielectric layer. The method further includes performing a planarization on the first dielectric layer to level a top surface of the first dielectric layer, forming a metal post over and electrically coupling to the first redistribution line, and encapsulating the metal post in an encapsulating material. The encapsulating material contacts a top surface of the planarized top surface of the first dielectric layer. 1. A device comprising:a first dielectric layer;a first redistribution line and a second redistribution line in the first dielectric layer;an adhesive film over and contacting both a first top surface of the first dielectric layer and a second top surface of the first redistribution line;a device die over and adhered to the adhesive film; andan encapsulating material encapsulating the device die therein, wherein the encapsulating material contacts the first top surface of the first dielectric layer.2. The device of further comprising:a through-via over and contacting a third top surface of the second redistribution line, with the through-via encapsulated in the encapsulating material, wherein the through-via comprises a diffusion barrier and a metallic material over the diffusion barrier, and an entirety of the diffusion barrier is planar.3. The device of claim 2 , wherein the through-via is wider than the second redistribution line claim 2 , and the diffusion barrier extends on the first top surface of the first dielectric layer.4. The device of claim 2 , wherein the through-via is narrower than the second redistribution line claim 2 , and the encapsulating material contacts the second top surface of the second redistribution line.5. The device of further comprising:a second dielectric layer over the encapsulating material;a plurality of ...

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Номер записи: 86
02-01-2020 дата публикации

Semiconductor Device and Method of Manufacture

Номер: US20200006241A1
Автор: Lee Chien-Hsun, Liu Chung-Shi, WU Jiun Yi, Yu Chen-Hua
Принадлежит:

A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate. 1. A method of forming a semiconductor device , the method comprising:arranging a plurality of interconnect structures on a carrier substrate to form a reconstructed wafer;encapsulating the plurality of interconnect structures in a first encapsulant;electrically coupling at least one semiconductor component of each of a plurality of semiconductor dies to one or more of the plurality of interconnect structures;encasing the plurality of semiconductor dies and portions of the first encapsulant in a second encapsulant to form a wafer level package;removing the carrier substrate from the plurality of interconnect structures; andbonding a plurality of external contacts to first sides of the plurality of interconnect structures.2. The method of claim 1 , further comprising:exposing a plurality of first contact areas on second sides of each of the plurality of interconnect structures, the second sides of the plurality of interconnect structures being opposite the first sides of the plurality of interconnect structures.3. The method of claim 2 , wherein the electrically coupling the at least one semiconductor component of each of the plurality of semiconductor dies to one or more of the plurality of interconnect structures includes placing at least one semiconductor die of the plurality of semiconductor ...

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Номер записи: 87
03-01-2019 дата публикации

Integrated Circuit Packages and Methods of Forming Same

Номер: US20190006194A1
Автор: CHENG Li-Hui, Lin Jing-Cheng, Tsai Po-Hao
Принадлежит:

An integrated circuit package and a method of forming the same are provided. A method includes forming a conductive column over a carrier. An integrated circuit die is attached to the carrier, the integrated circuit die being disposed adjacent the conductive column. An encapsulant is formed around the conductive column and the integrated circuit die. The carrier is removed to expose a first surface of the conductive column and a second surface of the encapsulant. A polymer material is formed over the first surface and the second surface. The polymer material is cured to form an annular-shaped structure. An inner edge of the annular-shaped structure overlaps the first surface in a plan view. An outer edge of the annular-shaped structure overlaps the second surface in the plan view. 1. A method comprising:forming a conductive column over a carrier;attaching an integrated circuit die to the carrier, the integrated circuit die being disposed adjacent the conductive column;forming an encapsulant around the conductive column and the integrated circuit die;removing the carrier to expose a first surface of the conductive column and a second surface of the encapsulant;forming a polymer material over and in physical contact with the first surface and the second surface; andcuring the polymer material to form an annular-shaped structure, wherein an inner edge of the annular-shaped structure overlaps the first surface in a plan view, and wherein an outer edge of the annular-shaped structure overlaps the second surface in the plan view.2. The method of claim 1 , wherein the polymer material comprises a UV curable polymer material.3. The method of claim 2 , wherein curing the polymer material comprises exposing the polymer material to UV light.4. The method of claim 1 , wherein the polymer material comprises a thermally curable polymer material.5. The method of claim 4 , wherein curing the polymer material comprises performing a thermal treatment on the polymer material.6. The ...

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Номер записи: 88
03-01-2019 дата публикации

CHIP ENCAPSULATING METHOD AND CHIP ENCAPSULATING STRUCTURE

Номер: US20190006195A1
Автор: Qiu Yun, QU Lianjie, WANG DAN, ZHAO Hebin
Принадлежит:

A chip encapsulating method includes: fixing a plurality of wafers to a first panel level substrate, the wafer including a plurality of chips; forming a re-distribution layer on the wafer for each of the chips; forming each individual chip and the re-distribution layer connected to the chip by cutting; fixing the chip and the re-distribution layer connected thereto to a second panel level substrate; and encapsulating the chip to form an encapsulating layer. A chip encapsulating structure is prepared by the above described chip encapsulating method. 1. A chip encapsulating method , comprising:fixing a plurality of wafers to a first panel level substrate, the wafer comprising a plurality of chips;forming a re-distribution layer on the wafer for each of the chips;forming each individual chip and the re-distribution layer connected to the chip by cutting;fixing the chip and the re-distribution layer connected to the chip to a second panel level substrate; andencapsulating the chip to form an encapsulating layer.2. The chip encapsulating method of claim 1 , wherein when the chip and the re-distribution layer connected with the chip are fixed to the second panel level substrate claim 1 , the re-distribution layer is close to the second panel level substrate;after the chip is encapsulated, the chip encapsulating method further comprises:removing the second panel level substrate;fixing the encapsulating layer to a third panel level substrate, and forming a solder ball on one side of the re-distribution layer.3. The chip encapsulating method of claim 1 , wherein when the chip and the re-distribution layer connected with the chip are fixed to the second panel level substrate claim 1 , the re-distribution layer is close to the second panel level substrate;after the chip is encapsulated, the chip encapsulating method further comprises:cutting the encapsulating layer, to form each individual chip encapsulating body; andforming a solder ball for each of the chip encapsulating ...

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Номер записи: 89
03-01-2019 дата публикации

Release Film as Isolation Film in Package

Номер: US20190006199A1
Автор: Chih-Wei Wu, Hsien-Ju Tsou, Jing-Cheng Lin, Pu Wang, Szu-Wei Lu, Ying-Ching Shih
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method includes forming a release film over a carrier, forming a metal post on the release film, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, decomposing a first portion of the release film to separate a second portion of the release film from the carrier, and forming an opening in the release film to expose the metal post.

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Номер записи: 90
03-01-2019 дата публикации

Release Film as Isolation Film in Package

Номер: US20190006200A1
Автор: CHENG Li-Hui, Lin Jing-Cheng, Tsai Po-Hao
Принадлежит:

A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an encapsulating material, performing a planarization on the encapsulating material to expose the device, detaching the device and the encapsulating material from the carrier, etching the die-attach film to expose a back surface of the device, and applying a thermal conductive material on the back surface of the device. 1. A method comprising:forming a release film over a carrier;attaching a device over the release film through a die-attach film;encapsulating the device in an encapsulating material;performing a planarization on the encapsulating material to expose the device;forming redistribution lines to electrically couple to the device;detaching the device and the encapsulating material from the carrier while the die-attach film remains attached to the device;after the detaching of the device and the encapsulating material from the carrier, removing the die-attach film to expose a back surface of the device; andapplying a thermal conductive material on the back surface of the device.2. The method of further comprising:dispensing an underfill to contact the thermal conductive material.3. The method of claim 1 , wherein after the die-attach film is removed claim 1 , a recess is formed to extend into the encapsulating material claim 1 , and the thermal conductive material is filled into the recess.4. The method of claim 1 , wherein the thermal conductive material has a thermal conductivity higher than about 1 W/k*m.5. The method of claim 1 , wherein the thermal conductive material is selected from the group consisting of solder claim 1 , silver claim 1 , copper paste claim 1 , and combinations thereof.6. The method of further comprising:forming a metal post over the carrier, wherein the metal post is encapsulated in the encapsulating material, wherein in the removing the die-attach film, a portion of the ...

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Номер записи: 91
03-01-2019 дата публикации

OFFSET TEST PADS FOR WLCSP FINAL TEST

Номер: US20190006249A1
Автор: Pedersen Bard M.
Принадлежит:

A device configured for WLCSP, can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to the test pad; and a second RDL path that connects the test pad to a solder ball. In another case, a device configured for WLCSP can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball. A wafer having devices configured for WLCSP, can include: a first device having a first pad; a second device having a test pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball. 1. A device configured for wafer level chip scale packaging (WLCSP) , the device comprising:a) a first pad;b) a test pad offset from the first pad;c) a first redistribution layer (RDL) path that connects the first pad to the test pad; andd) a second RDL path that connects the test pad to a solder ball.2. The device of claim 1 , wherein the device comprises a serial non-volatile memory (NVM) device.3. The device of claim 1 , wherein the first and second RDL paths are in a same layer.4. The device of claim 1 , wherein the first and second RDL paths are in different layers.5. The device of claim 1 , further comprising a polymer layer that fully covers the first pad claim 1 , and leaves a portion of the test pad exposed.6. The device of claim 1 , wherein the device further comprises:a) a plurality of the first pads; andb) a plurality of the test pads, where each of the plurality of the test pads is offset from a corresponding of the plurality of the first pads by a same offset length.7. A device configured for WLCSP claim 1 , the device comprising:a) a first pad;b) a test pad offset from the first pad;c) a first RDL path that connects the first pad to a solder ball; andd) a second RDL path that connects the test pad to the solder ball.8. The device of claim ...

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Номер записи: 92
02-01-2020 дата публикации

Fan-Out Package with Cavity Substrate

Номер: US20200006307A1
Автор: Meng-Liang Lin, Meng-Wei Chou, Po-Hao Tsai, Po-Yao Chuang, Shin-puu Jeng, Techi WONG
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

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Номер записи: 93
03-01-2019 дата публикации

Semiconductor Device and Method of Manufacture

Номер: US20190006256A1
Автор: Huang Kuan-Yu, HUANG Sung-Hui, Kuo Li-Chung, Lee Long Hua, Li Pai Yuan, Shih Ying-Ching, Wu Chih-Wei
Принадлежит:

In order to prevent cracks from occurring at the corners of semiconductor dies after the semiconductor dies have been bonded to other substrates, an opening is formed adjacent to the corners of the semiconductor dies, and the openings are filled and overfilled with a buffer material that has physical properties that are between the physical properties of the semiconductor die and an underfill material that is placed adjacent to the buffer material. 1. A method of manufacturing a device , the method comprising:forming an opening along an outside edge of a semiconductor die;overfilling at least a portion of the opening with a buffer material; andplacing an underfill material adjacent to the buffer material.2. The method of claim 1 , further comprising singulating the semiconductor die from a semiconductor wafer after the overfilling the opening and before the placing the underfill material.3. The method of claim 2 , wherein the singulating the semiconductor die is performed by slicing through the buffer material and the semiconductor wafer with a saw.4. The method of claim 1 , further comprising bonding the semiconductor die to a first substrate prior to the placing the underfill material adjacent to the buffer material.5. The method of claim 4 , wherein the underfill material flows between the first substrate and the buffer material during the placing the underfill material.6. The method of claim 5 , further comprising bonding the first substrate to a second substrate.7. The method of claim 1 , wherein the overfilling at least the portion of the opening with the buffer material leaves the buffer material along an entire perimeter of the semiconductor die.8. A method of manufacturing a device claim 1 , the method comprising:partially singulating a first wafer to form a first opening within the first wafer, the first wafer comprising a semiconductor substrate of a first material, the first material having a first property with a first value, wherein the first opening ...

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Номер записи: 94
03-01-2019 дата публикации

Molded package with chip carrier comprising brazed electrically conductive layers

Номер: US20190006260A1
Автор: Hable Wolfram, Kessler Angela, Pavier Mark, Pugatschow Anton, Rimbert-Riviere Charles, Sielaff Michael, SOBKOWIAK Marco
Принадлежит:

A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant. 1. A method of manufacturing a package , the method comprising:forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces;mounting at least one electronic chip on the chip carrier;electrically coupling an electrically conductive contact structure with the at least one electronic chip; andencapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.2. The method according to claim 1 ,wherein at least one of the electrically conductive layers has a larger thickness than a thickness of the thermally conductive and electrically insulating core.3. The method according to claim 1 ,forming a brazing structure between the thermally conductive and electrically insulating core and the electrically conductive layers.4. The method according to claim 2 ,wherein the electrically conductive layers are brazed at a temperature of above than 600° C. to the electrically insulating core with the respective brazing structure in between.5. The ...

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Номер записи: 95
02-01-2020 дата публикации

Method of manufacturing a semiconductor device

Номер: US20200006327A1
Автор: Masatoshi Aketa, Yuki Nakano
Принадлежит: ROHM CO LTD

A method for manufacturing a semiconductor device having an SiC-IGBT and an SiC-MOSFET in a single semiconductor chip, including forming a second conductive-type SiC base layer on a substrate, and selectively implanting first and second conductive-type impurities into surfaces of the substrate and base layer to form a collector region, a channel region in a surficial portion of the SiC base layer, and an emitter region in a surficial portion of the channel region, the emitter region serving also as a source region of the SiC-MOSFET.

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Номер записи: 96
03-01-2019 дата публикации

METHODS OF FORMING MULTI-CHIP PACKAGE STRUCTURES

Номер: US20190006291A1
Автор: Haehn Nicholas S., Neal Nicholas
Принадлежит: Intel Corporation

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a first die disposed on a substrate, a second die disposed on the substrate, a molding compound disposed between the first die and the second die, wherein the molding compound is disposed on a top surface of the substrate. An epoxy material is disposed between a top portion of a sidewall of the first die and the molding compound, and a thermal interface material (TIM) is disposed on top surfaces of the first and second die, wherein the TIM extends over the entire length of the substrate. 1. A microelectronic package structure comprising:a first die on a substrate;a second die on the substrate adjacent the first die;an array of interconnect structures between a bottom surface of the first die and a top surface of the substrate;a first portion of an epoxy material on a top portion of a sidewall of the first die;a second portion of the epoxy material surrounding the array of interconnect structures;a molding compound, wherein a first portion of the molding compound is adjacent the first portion and the second portion of the epoxy material, wherein the first portion of the molding compound is on the top surface of the substrate and is adjacent a first sidewall of the second die, and wherein the first portion of the epoxy material is between the first portion of the molding compound and the top portion of the sidewall of the fir at die, wherein a top surface of the first portion of the molding compound, a top surface of the first portion of the epoxy material, and a top surface of the first die share a common plane with each other;a third portion of the epoxy material on a second sidewall of the second die, wherein the third portion of the epoxy material comprises a sidewall that is parallel with the second sidewall of the second die; anda second portion of the molding compound adjacent the third portion of the epoxy material, ...

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Номер записи: 97
03-01-2019 дата публикации

Semiconductor package and method for manufacturing a semiconductor package

Номер: US20190006308A1
Автор: Bernd Karl Appelt
Принадлежит: Advanced Semiconductor Engineering Inc

A semiconductor package includes at least one semiconductor element, an encapsulant, a first circuitry, a second circuitry and at least one first stud bump. The encapsulant covers at least a portion of the semiconductor element. The encapsulant has a first surface and a second surface opposite to the first surface. The first circuitry is disposed adjacent to the first surface of the encapsulant. The second circuitry is disposed adjacent to the second surface of the encapsulant. The first stud bump is disposed in the encapsulant, and electrically connects the first circuitry and the second circuitry. The first stud bump contacts the second circuitry directly.

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Номер записи: 98
03-01-2019 дата публикации

FAN-OUT PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20190006314A1
Автор: Chuang Po-Yao, Fang Tzu-Jui, Jeng Shin-Puu, Lin Yi-Jou, Liu Hsien-Wen
Принадлежит:

Package structures and methods for forming the same are provided. A package structure includes a semiconductor die. The semiconductor die includes a passivation layer over a semiconductor substrate. The semiconductor die also includes a conductive pad in the passivation layer. The passivation layer partially exposes a top surface of the conductive pad. The package structure also includes an encapsulation layer surrounding the semiconductor die. The package structure further includes a dielectric layer covering the semiconductor die and the encapsulation layer. In addition, the package structure includes a redistribution layer covering the dielectric layer. The redistribution layer extends in the dielectric layer to be physically connected to the top surface of the conductive pad. 1. A package structure , comprising:a semiconductor die, comprising:a passivation layer over a semiconductor substrate; anda conductive pad in the passivation layer, wherein the passivation layer partially exposes a top surface of the conductive pad;an encapsulation layer surrounding the semiconductor die;a conductive pillar surrounded by the encapsulation layer and protruding from the encapsulation layer;a dielectric layer covering the semiconductor die and the encapsulation layer; anda redistribution layer covering the dielectric layer, wherein the redistribution layer extends in the dielectric layer to be physically connected to the top surface of the conductive pad.2. The package structure as claimed in claim 1 , wherein the dielectric layer adjoins the conductive pad claim 1 , the passivation layer and the encapsulation layer.3. (canceled)4. The package structure as claimed in claim 1 , wherein the dielectric layer extends in the passivation layer claim 1 , and the top surface of the conductive pad is partially exposed by the dielectric layer.5. (canceled)6. The package structure as claimed in claim 1 ,wherein the redistribution layer is in contact with the conductive pillar and the ...

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Номер записи: 99
03-01-2019 дата публикации

THREE-DIMENSIONAL INTEGRATED FAN-OUT WAFER LEVEL PACKAGE

Номер: US20190006339A1
Автор: FAN Chun Ho, John, KUAH Teng Hock, Lau Hon Shing, Li Ming, LI Qingqian
Принадлежит:

An integrated fan-out wafer level package houses a semiconductor package having a first semiconductor die encapsulated by a dielectric compound. A plurality of redistribution layers are formed on a first side of the semiconductor package which are in electrical contact with contact pads of the first semiconductor die. A plurality of solder balls located on the first side of the semiconductor package is electrically connected to the contact pads of the semiconductor die via the redistribution layers. A second semiconductor die is further attached to the first side of the semiconductor package and is electrically connected to the contact pads of the first semiconductor die via the redistribution layers. 1. An integrated fan-out wafer level package comprising:a semiconductor package comprising a first semiconductor die encapsulated by a dielectric compound;a plurality of redistribution layers formed on a first side of the semiconductor package in electrical contact with contact pads of the first semiconductor die;a plurality of solder balls located on the first side of the semiconductor package and electrically connected to the contact pads of the semiconductor die via the redistribution layers; anda second semiconductor die attached to the first side of the semiconductor package and electrically connected to the contact pads of the first semiconductor die via the redistribution layers; anda plurality of wire bond pads formed on the redistribution layers on the first side of the semiconductor package and wire bonds directly connecting the second semiconductor die to the wire bond pads.2. The integrated fan-out wafer level package as claimed in claim 1 , wherein the plurality of solder balls is arranged for electrically mounting the integrated fan-out wafer level package onto a printed circuit board.3. The integrated fan-out wafer level package as claimed in claim 1 , wherein the first semiconductor die comprises an application processor chip.4. The integrated fan-out ...

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Номер записи: 100