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Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 810. Отображено 197.
18-05-2017 дата публикации

Metal Bump Joint Structure and Methods of Forming

Номер: US20170141067A1
Автор: Jing-Cheng Lin, LIN JING-CHENG, Lin Jing-Cheng
Принадлежит:

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

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Номер записи: 1
10-01-2017 дата публикации

Semiconductor packages and methods of forming the same

Номер: US0009543170B2
Автор: Chen-Hua Yu, Jing-Cheng Lin, Po-Hao Tsai, YU CHEN-HUA, LIN JING-CHENG, TSAI PO-HAO, Yu Chen-Hua, Lin Jing-Cheng, Tsai Po-Hao
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including forming a first die package, the first die package including a first die, a first electrical connector, and a first redistribution layer, the first redistribution layer being coupled to the first die and the first electrical connector, forming an underfill over the first die package, patterning the underfill to have an opening to expose a portion of the first electrical connector, and bonding a second die package to the first die package with a bonding structure, the bonding structure being coupled to the first electrical connector in the opening of the underfill.

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Номер записи: 2
13-04-2017 дата публикации

STACKING OF MULTIPLE DIES FOR FORMING THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) STRUCTURE

Номер: US20170103954A1
Автор: Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, WU CHIH-WEI, SHIH YING-CHING, LU SZU-WEI, LIN JING-CHENG, Wu Chih-Wei, Shih Ying-Ching, Lu Szu-Wei, Lin Jing-Cheng
Принадлежит:

Some embodiments of the present disclosure relate to a three dimensional integrated circuit (3DIC) structure. The 3DIC structure has a first die and a second die that is bonded to the first die by one or more bonding structures. The one or more bonding structures respectively have a first metal pad arranged on the first die and a second metal pad arranged on the second die. A first plurality of support structures are disposed between the first die and the second die. The first plurality of support structures include polymers and are laterally spaced apart from a closest one of the one or more bonding structures. The first plurality of support structures extend below an upper surface of the second metal pad.

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Номер записи: 3
28-02-2017 дата публикации

Probing chips during package formation

Номер: US0009583461B2
Автор: Jing-Cheng Lin, Szu-Wei Lu, LIN JING-CHENG, LU SZU-WEI, Lin Jing-Cheng, Lu Szu-Wei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A method includes bonding a first package component on a first surface of a second package component, and probing the first package component and the second package component from a second surface of the second package component. The step of probing is performed by probing through connectors on the second surface of the second package component. The connectors are coupled to the first package component. After the step of probing, a third package component is bonded on the first surface of the second package component.

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Номер записи: 4
19-09-2017 дата публикации

Hybrid bonding with through substrate via (TSV)

Номер: US9768143B2
Автор: LIN JING-CHENG, Lin Jing-Cheng
Принадлежит: TAIWAN SEMICONDUCTOR MFG CO LTD, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer bonded via a hybrid bonding structure, and the hybrid bonding structure includes a first conductive material embedded in a polymer material and a second conductive material embedded in a second polymer material. The first conductive material of the first semiconductor wafer bonded to the second conductive material of the second semiconductor wafer and the first polymer material of the first semiconductor wafer is bonded to the second polymer material of the second semiconductor wafer. The semiconductor device structure further includes at least one through substrate via (TSV) extending from a bottom surface of the second semiconductor wafer to a top surface of the first semiconductor wafer.

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Номер записи: 5
28-07-2016 дата публикации

Semiconductor Device and Method of Manufactures

Номер: US20160218049A1
Автор: Jing-Cheng Lin, Po-Hao Tsai, Li-Hui Cheng, LIN JING-CHENG, TSAI PO-HAO, CHENG LI-HUI, Lin Jing-Cheng, Tsai Po-Hao, Cheng Li-Hui
Принадлежит:

A semiconductor device and method of manufacture is provided. A reflowable material is placed in electrical connection with a through via, wherein the through via extends through an encapsulant. A protective layer is formed over the reflowable material. In an embodiment an opening is formed within the protective layer to expose the reflowable material. In another embodiment the protective layer is formed such that the reflowable material is extending away from the protective layer.

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Номер записи: 6
16-05-2017 дата публикации

Integrated circuit structure having dies with connectors

Номер: US0009653423B2
Автор: Jing-Cheng Lin, Cheng-Lin Huang, LIN JING-CHENG, HUANG CHENG-LIN, Lin Jing-Cheng, Huang Cheng-Lin
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

An embodiment is an integrated circuit structure including a first die having a bump structure, and a second die having a pad structure. The first die is attached to the second die by bonding the bump structure and the pad structure. The bump structure includes a metal pillar, a metal cap layer on the metal pillar, a metal insertion layer on the metal cap layer, and a solder layer on the metal insertion layer. The pad structure includes at least one of a nickel (Ni) layer, a palladium (Pd) layer or a gold (Au) layer.

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Номер записи: 7
28-02-2017 дата публикации

Integrated circuit structure and method for reducing polymer layer delamination

Номер: US0009583424B2
Автор: Jing-Cheng Lin, Jui-Pin Hung, Hsien-Wen Liu, Min-Chen Lin, LIN JING-CHENG, HUNG JUI-PIN, LIU HSIEN-WEN, LIN MIN-CHEN, Lin Jing-Cheng, Hung Jui-Pin, Liu Hsien-Wen, Lin Min-Chen
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.

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Номер записи: 8
17-11-2016 дата публикации

METHOD OF FORMING A SEMICONDUCTOR PACKAGE

Номер: US20160336280A1
Автор: Jing-Cheng Lin, Chin-Chuan Chang, Jui-Pin Hung, LIN JING-CHENG, CHANG CHIN-CHUAN, HUNG JUI-PIN, Lin Jing-Cheng, Chang Chin-Chuan, Hung Jui-Pin
Принадлежит:

A method of forming a semiconductor package includes forming an interconnecting structure on an adhesive layer, wherein the adhesive layer is on a carrier. The method further includes placing a semiconductor die on a surface of the interconnecting structure. The method further includes placing a package structure on the surface of the interconnecting structure, wherein the semiconductor die fits in a space between the interconnecting structure and the package structure. The method further includes performing a reflow to bond the package structure to the interconnecting structure.

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Номер записи: 9
12-10-2017 дата публикации

Multi-Chip Fan Out Package and Methods of Forming the Same

Номер: US20170294409A1
Автор: Chen-Hua Yu, Jing-Cheng Lin, Jui-Pin Hung, YU CHEN-HUA, LIN JING-CHENG, HUNG JUI-PIN, Yu Chen-Hua, Lin Jing-Cheng, Hung Jui-Pin
Принадлежит:

A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.

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Номер записи: 10
10-08-2017 дата публикации

Semiconductor Device and Method

Номер: US20170229414A1
Автор: Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin, CHENG LI-HUI, TSAI PO-HAO, LIN JING-CHENG, Cheng Li-Hui, Tsai Po-Hao, Lin Jing-Cheng
Принадлежит:

A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.

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Номер записи: 11
18-08-2016 дата публикации

CIS Chips and Methods for Forming the Same

Номер: US20160240583A1
Автор: Chen-Hua Yu, Wen-Chih Chiou, Jing-Cheng Lin, YU CHEN-HUA, CHIOU WEN-CHIH, LIN JING-CHENG, Yu Chen-Hua, Chiou Wen-Chih, Lin Jing-Cheng
Принадлежит:

A device includes a semiconductor substrate, an image sensor at a front surface of the semiconductor substrate, and a plurality of dielectric layers over the image sensor. A color filter and a micro lens are disposed over the plurality of dielectric layers and aligned to the image sensor. A through via penetrates through the semiconductor substrate. A Redistribution Line (RDL) is disposed over the plurality of dielectric layers, wherein the RDL is electrically coupled to the through via. A polymer layer covers the RDL.

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Номер записи: 12
31-01-2017 дата публикации

Metal bump joint structure

Номер: US0009559072B2
Автор: Jing-Cheng Lin, LIN JING-CHENG, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

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Номер записи: 13
08-06-2017 дата публикации

Semiconductor Device and Method of Manufactures

Номер: US20170162551A1
Автор: Jing-Cheng Lin, Po-Hao Tsai, Li-Hui Cheng, LIN JING-CHENG, TSAI PO-HAO, CHENG LI-HUI, Lin Jing-Cheng, Tsai Po-Hao, Cheng Li-Hui
Принадлежит:

A semiconductor device and method of manufacture is provided. A reflowable material is placed in electrical connection with a through via, wherein the through via extends through an encapsulant. A protective layer is formed over the reflowable material. In an embodiment an opening is formed within the protective layer to expose the reflowable material. In another embodiment the protective layer is formed such that the reflowable material is extending away from the protective layer.

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Номер записи: 14
20-02-2018 дата публикации

De-bonding and cleaning process and system

Номер: US0009895871B2
Автор: Ying-Ching Shih, Jing-Cheng Lin, Szu-Wei Lu, SHIH YING CHING, LIN JING CHENG, LU SZU WEI, Shih Ying-Ching, Lin Jing-Cheng, Lu Szu-Wei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

Methods and tools for de-bonding and cleaning substrates are disclosed. A method includes de-bonding a surface of a first substrate from a second substrate, and after de-bonding, cleaning the surface of the first substrate. The cleaning comprises physically contacting a cleaning mechanism to the surface of the first substrate. A tool includes a de-bonding module and a cleaning module. The de-bonding module comprises a first chuck, a radiation source configured to emit radiation toward the first chuck, and a first robot arm having a vacuum system. The vacuum system is configured to secure and remove a substrate from the first chuck. The cleaning module comprises a second chuck, a spray nozzle configured to spray a fluid toward the second chuck, and a second robot arm having a cleaning device configured to physically contact the cleaning device to a substrate on the second chuck.

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Номер записи: 15
14-11-2017 дата публикации

Semiconductor package manufacturing method

Номер: US0009818697B2
Автор: Jing-Cheng Lin, Po-Hao Tsai, Ying Ching Shih, Szu Wei Lu, LIN JING-CHENG, TSAI PO-HAO, SHIH YING CHING, LU SZU WEI, Lin Jing-Cheng, Tsai Po-Hao, Shih Ying Ching, Lu Szu Wei
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., TAIWAN SEMICONDUCTOR MFG CO LTD

The present disclosure provides a manufacturing method of a semiconductor packaging, including forming a redistribution layer (RDL) on a carrier, defining an active portion and a dummy portion of the RDL, and placing a semiconductor die over the dummy portion of the RDL. The present disclosure also provides a manufacturing method of a package-on-package (PoP) semiconductor structure, including forming a first redistribution layer (RDL) on a polymer-based layer of a carrier, defining an active portion and a dummy portion of the first RDL, placing a semiconductor die over the dummy portion of the first RDL, a back side of the semiconductor die facing the first RDL, forming a second RDL over a front side of the semiconductor die, the front side having at least one contact pad, and attaching a semiconductor package at the back side of the semiconductor die.

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Номер записи: 16
29-11-2016 дата публикации

Semiconductor device structure comprising a plurality of metal oxide fibers and method for forming the same

Номер: US0009508664B1
Автор: Jing-Cheng Lin, Chen-Hua Yu, Szu-Wei Lu, Yen-Yao Chi, LIN JING-CHENG, YU CHEN-HUA, LU SZU-WEI, CHI YEN-YAO, Lin Jing-Cheng, Yu Chen-Hua, Lu Szu-Wei, Chi Yen-Yao
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a conductive structure over the substrate. The semiconductor device structure includes first metal oxide fibers over the conductive structure. The semiconductor device structure includes a dielectric layer over the substrate and covering the conductive structure and the first metal oxide fibers. The dielectric layer fills gaps between the first metal oxide fibers.

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Номер записи: 17
17-10-2017 дата публикации

3D packages and methods for forming the same

Номер: US0009793187B2
Автор: Shih Ting Lin, Kung-Chen Yeh, Szu-Wei Lu, Jing-Cheng Lin, LIN SHIH TING, YEH KUNG-CHEN, LU SZU-WEI, LIN JING-CHENG, Lin Shih Ting, Yeh Kung-Chen, Lu Szu-Wei, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including bonding a die to a top surface of a first substrate, the die being electrically coupled to the first substrate, and forming a support structure on the top surface of the first substrate, the support structure being physically separated from the die with a top surface of the support structure being coplanar with a top surface of the die. The method further includes performing a sawing process on the first substrate, the sawing process sawing through the support structure.

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Номер записи: 18
02-08-2016 дата публикации

Methods of packaging semiconductor devices and structures thereof

Номер: US0009406581B2
Автор: Jing-Cheng Lin, Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung, LIN JING-CHENG, HUNG JUI-PIN, LIN YI-HANG, TUNG TSAN-HUA, Lin Jing-Cheng, Hung Jui-Pin, Lin Yi-Hang, Tung Tsan-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

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Номер записи: 19
27-06-2017 дата публикации

Multi-chip fan out package and methods of forming the same

Номер: US0009691706B2
Автор: Chen-Hua Yu, Jing-Cheng Lin, Jui-Pin Hung, YU CHEN-HUA, LIN JING-CHENG, HUNG JUI-PIN, Yu Chen-Hua, Lin Jing-Cheng, Hung Jui-Pin
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., YU CHEN-HUA, LIN JING-CHENG, HUNG JUI-PIN, TAIWAN SEMICONDUCTOR MFG CO LTD, Yu Chen-Hua, Lin Jing-Cheng, Hung Jui-Pin

A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.

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Номер записи: 20
04-07-2017 дата публикации

Mechanisms for forming package structure

Номер: US0009698135B2
Автор: Jing-Cheng Lin, Po-Hao Tsai, LIN JING-CHENG, TSAI PO-HAO, Lin Jing-Cheng, Tsai Po-Hao
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Co., Ltd

A method for forming a package structure is provided. The method includes forming a plurality of conductive columns over a carrier substrate and forming an interfacial layer over sidewalls and tops of the conductive columns. The method also includes disposing a semiconductor die over a planar portion of the interfacial layer. The method further includes forming a molding compound to partially or completely encapsulate the semiconductor die, the conductive columns, and the interfacial layer such that the molding compound is in direct contact with the interfacial layer.

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Номер записи: 21
27-03-2018 дата публикации

Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure

Номер: US9929109B2
Автор: WU CHIH-WEI, SHIH YING-CHING, LU SZU-WEI, LIN JING-CHENG, Wu Chih-Wei, Shih Ying-Ching, Lu Szu-Wei, Lin Jing-Cheng
Принадлежит: TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Co., Ltd.

Some embodiments of the present disclosure relate to a three dimensional integrated circuit (3DIC) structure. The 3DIC structure has a first die and a second die that is bonded to the first die by one or more bonding structures. The one or more bonding structures respectively have a first metal pad arranged on the first die and a second metal pad arranged on the second die. A first plurality of support structures are disposed between the first die and the second die. The first plurality of support structures include polymers and are laterally spaced apart from a closest one of the one or more bonding structures. The first plurality of support structures extend below an upper surface of the second metal pad.

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Номер записи: 22
26-09-2017 дата публикации

Semiconductor devices, methods of manufacture thereof, and semiconductor device packages

Номер: US0009773724B2
Автор: I-Ting Chen, Ying-Ching Shih, Po-Hao Tsai, Szu Wei Lu, Jing-Cheng Lin, CHEN I-TING, SHIH YING-CHING, TSAI PO-HAO, LU SZU WEI, LIN JING-CHENG, Chen I-Ting, Shih Ying-Ching, Tsai Po-Hao, Lu Szu Wei, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer.

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Номер записи: 23
05-06-2013 дата публикации

Bump structures for multi-chip packaging

Номер: CN103137596A
Автор: Yu Chen-Hua, Lin Jing-Cheng
Принадлежит:

Mechanisms for forming a multi-chip package described enable chips with different bump sizes being packaged to a common substrate. A chip with larger bumps can be bonded with two or more smaller bumps on a substrate. Conversely, two or more small bumps on a chip may be bonded with a large bump on a substrate. By allowing bumps with different sizes to be bonded together, chips with different bump sizes can be packaged together to form a multi-chip package. The invention provides bump structures for multi-chip packaging.

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Номер записи: 24
25-04-2017 дата публикации

Semicondutor device and method of manufacture

Номер: US0009633934B2
Автор: Jing-Cheng Lin, Po-Hao Tsai, Li-Hui Cheng, Porter Chen, LIN JING-CHENG, TSAI PO-HAO, CHENG LI-HUI, CHEN PORTER, Lin Jing-Cheng, Tsai Po-Hao, Cheng Li-Hui, Chen Porter
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor device and method for providing an enhanced removal of heat from a semiconductor die within an integrated fan out package on package configuration is presented. In an embodiment a metal layer is formed on a backside of the semiconductor die, and the semiconductor die along and through vias are encapsulated. Portions of the metal layer are exposed and a thermal die is connected to remove heat from the semiconductor die.

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Номер записи: 25
27-03-2018 дата публикации

Chip package structure with adhesive layer

Номер: US9929128B1
Автор: CHENG LI-HUI, TSAI PO-HAO, LIN JING-CHENG, LIN YI-HANG, Cheng Li-Hui, Tsai Po-Hao, Lin Jing-Cheng, Lin Yi-Hang
Принадлежит: TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Co., Ltd.

A chip package structure is provided. The chip package structure includes a redistribution structure. The chip package structure includes a first chip over the redistribution structure. The first chip has a front surface and a back surface opposite to the front surface, and the front surface faces the redistribution structure. The chip package structure includes an adhesive layer on the back surface. The adhesive layer is in direct contact with the back surface, and a first maximum length of the adhesive layer is less than a second maximum length of the first chip. The chip package structure includes a molding compound layer over the redistribution structure and surrounding the first chip and the adhesive layer. A first top surface of the adhesive layer is substantially coplanar with a second top surface of the molding compound layer.

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Номер записи: 26
02-01-2018 дата публикации

Underfill dispensing in 3D IC using metrology

Номер: US0009859181B2
Автор: Jing-Cheng Lin, Szu-Wei Lu, I-Hsuan Peng, LIN JING-CHENG, LU SZU-WEI, PENG I-HSUAN, Lin Jing-Cheng, Lu Szu-Wei, Peng I-Hsuan
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

In some embodiments, a semiconductor device includes a first die, a second die coupled to a first surface of the first die, and a third die coupled to the first surface of the first die. The semiconductor device further includes an underfill material disposed between the first die and the second die and between the first die and the third die. A first volume of the underfill material for the second die is different than a second volume of the underfill material for the third die.

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Номер записи: 27
16-08-2016 дата публикации

Method of three dimensional integrated circuit assembly

Номер: US0009418876B2
Автор: Jing-Cheng Lin, Weng-Jin Wu, Shih Ting Lin, Cheng-Lin Huang, Szu Wei Lu, Shin-Puu Jeng, Chen-Hua Yu, LIN JING-CHENG, WU WENG-JIN, LIN SHIH TING, HUANG CHENG-LIN, LU SZU WEI, JENG SHIN-PUU, YU CHEN-HUA, Lin Jing-Cheng, Wu Weng-Jin, Lin Shih Ting, Huang Cheng-Lin, Lu Szu Wei, Jeng Shin-Puu, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., LIN JING-CHENG, WU WENG-JIN, LIN SHIH TING, HUANG CHENG-LIN, LU SZU WEI, JENG SHIN-PUU, YU CHEN-HUA, TAIWAN SEMICONDUCTOR MFG CO LTD, Lin Jing-Cheng, Wu Weng-Jin, Lin Shih Ting, Huang Cheng-Lin, Lu Szu Wei, Jeng Shin-Puu, Yu Chen-Hua

A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

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Номер записи: 28
18-10-2016 дата публикации

Fan out package structure and methods of forming

Номер: US0009472516B2
Автор: Pu Wang, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, WANG PU, SHIH YING-CHING, LU SZU-WEI, LIN JING-CHENG, Wang Pu, Shih Ying-Ching, Lu Szu-Wei, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

An embodiment is a structure comprising a die having a pad on a surface and an encapsulant at least laterally encapsulating the die. The pad is exposed through the encapsulant. The structure further includes a first dielectric layer over the encapsulant and the die, a first conductive pattern over the first dielectric layer, and a second dielectric layer over the first conductive pattern and the first dielectric layer. The first dielectric layer and the second dielectric layer have a first opening to the pad of the die. The structure further includes a second conductive pattern over the second dielectric layer and in the first opening. The second conductive pattern adjoins a sidewall of the first dielectric layer in the first opening and a sidewall of the second dielectric layer in the first opening.

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Номер записи: 29
02-02-2017 дата публикации

FAN-OUT PACKAGES AND METHODS OF FORMING SAME

Номер: US20170033063A1
Автор: Jing-Cheng Lin, Jeffrey Chang, Chun-Hsing Su, Tsei-Chung Fu, Yi-Chao Mao, LIN JING-CHENG, CHANG JEFFREY, SU CHUN-HSING, FU TSEI-CHUNG, MAO YI-CHAO, Lin Jing-Cheng, Chang Jeffrey, Su Chun-Hsing, Fu Tsei-Chung, Mao Yi-Chao
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

An embodiment a device package includes a semiconductor die, a molding compound extending along sidewalls of the semiconductor die, and a planarizing polymer layer over the molding compound and extending along the sidewalls of the semiconductor die. The molding compound includes first fillers, and the planarizing polymer layer includes second fillers smaller than the first fillers. The device package further includes one or more fan-out redistribution layers (RDLs) electrically connected to the semiconductor die, wherein the one or more fan-out RDLs extend past edges of the semiconductor die onto a top surface of the planarizing polymer layer.

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Номер записи: 30
19-01-2017 дата публикации

Semiconductor Device and Method of Manufacture

Номер: US20170018531A1
Автор: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai, LIN JING-CHENG, YU CHEN-HUA, TSAI PO-HAO, Lin Jing-Cheng, Yu Chen-Hua, Tsai Po-Hao
Принадлежит:

An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.

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Номер записи: 31
04-10-2016 дата публикации

Interconnect structure for package-on-package devices and a method of fabricating

Номер: US0009460987B2
Автор: Jui-Pin Hung, Jing-Cheng Lin, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh, Der-Chyang Yeh, HUNG JUI-PIN, LIN JING-CHENG, TSAI PO-HAO, LIN YI-JOU, CHEN SHUO-MAO, YEH CHIUNG-HAN, YEH DER-CHYANG, Hung Jui-Pin, Lin Jing-Cheng, Tsai Po-Hao, Lin Yi-Jou, Chen Shuo-Mao, Yeh Chiung-Han, Yeh Der-Chyang
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.

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Номер записи: 32
12-01-2017 дата публикации

Integrated Fan-Out Structure with Openings in Buffer Layer

Номер: US20170012024A1
Автор: Wu Sen Chiu, Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin, CHIU WU SEN, CHENG LI-HUI, TSAI PO-HAO, LIN JING-CHENG, Chiu Wu Sen, Cheng Li-Hui, Tsai Po-Hao, Lin Jing-Cheng
Принадлежит:

A package includes a molding compound, a through-via penetrating through the molding compound, a device die molded in the molding compound, and a buffer layer on and contacting the molding compound. An opening is through the buffer layer to the through-via. The buffer layer has ripples in a plane parallel to an interface between the molding compound and the buffer layer and around a circumference of the opening. Other embodiments contemplate an additional package bonded to the package, and methods for forming the package. 1. A structure comprising: a through-via extending through a molding compound;', 'a device die encapsulated in the molding compound;', 'a buffer layer over the molding compound;', 'an opening disposed in the buffer layer and extending to the through-via, wherein the buffer layer comprises ripples around a circumference of the opening; and', 'a guiding trench encircling a portion of the buffer layer in a top-down view of the structure, wherein the portion of the buffer layer at least partially overlaps the device die., 'a first package comprising2. The structure of claim 1 , wherein the first package further comprises a laminating film contacting the buffer layer claim 1 , wherein the buffer layer is disposed between the laminating film and the molding compound claim 1 , and wherein the opening extends through the laminating film.3. The structure of claim 1 , wherein the ripples are in a periodic configuration around the circumference of the opening.4. The structure of further comprising a second package bonded to the first package by an electrical connector disposed in the opening.5. The structure of further comprising an underfill around the electrical connector and disposed between the first package and the second package claim 4 , wherein the underfill is partially disposed in the guiding trench.6. The structure of further comprising an additional guiding ring encircling the guiding ring in a top-down view of the structure.7. The structure of ...

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Номер записи: 33
23-03-2017 дата публикации

Backside Redistribution Layer (RDL) Structure

Номер: US20170084550A1
Автор: Po-Hao Tsai, Jing-Cheng Lin, TSAI PO-HAO, LIN JING-CHENG, Tsai Po-Hao, Lin Jing-Cheng
Принадлежит:

An embodiment package on package (PoP) device includes a molding compound having a metal via embedded therein, a passivation layer disposed over the molding compound, the passivation layer including a passivation layer recess vertically aligned with the metal via, and a redistribution layer bond pad capping the metal via, a portion of the redistribution layer bond pad within the passivation layer recess projecting above a top surface of the molding compound.

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Номер записи: 34
27-07-2017 дата публикации

Sawing Underfill in Packaging Processes

Номер: US20170213809A1
Автор: Szu-Wei Lu, Ying-Da Wang, Li-Chung Kuo, Jing-Cheng Lin, LU SZU-WEI, WANG YING-DA, KUO LI-CHUNG, LIN JING-CHENG, Lu Szu-Wei, Wang Ying-Da, Kuo Li-Chung, Lin Jing-Cheng
Принадлежит:

A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

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Номер записи: 35
19-12-2017 дата публикации

Packages, packaging methods, and packaged semiconductor devices

Номер: US0009847315B2
Автор: Shih Ting Lin, Szu Wei Lu, Jui-Pin Hung, Jing-Cheng Lin, LIN SHIH TING, LU SZU WEI, HUNG JUI-PIN, LIN JING-CHENG, Lin Shih Ting, Lu Szu Wei, Hung Jui-Pin, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

Packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a redistribution layer (RDL) and a plurality of through package vias (TPV's) coupled to the RDL. Each of the plurality of TPV's comprises a first region proximate the RDL and a second region opposite the first region. The first region comprises a first width, and the second region comprises a second width. The second width is greater than the first width.

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Номер записи: 36
31-07-2013 дата публикации

Bump structural designs to minimize package defects

Номер: CN103227163A
Автор: Lin Jing-Cheng, Huang Cheng-Lin
Принадлежит:

The mechanisms for forming bump structures enable forming bump structures between a chip and a substrate eliminating or reducing the risk of solder shorting, flux residue and voids in underfill. A lower limit can be established for a cc ratio, defined by dividing the total height of copper posts in a bonded bump structure divided by the standoff of the bonded bump structure, to avoid shorting. A lower limit may also be established for standoff the chip package to avoid flux residue and underfill void formation. Further, aspect ratio of a copper post bump has a lower limit to avoid insufficient standoff and a higher limit due to manufacturing process limitation. By following proper bump design and process guidelines, yield and reliability of chip packages may be increases.

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Номер записи: 37
11-04-2017 дата публикации

Sawing underfill in packaging processes

Номер: US0009620430B2
Автор: Szu Wei Lu, Ying-Da Wang, Li-Chung Kuo, Jing-Cheng Lin, LU SZU WEI, WANG YING-DA, KUO LI-CHUNG, LIN JING-CHENG, Lu Szu Wei, Wang Ying-Da, Kuo Li-Chung, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., LU SZU WEI, WANG YING-DA, KUO LI-CHUNG, LIN JING-CHENG, TAIWAN SEMICONDUCTOR MFG CO LTD, Lu Szu Wei, Wang Ying-Da, Kuo Li-Chung, Lin Jing-Cheng

A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

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Номер записи: 38
22-07-2015 дата публикации

Fan-out type package and forming method thereof

Номер: CN104795371A
Автор: Shih Wan-Ting, Liu Nai-Wei, Lin Jing-Cheng, Huang Cheng-Lin
Принадлежит:

The invention provides a package, and one embodiment is the package comprising moulding compound. The moulding compound horizontally packages a chip with a touch bonding pad. A first dielectric layer is formed on the moulding compound and the chip, and is provided with a first opening which exposing the touch bonding pad. A first metalizing layer is formed on the first dielectric layer. The first metalizing layer fills the first opening. A second dielectric layer is formed on the first metalizing layer and the first dielectric layer, and is provided with a second opening above the first opening. A second metalizing layer is formed on the second dielectric layer and is formed in the second opening. The invention also provides a method for manufacturing the packages.

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Номер записи: 39
22-09-2016 дата публикации

Packaged Semiconductor Devices, Methods of Packaging Semiconductor Devices, and PoP Devices

Номер: US20160276278A1
Автор: Po-Hao Tsai, Jui-Pin Hung, Jing-Cheng Lin, TSAI PO-HAO, HUNG JUI-PIN, LIN JING-CHENG, Tsai Po-Hao, Hung Jui-Pin, Lin Jing-Cheng
Принадлежит:

Packaged semiconductor devices, methods of packaging semiconductor devices, and package-on-package (PoP) devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming through-package vias (TPVs) over a carrier, and coupling a semiconductor device to the carrier. The semiconductor device includes contact pads disposed on a surface thereof and an insulating material disposed over the contact pads. A molding material is formed over the carrier between the TPVs and the semiconductor device. Openings are formed in the insulating material using a laser drilling process over the contact pads, and a redistribution layer (RDL) is formed over the insulating material and the openings in the insulating material. A portion of the RDL is coupled to a top surface of each of the contact pads.

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Номер записи: 40
08-11-2016 дата публикации

Thermal dissipation through seal rings in 3DIC structure

Номер: US0009490190B2
Автор: Jing-Cheng Lin, Shih-Yi Syu, LIN JING-CHENG, SYU SHIH-YI, Lin Jing-Cheng, Syu Shih-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.

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Номер записи: 41
22-08-2017 дата публикации

Semiconductor package and method of forming the same

Номер: US0009741693B2
Автор: Chin-Fu Kao, Tsei-Chung Fu, Jing-Cheng Lin, KAO CHIN-FU, FU TSEI-CHUNG, LIN JING-CHENG, Kao Chin-Fu, Fu Tsei-Chung, Lin Jing-Cheng
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., TAIWAN SEMICONDUCTOR MFG CO LTD

The present disclosure provides a semiconductor package, including a first device having a first joining surface, a first conductive component at least partially protruding from the first joining surface, a second device having a second joining surface facing the first joining surface, and a second conductive component at least exposing from the second joining surface. The first conductive component and the second conductive component form a joint having a first beak. The first beak points to either the first joining surface or the second joining surface.

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Номер записи: 42
23-08-2016 дата публикации

3-D package having plurality of substrates

Номер: US0009425128B2
Автор: Chin-Chuan Chang, Jing-Cheng Lin, Chen-Hua Yu, CHANG CHIN-CHUAN, LIN JING-CHENG, YU CHEN-HUA, Chang Chin-Chuan, Lin Jing-Cheng, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A package includes an interposer, which includes a first substrate free from through-vias therein, redistribution lines over the first substrate, and a first plurality of connectors over and electrically coupled to the redistribution lines. A first die is over and bonded to the first plurality of connectors. The first die includes a second substrate, and through-vias in the second substrate. A second die is over and bonded to the plurality of connectors. The first die and the second die are electrically coupled to each other through the redistribution lines. A second plurality of connectors is over the first die and the second die. The second plurality of connectors is electrically coupled to the first plurality of connectors through the through-vias in the second substrate.

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Номер записи: 43
20-10-2016 дата публикации

Fan-out POP Structure with Inconsecutive Polymer Layer

Номер: US20160307871A1
Автор: Yi-Lin Tsai, Jeffrey Chang, Jing-Cheng Lin, Nai-Wei Liu, Tsei-Chung Fu, TSAI YI-LIN, CHANG JEFFREY, LIN JING-CHENG, LIU NAI-WEI, FU TSEI-CHUNG, Tsai Yi-Lin, Chang Jeffrey, Lin Jing-Cheng, Liu Nai-Wei, Fu Tsei-Chung
Принадлежит:

A package includes a device die, a molding material molding at least a portion of the device die therein, and a through-via substantially penetrating through the molding material. The package further includes a dielectric layer contacting the through-via and the molding material, and a die attach film attached to a backside of the device die. The die attach film includes a portion extending in the dielectric layer.

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Номер записи: 44
05-01-2017 дата публикации

3DIC Stacking Device and Method of Manufacture

Номер: US20170005073A1
Автор: Jing-Cheng Lin, Chen-Hua Yu, LIN JING-CHENG, YU CHEN-HUA, Lin Jing-Cheng, Yu Chen-Hua
Принадлежит:

A system and method for stacking semiconductor devices in three dimensions is provided. In an embodiment two or more semiconductor dies are attached to a carrier and encapsulated. Connections of the two or more semiconductor dies are exposed, and the two or more semiconductor dies may be thinned to form connections on an opposite side. Additional semiconductor dies may then be placed in either an offset or overhanging position. 1. A semiconductor device comprising:a first semiconductor die encapsulated by a first encapsulant;at least one through substrate via extending through at least a portion of the first semiconductor die and being exposed on a first side of the first semiconductor die;first external connectors located on a second side of the first semiconductor die;a first redistribution layer in electrical connection with the first external connectors, the first redistribution layer extending over the first encapsulant; anda second semiconductor die in electrical connection with the at least one through substrate via, the second semiconductor die extending over the first encapsulant.2. The semiconductor device of claim 1 , further comprising;a third semiconductor die encapsulated by the first encapsulant; anda fourth semiconductor die in electrical connection with the third semiconductor die, the fourth semiconductor die extending over the first encapsulant.3. The semiconductor device of claim 2 , wherein the second semiconductor die and the fourth semiconductor die are encapsulated by a second encapsulant.4. The semiconductor device of claim 1 , further comprising a second redistribution layer in electrical connection with the at least one through substrate via claim 1 , the second redistribution layer extending over the first encapsulant.5. The semiconductor device of claim 1 , wherein the second semiconductor die is offset from the first semiconductor die.6. The semiconductor device of claim 5 , wherein the offset is between about 100 um and about 3 mm.7. ...

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Номер записи: 45
10-08-2017 дата публикации

Package Structure and Method for Forming the Same

Номер: US20170229404A1
Автор: Chen-Hua Yu, Jing-Cheng Lin, Tsei-Chung Fu, YU CHEN-HUA, LIN JING-CHENG, FU TSEI-CHUNG, Yu Chen-Hua, Lin Jing-Cheng, Fu Tsei-Chung
Принадлежит:

A package structure and method for forming the same are provided. The package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer. The package structure includes a first insulating layer formed on the conductive structure, and the first insulating layer includes monovalent metal oxide. A second insulating layer is formed between the first insulating layer and the package layer. The second insulating layer includes monovalent metal oxide, and a weight ratio of the monovalent metal oxide in the second insulating layer is greater than a weight ratio of the monovalent metal oxide in first insulating layer.

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Номер записи: 46
15-11-2016 дата публикации

Pillar design for conductive bump

Номер: US0009496235B2
Автор: Cheng-Chieh Hsieh, Cheng-Lin Huang, Po-Hao Tsai, Shang-Yun Hou, Jing-Cheng Lin, Shin-Puu Jeng, HSIEH CHENG-CHIEH, HUANG CHENG-LIN, TSAI PO-HAO, HOU SHANG-YUN, LIN JING-CHENG, JENG SHIN-PUU, Hsieh Cheng-Chieh, Huang Cheng-Lin, Tsai Po-Hao, Hou Shang-Yun, Lin Jing-Cheng, Jeng Shin-Puu
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

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Номер записи: 47
09-05-2017 дата публикации

Semiconductor device and method

Номер: US0009646918B2
Автор: Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin, CHENG LI-HUI, TSAI PO-HAO, LIN JING-CHENG, Cheng Li-Hui, Tsai Po-Hao, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.

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Номер записи: 48
10-08-2017 дата публикации

Integrated Fan-Out Structure with Guiding Trenches in Buffer Layer

Номер: US20170229433A1
Автор: Po-Hao Tsai, Feng-Cheng Hsu, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin, TSAI PO-HAO, HSU FENG-CHENG, CHENG LI-HUI, HUNG JUI-PIN, LIN JING-CHENG, Tsai Po-Hao, Hsu Feng-Cheng, Cheng Li-Hui, Hung Jui-Pin, Lin Jing-Cheng
Принадлежит:

A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the buffer layer, wherein the guiding trench is misaligned with the device die.

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Номер записи: 49
25-10-2016 дата публикации

Alignment mark and method of formation

Номер: US0009478480B2
Автор: Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu, TSAI CHEN-YU, WANG SHIH-HUI, CHIU CHIEN-MING, CHEN CHIA-HO, TSAI FANG WEN, WU WENG-JIN, LIN JING-CHENG, CHIOU WEN-CHIH, JENG SHIN-PUU, YU CHEN-HUA, Tsai Chen-Yu, Wang Shih-Hui, Chiu Chien-Ming, Chen Chia-Ho, Tsai Fang Wen, Wu Weng-Jin, Lin Jing-Cheng, Chiou Wen-Chih, Jeng Shin-Puu, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

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Номер записи: 50
19-12-2017 дата публикации

Fan-out packages and methods of forming same

Номер: US0009847269B2
Автор: Jing-Cheng Lin, Jeffrey Chang, Chun-Hsing Su, Tsei-Chung Fu, Yi-Chao Mao, LIN JING-CHENG, CHANG JEFFREY, SU CHUN-HSING, FU TSEI-CHUNG, MAO YI-CHAO, Lin Jing-Cheng, Chang Jeffrey, Su Chun-Hsing, Fu Tsei-Chung, Mao Yi-Chao
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

An embodiment a device package includes a semiconductor die, a molding compound extending along sidewalls of the semiconductor die, and a planarizing polymer layer over the molding compound and extending along the sidewalls of the semiconductor die. The molding compound includes first fillers, and the planarizing polymer layer includes second fillers smaller than the first fillers. The device package further includes one or more fan-out redistribution layers (RDLs) electrically connected to the semiconductor die, wherein the one or more fan-out RDLs extend past edges of the semiconductor die onto a top surface of the planarizing polymer layer.

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Номер записи: 51
23-03-2017 дата публикации

Pillar Design for Conductive Bump

Номер: US20170084571A1
Автор: Cheng-Chieh Hsieh, Cheng-Lin Huang, Po-Hao Tsai, Shang-Yun Hou, Jing-Cheng Lin, Shin-Puu Jeng, HSIEH CHENG-CHIEH, HUANG CHENG-LIN, TSAI PO-HAO, HOU SHANG-YUN, LIN JING-CHENG, JENG SHIN-PUU, Hsieh Cheng-Chieh, Huang Cheng-Lin, Tsai Po-Hao, Hou Shang-Yun, Lin Jing-Cheng, Jeng Shin-Puu
Принадлежит:

A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

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Номер записи: 52
10-04-2018 дата публикации

Protective layer for contact pads in fan-out interconnect structure and method of forming same

Номер: US0009941244B2
Автор: Chin-Chuan Chang, Tsei-Chung Fu, Jing-Cheng Lin, CHANG CHIN-CHUAN, FU TSEI-CHUNG, LIN JING-CHENG, Chang Chin-Chuan, Fu Tsei-Chung, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

In accordance with a method embodiment includes providing a die having a contact pad on a top surface and forming a conductive protective layer over the die and covering the contact pad. A molding compound is formed over the die and the conductive protective layer. The conductive protective layer is exposed using a laser drilling process. A redistribution layer (RDL) is formed over the die. The RDL is electrically connected to the contact pad through the conductive protective layer.

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Номер записи: 53
02-01-2013 дата публикации

Interconnect structure for wafer level package

Номер: CN102856279A
Автор: Yu Chen-Hua, Lin Jing-Cheng, Liu Nai-Wei, Hung Jui-Pin, Jeng Shin-Puu
Принадлежит:

A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI. The invention also provides an interconnect structure for wafer level package.

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Номер записи: 54
04-05-2017 дата публикации

Rework Process and Tool Design for Semiconductor Package

Номер: US20170125374A1
Автор: Shih Ting Lin, Justin Huang, Tsung-Fu Tsai, Jing-Cheng Lin, Chen-Hua Yu, LIN SHIH TING, HUANG JUSTIN, TSAI TSUNG-FU, LIN JING-CHENG, YU CHEN-HUA, Lin Shih Ting, Huang Justin, Tsai Tsung-Fu, Lin Jing-Cheng, Yu Chen-Hua
Принадлежит:

A rework process includes attaching a first bond head to a first semiconductor package. The contact pads of the first semiconductor package are bonded to contact pads of a second semiconductor package by solder joints. The rework process further includes performing a first local heating process to melt the solder joints, removing the first semiconductor package using the first bond head, and removing at least a portion of solder from the contact pads of the second semiconductor package.

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Номер записи: 55
06-10-2016 дата публикации

DIE-ON-INTERPOSER ASSEMBLY WITH DAM STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Номер: US20160293532A1
Автор: Chih-Wei Wu, Szu Wei Lu, Jing-Cheng Lin, WU CHIH-WEI, LU SZU WEI, LIN JING-CHENG, Wu Chih-Wei, Lu Szu Wei, Lin Jing-Cheng
Принадлежит:

A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip.

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Номер записи: 56
26-01-2017 дата публикации

Interconnect Structure for Package-on-Package Devices and a Method of Fabricating

Номер: US20170025397A1
Автор: Jui-Pin Hung, Jing-Cheng Lin, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh, Der-Chyang Yeh, HUNG JUI-PIN, LIN JING-CHENG, TSAI PO-HAO, LIN YI-JOU, CHEN SHUO-MAO, YEH CHIUNG-HAN, YEH DER-CHYANG, Hung Jui-Pin, Lin Jing-Cheng, Tsai Po-Hao, Lin Yi-Jou, Chen Shuo-Mao, Yeh Chiung-Han, Yeh Der-Chyang
Принадлежит:

An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.

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Номер записи: 57
25-10-2016 дата публикации

De-bonding and cleaning process and system

Номер: US0009475272B2
Автор: Ying-Ching Shih, Jing-Cheng Lin, Szu Wei Lu, SHIH YING-CHING, LIN JING-CHENG, LU SZU WEI, Shih Ying-Ching, Lin Jing-Cheng, Lu Szu Wei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

Methods and tools for de-bonding and cleaning substrates are disclosed. A method includes de-bonding a surface of a first substrate from a second substrate, and after de-bonding, cleaning the surface of the first substrate. The cleaning comprises physically contacting a cleaning mechanism to the surface of the first substrate. A tool includes a de-bonding module and a cleaning module. The de-bonding module comprises a first chuck, a radiation source configured to emit radiation toward the first chuck, and a first robot arm having a vacuum system. The vacuum system is configured to secure and remove a substrate from the first chuck. The cleaning module comprises a second chuck, a spray nozzle configured to spray a fluid toward the second chuck, and a second robot arm having a cleaning device configured to physically contact the cleaning device to a substrate on the second chuck.

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Номер записи: 58
27-09-2016 дата публикации

Integrated fan-out structure with openings in buffer layer

Номер: US0009455211B2
Автор: Wu Sen Chiu, Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin, CHIU WU SEN, CHENG LI-HUI, TSAI PO-HAO, LIN JING-CHENG, Chiu Wu Sen, Cheng Li-Hui, Tsai Po-Hao, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A package includes a molding compound, a through-via penetrating through the molding compound, a device die molded in the molding compound, and a buffer layer on and contacting the molding compound. An opening is through the buffer layer to the through-via. The buffer layer has ripples in a plane parallel to an interface between the molding compound and the buffer layer and around a circumference of the opening. Other embodiments contemplate an additional package bonded to the package, and methods for forming the package.

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Номер записи: 59
10-08-2017 дата публикации

Semiconductor Device and Method of Manufacture

Номер: US20170229434A1
Автор: Jing-Cheng Lin, Po-Hao Tsai, Li-Hui Cheng, Porter Chen, LIN JING-CHENG, TSAI PO-HAO, CHENG LI-HUI, CHEN PORTER, Lin Jing-Cheng, Tsai Po-Hao, Cheng Li-Hui, Chen Porter
Принадлежит:

A semiconductor device and method for providing an enhanced removal of heat from a semiconductor die within an integrated fan out package on package configuration is presented. In an embodiment a metal layer is formed on a backside of the semiconductor die, and the semiconductor die along and through vias are encapsulated. Portions of the metal layer are exposed and a thermal die is connected to remove heat from the semiconductor die.

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Номер записи: 60
09-08-2016 дата публикации

Structure and approach to prevent thin wafer crack

Номер: US0009412662B2
Автор: Shih Ting Lin, Jing-Cheng Lin, Szu-Wei Lu, LIN SHIH TING, LIN JING-CHENG, LU SZU-WEI, Lin Shih Ting, Lin Jing-Cheng, Lu Szu-Wei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A semiconductor structure and a method of manufacture are provided. Devices, such as integrated circuit dies, are mounted on a substrate, such as another die, packaging substrate, interposer, or the like, and recesses are formed in the substrate along the scribe lines. One or more molding compound layers are formed in the recesses and between adjacent dies. A backside thinning process may be performed to expose the molding compound in the recesses. A singulation process is performed in the molding compound layer in the recesses. In an embodiment, a first molding compound layer is formed in the recess, and a second molding compound is formed over the first molding compound layer and between adjacent dies. The devices may be placed on the substrate before or after forming the recesses.

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Номер записи: 61
26-01-2017 дата публикации

Fan-out POP Structure with Inconsecutive Polymer Layer

Номер: US20170025359A1
Автор: Yi-Lin Tsai, Jeffrey Chang, Jing-Cheng Lin, Nai-Wei Liu, Tsei-Chung Fu, TSAI YI-LIN, CHANG JEFFREY, LIN JING-CHENG, LIU NAI-WEI, FU TSEI-CHUNG, Tsai Yi-Lin, Chang Jeffrey, Lin Jing-Cheng, Liu Nai-Wei, Fu Tsei-Chung
Принадлежит:

A package includes a device die, a molding material molding at least a portion of the device die therein, and a through-via substantially penetrating through the molding material. The package further includes a dielectric layer contacting the through-via and the molding material, and a die attach film attached to a backside of the device die. The die attach film includes a portion extending in the dielectric layer.

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Номер записи: 62
23-08-2016 дата публикации

Method for forming package systems having interposers

Номер: US0009425067B2
Автор: Yung-Chi Lin, Jing-Cheng Lin, Chen-Hua Yu, LIN YUNG-CHI, LIN JING-CHENG, YU CHEN-HUA, Lin Yung-Chi, Lin Jing-Cheng, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure.

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Номер записи: 63
19-10-2011 дата публикации

TSVs with different sizes in interposers for bonding dies

Номер: CN102222651A
Автор: Tsai Po-Hao, Lin Jing-Cheng, Yu Chen-Hua
Принадлежит:

A device includes an interposer including a substrate having a top surface and a bottom surface. A plurality of through-substrate vias (TSVs) penetrates through the substrate. The plurality of TSVs includes a first TSV having a first length and a first horizontal dimension, and a second TSV having a second length different from the first length, and a second horizontal dimension different from the first horizontal dimension. An interconnect structure is formed overlying the top surface of the substrate and electrically coupled to the plurality of TSVs.

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Номер записи: 64
21-11-2017 дата публикации

Fan-out package and methods of forming thereof

Номер: US0009824989B2
Автор: Wan-Ting Shih, Nai-Wei Liu, Jing-Cheng Lin, Cheng-Lin Huang, SHIH WAN-TING, LIU NAI-WEI, LIN JING-CHENG, HUANG CHENG-LIN, Shih Wan-Ting, Liu Nai-Wei, Lin Jing-Cheng, Huang Cheng-Lin
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

An embodiment is a package including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound and the chip and has a first opening exposing the contact pad. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer fills the first opening. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer and has a second opening over the first opening. A second metallization layer is formed overlying the second dielectric layer and formed in the second opening.

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Номер записи: 65
13-09-2016 дата публикации

Bump structures for multi-chip packaging

Номер: US0009443814B2
Автор: Chen-Hua Yu, Jing-Cheng Lin, YU CHEN-HUA, LIN JING-CHENG, Yu Chen-Hua, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

A multi-chip package includes a substrate having a plurality of first bump structures. A pitch between first bump structures of the plurality of first bump structures is uniform across a surface of the substrate. The multi-chip package includes a first chip bonded to the substrate and a second chip bonded to the substrate. The first chip includes a plurality of second bump structures, and the plurality of second bump structures are bonded to a first set of first bump structures of the plurality of first bump structures. The second chip includes a plurality of third bump structures, and the plurality of third bump structures are bonded to a second set of first bump structures of the plurality of first bump structures. A pitch between second bump structures of the plurality of second bump structures is different from a pitch between third bump structures of the plurality of third bump structures.

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Номер записи: 66
04-12-2013 дата публикации

Wafer-level packaging mechanisms

Номер: CN103426846A
Автор: Lin Jing-Cheng, Hung Jui-Pin
Принадлежит:

The invention relate to wafer-level packaging mechanisms. The embodiments of mechanisms of wafer-level packaging (WLP) described above utilize a planarization stop layer to determine an end-point of the removal of excess molding compound prior to formation of redistribution lines (RDLs). Such mechanisms of WLP are used to implement fan-out and multi-chip packaging. The mechanisms are also usable to manufacture a package including chips (or dies) with different types of external connections. For example, a die with pre-formed bumps can be packaged with a die without pre-formed bumps.

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Номер записи: 67
19-12-2017 дата публикации

TSV formation processes using TSV-last approach

Номер: US0009847255B2
Автор: Jing-Cheng Lin, Yung-Chi Lin, Ku-Feng Yang, LIN JING-CHENG, LIN YUNG-CHI, YANG KU-FENG, Lin Jing-Cheng, Lin Yung-Chi, Yang Ku-Feng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A device includes a semiconductor substrate having a front surface and a back surface opposite the front surface. An insulation region extends from the front surface into the semiconductor substrate. An inter-layer dielectric (ILD) is over the insulation region. A landing pad extends from a top surface of the ILD into the insulation region. A through-substrate via (TSV) extends from the back surface of the semiconductor substrate to the landing pad.

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Номер записи: 68
13-09-2016 дата публикации

3DIC stacking device and method of manufacture

Номер: US0009443783B2
Автор: Jing-Cheng Lin, Chen-Hua Yu, LIN JING-CHENG, YU CHEN-HUA, Lin Jing-Cheng, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., LIN JING-CHENG, YU CHEN-HUA, TAIWAN SEMICONDUCTOR MFG CO LTD, Lin Jing-Cheng, Yu Chen-Hua

A system and method for stacking semiconductor devices in three dimensions is provided. In an embodiment two or more semiconductor dies are attached to a carrier and encapsulated. Connections of the two or more semiconductor dies are exposed, and the two or more semiconductor dies may be thinned to form connections on an opposite side. Additional semiconductor dies may then be placed in either an offset or overhanging position.

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Номер записи: 69
22-08-2017 дата публикации

3-D package having plurality of substrates

Номер: US0009741689B2
Автор: Chin-Chuan Chang, Jing-Cheng Lin, Chen-Hua Yu, CHANG CHIN-CHUAN, LIN JING-CHENG, YU CHEN-HUA, Chang Chin-Chuan, Lin Jing-Cheng, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A package includes an interposer, which includes a first substrate free from through-vias therein, redistribution lines over the first substrate, and a first plurality of connectors over and electrically coupled to the redistribution lines. A first die is over and bonded to the first plurality of connectors. The first die includes a second substrate, and through-vias in the second substrate. A second die is over and bonded to the plurality of connectors. The first die and the second die are electrically coupled to each other through the redistribution lines. A second plurality of connectors is over the first die and the second die. The second plurality of connectors is electrically coupled to the first plurality of connectors through the through-vias in the second substrate.

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Номер записи: 70
05-12-2017 дата публикации

Bump structures for multi-chip packaging

Номер: US0009837370B2
Автор: Chen-Hua Yu, Jing-Cheng Lin, YU CHEN-HUA, LIN JING-CHENG, Yu Chen-Hua, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A multi-chip package includes a substrate having a plurality of first bump structures. A pitch between first bump structures of the plurality of first bump structures is uniform across a surface of the substrate. The multi-chip package includes a first chip bonded to the substrate and a second chip bonded to the substrate. The first chip includes a plurality of second bump structures, and the plurality of second bump structures are bonded to a first set of first bump structures of the plurality of first bump structures. The second chip includes a plurality of third bump structures, and the plurality of third bump structures are bonded to a second set of first bump structures of the plurality of first bump structures. A pitch between second bump structures of the plurality of second bump structures is different from a pitch between third bump structures of the plurality of third bump structures.

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Номер записи: 71
29-09-2016 дата публикации

Package on Package (PoP) Bonding Structures

Номер: US20160284677A1
Автор: Jing-Cheng Lin, Jui-Pin Hung, Po-Hao Tsai, LIN JING-CHENG, HUNG JUI-PIN, TSAI PO-HAO, Lin Jing-Cheng, Hung Jui-Pin, Tsai Po-Hao
Принадлежит:

Various embodiments of mechanisms for forming through package vias (TPVs) with multiple conductive layers and/or recesses in a die package and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. One of the multiple conductive layers acts as a protective layer of the main conductive layer of the TPVs. The protective layer is less likely to oxidize and also has a slower formation rate of intermetallic compound (IMC) when exposed to solder. The recesses in TPVs of a die package are filled by solder from the other die package and the IMC layer formed is below the surface of TPVs, which strengthen the bonding structures.

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Номер записи: 72
09-02-2017 дата публикации

Integrated Fan-Out Package Structures with Recesses in Molding Compound

Номер: US20170040288A1
Автор: Po-Hao Tsai, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin, TSAI PO-HAO, CHENG LI-HUI, HUNG JUI-PIN, LIN JING-CHENG, Tsai Po-Hao, Cheng Li-Hui, Hung Jui-Pin, Lin Jing-Cheng
Принадлежит:

A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

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Номер записи: 73
24-11-2016 дата публикации

Methods of Packaging Semiconductor Devices and Structures Thereof

Номер: US20160343615A1
Автор: Jing-Cheng Lin, Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung, LIN JING-CHENG, HUNG JUI-PIN, LIN YI-HANG, TUNG TSAN-HUA, Lin Jing-Cheng, Hung Jui-Pin, Lin Yi-Hang, Tung Tsan-Hua
Принадлежит:

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

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Номер записи: 74
08-08-2017 дата публикации

Packaged semiconductor devices and packaging devices and methods

Номер: US0009728496B2
Автор: Jing-Cheng Lin, Po-Hao Tsai, LIN JING-CHENG, TSAI PO-HAO, Lin Jing-Cheng, Tsai Po-Hao
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

Packaged semiconductor devices and packaging devices and methods are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a first integrated circuit die that is coupled to a first surface of a substrate that includes through-substrate vias (TSVs) disposed therein. A conductive ball is coupled to each of the TSVs on a second surface of the substrate that is opposite the first surface of the substrate. A second integrated circuit die is coupled to the second surface of the substrate, and a molding compound is formed over the conductive balls, the second integrated circuit die, and the second surface of the substrate. The molding compound is removed from over a top surface of the conductive balls, and the top surface of the conductive balls is recessed. A redistribution layer (RDL) is formed over the top surface of the conductive balls and the molding compound.

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Номер записи: 75
25-04-2017 дата публикации

Integrated fan-out structure with guiding trenches in buffer layer

Номер: US0009633895B2
Автор: Po-Hao Tsai, Feng-Cheng Hsu, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin, TSAI PO-HAO, HSU FENG-CHENG, CHENG LI-HUI, HUNG JUI-PIN, LIN JING-CHENG, Tsai Po-Hao, Hsu Feng-Cheng, Cheng Li-Hui, Hung Jui-Pin, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the buffer layer, wherein the guiding trench is misaligned with the device die.

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Номер записи: 76
22-11-2016 дата публикации

Warpage control for flexible substrates

Номер: US0009502271B2
Автор: Chen-Hua Yu, Shih Ting Lin, Jing-Cheng Lin, Shang-Yun Hou, Szu Wei Lu, YU CHEN-HUA, LIN SHIH TING, LIN JING-CHENG, HOU SHANG-YUN, LU SZU WEI, Yu Chen-Hua, Lin Shih Ting, Lin Jing-Cheng, Hou Shang-Yun, Lu Szu Wei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

Flexible structures and method of providing a flexible structure are disclosed. In some embodiments, a method of providing a flexible structure includes: providing a flex substrate having a device bonded to a first side of the flex substrate; and attaching a rigid layer to a second side of the flex substrate opposite the first side using an adhesive layer.

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Номер записи: 77
22-11-2016 дата публикации

Three dimensional integrated circuits stacking approach

Номер: US0009502380B2
Автор: Jing-Cheng Lin, Shang-Yun Hou, LIN JING-CHENG, HOU SHANG-YUN, Lin Jing-Cheng, Hou Shang-Yun
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer are provided. In some embodiments, the method is performed by placing an interposer with one or more through-substrate-vias (TSVs) on a first adhesive layer overlying a first carrier substrate. Connection structures are arranged along a first surface of the interposer facing the first adhesive layer. A first molding compound is formed over the first adhesive layer and surrounding the interposer. The first molding compound is arranged to expose the TSVs along a second surface of the interposer. A first redistribution structure is formed over the second surface of the interposer and the first molding compound, and conductive bump structures are formed over the first redistribution structure. A first packaged die is bonded to the conductive bump structures.

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Номер записи: 78
18-04-2017 дата публикации

Underfill pattern with gap

Номер: US0009627346B2
Автор: Feng-Cheng Hsu, Hou-Ju Huang, Szu-Wei Lu, Jing-Cheng Lin, HSU FENG-CHENG, HUANG HOU-JU, LU SZU-WEI, LIN JING-CHENG, Hsu Feng-Cheng, Huang Hou-Ju, Lu Szu-Wei, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

An embodiment is a structure comprising a package, a substrate, and external electrical connectors mechanically and electrically coupling the package to the substrate. The package contains a die. The external electrical connectors are between the package and the substrate. An underfill material is around a periphery region of the package and between the periphery region and the substrate. A gap is between a central region of the package and the substrate, and does not contain the underfill material. The underfill material may seal the gap. The gap may be an air gap. In some embodiments, the underfill material may fill greater than or equal to 10 percent and no more than 70 percent of a volume between the package and the substrate.

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Номер записи: 79
27-03-2018 дата публикации

Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure

Номер: US9929050B2
Автор: LIN JING-CHENG, Lin Jing-Cheng
Принадлежит: TAIWAN SEMICONDUCTOR MFG CO LTD, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Taiwan Semiconductor Manufacturing Company, Ltd.

Embodiments of mechanisms of forming a semiconductor device are provided. The semiconductor device includes a first semiconductor wafer comprising a first transistor formed in a front-side of the first semiconductor wafer. The semiconductor device also includes a second semiconductor wafer comprising a second transistor formed in a front-side of the second semiconductor wafer, and a backside of the second semiconductor wafer is bonded to the front-side of the first semiconductor wafer. The semiconductor device further includes an first interconnect structure formed between the first semiconductor wafer and the second semiconductor wafer, and the first interconnect structure comprises a first cap metal layer formed over a first conductive feature. The first interconnect structure is electrically connected to first transistor, and the first cap metal layer is configured to prevent diffusion and cracking of the first conductive feature.

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Номер записи: 80
21-09-2017 дата публикации

Methods of Packaging Semiconductor Devices and Structures Thereof

Номер: US20170271209A1
Автор: Jing-Cheng Lin, Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung, LIN JING-CHENG, HUNG JUI-PIN, LIN YI-HANG, TUNG TSAN-HUA, Lin Jing-Cheng, Hung Jui-Pin, Lin Yi-Hang, Tung Tsan-Hua
Принадлежит:

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

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Номер записи: 81
04-10-2016 дата публикации

Fan-out PoP structure with inconsecutive polymer layer

Номер: US0009461018B1
Автор: Yi-Lin Tsai, Jeffrey Chang, Jing-Cheng Lin, Nai-Wei Liu, Tsei-Chung Fu, TSAI YI-LIN, CHANG JEFFREY, LIN JING-CHENG, LIU NAI-WEI, FU TSEI-CHUNG, Tsai Yi-Lin, Chang Jeffrey, Lin Jing-Cheng, Liu Nai-Wei, Fu Tsei-Chung
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A package includes a device die, a molding material molding at least a portion of the device die therein, and a through-via substantially penetrating through the molding material. The package further includes a dielectric layer contacting the through-via and the molding material, and a die attach film attached to a backside of the device die. The die attach film includes a portion extending in the dielectric layer.

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Номер записи: 82
29-09-2016 дата публикации

Fan Out Package Method

Номер: US20160284653A1
Автор: Feng-Cheng Hsu, Szu-Wei Lu, Jing-Cheng Lin, HSU FENG-CHENG, LU SZU-WEI, LIN JING-CHENG, Hsu Feng-Cheng, Lu Szu-Wei, Lin Jing-Cheng
Принадлежит:

Methods of forming packages include forming an encapsulant laterally encapsulating a die over an active surface of the die. The active surface has an electrical pad. A first opening is formed through the encapsulant to the electrical pad. In some embodiments the first opening is formed using a photolithographic technique. In some embodiments the first opening is formed using a temporary pillar by forming the temporary pillar over the electrical pad, forming the encapsulant, and then exposing and removing the temporary pillar. A conductive pattern is formed over the encapsulant including a via formed in the first opening to the electrical pad of the die's active surface. In some embodiments, a dielectric layer is formed over the encapsulant, and the conductive pattern is over the dielectric layer. Embodiments may include forming additional dielectric layers and conductive patterns.

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Номер записи: 83
01-06-2017 дата публикации

Packaged Semiconductor Devices, Methods of Packaging Semiconductor Devices, and PoP Devices

Номер: US20170154858A1
Автор: Po-Hao Tsai, Jui-Pin Hung, Jing-Cheng Lin, TSAI PO-HAO, HUNG JUI-PIN, LIN JING-CHENG, Tsai Po-Hao, Hung Jui-Pin, Lin Jing-Cheng
Принадлежит:

A packaged semiconductor device includes a substrate and a contact pad disposed on the semiconductor substrate. The packaged semiconductor device also includes a dielectric layer disposed over the contact pad, the dielectric layer including a first opening over the contact pad, and an insulator layer disposed over the dielectric layer, the insulator layer including a second opening over the contact pad. The packaged semiconductor device also includes a molding material disposed around the substrate, the dielectric layer, and the insulator layer and a wiring over the insulator layer and extending through the second opening, the wiring being electrically coupled to the contact pad.

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Номер записи: 84
28-02-2017 дата публикации

Semiconductor device and method of manufactures

Номер: US0009583420B2
Автор: Jing-Cheng Lin, Po-Hao Tsai, Li-Hui Cheng, LIN JING-CHENG, TSAI PO-HAO, CHENG LI-HUI, Lin Jing-Cheng, Tsai Po-Hao, Cheng Li-Hui
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A semiconductor device and method of manufacture is provided. A reflowable material is placed in electrical connection with a through via, wherein the through via extends through an encapsulant. A protective layer is formed over the reflowable material. In an embodiment an opening is formed within the protective layer to expose the reflowable material. In another embodiment the protective layer is formed such that the reflowable material is extending away from the protective layer.

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Номер записи: 85
11-07-2017 дата публикации

Chip packages and methods of manufacture thereof

Номер: US0009704825B2
Автор: Chih-Wei Wu, Jing-Cheng Lin, Szu-Wei Lu, Ying-Ching Shih, WU CHIH-WEI, LIN JING-CHENG, LU SZU-WEI, SHIH YING-CHING, Wu Chih-Wei, Lin Jing-Cheng, Lu Szu-Wei, Shih Ying-Ching
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

Chip packages and method of manufacturing the same are disclosed. In an embodiment, a chip package may include: a redistribution layer (RDL); a first chip including a plurality of first contact pads, the plurality of first contact pads facing the RDL; a second chip disposed between the first chip and the redistribution layer (RDL) wherein a portion of the first chip is disposed outside a lateral extent of the second chip; and a conductive via laterally separated from the second chip, the conductive via extending between the RDL and a first contact pad of the plurality of first contact pads, the first contact pad located in the portion of the first chip disposed outside the lateral extent of the second chip.

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Номер записи: 86
04-08-2016 дата публикации

TSV Formation Processes Using TSV-Last Approach

Номер: US20160225668A1
Автор: Jing-Cheng Lin, Yung-Chi Lin, Ku-Feng Yang, LIN JING-CHENG, LIN YUNG-CHI, YANG KU-FENG, Lin Jing-Cheng, Lin Yung-Chi, Yang Ku-Feng
Принадлежит:

A device includes a semiconductor substrate having a front surface and a back surface opposite the front surface. An insulation region extends from the front surface into the semiconductor substrate. An inter-layer dielectric (ILD) is over the insulation region. A landing pad extends from a top surface of the ILD into the insulation region. A through-substrate via (TSV) extends from the back surface of the semiconductor substrate to the landing pad.

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Номер записи: 87
08-08-2017 дата публикации

Semiconductor device and method of manufacture

Номер: US0009728508B2
Автор: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai, LIN JING-CHENG, YU CHEN-HUA, TSAI PO-HAO, Lin Jing-Cheng, Yu Chen-Hua, Tsai Po-Hao
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A device comprising a semiconductor device, a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.

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Номер записи: 88
05-01-2017 дата публикации

Germanium-Based CMOS Comprising Silicon Cap Formed Over PMOS Region Having A Thickness Less Than That Over NMOS Region

Номер: US20170005010A1
Автор: Jing-Cheng Lin, Chen-Hua Yu, LIN JING-CHENG, YU CHEN-HUA, Lin Jing-Cheng, Yu Chen-Hua
Принадлежит:

A semiconductor structure includes a germanium substrate having a first region and a second region. A first silicon cap is over the first region of the germanium substrate. A second silicon cap is over the second region of the germanium substrate, wherein a first thickness of the first silicon cap is less than a second thickness of the second silicon cap. A PMOS device includes a first gate dielectric over the first silicon cap. An NMOS device includes a second gate dielectric over the second silicon cap. 1. A method comprising:growing a first silicon cap over a germanium-containing substrate, wherein the germanium-containing substrate comprises a first portion and a second portion, and the first silicon cap is over the first portion of the germanium-containing substrate;oxidizing a top portion of the first silicon cap to form a silicon oxide layer;using the silicon oxide layer as a mask to grow a second silicon cap over a second portion of the germanium-containing substrate; andremoving the silicon oxide layer, wherein after the silicon oxide layer is removed, a first thickness of the first silicon cap is greater than a second thickness of the second silicon cap.2. The method of further comprising:forming a first gate dielectric over the first silicon cap;forming n-type source and drain regions on opposite sides of the first gate dielectric;forming a second gate dielectric over the second silicon cap; andforming p-type source and drain regions on opposite sides of the second gate dielectric.3. The method of further comprising:forming a silicon germanium region in the germanium-containing substrate and adjacent to the first gate dielectric, wherein the silicon germanium region has a germanium atomic percentage less than an atomic percentage of the germanium-containing substrate.4. The method of claim 1 , wherein the second silicon cap has a first thickness claim 1 , and wherein before the oxidizing claim 1 , the first silicon cap has a second thickness claim 1 , and ...

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Номер записи: 89
22-06-2017 дата публикации

Semiconductor Device Structure Comprising a Plurality of Metal Oxide Fibers and Method for Forming the Same

Номер: US20170179054A1
Автор: Jing-Cheng Lin, Chen-Hua Yu, Szu-Wei Lu, Yen-Yao Chi, LIN JING-CHENG, YU CHEN-HUA, LU SZU-WEI, CHI YEN-YAO, Lin Jing-Cheng, Yu Chen-Hua, Lu Szu-Wei, Chi Yen-Yao
Принадлежит:

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a conductive structure over the substrate. The semiconductor device structure includes first metal oxide fibers over the conductive structure. The semiconductor device structure includes a dielectric layer over the substrate and covering the conductive structure and the first metal oxide fibers. The dielectric layer fills gaps between the first metal oxide fibers.

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Номер записи: 90
09-02-2017 дата публикации

De-bonding and Cleaning Process and System

Номер: US20170036433A1
Автор: Ying-Ching Shih, Jing-Cheng Lin, Szu-Wei Lu, SHIH YING-CHING, LIN JING-CHENG, LU SZU-WEI, Shih Ying-Ching, Lin Jing-Cheng, Lu Szu-Wei
Принадлежит:

Methods and tools for de-bonding and cleaning substrates are disclosed. A method includes de-bonding a surface of a first substrate from a second substrate, and after de-bonding, cleaning the surface of the first substrate. The cleaning comprises physically contacting a cleaning mechanism to the surface of the first substrate. A tool includes a de-bonding module and a cleaning module. The de-bonding module comprises a first chuck, a radiation source configured to emit radiation toward the first chuck, and a first robot arm having a vacuum system. The vacuum system is configured to secure and remove a substrate from the first chuck. The cleaning module comprises a second chuck, a spray nozzle configured to spray a fluid toward the second chuck, and a second robot arm having a cleaning device configured to physically contact the cleaning device to a substrate on the second chuck.

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Номер записи: 91
28-11-2017 дата публикации

Solution for reducing poor contact in info packages

Номер: US0009831224B2
Автор: Jing-Cheng Lin, Chen-Hua Yu, Szu-Wei Lu, Shih Ting Lin, Shin-Puu Jeng, LIN JING-CHENG, YU CHEN-HUA, LU SZU-WEI, LIN SHIH TING, JENG SHIN-PUU, Lin Jing-Cheng, Yu Chen-Hua, Lu Szu-Wei, Lin Shih Ting, Jeng Shin-Puu
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A package includes a first package including a device die, a molding compound molding the device die therein, a through-via penetrating through the molding compound, and a first plurality of Redistribution Lines (RDLs) and a second plurality of RDLs on opposite sides of the molding compound. The through-via electrically couples one of the first plurality of RDLs to one of the second plurality of RDLs. The package further includes a second package bonded to the first package, a spacer disposed in a gap between the first package and the second package, and a first electrical connector and a second electrical connector on opposite sides of the spacer. The first electrical connector and the second electrically couple the first package to the second package. The spacer is spaced apart from the first electrical connector and the second electrical connector.

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Номер записи: 92
03-11-2016 дата публикации

Fan-Out Wafer Level Package Structure

Номер: US20160322288A1
Автор: Jing-Cheng Lin, LIN JING-CHENG, Lin Jing-Cheng
Принадлежит:

A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips 104 may be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad.

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Номер записи: 93
21-09-2017 дата публикации

Package on Package (PoP) Bonding Structures

Номер: US20170271311A1
Автор: Jing-Cheng Lin, Jui-Pin Hung, Po-Hao Tsai, LIN JING-CHENG, HUNG JUI-PIN, TSAI PO-HAO, Lin Jing-Cheng, Hung Jui-Pin, Tsai Po-Hao
Принадлежит:

Various embodiments of mechanisms for forming through package vias (TPVs) with multiple conductive layers and/or recesses in a die package and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. One of the multiple conductive layers acts as a protective layer of the main conductive layer of the TPVs. The protective layer is less likely to oxidize and also has a slower formation rate of intermetallic compound (IMC) when exposed to solder. The recesses in TPVs of a die package are filled by solder from the other die package and the IMC layer formed is below the surface of TPVs, which strengthen the bonding structures.

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Номер записи: 94
28-09-2017 дата публикации

Molding Wafer Chamber

Номер: US20170278723A1
Автор: Jing-Cheng Lin, Chin-Chuan Chang, Jui-Pin Hung, Szu-Wei Lu, Shin-Puu Jeng, Chen-Hua Yu, LIN JING-CHENG, CHANG CHIN-CHUAN, HUNG JUI-PIN, LU SZU-WEI, JENG SHIN-PUU, YU CHEN-HUA, Lin Jing-Cheng, Chang Chin-Chuan, Hung Jui-Pin, Lu Szu-Wei, Jeng Shin-Puu, Yu Chen-Hua
Принадлежит:

A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired location defined by a guiding component. The guiding component may be entirely within the cavity, or extend above a surface of the bottom chase and extend over a contacting edge of the top chase and the bottom chase, so that there is a gap between the edge of the top chase and the edge of the molding carrier which are filled by molding materials to cover the edge of the molding carrier. Releasing components may be associated with the top chase and/or the bottom chase, which may be a plurality of tape roller with a releasing film, or a plurality of vacuum holes within the bottom chase, or a plurality of bottom pins with the bottom chase.

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Номер записи: 95
11-10-2016 дата публикации

Semiconductor package device and manufacturing method thereof

Номер: US0009466581B2
Автор: Nai-Wei Liu, Jui-Pin Hung, Jing-Cheng Lin, LIU NAI-WEI, HUNG JUI-PIN, LIN JING-CHENG, Liu Nai-Wei, Hung Jui-Pin, Lin Jing-Cheng
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., TAIWAN SEMICONDUCTOR MFG CO LTD

A semiconductor device includes a die, a pad disposed on the die and configured to be electrically coupled with a bump through a conductive trace attached on the pad, a polymer disposed over the die and patterned to provide a path for the conductive trace passing through, and a molding surrounding the die and the polymer. A top surface of the molding is substantially in a same level as a top surface of the polymer. Further, a method of manufacturing a semiconductor device includes providing a die, forming a pad on the die, disposing a first polymer over the die, patterning the first polymer with an opening over the pad, disposing a sacrificial layer over the patterned first polymer, disposing a molding surrounding the die, removing a portion of the molding thereby exposing the sacrificial layer, removing the sacrificial layer thereby exposing the pad and the first polymer, disposing a second polymer on the first polymer, patterning the second polymer with the opening over the pad, and disposing ...

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Номер записи: 96
28-11-2017 дата публикации

Front-to-back bonding with through-substrate via (TSV)

Номер: US0009831156B2
Автор: Jing-Cheng Lin, LIN JING-CHENG, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Methods for forming a semiconductor device structure are provided. The method includes providing a first semiconductor wafer and a second semiconductor wafer. A first transistor is formed in a front-side of the first semiconductor wafer, and no devices are formed in the second semiconductor wafer. The method further includes bonding the front-side of the first semiconductor wafer to a backside of the second semiconductor wafer and thinning a front-side of the second semiconductor wafer. After thinning the second semiconductor wafer, a second transistor is formed in the front-side of the second semiconductor wafer. At least one first through substrate via (TSV) is formed in the second semiconductor wafer, and the first TSV directly contacts a conductive feature of the first semiconductor wafer.

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Номер записи: 97
30-05-2017 дата публикации

Method for manufacturing germanium-based CMOS comprising forming silicon cap over PMOS region having a thickness less than that over NMOS region

Номер: US0009666487B2
Автор: Jing-Cheng Lin, Chen-Hua Yu, LIN JING-CHENG, YU CHEN-HUA, Lin Jing-Cheng, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A semiconductor structure includes a germanium substrate having a first region and a second region. A first silicon cap is over the first region of the germanium substrate. A second silicon cap is over the second region of the germanium substrate, wherein a first thickness of the first silicon cap is less than a second thickness of the second silicon cap. A PMOS device includes a first gate dielectric over the first silicon cap. An NMOS device includes a second gate dielectric over the second silicon cap.

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Номер записи: 98
10-11-2016 дата публикации

Integrated Fan-Out Structure with Guiding Trenches in Buffer Layer

Номер: US20160329307A1
Автор: Po-Hao Tsai, Feng-Cheng Hsu, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin, TSAI PO-HAO, HSU FENG-CHENG, CHENG LI-HUI, HUNG JUI-PIN, LIN JING-CHENG, Tsai Po-Hao, Hsu Feng-Cheng, Cheng Li-Hui, Hung Jui-Pin, Lin Jing-Cheng
Принадлежит:

A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the buffer layer, wherein the guiding trench is misaligned with the device die.

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Номер записи: 99
24-10-2017 дата публикации

Integrated fan-out structure with openings in buffer layer

Номер: US0009799581B2
Автор: Wu Sen Chiu, Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin, CHIU WU SEN, CHENG LI-HUI, TSAI PO-HAO, LIN JING-CHENG, Chiu Wu Sen, Cheng Li-Hui, Tsai Po-Hao, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A package includes a molding compound, a through-via penetrating through the molding compound, a device die molded in the molding compound, and a buffer layer on and contacting the molding compound. An opening is through the buffer layer to the through-via. The buffer layer has ripples in a plane parallel to an interface between the molding compound and the buffer layer and around a circumference of the opening. Other embodiments contemplate an additional package bonded to the package, and methods for forming the package.

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Номер записи: 100
05-01-2012 дата публикации

Alignment Mark and Method of Formation

Номер: US20120001337A1
Автор: Chen Chia-Ho, Chiou Wen-Chih, Chiu Chien-Ming, Jeng Shin-Puu, Lin Jing-Cheng, Tsai Chen-Yu, Tsai Fang Wen, Wang Shih-Hui, Wu Weng-Jin, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess. 1. A structure comprising:a substrate having a first area and a second area;a through substrate via (TSV) in the substrate penetrating the first area of the substrate;an isolation layer over the second area of the substrate, the isolation layer having a recess; anda conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.2. The structure of claim 1 , wherein the recess extends into substrate.3. The structure of claim 1 , wherein the recess does not extend into the substrate.4. The structure of claim 1 , wherein the isolation layer comprises a first sublayer and a second sublayer over the first sublayer claim 1 , the first sublayer having a different composition from the second sublayer.5. The structure of claim 4 , wherein the recess extends only through the second sublayer.6. The structure of claim 4 , wherein the first sublayer comprises silicon nitride.7. The structure of claim 1 , wherein the TSV extends to protrude from the substrate.8. A structure having an alignment mark claim 1 , the structure comprising:a substrate comprising a through substrate via (TSV), the TSV extending from a front surface of the substrate to a back surface of the substrate;an isolation layer over the back surface of the substrate, the isolation layer having a cavity; anda conductor positioned in the cavity, the isolation layer being disposed between the conductor and the substrate in the cavity.9. The structure of claim 8 , wherein the ...

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Номер записи: 101
26-01-2012 дата публикации

Controlling Defects in Thin Wafer Handling

Номер: US20120021604A1
Автор: Lin Jing-Cheng, LIN Yu-Liang, Wu Weng-Jin
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method includes bonding a wafer on a carrier through an adhesive, and performing a thinning process on the wafer. After the step of performing the thinning process, a portion of the adhesive not covered by the wafer is removed, while the portion of the adhesive covered by the wafer is not removed. 1. A method comprising:bonding a wafer on a carrier through an adhesive;performing a thinning process on the wafer; andafter the step of performing the thinning process, removing a portion of the adhesive not covered by the wafer, wherein a portion of the adhesive covered by the wafer is not removed.2. The method of claim 1 , wherein the step of removing the portion of the adhesive comprising spraying a chemical to the portion of the adhesive not covered by the wafer claim 1 , and wherein the chemical is configured to dissolve the adhesive.3. The method of further comprising claim 2 , at a time the step of spraying the chemical is performed claim 2 , simultaneously rotating the wafer claim 2 , wherein a nozzle for spraying the chemical is at a fixed position.4. The method of claim 2 , wherein the chemical is selected from the group consisting essentially of a solvent claim 2 , alcohol claim 2 , a thinner claim 2 , and combinations thereof.5. The method of further comprising claim 1 , after the step of removing the portion of the adhesive claim 1 , performing a process step to the wafer claim 1 , with plasma used in the process step claim 1 , wherein the wafer is bonded to the carrier through the adhesive during the process step claim 1 , and wherein the process step is selected from the group consisting essentially of a deposition and a dry etch.6. The method of claim 1 , wherein at a time the step of removing the portion of the adhesive is started claim 1 , the adhesive comprises a surface level with a surface of the wafer claim 1 , and wherein after the step of removing the portion of the adhesive claim 1 , the surface of the adhesive is at least reduced in size.7. The ...

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Номер записи: 102
02-02-2012 дата публикации

SUBSTRATE BONDING SYSTEM AND METHOD OF MODIFYING THE SAME

Номер: US20120024456A1
Автор: Lin Jing-Cheng, LIN Yu-Liang, Wu Weng-Jin
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

The embodiments described provide apparatus and methods for bonding wafers to carriers with the surface contours of plates facing the substrates or carriers are modified either by re-shaping, by using height adjusters, by adding shim(s), or by zoned temperature control. The modified surface contours of such plates compensate the effects that may cause the non-planarity of bonded substrates. 1. A substrate bonding system , comprising: an upper body with upper heating elements; and', 'an upper plate; and, 'an upper assembly, wherein the upper assembly includes'} a lower plate facing the upper plate, wherein the lower plate support a substrate during a bonding process;', 'a lower body with lower heating elements; and', 'a support structure for the lower body, wherein at least one shim is placed between support structure and a lower plate to improve planarity of a surface of the substrate after the substrate is bonded to a carrier., 'a lower assembly, wherein the lower assembly includes'}2. The substrate bonding system of claim 1 , wherein the shim is place at the center region below the substrate.3. The substrate bonding system of claim 1 , wherein a thickness of a thickest region of the shim is between about 10 μm to about 20 μm.4. The substrate bonding system of claim 1 , wherein the shim has a diameter between about 10 mm to about 25 mm.5. A substrate bonding system claim 1 , comprising: an upper body with upper heating elements; and', 'an upper plate; and, 'an upper assembly, wherein the upper assembly includes'} a lower plate facing the upper plate, wherein a substrate to be bonded is placed on the lower plate during the bonding process;', 'a lower body with lower heating elements;', 'a support structure for the lower body; and', 'a plurality of height adjusters under the support structure, wherein the heights of the plurality adjusters can be adjusted to improve planarity of a surface of the substrate after the substrate is bonded to a carrier., 'a lower assembly ...

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Номер записи: 103
02-02-2012 дата публикации

Semiconductor Device Cover Mark

Номер: US20120025368A1
Автор: Chiou Wen-Chih, Jeng Shin-Puu, Lin Jing-Cheng, Lin Yan-Fu, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A system and method for determining underfill expansion is provided. An embodiment comprises forming cover marks along a top surface of a substrate, attaching a semiconductor substrate to the top surface of the substrate, placing an underfill material between the semiconductor substrate and the substrate, and then using the cover marks to determine the expansion of the underfill over the top surface of the substrate. Additionally, cover marks may also be formed along a top surface of the semiconductor substrate, and the cover marks on both the substrate and the semiconductor substrate may be used together as alignment marks during the alignment of the substrate and the semiconductor substrate. 1. A device comprising:a substrate having a first surface, the substrate comprising a region of attachment, the region of attachment having one or more contact pads; andone or more cover marks along the first surface, the one or more cover marks comprising an indication of distance away from the region of attachment.2. The semiconductor device of claim 1 , further comprising:a semiconductor substrate comprising one or more contact bumps, the contact bumps in contact with the contact pads; andan underfill material between the semiconductor substrate and the substrate, the underfill material extending over at least a portion of the one or more cover marks.3. The semiconductor device of claim 2 , further comprising one or more semiconductor substrate cover marks located on the semiconductor substrate claim 2 , the one or more semiconductor substrate cover marks being aligned with respective ones of the one or more cover marks.4. The semiconductor device of claim 1 , wherein the one or more cover marks further comprise:a straight line extending perpendicularly away from a side of the region of attachment; andhash marks extending away from the straight line parallel with the side of the region of attachment.5. The semiconductor device of claim 1 , wherein the one or more cover ...

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Номер записи: 104
02-02-2012 дата публикации

Embedded Wafer-Level Bonding Approaches

Номер: US20120028411A1
Автор: Lin Jing-Cheng, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method includes providing a carrier with an adhesive layer disposed thereon; and providing a die including a first surface, a second surface opposite the first surface. The die further includes a plurality of bond pads adjacent the second surface; and a dielectric layer over the plurality of bond pads. The method further includes placing the die on the adhesive layer with the first surface facing toward the adhesive layer and dielectric layer facing away from the adhesive layer; forming a molding compound to cover the die, wherein the molding compound surrounds the die; removing a portion of the molding compound directly over the die to expose the dielectric layer; and forming a redistribution line above the molding compound and electrically coupled to one of the plurality of bond pads through the dielectric layer. 1. A method comprising:providing a carrier with an adhesive layer disposed thereon;providing a die comprising a substrate, a plurality of bond pads over the substrate, and a dielectric layer over the plurality of bond pads;placing the die on the adhesive layer;forming a molding compound to cover the die, wherein the molding compound surrounds the die;removing a portion of the molding compound directly over the die to expose the dielectric layer; andforming a redistribution line above the dielectric layer and electrically coupled to at least one of the plurality of bond pads.2. The method of claim 1 , wherein before the step of placing the die on the adhesive layer claim 1 , the die further comprises metal pillars formed in the dielectric layer and electrically coupled to the plurality of bond pads.3. The method of claim 2 , wherein during the step of forming the redistribution line claim 2 , the metal pillars are used as alignment marks.4. The method of further comprising claim 1 , after the step of removing the portion of the molding compound claim 1 , forming metal pillars penetrating through the dielectric layer and electrically coupled to the ...

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Номер записи: 105
16-02-2012 дата публикации

Semiconductor Molding Chamber

Номер: US20120040500A1
Автор: Chiou Wen-Chih, Jeng Shin-Puu, Lin Jing-Cheng, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A system and method for a semiconductor molding chamber is disclosed. An embodiment comprises a top molding portion and a bottom molding portion that form a cavity between them into which a semiconductor wafer is placed. The semiconductor molding chamber has a first set of vacuum tubes which hold and fix the position of the semiconductor wafer and a second set of vacuum tubes which evacuate the cavity of extraneous ambient gasses. The encapsulant may then be placed over the semiconductor wafer in order to encapsulate the semiconductor wafer. 1. A system for encapsulating a semiconductor device comprising:a molding chamber comprising a first variable pressure region, a second variable pressure region, and a semiconductor wafer receiving region located between the first variable pressure region and the second variable pressure region;at least one first vacuum hole extending through the molding chamber, the at least one first vacuum hole opening to the first variable pressure region; andat least one second vacuum hole extending through the molding chamber and located opposite the semiconductor wafer receiving region from the second variable pressure region and operably connected to the second variable pressure region.2. The system of claim 1 , wherein the molding chamber further comprises:a top molding portion with a first cavity; anda bottom molding portion with a second cavity, the bottom molding portion being separable from the top molding portion, the first cavity being aligned with the second cavity to form the molding chamber.3. The system of claim 2 , further comprising a release material located along sidewalls of the second cavity.4. The system of claim 3 , wherein the release material comprises gold claim 3 , Cr—N or Teflon.5. The system of claim 2 , wherein the at least one first vacuum hole and the at least one second vacuum hole both extend through the bottom molding portion.6. The system of claim 5 , further comprising a vacuum separator located on the ...

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Номер записи: 106
23-02-2012 дата публикации

Composite Carrier Structure

Номер: US20120045611A1
Автор: Chiou Wen-Chih, Jeng Shin-Puu, Lin Jing-Cheng, Shih Ying-Ching, Wu Weng-Jin, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A composite carrier structure for manufacturing semiconductor devices is provided. The composite carrier structure utilizes multiple carrier substrates, e.g., glass or silicon substrates, coupled together by interposed adhesive layers. The composite carrier structure may be attached to a wafer or a die for, e.g., backside processing, such as thinning processes. In an embodiment, the composite carrier structure comprises a first carrier substrate having through-substrate vias formed therethrough. The first substrate is attached to a second substrate using an adhesive such that the adhesive may extend into the through-substrate vias. 1. A carrier structure comprising:a first carrier substrate; anda second carrier substrate attached to the first carrier substrate.2. The carrier structure of claim 1 , wherein the first carrier substrate has a recess formed therein claim 1 , wherein the second carrier substrate is placed over the recess.3. The carrier structure of claim 1 , wherein at least one of the first carrier substrate and the second carrier substrate comprises through-substrate vias.4. The carrier structure of claim 1 , wherein at least one of the first carrier substrate and the second carrier substrate comprises a glass substrate.5. The carrier structure of claim 1 , wherein at least one of the first carrier substrate and the second carrier substrate comprises a silicon wafer.6. A carrier structure comprising:a plurality of carrier substrates; andat least one adhesive layer interposed between adjacent ones of the plurality of carrier substrates.7. The carrier structure of claim 6 , wherein the plurality of carrier substrates comprises a first carrier substrate claim 6 , the first carrier substrate having a recess formed therein.8. The carrier structure of claim 7 , wherein the recess is filled with an adhesive.9. The carrier structure of claim 7 , wherein the recess has a depth from about 20 μm to about 300 μm.10. The carrier structure of claim 6 , wherein at ...

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Номер записи: 107
08-03-2012 дата публикации

Alignment Marks in Substrate Having Through-Substrate Via (TSV)

Номер: US20120056315A1
Автор: Chang Hsin, Chiou Wen-Chih, Jeng Shin-Puu, Lin Jing-Cheng, Tsai Fang Wen
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate. 1. A device comprising:a substrate; anda first alignment mark comprising a first conductive through-substrate via (TSV) penetrating through the substrate.2. The device of claim 1 , wherein the first alignment mark comprises a plurality of first conductive TSVs penetrating through the substrate.3. The device of claim 2 , wherein the plurality of first conductive TSVs are arranged in a rectangular region.4. The device of claim 2 , wherein the plurality of first conductive TSVs are aligned into two lines crossing each other.5. The device of claim 1 , further comprising a conductive feature over a backside of the substrate claim 1 , wherein the conductive feature is not electrically coupled to the first conductive TSV.6. The device of claim 1 , wherein the first conductive TSV is electrically floating.7. The device of claim 1 , further comprising a dielectric layer on a backside of the substrate claim 1 , and wherein the first conductive TSV penetrates through the dielectric layer.8. The device of claim 1 , wherein the substrate is a semiconductor substrate claim 1 , and wherein no active device is formed at opposite surfaces of the semiconductor substrate.9. The device of claim 1 , wherein the substrate is a semiconductor substrate claim 1 , and wherein an active device is formed on a front side of the semiconductor substrate.10. The device of claim 1 , further comprising a second alignment mark on a front side of the substrate claim 1 , wherein the second alignment mark includes a metal layer.11. The device of claim 1 , further comprising a second conductive TSV penetrating through the substrate and not electrically floating.12. The device of claim 11 , wherein the first conductive TSV and the second conductive TSV have substantially a same diameter.13. The device of claim 11 , wherein the first conductive TSV and the second ...

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Номер записи: 108
20-09-2012 дата публикации

Approach for Bonding Dies onto Interposers

Номер: US20120238057A1
Автор: Chiou Wen-Chih, Hou Shang-Yun, Hu Hsien-Pin, Jeng Shin-Puu, Lin Jing-Cheng, TU Hung-Jung, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs. 1. A method comprising: a substrate; and', 'a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate;, 'bonding a plurality of dies onto a front surface of an interposer wafer, wherein the interposer wafer comprisesafter the step of bonding the plurality of dies, filling a molding compound into gaps between the plurality of dies;grinding the molding compound and a top surface of the plurality of dies;after the step of grinding on the molding compound, performing a grinding on a backside of the substrate to expose the plurality of TSVs; andforming a plurality of metal bumps on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.2. The method of further comprising bonding a carrier over the plurality of dies before grinding the backside of the substrate.3. The method of further comprising:after the step of performing the grinding on the molding compound, applying an adhesive to top surfaces of the plurality of dies; andmounting a carrier over the top surfaces of the plurality of dies through the adhesive.4. The method of further comprising mounting a carrier over the plurality of dies and the molding compound through an adhesive before performing the grinding on the backside of the substrate.5. The method of further comprising:after the step of bonding the plurality of dies, filling an adhesive into gaps between the plurality of dies; andmounting a carrier over top ...

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Номер записи: 109
06-12-2012 дата публикации

Packaging Structures and Methods

Номер: US20120306080A1
Автор: Hou Shang-Yun, Hsieh Cheng-Chieh, HSU Kuo-Ching, Huang Cheng-Lin, Jeng Shin-Puu, Lin Jing-Cheng, Shih Ying-Ching, Tsai Po-Hao, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier. 1. A device comprising: a substrate;', 'a through-via in the substrate;', 'a top dielectric layer over the substrate;', 'a first metal pillar having a top surface over a top surface of the top dielectric layer, wherein the first metal pillar is electrically coupled to the through-via;', 'a first diffusion barrier over the top surface of the first metal pillar; and', 'a solder cap over the first diffusion barrier., 'a first package component, wherein the first package component comprises2. The device of claim 1 , wherein the first package component is free from at least one of an active device and a passive device therein.3. The device of claim 1 , wherein a thickness of the first diffusion barrier is greater than about 2 μm.4. The device of further comprising a protection layer extending on sidewalls of the first metal pillar.5. The device of claim 1 , wherein the first diffusion barrier does not extend on sidewalls of the first metal pillar.6. The device of further comprising: a second metal pillar at a top surface of the second package component; and', 'a second diffusion barrier on a top surface of the first metal pillar and electrically coupled to, and bonded to, the solder cap., 'a second package component comprising7. The device of claim 1 , wherein the first diffusion barrier comprises nickel.8. A device comprising: a substrate;', 'a through-via in the substrate;', 'a top dielectric layer over the substrate;', 'a first metal pillar having a top surface over a top surface of the top dielectric layer; and', 'a first diffusion ...

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Номер записи: 110
24-01-2013 дата публикации

Pillar Design for Conductive Bump

Номер: US20130020698A1
Автор: Hou Shang-Yun, Hsieh Cheng-Chieh, Huang Cheng-Lin, Jeng Shin-Puu, Lin Jing-Cheng, Tsai Po-Hao
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material. 1. A semiconductor device comprising:a first substrate; anda conductive post extending away from the first substrate, the conductive post comprising one or more trenches perpendicular to the first substrate.2. The semiconductor device of claim 1 , further comprising a conductive material located within the one or more trenches.3. The semiconductor device of claim 2 , wherein the conductive material is solder.4. The semiconductor device of claim 2 , further comprising:a second substrate located over the first substrate; anda conductive region located on the second substrate, wherein the conductive region is in contact with the conductive material.5. The semiconductor device of claim 2 , wherein the conductive material extends beyond a diameter of the conductive post.6. The semiconductor device of claim 2 , wherein the conductive material fills only part of the one or more trenches.7. The semiconductor device of claim 1 , wherein the conductive post comprises copper.8. The semiconductor device of claim 1 , wherein the one or more trenches comprise at least two or more trenches arranged symmetrically around the conductive post.9. A semiconductor device comprising:a passivation layer located over a substrate;a conductive post extending through the passivation layer, the conductive post having an outer circumference;a plurality of grooves located around the outer circumference of the conductive post; anda conductive material located over the conductive post.10. The semiconductor device of claim 9 , wherein the conductive material is solder.11. The semiconductor device of claim 9 , wherein the ...

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Номер записи: 111
31-01-2013 дата публикации

SELF-ALIGNING CONDUCTIVE BUMP STRUCTURE AND METHOD OF MAKING THE SAME

Номер: US20130026620A1
Автор: Chen I-Ting, Huang Cheng-Lin, Jeng Shin-Puu, Lin Jing-Cheng, Lu Szu Wei, SHIH YING CHING, Tsai Po-Hao, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

The disclosure relates to a conductive bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface and conductive bumps distributed over the major surface of the substrate. Each of a first subset of the conductive bumps comprise a regular body, and each of a second subset of the conductive bumps comprise a ring-shaped body. 1. A semiconductor device comprising:a substrate comprising a major surface; andconductive bumps distributed over the major surface of the substrate, wherein each of a first subset of the conductive bumps comprise a regular body and each of a second subset of the conductive bumps comprise a ring-shaped body.2. The semiconductor device of claim 1 , wherein the regular body has a first thickness and the ring-shaped body has a second thickness greater than the first thickness.3. The semiconductor device of claim 1 , wherein the ring-shaped body comprises substantially vertical sidewalls.4. The semiconductor device of claim 1 , wherein the ring-shaped body comprises tapered sidewalls.5. The semiconductor device of claim 1 , wherein a top-down view of the ring-shaped body comprises a shape selected from circle claim 1 , square claim 1 , and rectangular6. The semiconductor device of claim 1 , wherein the conductive bumps is a heat re-flowable material.7. The semiconductor device of claim 1 , wherein the conductive bumps comprise Sn claim 1 , SnAg claim 1 , Sn—Pb claim 1 , SnAgCu claim 1 , SnAgZn claim 1 , SnZn claim 1 , SnBi—In claim 1 , Sn—In claim 1 , Sn—Au claim 1 , SnPb claim 1 , SnCu claim 1 , SnZnIn claim 1 , or SnAgSb.8. The semiconductor device of claim 1 , wherein the conductive bumps is a non-flowable material.9. The semiconductor device of claim 1 , wherein the conductive bumps comprise Cu claim 1 , Ag claim 1 , Au claim 1 , Cu alloy claim 1 , Ag alloy claim 1 , or Au alloy.10. A semiconductor device comprising:a substrate comprising a major surface; ...

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Номер записи: 112
14-02-2013 дата публикации

Molding Wafer Chamber

Номер: US20130037990A1
Автор: Chang Chin-Chuan, Hung Jui-Pin, Jeng Shin-Puu, Lin Jing-Cheng, Lu Szu Wei, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired location defined by a guiding component. The guiding component may be entirely within the cavity, or extend above a surface of the bottom chase and extend over a contacting edge of the top chase and the bottom chase, so that there is a gap between the edge of the top chase and the edge of the molding carrier which are filled by molding materials to cover the edge of the molding carrier. Releasing components may be associated with the top chase and/or the bottom chase, which may be a plurality of tape roller with a releasing film, or a plurality of vacuum holes within the bottom chase, or a plurality of bottom pins with the bottom chase. 1. A molding system comprising:a bottom chase with a first shape;a top chase with a second shape, wherein when the first shape and the second shape together form a cavity to house a molding carrier and a plurality of devices; anda guiding component mounted in the bottom chase, the guiding component positioned to hold the molding carrier in a predetermined location, wherein the guiding component extends above a surface of the bottom chase and extends over a contacting edge between the top chase and the bottom chase.2. The molding system of claim 1 , wherein the guiding component is in a fixed position that is within the cavity formed by the top chase and the bottom chase.3. The molding system of claim 1 , wherein the guiding component comprises a guide ring within the bottom chase.4. The molding system of claim 1 , wherein the guiding component comprises a plurality of guide pins that are movable up and down.5. The molding system of claim 1 , further comprising a trench within the bottom chase placed outside the guiding component.6. The molding system of claim 1 , further comprising a releasing component comprising a plurality of tape rollers adjacent to the top chase claim 1 , ...

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Номер записи: 113
28-02-2013 дата публикации

Three-Dimensional Integrated Circuit (3DIC) Formation Process

Номер: US20130049195A1
Автор: Jeng Shin-Puu, Lin Jing-Cheng, Lu Szu Wei, Wu Chih-Wei, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method includes performing a laser grooving to remove a dielectric material in a wafer to form a trench, wherein the trench extends from a top surface of the wafer to stop at an intermediate level between the top surface and a bottom surface of the wafer. The trench is in a scribe line between two neighboring chips in the wafer. A polymer is filled into the trench and then cured. After the step of curing the polymer, a die saw is performed to separate the two neighboring chips, wherein a kerf line of the die saw cuts through a portion of the polymer filled in the trench. 1. A method comprising:performing a laser grooving to remove a low-k dielectric material in a wafer to form a trench, wherein the trench extends from a top surface of the wafer to stop at an intermediate level between the top surface and a bottom surface of the wafer, and wherein the trench is in a scribe line between two neighboring chips in the wafer;filling a polymer into the trench;curing the polymer; andafter the step of curing the polymer, performing a die saw to separate the two neighboring chips, wherein a kerf line of the die saw cuts through a portion of the polymer filled in the trench and wherein a portion of the polymer at a bottom end of the trench is embedded within a semiconductor substrate of the wafer after the die saw.2. The method of claim 1 , wherein after the step of performing the laser grooving claim 1 , a semiconductor substrate of the wafer is exposed through the trench.3. The method of claim 1 , wherein the trench has a first width claim 1 , and wherein the kerf line has a second width smaller than the first width.4. The method of claim 1 , wherein after the two neighboring chips are separated by the step of die saw claim 1 , each of the two neighboring chips comprises a remaining portion of the polymer that is filled in the trench claim 1 , and wherein an edge of the low-k dielectric material in the each of the two neighboring chips is covered by the remaining portion ...

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Номер записи: 114
28-02-2013 дата публикации

Die-to-Die Gap Control for Semiconductor Structure and Method

Номер: US20130049216A1
Автор: Jeng Shin-Puu, Kuo Li-Chung, Lee Long Hua, Lin Jing-Cheng, Lu Szu Wei, Shih Ying-Ching, Wang Ying-Da, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface and a second surface opposite the first surface. The substrate has a through substrate via extending from the first surface towards the second surface. The first die is attached to the substrate, and the first die is coupled to the first surface of the substrate. The second die is attached to the substrate, and the second die is coupled to the first surface of the substrate. A first distance is between a first edge of the first die and a first edge of the second die, and the first distance is in a direction parallel to the first surface of the substrate. The first distance is equal to or less than 200 micrometers. 1. A structure comprising:a substrate having a first surface and a second surface opposite the first surface, the substrate having a through substrate via extending from the first surface towards the second surface;a first die attached to the substrate, the first die being coupled to the first surface of the substrate; anda second die attached to the substrate, the second die being coupled to the first surface of the substrate, a first distance being between a first edge of the first die and a first edge of the second die, the first distance being in a direction parallel to the first surface of the substrate, the first distance being equal to or less than 200 micrometers.2. The structure of further comprising a third die attached to the substrate claim 1 , the third die being coupled to the first surface of the substrate claim 1 , a second distance being between a second edge of the second die and a first edge of the third die claim 1 , the second distance being in a direction parallel to the first surface of the substrate claim 1 , a sum of the first distance and the second distance being equal to or less than 250 micrometers.3. The structure of claim 2 , wherein each of the first distance and the second distance is equal to or less than ...

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Номер записи: 115
28-02-2013 дата публикации

Substrate Dicing

Номер: US20130049234A1
Автор: Chen-Hua Yu, Chih-Wei Wu, Jing-Cheng Lin, Shin-puu Jeng, Szu Wei Lu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method and apparatus for separating a substrate into individual dies and the resulting structure is provided. A modification layer, such as an amorphous layer, is formed within the substrate. A laser focused within the substrate may be used to create the modification layer. The modification layer creates a relatively weaker region that is more prone to cracking than the surrounding substrate material. As a result, the substrate may be pulled apart into separate sections, causing cracks the substrate along the modification layers. Dice or other components may be attached to the substrate before or after separation.

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Номер записи: 116
07-03-2013 дата публикации

Method of Three Dimensional Integrated Circuit Assembly

Номер: US20130056865A1
Автор: Huang Cheng-Lin, Jeng Shin-Puu, Lin Jing-Cheng, Lin Shih Ting, Lu Szu Wei, Wu Weng-Jin, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages. 1. A method comprising:attaching a wafer to a carrier;mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack;flipping the wafer stack;attaching the wafer stack to a tape frame; anddicing the wafer stack to separate the wafer stack into a plurality of individual packages.2. The method of claim 1 , further comprising:forming a first underfill layer between the wafer and the carrier.3. The method of claim 1 , further comprising:forming a second underfill layer between the wafer and the plurality of semiconductor dies.4. The method of claim 1 , further comprising:de-bonding the wafer stack from the carrier.5. The method of claim 1 , further comprising:detaching each individual package from the tape frame; andattaching the individual package on a substrate layer.6. The method of claim 5 , further comprising:detaching each individual package from the tape frame using a pick-and-place process.7. The method of claim 1 , further comprising:forming a plurality of first bumps on a first side of the wafer; andforming a plurality of second bumps on a second side the wafer.8. A method comprising:attaching a wafer to a carrier;mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack;encapsulating one side of the wafer stack with a molding compound layer;flipping the wafer stack;attaching the wafer stack to a tape frame; andsawing the wafer stack into a plurality of individual packages.9. The method of claim 8 , further comprising:embedding the plurality of semiconductor dies into the molding compound layer.10. The ...

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Номер записи: 117
14-03-2013 дата публикации

Packaging Methods and Structures Using a Die Attach Film

Номер: US20130062760A1
Автор: Chang Chin-Chuan, Hung Jui-Pin, Jeng Shin-Puu, Kao Chin-Fu, Lin Jing-Cheng, LIU Nai-Wei, Lu Szu Wei, Mao Yi-Chao, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

Packaging methods and structures for semiconductor devices that utilize a novel die attach film are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer and forming a die attach film (DAF) that includes a polymer over the carrier wafer. A plurality of dies is attached to the DAF, and the plurality of dies is packaged. At least the carrier wafer is removed from the packaged dies, and the packaged dies are singulated. 1. A method of packaging a semiconductor device , the method comprising:providing a carrier wafer;forming a die attach film (DAF) over the carrier wafer, the DAF comprising a polymer;attaching a plurality of dies to the DAF;packaging the plurality of dies;removing at least the carrier wafer from the packaged dies; andsingulating the packaged dies.2. The method according to claim 1 , wherein forming the DAF over the carrier wafer comprises forming a thermoplastic material.3. The method according to claim 2 , wherein forming the thermoplastic material comprises forming epoxy resin claim 2 , phenol resin claim 2 , or poly-olefin.4. The method according to claim 1 , wherein the step of packaging includes at least partially encapsulating the respective plurality of dies in a molding compound.5. The method according to claim 2 , wherein attaching the plurality of dies to the DAF comprises heating the DAF and applying pressure to the DAF.6. The method according to claim 5 , wherein heating the DAF comprises heating the DAF to a temperature of about 150 to 270 degrees C. for about 1 second to 2 minutes.7. The method according to claim 5 , wherein applying pressure to the DAF comprises applying a pressure of about 1 Newton (N) or greater.8. The method according to claim 1 , further comprising forming a release film over the carrier wafer claim 1 , before forming the DAF over the carrier wafer.9. The method according to claim 1 , further comprising marking the DAF.10. The method according to claim 9 , ...

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Номер записи: 118
28-03-2013 дата публикации

Method for Three Dimensional Integrated Circuit Fabrication

Номер: US20130075892A1
Автор: Hung Jui-Pin, Jeng Shin-Puu, Lin Jing-Cheng, Lu Szu Wei, Shih Ying-Ching, Wu Weng-Jin, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method for fabricating three dimensional integrated circuits comprises providing a wafer stack wherein a plurality of semiconductor dies are mounted on a first semiconductor die, forming a molding compound layer on the first side of the first semiconductor die, wherein the plurality of semiconductor dies are embedded in the molding compound layer. The method further comprises grinding a second side of the first semiconductor die until a plurality of through vias become exposed, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages. 1. A method comprising:providing a stack wherein a plurality of semiconductor dies are mounted on a first side of a wafer;forming a molding compound layer on the first side of the wafer, wherein the plurality of semiconductor dies are embedded in the molding compound layer;thinning a second side of the wafer until a plurality of through vias become exposed;attaching the stack to a tape frame; anddicing the stack to separate the stack into a plurality of individual packages.2. The method of claim 1 , further comprising:forming a first underfill layer between the wafer and the plurality of semiconductor dies.3. The method of claim 1 , further comprising:forming the plurality of through vias in the wafer;forming a plurality of first bumps on the first side of the wafer; andforming a first redistribution layer on the first side of the wafer.4. The method of claim 3 , wherein the plurality of semiconductor dies are connected to the wafer through the plurality of first bumps and the first redistribution layer.5. The method of claim 1 , further comprising:forming a plurality of second bumps on the second side of the wafer; andforming a second redistribution layer on the second side of the wafer.6. The method of claim 1 , further comprising:detaching each individual package from the tape frame.7. The method of claim 6 , further comprising:attaching the individual ...

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Номер записи: 119
28-03-2013 дата публикации

Apparatus and Methods for Molding Die on Wafer Interposers

Номер: US20130075937A1
Автор: Lin Jing-Cheng, Lu Szu Wei, Wang Chung Yu, Wu Chih-Wei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits. 1. A method , comprising:receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer assembly, the interposer assembly having spaces between the two or more integrated circuit dies;mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; andmolding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature.2. The method of and further comprising:curing the mold compound.3. The method of and further comprising:backgrinding the interposer assembly to thin the opposite side of the interposer assembly.4. The method of claim 1 , wherein the interposer assembly comprises a silicon wafer interposer.5. The method of claim 1 , wherein mounting at least one stress relief feature on the die side of the interposer assembly further comprises:dispensing a low modulus material on the die ...

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Номер записи: 120
28-03-2013 дата публикации

Structure Design for 3DIC Testing

Номер: US20130077272A1
Автор: Lin Jing-Cheng, Tsai Po-Hao
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A work piece includes a first copper-containing pillar having a top surface and sidewalls, and a first protection layer on the sidewalls, and not over the top surface, of the first copper-containing pillar. A test pad includes a second copper-containing pillar having a top surface and sidewalls. The test pad is electrically coupled to the first copper-containing pillar. A second protection layer is disposed on the sidewalls, and not over the top surface, of the second copper-containing pillar. The first and the second protection layers include a compound of copper and a polymer, and are dielectric layers. 1. A device comprising: a first copper-containing pillar having a top surface and sidewalls;', 'a first protection layer on the sidewalls, and not over the top surface, of the first copper-containing pillar;', 'a test pad comprising a second copper-containing pillar having a top surface and sidewalls, wherein the test pad is electrically coupled to the first copper-containing pillar; and', 'a second protection layer on the sidewalls, and not over the top surface, of the second copper-containing pillar, wherein the first and the second protection layers comprise a compound of copper and a polymer, and wherein the first and the second protection layers are dielectric layers., 'a first work piece comprising2. The device of claim 1 , wherein the second copper-containing pillar has a horizontal dimension greater than a horizontal dimension of the first copper-containing pillar.3. The device of further comprising a first and a second non-copper metal layer over and contacting the top surfaces of the first and the second copper-containing pillars.4. The device of further comprising metal finishes contacting a top surface and sidewalls of each of the first and the second non-copper metal layers.5. The device of further comprising a polyimide layer claim 1 , wherein the first and the second copper-containing pillars comprise portions over and overlapping the polyimide layer ...

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Номер записи: 121
11-04-2013 дата публикации

Selective Epitaxial Growth of Semiconductor Materials with Reduced Defects

Номер: US20130087831A1
Автор: Lin Jing-Cheng, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and over the substrate. The semiconductor region has a bottom surface contacting the substrate and having sloped sidewalls. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material. 1. A device comprising:a first semiconductor layer of a first semiconductor material;a first insulator layer disposed on the first semiconductor layer; anda semiconductor region having a first portion disposed in the first insulator layer and a second portion disposed in the first semiconductor layer, the second portion in contact with the first portion and having a width greater than a width of the first portion, and the first portion of a second semiconductor material different from the first semiconductor material.2. The device of claim 1 , wherein a sidewall of the first portion and a sidewall of the second portion are substantially vertical.3. The device of claim 1 , further comprising:a substrate of a third semiconductor material; anda second insulator layer in contact with and disposed between the substrate and the first semiconductor layer, the second portion of the semiconductor region extending through the first semiconductor layer and in contact with the second insulator layer.4. The device of claim 3 , wherein the second insulator layer is a buried oxide claim 3 , and wherein the first semiconductor material and the third semiconductor material are a same material.5. The device of claim 1 , wherein the first insulator layer is an oxide of the first semiconductor material.6. The device of claim 1 , wherein the second portion of the semiconductor region is formed of a fourth semiconductor material different from the second semiconductor material claim 1 , the second semiconductor material and fourth semiconductor material both ...

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Номер записи: 122
11-04-2013 дата публикации

Methods of Packaging Semiconductor Devices and Structures Thereof

Номер: US20130087916A1
Автор: Jing-Cheng Lin, Jui-Pin Hung, Tsan-Hua Tung, Yi-Hang Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

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Номер записи: 123
11-04-2013 дата публикации

Integrated Circuit Structure Having Dies with Connectors of Different Sizes

Номер: US20130087920A1
Автор: Jeng Shin-Puu, Lin Jing-Cheng, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface. The first die is attached to the first surface of the substrate by first electrical connectors. The second die is attached to the first surface of the substrate by second electrical connectors. A size of one of the second electrical connectors is smaller than a size of one of the first electrical connectors. 1. A structure comprising:a substrate having a first surface;a first die attached to the first surface of the substrate by first electrical connectors; anda second die attached to the first surface of the substrate by second electrical connectors, a size of one of the second electrical connectors being smaller than a size of one of the first electrical connectors.2. The structure of claim 1 , wherein each of the second electrical connectors has the size of the one of the second electrical connectors claim 1 , and each of the first electrical connectors has the size of the one of the first electrical connectors.3. The structure of claim 1 , wherein each of the size of the one of the second electrical connectors and the size of the one of the first electrical connectors is a diameter of a cross section of the respective connector claim 1 , the cross section being parallel to the first surface of the substrate.4. The structure of claim 1 , wherein respective adjacent ones of the first electrical connectors have a first pitch therebetween claim 1 , and respective adjacent ones of the second electrical connectors have a second pitch therebetween claim 1 , the first pitch being greater than the second pitch.5. The structure of further comprising a molding compound claim 1 , the molding compound being around and between the first die and the second die.6. The structure of claim 5 , wherein a top surface of the first die is exposed from the molding compound claim 5 , and the molding compound covers a top surface of the second die.7. The structure of ...

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Номер записи: 124
11-04-2013 дата публикации

Molding Chamber Apparatus and Curing Method

Номер: US20130087951A1
Автор: Hung Jui-Pin, Jeng Shin-Puu, Lin Jing-Cheng, Liu Hsien-Wen, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

An embodiment is a molding chamber. The molding chamber comprises a mold-conforming chase, a substrate-base chase, a first radiation permissive component, and a microwave generator coupled to a first waveguide. The mold-conforming chase is over the substrate-base chase, and the mold-conforming chase is moveable in relation to the substrate-base chase. The first radiation permissive component is in one of the mold-conforming chase or the substrate-base chase. The microwave generator and the first waveguide are together operable to direct microwave radiation through the first radiation permissive component. 1. A molding chamber comprising:a mold-conforming chase and a substrate-base chase, the mold-conforming chase being over the substrate-base chase, the mold-conforming chase being moveable in relation to the substrate-base chase;a first radiation permissive component in one of the mold-conforming chase or the substrate-base chase; anda microwave generator coupled to a first waveguide, the microwave generator and the first waveguide together operable to direct microwave radiation through the first radiation permissive component.2. The molding chamber of claim 1 , wherein the first radiation permissive component is in the mold-conforming chase claim 1 , the first waveguide being over the mold-conforming chase.3. The molding chamber of claim 1 , wherein the first radiation permissive component is in the substrate-base chase claim 1 , the first waveguide being under the substrate-base chase.4. The molding chamber of further comprising a second radiation permissive component in the substrate-base chase claim 1 , the first radiation permissive component being in the mold-conforming chase claim 1 , wherein the microwave generator is coupled to a second waveguide claim 1 , the microwave generator and the second waveguide together are operable to direct microwave radiation through the second permissive component.5. The molding chamber of claim 1 , wherein the first radiation ...

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Номер записи: 125
25-04-2013 дата публикации

Molded Chip Interposer Structure and Methods

Номер: US20130099377A1
Автор: Lin Jing-Cheng, Yu Chen-Hua, Yu Chun Hui
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

Apparatus and methods for providing a molded chip interposer structure and assembly. A molded chip structure having at least two integrated circuit dies disposed within a mold compound is provided having the die bond pads on the bottom surface; and solder bumps are formed in the openings of a dielectric layer on the bottom surface, the solder bumps forming connections to the bond pads. An interposer having a die side surface and a board side surface is provided having bump lands receiving the solder bumps of the molded chip structure on the die side of the interposer. An underfill layer is formed between the die side of the interposer and the bottom surface of the molded chip structure surrounding the solder bumps. Methods for forming the molded chip interposer structure are disclosed. 1. An apparatus , comprising:at least two integrated circuit dies formed in a mold compound layer, a bottom surface of the at least two integrated circuit dies and a bottom surface of the mold compound layer being coplanar;a passivation layer formed over the bottom surface of the mold compound layer and the bottom surface of the at least two integrated circuit dies;one or more openings in the passivation layer exposing one or more bond pads of the at least two integrated circuit dies; andsolder bumps formed on the bond pads of the at least two integrated circuit dies.2. The apparatus of claim 1 , further comprising a dummy solder bump disposed underneath the mold compound layer and positioned between the at least two integrated circuit dies.3. The apparatus of claim 1 , further comprising a support layer overlying the top surface of the mold compound layer.4. The apparatus of claim 1 , wherein one of the at least two integrated circuit dies has a first vertical thickness and another one of the at least two integrated circuit dies has a second vertical thickness different from the first vertical thickness.5. The apparatus of claim 1 , wherein the mold compound layer is free from ...

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Номер записи: 126
09-05-2013 дата публикации

End Point Detection in Grinding

Номер: US20130115854A1
Автор: Hung Jui-Pin, Jeng Shin-Puu, Lin Jing-Cheng, Mao Yi-Chao, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method for performing grinding includes selecting a target wheel loading for wafer grinding processes, and performing a grinding process on a wafer. With the proceeding of the grinding process, wheel loadings of the grinding process are measured. The grinding process is stopped after the target wheel loading is reached. The method alternatively includes selecting a target reflectivity of wafer grinding processes, and performing a grinding process on a wafer. With a proceeding of the grinding process, reflectivities of a light reflected from a surface of the wafer are measured. The grinding process is stopped after one of the reflectivities reaches the target reflectivity. 1. A method comprising:selecting a target wheel loading for wafer grinding processes;performing a grinding process on a wafer, and with a proceeding of the grinding process, measuring wheel loadings of the grinding process; andstopping the grinding process after the target wheel loading is reached.2. The method of further comprising claim 1 , when the target wheel loading is reached claim 1 , performing an extended grinding to remove a layer of the wafer having a pre-determined thickness claim 1 , wherein the step of stopping the grinding process is performed upon finishing of the extended grinding.3. The method of further comprising claim 1 , when the target wheel loading is reached claim 1 , performing an extended grinding for a pre-determined period of time claim 1 , wherein the step of stopping the grinding process is performed upon finishing of the extended grinding.4. The method of claim 1 , wherein the step of selecting the target wheel loading comprises:grinding a sample wafer having a same structure as the wafer;during the step of grinding the sample wafer, monitoring wheel loadings for grinding the sample wafer;inspecting the sample wafer to determine an optimal end point of the grinding process; andrecording one of the wheel loadings corresponding to the optimal end point as the target ...

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Номер записи: 127
16-05-2013 дата публикации

Plating Process and Structure

Номер: US20130119382A1
Автор: Huang Cheng-Lin, Kao Chin-Fu, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A system and method for plating a contact is provided. An embodiment comprises forming protective layers over a contact and a test pad, and then selectively removing the protective layer over the contact without removing the protective layer over the test pad. With the protective layer still on the test pad, a conductive layer may be plated onto the contact without plating it onto the test pad. After the contact has been plated, the protective layer over the contact may be removed. 1. A method for manufacturing a semiconductor device , the method comprising:providing a contact and a test pad on a substrate, the contact and the test pad being electrically in contact with each other;forming a first protective layer from a portion of the test pad; andplating a conductive layer over the contact while the first protective layer is on the test pad.2. The method of claim 1 , further comprising forming a second protective layer from a portion of the contact claim 1 , the forming the second protective layer occurring in the same process as the forming the first protective layer.3. The method of claim 2 , further comprising removing the second protective layer from the contact before the plating the conductive layer claim 2 , the removing the second protective layer comprising etching the second protective layer with a solution comprising sulfuric acid.4. The method of claim 1 , further comprising removing the first protective layer from the test pad after the plating the conductive layer.5. The method of claim 4 , wherein the removing the first protective layer further comprises etching the first protective layer with a solution comprising sodium hydroxide.6. The method of claim 1 , wherein the plating the conductive layer comprises an electroless immersion process.7. The method of claim 1 , wherein the forming the first protective layer further comprises oxidizing the portion of the test pad.8. The method of claim 1 , wherein the forming the first protective layer further ...

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Номер записи: 128
16-05-2013 дата публикации

Package for Three Dimensional Integrated Circuit

Номер: US20130119533A1
Автор: Chen Chih-Hao, Hung Jui-Pin, Lee Long Hua, Lin Jing-Cheng, Su Chun-Hsing, Tsai Yi-Lin, Wang Chung Yu, Yeh Kung-Chen
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package. 1. A device comprising:a semiconductor substrate having a recess portion and a non-recess portion, wherein a first recess is located at the recess portion;an isolation layer formed on the non-recess portion of the semiconductor substrate;a redistribution layer formed on the isolation layer;an under bump metal structure formed on the redistribution layer; anda first bump formed on the under bump metal structure.2. The device of claim 1 , wherein the first recess is of a step shape at a first side of the device.3. The device of claim 2 , further comprising:a second recess having the step shape at a second side of the device; anda third recess having the step shape at a third side of the device.4. The device of claim 2 , further comprising:a second recess having the step shape at a second side of the device.5. The device of claim 1 , wherein the first recess is of a slope shape.6. The device of claim 1 , wherein the first recess is of a curved shape.7. A method comprising:cutting into a semiconductor die with a first dicing depth using a first dicing saw;cutting through the semiconductor die with a second dicing saw to separate the semiconductor die from a wafer, wherein the second dicing sawing has a second blade different from a first blade of the first dicing sawing;forming a step recess at one side of the semiconductor die;flipping the semiconductor die; andattaching a first side of the semiconductor die on a first side of a package substrate.8. The method of claim 7 , further comprising:forming an underfill layer between the ...

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Номер записи: 129
16-05-2013 дата публикации

Method for Forming Chip-on-Wafer Assembly

Номер: US20130119552A1
Автор: Chen-Hua Yu, Cheng-Lin Huang, Jing-Cheng Lin, Jui-Pin Hung, Shin-puu Jeng, Szu Wei Lu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.

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Номер записи: 130
16-05-2013 дата публикации

Embedded Wafer-Level Bonding Approaches

Номер: US20130122655A1
Автор: Lin Jing-Cheng, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method includes providing a carrier with an adhesive layer disposed thereon; and providing a die including a first surface, a second surface opposite the first surface. The die further includes a plurality of bond pads adjacent the second surface; and a dielectric layer over the plurality of bond pads. The method further includes placing the die on the adhesive layer with the first surface facing toward the adhesive layer and dielectric layer facing away from the adhesive layer; forming a molding compound to cover the die, wherein the molding compound surrounds the die; removing a portion of the molding compound directly over the die to expose the dielectric layer; and forming a redistribution line above the molding compound and electrically coupled to one of the plurality of bond pads through the dielectric layer. 1. A method comprising: a substrate;', 'a plurality of bond pads over the substrate; and', 'a dielectric layer over the plurality of bond pads;, 'placing a die over a carrier, wherein the die comprisesforming a molding compound surrounding the die;etching the dielectric layer to forming openings; andforming conductive pillars in the openings to electrically couple to the plurality of bond pads.2. The method of further comprising claim 1 , before the step of etching the dielectric layer claim 1 , removing a portion of the molding compound overlapping the die to expose the dielectric layer.3. The method of claim 2 , wherein the step of removing the portion of the molding compound overlapping the die comprises grinding.4. The method of further comprising claim 1 , after the step of forming the conductive pillars claim 1 , forming metal bumps over and electrically coupled to the conductive pillars.5. The method of further comprising claim 1 , after the conductive pillars are formed claim 1 , demounting the carrier.6. The method of claim 1 , wherein a thickness of the dielectric layer is greater than about 10 μm.7. The method of further comprising sawing ...

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Номер записи: 131
16-05-2013 дата публикации

Assembly Method for Three Dimensional Integrated Circuit

Номер: US20130122659A1
Автор: Jeng Shin-Puu, Lin Jing-Cheng, Lu Szu Wei, Wu Chih-Wei, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method comprises attaching a first side of an interposer on a carrier wafer. The first side of the interposer comprises a plurality of bumps. The carrier wafer comprises a plurality of cavities formed in the carrier wafer. Each bump on the first side of the interposer can fit into its corresponding cavity on the carrier wafer. Subsequently, the method comprises attaching a semiconductor die on the second side of the interposer to form a wafer stack, detaching the wafer stack from the carrier wafer and attaching the wafer stack to a substrate. 1. A method comprising:receiving a carrier wafer having a plurality of cavities formed in the carrier wafer; a plurality of first bumps on a first side of the interposer; and', 'a plurality of second bumps on a second side of the interposer, wherein each of the first bumps and second bumps respectively has a circular shape;, 'receiving an interposer comprising'}attaching the interposer to the carrier wafer, wherein the first bumps are configured such that each first bump is located in a corresponding cavity in the carrier wafer, and wherein the first bumps are configured to maintain a gap between interior walls of a cavity and exterior walls of a corresponding first bump;attaching a semiconductor die on the second side of the interposer to form a wafer stack; andattaching the wafer stack to a substrate.2. The method of claim 1 , further comprising:forming a first underfill layer between the interposer and the semiconductor die.3. The method of claim 1 , further comprising:forming a second underfill layer between the interposer and the substrate.4. The method of claim 1 , wherein the interposer comprises:a plurality of through vias in the interposer.5. The method of claim 4 , wherein the interposer comprises:a first redistribution layer on the first side of the interposer; anda second redistribution layer on the second side of the interposer, wherein the first bumps are connected to respective through vias through the first ...

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Номер записи: 132
30-05-2013 дата публикации

Chip-on-Wafer Structures and Methods for Forming the Same

Номер: US20130134559A1
Автор: Chang Hsin, Lin Jing-Cheng, Lin Shih Ting
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A package component includes a substrate, wherein the substrate has a front surface and a back surface over the front surface. A through-via penetrates through the substrate. A conductive feature is disposed over the back surface of the substrate and electrically coupled to the through-via. A first dielectric pattern forms a ring covering edge portions of the conductive feature. An Under-Bump-Metallurgy (UBM) is disposed over and in contact with a center portion of the conductive feature. A polymer contacts a sidewall of the substrate. A second dielectric pattern is disposed over and aligned to the polymer. The first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level. 1. A device comprising:a package component comprising a substrate, wherein the substrate comprises a front surface, and a back surface over the front surface;a through-via penetrating through the substrate;a conductive feature over the back surface of the substrate and electrically coupled to the through-via;a first dielectric pattern forming a ring covering edge portions of the conductive feature;a Under-Bump-Metallurgy (UBM) over and in contact with a center portion of the conductive feature;a polymer contacting a sidewall of the substrate; anda second dielectric pattern over and aligned to the polymer, wherein the first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level.2. The device of claim 1 , wherein the first and the second dielectric patterns comprise an additional polymer.3. The device of claim 1 , wherein the first and the second dielectric patterns comprise a photo sensitive material.4. The device of further comprising a die bonded to a front side of the package component claim 1 , wherein the polymer further encircles the die claim 1 , and contacts sidewalls of the die.5. The device of being a discrete package claim 1 , wherein the polymer forms ...

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Номер записи: 133
30-05-2013 дата публикации

PLANARIZED BUMPS FOR UNDERFILL CONTROL

Номер: US20130134581A1
Автор: Lin Jing-Cheng, Tsai Po-Hao
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

The mechanisms for forming bump structures reduce variation of standoffs between chips and package substrates. By planarizing the solder layer on bump structures on chips and/or substrates after plating, the heights of bump structures are controlled to minimize variation due to within die and within wafer locations, pattern density, die size, and process variation. As a result, the standoffs between chips and substrates are controlled to be more uniform. Consequently, underfill quality is improved. 1. A chip package , comprising:a plurality of bump structures between a first chip and a substrate of the chip package; anda solder layer in a first bump structure of the plurality of bump structures near a center of the first chip is thicker than a solder layer in a second bump structure of the plurality of bump structures near an edge of the first chip, and a solder layer in a third bump structure of the plurality of bump structures positioned between the first bump structure and the second bump structure is thicker than the solder layer of the second bump structure and thinner than a solder layer of the first bump structure.2. The chip package of claim 1 , wherein each of the plurality of bump structures comprises a copper layer claim 1 , and a metal layer claim 1 , wherein the metal layer is between the copper layer and the solder layer.3. The chip package of claim 1 , wherein the substrate is an interposer.4. The chip package of claim 1 , wherein a second chip is bonded to the substrate by another plurality of bump structures claim 1 , and wherein a first standoff between the first chip and the substrate and a second standoff between the second chip and the substrate are substantially the same.5. The chip package of claim 4 , wherein there is a first underfill between the first chip and the substrate and a second underfill between the second chip and the substrate claim 4 , and wherein the first underfill and the second underfill have about the same volume.6. The ...

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Номер записи: 134
30-05-2013 дата публикации

NOVEL BUMP STRUCTURES FOR MULTI-CHIP PACKAGING

Номер: US20130134582A1
Автор: Lin Jing-Cheng, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

The mechanisms for forming a multi-chip package described enable chips with different bump sizes being packaged to a common substrate. A chip with larger bumps can be bonded with two or more smaller bumps on a substrate. Conversely, two or more small bumps on a chip may be bonded with a large bump on a substrate. By allowing bumps with different sizes to be bonded together, chips with different bump sizes can be packaged together to form a multi-chip package. 1. A chip package , comprising:a first bump structure between a first chip and a substrate of the chip package, wherein a first solder layer of the first bump structure covers more than one bump on the substrate.2. The chip package of claim 1 , wherein the first bump structure includes one bump of the first chip.3. The chip package of claim 1 , wherein there is a second chip on the chip package claim 1 , and wherein there is a second bump structure between the second chip and the substrate claim 1 , wherein a solder layer of the second bump structure connects a bump on the substrate with a bump on the second chip.4. The chip package of claim 1 , wherein the more than one bump of the first bump structure and the bump on the substrate of the second bump structure are about the same size.5. The chip package of claim 1 , wherein widths of the more than one bump on the substrate are in a range from about 5 μm to about 30 μm.6. The chip package of claim 1 , wherein the more than one bump on the substrate includes 2 claim 1 , 3 claim 1 , 4 claim 1 , 5 claim 1 , 6 claim 1 , 7 claim 1 , or 8 bumps.7. The chip package of claim 2 , where the bump on the first chip has a width greater than about 40 μm and equal to or less than about 120 μm.8. The chip package of claim 1 , the first chip is memory chip.9. The chip package of claim 1 , wherein the substrate is an interposer.10. The chip package of claim 9 , wherein the more than one bump on the substrate includes a copper post bump.114. The chip package of claim 2 , wherein ...

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Номер записи: 135
06-06-2013 дата публикации

Plating Process and Structure

Номер: US20130140563A1
Автор: Huang Cheng-Lin, Kao Chin-Fu, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another embodiment a blocking structure may be inserted between the contact and the test pad. In yet another embodiment a blocking layer may be inserted into a contact stack. Once the blocking material, the blocking structure, or the blocking layer have been formed, the contact may be plated, with the blocking material, the blocking structure, or the blocking layer reducing or preventing degradation of the test pad due to galvanic effects. 1. A semiconductor device comprising:a contact on a substrate, the contact comprising a first material with a first reduction potential, the first reduction potential being at a first end of a range of reduction potentials;a test pad on the substrate, the test pad comprising a second material with a second reduction potential different from the first reduction potential, the second reduction potential being at a second end of the range of reduction potentials; andat least one via electrically connecting the test pad to the contact, the at least one via comprising a third material with a third reduction potential, the third reduction potential being outside of the range of reduction potentials.2. The semiconductor device of claim 1 , wherein the third reduction potential is greater than the second reduction potential.3. The semiconductor device of claim 1 , wherein the third reduction potential is lower than the first reduction potential.4. The semiconductor device of claim 1 , wherein the first material comprises copper and the second material comprises aluminum.5. The semiconductor device of claim 4 , wherein the third material comprises magnesium.6. The semiconductor device of claim 4 , wherein the third material comprises platinum.7. The semiconductor device of claim 1 , further comprising a redistribution line electrically connecting the test pad ...

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Номер записи: 136
06-06-2013 дата публикации

TSV Structures and Methods for Forming the Same

Номер: US20130140690A1
Автор: Chen Hsin-Yu, Chiou Wen-Chih, Lin Jing-Cheng, LIN Yung-Chi, WU Tsang-Jiuh, YANG Ku-Feng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad. 1. A device comprising:a substrate comprising a front side and a backside;a through-via extending from the backside to the front side of the substrate;a conductive pad on the backside of the substrate and over the through-via, wherein the conductive pad comprises a substantially planar top surface; anda conductive bump having a non-planar top surface over the substantially planar top surface and aligned to the through-via, wherein the conductive bump and the conductive pad are formed of a same material, and wherein no interface is formed between the conductive bump and the conductive pad.2. The device of claim 1 , wherein the top surface of the conductive bump is rounded.3. The device of claim 1 , wherein the conductive bump has a height between about 0.1 μm and about 10 μm.4. The device of claim 1 , wherein the conductive bump has a lateral dimension between about 2.0 μm and about 30 μm.5. The device of claim 1 , wherein the substantially planar top surface is aligned to a portion of the substrate encircling the through-via.6. The device of further comprising a metal-oxide-semiconductor (MOS) device on the front side of the substrate.7. The device of further comprising an under-bump metallurgy (UBM) over the conductive bump and the conductive pad claim 1 , wherein the UBM comprises a first portion over and in contact with the non-planar top surface of the conductive bump claim 1 , and a second portion over and in contact ...

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Номер записи: 137
20-06-2013 дата публикации

Die Structure and Method of Fabrication Thereof

Номер: US20130154062A1
Автор: Kuo Li-Chung, Lin Jing-Cheng, Lu Szu Wei, Wang Ying-Da
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A die having a ledge along a sidewall, and a method of forming the die, is provided. A method of packaging the die is also provided. A substrate, such as a processed wafer, is diced by forming a first notch having a first width, and then forming a second notch within the first notch such that the second notch has a second width less than the first width. The second notch extends through the substrate, thereby dicing the substrate. The difference in widths between the first width and the second width results in a ledge along the sidewalls of the dice. The dice may be placed on a substrate, e.g., an interposer, and underfill placed between the dice and the substrate. The ledge prevents or reduces the distance the underfill is drawn up between adjacent dice. A molding compound may be formed over the substrate. 1. A method comprising:providing a substrate;forming a first notch between a first region and a second region, the first notch having a first width;forming a second notch within the first notch, the second notch having a second width less than the first width, thereby forming a ledge, the second notch extending through the substrate, thereby dicing the substrate into separate dice;placing one or more of the dice onto a second substrate such that the ledge is opposite the second substrate; andplacing an underfill between the one or more of the dice and the second substrate, an upper surface of the underfill being at the ledge.2. The method of claim 1 , further comprising placing the substrate on a carrier tape prior to forming the second notch.3. The method of claim 2 , wherein the substrate is attached to the carrier tape via conductive bumps.4. (canceled)5. The method of claim 1 , wherein the second substrate comprises an interposer.6. The method of claim 1 , further comprising forming a molding compound over the underfill between adjacent dice.7. The method of claim 6 , further comprising thinning the molding compound.8. The method of claim 1 , wherein the ...

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Номер записи: 138
04-07-2013 дата публикации

PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING THE SEMICONDUCTOR DEVICE

Номер: US20130168848A1
Автор: Hung Jui-Pin, Lin Jing-Cheng, LIU Nai-Wei, Mao Yi-Chao, SHIH Wan-Ting, TUNG Tsan-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved. 1. A packaged semiconductor device , comprising:a contact pad on a semiconductor die;an insulating layer surrounding the contact pad; anda molding compound surrounding the insulating layer, wherein the molding compound comes in contact with two adjacent and non-linear surfaces of the insulating layer.2. The package semiconductor device of claim 1 , wherein a wiring layer is disposed on and physically connects to the contact pad claim 1 , wherein the wiring layer extends beyond the boundary of the semiconductor die.3. The package semiconductor device of claim 1 , wherein the insulating layer surrounding the contact pad has a thin portion and a thick portion claim 1 , and wherein the thin portion has a thickness in a range from about 1 μm to about 30 μm.4. The package semiconductor device of claim 1 , wherein a protective layer is between the contact pad and the insulating layer.5. The package semiconductor device of claim 4 , wherein the protective layer is a copper diffusion barrier.6. The package semiconductor device of claim 4 , wherein the protective layer has a thickness in a range from about 50 nm to about 2 μm.7. The package semiconductor device of claim 4 , wherein the protective layer is also between the ...

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Номер записи: 139
11-07-2013 дата публикации

Interposer-on-Glass Package Structure

Номер: US20130174417A1
Автор: Lin Jing-Cheng, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method comprises providing an interposer comprising a substrate and a first through-substrate via (TSV) penetrating through the substrate, forming a first oxide layer on a surface of the interposer, bonding a glass substrate to the interposer through a fusion bonding, with the first oxide layer being between the interposer and the glass substrate and forming a second TSV in the glass substrate and electrically coupled to the first TSV. 1. A method comprising: a substrate; and', 'a first through-substrate via (TSV) penetrating through the substrate;, 'providing an interposer comprisingforming a first oxide layer on a surface of the interposer;bonding a glass substrate to the interposer through a fusion bonding, with the first oxide layer being between the interposer and the glass substrate; andforming a second TSV in the glass substrate and electrically coupled to the first TSV.2. The method of claim 1 , further comprising forming a second oxide layer on the glass substrate before the step of bonding claim 1 , wherein the second oxide layer is bonded to and contacts the first oxide layer after the step of bonding.3. The method of claim 1 , wherein the glass substrate comprises a glass layer comprising an oxide claim 1 , and wherein the glass layer is directly bonded to the first oxide layer.4. The method of claim 1 , wherein the glass substrate comprises a photo-sensitive glass layer and a non-photo-sensitive glass layer claim 1 , and wherein the step of forming the second TSV comprises:exposing the photo-sensitive glass layer using a lithography mask, with first portions of the photo-sensitive glass layer being exposed to light, and second portions of the photo-sensitive glass layer not exposed to the light;etching the first portions of the photo-sensitive glass layer without etching the second portions of the photo-sensitive glass layer;using the photo-sensitive glass layer as a hard mask to etch the non-photo-sensitive glass layer; andfilling an opening in the ...

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Номер записи: 140
11-07-2013 дата публикации

Packages and Method of Forming the Same

Номер: US20130175694A1
Автор: Jing-Cheng Lin, Szu Wei Lu, Ying-Ching Shih
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method includes forming a dielectric layer over a substrate, forming an interconnect structure over the dielectric layer, and bonding a die to the interconnect structure. The substrate is then removed, and the dielectric layer is patterned. Connectors are formed at a surface of the dielectric layer, wherein the connectors are electrically coupled to the die.

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Номер записи: 141
25-07-2013 дата публикации

Sawing Underfill in Packaging Processes

Номер: US20130187258A1
Автор: Kuo Li-Chung, Lin Jing-Cheng, Lu Szu Wei, Wang Ying-Da
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components. 1. A method comprising:bonding a first and a second package component on a top surface of a third package component; a first portion in a space between the first and the third package components;', 'a second portion in a space between the second and the third package components; and', 'a third portion in a gap between the first and the second package components;, 'dispensing a first polymer, wherein the first polymer comprisesperforming a curing on the first polymer; andafter the curing, sawing the third portion of the first polymer to form a trench between the first and the second package components, wherein at a time the step of sawing is performed.2. The method of claim 1 , wherein the curing is a partial curing claim 1 , and wherein the method further comprises claim 1 , after the step of sawing the third portion of the first polymer claim 1 , performing a thermal step to fully cure the first polymer.3. The method of claim 1 , wherein after the step of curing claim 1 , the first polymer is fully cured.4. The method of further comprising claim 1 , after the step of sawing claim 1 , molding the first claim 1 , the second claim 1 , and the third package components with a second polymer claim 1 , wherein the second polymer is filled into the trench.5. The method of further comprising claim 4 , after the step of molding with the second polymer claim 4 , performing a die-saw on the third package ...

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Номер записи: 142
25-07-2013 дата публикации

Multi-Chip Fan Out Package and Methods of Forming the Same

Номер: US20130187270A1
Автор: Hung Jui-Pin, Lin Jing-Cheng, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line. 1. A device comprising:a die comprising a conductive pad at a top surface of the die;a stud bump over and connected to the conductive pad;a redistribution line over and connected to the stud bump; andan electrical connector over and electrically coupled to the redistribution line.2. The device of further comprising a polymer encircling the die and contacting sidewalls of the die claim 1 , wherein a bottom surface of the polymer is substantially level with a bottom surface of the die.3. The device of claim 2 , wherein the redistribution line extends beyond edges of the die to overlap the polymer.4. The device of further comprising:a semiconductor substrate in the die; anda dielectric layer, wherein the stud bump is in the dielectric layer, wherein the dielectric layer and the polymer comprise different materials, and wherein edges of the dielectric layer are aligned to respective edges of the semiconductor substrate.5. The device of claim 2 , wherein the polymer comprises a portion overlapping the die claim 2 , and wherein the portion of the polymer encircles and contacts the stud bump.6. The device of claim 5 , wherein a top surface of the polymer is level with a top surface of the stud bump.7. The device of claim 1 , wherein the stud bump is a wire bonding stud bump having non-vertical sidewalls.8. A device comprising: a semiconductor substrate; and', 'a first conductive pad at a top surface of the first die;, 'a first die comprisinga first stud bump over and connected to the first conductive pad;a polymer encircling the first die and contacting sidewalls of the first die, wherein a bottom surface of the polymer is substantially level with a bottom surface of the semiconductor substrate, ...

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Номер записи: 143
01-08-2013 дата публикации

BUMP STRUCTURAL DESIGNS TO MINIMIZE PACKAGE DEFECTS

Номер: US20130193593A1
Автор: Huang Cheng-Lin, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

The mechanisms for forming bump structures enable forming bump structures between a chip and a substrate eliminating or reducing the risk of solder shorting, flux residue and voids in underfill. A lower limit can be established for a cc ratio, defined by dividing the total height of copper posts in a bonded bump structure divided by the standoff of the bonded bump structure, to avoid shorting. A lower limit may also be established for standoff the chip package to avoid flux residue and underfill void formation. Further, aspect ratio of a copper post bump has a lower limit to avoid insufficient standoff and a higher limit due to manufacturing process limitation. By following proper bump design and process guidelines, yield and reliability of chip packages may be increases. 1. A chip package , comprising:a first copper post on a chip having a first height; anda second copper post on a substrate having a second height, wherein the second copper post is bonded to the first copper post by a solder layer to form a first copper post bump structure of the chip package having a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1.2. The chip package of claim 1 , wherein a first width of the first copper post is equal to or less than about 30 μm and a second width of the second copper post is also equal to or less than about 30 μm.3. The chip package of claim 1 , further comprising a second copper post bump structure formed next to the first copper post bump structure claim 1 , wherein a pitch between the first and the second copper post bump structures is equal to or less than about 60 μm.4. The chip package of claim 1 , wherein an aspect ratio of the first copper post is equal to or greater than about 0.45.5. The chip package of claim 1 , wherein the standoff is equal to or greater than about 30 μm.6. The chip package of claim 1 , wherein the first copper post is disposed on a ...

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Номер записи: 144
08-08-2013 дата публикации

Flux Residue Cleaning System and Method

Номер: US20130199577A1
Автор: Chen I-Ting, Lin Jing-Cheng, Lu Szu Wei, Shih Ying-Ching
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A flux residue cleaning system includes first and second immersion chambers, first and second spray chambers, and a drying chamber. The first immersion chamber softens an outer region of a flux residue formed around microbumps interposed between a wafer and a die when the wafer is immersed in a first chemical. The first spray chamber removes the outer region of the flux residue when the wafer is impinged upon by a first chemical spray in order to expose an inner region of the flux residue. The second immersion chamber softens the inner region of the flux residue when the wafer is immersed in a second chemical. The second spray chamber removes the inner region of the flux residue when the wafer is impinged upon by a second chemical spray in order to clean the wafer to a predetermined standard. The drying chamber dries the wafer. 1. A flux residue cleaning system , comprising:a first immersion chamber configured to soften an outer region of a flux residue formed around microbumps interposed between a wafer and a die when the wafer is immersed in a first chemical;a first spray chamber configured to remove the outer region of the flux residue when the wafer is impinged upon by a first chemical spray in order to expose an inner region of the flux residue;a second immersion chamber configured to soften the inner region of the flux residue formed around the microbumps interposed between the wafer and the die when the wafer is immersed in a second chemical;a second spray chamber configured to remove the inner region of the flux residue when the wafer is impinged upon by a second chemical spray in order to clean the wafer; anda drying chamber configured to dry the wafer when the wafer is exposed to a flow of nitrogen.2. The flux residue cleaning system of claim 1 , wherein the first immersion chamber is equipped with a first sonic wave apparatus configured to propagate at least one of an ultrasonic wave and a megasonic wave through the first chemical to promote removal of ...

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Номер записи: 145
08-08-2013 дата публикации

Semiconductor Device Packaging Methods and Structures Thereof

Номер: US20130200529A1
Автор: I-Hsuan Peng, Jing-Cheng Lin, Szu Wei Lu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Semiconductor device packaging methods and structures thereof are disclosed. In one embodiment, a method of packaging semiconductor devices includes coupling a plurality of second dies to a top surface of a first die, and determining a distance between each of the plurality of second dies and the first die. The method also includes determining an amount of underfill material to dispose between the first die and each of the plurality of second dies based on the determined distance, and disposing the determined amount of the underfill material under each of the plurality of second dies.

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Номер записи: 146
08-08-2013 дата публикации

Packaging Methods for Semiconductor Devices

Номер: US20130203215A1
Автор: Hung Jui-Pin, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

Methods of packaging semiconductor devices are disclosed. In one embodiment, a packaging method for semiconductor devices includes providing a workpiece including a plurality of first dies, and coupling a plurality of second dies to the plurality of first dies. The plurality of second dies and the plurality of first dies are partially packaged and separated. Top surfaces of the second dies are coupled to a carrier, and the partially packaged plurality of second dies and plurality of first dies are fully packaged. The carrier is removed, and the fully packaged plurality of second dies and plurality of first dies are separated. 1. A packaging method for semiconductor devices , the method comprising:providing a workpiece including a plurality of first dies;coupling a plurality of second dies to the plurality of first dies;partially packaging the plurality of second dies and the plurality of first dies;separating the partially packaged plurality of second dies and plurality of first dies;coupling top surfaces of the plurality of second dies to a carrier;fully packaging the partially packaged plurality of second dies and plurality of first dies;removing the carrier; andseparating the fully packaged plurality of second dies and plurality of first dies.2. The method according to claim 1 , wherein fully packaging the partially packaged plurality of second dies and plurality of first dies comprises:forming a molding compound over the plurality of first dies and the carrier;reducing a thickness of the plurality of first dies and the molding compound, exposing conductive features formed within the plurality of first dies;coupling a wiring structure to the exposed conductive features of the plurality of first dies; andforming a plurality of conductive bumps on the wiring structure.3. The method according to claim 2 , wherein coupling the wiring structure comprises forming a redistribution layer (RDL).4. The method according to claim 2 , wherein the conductive features formed ...

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Номер записи: 147
15-08-2013 дата публикации

Methods for Molding Integrated Circuits

Номер: US20130207306A1
Автор: Chen Chih-Hao, Hung Jui-Pin, Lin Jing-Cheng, Liu Hsien-Wen, Tsai Yi-Lin
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method includes molding a polymer onto a package component. The step of molding includes a first molding stage performed at a first temperature, and a second molding stage performed at a second temperature different from the first temperature. 1. A method comprising: a first molding stage performed at a first temperature; and', 'a second molding stage performed at a second temperature different from the first temperature., 'molding a polymer onto a package component, wherein the step of molding comprises2. The method of claim 1 , wherein the first temperature is lower than a gel temperature of the polymer claim 1 , and wherein the second temperature is higher than the gel temperature of the polymer.3. The method of claim 1 , wherein the step of molding further comprises:dispensing the polymer onto the package component;pressing the polymer using a mold to spread the polymer, wherein during a period of time starting from a first time point the mold is in contact with the polymer and ending at a second time point the polymer is fully spread, the mold is maintained at, or below, the first temperature; andafter the polymer is fully spread, heating the mold to the second temperature.4. The method of further comprising claim 3 , after the second molding stage claim 3 , and without removing the mold from the polymer claim 3 , cooling the polymer.5. The method of claim 4 , wherein the step of cooling the polymer is performed by conducting a coolant into a pipe built in the mold.6. The method of claim 1 , wherein the second temperature is higher than the first temperature by a temperature difference greater than about 2° C.7. The method of claim 1 , wherein during the first molding stage claim 1 , a first current is conducted to a heating element in an mold claim 1 , wherein the mold is used to heat the polymer claim 1 , and wherein during the second molding stage claim 1 , a second current higher than the first current is conducted to the heating element.8. A method ...

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Номер записи: 148
15-08-2013 дата публикации

PROCESS FOR FORMING SEMICONDUCTOR STRUCTURE

Номер: US20130210198A1
Автор: Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A method for forming a semiconductor structure. A semiconductor substrate including a plurality of dies mounted thereon is provided. The substrate includes a first portion proximate to the dies and a second portion distal to the dies. In some embodiments, the first portion may include front side metallization. The second portion of the substrate is thinned and a plurality of conductive through substrate vias (TSVs) is formed in the second portion of the substrate after the thinning operation. Prior to thinning, the second portion may not contain metallization. In one embodiment, the substrate may be a silicon interposer. Further back side metallization may be formed to electrically connect the TSVs to other packaging substrates or printed circuit boards. 1. A method for fabricating a semiconductor structure comprising:providing a semiconductor substrate including a plurality of dies mounted thereon, the substrate including a first portion proximate to the dies and a second portion distal to the dies;thinning the second portion of the substrate; andforming a plurality of conductive through substrate vias (TSVs) in the second portion of the substrate after thinning2. The method of claim 1 , wherein the first portion of the substrate includes front side metallization electrically connected to the dies.3. The method of claim 2 , wherein the front side metallization includes redistribution layer interconnects.4. The method of claim 1 , wherein prior to the thinning step claim 1 , the second portion does not contain metallization.5. The method of claim 1 , further comprising filling interstitial spaces between the dies with a molding compound before the thinning step.6. The method of claim 1 , further comprising attaching a temporary carrier to dies for handling the semiconductor structure before the thinning step.7. The method of claim 1 , wherein the substrate has a total thickness of less than 100 microns after the thinning step.8. The method of claim 1 , further ...

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Номер записи: 149
22-08-2013 дата публикации

Structures and Formation Methods of Packages with Heat Sinks

Номер: US20130217188A1
Автор: Lin Jing-Cheng, Syu Shih-Yi, Wang Chung Yu
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A device includes a package component, and a die over and bonded to the package component. The die includes a substrate. A heat sink is disposed over and bonded to a back surface of the substrate through direct bonding. 1. A device comprising:a first package component;a die over and bonded to the first package component, wherein the die comprises a substrate; anda heat sink over and bonded to a back surface of the substrate.2. The device of claim 1 , wherein the heat sink comprises silicon claim 1 , and wherein a surface of the silicon is in physical contact with the back surface of the substrate of the die.3. The device of claim 2 , wherein the substrate of the die comprises silicon claim 2 , and wherein the bonding of the heat sink and the substrate comprises silicon-to-silicon bonding.4. The device of further comprising a molding material encircling the die claim 1 , wherein the molding material comprises edges aligned to corresponding edges of the heat sink claim 1 , and wherein the edges of the molding material are further aligned to corresponding edges of the first package component.5. The device of claim 1 , wherein the first package component further comprises:an additional substrate;through vias penetrating through the additional substrate and electrically coupled to the die; andconnectors at a bottom surface of the first package component, wherein the connectors and the die are on opposite sides of the first package component.6. The device of further comprising a second package component claim 5 , wherein the first package component and the second package component are bonded to each other through the connectors.7. A device comprising:a first package component;a die over and bonded to the first package component, wherein the die comprises a silicon substrate; anda heat sink over and bonded to a back surface of the silicon substrate, wherein the heat sink comprises a plurality of pillars separated from each other by trenches, and wherein the silicon ...

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Номер записи: 150
29-08-2013 дата публикации

MECHANISMS FOR CONTROLLING BUMP HEIGHT VARIATION

Номер: US20130223014A1
Автор: Lin Jing-Cheng, Tsai Po-Hao
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

The mechanisms for forming bumps on packaged dies and package substrates reduce variation of bump heights across the packaged dies and packaged substrates. Bumps are designed to have different widths to counter the higher plating current near edge(s) of dies or substrates. Bump sizes can be divided into different zones depending on the bump patterns and densities across the packaged die and/or substrates. Smaller bumps near edges reduce the thickness of plated film(s), which would have been thicker due to being near the edges. As a result, the bump heights across the packaged dies and/or substrates can be kept significantly constant and chip package can be properly formed. 1. A chip package , comprising:a packaged chip;a substrate; anda plurality of bump structures between the packaged chip and the substrate, wherein bump structures near an edge of the chip package have widths smaller than bumps structures near a center of the chip package by an amount ranging from about 5% to about 50%.2. The chip package of claim 1 , wherein each of the plurality of bump structures comprises a copper layer claim 1 , a metal layer claim 1 , and a solder layer wherein the metal layer is between the copper layer and the solder layer.3. The chip package of claim 1 , wherein the substrate is an interposer.4. The chip package of claim 1 , wherein the plurality of bump structures are divided into two or more zones and bump structures in each of the two or more zones have substantially the same width.5. The chip package of claim 4 , wherein the bump structures near the edge of the chip package are in one zone of the two or more zones claim 4 , and wherein the bump structures near the center of the chip package are in another zone of the two or more zones.6. The chip package of claim 1 , wherein the plurality of bump structures are formed by bonding bumps on the chip package with bumps on the substrate.7. The chip package of claim 1 , wherein the plurality of bump structures include copper ...

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Номер записи: 151
12-09-2013 дата публикации

SURFACE METAL WIRING STRUCTURE FOR AN IC SUBSTRATE

Номер: US20130233601A1
Автор: Chiou Wen-Chih, Huang Cheng-Lin, Kao Chin-Fu, Lin Jing-Cheng, Tsai Po-Hao
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A surface metal wiring structure for a substrate includes one or more functional μbumps formed of a first metal and an electrical test pad formed of a second metal for receiving an electrical test probe and electrically connected to the one or more functional μbumps. The surface metal wiring structure also includes a plurality of sacrificial μbumps formed of the first metal that are electrically connected to the electrical test pads, where the sacrificial μbumps are positioned closer to the electrical test pad than the one or more functional μbumps. 1. A surface metal wiring structure for a substrate comprising:one or more functional μbumps formed of a first metal;an electrical test pad formed of a second metal for receiving an electrical test probe and electrically connected to the one or more functional μbumps, wherein the first and second metal are different;a plurality of sacrificial μbumps formed of the first metal and electrically connected to the electrical test pads, wherein the sacrificial μbumps are positioned closer to the electrical test pad than the one or more functional μbumps.2. The surface metal wiring structure according to claim 1 , wherein the first metal is copper.3. The surface metal wiring structure according to claim 1 , wherein the second metal is aluminum or an aluminum alloy.4. The surface metal wiring structure according to claim 1 , wherein the sacrificial μbumps are positioned closer to the electrical test pad than the one or more functional μbumps by about 3% to 97%.5. The surface metal wiring structure according to claim 1 , wherein the sacrificial μbumps are positioned closer to the electrical test pad than the one or more functional μbumps by about 70%.6. The surface metal wiring structure according to claim 1 , further wherein each of the plurality of sacrificial μbumps has up to 10% larger surface area than the one or more functional μbumps.7. The surface metal wiring structure according to claim 1 , further wherein each of the ...

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Номер записи: 152
19-09-2013 дата публикации

Packaging Methods, Material Dispensing Methods and Apparatuses, and Automated Measurement Systems

Номер: US20130244346A1
Автор: Chien Rhone Wang, Chih-Chiang Chang, Chih-Wei Lai, Jing-Cheng Lin, Kewei Zuo
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Packaging methods, material dispensing methods and apparatuses, and automatic measurement systems are disclosed. In one embodiment, a method of packaging semiconductor devices includes coupling a second die to a top surface of a first die, dispensing a first amount of underfill material between the first die and the second die, and capturing an image of the underfill material. Based on the image captured, a second amount or no additional amount of underfill material is dispensed between the first die and the second die.

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Номер записи: 153
19-09-2013 дата публикации

UNDERFILL CURING METHOD USING CARRIER

Номер: US20130244378A1
Автор: Hung Jui-Pin, Kao Chin-Fu, Lin Jing-Cheng, Lu Szu Wei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method includes bonding a carrier over a top die. The method further includes curing an underfill disposed between a substrate and the top die. The method further includes applying a force over the carrier during the curing. The method further includes removing the carrier from the top die. 1. A method , comprising:bonding a carrier over a top die;curing an underfill disposed between a substrate and the top die;applying a force over the carrier during the curing; andremoving the carrier from the top die.2. The method of claim 1 , wherein a coefficient of thermal expansion (CTE) of the carrier is greater than a CTE of the substrate.3. The method of claim 1 , further comprising dispensing the underfill between the top die and the substrate.4. The method of claim 1 , further comprising forming an adhesive layer over the top die or under the carrier.5. The method of claim 4 , further comprising cleaning the adhesive layer after removing the carrier from the top die.6. The method of claim 5 , wherein the cleaning is performed using a wet clean process.7. The method of claim 4 , wherein the adhesive layer is peeled off using a wafer tape after removing the carrier from the top die.8. The method of claim 1 , further comprising applying a release layer to the carrier.9. The method of claim 8 , wherein the release layer comprises a light to heat conversion (LTHC) material.10. The method of claim 8 , further comprising decomposing the release layer using a laser prior to removing the carrier.11. The method of claim 1 , wherein the force ranges from about 1000 N to about 8000 N.12. The method of claim 1 , wherein the curing is performed at a temperature ranging from about 80° C. to about 200° C.13. The method of claim 1 , wherein the curing is performed for a time period ranging from about 30 minutes to about 20 hours.14. A method claim 1 , comprising:bonding a carrier over a top die;dispensing an underfill between the top die and a substrate wherein a coefficient of thermal ...

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Номер записи: 154
26-09-2013 дата публикации

Probing Chips during Package Formation

Номер: US20130249532A1
Автор: Jing-Cheng Lin, Szu Wei Lu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method includes bonding a first package component on a first surface of a second package component, and probing the first package component and the second package component from a second surface of the second package component. The step of probing is performed by probing through connectors on the second surface of the second package component. The connectors are coupled to the first package component. After the step of probing, a third package component is bonded on the first surface of the second package component.

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Номер записи: 155
17-10-2013 дата публикации

Methods for Forming Silicon-Based Hermetic Thermal Solutions

Номер: US20130270690A1
Автор: Hsieh Cheng-Chieh, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method includes forming a first oxide layer on a surface of an integrated heat spreader, and forming a second oxide layer on top surfaces of fins, wherein the fins are parts of a heat sink. The integrated heat spreader is bonded to the heat sink through the bonding of the first oxide layer to the second oxide layer. 1. A method comprising:forming a first oxide layer on a surface of an integrated heat spreader;forming a second oxide layer on top surfaces of fins, wherein the fins are parts of a heat sink; andbonding the integrated heat spreader to the heat sink by bonding the first oxide layer to the second oxide layer.2. The method of further comprising attaching a die to the heat sink through an adhesive claim 1 , wherein the adhesive is attached to a bottom surface of the heat sink claim 1 , with the bottom surface being opposite to the top surfaces of the fins.3. The method of claim 2 , wherein the step of forming the second oxide layer is performed after the die is attached to the heat sink.4. The method of claim 1 , wherein the heat sink comprises a plurality of trenches interconnected to each other and separated by the fins claim 1 , wherein the integrated heat spreader seals the plurality of trenches claim 1 , and wherein the method further comprises forming holes in the integrated heat spreader and connected to the plurality of trenches.5. The method of further comprising installing pipes on the integrated heat spreader claim 4 , wherein inner spaces of the pipes are connected to the plurality of trenches.6. The method of claim 4 , wherein the step of forming the first oxide layer comprises:forming the first oxide layer as a blanket layer on the surface of the integrated heat spreader; andpatterning the first oxide layer, wherein after the step of bonding the integrated heat spreader to the heat sink, portions of the surface of the integrated heat spreader are exposed to the plurality of trenches, with no portion of the first oxide layer therebetween.7. ...

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Номер записи: 156
31-10-2013 дата публикации

Apparatus For Dicing Interposer Assembly

Номер: US20130285241A1
Автор: Lin Jing-Cheng, Lu Szu Wei, Wang Chung Yu, Wu Chih-Wei, Yeh Kung-Chen
Принадлежит:

Apparatus for performing dicing of die on wafer interposers. Apparatuses are disclosed for use with the methods of dicing an interposer having integrated circuit dies mounted thereon. An apparatus includes a wafer carrier mounted in a frame and having a size corresponding to a silicon interposer, a fixture mounted to the wafer carrier and comprising a layer of material to provide mechanical support to the die side of the silicon interposer, the fixture being patterned to fill spaces between integrated circuit dies mounted on an interposer; and an adhesive tape disposed on a surface of the fixture for adhering to the surface of a silicon interposer. Additional alternative apparatuses are disclosed. 1. An apparatus , comprising:a plurality of integrated circuit dies mounted on a die side surface of an interposer, the integrated circuit dies having gaps between them;external connectors mounted on an opposite side of the interposer; andspacers disposed in the gaps between the integrated circuit dies on the die side of the interposer.2. The apparatus of claim 1 , further comprising a tape layer between the spacers and the interposer.3. The apparatus of claim 1 , wherein the interposer is one selected from the group consisting of a silicon substrate and a glass substrate.4. The apparatus of claim 3 , wherein the interposer further comprises through silicon vias extending from the die side surface to an opposite surface of the interposer.5. The apparatus of claim 1 , wherein the interposer further comprises a plurality of board level connections formed on a surface on a surface of the interposer opposite the die side surface.6. The apparatus of claim 5 , wherein the plurality of board level connections further comprises a plurality of solder balls.7. The apparatus of claim 6 , wherein the plurality of board level connections further comprises copper posts.8. The apparatus of claim 7 , wherein the copper posts further comprise a plating on an exterior surface.9. The ...

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Номер записи: 157
31-10-2013 дата публикации

Through Silicon Via with Embedded Barrier Pad

Номер: US20130285244A1
Автор: Chen Yen-Hung, Chiou Wen-Chih, Lin Jing-Cheng, LIN Yung-Chi, Lo Sylvia
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A system and method are disclosed for providing a through silicon via (TSV) with a barrier pad deposited below the top surface of the TSV, the top surface having reduced topographic variations. A bottom TSV pad is deposited into a via and then polished so the top surface is below the substrate top surface. A barrier pad is then deposited in the via, and a top TSV pad deposited on the barrier pad. The top TSV barrier pad is polished to bring the top surface of the top TSV pad about level with the substrate. The barrier pad may be less than about 1 microns thick, and the top TSV pad may be less than about 6 microns thick. The barrier pad may be a dissimilar metal from the top and bottom TSV pads, and may be selected from a group comprising titanium, tantalum, cobalt, nickel and the like. 1. An embedded interconnect apparatus comprising:an electrically insulating substrate having a plurality of vias disposed therein;a bottom through silicon via (TSV) pad disposed within a via and filling the length and width of the via;a barrier pad disposed on the top surface of the bottom TSV pad, the top surface of the barrier pad below the target surface of the substrate and the barrier pad; and wherein the top TSV pad has a thickness associated with predetermined maximum surface topography variation; and', 'wherein the barrier pad has a thickness sufficient to prevent the bottom TSV pad from affecting the crystal growth of a top TSV section, and having sufficient thinness to prevent barrier pad surface topography variations greater than a predetermined size., 'a top TSV pad disposed on the top surface of the barrier pad;'}2. The apparatus of claim 1 , wherein the barrier pad material is selected from a group consisting of tantalum claim 1 , titanium claim 1 , cobalt claim 1 , nickel.3. The apparatus of claim 2 , wherein the bottom TSV pad is copper.4. The apparatus of claim 1 , wherein the barrier pad has a thickness less than about 1 micron.5. The apparatus of claim 1 , wherein ...

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Номер записи: 158
21-11-2013 дата публикации

WAFER-LEVEL PACKAGING MECHANISMS

Номер: US20130307143A1
Автор: Hung Jui-Pin, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

The embodiments of mechanisms of wafer-level packaging (WLP) described above utilize a planarization stop layer to determine an end-point of the removal of excess molding compound prior to formation of redistribution lines (RDLs). Such mechanisms of WLP are used to implement fan-out and multi-chip packaging. The mechanisms are also usable to manufacture a package including chips (or dies) with different types of external connections. For example, a die with pre-formed bumps can be packaged with a die without pre-formed bumps. 19-. (canceled)10. A method of forming a semiconductor package , comprising:providing a carrier with an adhesive layer disposed thereon;providing a die comprising a substrate, wherein a plurality of bond pads are formed over the substrate, and wherein a planarization stop layer is formed over the plurality of bond pads;placing the die on the adhesive layer;forming a molding compound to cover the die, wherein the molding compound surrounds the die;planarizing the molding compound until the planarization stop layer is exposed;removing the planarization stop layer; andforming redistribution lines over the die, wherein the redistribution lines electrically connect to the at least one of the plurality of bond pads.11. The method of claim 10 , wherein the planarization stop layer has a thickness in a range from about 5 μm to about 100 μm.12. The method of claim 10 , wherein the planarization stop layer has a first planarization rate lower than a second planarization rate of the molding compound during the performance of the planarizing the molding compound.13. The method of claim 10 , wherein an end point of the performance of the planarizing the molding compound is determined by detecting a change in resistance by a planarization tool claim 10 , wherein the change in resistance is caused by lower Young's modulus of the planarization stop layer in comparison to the molding compound.14. The method of claim 10 , wherein the planarization stop layer is ...

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Номер записи: 159
21-11-2013 дата публикации

Three-Dimensional Integrated Circuit (3DIC)

Номер: US20130307149A1
Автор: Jeng Shin-Puu, Lin Jing-Cheng, Lu Szu Wei, Wu Chih-Wei, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

An embodiment 3DIC device includes a semiconductor chip, a die, and a polymer. The semiconductor chip includes a semiconductor substrate, wherein the semiconductor substrate comprises a first edge, and a low-k dielectric layer over the semiconductor substrate. The die is disposed over and bonded to the semiconductor chip. The polymer is molded onto the semiconductor chip and the die. The polymer includes a portion level with the low-k dielectric layer, wherein the portion of the polymer comprises a second edge vertically aligned to the first edge of the semiconductor substrate and a third edge contacting the low-k dielectric layer, wherein the second and the third edges are opposite edges of the portion of the polymer. 1. A device comprising: a semiconductor substrate, wherein the semiconductor substrate comprises a first edge; and', 'a low-k dielectric layer over the semiconductor substrate;, 'a semiconductor chip comprisinga die over and bonded to the semiconductor chip; and a second edge vertically aligned to the first edge of the semiconductor substrate; and', 'a third edge contacting the low-k dielectric layer, wherein the second and the third edges are opposite edges of the portion of the polymer., 'a polymer molded onto the semiconductor chip and the die, wherein the polymer comprises a portion level with the low-k dielectric layer, and wherein the portion of the polymer comprises2. The device of claim 1 , wherein the portion of the polymer comprises an end in physical contact with the semiconductor substrate.3. The device of claim 1 , wherein an interface between the portion of the polymer and the semiconductor substrate is substantially level with a surface of the semiconductor substrate that is directly underlying the low-k dielectric layer.4. The device of claim 1 , wherein an interface between the portion of the polymer and the semiconductor substrate is lower than a surface of the semiconductor substrate that is directly underlying the low-k dielectric ...

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Номер записи: 160
21-11-2013 дата публикации

Embedded 3D Interposer Structure

Номер: US20130309813A1
Автор: Chiou Wen-Chih, Jeng Shin-Puu, Lin Jing-Cheng, Shih Ying-Ching, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump. 1. A method comprising:attaching a first device die onto a top surface of a substrate, wherein a plurality of TSVs extends into an intermediate level of the substrate, with the intermediate level being between the top surface and a bottom surface of the substrate;forming a dielectric layer to cover the first device die and the substrate, with bond pads of the first device die facing up;forming vias extending from a top surface of the dielectric layer into the dielectric layer, wherein the vias are electrically coupled to the bond pads of the first die and the plurality of TSVs;forming a first plurality of metal bumps over and electrically coupled to the vias;grinding a bottom side of the substrate to expose the plurality of TSVs; andforming a second plurality of metal bumps underlying and electrically coupled to the plurality of TSVs.2. The method of claim 1 , wherein the dielectric layer has a flat top surface higher than the bond pads of the first device die claim 1 , and wherein the step of forming the vias comprises etching the dielectric layer.3. The method of further comprising claim 1 , before the step of forming the second plurality of metal bumps claim 1 , bonding a second device die to the first plurality of metal bumps.4. The method of further comprising claim 3 , before the step of forming the second plurality of metal bumps and after the step of bonding the second device die claim 3 , molding the second device die in a molding material.5. The method of claim 3 , wherein the vias comprise a first portion ...

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Номер записи: 161
05-12-2013 дата публикации

Semiconductor Molding Chamber

Номер: US20130323886A1
Автор: Chiou Wen-Chih, Jeng Shin-Puu, Lin Jing-Cheng, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A system and method for a semiconductor molding chamber is disclosed. An embodiment comprises a top molding portion and a bottom molding portion that form a cavity between them into which a semiconductor wafer is placed. The semiconductor molding chamber has a first set of vacuum tubes which hold and fix the position of the semiconductor wafer and a second set of vacuum tubes which evacuate the cavity of extraneous ambient gasses. The encapsulant may then be placed over the semiconductor wafer in order to encapsulate the semiconductor wafer. 1. A method for encapsulating a semiconductor device , the method comprising:providing a semiconductor device with a top surface and a bottom surface;positioning the bottom surface adjacent to a first mold portion;reducing a pressure along the bottom surface to affix the bottom surface to the first mold portion;positioning a second mold portion over the first mold portion and the semiconductor device, the second mold portion and the first mold portion defining a cavity enclosing the semiconductor device;evacuating gasses adjacent to the top surface of the semiconductor device through a first vacuum hole; andapplying an encapsulant to the top surface of the semiconductor device.2. The method of claim 1 , further comprising ejecting the semiconductor device after the applying the encapsulant claim 1 , the ejecting being performed by engaging ejection pins located in the first mold portion.3. The method of claim 1 , wherein a release film is located on the second mold portion.4. The method of claim 1 , wherein the reducing the pressure along the bottom surface is performed by evacuating an ambient atmosphere through a second vacuum hole located through the first mold portion.5. The method of claim 1 , further comprising curing the encapsulant.6. The method of claim 1 , wherein the first mold portion comprises a separation component which separates a first pressure region adjacent to the bottom surface and a second pressure region ...

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Номер записи: 162
12-12-2013 дата публикации

Plating Process and Structure

Номер: US20130330921A1
Автор: Huang Cheng-Lin, Kao Chin-Fu, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another embodiment a blocking structure may be inserted between the contact and the test pad. In yet another embodiment a blocking layer may be inserted into a contact stack. Once the blocking material, the blocking structure, or the blocking layer have been formed, the contact may be plated, with the blocking material, the blocking structure, or the blocking layer reducing or preventing degradation of the test pad due to galvanic effects. 1. A method of manufacturing a semiconductor device , the method comprising:forming at least one via over a substrate;forming a contact on the substrate, the contact comprising a first material with a first reduction potential, the first reduction potential being at a first end of a range of reduction potentials; andforming a test pad on the substrate, wherein the at least one via is located in an electrical pathway between the contact and the test pad, the test pad comprising a second material with a second reduction potential different from the first reduction potential, the second reduction potential being at a second end of the range of reduction potentials, wherein the at least one via comprises a third material with a third reduction potential outside of the range of reduction potentials.2. The method of claim 1 , wherein the third reduction potential is greater than the second reduction potential.3. The method of claim 1 , wherein the third reduction potential is lower than the first reduction potential.4. The method of claim 1 , wherein the first material comprises copper and the second material comprises aluminum.5. The method of claim 4 , wherein the third material comprises magnesium.6. The method of claim 4 , wherein the third material comprises platinum.7. The method of claim 1 , further comprising forming a redistribution line over the ...

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Номер записи: 163
19-12-2013 дата публикации

Reconfigurable Guide Pin Design for Centering Wafers Having Different Sizes

Номер: US20130334832A1
Автор: Chang Hsin, Chen Hsin-Yu, Chiou Wen-Chih, Jeng Shin-Puu, Lin Jing-Cheng, Tsai Fang Wen, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

An apparatus includes a robot arm, and a plurality of guide pins mounted on the robot arm. Each of the plurality of guide pins includes a plurality of wafer supports at different levels, with each of the plurality of wafer supports configured to support and center a wafer having a size different from wafers configured to be supported and centered by remaining ones of the plurality of wafer supports 1. An apparatus comprising:a robot arm; anda plurality of guide pins mounted on the robot arm, wherein each of the plurality of guide pins comprises a plurality of wafer supports at different levels, with each of the plurality of wafer supports configured to support and center a wafer having a size different from wafers configured to be supported and centered by remaining ones of the plurality of wafer supports.2. The apparatus of claim 1 , wherein each of the plurality of guide pins comprises a slanted portion and parallel portions not vertical to the slanted portion claim 1 , with the parallel portions attached to the slanted portion.3. The apparatus of claim 1 , wherein upper ones of the plurality of wafer supports are configured to support and center wafers having greater diameters than lower ones of the plurality of wafer supports.4. The apparatus of claim 1 , wherein the robot arm is a part of process robot arm (PRA) module.5. The apparatus of claim 1 , wherein the robot arm comprises arc arms claim 1 , and wherein two of the plurality of guide pins are secured onto the arc arms of the robot arm.6. The apparatus of further comprising:a base, wherein at least one of the plurality of guide pins is mounted to the base, and wherein the arc arms are attached to the base.7. The apparatus of claim 1 , wherein each of the plurality of guide pins comprises:a wafer supporting portion configured to support a wafer, the wafer supporting portion having a top surface parallel to a major surface of the wafer;a slanted portion attached to the wafer supporting portion, the slanted ...

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Номер записи: 164
02-01-2014 дата публикации

3DIC Stacking Device and Method of Manufacture

Номер: US20140001645A1
Автор: Lin Jing-Cheng, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A system and method for stacking semiconductor devices in three dimensions is provided. In an embodiment two or more semiconductor dies are attached to a carrier and encapsulated. Connections of the two or more semiconductor dies are exposed, and the two or more semiconductor dies may be thinned to form connections on an opposite side. Additional semiconductor dies may then be placed in either an offset or overhanging position. 1. A method for forming a device comprising:placing one or more bottom dies on a first carrier wafer;forming a first molding compound between the one or more bottom dies such that electrical contacts on the one or more bottom dies are exposed;attaching the one or more bottom dies and the first molding compound to a second carrier wafer;thinning the one or more bottom dies to expose through vias formed through the one or more bottom dies;forming electrical contacts to the through vias along a backside of the one or more bottom dies; andattaching one or more top dies to the one or more bottom dies.2. The method of claim 1 , wherein the first molding compound covers a bottom side of the one or more bottom dies.3. The method of claim 1 , wherein the forming a first molding compound comprises thinning the first molding compound to expose the electrical contacts on the one or more bottom dies.4. The method of claim 1 , further comprising forming a redistribution layer formed over the one or more bottom dies.5. The method of claim 4 , wherein the redistribution layer extends over the first molding compound.6. The method of claim 1 , further comprising a second molding compound formed over the one or more top dies.7. A method of manufacturing a semiconductor device claim 1 , the method comprising:attaching a first semiconductor die to a carrier, the first semiconductor die comprising first external contacts;attaching a second semiconductor die to the carrier, the second semiconductor die comprising second external contacts;encapsulating the first ...

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Номер записи: 165
09-01-2014 дата публикации

System and Method for Through Silicon Via Yield

Номер: US20140011301A1
Автор: Lin Jing-Cheng, Liu Yen-Hsin, Wang Chien Rhone, Yu Chen-Hua, Zuo Kewei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

The present disclosure provides one embodiment of an integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features. The IC fabrication method includes performing a plurality of processing steps; collecting physical metrology data from the plurality of processing steps; collecting virtual metrology data from the plurality of processing steps based on the physical metrology data; generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; and identifying an action at an earlier processing step based on the yield prediction. 1. An integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features , comprising:performing a plurality of processing steps;collecting physical metrology data from the plurality of processing steps;collecting virtual metrology data from the plurality of processing steps based on the physical metrology data;generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; andidentifying an action at an earlier processing step based on the yield prediction.2. The IC fabrication method of claim 1 , wherein the action includes one selected from a group consisting of scraping claim 1 , rework claim 1 , feeding-forward to a later processing step claim 1 , feeding-back to tune processing parameters of an earlier processing step claim 1 , marking a failed die claim 1 , and combination thereof.3. The IC fabrication method of claim 2 , wherein the plurality of processing steps include via etching claim 2 , grinding claim 2 , and recessing.4. The IC fabrication method of claim 3 , wherein:the earlier processing step includes the via etching; andthe later processing step includes one of the grinding and the recessing.5. The IC fabrication method of claim 3 , wherein the rework includes performing another via etching process.6. The IC ...

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Номер записи: 166
30-01-2014 дата публикации

CIS Chips and Methods for Forming the Same

Номер: US20140027872A1
Автор: Chiou Wen-Chih, Lin Jing-Cheng, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A device includes a semiconductor substrate, an image sensor at a front surface of the semiconductor substrate, and a plurality of dielectric layers over the image sensor. A color filter and a micro lens are disposed over the plurality of dielectric layers and aligned to the image sensor. A through via penetrates through the semiconductor substrate. A Redistribution Line (RDL) is disposed over the plurality of dielectric layers, wherein the RDL is electrically coupled to the through via. A polymer layer covers the RDL. 1. A device comprising:a semiconductor substrate;an image sensor at a front surface of the semiconductor substrate;a plurality of dielectric layers over the image sensor;a through via penetrating through the semiconductor substrate;a first Redistribution Line (RDL) over the plurality of dielectric layers, wherein the RDL is electrically coupled to the through via; anda polymer layer covering the first RDL.2. The device of claim 1 , wherein the polymer layer contacts a top surface and sidewalls of the first RDL.3. The device of claim 1 , wherein the polymer layer comprises a photo sensitive polymer.4. The device of further comprising:a micro lens over the plurality of dielectric layer; andan oxide layer over the micro lens.5. The device of claim 4 , wherein the oxide layer further comprises portions on a top surface of the polymer layer.6. The device of claim 4 , wherein the polymer layer is free from portions overlapping the micro lens.7. The device of claim 1 , wherein the through via further penetrates through the plurality of dielectric layers claim 1 , and wherein a top end of the through via contacts the first RDL8. The device of further comprising:a second RDL on a backside of the semiconductor substrate; andan electrical connector on the backside of the semiconductor substrate, wherein the electrical connector is electrically coupled to the second RDL and the through via.9. A device comprising:a semiconductor substrate;an image sensor array at ...

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Номер записи: 167
06-02-2014 дата публикации

SOLDER BUMP FOR BALL GRID ARRAY

Номер: US20140035135A1
Автор: Chang Jung-Hua, Huang Cheng-Lin, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1. 1. A solder bump structure for a ball grid array (BGA) , comprising:at least one under bump metal (UBM) layer;a solder bump formed over the at least one UBM layer, the solder bump having a bump width and a bump height, wherein a ratio of the bump height over the bump width is less than 1;at least one non-metallic core inside the solder bump; anda conductive layer surrounding the at least one non-metallic core, wherein the solder bump surrounds the conductive layer.2. (canceled)3. (canceled)4. The structure of claim 1 , wherein the at least one non-metallic core comprises plastic.5. The structure of claim 1 , further comprising a copper layer between the at least one UBM layer and the solder bump.6. The structure of claim 1 , wherein the solder bump is lead-free.7. The structure of claim 1 , wherein the at least one UBM layer comprises a first layer and a second layer.8. The structure of claim 7 , wherein the first layer comprises Ti claim 7 , W claim 7 , Cr claim 7 , TiW claim 7 , or any combination thereof.9. The structure of claim 7 , wherein the second layer comprises Cu claim 7 , Ni claim 7 , Ni—V alloy claim 7 , or any combination thereof.10. A method of forming a solder bump structure for a ball grid array (BGA) claim 7 , comprising:forming at least one under bump metal (UBM) layer over a substrate;forming a solder bump over the at least one UBM layer, wherein the solder bump has a bump width and a bump height and a ratio of the bump height over the bump width is less than 1; and placing the non-metallic core atop the solder bump; and', 'reflowing the solder bump., 'forming at least one non-metallic core inside the solder bump, wherein forming the at least one non-metallic core ...

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Номер записи: 168
06-02-2014 дата публикации

Apparatus and Methods for Molding Die on Wafer Interposers

Номер: US20140038360A1
Автор: Lin Jing-Cheng, Lu Szu Wei, Wang Chung Yu, Wu Chih-Wei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits. 1. A method , comprising:forming through vias in a wafer having a die side and an opposite side;mounting a plurality of integrated circuit dies on the die side of the wafer, the integrated circuit dies having gaps adjacent ones of the plurality of integrated circuit dies;molding the plurality of integrated circuit dies and the die side of the wafer with a mold compound;dicing the mold compound to form at least one stress relief trench extending into the mold compound in at least one of the gaps; anddispensing stress relief material different from the mold compound into the at least one stress relief trench to form at least one stress relief feature.2. The method of claim 1 , and further comprising:performing a top grind operation on the mold compound until a top surface of at least one of the integrated circuit dies is exposed.3. The method of claim 1 , and further comprising:performing a backgrind operation on the opposite side of the wafer to thin the wafer to a thickness less than 200 microns.4. The method of claim 1 , wherein dispensing the stress relief material ...

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Номер записи: 169
06-02-2014 дата публикации

Packaging Structures and Methods with a Metal Pillar

Номер: US20140038405A1
Автор: Chen-Hua Yu, Cheng-chieh Hsieh, Cheng-Lin Huang, Jing-Cheng Lin, Kuo-Ching Hsu, Po-Hao Tsai, Shang-Yun Hou, Shin-puu Jeng, Ying-Ching Shih
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

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Номер записи: 170
27-02-2014 дата публикации

Carrier Warpage Control for Three Dimensional Integrated Circuit (3DIC) Stacking

Номер: US20140057391A1
Автор: Lin Jing-Cheng, Lin Shih Ting, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate. 1. A method of forming a package-on-package (PoP) device , comprising:temporarily mounting a substrate on a carrier;stacking a first die on the substrate, at least one of the first die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier; andstacking a second die on the first die.2. The method of claim 1 , wherein the substrate is formed from one of an organic substrate claim 1 , a ceramic substrate claim 1 , a silicon substrate claim 1 , a glass substrate claim 1 , and a laminate substrate.3. The method of claim 1 , wherein the substrate is formed from one of an epoxy and a resin.4. The method of claim 1 , further comprising temporarily mounting the substrate on the carrier using glue.5. The method of claim 1 , further comprising horizontally offsetting the second die relative to the first die to provide the second die with an overhang.6. The method of claim 1 , further comprising performing a pressure anneal on the substrate using a pressure anneal cap prior to the first and second dies being stacked.7. The method of claim 1 , further comprising flowing an underfill material between the first die and the substrate only.8. The method of claim 1 , further comprising flowing an underfill material between the first die and the second die only.9. The method of claim 1 , further comprising forming a molding material over exposed portions of the organic substrate claim 1 , the first die claim 1 , and the second die.10. The method of claim 1 , further comprising ...

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Номер записи: 171
06-03-2014 дата публикации

THREE DIMENSIONAL (3D) FAN-OUT PACKAGING MECHANISMS

Номер: US20140061888A1
Автор: Chang Chin-Chuan, Hung Jui-Pin, Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

The mechanisms of forming a semiconductor device package described above provide a low-cost manufacturing process due to the relative simple process flow. By forming an interconnecting structure with a redistribution layer(s) to enable bonding of one or more dies underneath a package structure, the warpage of the overall package is greatly reduced. In addition, interconnecting structure is formed without using a molding compound, which reduces particle contamination. The reduction of warpage and particle contamination improves yield. Further, the semiconductor device package formed has low form factor with one or more dies fit underneath a space between a package structure and an interconnecting structure. 1. A semiconductor package comprising:an interconnecting structure, wherein the interconnecting structure includes a redistribution layer (RDL);a semiconductor die bonded to the interconnecting structure by a first plurality of bonding structures, wherein the RDL of the interconnecting layer enables fan-out connection of the semiconductor die; anda package structure bonded to the interconnecting structure by a second plurality of bonding structures, wherein the semiconductor die is placed in a space between the package structure and the interconnecting structure.2. The semiconductor package of claim 1 , the interconnecting structure includes conductive structures surrounded by one or more dielectric layers.3. The semiconductor package of claim 2 , wherein the one of more dielectric layers are made of photo-sensitive polymers.4. The semiconductor package of claim 1 , wherein the interconnecting structure has a thickness equal to or less than about 30 μm.5. The semiconductor package of claim 1 , wherein a total thickness of the interconnecting structure and the package structure covered with a molding layer is in a range from about 350 μm to about 1050 μm.6. The semiconductor package of claim 1 , wherein a distance between a first surface of the package structure ...

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Номер записи: 172
06-03-2014 дата публикации

Bump Structures for Semiconductor Package

Номер: US20140061897A1
Автор: Lin Jing-Cheng, Tsai Po-Hao
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A package structure includes a first substrate bonded to a second substrate by connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a second metal pillar is formed overlying a passivation layer in a second region of the first substrate. A first solder joint region is formed between metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The thickness of the first metal pillar is greater than the thickness of the second metal pillar. 1. A package structure , comprising:a first substrate having a first region and a second region and comprising a metal pad overlying the first substrate in the first region, a first metal pillar overlying the metal pad, a passivation layer overlying the first substrate in the second region, and a second metal pillar overlying the passivation layer in the second region; anda second substrate comprising a first connector and a second connector,wherein the first substrate is bonded to the second substrate, in which a first solder joint region is formed between the first metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector; andwherein the thickness of the first metal pillar is greater than the thickness of the second metal pillar.2. The package structure of claim 1 , wherein the thickness of the second solder joint region is greater than the thickness of the first solder joint region.3. The package structure of claim 1 , wherein the thickness of the second solder joint region is substantially equal to the thickness of the first solder joint region.4. The package structure of claim 1 , wherein the passivation layer is formed overlying the first substrate in the first region and comprises at least one opening exposing ...

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Номер записи: 173
27-03-2014 дата публикации

Thermal Dissipation Through Seal Rings in 3DIC Structure

Номер: US20140084444A1
Автор: Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer. 1. A package comprising: a first semiconductor substrate;', 'a first plurality of through-vias penetrating through the first semiconductor substrate;', 'a first seal ring overlapping and connected to the first plurality of through-vias; and', 'a first plurality of electrical connectors underlying the semiconductor substrate and connected to the first seal ring;, 'a first die comprising a substrate; and', 'a plurality of metal lines over the substrate, wherein the plurality of metal lines is electrically coupled to the first plurality of electrical connectors, and wherein each of the plurality metal lines comprises a first portion overlapped by the first die, and a second portion misaligned with the first die; and, 'an interposer underlying and bonded to the first die, wherein the interposer comprisesa thermal conductive block encircling the first die, wherein the thermal conductive block is mounted on the plurality of metal lines of the interposer.2. The package of further comprising a thermal conductive adhesive layer claim 1 , wherein the thermal conductive adhesive layer comprises:a first portion overlapping the first die; anda second portion over and contacting a top ...

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Номер записи: 174
27-03-2014 дата публикации

Thermal Dissipation Through Seal Rings in 3DIC Structure

Номер: US20140084445A1
Автор: Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A heat spreader encircles the die and the interposer. A wire includes a first end bonded to one of the plurality of metal lines, and a second end bonded to the heat spreader. 1. A package comprising: a first semiconductor substrate;', 'a first plurality of through-vias penetrating through the first semiconductor substrate;', 'a first seal ring overlapping and connected to the first plurality of through-vias; and', 'a first plurality of electrical connectors underlying the semiconductor substrate and connected to the first seal ring; and, 'a first die comprising a seal-ring-comprising thermal path comprising a substrate; and', 'a plurality of metal lines over the substrate, wherein the plurality of metal lines is electrically coupled to the first plurality of electrical connectors of the first die, and wherein each of the plurality metal lines comprises a first portion overlapped by the first die, and a second portion misaligned with the first die;, 'an interposer underlying and bonded to the first die, wherein the interposer comprisesa first heat spreader encircling the first die and the interposer; anda wire comprising a first end bonded to one of the plurality of metal lines, and a second end bonded to the first heat spreader.2. The package of further comprising a thermal conductive ...

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Номер записи: 175
27-03-2014 дата публикации

Thermal Dissipation Through Seal Rings in 3DIC Structure

Номер: US20140084476A1
Автор: Lin Jing-Cheng, Syu Shih-Yi
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via. 1. A package comprising: a first semiconductor substrate;', 'a first through-via penetrating through the first semiconductor substrate;', 'a first seal ring overlying and connected to the first through-via; and', 'a first electrical connector underlying the semiconductor substrate and electrically coupled to the first seal ring through the first through-via., 'a first die comprising2. The package of further comprising:a polymer layer at a top surface of the first die; anda second electrical connector overlying and electrically coupled to the first seal ring, wherein a top surface of the electrical connector is higher than a top surface of the polymer layer.3. The package of further comprising a second die overlying and bonded to the first die claim 2 , wherein the second die comprises:a second semiconductor substrate;a second through-via penetrating through the second semiconductor substrate;a second seal ring overlying and electrically connected to the second through-via; anda third electrical connector underlying the semiconductor substrate and electrically coupled to the second seal ring through the second through-via, wherein the third electrical connector is bonded to the second electrical connector.4. The package of further comprising a plurality of electrical connectors overlying and electrically coupled to the first seal ring claim 1 , wherein the plurality of electrical connectors are aligned to the first seal ring claim 1 , and are distributed with a substantially uniform pitch.5. The package of further comprising a package component underlying and bonded to the first claim 1 , die claim 1 , wherein the package component comprises:a metal line comprising a first ...

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Номер записи: 176
07-01-2016 дата публикации

Fan-Out Package and Methods of Forming Thereof

Номер: US20160005702A1
Автор: Huang Cheng-Lin, Lin Jing-Cheng, LIU Nai-Wei, SHIH Wan-Ting
Принадлежит:

An embodiment is a package including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound and the chip and has a first opening exposing the contact pad. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer fills the first opening. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer and has a second opening over the first opening. A second metallization layer is formed overlying the second dielectric layer and formed in the second opening. 1. A package comprising:a chip comprising a substrate and a contact pad on the substrate;a molding compound laterally encapsulating the chip;a first dielectric layer overlying the molding compound and the chip and having a first opening exposing the contact pad;a first metallization layer overlying the first dielectric layer, wherein the first metallization layer fills the first opening and laterally extends over the molding compound;a second dielectric layer overlying the first metallization layer and the first dielectric layer and having a second opening over the first opening; anda second metallization layer overlying the second dielectric layer and electrically coupled to the first metallization layer through the second opening and laterally extends over the molding compound.2. The package of claim 1 , wherein the second metallization layer is formed in the second opening and physically contacts the first metallization layer.3. The package of claim 1 , wherein the second metallization layer lines a sidewall and a bottom of the second opening.4. The package of claim 1 , wherein the first metallization layer comprises a first seed layer and a first conductive layer formed on the first seed layer.5. The package of claim 4 , wherein the first seed layer comprises titanium and the first conductive layer comprises copper.6. The package ...

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Номер записи: 177
07-01-2021 дата публикации

Integrated circuit packages and methods of forming same

Номер: US20210005464A1
Автор: Jing-Cheng Lin, Li-Hui Cheng, Po-Hao Tsai
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An integrated circuit package and a method of forming the same are provided. A method includes forming a conductive column over a carrier. An integrated circuit die is attached to the carrier, the integrated circuit die being disposed adjacent the conductive column. An encapsulant is formed around the conductive column and the integrated circuit die. The carrier is removed to expose a first surface of the conductive column and a second surface of the encapsulant. A polymer material is formed over the first surface and the second surface. The polymer material is cured to form an annular-shaped structure. An inner edge of the annular-shaped structure overlaps the first surface in a plan view. An outer edge of the annular-shaped structure overlaps the second surface in the plan view.

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Номер записи: 178
04-01-2018 дата публикации

METHOD FOR FORMING HYBRID BONDING WITH THROUGH SUBSTRATE VIA (TSV)

Номер: US20180005977A1
Автор: Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A method for forming a semiconductor device structure and method for forming the same are provided. The method includes hybrid bonding a first wafer and a second wafer to form a hybrid bonding structure, and the hybrid bonding structure comprises a metallic bonding interface and a polymer-to-polymer bonding structure. The method includes forming at least one through-substrate via (TSV) through the second wafer, and the TSV extends from a bottom surface of the second wafer to a top surface of the first wafer. 1. A method for forming a semiconductor device structure , comprising:hybrid bonding a first wafer and a second wafer to form a hybrid bonding structure, wherein the hybrid bonding structure comprises a metallic bonding interface and a polymer-to-polymer bonding structure; andforming at least one through-substrate via (TSV) through the second wafer, wherein the TSV extends from a bottom surface of the second wafer to a top surface of the first wafer.2. The method as claimed in claim 1 , further comprising:forming an interconnect structure over the bottom surface of the second wafer after forming the TSV, wherein the interconnect structure is electrically connected to a metallization structure of the first wafer.3. The method as claimed in claim 1 , wherein hybrid bonding the first wafer and the second wafer comprises:bonding a first conductive material of the first wafer to a second conductive material of the second wafer.4. The method as claimed in claim 3 , wherein hybrid bonding the first wafer and the second wafer further comprises:bonding a first polymer material of the first wafer to a second polymer material of the second wafer.5. The method as claimed in claim 1 , wherein hybrid bonding the first wafer and the second wafer further comprises:heating the first wafer and the second wafer to a first temperature such that the first polymer material and the second polymer material are intermixed; andheating the first wafer and the second wafer to a second ...

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Номер записи: 179
04-01-2018 дата публикации

SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Номер: US20180006005A1
Автор: CHENG Li-Hui, Lin Jing-Cheng, Tsai Po-Hao
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process. 1. A semiconductor package comprising:a redistribution layer;at least one die, disposed on the redistribution layer;a molding compound, disposed on the redistribution layer and encapsulating the at least one die;through interlayer vias, disposed on the redistribution layer and penetrating the molding compound, wherein the through interlayer vias are electrically connected to the redistribution layer and the at least one die;a protection film, disposed on the molding compound and the at least one die, wherein the protection film located on the at least one die includes a trench pattern with trenches of substantially flat bottoms;connectors, disposed on the through interlayer vias; andconductive elements, electrically connected to the redistribution layer.2. The semiconductor package as claimed in claim 1 , further comprising a dielectric material layer disposed on the molding compound claim 1 , on the at least one die and disposed between the molding compound claim 1 , the at least one die and the protection film claim 1 , wherein the dielectric material layer exposes the through interlayer vias.3. The semiconductor package as claimed in claim 2 , wherein the dielectric material layer located on the molding compound includes first openings and the connectors located within the first openings are in direct contact with the through interlayer vias.4. The semiconductor package as claimed in claim 3 ...

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Номер записи: 180
02-01-2020 дата публикации

INTEGRATED FAN-OUT PACKAGES AND METHODS OF FORMING THE SAME

Номер: US20200006136A1
Автор: Lee Long Hua, Lin Jing-Cheng, Lu Szu-Wei, Shih Ying-Ching, Wu Chih-Wei
Принадлежит:

A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material. 1. A method of forming a semiconductor device , the method comprising:forming a conductive pillar over a first side of a carrier;attaching a backside of a die to the first side of the carrier;forming a molding material over the first side of the carrier around the die and around the conductive pillar;forming a redistribution structure over the die, the conductive pillar, and the molding material;removing the carrier, wherein after removing the carrier, a first end of the conductive pillar distal to the redistribution structure is exposed;forming a heat sink on the backside of the die; andbonding a semiconductor package to the first end of the conductive pillar, the heat sink being between the semiconductor package and the die.2. The method of claim 1 , wherein forming the heat sink comprises depositing a thermally conductive material on the backside of the die.3. The method of claim 2 , wherein the thermally conductive material has a thermal conductivity between about 100 watts per meter-kelvin (W/(m-k)) and about 400 W/(m-k).4. The method of claim 3 , wherein the thermally conductive material has a heat capacity of about 1700 joules per gram per degree Celsius (J/(g ° C.)) or larger.5. The method of claim 2 , wherein the backside of the die is attached to the first side of the carrier by an adhesive layer claim 2 , wherein forming the heat sink comprises:after removing the carrier, removing the adhesive layer to form a recess in the molding material, the recess exposing the backside of the die; andforming the thermally ...

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Номер записи: 181
02-01-2020 дата публикации

Underfill Structure for Semiconductor Packages and Methods of Forming the Same

Номер: US20200006181A1
Автор: CHEN Yu-Wei, Huang Kuan-Yu, Kuo Li-Chung, Lee Long Hua, Lin Jing-Cheng, Lu Szu-Wei, Shih Ying-Ching
Принадлежит:

A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE. 1. A device comprising: an integrated circuit die;', 'an interposer bonded to the integrated circuit die by a plurality of die connectors; and', 'an encapsulant surrounding the integrated circuit die;, 'a package comprisinga package substrate bonded to the interposer by a plurality of conductive connectors;a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); anda second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.2. The device of claim 1 , wherein the first underfill tapers from the package toward the package substrate.3. The device of claim 2 , wherein the second underfill tapers from the package substrate toward the package.4. The device of claim 1 , wherein the first underfill and the second underfill taper from the package substrate toward the package.5. The device of claim 1 , wherein the first underfill is in contact with the interposer and spaced apart from the encapsulant.6. The device of claim 1 , wherein the second underfill is in contact with the package and spaced apart from the conductive connectors.7. The device of claim 1 , wherein the first underfill has a ...

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Номер записи: 182
02-01-2020 дата публикации

SEMICONDUCTOR PACKAGES

Номер: US20200006196A1
Автор: Lin Jing-Cheng, Lu Szu-Wei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor packages are provided. One of the semiconductor package includes a semiconductor die, a thermal conductive pattern, an encapsulant and a thermal conductive layer. The thermal conductive pattern is disposed aside the semiconductor die. The encapsulant encapsulates the semiconductor die and the thermal conductive pattern. The thermal conductive layer covers a rear surface of the semiconductor die, wherein the thermal conductive pattern is thermally coupled to the semiconductor die through the thermal conductive layer and electrically insulated from the semiconductor die. 1. A semiconductor package , comprising:a semiconductor die;a thermal conductive pattern aside the semiconductor die;an encapsulant, encapsulating the semiconductor die and the thermal conductive pattern; anda thermal conductive layer covering a rear surface of the semiconductor die, wherein the thermal conductive pattern is thermally coupled to the semiconductor die through the thermal conductive layer and electrically insulated from the semiconductor die.2. The semiconductor package as claimed in claim 1 , further comprising a semiconductor device stacked over and electrically connected to the semiconductor die.3. The semiconductor package as claimed in claim 1 , wherein the thermal conductive pattern comprises a plurality of discrete through vias.4. The semiconductor package as claimed in claim 3 , wherein the plurality of discrete through vias are arranged along at least one ring-shaped path surrounding the semiconductor die.5. The semiconductor package as claimed in claim 1 , wherein the thermal conductive pattern comprises a ring-shaped structure surrounding the semiconductor die.6. The semiconductor package as claimed in claim 1 , wherein the thermal conductive pattern comprises a plurality of discrete wall-shaped structures.7. The semiconductor package as claimed in claim 1 , further comprising a redistribution circuit structure disposed over an active surface of the ...

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Номер записи: 183
02-01-2020 дата публикации

Semiconductor Device and Method of Manufacture

Номер: US20200006225A1
Автор: Lin Jing-Cheng, Lu Szu-Wei, Shih Ying-Ching, Tsou Hsien-Ju, WANG Pu, Wu Chih-Wei
Принадлежит:

An integrated fan out package on package architecture is utilized along with de-wetting structures in order to reduce or eliminated delamination from through vias. In embodiments the de-wetting structures are titanium rings formed by applying a first seed layer and a second seed layer in order to help manufacture the vias. The first seed layer is then patterned into a ring structure which also exposes at least a portion of the first seed layer. 1. A semiconductor device comprising:an encapsulant surrounding a semiconductor die and a through via, wherein the through via comprises a conductive material and a seed layer;a conductive material in physical contact with the through via; anda liner ring in between a portion of the conductive material and the through via, the liner ring having outer sidewalls aligned with the through via.2. The semiconductor device of claim 1 , wherein the liner ring comprises a de-wetting material.3. The semiconductor device of claim 2 , wherein the de-wetting material is titanium.4. The semiconductor device of claim 3 , wherein the seed layer comprises copper.5. The semiconductor device of claim 1 , wherein the liner ring has an inner diameter of between about 150 μm and about 200 μm.6. The semiconductor device of claim 1 , wherein the liner ring has an outer diameter of less than about 200 μm.7. The semiconductor device of claim 1 , wherein the liner ring has a thickness of between about 50 Å and about 300 Å.8. A semiconductor device comprising:an encapsulant encapsulating a semiconductor device and a through via, the through via being separated from the semiconductor device by the encapsulant, wherein the through via comprises a first seed layer;a first lining layer adjacent to the encapsulant in a first direction and adjacent to the first seed layer in a second direction different from the first direction, wherein an outer sidewall of the first lining layer has a ring shape; anda conductive material extending through the first lining ...

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Номер записи: 184
02-01-2020 дата публикации

Method of Forming Contact Holes in a Fan Out Package

Номер: US20200006264A1
Автор: Hsu Feng-Cheng, Lin Jing-Cheng, Lu Szu-Wei
Принадлежит:

Methods of forming packages include forming an encapsulant laterally encapsulating a die over an active surface of the die. The active surface has an electrical pad. A first opening is formed through the encapsulant to the electrical pad. In some embodiments the first opening is formed using a photolithographic technique. In some embodiments the first opening is formed using a temporary pillar by forming the temporary pillar over the electrical pad, forming the encapsulant, and then exposing and removing the temporary pillar. A conductive pattern is formed over the encapsulant including a via formed in the first opening to the electrical pad of the die's active surface. In some embodiments, a dielectric layer is formed over the encapsulant, and the conductive pattern is over the dielectric layer. Embodiments may include forming additional dielectric layers and conductive patterns. 1. A method comprising:depositing an encapsulant laterally encapsulating a die and over an active surface of the die, the active surface comprising an electrical pad;forming a first opening in the encapsulant, the first opening exposing the electrical pad;depositing a first dielectric layer over the encapsulant and in the first opening;exposing the first dielectric layer to a patterned light exposure, the patterned light exposure corresponding to a second opening to be formed in the first dielectric layer;developing the first dielectric layer after the patterned light exposure to form the second opening, the second opening being aligned to the first opening, the second opening exposing the electrical pad; anddepositing a first conductive pattern over the first dielectric layer, the first conductive pattern comprising a first via in the first opening and in the second opening electrically coupled to the electrical pad.2. The method of claim 1 , wherein the die includes a pillar disposed on the electrical pad prior to depositing the encapsulant claim 1 , wherein forming the first opening ...

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Номер записи: 185
03-01-2019 дата публикации

Integrated Circuit Packages and Methods of Forming Same

Номер: US20190006194A1
Автор: CHENG Li-Hui, Lin Jing-Cheng, Tsai Po-Hao
Принадлежит:

An integrated circuit package and a method of forming the same are provided. A method includes forming a conductive column over a carrier. An integrated circuit die is attached to the carrier, the integrated circuit die being disposed adjacent the conductive column. An encapsulant is formed around the conductive column and the integrated circuit die. The carrier is removed to expose a first surface of the conductive column and a second surface of the encapsulant. A polymer material is formed over the first surface and the second surface. The polymer material is cured to form an annular-shaped structure. An inner edge of the annular-shaped structure overlaps the first surface in a plan view. An outer edge of the annular-shaped structure overlaps the second surface in the plan view. 1. A method comprising:forming a conductive column over a carrier;attaching an integrated circuit die to the carrier, the integrated circuit die being disposed adjacent the conductive column;forming an encapsulant around the conductive column and the integrated circuit die;removing the carrier to expose a first surface of the conductive column and a second surface of the encapsulant;forming a polymer material over and in physical contact with the first surface and the second surface; andcuring the polymer material to form an annular-shaped structure, wherein an inner edge of the annular-shaped structure overlaps the first surface in a plan view, and wherein an outer edge of the annular-shaped structure overlaps the second surface in the plan view.2. The method of claim 1 , wherein the polymer material comprises a UV curable polymer material.3. The method of claim 2 , wherein curing the polymer material comprises exposing the polymer material to UV light.4. The method of claim 1 , wherein the polymer material comprises a thermally curable polymer material.5. The method of claim 4 , wherein curing the polymer material comprises performing a thermal treatment on the polymer material.6. The ...

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Номер записи: 186
03-01-2019 дата публикации

Release Film as Isolation Film in Package

Номер: US20190006199A1
Автор: Chih-Wei Wu, Hsien-Ju Tsou, Jing-Cheng Lin, Pu Wang, Szu-Wei Lu, Ying-Ching Shih
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method includes forming a release film over a carrier, forming a metal post on the release film, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, decomposing a first portion of the release film to separate a second portion of the release film from the carrier, and forming an opening in the release film to expose the metal post.

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Номер записи: 187
03-01-2019 дата публикации

Release Film as Isolation Film in Package

Номер: US20190006200A1
Автор: CHENG Li-Hui, Lin Jing-Cheng, Tsai Po-Hao
Принадлежит:

A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an encapsulating material, performing a planarization on the encapsulating material to expose the device, detaching the device and the encapsulating material from the carrier, etching the die-attach film to expose a back surface of the device, and applying a thermal conductive material on the back surface of the device. 1. A method comprising:forming a release film over a carrier;attaching a device over the release film through a die-attach film;encapsulating the device in an encapsulating material;performing a planarization on the encapsulating material to expose the device;forming redistribution lines to electrically couple to the device;detaching the device and the encapsulating material from the carrier while the die-attach film remains attached to the device;after the detaching of the device and the encapsulating material from the carrier, removing the die-attach film to expose a back surface of the device; andapplying a thermal conductive material on the back surface of the device.2. The method of further comprising:dispensing an underfill to contact the thermal conductive material.3. The method of claim 1 , wherein after the die-attach film is removed claim 1 , a recess is formed to extend into the encapsulating material claim 1 , and the thermal conductive material is filled into the recess.4. The method of claim 1 , wherein the thermal conductive material has a thermal conductivity higher than about 1 W/k*m.5. The method of claim 1 , wherein the thermal conductive material is selected from the group consisting of solder claim 1 , silver claim 1 , copper paste claim 1 , and combinations thereof.6. The method of further comprising:forming a metal post over the carrier, wherein the metal post is encapsulated in the encapsulating material, wherein in the removing the die-attach film, a portion of the ...

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Номер записи: 188
08-01-2015 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20150008586A1
Автор: Jing-Cheng Lin, Jui-Pin Hung, Long-Hua Lee, Po-Hao Tsai
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor structure includes a molding compound, a conductive plug, and a cover. The conductive plug is in the molding compound. The cover is over a top meeting joint between the conductive plug and the molding compound. The semiconductor structure further has a dielectric. The dielectric is on the cover and the molding compound.

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Номер записи: 189
08-01-2015 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20150008587A1
Автор: Hung Jui-Pin, Lin Jing-Cheng, Tsai Po-Hao
Принадлежит:

A fan-out package includes a molding compound, a conductive plug and a stress buffer. The conductive plug is in the molding compound. The stress buffer is between the conductive plug and the molding compound. The stress buffer has a coefficient of thermal expansion (CTE). The CTE of the stress buffer is between a CTE of the molding compound and a CTE of the conductive plug. A method of manufacturing a three dimensional includes plating a post on a substrate, and disposing a stress buffer on the sidewall of the post. The method further includes surrounding the stress buffer with a molding compound. 1. A fan out package , comprising:a molding compound;a conductive plug in the molding compound; anda stress buffer between the conductive plug and the molding compound, wherein a coefficient of thermal expansion (CTE) of the stress buffer is between a CTE of the molding compound and a CTE of the conductive plug, and the stress buffer is a composite film, and stress buffer layers of the composite film have increasing CTE away from the conductive plug.2. (canceled)3. (canceled)4. The fan out package in claim 1 , wherein a thickness of the stress buffer is between about 0.2 μm and about 5 μm.5. The fan out package in claim 1 , wherein a top surface of the conductive plug is below a top surface of the molding compound.6. The fan out package in claim 1 , wherein a portion of the conductive plug contacts the molding compound.7. The fan out package in claim 1 , further comprising an interconnect over and contacting the conductive plug claim 1 , wherein the interconnect contacts a portion of the top surface of the conductive plug.8. A semiconductor structure claim 1 , comprising:a molding compound;a filled via in the molding compound; and a liner between the molding compound and the filled via, wherein the liner is tin, tungsten, zirconium, gold, palladium, polyimide, ENEPIG, ENEP, or PBO, and the liner is a composite film, and liner layers of the composite film have increasing ...

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Номер записи: 190
08-01-2015 дата публикации

Package Systems Having Interposers

Номер: US20150011051A1
Автор: Lin Jing-Cheng, LIN Yung-Chi, Yu Chen-Hua
Принадлежит:

A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure. 1. A method comprising:providing a first substrate;forming a first interconnect layer on the first substrate;attaching the first interconnect layer to a second substrate;removing the first substrate;forming electrical connections on the first interconnect layer;forming a molding compound over the first interconnect layer, the molding compound encircling each of the electrical connections;forming a second interconnect layer on the molding compound; andremoving the second substrate.2. The method of claim 1 , wherein the forming the electrical connections on the first interconnect layer comprises:forming a patterned layer over the first interconnect layer, the patterned layer having openings;forming a conductive material in the openings; andremoving the patterned layer.3. The method of claim 2 , further comprising forming a conductive seed layer over the first interconnect layer prior to the forming the patterned layer claim 2 , and further comprising removing exposed portions of the conductive seed layer after the removing the patterned layer.4. The method of claim 1 , further comprising attaching a semiconductor substrate between adjacent ones of the electrical connections prior to the forming the molding compound.5. The method of claim 4 , wherein the molding compound extends over the semiconductor substrate.6. The method of claim 1 , further comprising forming external electrical connectors on the first interconnect layer prior to attaching to ...

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Номер записи: 191
12-01-2017 дата публикации

SEMICONDUCTOR PACKAGE DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20170011981A1
Автор: Hung Jui-Pin, Lin Jing-Cheng, LIU Nai-Wei
Принадлежит:

A method of manufacturing a semiconductor device including providing a die, forming a pad on the die, disposing a first polymer over the die, patterning the first polymer with an opening over the pad, disposing a sacrificial layer over the patterned first polymer, disposing a molding surrounding the die, removing a portion of the molding thereby exposing the sacrificial layer, removing the sacrificial layer thereby exposing the pad and the first polymer, disposing a second polymer on the first polymer, patterning the second polymer with the opening over the pad, and disposing a conductive material on the pad within the opening. 1. A method of manufacturing a semiconductor device , comprising:providing a die;forming a pad on the die;disposing a first polymer over the die;patterning the first polymer with an opening over the pad;disposing a sacrificial layer over the patterned first polymer;disposing a molding surrounding the die;removing a portion of the molding thereby exposing the sacrificial layer;removing the sacrificial layer thereby exposing the pad and the first polymer;disposing a second polymer an the first polymer;patterning the second polymer with the opening over the pad; anddisposing a conductive material on the pad within the opening.2. The method of claim 1 , wherein the first polymer is surrounded by the molding.3. The method of claim 1 , wherein a portion of the pad is exposed from the first polymer.4. method of claim 1 , wherein the opening is disposed between the sacrificial layer and the pad.5. method of claim 1 , wherein the sacrificial layer includes a polymeric material.6. The method of claim 1 , wherein the molding is disposed over the sacrificial layer.7. The method of claim 1 , wherein the patterning the first polymer is performed by photolithography and etching operations.8. The method of claim 1 , wherein the removing the sacrificial layer is performed by etching operations.9. The method of claim 1 , wherein the removing the portion of the ...

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Номер записи: 192
14-01-2016 дата публикации

Integrated Fan-Out Package Structures with Recesses in Molding Compound

Номер: US20160013150A1
Автор: CHENG Li-Hui, Hung Jui-Pin, Lin Jing-Cheng, Tsai Po-Hao
Принадлежит:

A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface. 1. A method comprising:encapsulating a first die and a second die in an encapsulating material;planarizing the encapsulating material;after the planarizing, recessing a first portion of the encapsulating material, wherein a second portion of the encapsulating material is not recessed; andforming redistribution lines over and electrically coupled to the first die and the second die.2. The method of claim 1 , wherein the recessing is performed through laser drilling.3. The method of claim 1 , wherein the second portion forms a ring encircling the first portion.4. The method of claim 3 , wherein the second portion further encircles the first die and the second die.5. The method of claim 1 , wherein after the recessing claim 1 , a portion of the encapsulating material directly underlying the recessed first portion is left un-removed.6. The method of claim 1 , wherein the first die and the second die comprise a first protection film and a second protection film claim 1 , respectively claim 1 , wherein the planarizing is stopped when the first protection film and the second protection film are exposed claim 1 , and wherein the method further comprises:after the planarizing, removing the first protection film and a second protection film to expose the first die and the second die, respectively, wherein metal pads of ...

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Номер записи: 193
11-01-2018 дата публикации

Semiconductor Devices, Methods of Manufacture Thereof, and Semiconductor Device Packages

Номер: US20180012830A1
Автор: Chen I-Ting, Lin Jing-Cheng, Lu Szu-Wei, Shih Ying-Ching, Tsai Po-Hao
Принадлежит:

Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer. 1. A method of manufacturing a semiconductor device , the method comprising:forming a insulating material layer over a first substrate;removing a first portion of the insulating material layer to expose a contact pad at a top surface of the first substrate;forming one or more first insertion bumps over the insulating material layer; andwhile forming the one or more first insertion bumps, forming a first signal bump extending through the insulating material layer and electrically connected to the contact pad.2. The method according to claim 1 , wherein forming the one or more first insertion bumps and forming the first signal bump comprises:patterning a mask to form a first opening over the contact pad on the top surface of the first substrate, and to form one or more second openings over one or more areas of the insulating material layer over which the one or more first insertion bumps will be formed;performing a first plating process with a first conductive material to deposit the first conductive material in the first opening and the one or more second openings; andremoving the mask.3. The method according to claim 2 , further comprising:before removing the mask, performing a second plating process with a second conductive material to deposit the second conductive material in the first opening of the mask and the one or more second openings of the mask, wherein the second conductive material is different than the first conductive material.4. The method according to claim 2 , further comprising patterning the insulating material layer to remove ...

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Номер записи: 194
15-01-2015 дата публикации

Die-on-Interposer Assembly with Dam Structure and Method of Manufacturing the Same

Номер: US20150014844A1
Автор: Lin Jing-Cheng, Lu Szu Wei, Wu Chih-Wei
Принадлежит:

A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip.

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Номер записи: 195
15-01-2015 дата публикации

Dam Structure for Enhancing Joint Yield in Bonding Processes

Номер: US20150014863A1
Автор: Lin Jing-Cheng, Lu Szu Wei, Shih Ying-Ching
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A package structure includes a bottom package component, a top package component overlying and bonded to the bottom package component, and a dam between the bottom package component and the top package component. The dam has a top surface attached to a bottom surface of the top package component, and a bottom surface spaced apart from a top surface of the bottom package component.

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Номер записи: 196
15-01-2015 дата публикации

METHOD OF FORMING A SEMICONDUCTOR PACKAGE

Номер: US20150017764A1
Автор: Chang Chin-Chuan, Hung Jui-Pin, Lin Jing-Cheng
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A method of forming a semiconductor package includes forming an interconnecting structure on an adhesive layer, wherein the adhesive layer is on a carrier. The method further includes placing a semiconductor die on a surface of the interconnecting structure. The method further includes placing a package structure on the surface of the interconnecting structure, wherein the semiconductor die fits in a space between the interconnecting structure and the package structure. The method further includes performing a reflow to bond the package structure to the interconnecting structure. 1. A method of forming a semiconductor package , the method comprising:forming an interconnecting structure on an adhesive layer, wherein the adhesive layer is on a carrier;placing a semiconductor die on a surface of the interconnecting structure;placing a package structure on the surface of the interconnecting structure, wherein the semiconductor die fits in a space between the interconnecting structure and the package structure; andperforming a reflow to bond the package structure to the interconnecting structure.2. The method of claim 1 , wherein the reflow also bonds the semiconductor die to the interconnecting structure.3. The method of claim 1 , further comprising:performing another reflow after the semiconductor die is place on the surface of the interconnecting structure and prior to placing the package structure.4. The method of claim 1 , wherein the interconnecting structure includes a redistribution layer (RDL) claim 1 , and wherein the RDL of the interconnecting layer enables fan-out connection of the semiconductor die.5. The method of claim 1 , wherein the interconnecting structure includes a first contact to bond with the semiconductor die and a second contact to bond with the package structure claim 1 , wherein the first contact is smaller than the second contact.6. A method of making a semiconductor package claim 1 , the method comprising:forming an interconnecting structure ...

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Номер записи: 197