Semiconductor package and method of forming the same

The present disclosure provides a semiconductor package, including a first device having a first joining surface, a first conductive component at least partially protruding from the first joining surface, a second device having a second joining surface facing the first joining surface, and a second conductive component at least exposing from the second joining surface. The first conductive component and the second conductive component form a joint having a first beak. The first beak points to either the first joining surface or the second joining surface.

Packaging Methods and Structures Using a Die Attach Film

Packaging methods and structures for semiconductor devices that utilize a novel die attach film are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer and forming a die attach film (DAF) that includes a polymer over the carrier wafer. A plurality of dies is attached to the DAF, and the plurality of dies is packaged. At least the carrier wafer is removed from the packaged dies, and the packaged dies are singulated. 1. A method of packaging a semiconductor device , the method comprising:providing a carrier wafer;forming a die attach film (DAF) over the carrier wafer, the DAF comprising a polymer;attaching a plurality of dies to the DAF;packaging the plurality of dies;removing at least the carrier wafer from the packaged dies; andsingulating the packaged dies.2. The method according to claim 1 , wherein forming the DAF over the carrier wafer comprises forming a thermoplastic material.3. The method according to claim 2 , wherein forming the thermoplastic material comprises forming epoxy resin claim 2 , phenol resin claim 2 , or poly-olefin.4. The method according to claim 1 , wherein the step of packaging includes at least partially encapsulating the respective plurality of dies in a molding compound.5. The method according to claim 2 , wherein attaching the plurality of dies to the DAF comprises heating the DAF and applying pressure to the DAF.6. The method according to claim 5 , wherein heating the DAF comprises heating the DAF to a temperature of about 150 to 270 degrees C. for about 1 second to 2 minutes.7. The method according to claim 5 , wherein applying pressure to the DAF comprises applying a pressure of about 1 Newton (N) or greater.8. The method according to claim 1 , further comprising forming a release film over the carrier wafer claim 1 , before forming the DAF over the carrier wafer.9. The method according to claim 1 , further comprising marking the DAF.10. The method according to claim 9 , ...

Plating Process and Structure

A system and method for plating a contact is provided. An embodiment comprises forming protective layers over a contact and a test pad, and then selectively removing the protective layer over the contact without removing the protective layer over the test pad. With the protective layer still on the test pad, a conductive layer may be plated onto the contact without plating it onto the test pad. After the contact has been plated, the protective layer over the contact may be removed. 1. A method for manufacturing a semiconductor device , the method comprising:providing a contact and a test pad on a substrate, the contact and the test pad being electrically in contact with each other;forming a first protective layer from a portion of the test pad; andplating a conductive layer over the contact while the first protective layer is on the test pad.2. The method of claim 1 , further comprising forming a second protective layer from a portion of the contact claim 1 , the forming the second protective layer occurring in the same process as the forming the first protective layer.3. The method of claim 2 , further comprising removing the second protective layer from the contact before the plating the conductive layer claim 2 , the removing the second protective layer comprising etching the second protective layer with a solution comprising sulfuric acid.4. The method of claim 1 , further comprising removing the first protective layer from the test pad after the plating the conductive layer.5. The method of claim 4 , wherein the removing the first protective layer further comprises etching the first protective layer with a solution comprising sodium hydroxide.6. The method of claim 1 , wherein the plating the conductive layer comprises an electroless immersion process.7. The method of claim 1 , wherein the forming the first protective layer further comprises oxidizing the portion of the test pad.8. The method of claim 1 , wherein the forming the first protective layer further ...

Methods for De-Bonding Carriers

A method includes performing a dicing on a composite wafer including a plurality of dies, wherein the composite wafer is bonded on a carrier when the step of dicing is performed. After the step of dicing, the composite wafer is mounted onto a tape. The carrier is then de-bonded from the composite wafer and the first tape. 1. A method comprising:performing a dicing on a composite wafer comprising a plurality of dies, wherein the composite wafer is bonded on a carrier when the step of dicing is performed;after the step of dicing, mounting the composite wafer onto a first tape; andde-bonding the carrier from the composite wafer and the first tape.2. The method of claim 1 , wherein the composite wafer comprises a wafer claim 1 , wherein each of the plurality of dies comprises a tile of the wafer and one of a plurality of package components bonded to the wafer claim 1 , and wherein after the step of dicing claim 1 , tiles of the wafer are separated from each other.3. The method of claim 2 , wherein the compositing wafer further comprises a polymer molded onto the wafer claim 2 , with the polymer disposed in gaps between the plurality of package components claim 2 , and wherein after the step of dicing claim 2 , the plurality of dies are connected to each other through un-diced portions of the polymer.4. The method of further comprising:after the step of de-bonding the carrier, cutting the first tape to substantially a same size as the composite wafer; andperforming a grinding on the composite wafer to separate the plurality of dies from each other, wherein during the step of grinding, the first tape that has been cut remains mounted on the composite wafer.5. The method of further comprising:after the step of grinding, mounting a second tape onto the plurality of dies, wherein the first tape and the second tape are on opposite sides of the plurality of dies; anddemounting the first tape from the composite wafer.6. The method of further comprising:before the step of dicing ...

Plating Process and Structure

A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another embodiment a blocking structure may be inserted between the contact and the test pad. In yet another embodiment a blocking layer may be inserted into a contact stack. Once the blocking material, the blocking structure, or the blocking layer have been formed, the contact may be plated, with the blocking material, the blocking structure, or the blocking layer reducing or preventing degradation of the test pad due to galvanic effects. 1. A semiconductor device comprising:a contact on a substrate, the contact comprising a first material with a first reduction potential, the first reduction potential being at a first end of a range of reduction potentials;a test pad on the substrate, the test pad comprising a second material with a second reduction potential different from the first reduction potential, the second reduction potential being at a second end of the range of reduction potentials; andat least one via electrically connecting the test pad to the contact, the at least one via comprising a third material with a third reduction potential, the third reduction potential being outside of the range of reduction potentials.2. The semiconductor device of claim 1 , wherein the third reduction potential is greater than the second reduction potential.3. The semiconductor device of claim 1 , wherein the third reduction potential is lower than the first reduction potential.4. The semiconductor device of claim 1 , wherein the first material comprises copper and the second material comprises aluminum.5. The semiconductor device of claim 4 , wherein the third material comprises magnesium.6. The semiconductor device of claim 4 , wherein the third material comprises platinum.7. The semiconductor device of claim 1 , further comprising a redistribution line electrically connecting the test pad ...

SURFACE METAL WIRING STRUCTURE FOR AN IC SUBSTRATE

A surface metal wiring structure for a substrate includes one or more functional μbumps formed of a first metal and an electrical test pad formed of a second metal for receiving an electrical test probe and electrically connected to the one or more functional μbumps. The surface metal wiring structure also includes a plurality of sacrificial μbumps formed of the first metal that are electrically connected to the electrical test pads, where the sacrificial μbumps are positioned closer to the electrical test pad than the one or more functional μbumps. 1. A surface metal wiring structure for a substrate comprising:one or more functional μbumps formed of a first metal;an electrical test pad formed of a second metal for receiving an electrical test probe and electrically connected to the one or more functional μbumps, wherein the first and second metal are different;a plurality of sacrificial μbumps formed of the first metal and electrically connected to the electrical test pads, wherein the sacrificial μbumps are positioned closer to the electrical test pad than the one or more functional μbumps.2. The surface metal wiring structure according to claim 1 , wherein the first metal is copper.3. The surface metal wiring structure according to claim 1 , wherein the second metal is aluminum or an aluminum alloy.4. The surface metal wiring structure according to claim 1 , wherein the sacrificial μbumps are positioned closer to the electrical test pad than the one or more functional μbumps by about 3% to 97%.5. The surface metal wiring structure according to claim 1 , wherein the sacrificial μbumps are positioned closer to the electrical test pad than the one or more functional μbumps by about 70%.6. The surface metal wiring structure according to claim 1 , further wherein each of the plurality of sacrificial μbumps has up to 10% larger surface area than the one or more functional μbumps.7. The surface metal wiring structure according to claim 1 , further wherein each of the ...

UNDERFILL CURING METHOD USING CARRIER

A method includes bonding a carrier over a top die. The method further includes curing an underfill disposed between a substrate and the top die. The method further includes applying a force over the carrier during the curing. The method further includes removing the carrier from the top die. 1. A method , comprising:bonding a carrier over a top die;curing an underfill disposed between a substrate and the top die;applying a force over the carrier during the curing; andremoving the carrier from the top die.2. The method of claim 1 , wherein a coefficient of thermal expansion (CTE) of the carrier is greater than a CTE of the substrate.3. The method of claim 1 , further comprising dispensing the underfill between the top die and the substrate.4. The method of claim 1 , further comprising forming an adhesive layer over the top die or under the carrier.5. The method of claim 4 , further comprising cleaning the adhesive layer after removing the carrier from the top die.6. The method of claim 5 , wherein the cleaning is performed using a wet clean process.7. The method of claim 4 , wherein the adhesive layer is peeled off using a wafer tape after removing the carrier from the top die.8. The method of claim 1 , further comprising applying a release layer to the carrier.9. The method of claim 8 , wherein the release layer comprises a light to heat conversion (LTHC) material.10. The method of claim 8 , further comprising decomposing the release layer using a laser prior to removing the carrier.11. The method of claim 1 , wherein the force ranges from about 1000 N to about 8000 N.12. The method of claim 1 , wherein the curing is performed at a temperature ranging from about 80° C. to about 200° C.13. The method of claim 1 , wherein the curing is performed for a time period ranging from about 30 minutes to about 20 hours.14. A method claim 1 , comprising:bonding a carrier over a top die;dispensing an underfill between the top die and a substrate wherein a coefficient of thermal ...

Plating Process and Structure

A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another embodiment a blocking structure may be inserted between the contact and the test pad. In yet another embodiment a blocking layer may be inserted into a contact stack. Once the blocking material, the blocking structure, or the blocking layer have been formed, the contact may be plated, with the blocking material, the blocking structure, or the blocking layer reducing or preventing degradation of the test pad due to galvanic effects. 1. A method of manufacturing a semiconductor device , the method comprising:forming at least one via over a substrate;forming a contact on the substrate, the contact comprising a first material with a first reduction potential, the first reduction potential being at a first end of a range of reduction potentials; andforming a test pad on the substrate, wherein the at least one via is located in an electrical pathway between the contact and the test pad, the test pad comprising a second material with a second reduction potential different from the first reduction potential, the second reduction potential being at a second end of the range of reduction potentials, wherein the at least one via comprises a third material with a third reduction potential outside of the range of reduction potentials.2. The method of claim 1 , wherein the third reduction potential is greater than the second reduction potential.3. The method of claim 1 , wherein the third reduction potential is lower than the first reduction potential.4. The method of claim 1 , wherein the first material comprises copper and the second material comprises aluminum.5. The method of claim 4 , wherein the third material comprises magnesium.6. The method of claim 4 , wherein the third material comprises platinum.7. The method of claim 1 , further comprising forming a redistribution line over the ...

Metal-Bump Sidewall Protection

A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer. 1. A package comprising: a dielectric layer;', 'a metal bump protruding beyond the dielectric layer;', 'a solder region over and contacting the metal bump; and', 'a protection layer contacting a sidewall of the metal bump and a surface of the dielectric layer, wherein the protection layer is formed of a dielectric material., 'a first package component comprising2. The package of claim 1 , wherein the protection layer is free from filler particles therein.3. The package of further comprising:a second package component bonded to the first package component; andan underfill contacting the protection layer, wherein the underfill comprises a portion lower than a bottom surface of the metal bump.4. The package of claim 1 , wherein the protection layer is lower than claim 1 , and is spaced apart from claim 1 , the solder region.5. The package of claim 1 , wherein the protection layer and the dielectric layer are formed of a same dielectric material claim 1 , and have a distinguishable interface therebetween.6. The package of claim 1 , wherein the protection layer comprises polyimide claim 1 , polybenzoxazole (PBO) claim 1 , or benzocyclobutene (BCB).7. The package of claim 1 , wherein the first package component comprises an edge claim 1 , and the protection layer is recessed laterally from the edge.8. The package of claim 1 , wherein the first package component further comprises an additional metal bump protruding beyond the dielectric layer claim 1 , and the protection layer comprises:a first portion contacting the ...

Package-on-package structure and method of manufacturing package

A package-on-package (PoP) structure includes a first package and a second package stacked on the first package. The first package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes an amorphous layer located on the rear surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is on the active surface of the die and is electrically connected to the conductive structures and the die.

AN ADHESIVE AND THERMAL INTERFACE MATERIAL ON A PLURALITY OF DIES COVERED BY A LID

Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die. The TIM is disposed on the first die, the second die, and the underfill layer. The adhesive pattern is disposed between the underfill layer and the TIM to separate the underfill layer from the TIM. 1. A package structure , comprising:a first die and a second die group, disposed side by side on an interposer;an underfill layer, disposed between the first die and the second die group;a thermal interface material (TIM), disposed on the first die, the second die group, and the underfill layer;an adhesive pattern, disposed between the underfill layer and the TIM to separate the underfill layer from the TIM; andan encapsulant laterally encapsulating the first die, the second die group, and the underfill layer, wherein a sidewall of the encapsulant is substantially aligned with a sidewall of the interposer.2. The package structure of claim 1 , wherein the second die group comprises at least one second die or a plurality of second dies claim 1 , the plurality of second dies are respectively disposed at both sides of the first die claim 1 , and the adhesive pattern comprises a plurality of adhesive layers discretely distributed on the underfill layer between the first die and the plurality of second dies.3. The package structure of claim 2 , wherein a portion of the plurality of adhesive layers is disposed between the encapsulant and the TIM to separate the encapsulant from the TIM.4. (canceled)5. The package structure of claim 2 , wherein one of the plurality of adhesive layers has a curved top surface and has a thickness decreasing along a direction from center to edge.6. The package structure of claim 1 , ...

Package structure and method of fabricating the same

A package structure including a first semiconductor die, a second semiconductor die, a molding compound, an interconnect structure, first conductive features, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The molding compound is encapsulating the first semiconductor die and the second semiconductor die. The interconnect structure is disposed on the molding compound and electrically connecting the first semiconductor die to the second semiconductor die. The first conductive features are electrically connected to the first semiconductor die and the second semiconductor die, wherein each of the first conductive features has a recessed portion. The through insulator vias are disposed on the recessed portion of the first conductive features and electrically connected to the first and second semiconductor die. The insulating encapsulant is encapsulating the interconnect structure and the through insulator vias. The redistribution layer is disposed on the insulating encapsulant and over the interconnect structure.

Semiconductor Device and Method of Forming the Same

A method of forming a semiconductor device includes attaching a first semiconductor device to a first surface of a substrate; forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; and forming an underfill material in the first region. 1. A semiconductor structure comprises:a substrate;a first semiconductor device attached to a first side of the substrate; andan underfill material around the first semiconductor device and between the substrate and the first semiconductor device, wherein a fillet of the underfill material has a first portion distal from the substrate and a second portion between the first portion and the substrate, wherein a first width of the first portion increases continuously as the first portion extends toward the substrate, and a second width of the second portion is uniform.2. The semiconductor structure of claim 1 , wherein the fillet of the underfill material further comprises a third portion between the second portion and the substrate claim 1 , wherein a third width of the third portion changes continuously as the third portion extends toward the substrate.3. The semiconductor structure of claim 2 , wherein the third width of the third portion decreases continuously as the third portion extends toward the substrate.4. The semiconductor structure of claim 2 , wherein the third width of the third portion increases continuously as the third portion extends toward the substrate.5. The semiconductor structure of claim 2 , wherein a lower surface of the third portion of the fillet contacts and extends along the first side of the substrate.6. The semiconductor structure of claim 1 , wherein the second portion of the fillet contacts and extends along the first side of the substrate.7. The semiconductor structure of claim 1 , further comprising a second semiconductor device attached to the first side of ...

Package structure and method for forming the same

A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes an interposer, a first semiconductor die and a second semiconductor die over the interposer. The method for forming a package structure also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component. The method for forming a package structure further includes forming an underfill layer between the dam structure and the package component, and removing the dam structure after the underfill layer is formed.

Connector Design for Packaging Integrated Circuits

A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar. 1. A method comprising:forming a top dielectric layer of a first package component;forming a metal pillar extending over a top surface of the top dielectric layer;forming a metal cap over the metal pillar, wherein the metal cap comprises edge portions extending beyond respective sidewalls the metal pillar;performing a treatment on a sidewall surface of the metal cap to form a first non-wettable surface layer; andforming a solder region over the metal cap.2. The method of claim 1 , further comprising performing the treatment on a sidewall surface of the metal to form a second non-wettable surface layer.3. The method of claim 1 , wherein performing the treatment comprises treating the sidewall surface of the metal cap in a process gas selected from a group consisting essentially of nitrogen claim 1 , oxygen claim 1 , and combinations thereof.4. The method of further comprising claim 1 , after forming the metal cap and the solder region claim 1 , performing an etching step to etch the metal pillar claim 1 , wherein the metal cap is not etched claim 1 , and wherein portions of the metal pillar directly underlying the edge portions of the metal cap are etched.5. The method of further comprising bonding a second package component to the first package component claim 1 , wherein bonding the second package comprises reflowing the solder region.6. The method of claim 5 , wherein after the bonding the second package comprises bending the edge portions of the metal cap away from the top dielectric layer.7. The method of claim 5 , wherein after the bonding the second package comprises bending the edge portions of the metal cap ...

SEMICONDUCTOR PACKAGES AND FORMING METHOD THEREOF

Semiconductor packages and methods of forming the same are provided. One of the semiconductor packages includes a first semiconductor die, an adhesive layer, a second semiconductor die and an underfill. The first semiconductor die includes a first surface, and the first surface includes a central region and a peripheral region surrounding the central region. The adhesive layer is adhered to the peripheral region and exposes the central region. The second semiconductor die is stacked over the first surface of the first semiconductor die. The underfill is disposed between the first semiconductor die and the second semiconductor die. 1. A semiconductor package , comprising:a first semiconductor die comprising a first surface, the first surface having a central region and a peripheral region surrounding the central region;an adhesive layer adhered to the peripheral region and exposing the central region;a second semiconductor die, stacked over the first surface of the first semiconductor die; andan underfill between the first semiconductor die and the second semiconductor die.2. The semiconductor package of claim 1 , wherein the underfill is in contact with the central region of the first surface.3. The semiconductor package of claim 1 , wherein the first semiconductor die comprises a substrate and an amorphous layer on the substrate claim 1 , the first surface is a surface of the amorphous layer.4. The semiconductor package of claim 1 , wherein the adhesive layer has a ring shape.5. The semiconductor package of claim 1 , wherein the adhesive layer comprises a plurality of discrete patterns.6. The semiconductor package of claim 1 , further comprising a conductive pillar aside the first semiconductor die claim 1 , wherein the conductive pillar comprises a seed layer pattern and a conductive pattern claim 1 , wherein a surface of the seed layer pattern is lower than a surface of the adhesive layer.7. The semiconductor package of claim 1 , further comprising an encapsulant ...

PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

A package structure includes a circuit substrate, a semiconductor package, a lid structure, a passive device and a barrier structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package. The lid structure is attached to the circuit substrate through an adhesive material. The passive device is disposed on the circuit substrate in between the semiconductor package and the lid structure. The barrier structure is separating the passive device from the lid structure and the adhesive material, and the barrier structure is in contact with the adhesive material. 1. A package structure , comprising:a circuit substrate;a semiconductor package disposed on and electrically connected to the circuit substrate;a lid structure disposed on the circuit substrate covering the semiconductor package, wherein the lid structure is attached to the circuit substrate through an adhesive material;a passive device disposed on the circuit substrate in between the semiconductor package and the lid structure; anda barrier structure separating the passive device from the lid structure and the adhesive material, wherein the barrier structure is in contact with the adhesive material.2. The package structure according to claim 1 , wherein the barrier structure comprises a first dam portion located in between the passive device and the lid structure claim 1 , and spaced apart from the passive device and the lid structure claim 1 , the first dam portion has a first sidewall that faces the lid structure and a second sidewall opposite to the first sidewall that faces the passive device claim 1 , and the first sidewall of the first dam portion is in contact with the adhesive material.3. The package structure according to claim 2 , wherein the first dam portion further surrounds side surfaces of the passive device.4. The package structure according to claim 2 , wherein the ...

ADHESIVE AND THERMAL INTERFACE MATERIAL ON A PLURALITY OF DIES COVERED BY A LID

Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure and a manufacturing method thereof are provided. The package structure includes a substrate, a semiconductor package, a thermal conductive gel, a thermal conductive film, and a heat spreader. The semiconductor package has an uneven top surface. The thermal conductive gel covers the uneven top surface of the semiconductor package. The thermal conductive film is over the uneven top surface of the semiconductor package. A thermal conductivity of the thermal conductive film is higher than a thermal conductivity of the thermal conductive gel. The heat spreader is disposed over the thermal conductive film. 1. A package structure comprising:a substrate;a semiconductor package over the substrate, wherein the semiconductor package has an uneven top surface;a thermal conductive gel covering the uneven top surface of the semiconductor package;a thermal conductive film over the uneven top surface of the semiconductor package and the thermal conductive gel, wherein a thermal conductivity of the thermal conductive film is higher than a thermal conductivity of the thermal conductive gel; anda heat spreader over the thermal conductive film.2. The package structure as claimed in claim 1 , wherein the semiconductor package comprises an integrated circuit and a plurality of components claim 1 , wherein the integrated circuit is disposed between the substrate and the plurality of components claim 1 , wherein the thermal conductive gel is disposed between the plurality of components over the integrated circuit.3. The package structure as claimed in claim 2 , wherein a top surface of the thermal conductive gel is substantially coplanar with top surfaces of the plurality of components.4. The package structure as claimed in claim 2 , wherein the plurality of components comprise a plurality of dies.5. The package structure as claimed in claim 2 , wherein the plurality of components comprise a plurality of dies and a dam surrounding the plurality of dies claim 2 , and the ...

METHOD OF FABRICATING PACKAGE STRUCTURE

A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer. 1. A method , comprising:placing devices on a tape;forming a metallic material layer covering the devices and the tape;pick-up at least one of the devices covered by the metallic material layer from the tape such that a metal layer of the metallic material layer is separated from a residue portion of the metallic material layer, wherein the metal layer at least covers a back surface of the at least one of the devices, and the residue portion covers the tape;mounting at least one of the devices covered by the metal layer onto a circuit substrate; andmounting a lid on the circuit substrate, wherein the lid is adhered to the metal layer on the at least one of the devices through a thermal interface material layer.2. The method according to claim 1 , wherein the metallic material layer is conformally formed over the tape and over the back surface and side surfaces of the at least one of the devices.3. The method according to claim 1 , wherein conductive terminals of the devices are distributed on front surfaces of the devices and embedded in the tape claim 1 , and the front surfaces of the devices are attached to the tape after placing the devices on the tape.4. The method according to further comprising:before mounting the lid on the circuit substrate and after mounting the at least one of the devices covered by the metal layer onto the circuit substrate, forming an underfill between the at least one of the devices and circuit ...

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure includes a substrate, a die, an adhesive layer, a dam structure, and an encapsulant. The die is disposed on the substrate. The adhesive layer is disposed between the substrate and the die. The adhesive layer has a curved surface. The dam structure is disposed on the substrate and surrounded by the adhesive layer. The encapsulant encapsulates the die. 1. A package structure , comprising:a substrate;a die disposed on the substrate;an adhesive layer disposed between the substrate and the die, wherein the adhesive layer has a curved surface;a dam structure disposed on the substrate and surrounded by the adhesive layer; andan encapsulant encapsulating the die.2. The package structure according to claim 1 , wherein the adhesive layer comprises a liquid-type die attach film (DAF) or a liquid-type film over wire (FOW).3. The package structure according to claim 1 , wherein the adhesive layer is free of filler.4. The package structure according to claim 1 , wherein the adhesive layer has a sinking portion claim 1 , and a surface of the sinking portion is the curved surface.5. The package structure according to claim 4 , wherein a maximum thickness of the adhesive layer is smaller than or substantially equal to a thickness of the dam structure.6. The package structure according to claim 1 , wherein the adhesive layer has an overflow portion partially covers sidewalls of the die and a top surface of the dam structure claim 1 , and a surface of the overflow portion is the curved surface.7. The package structure according to claim 6 , wherein a maximum thickness of the adhesive layer is greater than a thickness of the dam structure.8. A package structure claim 6 , comprising:a first die;a second die and a third die disposed side by side over the first die, wherein the third die has a through hole exposing the first die;an adhesive layer sandwiched between the third die and the first die, wherein the adhesive layer comprises a concave portion located in the ...

Integrated Circuit Package and Method

In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.

SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME

The present disclosure provides a semiconductor package, including a first device having a first joining surface, a first conductive component at least partially protruding from the first joining surface, a second device having a second joining surface facing the first joining surface, and a second conductive component at least exposing from the second joining surface. The first conductive component and the second conductive component form a joint having a first beak. The first beak points to either the first joining surface or the second joining surface. 1. A semiconductor package , comprising:a first device having a first joining surface;a first conductive component at least partially protruding from the first joining surface;a second device having a second joining surface facing the first joining surface; anda second conductive component at least exposing from the second joining surface,wherein the first conductive component and the second conductive component forming a joint having a first beak contour and a second beak contour, the first beak contour having a tip at a first side of the joint, the tip at a first side of the joint pointing to either the first joining surface or the second joining surface, and the second beak contour having a tip at a second side of the joint, the tip at a second side of the joint pointing to either the first joining surface or the second joining surface.2. The semiconductor package of claim 1 , wherein the first device is selected from a group consisting essentially of a semiconductor wafer and a semiconductor chip.3. The semiconductor package of claim 2 , wherein the second device is selected from a group consisting essentially of a semiconductor wafer and a semiconductor chip.4. The semiconductor package of claim 1 , wherein the first conductive component is a through dielectric via (TDV) or a through silicon via (TSV).5. The semiconductor package of claim 1 , wherein a width of the first conductive component and a width of the ...

Package structure and manufacturing method thereof

A package structure includes a plurality of first dies, a first encapsulant, and a first redistribution structure. The first encapsulant encapsulates the first dies. The first redistribution structure is disposed on the first dies and the first encapsulant. The first redistribution structure includes a dielectric layer covering a top surface and sidewalls of the first encapsulant.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

A method of forming a semiconductor device includes attaching a first semiconductor device to a first surface of a substrate; forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; and forming an underfill material in the first region. 1. A method of forming a semiconductor device , the method comprising:attaching a first semiconductor device to a first surface of a substrate;forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; andforming an underfill material in the first region.2. The method of claim 1 , wherein the first surface of the substrate has passive components attached thereto claim 1 , wherein the sacrificial structure is formed between the passive components and the first semiconductor device.3. The method of claim 1 , wherein forming the sacrificial structure comprises:dispensing a sacrificial material in liquid form or gel form on the first surface of the substrate around the first semiconductor device; andcuring the sacrificial material while the sacrificial material is being dispensed.4. The method of claim 3 , wherein curing the sacrificial material comprises performing an ultraviolet (UV) curing process or a thermal curing process.5. The method of claim 4 , wherein the sacrificial material is cured by the UV curing process claim 4 , wherein forming the sacrificial structure comprises controlling a shape of the sacrificial structure by adjusting a UV dosage of the UV curing process.6. The method of claim 3 , wherein the sacrificial material comprises polymer claim 3 , polyimide claim 3 , or epoxy.7. The method of claim 1 , wherein the sacrificial structure keeps the underfill material within the first region claim 1 , wherein regions of the first surface of the ...

Package structure, semiconductor pacakge and method of fabricating the same

A package structure including a first semiconductor die, a second semiconductor die, a molding compound, an interconnect structure, first conductive features, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The molding compound is encapsulating the first semiconductor die and the second semiconductor die. The interconnect structure is disposed on the molding compound and electrically connecting the first semiconductor die to the second semiconductor die. The first conductive features are electrically connected to the first semiconductor die and the second semiconductor die, wherein each of the first conductive features has a recessed portion. The through insulator vias are disposed on the recessed portion of the first conductive features and electrically connected to the first and second semiconductor die. The insulating encapsulant is encapsulating the interconnect structure and the through insulator vias. The redistribution layer is disposed on the insulating encapsulant and over the interconnect structure.

Metal-Bump Sidewall Protection

A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer. 1. A method of forming a package , the method comprising:forming a metal bump on a top surface of a first package component;forming a solder region on a top surface of the metal bump;forming a protection layer extending on a sidewall of the metal bump;reflowing the solder region to bond the first package component to a second package component; anddispensing an underfill between the first package component and the second package component, wherein the underfill is in contact with the protection layer.2. The method of claim 1 , wherein the protection layer is formed through inkjet printing.3. The method of claim 2 , wherein in the inkjet printing claim 2 , the protection layer is printed to a location spaced apart from the metal bump claim 2 , and the protection layer extends to the sidewall of the metal bump through capillary action.4. The method of claim 1 , wherein the forming the protection layer comprises:spin coating the protection layer on the first package component, wherein the protection layer comprises a portion on a top surface of the solder region; andperforming a lithography process to remove the portion of the protection layer on the top surface of the solder region.5. The method of claim 1 , wherein the forming the protection layer comprises dispensing a light-sensitive polymer claim 1 , and the protection layer is free from filler particles therein.6. The method of claim 1 , wherein the protection layer is spaced apart from the solder region.7. The method of further comprising claim 1 , after ...

OPTICAL TRANSCEIVER AND MANUFACTURING METHOD THEREOF

An optical transceiver including a photonic integrated circuit component, an electric integrated circuit component and an insulating encapsulant is provided. The photonic integrated circuit component includes at least one optical input/output portion and at least one groove located in proximity of the at least one optical input/output portion. The electric integrated circuit component is disposed on and electrically connected to the photonic integrated circuit component. 1. An optical transceiver , comprising:a photonic integrated circuit component comprising at least one optical input/output portion and at least one groove located in proximity of the at least one optical input/output portion;an electric integrated circuit component disposed on and electrically connected to the photonic integrated circuit component; andan insulating encapsulant disposed on the photonic integrated circuit component and laterally encapsulating the electric integrated circuit component, wherein the insulating encapsulant and the at least one groove of the photonic integrated circuit component are adapted for insertion of a photonic device.2. The optical transceiver as claimed in claim 1 , wherein the electric integrated circuit component is electrically connected to the photonic integrated circuit component through a plurality of micro-bumps.3. The optical transceiver as claimed in claim 1 , wherein a portion of the insulating encapsulant is located above a portion of the at least one optical input/output portion claim 1 , the portion of the insulating encapsulant comprises a curved sidewall claim 1 , and a top dimension of the portion of the insulating encapsulant is greater than a bottom dimension of the portion of the insulating encapsulant.4. The optical transceiver as claimed in claim 1 , wherein a portion of the insulating encapsulant is located above a portion of the at least one optical input/output portion claim 1 , the portion of the insulating encapsulant comprises a curved ...

PACKAGE-ON-PACKAGE STRUCTURE

A package-on-package (PoP) structure includes a first package and a second package stacked on the first package. The first package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes an amorphous layer located on the rear surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is on the active surface of the die and is electrically connected to the conductive structures and the die. 1. A package-on-package (PoP) structure , comprising: a die having an active surface and a rear surface opposite to the active surface, wherein the die comprises an amorphous layer located on the rear surface;', 'a plurality of conductive structures surrounding the die;', 'an encapsulant encapsulating the die and the plurality of conductive structures; and', 'a redistribution structure on the active surface of the die, wherein the redistribution structure is electrically connected to the plurality of conductive structures and the die; and, 'a first package, comprisinga second package stacked on the first package.2. The PoP structure according to claim 1 , wherein the amorphous layer comprises an amorphous silicon layer.3. The PoP structure according to claim 1 , wherein a ratio of a thickness of the amorphous layer to a thickness of the die ranges between about 1:133.3 and about 1:250000.4. The PoP structure according to claim 1 , wherein a thickness of the amorphous layer ranges between about 1 nm and about 300 nm.5. The PoP structure according to claim 1 , wherein a surface of the amorphous layer is substantially coplanar with a surface of the encapsulant.6. The PoP structure according to claim 1 , wherein a surface of the amorphous layer is located at a different level height from a surface of the encapsulant.7. The PoP structure according to ...

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate, a package structure, a lid structure, and a thermal spreader layer. The package structure is disposed on the substrate, wherein the package structure includes a plurality of device dies and a filling material filling a gap between adjacent two of the plurality of device dies. The lid structure is disposed over substrate and covering the package structure. The thermal spreader layer is disposed between the lid structure and the package structure, wherein the thermal spreader layer has a profile that is discontinuous in thickness at a gap region corresponding to the gap. 1. A semiconductor package , comprising:a substrate;a package structure disposed on the substrate, wherein the package structure comprises a plurality of device dies and a filling material filling a gap between adjacent two of the plurality of device dies;a lid structure disposed over substrate and covering the package structure; anda thermal spreader layer disposed between the lid structure and the package structure, wherein the thermal spreader layer has a profile that is discontinuous in thickness at a gap region corresponding to the gap.2. The semiconductor package as claimed in claim 1 , wherein a thickness of the thermal spreader layer at the gap region is substantially thinner than a thickness of the thermal spreader layer at other region.3. The semiconductor package as claimed in claim 1 , wherein a thickness of the thermal spreader layer at the gap region is substantially equal to zero.4. The semiconductor package as claimed in claim 1 , wherein a young's modulus of the thermal spreader layer is substantially greater than a young's modulus of the filling material.5. The semiconductor package as claimed in claim 1 , wherein the filling material comprising a protruding portion protruding from back surfaces of the plurality of device dies and fills a space defined by thickness discontinuity of the thermal spreader layer at the gap region.6. The ...

PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

A package structure includes a circuits substrate, a semiconductor package, a lid structure and a plurality of first spacer structures. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package, wherein the lid structure is attached to the circuit substrate through an adhesive material. The plurality of first spacer structures is surrounding the semiconductor package, wherein the first spacer structures are sandwiched between the lid structure and the circuit substrate, and includes a top portion in contact with the lid structure and a bottom portion in contact with the circuit substrate. 1. A package structure , comprising:a circuit substrate;a semiconductor package disposed on and electrically connected to the circuit substrate;a lid structure disposed on the circuit substrate covering the semiconductor package, wherein the lid structure is attached to the circuit substrate through an adhesive material; anda plurality of first spacer structures surrounding the semiconductor package, wherein the plurality of first spacer structures is sandwiched between the lid structure and the circuit substrate, and includes a top portion in contact with the lid structure and a bottom portion in contact with the circuit substrate.2. The package structure according to claim 1 , wherein the circuit substrate comprises a plurality of openings that exposes conductive pads of the circuit substrate claim 1 , and the plurality of first spacer structures is disposed within the plurality of openings and connected to the conductive pads.3. The package structure according to claim 1 , further comprising a plurality of second spacer structures surrounding the plurality of first spacer structures claim 1 , wherein the plurality of second spacer structures is sandwiched between the lid structure and the circuit substrate claim 1 , and includes a top portion in contact ...

PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer 19-. (canceled)10. A method , comprising:placing devices in cavities of a tray;forming a metallic material layer covering the devices and the tray;pick-up at least one of the devices covered by the metallic material layer from the tray such that a metal layer of the metallic material layer is separated from a residue portion of the metallic material layer, wherein the metal layer at least covers a back surface of the at least one of devices, and the residue portion covers the tray;mounting at least one of the devices covered by the metal layer onto a circuit substrate; andmounting a lid on the circuit substrate, wherein the lid is adhered to the metal layer on the at least one of the devices through a thermal interface material layer.11. The method according to claim 10 , wherein the tray comprises partition walls and support walls claim 10 , the partition walls define the cavities of the tray claim 10 , and the support walls support the devices in the cavities of the tray claim 10 , and conductive terminals of the devices are surrounded by the support walls of the tray when the devices are placed in the cavities of the tray.12. The method according to claim 11 , wherein the metallic material layer is conformally formed over the partition walls claim 11 , the support walls of the tray and over the back surface and side surfaces of the at least one of the devices.13. The method according to further comprising:before mounting the ...

Integrated Circuit Package and Method

In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.

PACKAGE CONTACT STRUCTURE, SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A package contact structure, a semiconductor package and a manufacturing method are provided. The package contact structure includes a conductive feature and a dielectric barrier. The conductive feature includes a first portion and a second portion disposed on the first portion. Materials of the first portion and the second portion are different. The dielectric barrier is sleeved on the first portion and extends to cover at least a part of the second portion. A maximum height of the dielectric barrier is less than a maximum height of the conductive feature. 1. A package contact structure , comprising:a conductive contact, comprising a first portion and a second portion disposed on the first portion, wherein materials of the first portion and the second portion are different; anda dielectric barrier, sleeved on the first portion and extending to cover at least a part of the second portion, wherein a maximum height of the dielectric barrier is less than a maximum height of the conductive contact, and a minimum height of the dielectric barrier is less than a maximum height of the first portion of the conductive contact.2. The package contact structure of claim 1 , wherein a thickness of the dielectric barrier decreases from the first portion of the conductive contact to the second portion of the conductive contact.3. The package contact structure of claim 1 , wherein a maximum thickness of the dielectric barrier on the second portion of the conductive contact is less than about 3 μm.4. The package contact structure of claim 1 , wherein the dielectric barrier has a curvilinear surface surrounding the conductive contact.5. The package contact structure of claim 1 , whereinthe package contact structure is configured to electrically connect a first package component to a second package component, andthe package contact structure is configured to be covered by an underfill layer disposed between the first package component and the second package component, wherein the ...

Integrated circuit package and method of forming same

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, and a redistribution structure disposed on the first semiconductor die and the insulating encapsulation. The first semiconductor die includes a first contact region and a first non-contact region in proximity to the first contact region. The first semiconductor die includes a first electrical connector disposed on the first contact region and a first dummy conductor disposed on the first non-contact region, and the first electrical connector is electrically connected to a first integrated circuit (IC) component in the first semiconductor die. The first electrical connector is electrically connected to the redistribution structure, and the first dummy conductor is electrically insulated from the first IC component in the first semiconductor die and the redistribution structure. 1. A semiconductor package , comprising:a first semiconductor die, comprising a first contact region and a first non-contact region in proximity to the first contact region, the first semiconductor die comprising a first electrical connector disposed on the first contact region and a first dummy conductor disposed on the first non-contact region, the first electrical connector being electrically connected to a first integrated circuit (IC) component in the first semiconductor die;an insulating encapsulation, laterally encapsulating the first semiconductor die; anda redistribution structure, disposed on the first semiconductor die and the insulating encapsulation, wherein the first electrical connector is electrically connected to the redistribution structure, and the first dummy conductor is electrically insulated from the first IC component in the first semiconductor die and the redistribution structure.2. The semiconductor package of claim 1 , whereinat least two sides of the ...

PACKAGE STRUCTURE AND SEMICONDUCTOR PACAKGE

A package structure includes a semiconductor die, a plurality of conductive features, a bridge structure, an underfill, via structures and an encapsulant. The conductive features are electrically connected to the semiconductor die, wherein the conductive features include a first group with planar top surfaces, and a second group with uneven top surfaces. The bridge structure is partially overlapped with the semiconductor die and electrically connected to the first group of the conductive feature. The underfill is covering and contacting the first group of the conductive features. The via structures are disposed on and overlapped with the semiconductor die and electrically connected to the second group of the conductive features. The encapsulant is covering and contacting the via structures and the second group of the conductive features. 1. A structure , comprising:a semiconductor die;a plurality of conductive features electrically connected to the semiconductor die, wherein the plurality of conductive features comprises a first group with planar top surfaces, and a second group with uneven top surfaces;a bridge structure partially overlapped with the semiconductor die and electrically connected to the first group of the plurality of conductive features;an underfill covering and contacting the first group of the plurality of conductive features;via structures disposed on and overlapped with the semiconductor die and electrically connected to the second group of the plurality of conductive features; andan encapsulant covering and contacting the via structures and the second group of the plurality of conductive features.2. The structure according to claim 1 , further comprising a molding compound surrounding the semiconductor die claim 1 , wherein sidewalls of the molding compound are aligned with sidewalls of the encapsulant.3. The structure according to claim 2 , further comprising a dielectric layer sandwiched between the molding compound and the encapsulant.4. The ...

Package structure and method of forming the same

A package structure and method of forming the same are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is laterally aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element insertion. The encapsulant laterally encapsulates the second die and the wall structure.

Method for forming package structure

A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes a first semiconductor die and a second semiconductor die. The method also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component, and a top surface of the dam structure is higher than a top surface of the package component. The method further includes forming an underfill layer between the dam structure and the package component. In addition, the method includes removing the dam structure after the underfill layer is formed.

Semiconductor package, integrated optical communication system and manufacturing method of integrated optical communication system

A semiconductor package includes a photonic integrated circuit, an encapsulating material, and a redistribution structure. The photonic integrated circuit includes a coupling surface, a back surface opposite to the coupling surface and a plurality of optical couplers disposed on the coupling surface and configured to be coupled to a plurality of optical fibers. The encapsulating material encapsulates the photonic integrated circuit and revealing the plurality of optical couplers. The redistribution structure is disposed over the encapsulating material and the back surface of the photonic integrated circuit, wherein the redistribution structure is electrically connected to the photonic integrated circuit.

PACKAGE-ON-PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package-on-package structure including a first and second package is provided. The first package includes a semiconductor die, through insulator vias, an insulating encapsulant, conductive terminals and a redistribution layer. The semiconductor die has a die height H. The plurality of through insulator vias is surrounding the semiconductor die and has a height H, and H Подробнее

SEMICONDUCTOR DEVICE PACKAGE HAVING METAL THERMAL INTERFACE MATERIAL AND METHOD FOR FORMING THE SAME

A method for forming a semiconductor device package is provided. The method includes bonding a semiconductor device to a package substrate; placing a metal lid over the semiconductor device and the package substrate with a metal thermal interface material (TIM) provided between the metal lid and the semiconductor device; heating the metal TIM to melt the metal TIM; pressing the metal lid downward so that the molten metal TIM flows toward the boundary of the semiconductor device, and the outermost point of the lateral sidewall of the molten metal TIM extends beyond the boundary of the semiconductor device; lifting the metal lid upward so that the molten metal TIM flows back, and the outermost point of the lateral sidewall is within the boundary of the semiconductor device; and bonding the metal lid to the semiconductor device through the metal TIM by curing the molten metal TIM. 1. A method for forming a semiconductor device package , comprising:bonding a semiconductor device to a first surface of a package substrate;placing a metal lid over the semiconductor device and the package substrate with a metal thermal interface material (TIM) provided between the metal lid and a top surface of the semiconductor device;heating the metal TIM to melt the metal TIM;pressing the metal lid downward so that the molten metal TIM flows toward a boundary of the semiconductor device, and an outermost point of a lateral sidewall of the molten metal TIM extends beyond the boundary of the semiconductor device;lifting the metal lid upward so that the molten metal TIM flows back, and the outermost point of the lateral sidewall of the molten metal TIM is within the boundary of the semiconductor device; andbonding the metal lid to the semiconductor device through the metal TIM by cooling the molten metal TIM.2. The method as claimed in claim 1 , wherein the metal lid is pressed down using a thermal compression bonding head claim 1 , and the metal lid is lifted up using the thermal ...

PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

A package structure includes a circuit substrate, a semiconductor package, a lid structure, a passive device and a barrier structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package. The lid structure is attached to the circuit substrate through an adhesive material. The passive device is disposed on the circuit substrate in between the semiconductor package and the lid structure. The barrier structure is separating the passive device from the lid structure and the adhesive material, and the barrier structure is in contact with the adhesive material. 1. A structure , comprising:a substrate;a package disposed on the substrate;an underfill structure disposed in between the substrate and the package;a first passive device disposed on the substrate aside the package; anda first dam portion disposed on the substrate, wherein the first dam portion includes a first section, a second section and a third section, the first section and the second section surround two opposing side surfaces of the first passive device, the third section physically joins the first section to the second section and surrounds a third side surface of the first passive device, and the first dam portion uncovers a fourth side surface of the first passive device that is facing the package, and wherein disconnected ends of the first section and the second section include end terminal surfaces that are facing the underfill structure.2. The structure according to claim 1 , further comprising:a lid structure disposed on the substrate and attached to the substrate through an adhesive, wherein the adhesive is in physical contact with the first dam portion.3. The structure according to claim 1 , further comprising a second dam portion disposed on the substrate claim 1 , wherein the second dam portion includes a first section claim 1 , a second section and a third section ...

PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

A package structure includes a circuit substrate, a semiconductor package, a lid structure and a plurality of first spacer structures. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package, wherein the lid structure is attached to the circuit substrate through an adhesive material. The plurality of first spacer structures is surrounding the semiconductor package, wherein the first spacer structures are sandwiched between the lid structure and the circuit substrate, and includes a top portion in contact with the lid structure and a bottom portion in contact with the circuit substrate. 1. A structure , comprising:a package disposed on and electrically connected to a circuit substrate;a lid structure disposed on the circuit substrate covering the package; anda plurality of first spacer structures surrounding the semiconductor package and separated from the semiconductor package, wherein the plurality of first spacer structures includes a top portion in physical contact with the lid structure and a bottom portion in physical contact with the circuit substrate.2. The structure according to claim 1 , further comprising an adhesive material covering the plurality of first spacer structures.3. The structure according to claim 1 , further comprising a plurality of second spacer structures surrounding the plurality of first spacer structures claim 1 , wherein the plurality of second spacer structures includes a top portion in contact with the lid structure and a bottom portion in contact with the circuit substrate.4. The structure according to claim 3 , wherein an adhesive material is located in between the plurality of first spacer structures and the plurality of second spacer structures claim 3 , and spaced apart from the plurality of first spacer structures and the plurality of second spacer structures.5. The structure according to claim 3 , ...

Metal-Bump Sidewall Protection

A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer.

Package contact structure, semiconductor package and manufacturing method thereof

A package contact structure, a semiconductor package and a manufacturing method are provided. The package contact structure includes a conductive feature and a dielectric barrier. The conductive feature includes a first portion and a second portion disposed on the first portion. Materials of the first portion and the second portion are different. The dielectric barrier is sleeved on the first portion and extends to cover at least a part of the second portion. A maximum height of the dielectric barrier is less than a maximum height of the conductive feature.

Package structure and method of fabricating the same

A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.

Package-on-package structure and method of manufacturing package

A package-on-package (PoP) structure includes a first package and a second package stacked on the first package. The first package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes an amorphous layer located on the rear surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is on the active surface of the die and is electrically connected to the conductive structures and the die.

Semiconductor package and manufacturing method thereof

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, and a redistribution structure disposed on the first semiconductor die and the insulating encapsulation. The first semiconductor die includes a first contact region and a first non-contact region in proximity to the first contact region. The first semiconductor die includes a first electrical connector disposed on the first contact region and a first dummy conductor disposed on the first non-contact region, and the first electrical connector is electrically connected to a first integrated circuit (IC) component in the first semiconductor die. The first electrical connector is electrically connected to the redistribution structure, and the first dummy conductor is electrically insulated from the first IC component in the first semiconductor die and the redistribution structure.

Package structure and manufacturing method thereof

A package structure and a manufacturing method thereof are provided. The package structure includes a substrate, a semiconductor package, a thermal conductive gel, a thermal conductive film, and a heat spreader. The semiconductor package has an uneven top surface. The thermal conductive gel covers the uneven top surface of the semiconductor package. The thermal conductive film is over the uneven top surface of the semiconductor package. A thermal conductivity of the thermal conductive film is higher than a thermal conductivity of the thermal conductive gel. The heat spreader is disposed over the thermal conductive film.

Semiconductor device and method of forming the same

A method of forming a semiconductor device includes attaching a first semiconductor device to a first surface of a substrate; forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; and forming an underfill material in the first region.

Connector design for packaging integrated circuits

A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.

Optical transceiver and manufacturing method thereof

An optical transceiver including a photonic integrated circuit component, an electric integrated circuit component and an insulating encapsulant is provided. The photonic integrated circuit component includes at least one optical input/output portion and at least one groove located in proximity of the at least one optical input/output portion. The electric integrated circuit component is disposed on and electrically connected to the photonic integrated circuit component. The insulating encapsulant is disposed on the photonic integrated circuit component and laterally encapsulating the electric integrated circuit component. The at least one groove of the photonic integrated circuit component is revealed by the insulating encapsulant and is adapted for insertion of a photonic device.

Semiconductor device package and methods of manufacture

A method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the TCB head.

Non-volatile germanium memory devices

Method of forming package structure

A package structure and methods of forming a package structure are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is located aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element. The encapsulant laterally encapsulates the second die and the wall structure.

Test structures to determine integrated circuit bonding energies and methods of making and using the same

An embodiment interfacial bonding test structure may include a first substrate having a first planar surface, a second substrate having a second planar surface that is parallel to the first planar surface, a first semiconductor die, and a second semiconductor die, each semiconductor die bonded between the first substrate and the second substrate thereby forming a sandwich structure. The first semiconductor die and the second semiconductor die may be bonded to the first surface with a first adhesive and may be bonded to the second surface with a second adhesive. The first semiconductor die and the second semiconductor die may be displaced from one another by a first separation along a direction parallel to the first planar surface and the second planar surface. The second substrate may include a notch having an area that overlaps with an area of the first separation in a plan view.

Adhesive and thermal interface material on a plurality of dies covered by a lid

Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.

Integrated circuit package and method

In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.

Package structure and method of fabricating the same

A package structure includes a circuit substrate, a semiconductor package, a lid structure and a plurality of first spacer structures. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package, wherein the lid structure is attached to the circuit substrate through an adhesive material. The plurality of first spacer structures is surrounding the semiconductor package, wherein the first spacer structures are sandwiched between the lid structure and the circuit substrate, and includes a top portion in contact with the lid structure and a bottom portion in contact with the circuit substrate.

Method for forming package structure

A method for forming a package structure is provided. The method includes bonding a package component to a substrate through a plurality of first connectors. The package component comprises a first semiconductor die and a second semiconductor die. The method also includes forming a dam structure over the substrate and surrounding the first connectors. A top surface of the dam structure is lower than a bottom surface of the package component. The method further includes filling an underfill layer in a space between the dam structure and the first connectors. In addition, the method includes removing the dam structure after the underfill layer is formed.

Method of fabricating package structure

A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.

Method of forming package structure

A package structure and methods of forming a package structure are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is located aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element. The encapsulant laterally encapsulates the second die and the wall structure.

Semiconductor device and method of forming the same

A method of forming a semiconductor device includes attaching a first semiconductor device to a first surface of a substrate; forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; and forming an underfill material in the first region.

Semiconductor device package and methods of manufacture

A method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the TCB head.

Bridge Die Having Different Surface Orientation Than Ic Dies Interconnected By The Bridge Die

A first integrated circuit (IC) die includes a first substrate. A second IC die includes a second substrate. At least one of the first substrate or the second substrate has a first surface orientation. The first IC die is spaced apart from the second IC die. A third die electrically interconnects the first IC die to the second IC die. The third die includes a third substrate having a second surface orientation. The second surface orientation is different from the first surface orientation.

Integrated Circuit Package and Method

In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.

Chip package structure with anchor structure

A chip package structure is provided. The chip package structure includes a wiring substrate having a first conductive pad. The chip package structure includes a chip structure over the wiring substrate. The chip package structure includes an antiwarpage structure over the wiring substrate. The antiwarpage structure surrounds the chip structure. The chip package structure includes a first anchor structure on the first conductive pad of the wiring substrate and adjacent to a first lower portion of the antiwarpage structure. The first lower portion is between the first anchor structure and the chip structure, and the first anchor structure and the first conductive pad are electrically insulated from the chip structure.

Method of forming package structure and package structure therefrom

A package structure and methods of forming a package structure are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is located aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element. The encapsulant laterally encapsulates the second die and the wall structure.

Integrated circuit package and method of forming same

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Semiconductor device package having metal thermal interface material

A semiconductor device package is provided, including a package substrate, a semiconductor device, a metal lid, and a metal thermal interface material (TIM). The package substrate has a first surface. The semiconductor device is disposed over the first surface of the package substrate. The metal lid is disposed over the semiconductor device and the package substrate. The metal TIM is interposed between the metal lid and the top surface of the semiconductor device for bonding the metal lid and the semiconductor device. A shape of the lateral sidewall of the metal TIM in a longitudinal section is concave arc, and the outermost point of the lateral sidewall is within the boundary of the semiconductor device.

Semiconductor package structure having ring portion with recess for adhesive

A package structure is provided. The package structure includes a substrate, a cover element, a semiconductor device, a protruding element, an adhesive element, and an electrical connector. The cover element is disposed on the substrate and having a recess. The semiconductor device is disposed on the substrate and disposed in the space surrounded by the cover element. The protruding element extends from the substrate and disposed in the recess. The adhesive element is disposed in the recess. The electrical connector is in contact with the substrate and the semiconductor device.

Adhesive and thermal interface material on a plurality of dies covered by a lid

Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.

Semiconductor package structure having ring portion with recess for adhesive and method for forming the same

A package structure is provided. The package structure includes a substrate, a cover element, a semiconductor device, a protruding element, and an adhesive element. The cover element is disposed on the substrate and having a ring portion, a space is surrounded by the ring portion, and a recess is formed on a surface of the ring portion that faces the substrate. The semiconductor device is disposed on the substrate and disposed in the space surrounded by the ring portion, wherein the semiconductor device is spaced apart from the recess by the ring portion. The protruding element extends from the substrate and disposed in the recess. The adhesive element is disposed in the recess, wherein in a top view, the semiconductor device is surrounded by the protruding element.

Chip package structure with anchor structure and method for forming the same

A chip package structure is provided. The chip package structure includes a wiring substrate having a surface. The chip package structure includes a chip structure over the surface of the wiring substrate. The chip package structure includes an antiwarpage structure over the surface of the wiring substrate. The antiwarpage structure surrounds the chip structure. The chip package structure includes a first anchor structure affixed to the surface of the wiring substrate and adjacent to a first lower portion of the antiwarpage structure. The first lower portion is between the first anchor structure and the chip structure, and the first anchor structure is electrically isolated from the chip structure.

Package structures

A package structure includes a semiconductor package, a thermal conductive gel, a thermal conductive film and a heat spreader. The thermal conductive gel is disposed over the semiconductor package. The thermal conductive film is disposed over the semiconductor package and the thermal conductive gel. A thermal conductivity of the thermal conductive film is different from a thermal conductivity of the thermal conductive gel. The thermal conductive film is surrounded by the heat spreader.

Phase-separated type non-volatile memory

Phase change memory device

A phase change memory device is disclosed, including a substrate, a phase change layer over the substrate, a first electrode electrically connecting a first side of the phase change layer, a second electrode electrically connecting a second side of the phase change layer, wherein the phase change layer composes mainly of gallium (Ga), antimony (Sb) and tellurium (Te) and unavoidable impurities, having the composition range of Ga x Te y Sb z , 5<x<40; 8≦y<48; 42<x<80; and x+y+z=100.

Semiconductor device package and methods of manufacture

A method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the TCB head.

Integrated circuit package and method of forming same

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Improved bonding structures for semiconductor devices and methods of forming the same

An embodiment method of forming a hybrid bond between a first semiconductor device component and a second semiconductor device component may include forming the first semiconductor device component including a first electrical bonding structure formed within a first dielectric material; forming the second semiconductor device component including a second electrical bonding structure formed within a second dielectric material; placing the first semiconductor device component and the second semiconductor device component together such that the first electrical bonding structure is in contact with the second electrical bonding structure; performing a first annealing process that forms a direct metal-to-metal bond between the first electrical bonding structure and the second electrical bonding structure; and performing a second annealing process that forms a direct dielectric-to-dielectric bond between the first dielectric material and the second dielectric material.

Semiconductor package and method of manufacturing semiconductor package

A semiconductor package includes a substrate, a package structure, a lid structure, and a thermal spreader layer. The package structure is disposed on the substrate, wherein the package structure includes a plurality of device dies and a filling material filling a gap between adjacent two of the plurality of device dies. The lid structure is disposed over substrate and covering the package structure. The thermal spreader layer is disposed between the lid structure and the package structure, wherein the thermal spreader layer has a profile that is discontinuous in thickness at a gap region corresponding to the gap.

Semiconductor device package having metal thermal interface material

A semiconductor device package is provided, including a package substrate, a semiconductor device, a metal lid, and a metal thermal interface material (TIM). The package substrate has a first surface. The semiconductor device is disposed over the first surface of the package substrate. The metal lid is disposed over the semiconductor device and the package substrate. The metal TIM is interposed between the metal lid and the top surface of the semiconductor device for bonding the metal lid and the semiconductor device. A shape of the lateral sidewall of the metal TIM in a longitudinal section is concave arc, and the outermost point of the lateral sidewall is within the boundary of the semiconductor device.

Method of manufacturing semiconductor package

A manufacturing method of a semiconductor package includes the following steps. A package structure is provided over a substrate, wherein the package structure includes a plurality of device dies and a filling material filling a gap between adjacent two of the plurality of device dies. A thermal spreader layer is provided over the package structure, wherein the thermal spreader layer has a profile that is discontinuous in thickness at a gap region aligned with the gap. A lid structure is provided over the substrate and in contact with the thermal spreader layer.

Method for forming semiconductor device package having metal thermal interface material

A method is provided, including bonding a semiconductor device to a surface of a package substrate; placing a lid over the semiconductor device and the package substrate with a metal thermal interface material (TIM) provided between the lid and the top surface of the semiconductor device; heating the metal TIM to melt the metal TIM; pressing the lid downward so that the molten metal TIM laterally flows beyond the boundary of the semiconductor device, and the shape of the lateral sidewall of the molten metal TIM in a longitudinal section is a convex arc; lifting the lid upward so that the molten metal TIM laterally flows back, and the shape of the lateral sidewall of the molten metal TIM in the longitudinal section is a concave arc; and bonding the lid to the semiconductor device through the metal TIM by cooling the molten metal TIM.