SEMICONDUCTOR COMPONENT HAVING THROUGH-SILICON VIAS AND METHOD OF MANUFACTURE

A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. 1. A semiconductor component comprising:a semiconductor substrate having an opening;a first dielectric liner having a first stress over an interior surface of the opening;a second dielectric liner having a second stress over the first dielectric liner, wherein a direction of the first stress is opposite a direction of the second stress; anda conductive material over the second dielectric liner.2. The semiconductor component of claim 1 , wherein the first dielectric liner has a first thickness adjacent to a top surface of the substrate and a second thickness adjacent to a bottom surface of the substrate claim 1 , and the first thickness is different from the second thickness.3. The semiconductor component of claim 2 , wherein the first thickness ranges from about 200 Angstroms (Å) to about 2000 Å claim 2 , and the second thickness ranges from about 20 Å to about 200 Å.4. The semiconductor component of claim 1 , wherein the second dielectric liner has a first thickness adjacent to a top surface of the substrate and a second thickness adjacent to a bottom surface of the substrate claim 1 , and the first thickness is different from the second thickness.5. The semiconductor component of claim 4 , wherein the first thickness ranges from about 500 Å to about 2500 Å claim 4 , and the second thickness ranges from about 500 Å to about 2500 Å.6. The semiconductor component of claim 1 , further comprising a third dielectric liner between the second dielectric liner and the conductive material claim 1 , the third dielectric liner having a third stress in a same direction as the first stress claim 1 , wherein the third ...

Three-Dimensional Integrated Circuit Structure with Low-K Materials

A device includes an interposer free from active devices therein. The interposer includes a substrate; a through-substrate via (TSV) penetrating through the substrate; and a low-k dielectric layer over the substrate. 1. A device comprising: a substrate;', 'a through-substrate via (TSV) penetrating through the substrate; and', 'a first dielectric layer over the substrate, wherein the first dielectric layer has a first k value lower than about 3.8., 'an interposer free from active devices therein, wherein the interposer comprises2. The device of claim 1 , wherein the first k value is lower than about 3.5.3. The device of claim 1 , wherein the first k value is lower than about 3.0.4. The device of claim 1 , wherein the substrate is a semiconductor substrate comprising silicon.5. The device of claim 1 , wherein the substrate is a dielectric substrate.6. The device of claim 1 , wherein the interposer comprises a plurality of second dielectric layers over the substrate claim 1 , and a redistribution line formed in the plurality of second dielectric layers claim 1 , and wherein at least one of the plurality of second dielectric layers has a second k value lower than about 3.8.7. The device of claim 6 , wherein critical dimension of the redistribution line is greater than about 0.3 μm.8. The device of further comprising:a first die; anda metal bump bonding the first die to a first side of the interposer, wherein the first dielectric layer is between the substrate and the die.9. The device of claim 8 , wherein the first dielectric layer is a top dielectric layer of the interposer.10. The device of claim 8 , wherein the interposer comprises a top dielectric layer formed over the first dielectric layer and having a k value greater than the first k value of the first dielectric layer.11. The device of further comprising an underfill material disposed between the first die and the interposer claim 8 , wherein the first dielectric layer contacts the underfill material.12. The ...

INTEGRATED CIRCUITS INCLUDING CONDUCTIVE STRUCTURES THROUGH A SUBSTRATE AND METHODS OF MAKING THE SAME

An integrated circuit includes a substrate having a first surface and a second surface. At least one conductive structure continuously extends through the substrate. At least one sidewall of the at least one conductive structure is spaced from a sidewall of the substrate by an air gap. 1. An integrated circuit comprising:a substrate having a first surface and a second surface; andat least one conductive structure continuously extending through the substrate, wherein at least one sidewall of the at least one conductive structure is spaced from a sidewall of the substrate by an air gap.2. The integrated circuit of claim 1 , wherein the air gap has a first space adjacent to the first surface and a second space adjacent to the second surface claim 1 , and the first space is larger than the second space.3. The integrated circuit of claim 1 , wherein the air gap is around the at least one conductive structure.4. The integrated circuit of claim 1 , further comprising:at least one dielectric layer disposed around the at least one conductive structure.5. The integrated circuit of claim 1 , wherein the at least one conductive structure comprises at least one through-silicon-via (TSV) structure.6. The integrated circuit of claim 1 , further comprising:an etch-stop layer disposed over the first surface of the substrate, wherein a surface of the at least one conductive layer is not level with a surface of the etch-stop layer.7. The integrated circuit of claim 1 , wherein the at least one conductive structure has a first width adjacent to the first surface and a second width adjacent to the second surface claim 1 , and the second width is larger than the first width.8. An integrated circuit comprising:a substrate having a first surface and a second surface; andat least one conductive structure continuously extending through the substrate, wherein at least one sidewall of the at least one conductive structure is spaced from a sidewall of the substrate by an air gap, the air gap is ...

Through-silicon vias for semicondcutor substrate and method of manufacture

A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.

Apparatus and Methods for End Point Determination in Reactive Ion Etching

Methods and apparatus for performing end point determination. A method includes receiving a wafer into an etch tool chamber for performing an RIE etch; beginning the RIE etch to form vias in the wafer; receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process; providing a virtual metrology model for the RIE etch in the chamber; inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber; executing the virtual metrology model to estimate the current via depth; comparing the estimated current via depth to a target depth; and when the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal. An apparatus for use with the method embodiment is disclosed. 1. A method , comprising:receiving a wafer into an etch tool chamber for performing an RIE etch;beginning the RIE etch to form vias in the wafer;receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process;providing a virtual metrology model for the RIE etch in the chamber;inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber;executing the virtual metrology model to estimate the current via depth;comparing the estimated current via depth to a target depth; andwhen the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal.2. The method of claim 1 , and further comprising:when the comparing indicates the current via depth is not within the predetermined threshold of the target depth, then iteratively repeating the receiving, inputting, executing and comparing while continuing the RIE etch processing until the comparing indicates the current via depth is within the predetermined threshold of the target depth.3. The method of claim 1 , wherein ...

APPARATUS AND METHODS FOR END POINT DETERMINATION IN SEMICONDUCTOR PROCESSING

Methods and apparatus for performing end point determination are disclosed. An embodiment includes an apparatus comprising a process tool and a programmable processor. The process tool has an output for signaling in-situ measurements of physical parameters during processing of a wafer in the process tool, and the process tool has an input for receiving a signal indicating a modification of a recipe for the processing. The programmable processor is for executing a virtual metrology model of the process tool to estimate an estimated characteristic of the wafer achieved during the processing. The estimated characteristic is based on the in-situ measurements and the virtual metrology model. The programmable processor has an output for transmitting the signal when the estimated characteristic exceeds a predetermined threshold based on a target characteristic. 1. An apparatus comprising:a process tool having an output for signaling in-situ measurements of physical parameters during processing of a wafer in the process tool, the process tool having an input for receiving a signal indicating a modification of a recipe for the processing; anda programmable processor for executing a virtual metrology model of the process tool to estimate an estimated characteristic of the wafer achieved during the processing, the estimated characteristic being based on the in-situ measurements and the virtual metrology model, and the programmable processor having an output for transmitting the signal when the estimated characteristic exceeds a predetermined threshold based on a target characteristic.2. The apparatus of further comprising a storage communicatively coupled to the programmable processor claim 1 , the storage storing the virtual metrology model of the process tool.3. The apparatus of claim 1 , wherein the programmable processor is located within the process tool.4. The apparatus of claim 1 , wherein the modification of the recipe includes stopping the processing claim 1 , ...

BUMP WITH PROTECTION STRUCTURE

A semiconductor device includes a bump structure formed on a post-passivation interconnect (PPI) line and surrounded by a protection structure. The protection structure includes a polymer layer and at least one dielectric layer. The dielectric layer may be formed on the top surface of the polymer layer, underlying the polymer layer, inserted between the bump structure and the polymer layer, inserted between the PPI line and the polymer layer, covering the exterior sidewalls of the polymer layer, or combinations thereof. 1. A semiconductor device , comprising:a semiconductor substrate;a passivation layer over the semiconductor substrate;a post-passivation interconnect (PPI) line overlying the passivation layer;a protection structure overlying the passivation layer and the PPI line, wherein the protection structure has an opening at least exposing a portion of the PPI line; anda bump structure formed in the protection structure and electrically connected to the PPI line through the opening of the protection structure;wherein the protection structure comprises a polymer layer, a first dielectric layer formed underlying the polymer layer, and a second dielectric layer formed overlying the passivation layer.2. The semiconductor device of claim 1 , wherein the first dielectric layer is formed of silicon nitride claim 1 , silicon carbide claim 1 , silicon carbonitride claim 1 , silicon oxycarbide claim 1 , tetra-ethyl-ortho-silicate (TEOS) oxide claim 1 , silicon oxide claim 1 , or combinations thereof.3. The semiconductor device of claim 1 , wherein the second dielectric layer is formed of silicon nitride claim 1 , silicon carbide claim 1 , silicon carbonitride claim 1 , silicon oxycarbide claim 1 , tetra-ethyl-ortho-silicate (TEOS) oxide claim 1 , silicon oxide claim 1 , or combinations thereof.4. The semiconductor device of claim 1 , wherein the polymer layer has a thickness greater than 30 μm.5. The semiconductor device of claim 1 , wherein the opening of the ...

Through substrate via structures and methods of forming the same

The embodiments of forming a through substrate via (TSV) structure described enable reducing risk of damaging gate structures due to over polishing of an inter-level dielectric layer (ILD) layer. The TSV structure with a wider opening near one end also enables better gapfill.

TSV Structures and Methods for Forming the Same

A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad. 1. A device comprising:a substrate comprising a front side and a backside;a through-via extending from the backside to the front side of the substrate;a conductive pad on the backside of the substrate and over the through-via, wherein the conductive pad comprises a substantially planar top surface; anda conductive bump having a non-planar top surface over the substantially planar top surface and aligned to the through-via, wherein the conductive bump and the conductive pad are formed of a same material, and wherein no interface is formed between the conductive bump and the conductive pad.2. The device of claim 1 , wherein the top surface of the conductive bump is rounded.3. The device of claim 1 , wherein the conductive bump has a height between about 0.1 μm and about 10 μm.4. The device of claim 1 , wherein the conductive bump has a lateral dimension between about 2.0 μm and about 30 μm.5. The device of claim 1 , wherein the substantially planar top surface is aligned to a portion of the substrate encircling the through-via.6. The device of further comprising a metal-oxide-semiconductor (MOS) device on the front side of the substrate.7. The device of further comprising an under-bump metallurgy (UBM) over the conductive bump and the conductive pad claim 1 , wherein the UBM comprises a first portion over and in contact with the non-planar top surface of the conductive bump claim 1 , and a second portion over and in contact ...

THROUGH-SILICON VIAS FOR SEMICONDCUTOR SUBSTRATE AND METHOD OF MANUFACTURE

A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening. 1. A semiconductor component comprising:a semiconductor substrate having a top surface;an opening extending from the top surface into the semiconductor substrate, wherein the opening comprises an interior surface;a first dielectric liner having a first compressive stress disposed on the interior surface of the opening;a second dielectric liner having a tensile stress disposed on the first dielectric liner;a third dielectric liner having a second compressive stress disposed on the second dielectric liner; 'a conductive material disposed on the metal barrier layer and filling the opening.', 'a metal barrier layer disposed on the third dielectric liner; and'}2. The semiconductor component of claim 1 , wherein the first dielectric liner and the third dielectric liner comprise the same dielectric material.3. The semiconductor component of claim 1 , wherein the first dielectric liner and the third dielectric liner comprise different dielectric materials.4. The semiconductor component of claim 1 , wherein the first compressive stress and the second compressive stress are equal.5. The semiconductor component of claim 1 , wherein the first compressive stress and the second compressive stress differ from each other.6. The semiconductor component of claim 1 , wherein at least one of the first compressive stress and the second ...

METHODS OF FORMING SEMICONDUCTOR STRUCTURES

In a method of forming a semiconductor structure, a through-silicon-via (TSV) opening is formed in a substrate. A dielectric layer is formed to continuously extend over the substrate and into the TSV opening. At least one conductive material is formed over the dielectric layer and in the TSV opening. A portion of the at least one conductive material that is over the dielectric layer is removed to form a TSV structure in the substrate. A metallic line is formed in the dielectric layer. A portion of the substrate is removed, such that the TSV structure continuously extends through the substrate and the dielectric layer. 1. A method of forming a semiconductor structure , the method comprising:forming a through-silicon-via (TSV) opening in a substrate;forming a dielectric layer continuously extending over the substrate and into the TSV opening;forming at least one conductive material over the dielectric layer and in the TSV opening;removing a portion of the at least one conductive material that is over the dielectric layer to form a TSV structure in the substrate;forming a metallic line in the dielectric layer; andremoving a portion of the substrate, such that the TSV structure continuously extends through the substrate and the dielectric layer.2. The method of claim 1 , wherein forming the metallic line comprises:forming a cap layer over the dielectric layer;forming a patterned mask layer over the cap layer, the patterned mask layer covering the TSV structure and exposing a portion of the cap layer;removing the exposed portion of the cap layer and a portion of the dielectric layer by using the patterned mask layer as an etch mask to form an opening in the dielectric layer;removing the patterned mask layer; andforming the metallic line in the opening in the dielectric layer.3. The method of claim 2 , wherein forming the metallic line in the opening in the dielectric layer comprisesforming at least one metallic material over the cap layer and in the opening in the ...

Interconnect Barrier Structure and Method

A system and method for forming through substrate vias is provided. An embodiment comprises forming an opening in a substrate and lining the opening with a first barrier layer. The opening is filled with a conductive material and a second barrier layer is formed in contact with the conductive material. The first barrier layer is formed with different materials and different methods of formation than the second barrier layer so that the materials and methods may be tuned to maximize their effectiveness within the device. 1. A method of manufacturing a semiconductor device , the method comprising:forming a first opening in a substrate, the substrate comprising a first side and a second side opposite the first side;depositing a first barrier layer in the first opening using a first process, wherein the first process has a first step coverage;filling a remainder of the first opening with a conductive material;forming a dielectric layer over the conductive material;forming a second opening in the conductive material to expose at least a portion of the conductive material, the second opening having a different width than the first opening;depositing a second barrier layer in the second opening and in contact with the conductive material using a second process, wherein the second process has a second step coverage smaller than the first step coverage;grinding the second side of the substrate to expose the conductive material; anddepositing a third barrier layer in physical contact with the conductive material within the opening using a third process, wherein the third process has a third step coverage different from the first step coverage.2. The method of claim 1 , wherein the first barrier layer comprises a first material and the second barrier layer comprises a second material different from the first material.3. The method of claim 1 , wherein the first barrier layer is a composite barrier layer.4. The method of claim 3 , wherein the depositing the first barrier layer ...

DEVICE WITH THROUGH-SILICON VIA (TSV) AND METHOD OF FORMING THE SAME

A method includes forming an opening extending from a top surface of a silicon substrate into the silicon substrate to a predetermined depth. The method further includes forming an insulation structure on the silicon substrate along the sidewalls and the bottom of the opening and forming a conductive layer on the insulation structure to fill the opening. A first interface between the insulation structure and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm, and a second interface between the insulation structure and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm. 2. The method of claim 1 , wherein forming the insulation structure comprises:performing a first deposition process to form a first insulation layer adjacent to the silicon substrate, andperforming a second deposition process to form a second insulation layer adjacent to the conductive layer;wherein the second deposition process is different from the first deposition process.3. The method of claim 2 , wherein the first deposition process is a thermal oxidation process.4. The method of claim 3 , wherein the second deposition process includes at least one of a sub-atmospheric chemical vapor deposition (SACVD) process claim 3 , a plasma-enhanced chemical vapor deposition (PECVD) process claim 3 , and a plasma-enhanced atomic layer deposition (PEALD) process.5. The method of claim 4 , wherein the second insulation layer has an isotropic etching rate greater than an isotropic etching rate of the first insulation layer.6. The method of claim 2 , wherein the first deposition process includes at least one of a sub-atmospheric chemical vapor deposition (SACVD) process claim 2 , a plasma-enhanced chemical vapor deposition (PECVD) process claim 2 , and a plasma-enhanced atomic layer deposition (PEALD) process.7. The method of claim 6 , wherein the second deposition process is a thermal oxidation process.8. The method of claim 2 , ...

Cost-Effective TSV Formation

A device includes a substrate having a first surface, and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the substrate. A dielectric layer is disposed over the substrate. A metal pad is disposed in the dielectric layer and physically contacting the TSV, wherein the metal pad and the TSV are formed of a same material, and wherein no layer formed of a material different from the same material is between and spacing the TSV and the metal pad apart from each other. 1. A device comprising:a substrate comprising a first surface, and a second surface opposite the first surface;a through-substrate via (TSV) extending from the first surface to the second surface of the substrate, wherein the TSV is formed of a continuous metallic material;a dielectric liner between the TSV and the substrate, wherein the dielectric liner extends over the first surface of the substrate;a dielectric layer over the substrate, wherein the dielectric layer is on a top surface of the dielectric liner; anda first metal pad in the dielectric layer and physically contacting the TSV, wherein the first metal pad is formed of the continuous metallic material.2. The device of claim 1 , wherein the dielectric layer is on a same side of the substrate as the first surface claim 1 , and wherein the device further comprises a barrier layer continuously extending from a top surface of the dielectric layer to the second surface of the substrate claim 1 , with the barrier layer separating the TSV from the substrate.3. The device of claim 1 , wherein the substrate is a semiconductor substrate claim 1 , and wherein the first metal pad is in a first metal layer immediately over an inter-layer dielectric.4. The device of claim 1 , wherein the substrate is a semiconductor substrate claim 1 , and wherein no active device is formed at the first and the second surfaces of the substrate.5. The device of claim 1 , wherein the substrate is a ...

SEMICONDUCTOR COMPONENT HAVING THROUGH-SILICON VIAS AND METHOD OF MANUFACTURE

A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. 1. A semiconductor component comprising:a semiconductor substrate having an opening;a first dielectric liner having a first stress disposed over an interior surface of the opening;a second dielectric liner having a second stress disposed over the first dielectric liner, wherein a direction of the first stress is opposite a direction of the second stress; anda conductive material disposed over the second dielectric liner.2. The semiconductor component of claim 1 , wherein the first dielectric liner has a first thickness adjacent to a top surface of the substrate and a second thickness adjacent to a bottom surface of the substrate claim 1 , and the first thickness is different from the second thickness.3. The semiconductor component of claim 2 , wherein the first thickness ranges from about 200 Angstroms (Å) to about 2000 Å claim 2 , and the second thickness ranges from about 20 Å to about 200 Å.4. The semiconductor component of claim 1 , wherein the second dielectric liner has a first thickness adjacent to a top surface of the substrate and a second thickness adjacent to a bottom surface of the substrate claim 1 , and the first thickness is different from the second thickness.5. The semiconductor component of claim 4 , wherein the first thickness ranges from about 500 Å to about 2500 Å claim 4 , and the second thickness ranges from about 500 Å to about 2500 Å.6. The semiconductor component of claim 1 , further comprising a third dielectric liner between the second dielectric liner and the conductive material claim 1 , the third dielectric liner having a third stress in a same direction as the first stress claim 1 ...

Interconnect Structure and Method

An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first metallization layer formed over the interlayer dielectric layer, wherein the first metallization layer comprises a first metal line and a dielectric layer formed over the first metallization layer, wherein the dielectric layer comprises a metal structure having a bottom surface coplanr with a top surface of the first metal line. 1. An apparatus comprising:an interlayer dielectric layer formed on a first side of a substrate;a first metallization layer formed over the interlayer dielectric layer, wherein the first metallization layer comprises a first metal line; anda dielectric layer formed over the first metallization layer, wherein the dielectric layer comprises a metal structure having a bottom surface coplanar with a top surface of the first metal line.2. The apparatus of claim 1 , wherein the metal structure is a dual damascene structure comprising:a via portion formed over the first metal line; anda metal line portion formed over the via portion.3. The apparatus of claim 2 , wherein a bottom surface of the via portion is coplanar with a top surface of the first metal line.4. The apparatus of claim 2 , wherein the via portion and the metal line portion are formed in a same dielectric material.5. The apparatus of claim 4 , wherein the dielectric material is a photo sensitive polymer material.6. The apparatus of claim 1 , further comprising:a first side interconnect structure formed over the first metallization layer; anda second side interconnect structure formed over a second side of the substrate, wherein the second side interconnect structure is coupled to the first side interconnect structure through a through via.7. The apparatus of claim 1 , wherein the metal structure is formed of copper.8. A method comprising:forming an interlayer dielectric layer over a first side of a substrate;depositing a first dielectric layer over the interlayer dielectric layer; ...

Through Via Structure and Method

An apparatus comprises a through via formed in a substrate. The through via is coupled between a first side and a second side of the substrate. The through via comprises a bottom portion adjacent to the second side of the substrate, wherein the bottom portion is formed of a conductive material. The through via further comprises sidewall portions formed of the conductive material and a middle portion formed between the sidewall portions, wherein the middle portion is formed of a dielectric material. 1. An apparatus comprising:an interlayer dielectric layer formed on a first side of a substrate;a first metallization layer formed over the interlayer dielectric layer, wherein the first metallization layer comprises a plurality of metal lines formed in a first inter-metal dielectric material; and a bottom portion formed of a conductive material, wherein the bottom portion is adjacent to a second side of the substrate;', 'sidewall portions formed of the conductive material, wherein first terminals of the sidewall portions are coupled to the bottom portion and second terminals of the sidewall portions are coupled to the metal lines of the first metallization layer; and', 'a middle portion formed between the sidewall portions, wherein the middle portion is formed of a dielectric material., 'a through via formed in the substrate, wherein the through via comprises2. The apparatus of claim 1 , wherein the through via comprises:a liner layer formed on sidewalls of a through via trench;a barrier layer formed on the liner layer; anda seed layer formed on the barrier layer.3. The apparatus of claim 1 , wherein a bottom surface of the middle portion is lower than a top surface of the substrate.4. The apparatus of claim 1 , wherein the middle portion is formed of the first inter-metal dielectric material.5. The apparatus of claim 4 , wherein the first inter-metal dielectric material is a photo sensitive polymer material.6. The apparatus of claim 1 , further comprising:a first side ...

SEMICONDUCTOR COMPONENT HAVING THROUGH-SILICON VIAS

A semiconductor component includes a substrate having an opening. The semiconductor component further includes a first dielectric liner in the opening, wherein the first dielectric liner having a thickness Tat a first end of the opening, and a thickness Tat a second end of the opening, and Ris a ratio of Tto T. The semiconductor component further includes a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness Tat the first end of the opening, a thickness Tat the second end of the opening, Ris a ratio of Tto T, and Ris greater than R. 1. A semiconductor component comprising:a substrate having an opening;{'sub': 1', '2', '1', '1', '2, 'a first dielectric liner in the opening, wherein the first dielectric liner having a thickness Tat a first end of the opening, and a thickness Tat a second end of the opening, and Ris a ratio of Tto T; and'}{'sub': 3', '4', '2', '3', '1', '2, 'a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness Tat the first end of the opening, a thickness Tat the second end of the opening, Ris a ratio of Tto Ta, and Ris greater than R.'}2. The semiconductor component of claim 1 , wherein the opening extends through an entirety of the substrate.3. The semiconductor component of claim 1 , further comprising a conductive material surrounded by the second dielectric liner.4. The semiconductor component of claim 1 , wherein the ratio Rranges from about 5 to about 20.5. The semiconductor component of claim 1 , wherein the ratio Rranges from about 1 to about 5.6. The semiconductor component of claim 1 , wherein the second dielectric liner comprises an oxide layer.7. The semiconductor component of claim 1 , wherein the first dielectric liner has an etching rate of about 1 angstrom/minute (A/min) to about 10 Å/min in a HF solution.8. A semiconductor component comprising:a substrate having an opening;{'sub': 1', '2', '1', '1', '2, 'a first ...

Semiconductor Device Having Backside Interconnect Structure on Through Substrate Via and Method of Forming the Same

A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer. 1. A method of forming a semiconductor device , the method comprising:forming a through-substrate via in a substrate;thinning a backside of the substrate to expose a first end of the through-substrate via, the first end having a convex shape protruding from the backside of the substrate;forming an isolation film over the backside of the substrate and the first end of the through-substrate via;removing the isolation film from a topmost surface of the first end of the through-substrate via;depositing a conductive layer on the isolation film and the topmost surface of the first end of the through-substrate via; andpatterning the conductive layer.2. The method of claim 1 , wherein the step of patterning the conductive layer further comprises:forming a patterned mask on the conductive layer;etching the conductive layer; andremoving the patterned mask.3. The method of claim 1 , further comprising forming a patterned passivation layer over the conductive layer claim 1 , the patterned passivation layer exposing a portion of the conductive layer over the through-substrate via.4. The method of claim 1 , wherein after thinning the backside of the substrate claim 1 , a distance between the topmost surface of the first end of the through-substrate via and a topmost surface of the backside of the substrate is in a range of about 1000 Å to about 2 μm.5. The method of claim 1 , wherein after patterning the conductive layer claim 1 , the ...

Semiconductor Device Having Backside Interconnect Structure on Through Substrate Via and Method of Forming the Same

A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer. 1. A semiconductor device comprising:a semiconductor substrate;a through-substrate via extending from a frontside to a backside of the semiconductor substrate and comprising a convex portion protruding from the backside of the semiconductor substrate;an isolation film comprising a first portion formed on a sidewall of the convex portion of the through-substrate via and a second portion formed on the backside of the semiconductor substrate;a conductive layer comprising a first portion formed on a top of the convex portion of the through-substrate via and a second portion formed on the second portion of the isolation film; anda passivation layer partially covering the conductive layer.2. The semiconductor device of claim 1 , wherein the conductive layer comprises a third portion on the first portion of the isolation film.3. The semiconductor device of claim 1 , wherein the passivation layer exposes the first portion of the conductive layer and covers the second portion of the conductive layer.4. The semiconductor device of claim 1 , wherein the conductive layer acts as a redistribution line or a conductive pad.5. The semiconductor device of claim 1 , wherein the conductive layer comprises aluminum or aluminum alloy.6. The semiconductor device of claim 1 , wherein the through-substrate via comprises copper or copper alloy.7. The semiconductor device of claim 1 , wherein the top of the convex portion of the through-substrate via is ...

Self-Alignment for Redistribution Layer

An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value. 1. A method comprising:forming a functional through via (TV) within a die area of a substrate, the functional TV having a first protruding portion extending above a first surface of the substrate by a first height;forming an alignment mark within a die street region of the substrate, the die street region of the substrate surrounding the die area of the substrate, the alignment mark comprising a dummy TV, the dummy TV having a second protruding portion extending above the first surface of the substrate by a second height, the second height being equal to the first height;reducing the first height of the first protruding portion of the functional TV by a first amount; andreducing the second height of the second protruding portion of the dummy TV by a second amount, the second amount being less than the first amount.2. The method of claim 1 , further comprising:before reducing the first height of the first protruding portion of the functional TV and the second height of the second protruding portion of the dummy TV, forming a dielectric layer over the first surface of the substrate, the first protruding portion of the functional TV and the second protruding portion of the dummy TV; andbefore reducing the first height of the first protruding portion of the functional TV and ...

Interconnect Structures for Substrate

A device for use with integrated circuits is provided. The device includes a substrate having a through-substrate via formed therethrough. Dielectric layers are formed over at least one side of the substrate and metallization layers are formed within the dielectric layers. A first metallization layer closest to the through-substrate via is larger than one or more overlying metallization layers. In an embodiment, a top metallization layer is larger than one or more underlying metallization layers. Integrated circuit dies may be attached to the substrate on either or both sides of the substrate, and either side of the substrate may be attached to another substrate, such as a printed circuit board, a high-density interconnect, a packaging substrate, an organic substrate, a laminate substrate, or the like. 1. A semiconductor device comprising:a first substrate having a first side and a second side;a through-substrate via extending through the first substrate from the first side to the second side;a plurality of metallization layers formed over at least one of the first side and the second side and comprising a first metallization layer being in contact with the through-substrate via, the first metallization layer having a thickness larger than one or more overlying metallization layers, wherein each one of the plurality of metallization layers has a different thickness than adjacent ones of the plurality of metallization layers, and wherein the plurality of metallization layers comprises a top metallization layer with an overlying passivation layer, the top metallization layer being larger than one or more underlying metallization layers;a first die electrically connected to the through substrate via through the plurality of metallization layers; anda second die electrically connected to the plurality of metallization layers through the through-substrate via.2. The semiconductor device of claim 1 , further comprising a second substrate connected to the first substrate ...

SEMICONDUCTOR DEVICE HAVING BACKSIDE INTERCONNECT STRUCTURE ON THROUGH SUBSTRATE VIA AND METHOD OF FORMING THE SAME

A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer. 1. A semiconductor device , comprising:a semiconductor substrate;a through-substrate via extending from a frontside to a backside of the semiconductor substrate and comprising a concave surface adjacent to the backside of the semiconductor substrate;an isolation film formed on the backside of the semiconductor substrate without covering the concave surface of the through-substrate via;a conductive layer comprising a first portion formed on the concave surface of the through substrate via and a second portion formed on the isolation film, wherein the first portion is a concave portion; anda passivation layer partially covering the conductive layer.2. The semiconductor device of claim 1 , wherein the second portion of the conductive layer is a planar portion.3. The semiconductor device of claim 1 , wherein the passivation layer covers the first portion of the conductive layer and exposes the second portion of the conductive layer.4. The semiconductor device of claim 1 , wherein the conductive layer acts as a redistribution line or a conductive pad.5. The semiconductor device of claim 1 , wherein the conductive layer comprises aluminum or aluminum alloy.6. The semiconductor device of claim 1 , wherein the through-substrate via comprises copper or copper alloy.7. The semiconductor device of claim 1 , wherein the concave surface is lower than the surface of the isolation film.8. The semiconductor device of claim 1 , further ...

Interconnect Structure and Method of Forming Same

A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer. 1. A device comprising:a dielectric layer on a first side of a semiconductor substrate;a first redistribution line in a first recess in the dielectric layer, the first redistribution line comprising a first layer, the first layer completely filling the first recess;a contact pad in a second recess in the dielectric layer, wherein a width of the contact pad is greater than a width of a first redistribution line, wherein the contact pad comprises a second layer and a third layer over the second layer, wherein the second layer and the first layer are a same material, wherein the second layer and the third layer completely fills the second recess, the second layer and the third layer comprising different materials; anda passivation layer over the dielectric layer.2. The device of further comprising a transistor on a second side of the semiconductor substrate.3. The device of further comprising:a front-side interconnect structure on the second side of the semiconductor substrate; anda through via extending from a conductive feature in the front-side interconnect structure through the semiconductor substrate to the first side of the semiconductor substrate, wherein the contact pad is electrically coupled to the through via.4. The device of claim 3 , wherein the contact pad directly contacts the through via.5. The device of claim 1 , wherein the dielectric layer is interposed between the contact pad and the first side of the semiconductor substrate.6. The device of further comprising a passivation layer over the dielectric layer.7. The device of claim 6 , ...

Interconnection Structure with Confinement Layer

An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad. 1. A semiconductor device comprising:a contact pad disposed over a substrate, wherein the contact pad comprises a first layer of a first conductive material and a second layer of a second conductive material over the first layer, wherein the first conductive material and the second conductive material are made of substantially the same material, wherein the first conductive material has a first average grain size and the second conductive material has a second average grain size that is smaller than the first average grain size;a passivation layer covering the substrate and the contact pad, wherein the passivation layer has an opening exposing the contact pad; anda connector coupled to the contact pad through the opening.2. The semiconductor device of claim 1 , wherein first average grain size is about 3 times to about 5 times as large as the second average grain size.3. The semiconductor device of claim 1 , wherein the second average grain size is in a range from about 0.1 microns to about 0.5 microns.4. The semiconductor device of claim 1 , wherein the first conductive material comprises copper claim 1 , gold claim 1 , palladium claim 1 , nickel claim 1 , gold-nickel alloy claim 1 , ...

Device with Through-Substrate Via Structure and Method for Forming the Same

A device including a first dielectric layer on a semiconductor substrate, a gate electrode formed in the first dielectric layer, and a through-substrate via (TSV) structure penetrating the first dielectric layer and extending into the semiconductor substrate. The TSV structure includes a conductive layer, a diffusion barrier layer surrounding the conductive layer and an isolation layer surrounding the diffusion barrier layer. A capping layer including cobalt is formed on the top surface of the conductive layer of the TSV structure. 1. A device comprising:a semiconductor substrate;a first dielectric layer on the semiconductor substrate;a gate electrode formed in the first dielectric layer;a through-substrate via (TSV) structure penetrating the first dielectric layer and extending into the semiconductor substrate, wherein the TSV structure comprises a conductive layer, a diffusion barrier layer surrounding the conductive layer and an isolation layer surrounding the diffusion barrier layer; anda capping layer comprising cobalt formed on a top surface of the conductive layer of the TSV structure.2. The device of claim 1 , wherein a top surface of the TSV structure is substantially level with the surface of the first dielectric layer.3. The device of claim 1 , wherein the capping layer is formed on a top surface of the diffusion barrier layer of the TSV structure.4. The device of claim 1 , further comprising:a second dielectric layer on the first dielectric layer, the TSV structure and the capping layer; anda contact via formed in the second dielectric layer and electrically connected to the TSV structure.5. The device of claim 4 , wherein the contact via is in physical contact with the capping layer.6. The device of claim 4 , wherein the contact via penetrates the capping layer and is in physical contact with the conductive layer of the TSV structure.7. The device of claim 4 , further comprising an etch stop layer between the first dielectric layer and the second ...

Through Via Structure and Method

A device comprises a via in a substrate comprising a lower via portion with a first width formed of a first conductive material and an upper via portion with a second width greater than the first width, wherein the upper via portion comprises a protection layer formed of the first conductive material and a via fill material portion formed of a second conductive material. 1. A device comprising: a lower via portion with a first width formed of a first conductive material; and', a protection layer formed of the first conductive material; and', 'a via fill material portion formed of a second conductive material., 'an upper via portion with a second width greater than the first width, wherein the upper via portion comprises], 'a via in a substrate comprising2. The device of claim 1 , wherein:the first conductive material is tungsten; andthe second conductive material is copper.3. The device of claim 1 , further comprising:a seam in the lower via portion, wherein the seam is surrounded by the first conductive material.4. The device of claim 1 , wherein:the upper via portion comprises non-vertical sidewalls.5. The device of claim 1 , wherein:the protection layer is a barrier layer between the via fill material portion and the substrate.6. The device of claim 1 , wherein:the lower via portion is formed of a same material from a first sidewall of the lower via portion to a second sidewall of the lower via portion.7. The device of claim 6 , wherein:the same material extends from the lower via portion to the protection layer of the upper via portion.8. A device comprising:a substrate comprising a transistor in a first side of the substrate; a lower portion with a first width formed of a first conductive material, wherein the lower portion is adjacent to a second side of the substrate; and', a protection layer formed of the first conductive material; and', 'a via fill material portion formed of a second conductive material., 'an upper portion with a second width greater than ...

Integrated Circuit Packages and Methods of Forming Same

Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages. 1. A method comprising:forming one or more redistribution layers (RDLs) over a carrier;forming a first connector on a first side of the one or more RDLs;bonding a die to the first side of the one or more RDLs using the first connector;forming an encapsulant on the first side of the one or more RDLs and around the die;after forming the encapsulant, detaching the carrier from the one or more RDLs; andforming a second connector on a second side of the one or more RDLs, the second side being opposite the first side, wherein the second connector is larger than the first connector.2. The method of claim 1 , further comprising:forming a release layer on the carrier;forming a seed layer on the release layer; andforming an under-bump metallurgy (UBM) on the seed layer, wherein the UBM is interposed between the seed layer and the one or more RDLs.3. The method of claim 1 , wherein a portion of the encapsulant is interposed between the die and the one or more RDLs claim 1 , and surrounds the first connector.4. The method of claim 1 , wherein the one or more RDLs comprise first interconnects on the first side of the one or more RDLs and second interconnects on the second side of the one or more RDLs claim 1 , a pitch of the second interconnects being larger than a pitch of the first interconnects.5. The method of claim 4 , wherein the first interconnects and the second interconnects are formed using a dual damascene technique.6. The method of claim 4 , wherein the first ...

METHOD OF MAKING A SEMICONDUCTOR COMPONENT HAVING THROUGH-SILICON VIAS

A method of making a semiconductor component includes etching a substrate to define an opening. The method further includes depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first stress. The method further includes depositing a second dielectric liner over the first dielectric liner, wherein the second dielectric liner has a second stress, and a direction of the first stress is opposite a direction of the second stress. The method further includes depositing a conductive material over the second dielectric liner. 1. A method of making a semiconductor component comprising:etching a substrate to define an opening;depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first stress;depositing a second dielectric liner over the first dielectric liner, wherein the second dielectric liner has a second stress, and a direction of the first stress is opposite a direction of the second stress; anddepositing a conductive material over the second dielectric liner.2. The method of claim 1 , wherein the depositing the first dielectric liner comprises depositing the first dielectric liner having a first thickness ratio claim 1 , the first thickness ratio is determined based on a thickness of the first dielectric liner at a top portion of the opening and a thickness of the first dielectric liner at a bottom portion of the opening.3. The method of claim 2 , wherein the depositing the first dielectric liner comprises depositing the second dielectric liner having a second thickness ratio claim 2 , the second thickness ratio is determined based on a thickness of the second dielectric liner at the top portion of the opening and a thickness of second the dielectric liner at the bottom portion of the opening claim 2 , and the first thickness ratio is different from the second thickness ratio.4. The method of claim 1 , wherein the depositing the first dielectric liner comprises depositing the first dielectric ...

TSV Structure and Method Forming Same

A method includes forming a plurality of dielectric layers over a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and depositing a second liner over the first liner. The second liner extends into the opening. The method further includes filling a conductive material into the opening to form a through-via, and forming conductive features on opposing sides of the semiconductor substrate. The conductive features are electrically interconnected through the through-via. 1. A method comprising:forming a plurality of dielectric layers over a semiconductor substrate;etching the plurality of dielectric layers and the semiconductor substrate to form an opening;depositing a first liner extending into the opening;depositing a second liner over the first liner, wherein the second liner extends into the opening;filling a conductive material into the opening to form a through-via; andforming conductive features on opposite sides of the semiconductor substrate, wherein the conductive features are electrically interconnected through the through-via.2. The method of claim 1 , wherein the depositing the first liner is performed using a non-conformal deposition method.3. The method of claim 2 , wherein the depositing the second liner is performed using a conformal deposition method.4. The method of claim 1 , wherein a bottom of the first liner is higher than a bottom of the opening.5. The method of claim 4 , wherein the bottom of the first liner is level with a top surface of the semiconductor substrate.6. The method of claim 4 , wherein the bottom of the first liner is higher than a top surface of the semiconductor substrate.7. The method of claim 4 , wherein the bottom of the first liner is lower than a top surface of the semiconductor substrate.8. The method of claim 1 , wherein the depositing the first liner comprises depositing a conductive liner claim 1 , ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, an interconnection structure, a through substrate via, an insulating layer, a conductive pillar, a dummy conductive pillar, a passivation layer and a bonding pad. The interconnection structure is disposed over the semiconductor substrate. The through substrate via at least partially extends in the semiconductor substrate along a thickness direction of the semiconductor substrate, and electrically connects to the interconnection structure. The insulating layer is disposed over the interconnection structure. The conductive pillar is disposed in the insulating layer, and electrically connected to the through substrate via. The dummy conductive pillar is disposed in the insulating layer, and laterally separated from the conductive pillar. The passivation layer is disposed over the insulating layer. The bonding pad is disposed in the passivation layer, and electrically connected to the conductive pillar. 1. A semiconductor structure , comprising:a semiconductor substrate;an interconnection structure, disposed over the semiconductor substrate;a through substrate via, penetrating through the semiconductor substrate and the interconnection structure, and electrically connected to the interconnection structure;an insulating layer, disposed over the interconnection structure;a conductive pillar, disposed in the insulating layer, and electrically connected to the through substrate via;a dummy conductive pillar, disposed in the insulating layer, and laterally separated from the conductive pillar;a passivation layer, disposed over the insulating layer; anda bonding pad, disposed in the passivation layer, and electrically connected to the conductive pillar.2. The semiconductor structure of claim 1 , wherein a front surface of the dummy conductive pillar facing away from the interconnection structure is covered by the passivation layer.3. The ...

Device with Through-Substrate Via Structure and Method for Forming the Same

A device including a first dielectric layer on a semiconductor substrate, a gate electrode formed in the first dielectric layer, and a through-substrate via (TSV) structure penetrating the first dielectric layer and extending into the semiconductor substrate. The TSV structure includes a conductive layer, a diffusion barrier layer surrounding the conductive layer and an isolation layer surrounding the diffusion barrier layer. A capping layer including cobalt is formed on the top surface of the conductive layer of the TSV structure. 1. A method of forming a device with a through-substrate via (TSV) structure , comprising:forming a source/drain region at a frontside surface of a semiconductor substrate;forming a first dielectric layer over the source/drain region;forming a contact plug in the first dielectric layer and electrically connected to the source/drain region;forming a second dielectric layer over the first dielectric layer;patterning an opening penetrating the first dielectric layer and the second dielectric layer and extending into the semiconductor substrate;depositing an isolation layer lining a sidewall and a bottom surface of the opening;depositing a diffusion barrier layer over the isolation layer along the sidewall and the bottom surface of the opening;forming a conductive layer over the diffusion barrier to fill the opening; andforming a capping layer comprising cobalt on a top surface of the conductive layer, wherein the capping layer extends from below a top surface of the isolation layer to above the top surface of the isolation layer, and wherein the top surface of the isolation layer is substantially parallel to the frontside surface of the semiconductor substrate.2. The method of claim 1 , wherein forming the capping layer comprises a chemical vapor deposition (CVD) process.3. The method of further comprising forming an etch stop layer between the first dielectric layer and the second dielectric layer.4. The method of claim 3 , wherein the etch ...

Interconnect Structure and Method of Forming Same

An apparatus comprises a dielectric layer formed on a first side of a substrate, a first side interconnect structure comprising a first metal line and a pad formed in the dielectric layer, wherein the pad comprises a bottom portion formed of a first conductive metal and an upper portion formed of a second conductive metal, and wherein sidewalls of the upper portion are surrounded by the bottom portion and a top surface of the pad is coplanar with a top surface of the first metal line and a passivation layer formed over the dielectric layer. 1. An apparatus comprising:a dielectric layer formed on a first side of a substrate; the pad comprises a bottom portion formed of a first conductive metal and an upper portion formed of a second conductive metal, and wherein sidewalls of the upper portion are surrounded by the bottom portion; and', 'a top surface of the pad is substantially level with a top surface of the first metal line; and, 'a first side interconnect structure comprising a first metal line and a pad formed in the dielectric layer, whereina passivation layer formed over the dielectric layer.2. The apparatus of claim 1 , further comprising:a via formed in the substrate and coupled to the pad, wherein the via comprise an end extending to the first side of the substrate.3. The apparatus of claim 1 , wherein:the bottom portion of the pad is formed of copper; andthe upper portion of the pad is formed of nickel.4. The apparatus of claim 1 , further comprising:a second metal line formed in the dielectric layer, wherein a top surface of the pad is substantially level with a top surface of the second metal line.5. The apparatus of claim 1 , further comprising:a bump formed over the pad.6. The apparatus of claim 1 , further comprising:a second side interconnect structure formed over a second side of the substrate, wherein the second side interconnect structure is coupled to the first side interconnect structure through a via formed in the substrate.7. The apparatus of ...

Substrateless Integrated Circuit Packages and Methods of Forming Same

Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages. 1. A device comprising: a first dielectric layer;', 'a first conductive feature extending from a first side of the first dielectric layer to a second side of the first dielectric layer, the first conductive feature having a first width at the first side of the first dielectric layer and a second width at the second side of the first dielectric layer, the first width being greater than the second width;', 'a plurality of second dielectric layers on the first side of the first dielectric layer; and', 'a plurality of second conductive features in the second dielectric layers;, 'an interconnect comprisinga third dielectric layer on the second side of the first dielectric layer; andan under-bump metallurgy (UBM) extending through the third dielectric layer to couple with the first conductive feature.2. The device of claim 1 , further comprising:first connectors coupled to the second conductive features of the interconnect.3. The device of claim 2 , further comprising:a die attached to the first connectors; andan encapsulant on the second dielectric layers of the interconnect, the encapsulant surrounding the die and the first connectors.4. The device of claim 2 , further comprising:second connectors coupled to the UBM, the second connectors being larger than the first connectors.5. The device of claim 4 , further comprising:a package substrate connected to the second connectors.6. The device of claim 4 , wherein a pitch of the first connectors is smaller than a ...

Low Cost and Ultra-Thin Chip on Wafer on Substrate (CoWoS) Formation

Methods of making and an integrated circuit device. An embodiment method includes patterning a first polymer layer disposed over a first copper seed layer, electroplating a through polymer via in the first polymer layer using the first copper seed layer, a via end surface offset from a first polymer layer surface, forming a second polymer layer over the first polymer layer, the second polymer layer patterned to expose the via end surface, and electroplating an interconnect in the second polymer layer to cap the via end surface using a second copper seed layer. 1. An integrated circuit device comprising:a first polymer layer having a first side and a second side;an interconnect structure on the first side of the first polymer layer:a conductive via extending from the interconnect structure to the second side of the first polymer layer, wherein an end of the conductive via contacting the interconnect structure is offset from the first side of the first polymer layer;a seed layer over the conductive via on the second side of the first polymer layer; anda first bump over the seed layer.2. The integrated circuit device of claim 1 , wherein the interconnect structure extends into the first polymer layer.3. The integrated circuit device of claim 1 , wherein the conductive via protrudes from the first side of the first polymer layer.4. The integrated circuit device of claim 1 , wherein the interconnect structure includes a barrier layer and a conductive layer claim 1 , the barrier layer being interposed between the conductive via and the conductive layer.5. The integrated circuit device of claim 1 , wherein the conductive via and the second side of the first polymer layer are coplanar.6. The integrated circuit device of claim 1 , further comprising:one or more second polymer layers directly on the first side of the first polymer layer; anda second bump directly on the second polymer layers, the second bump being electrically coupled to the first bump.7. The integrated ...

Profile of Through Via Protrusion in 3DIC Interconnect

An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.

TSV Structures and Methods for Forming the Same

A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad. 1. A device comprising:a substrate; a conductive pad extending past a first surface of the substrate, wherein the conductive pad comprises a substantially planar top surface; and', 'a conductive bump contacting the conductive pad, wherein the conductive bump comprises a non-planar top surface over the substantially planar top surface, and wherein the conductive bump and the conductive pad are formed of a same material., 'a conductive feature extending through the substrate, wherein the conductive feature comprises2. The device of claim 1 , wherein the non-planar top surface of the conductive bump is rounded.3. The device of claim 1 , wherein no interface is formed between the conductive bump and the conductive pad.4. The device of claim 1 , wherein the conductive bump is aligned with a portion of the conductive feature in the substrate.5. The device of claim 1 , wherein the substantially planar top surface is aligned to a portion of the substrate encircling the conductive feature.6. The device of further comprising an under-bump metallurgy (UBM) over the conductive bump and the conductive pad claim 1 , wherein the UBM comprises a first portion over and in contact with the non-planar top surface of the conductive bump claim 1 , and a second portion over and in contact with the substantially planar top surface of the conductive pad.7. The device of further comprising a solder region over the conductive pad and the conductive ...

SELF-ALIGNMENT FOR REDISTRIBUTION LAYER

An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value. 1. An apparatus , comprising:a substrate comprising a plurality of electronic devices;an interconnect structure formed on a first side of the substrate and interconnecting ones of the plurality of electronic devices;a plurality of dummy through-silicon-vias (TSVs) each extending through the substrate and forming an alignment mark on a second side of the substrate;a plurality of functional TSVs each extending through the substrate and electrically connected to one of the plurality of electronic devices; anda redistribution layer (RDL) formed on the second side of the substrate and interconnecting ones of the plurality of dummy TSVs with ones of the functional TSVs, wherein first step heights over the functional TSVs are less than a predetermined value, and wherein second step heights over the dummy TSVs are greater than the predetermined value.2. The apparatus of wherein the predetermined value is about 1000 Angstroms.3. The apparatus of wherein the first step heights are less than about 700 Angstroms claim 1 , and wherein the second step heights are greater than about 3000 Angstroms.4. The apparatus of wherein the first step heights are each a height difference between a planarized portion of the RDL and an un-planarized portion of the RDL.5. The apparatus of wherein the ...

Robust Through-Silicon-Via Structure

Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material. A through-silicon-via (TSV) structure is formed laterally offset from the interconnect structure by forming a first portion of the TSV structure with a first conductive material and forming a second portion of the TSV structure with a second conductive material. Forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the interconnect features. 1. A semiconductor structure comprising:an interconnect structure comprising a plurality of interconnect features disposed in a dielectric material over a substrate, wherein a first interconnect feature of the plurality of interconnect features comprises a conductive line and a conductive via; and a first conductive layer extending into the substrate;', 'a second conductive layer over the first conductive layer; and', 'a first barrier layer extending between the first conductive layer and the second conductive layer, wherein an interface between the conductive line and the conductive via is substantially level with an interface between the first conductive layer and the first barrier layer., 'a through-silicon-via (TSV) structure laterally offset from the interconnect structure, the TSV structure comprising2. The semiconductor structure of claim 1 , wherein the dielectric material comprises a plurality of dielectric layers.3. The semiconductor structure of claim 2 , wherein the first conductive layer of the TSV structure extends through at least one of the plurality of dielectric layers claim 2 , and wherein the second conductive layer of the TSV structure extends from the first conductive layer through each of the plurality of dielectric layers not penetrated by the ...

Through Via Structure and Method

A method comprises forming a trench extending through an interlayer dielectric layer over a substrate and partially through the substrate, depositing a photoresist layer over the trench, wherein the photoresist layer partially fills the trench, patterning the photoresist layer to remove the photoresist layer in the trench and form a metal line trench over the interlayer dielectric layer, filling the trench and the metal line trench with a conductive material to form a via and a metal line, wherein an upper portion of the trench is free of the conductive material and depositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the trench. 1. A method comprising:forming a trench extending through an interlayer dielectric layer over a substrate and partially through the substrate;depositing a photoresist layer over the trench, wherein the photoresist layer partially fills the trench;patterning the photoresist layer to remove the photoresist layer in the trench and form a metal line trench over the interlayer dielectric layer;filling the trench and the metal line trench with a conductive material to form a via and a metal line, wherein an upper portion of the trench is free of the conductive material; anddepositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the trench.2. The method of claim 1 , further comprising:depositing a liner layer on sidewalls and a bottom of the trench;depositing a barrier layer over the liner layer, wherein the barrier layer is in contact with a top surface of the interlayer dielectric layer; anddepositing a seed layer over the barrier layer.3. The method of claim 2 , wherein:the metal line and the interlayer dielectric layer are separated by the liner layer and the barrier layer.4. The method of claim 1 , wherein:after filling the trench and the metal line trench with the conductive material, the conductive material forms a U-shaped ...

Interconnect Structure and Method of Forming Same

A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer. 1. A device comprising:a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate;a dielectric layer over a second side of the substrate;a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials; anda passivation layer over the dielectric layer.2. The device of claim 1 , further comprising:a via extending through the substrate and partially through the dielectric layer.3. The device of claim 1 , further comprising:a first metal line embedded in the dielectric layer, wherein a bottom of the first metal line is substantially level with a bottom of the pad.4. The device of claim 3 , wherein:a width of the pad is greater than a width of the first metal line.5. The device of claim 3 , further comprising:an isolation region in the substrate; anda second metal line embedded in the dielectric layer, wherein a distance between the first metal line and the isolation region is substantially equal to a distance between the isolation region and the second metal line.6. The device of claim 1 , wherein:the bottom portion of the pad is formed of a first conductive material; andthe upper portion of the pad is formed of a second conductive material, and wherein the upper portion of the pad is of a trapezoidal shape surrounded by the bottom portion of the pad.7. The device of claim 6 , wherein:the first conductive material is copper; andthe second conductive material is nickel.8. The device of claim ...

Singulation and Bonding Methods and Structures Formed Thereby

Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure. 1. A method comprising: etching through a back side of the first semiconductor substrate through the first interconnect structure to expose an adhesive located adjacent to the first interconnect structure; and', 'removing the adhesive; and, 'singulating a first chip, the first chip comprising a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate, the singulating the first chip comprisingafter the singulating the first chip, bonding the first chip to a second chip.2. The method of claim 1 , wherein after the etching claim 1 , an exterior sidewall of the first interconnect structure does not meet an exterior surface of the first interconnect structure most distal from the first semiconductor substrate at an angle of 90°.3. The method of claim 1 , wherein the second chip comprises a second semiconductor substrate and a second interconnect structure on a front side of the second semiconductor substrate claim 1 , the second semiconductor substrate being an unsingulated part of a wafer during the bonding the first chip to the second chip.4. The method of claim 1 , wherein the second chip comprises a second semiconductor substrate and a second interconnect structure on a front side of the second semiconductor substrate claim 1 , the first interconnect structure being bonded to the second interconnect structure when the first chip is bonded to the second chip.5. The method of further comprising:encapsulating the ...

Profile of Through Via Protrusion in 3DIC Interconnect

An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.

Semiconductor device with nanostructures aligned with grating coupler and manufacturing method thereof

A semiconductor device includes a photonic die and an optical die. The photonic die includes a grating coupler and an optical device. The optical device is connected to the grating coupler to receive radiation of predetermined wavelength incident on the grating coupler. The optical die is disposed over the photonic die and includes a substrate with optical nanostructures. Positions and shapes of the optical nanostructures are such to perform an optical transformation on the incident radiation of predetermined wavelength when the incident radiation passes through an area of the substrate where the optical nanostructures are located. The optical nanostructures overlie the grating coupler so that the incident radiation of predetermined wavelength crosses the optical die where the optical nanostructures are located before reaching the grating coupler.

Singulation and Bonding Methods and Structures Formed Thereby

Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.

Low Cost and Ultra-Thin Chip on Wafer on Substrate (CoWoS) Formation

Methods of making and an integrated circuit device. An embodiment method includes patterning a first polymer layer disposed over a first copper seed layer, electroplating a through polymer via in the first polymer layer using the first copper seed layer, a via end surface offset from a first polymer layer surface, forming a second polymer layer over the first polymer layer, the second polymer layer patterned to expose the via end surface, and electroplating an interconnect in the second polymer layer to cap the via end surface using a second copper seed layer. 1. A method of forming an integrated circuit , comprising:patterning a first polymer layer disposed over a first copper seed layer;electroplating a through polymer via in the first polymer layer using the first copper seed layer, a via end surface offset from an uppermost surface of the first polymer layer;forming a second polymer layer over the first polymer layer, the second polymer layer patterned to expose the via end surface; andforming an interconnect over the via end surface.2. The method of claim 1 , further comprising offsetting the via end surface vertically above the uppermost surface.3. The method of claim 1 , further comprising offsetting the via end surface vertically below the uppermost surface.4. The method of claim 1 , further comprising forming a second copper seed layer on exposed surfaces of the second polymer layer.5. The method of claim 1 , further comprising repeating the forming an interconnect to form subsequent interconnects in subsequent polymer layers.6. The method of claim 5 , further comprising forming microbumps in one of the subsequent polymer layers claim 5 , the microbumps electrically coupled to one of the subsequent interconnects.7. The method of claim 6 , further comprising bonding the microbumps to corresponding microbumps on an integrated package claim 6 , the integrated package including one or more dies.8. The method of claim 7 , further comprising applying ultraviolet ...

Interconnect Structures for Substrate

A device for use with integrated circuits is provided. The device includes a substrate having a through-substrate via formed therethrough. Dielectric layers are formed over at least one side of the substrate and metallization layers are formed within the dielectric layers. A first metallization layer closest to the through-substrate via is larger than one or more overlying metallization layers. In an embodiment, a top metallization layer is larger than one or more underlying metallization layers. Integrated circuit dies may be attached to the substrate on either or both sides of the substrate, and either side of the substrate may be attached to another substrate, such as a printed circuit board, a high-density interconnect, a packaging substrate, an organic substrate, a laminate substrate, or the like. 1. A method of forming a device , the method comprising:providing a first substrate;forming a through-substrate via extending through the first substrate, the through-substrate via having a first thickness after the forming the through-substrate via; andforming a first metallization layer in a first dielectric layer on a first side of the first substrate, the first metallization layer being in direct contact with the through-substrate via, the first metallization layer having a second thickness, wherein the forming the first metallization layer further comprises extending the through-substrate via to a third thickness different from the first thickness and smaller than the second thickness.2. The method of claim 1 , further comprising bonding a second substrate to the first substrate claim 1 , wherein the second substrate is located on an opposite side of the first substrate from the first metallization layer.3. The method of claim 1 , further comprising bonding a dummy substrate to the first substrate claim 1 , wherein the dummy substrate is located on the opposite side of the first substrate from the first metallization layer.4. The method of claim 1 , further ...

Robust Through-Silicon-Via Structure

Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material. A through-silicon-via (TSV) structure is formed laterally offset from the interconnect structure by forming a first portion of the TSV structure with a first conductive material and forming a second portion of the TSV structure with a second conductive material. Forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the interconnect features. 1. A method , comprising:forming an interconnect structure comprising a plurality of interconnect features disposed in dielectric material over a substrate, wherein each of the plurality of interconnect features comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material; and forming a first portion of the TSV structure with a first conductive material; and', 'forming a second portion of the TSV structure with a second conductive material;, 'forming a through-silicon-via (TSV) structure laterally offset from the interconnect structure bywherein forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the plurality of interconnect features.2. The method of wherein the dielectric material comprises a plurality of dielectric layers formed over the substrate.3. The method of wherein at least one of the plurality of interconnect features extends through no more than one of the plurality of dielectric layers.4. The method of wherein claim 2 , for at least one of the plurality of interconnect features:the interconnect member extends through a first one of the plurality of dielectric layers;the via extends through a second one of the plurality of ...

Interconnect Structure and Method of Forming Same

An apparatus comprises a dielectric layer formed on a first side of a substrate, a first side interconnect structure comprising a first metal line and a pad formed in the dielectric layer, wherein the pad comprises a bottom portion formed of a first conductive metal and an upper portion formed of a second conductive metal, and wherein sidewalls of the upper portion are surrounded by the bottom portion and a top surface of the pad is coplanar with a top surface of the first metal line and a passivation layer formed over the dielectric layer, wherein the first metal line is embedded in the passivation layer. 1. An apparatus comprising:a dielectric layer formed on a first side of a substrate; the pad comprises a bottom portion formed of a first conductive metal and an upper portion formed of a second conductive metal, and wherein sidewalls of the upper portion are surrounded by the bottom portion; and', 'a top surface of the pad is substantially level with a top surface of the first metal line; and, 'a first side interconnect structure comprising a first metal line and a pad formed in the dielectric layer, whereina passivation layer formed over the dielectric layer, wherein the first metal line is embedded in the passivation layer.2. The apparatus of claim 1 , further comprising:a via formed in the substrate and coupled to the pad, wherein the via comprise an end extending to the first side of the substrate.3. The apparatus of claim 1 , wherein:the bottom portion of the pad is formed of copper; andthe upper portion of the pad is formed of nickel.4. The apparatus of claim 1 , further comprising:a second metal line formed in the dielectric layer, wherein a top surface of the pad is substantially level with a top surface of the second metal line.5. The apparatus of claim 1 , further comprising:a bump formed over the pad.6. The apparatus of claim 1 , further comprising:a second side interconnect structure formed over a second side of the substrate, wherein the second side ...

METHODS OF MAKING INTEGRATED CIRCUITS INCLUDING CONDUCTIVE STRUCTURES THROUGH SUBSTRATES

A method of forming an integrated circuit includes forming at least one opening through a first surface of a substrate. The method further includes forming at least one conductive structure in the at least one opening. The method further includes removing a portion of the substrate to form a processed substrate having the first surface and a second surface opposite the first surface and to expose a portion of the at least one conductive structure adjacent to the second surface. The at least one conductive structure continuously extending from the first surface through the processed substrate to the second surface of the processed substrate, at least one sidewall of the at least one conductive structure spaced from a sidewall of the at least one opening by an air gap. 1. A method of forming an integrated circuit , the method comprising:forming at least one opening through a first surface of a substrate;forming at least one conductive structure in the at least one opening; andremoving a portion of the substrate to form a processed substrate having the first surface and a second surface opposite the first surface and to expose a portion of the at least one conductive structure adjacent to the second surface,the at least one conductive structure continuously extending from the first surface through the processed substrate to the second surface of the processed substrate, at least one sidewall of the at least one conductive structure spaced from a sidewall of the at least one opening by an air gap.2. The method of claim 1 , wherein forming the at least one conductive structure comprises:forming a sacrificial layer on the sidewall of the at least one opening; andsubstantially removing the sacrificial layer to form the air gap between the sidewall of the at least one opening and the at least one sidewall of the at least one conductive structure.3. The method of claim 2 , wherein the sacrificial layer is non-conformal on the sidewall of the at least one opening.4. The ...

Interconnect Structure and Method

An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first photo-sensitive dielectric layer formed over the interlayer dielectric layer, wherein the first photo-sensitive dielectric layer comprises a first metal structure and a second photo-sensitive dielectric layer formed over the first photo-sensitive dielectric, wherein the second photo-sensitive dielectric layer comprises a second metal structure having a bottom surface coplanar with a top surface of the first metal structure. 1. An apparatus comprising:an interlayer dielectric layer formed on a first side of a substrate;a first photo-sensitive dielectric layer formed over the interlayer dielectric layer, wherein the first photo-sensitive dielectric layer comprises a first metal structure; anda second photo-sensitive dielectric layer formed over the first photo-sensitive dielectric, wherein the second photo-sensitive dielectric layer comprises a second metal structure having a bottom surface coplanar with a top surface of the first metal structure.2. The apparatus of claim 1 , wherein: a first via portion; and', 'a first metal line portion over the first via portion., 'the first metal structure is a first dual damascene structure comprising3. The apparatus of claim 2 , wherein: a second via portion; and', 'a second metal line portion over the second via portion., 'the second metal structure is a second dual damascene structure comprising4. The apparatus of claim 3 , wherein:a top surface of the first metal line portion is in direct contact with a bottom surface of the second via portion.5. The apparatus of claim 4 , wherein:the top surface of the first metal line portion is coplanar with a top surface of the first photo-sensitive dielectric layer;the bottom surface of the second via portion is coplanar with a bottom surface of the second photo-sensitive dielectric layer; andthe top surface of the first photo-sensitive dielectric layer is in direct contact with the ...

THROUGH SUBSTRATE VIA STRUCTURES AND METHODS OF FORMING THE SAME

A structure includes a substrate, and an interconnect structure over the substrate. The structure further includes a through-substrate-via (TSV) extending through the interconnect structure and into the substrate, the TSV comprising a conductive material layer. The structure further includes a dielectric layer having a first portion over the interconnect structure and a second portion within the TSV, wherein the first portion and the second portion comprise a same material. The conductive material layer includes a first section separated from substrate by the second portion of the dielectric layer. The conductive material layer further includes a second section over a top surface of the second portion of the dielectric layer. The conductive material layer further includes a third section over the second section, wherein the third section has a width greater than a width of the second section. 1. A structure comprising:a substrate;an interconnect structure over the substrate;a through-substrate-via (TSV) extending through the interconnect structure and into the substrate, the TSV comprising a conductive material layer; and a first section separated from substrate by the second portion of the dielectric layer,', 'a second section over a top surface of the second portion of the dielectric layer, and', 'a third section over the second section, wherein the third section has a width greater than a width of the second section., 'a dielectric layer having a first portion over the interconnect structure and a second portion within the TSV, wherein the first portion and the second portion comprise a same material, wherein the conductive material layer comprises2. The structure of claim 1 , wherein the top surface of the second portion of the dielectric layer is spaced from a top surface of the interconnect structure by a distance ranging from about 2 claim 1 ,000 angstroms to about 20 claim 1 ,000 angstroms.3. The structure of claim 1 , further comprising a metal layer over ...

TSV Structures and Methods for Forming the Same

A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad. 1. A method comprising:forming a first opening from a backside of a substrate, wherein the first opening extends to a front side of the substrate; a substantially planar top surface; and', 'a non-planar top surface smoothly connected to the substantially planar top surface, wherein the non-planar top surface is higher than the planar top surface; and, 'filling the first opening with a conductive material to form a through-via in the first opening, until a portion of the conductive material outside the first opening forms a connector over the substrate and on the backside of the substrate, wherein the connector comprisesforming a metal feature over and in contact with the substantially planar top surface and the non-planar top surface of the connector, wherein the metal feature and the connector comprise different materials.2. The method of claim 1 , wherein filling the first opening and forming the metal feature comprise electro-chemical plating claim 1 , and wherein a same mask is used for filling the first opening and forming the metal feature claim 1 , with the connector and the metal feature plated through an opening in the mask.3. The method of claim 1 , wherein forming the metal feature comprises:plating a nickel-containing layer on the connector, wherein the nickel-containing layer comprises a non-planar portion aligned to the through-via, and a planar portion not aligned to the through-via; andplating a solder ...

Via for Semiconductor Device Connection and Methods of Forming the Same

A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.

Via for Semiconductor Device Connection and Methods of Forming the Same

A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via. 1. A method comprising:bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate;separating the first substrate to form a first component device and a second component device;forming a gap fill material over the first component device, the second component device, and the second substrate;forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; andforming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.2. The method of claim 1 , wherein separating the first substrate comprises:depositing a first hard mask over a top surface of the first substrate;patterning the first hard mask to form a first portion and a second portion; andetching the first substrate to form the first component device and the second component device using the first portion and the second portion as a mask.3. The method of claim 1 , wherein forming the gap fill material comprises:depositing the gap fill ...

Robust Through-Silicon-Via Structure

Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material. A through-silicon-via (TSV) structure is formed laterally offset from the interconnect structure by forming a first portion of the TSV structure with a first conductive material and forming a second portion of the TSV structure with a second conductive material. Forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the interconnect features. 1. A semiconductor structure comprising:a first interconnect feature over a substrate, the first interconnect feature comprising a conductive line and a conductive via; and a first conductive layer extending into the substrate;', 'a second conductive layer over the first conductive layer, wherein a width of the second conductive layer is less than a width of the first conductive layer; and', 'a first barrier layer extending between the first conductive layer and the second conductive layer, wherein an interface between the conductive line and the conductive via is substantially level with an interface between the first conductive layer and the first barrier layer., 'a through-silicon-via (TSV) structure laterally offset from the first interconnect feature, the TSV structure comprising2. The semiconductor structure of claim 1 , further comprising a liner extending along a bottom surface and sidewalls of the first conductive layer claim 1 , wherein a topmost surface of the liner is substantially level with a topmost surface of the first barrier layer.3. The semiconductor structure of claim 1 , wherein the first interconnect feature comprises a second barrier layer claim 1 , and wherein the first barrier layer and the second barrier layer comprise a same material.4. The ...

Interconnection Structure with Confinement Layer

An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.

Interconnect Structure and Method of Forming Same

A method includes depositing a dielectric layer over a substrate, patterning the dielectric layer to form a first opening and a second opening, wherein a width of the second opening is greater than a width of the first opening, forming a first metal layer over the dielectric layer, wherein a planar surface of the first metal layer in the second opening is lower than a top surface of the dielectric layer, forming a second metal layer in a conformal manner over the first metal layer, wherein a material of the first metal layer is different from a material of the second metal layer and applying a polishing process to the first metal layer and the second metal layer until the dielectric layer is exposed.

Profile of Through Via Protrusion in 3DIC Interconnect

An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.

Die stack structure and method of fabricating the same

A die stack structure includes a first die, a dielectric material layer, a first bonding dielectric layer and a second die. The first die has an active surface and a rear surface opposite to the active surface. The first die includes a through-substrate via (TSV) therein. The TSV protrudes from the rear surface of the first die. The dielectric material layer surrounds and wraps around the first die. The first bonding dielectric layer is disposed on a top surface of the dielectric material layer and the rear surface of the first die and covers the TSV, wherein the TSV penetrates through the first bonding dielectric layer. The second die is disposed on the first die and has an active surface and a rear surface opposite to the active surface. The second die has a second bonding dielectric layer and a conductive feature disposed in the second bonding dielectric layer. The first bonding dielectric layer separates the second bonding dielectric layer from the dielectric material layer, and the first die and the second die are bonded through bonding the second bonding dielectric layer with the first bonding dielectric layer and bonding the conductive feature with the TSV.

Through Via Structure

An apparatus comprises a through via formed in a substrate. The through via is coupled between a first side and a second side of the substrate. The through via comprises a bottom portion adjacent to the second side of the substrate, wherein the bottom portion is formed of a conductive material. The through via further comprises sidewall portions formed of the conductive material and a middle portion formed between the sidewall portions, wherein the middle portion is formed of a dielectric material. 1. An apparatus comprising:an interlayer dielectric layer formed on a first side of a substrate, wherein the substrate comprise a plurality of active circuits adjacent to the first side of the substrate;a first metallization layer formed over the interlayer dielectric layer, wherein the first metallization layer comprises a first metal line and a second metal line; and a bottom portion formed of a conductive material, wherein the bottom portion is adjacent to a second side of the substrate;', 'sidewall portions formed of the conductive material, wherein the sidewall portions are connected between the bottom portion and the second metal line; and', 'a middle portion formed between the sidewall portions, wherein the middle portion is formed of a first dielectric material., 'a through via formed in the substrate, wherein the through via comprises2. The apparatus of claim 1 , further comprising:a liner layer on sidewalls of a through via trench, wherein the liner layer is formed of a second dielectric material;a barrier layer on the liner layer; anda seed layer on the barrier layer.3. The apparatus of claim 1 , wherein:a bottom surface of the middle portion is lower than a top surface of the substrate.4. The apparatus of claim 1 , wherein:a top surface of the first metal line is level with a top surface of the second metal line.5. The apparatus of claim 1 , wherein:the first dielectric material is a photo sensitive polymer material.6. The apparatus of claim 1 , further ...

Via for component electrode connection

Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate.

Singulation and Bonding Methods and Structures Formed Thereby

Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure. 1. A structure comprising:a first chip comprising a first semiconductor substrate and a first interconnect structure on front side of the first semiconductor substrate; anda second chip bonded to the first chip, the second chip comprising a second semiconductor substrate and a second interconnect structure on front side of the second semiconductor substrate, an exterior sidewall of the first chip at a bonding interface between the first chip and the second chip meeting the bonding interface at an interior angle of less than 90°.2. The structure of claim 1 , wherein the exterior sidewall of the first chip is an exterior sidewall of the first interconnect structure.3. The structure of claim 1 , wherein a shape of the first chip in a plane parallel to the bonding interface is non-rectangular.4. The structure of claim 1 , further comprising an encapsulant encapsulating the second chip and in physical contact with both the exterior sidewall and the first interconnect structure.5. The structure of claim 1 , further comprising a through substrate via extending through the first chip.6. The structure of claim 5 , further comprising;a via extending through a dielectric layer to be in physical contact with the through substrate via; anda conductive bump in electrical contact with the via.7. A semiconductor device comprising: a first semiconductor substrate; and', 'a first metallization layer adjacent to the first semiconductor substrate, wherein an angle measured from a first ...

Through Via Structure and Method

A method comprises forming a trench extending through an interlayer dielectric layer over a substrate and partially through the substrate, depositing a photoresist layer over the trench, wherein the photoresist layer partially fills the trench, patterning the photoresist layer to remove the photoresist layer in the trench and form a metal line trench over the interlayer dielectric layer, filling the trench and the metal line trench with a conductive material to form a via and a metal line, wherein an upper portion of the trench is free of the conductive material and depositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the trench. 1. A method of forming a semiconductor device , the method comprising:forming a first dielectric layer over a first side of a substrate;forming an opening through the first dielectric layer and into the substrate; andsimultaneously forming a first conductive line and a second conductive line, wherein an entirety of the first conductive line is over an upper surface of the first dielectric layer, wherein the second conductive line extends along sidewalls and a bottom surface of the opening, the second conductive line extending over the upper surface of the first dielectric layer.2. The method of further comprising claim 1 , prior to forming the first conductive line and the second conductive line claim 1 , forming a dielectric liner layer in the opening.3. The method of claim 2 , wherein an upper surface of the dielectric liner layer is level with the upper surface of the first dielectric layer.4. The method of claim 1 , wherein simultaneously forming the first conductive line and the second conductive line comprises:forming a seed layer over the upper surface of the first dielectric layer and along the sidewalls and the bottom surface of the opening;forming a mask layer over the seed layer, the mask layer having openings corresponding to the first conductive line and the second ...

DIE STRUCTURE, DIE STACK STRUCTURE AND METHOD OF FABRICATING THE SAME

Provided is a die structure including a die, a bonding structure, and a protection structure. The die includes a substrate and a metal feature disposed over the substrate. The bonding structure is disposed over the die. The bonding structure includes a bonding dielectric layer and a bonding metal layer disposed in the bonding dielectric layer. The bonding metal layer is electrically connected to the metal feature of the die. The protection structure is disposed between a top portion of the bonding metal layer and a top portion of the bonding dielectric layer. A die stack structure and a method of fabricating the die structure are also provided. 1. A die structure , comprising:a die;a bonding structure disposed over the die, the bonding structure comprising a bonding dielectric layer and a bonding metal layer disposed in the bonding dielectric layer, wherein the bonding metal layer is electrically connected to a metal feature of the die; anda protection structure disposed between a top portion of the bonding metal layer and a top portion of the bonding dielectric layer, wherein a material of the protection structure comprises an insulating material.2. The die structure of claim 1 , wherein a top surface of the protection structure claim 1 , a top surface of the bonding metal layer claim 1 , and a top surface of the bonding dielectric layer are substantially coplanar.3. The die structure of claim 1 , wherein the protection structure has a tapered sidewall claim 1 , a horizontal cross-sectional area of the protection structure gradually decreases in a direction from a top of the protection structure to a bottom of the protection structure.4. The die structure of claim 1 , wherein sidewalls of the protection structure are straight or curved.5. The die structure of claim 1 , wherein the top portion of the bonding metal layer has a tapered sidewall claim 1 , a horizontal cross-sectional area of the top portion of the bonding metal layer gradually decreases in a direction ...

Via for Component Electrode Connection

Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate. 1. A structure comprising:a first metal pad and a second metal pad disposed at an upper surface of a substrate;a first component attached to the first metal pad, the first component comprising a bottom electrode and a top electrode, the bottom electrode attached to the first metal pad, the top electrode electrically coupled to the second metal pad;an encapsulant over the substrate and laterally encapsulating the first component;a first metal via disposed within the encapsulant adjacent the first component, the first metal via disposed directly over and electrically coupled to the first metal pad, the first metal via extending vertically from an upper surface of the encapsulant to a lower surface of the encapsulant, the first metal via having a homogeneous structure; anda conductive bridge coupling the top electrode of the first component to a top portion of the first metal via.2. The structure of claim 1 , wherein the top electrode of the first component is closer to the substrate than the top portion of the first metal via.3. The structure of claim 1 , wherein a first portion of a top surface of the first component is circumscribed by the conductive bridge claim 1 , the first portion being uncovered by the conductive bridge.4. The structure of claim 1 , further comprising a second metal via disposed within the encapsulant adjacent the first component and the first metal via claim 1 , wherein the conductive bridge electrically couples the top electrode of the first component ...

TSV Structure and Method Forming Same

A method includes forming a plurality of dielectric layers over a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and depositing a second liner over the first liner. The second liner extends into the opening. The method further includes filling a conductive material into the opening to form a through-via, and forming conductive features on opposing sides of the semiconductor substrate. The conductive features are electrically interconnected through the through-via. 1. A structure comprising:a semiconductor substrate;a plurality of dielectric layers over the semiconductor substrate;a first conductive feature over the plurality of dielectric layers;a second conductive feature underlying the semiconductor substrate;a through-via penetrating through the semiconductor substrate and the plurality of dielectric layers, wherein the through-via electrically interconnects the first conductive feature and the second conductive feature;a first liner encircling the through-via; anda second liner encircling the first liner, wherein the second liner has a higher density than the first liner.2. The structure of claim 1 , wherein the first liner is in physical contact with a top portion of the through-via claim 1 , and the second liner is in physical contact with a bottom portion of the through-via.3. The structure of claim 2 , wherein a bottom end of the second liner is level with a top surface of the semiconductor substrate.4. The structure of claim 2 , wherein a bottom end of the second liner is higher than a top surface of the semiconductor substrate.5. The structure of claim 2 , wherein a bottom end of the second liner is lower than a top surface of the semiconductor substrate.6. The structure of claim 1 , wherein the first liner comprises silicon oxide claim 1 , and the second liner comprises silicon nitride.7. The structure of claim 1 , wherein the ...

Wafer Bonding Method

In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

Wafer bonding method

In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

Device with through-silicon via (TSV) and method of forming the same

A device with through-silicon via (TSV) and a method of forming the same includes the formation of an opening in a silicon substrate, the formation of a first insulation layer on the sidewalls and bottom of the opening, the formation of a second insulation layer on the sidewalls and bottom of the opening. A first interface between the first insulation layer and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm. A second interface between the second insulation layer and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm.

Semiconductor component having through-silicon vias and method of manufacture

A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner.

Dual damascene process without an etch stop layer

A non-ESL semiconductor interconnection structure and a method of forming the same are provided. The non-ESL semiconductor interconnection structure includes a first low-k dielectric layer comprising a first region and a second region overlying the substrate, a plurality of conductive features in the first low-k dielectric layer, a cap layer on at least a portion of the conductive features, and a dielectric capping layer overlying the first low-k dielectric layer in the second region but not in the first region. The conductive features in the second region have a substantially greater spacing than the conductive features in the first region. The dielectric capping layer preferably has an inherent compressive stress.

Semiconductor device

本發明揭示一種半導體裝置，包括自一半導體基板的一前側延伸至一背側的一基底通孔電極(through-substrate via,TSV)。基底通孔電極包括鄰近於半導體基板背側的一凹陷或突起部。一隔離膜係形成於半導體基板的背側上。一導電層包括形成於基底通孔電極的凹陷或突起部上的第一部，以及形成於隔離膜上的第二部。一鈍化護層係部分覆蓋導電層。

Apparatus and methods for end point determination in reactive ion etching

Methods and apparatus for performing end point determination. A method includes receiving a wafer into an etch tool chamber for performing an RIE etch; beginning the RIE etch to form vias in the wafer; receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process; providing a virtual metrology model for the RIE etch in the chamber; inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber; executing the virtual metrology model to estimate the current via depth; comparing the estimated current via depth to a target depth; and when the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal. An apparatus for use with the method embodiment is disclosed.

Dual damascene process

A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.

Through via structure and method

A device comprises a via in a substrate comprising a lower via portion with a first width formed of a first conductive material and an upper via portion with a second width greater than the first width, wherein the upper via portion comprises a protection layer formed of the first conductive material and a via fill material portion formed of a second conductive material.

Interconnect structure and method of forming same

A method includes depositing a dielectric layer over a substrate, patterning the dielectric layer to form a first opening and a second opening, wherein a width of the second opening is greater than a width of the first opening, forming a first metal layer over the dielectric layer, wherein a planar surface of the first metal layer in the second opening is lower than a top surface of the dielectric layer, forming a second metal layer in a conformal manner over the first metal layer, wherein a material of the first metal layer is different from a material of the second metal layer and applying a polishing process to the first metal layer and the second metal layer until the dielectric layer is exposed.

Substrateless integrated circuit packages and methods of forming same

Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages.

Bi-level resist structure and fabrication method for contact holes on semiconductor substrates

An improved method of etching very small contact holes through dielectric layers used to separate conducting layers in multilevel integrated circuits formed on semiconductor substrates has been developed. The method uses bi-level ARC coatings in the resist structure and a unique combination of gaseous components in a plasma etching process which is used to dry develop the bi-level resist mask as well as etch through a silicon oxide dielectric layer. The gaseous components comprise a mixture of a fluorine containing gas, such as C 4 F 8 , C 5 F 8 , C 4 F 6 , CHF 3 or similar species, an inert gas, such as helium or argon, an optional weak oxidant, such as CO or O 2 or similar species, and a nitrogen source, such as N 2 , N 2 O, or NH 3 or similar species. The patterned masking layer can be used to reliably etch contact holes in silicon oxide layers on semiconductor substrates, where the holes have diameters of about 0.1 micron or less.

Self-alignment for redistribution layer

An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value.

TSV structure and method forming same

A method includes forming a plurality of dielectric layers over a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and depositing a second liner over the first liner. The second liner extends into the opening. The method further includes filling a conductive material into the opening to form a through-via, and forming conductive features on opposing sides of the semiconductor substrate. The conductive features are electrically interconnected through the through-via.

Method of making a semiconductor component having through-silicon vias

A method of making a semiconductor component includes etching a substrate to define an opening. The method further includes depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first stress. The method further includes depositing a second dielectric liner over the first dielectric liner, wherein the second dielectric liner has a second stress, and a direction of the first stress is opposite a direction of the second stress. The method further includes depositing a conductive material over the second dielectric liner.

Substrateless integrated circuit packages and methods of forming same

Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages.

Dual damascene process

A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.

Interconnect structures for substrate

A device for use with integrated circuits is provided. The device includes a substrate having a through-substrate via formed therethrough. Dielectric layers are formed over at least one side of the substrate and metallization layers are formed within the dielectric layers. A first metallization layer closest to the through-substrate via is larger than one or more overlying metallization layers. In an embodiment, a top metallization layer is larger than one or more underlying metallization layers. Integrated circuit dies may be attached to the substrate on either or both sides of the substrate, and either side of the substrate may be attached to another substrate, such as a printed circuit board, a high-density interconnect, a packaging substrate, an organic substrate, a laminate substrate, or the like.

Method of Forming Semiconductor Device Having Backside Interconnect Structure on Through Substrate Via

A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.

Method for forming a through-substrate via (TSV)

Semiconductor structure and manufacturing method thereof

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an interconnect structure disposed over a semiconductor substrate, contact pads disposed on the interconnect structure, a dielectric structure disposed on the interconnect structure and covering the contact pads, bonding connectors covered by the dielectric structure and landing on the contact pads, and a dummy feature covered by the dielectric structure and laterally interposed between adjacent two of the bonding connectors. Top surfaces of the bonding connectors are substantially coplanar with a top surface of the dielectric structure, and the bonding connectors are electrically coupled to the interconnect structure through the contact pads.

Semiconductor structure with through substrate vias and manufacturing method thereof

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, an interconnection structure, through substrate vias, conductive pillars and dummy conductive pillars. The interconnection structure is disposed at a front side of the semiconductor substrate, and comprises a stack of dielectric layers and interconnection elements spreading in the stack of dielectric layers. The through substrate vias separately penetrate through the semiconductor substrate and the stack of dielectric layers. The conductive pillars are disposed at a front side of the interconnection structure facing away from the semiconductor substrate, and respectively in electrical connection with one of the through substrate vias. The dummy conductive pillars are disposed aside the conductive pillars at the front side of the interconnection structure.

Semiconductor structure and manufacturing method thereof

A semiconductor structure including a first die, a second die stacked on the first die, a smoothing layer disposed on the first die and a filling material layer disposed on the smoothing layer. The second die has a dielectric portion and a semiconductor material portion disposed on the dielectric portion. The smoothing layer includes a first dielectric layer and a second dielectric layer, and the second dielectric layer is disposed on the first dielectric layer. The dielectric portion is surrounded by the smoothing layer, and the semiconductor material portion is surrounded by the filling material layer. A material of the first dielectric layer is different from a material of the second dielectric layer and a material of the filling material layer.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a photonic die and an optical die. The photonic die includes a grating coupler and an optical device. The optical device is connected to the grating coupler to receive radiation of predetermined wavelength incident on the grating coupler. The optical die is disposed over the photonic die and includes a substrate with optical nanostructures. Positions and shapes of the optical nanostructures are such to perform an optical transformation on the incident radiation of predetermined wavelength when the incident radiation passes through an area of the substrate where the optical nanostructures are located. The optical nanostructures overlie the grating coupler so that the incident radiation of predetermined wavelength crosses the optical die where the optical nanostructures are located before reaching the grating coupler.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a photonic die and an optical die. The photonic die includes a grating coupler and an optical device. The optical device is connected to the grating coupler to receive radiation of predetermined wavelength incident on the grating coupler. The optical die is disposed over the photonic die and includes a substrate with optical nanostructures. Positions and shapes of the optical nanostructures are such to perform an optical transformation on the incident radiation of predetermined wavelength when the incident radiation passes through an area of the substrate where the optical nanostructures are located. The optical nanostructures overlie the grating coupler so that the incident radiation of predetermined wavelength crosses the optical die where the optical nanostructures are located before reaching the grating coupler.

Method of forming semiconductor device having backside interconnect structure on through substrate via

A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.

Semiconductor Device Having Backside Interconnect Structure on Through Substrate Via

A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.

Method of forming openings for avoiding the arcing effect