Apparatus and Methods for End Point Determination in Reactive Ion Etching

Methods and apparatus for performing end point determination. A method includes receiving a wafer into an etch tool chamber for performing an RIE etch; beginning the RIE etch to form vias in the wafer; receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process; providing a virtual metrology model for the RIE etch in the chamber; inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber; executing the virtual metrology model to estimate the current via depth; comparing the estimated current via depth to a target depth; and when the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal. An apparatus for use with the method embodiment is disclosed. 1. A method , comprising:receiving a wafer into an etch tool chamber for performing an RIE etch;beginning the RIE etch to form vias in the wafer;receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process;providing a virtual metrology model for the RIE etch in the chamber;inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber;executing the virtual metrology model to estimate the current via depth;comparing the estimated current via depth to a target depth; andwhen the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal.2. The method of claim 1 , and further comprising:when the comparing indicates the current via depth is not within the predetermined threshold of the target depth, then iteratively repeating the receiving, inputting, executing and comparing while continuing the RIE etch processing until the comparing indicates the current via depth is within the predetermined threshold of the target depth.3. The method of claim 1 , wherein ...

APPARATUS AND METHODS FOR END POINT DETERMINATION IN SEMICONDUCTOR PROCESSING

Methods and apparatus for performing end point determination are disclosed. An embodiment includes an apparatus comprising a process tool and a programmable processor. The process tool has an output for signaling in-situ measurements of physical parameters during processing of a wafer in the process tool, and the process tool has an input for receiving a signal indicating a modification of a recipe for the processing. The programmable processor is for executing a virtual metrology model of the process tool to estimate an estimated characteristic of the wafer achieved during the processing. The estimated characteristic is based on the in-situ measurements and the virtual metrology model. The programmable processor has an output for transmitting the signal when the estimated characteristic exceeds a predetermined threshold based on a target characteristic. 1. An apparatus comprising:a process tool having an output for signaling in-situ measurements of physical parameters during processing of a wafer in the process tool, the process tool having an input for receiving a signal indicating a modification of a recipe for the processing; anda programmable processor for executing a virtual metrology model of the process tool to estimate an estimated characteristic of the wafer achieved during the processing, the estimated characteristic being based on the in-situ measurements and the virtual metrology model, and the programmable processor having an output for transmitting the signal when the estimated characteristic exceeds a predetermined threshold based on a target characteristic.2. The apparatus of further comprising a storage communicatively coupled to the programmable processor claim 1 , the storage storing the virtual metrology model of the process tool.3. The apparatus of claim 1 , wherein the programmable processor is located within the process tool.4. The apparatus of claim 1 , wherein the modification of the recipe includes stopping the processing claim 1 , ...

HEATING AND HEAT DISSIPATING MULTI-LAYER CIRCUIT BOARD STRUCTURE FOR KEEPING OPERATING TEMPERATURE OF ELECTRONIC COMPONENTS

A heating and heat dissipating multi-layer circuit board structure for keeping operating temperatures of electronic components is provided. The outer layer of the multi-layer printed circuit board is in contact with electronic components. The operating temperatures of electronic components are measured through by a temperature measuring circuit. When the operating temperature of at least one electronic component is lower than a default temperature, the heating circuits corresponding to the electronic components are enabled respectively to heat the electronic components through corresponding heat conduction elements. When the operating temperature of at least one electronic component is higher than another default temperature, the heating circuits corresponding to the electronic components are disabled to transfer the heat from the electronic components to the heat conduction elements automatically. Therefore, the structure achieves the goal of keeping the operating temperature of each electronic component in the corresponding environment. 1. A heating and heat dissipating multi-layer circuit board structure for keeping operating temperatures of electronic components , comprising:at least one electronic component; and a temperature sensing circuit in electrical connection with at least one of the heating circuits or in connection with at least one of the thermal conduction elements configured on the multi-layer PCB to detect a temperature thereof and using the temperature as the operating temperature thereof; and', 'a control circuit in electrical connection with at least one of the heating circuits, wherein', 'when the operating temperature of one of the electronic components measured by the temperature sensing circuit is lower than a first default value corresponding to the electronic component, the heating circuit corresponding to the contact position of the electronic component is enabled, with the corresponding thermal conduction element transferring heat, to ...

Machine learning on overlay virtual metrology

The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.

Machine learning on overlay management

The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and machine learning are used to train a classification that correlates the overlay error source factors with overlay metrology categories. The overlay error source factors include tool signals. The trained classification includes a base classification and a Meta classification.

SYSTEM AND METHOD FOR AUTOMATIC QUALITY CONTROL FOR ASSEMBLY LINE PROCESSES

A system and method is disclosed for a quality control and/or inspection procedure for assembly line processes. The disclosed system and method enable automatic optical inspection of a device during different stages of manufacture as well as in its finished form. The disclosed system and method enable the automatic quality control process to be self-learning, dynamic, and to identify and classify defects in real time. 1. A method for an inspection procedure , the method comprising the steps of:(a) providing a device having a plurality of features;(b) obtaining a first image of the device;(c) providing a second image wherein the second image is a benchmark image for the device;(d) characterizing each of the plurality of features in the first image using a first predetermined criteria;(e) characterizing each of a plurality of features in the second image using the first predetermined criteria;(f) comparing the characterization of one of the plurality of features in the first image with the characterization of the corresponding feature in the second image; and(g) creating an output image comprising the first image with a highlighted area wherein the highlighted area comprises a defect determined from the comparison.2. The method of further comprising the step of:(h) repeating step (f) for each of the plurality of features.3. The method of further comprising the step of:(i) repeating steps (d) through (f) and step (h) using a second predetermined criteria.4. The method of further comprising the steps of:(j) classifying each defect by a type of defect according to a predetermined classification system; and(k) creating a report including a number of defects by type of defect.5. The method of wherein the predetermined classification system includes classifications selected from the group consisting of: bridge claim 4 , cold joint claim 4 , solder void claim 4 , missing bump claim 4 , and die shift.6. The method of further comprising the steps of:(l) correlating a first ...

Machine learning on overlay management

The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.

SEMICONDUCTOR DEVICE PACKAGE

A semiconductor device package includes a first substrate, a second substrate, a first electronic component, a second electronic component and a shielding layer. The second substrate is disposed over the first substrate. The first electronic component is disposed between the first substrate and the second substrate. The second electronic component is disposed between the first substrate and the second substrate and adjacent to the second substrate than the first electronic component. The shielding element electrically connects the second electronic component to the second substrate. The second electronic component and the shielding element define a space accommodating the first electronic component. 1. A semiconductor device package , comprising:a first substrate;a second substrate disposed over the first substrate;a first electronic component disposed between the first substrate and the second substrate; anda second electronic component disposed between the first substrate and the second substrate and adjacent to the second substrate than the first electronic component,a shielding element electrically connect the second electronic component to the second substrate,wherein the second electronic component and the shielding element define a space accommodating the first electronic component.2. The semiconductor device package of claim 1 , wherein the first electronic component and the second electronic component are at least partially overlapped in a direction substantially perpendicular to the first substrate or the second substrate.3. The semiconductor device package of claim 1 , further comprising a first interposer disposed between the first substrate and the second substrate.4. The semiconductor device package of claim 1 , further comprising:a third electronic component disposed between the first electronic component and the third electronic component; anda first compartment shield disposed between the first electronic component and the third electronic component ...

Control apparatus of catheter feeder

The invention is disclosed to a control apparatus of catheter feeder. It comprises two rotatable mechanisms and a transmittal device that can propel the guidewire into continuous motion comprising moving forward, moving backward, moving clockwise, and moving counter-clockwise. The invention comprises of a square frame and three gears that are meshed together and are referred to the first, second, and third gear, respectively. At the front of the third gear are the first and second sets of the idle wheels that can hold the guidewire tightly. The invention employs the mechanical gears to control movement of the guidewire.

The control system of catheter feeder

Heating and heat dissipating multi-layer circuit board structure for keeping operating temperature of electronic components

A heating and heat dissipating multi-layer circuit board structure for keeping operating temperatures of electronic components is provided. The outer layer of the multi-layer printed circuit board is in contact with electronic components. The operating temperatures of electronic components are measured through by a temperature measuring circuit. When the operating temperature of at least one electronic component is lower than a default temperature, the heating circuits corresponding to the electronic components are enabled respectively to heat the electronic components through corresponding heat conduction elements. When the operating temperature of at least one electronic component is higher than another default temperature, the heating circuits corresponding to the electronic components are disabled to transfer the heat from the electronic components to the heat conduction elements automatically. Therefore, the structure achieves the goal of keeping the operating temperature of each electronic component in the corresponding environment.

Apparatus and methods for end point determination in reactive ion etching

Methods and apparatus for performing end point determination. A method includes receiving a wafer into an etch tool chamber for performing an RIE etch; beginning the RIE etch to form vias in the wafer; receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process; providing a virtual metrology model for the RIE etch in the chamber; inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber; executing the virtual metrology model to estimate the current via depth; comparing the estimated current via depth to a target depth; and when the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal. An apparatus for use with the method embodiment is disclosed.

A system and a method for monitoring a process

Heat dissipation structure of expanded and laminated architecture

Semiconductor device package

A semiconductor device package includes a first substrate, a second substrate, a first electronic component, a second electronic component and a shielding layer. The second substrate is disposed over the first substrate. The first electronic component is disposed between the first substrate and the second substrate. The second electronic component is disposed between the first substrate and the second substrate and adjacent to the second substrate than the first electronic component. The shielding element electrically connects the second electronic component to the second substrate. The second electronic component and the shielding element define a space accommodating the first electronic component.

System and method for monitoring a manufacturing process

Es wird ein System und ein Verfahren zur Überwachung eines Fertigungsprozesses bereitgestellt. Ein Wafer wird bereitgestellt. Prozessparameter einer Fn und aufgezeichnet, wenn der Wafer in der Fertigungsmaschine bearbeitet wird. Ein Wafermesswert des Wafers wird gemessen, nachdem der Wafer bearbeitet wurde. Die Prozessparameter werden in einen Prozesssummenwert umgewandelt. Ein zweidimensionaler orthogonaler Graph mit einer ersten Achse, die den Wafermesswert repräsentiert und einer zweiten Achse, die den Prozesssummenwert repräsentiert, wird bereitgestellt. Der zweidimensionale orthogonale Graph beinhaltet eine ringförmige Steurungsbegrenzung. Ein sichtbarer Punkt, der den Wafermesswert und den Prozesssummenwert darstellt, wird auf dem zweidimensionalen orthogonalen Graphen angezeigt. A system and method for monitoring a manufacturing process is provided. A wafer is provided. Process parameters of a Fn and recorded when the wafer is processed in the production machine. A wafer reading of the wafer is measured after the wafer has been processed. The process parameters are converted into a process sum value. A two-dimensional orthogonal graph having a first axis representing the wafer reading and a second axis representing the process sum value is provided. The two-dimensional orthogonal graph includes an annular control boundary. A visible point representing the wafer reading and the process sum value is displayed on the two-dimensional orthogonal graph.

Machine learning on overlay management

The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.

Temperature gain control device and method thereof