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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 38561. Отображено 100.
12-01-2012 дата публикации

Wiring board and method for manufacturing the same

Номер: US20120006592A1
Автор: Makoto Terui, Shigeru Yamada, Shinji OUCHI, Yoshinori Shizuno
Принадлежит: Ibiden Co Ltd

A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

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Номер записи: 1
12-01-2012 дата публикации

Microelectronic packages with dual or multiple-etched flip-chip connectors

Номер: US20120007232A1
Автор: Belgacem Haba
Принадлежит: TESSERA RESEARCH LLC

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

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Номер записи: 2
19-01-2012 дата публикации

Methods of forming semiconductor chip underfill anchors

Номер: US20120012987A1
Автор: Neil McLellan, Roden R. Topacio
Принадлежит: Individual

Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.

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Номер записи: 3
19-01-2012 дата публикации

Conductive Sidewall for Microbumps

Номер: US20120012998A1
Автор: Arvind Chandrasekaran, Christine S. Hay-Riege, Shiqun Gu
Принадлежит: Qualcomm Inc

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

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Номер записи: 4
26-01-2012 дата публикации

Method of fabricating film circuit substrate and method of fabricating chip package including the same

Номер: US20120021600A1
Автор: Dae-Woo Son, Jeong-kyu Ha, Kwan-Jai Lee, Sang-uk Han, Ye-Chung Chung, Yun-young Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of fabricating a film circuit substrate and a method of fabricating a chip package. The method of fabricating a film circuit substrate can include providing a base film including a chip packaging area to package a chip and a separation area to separate the two chip packaging areas from each other, the separation area including a cut area and an uncut area; forming a reserve interconnection pattern having a first height on the base film; and forming an interconnection pattern having a second height that is lower than the first height on the out area by selectively etching the reserve interconnection pattern of the cut area.

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Номер записи: 5
09-02-2012 дата публикации

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

Номер: US20120032298A1
Автор: Hideki Fujii, Kenji Furuya, Yuichi Miyagawa
Принадлежит: Renesas Electronics Corp

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

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Номер записи: 6
23-02-2012 дата публикации

Flexible circuit structure with stretchability and method of manufacturing the same

Номер: US20120043115A1
Автор: Ying-Ching Shih, Yu-Hua Chen
Принадлежит: Industrial Technology Research Institute ITRI

In one example embodiment, a flexible circuit structure with stretchability is provided that includes a flexible substrate, a plurality of flexible bumps formed on the flexible substrate, and a metal layer formed on the plurality of flexible bumps and the flexible substrate.

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Номер записи: 7
01-03-2012 дата публикации

Semiconductor structure having conductive vias and method for manufacturing the same

Номер: US20120049347A1
Автор: Meng-Jen Wang
Принадлежит: Advanced Semiconductor Engineering Inc

A semiconductor structure includes a plurality of thermal vias and a heat dissipation layer disposed at a periphery of a back surface of a lower chip in a stacked-chip package. This arrangement improves solderability of a subsequently-bonded heat sink. Additionally, the thermal vias and the heat dissipation layer provide an improved thermal conduction path for enhancing heat dissipation efficiency of the semiconductor structure. A method for manufacturing the semiconductor structure is also provided.

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Номер записи: 8
01-03-2012 дата публикации

Electronic component mounting method and electronic component mount structure

Номер: US20120052633A1
Автор: Shoji Sakemi
Принадлежит: Panasonic Corp

A challenge to be met by the present invention is to provide an electronic component mounting method and an electronic component mount structure that make it possible to assure bonding strength for an electronic component whose underside is provided with bumps. In electronic component mounting operation during which an electronic component ( 6 ) whose underside is provided with bumps ( 7 ) with solder is mounted on a substrate ( 1 ), a solder bonding material ( 3 ) including solder particles contained in a first thermosetting resin is used for bonding the bumps ( 7 ) to an electrode ( 2 ) formed on the substrate ( 1 ), thereby forming a solder bonding area ( 7 *) where the solder particles and the bumps ( 7 ) are fused and solidified and a first resin reinforcement area ( 3 a *) that reinforces the solder bonding area ( 7 *). Further, an adhesive ( 4 ) containing as a principal component a second thermosetting resin not including solder particles is used for fixing an outer edge ( 6 a ) of the electronic component ( 6 ) to reinforcement points set on the substrate ( 1 ). Even when the solder bonding material ( 3 ) and the bonding agent ( 4 ) are blended together, normal thermal curing of the thermosetting resin is not hindered. Bonding strength can thereby be assured for the electronic component ( 6 ) whose underside is provided with the bumps ( 7 ).

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Номер записи: 9
08-03-2012 дата публикации

Multi-chip package with offset die stacking

Номер: US20120056335A1
Автор: Peter B. Gillingham
Принадлежит: Mosaid Technologies Inc

A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed.

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Номер записи: 10
15-03-2012 дата публикации

Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package

Номер: US20120064666A1
Автор: Shigeru Hosomomi, Yoichiro Hamada
Принадлежит: SUMITOMO METAL MINING CO LTD

A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.

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Номер записи: 11
22-03-2012 дата публикации

Package substrate unit and method for manufacturing package substrate unit

Номер: US20120067635A1
Автор: Hideaki Yoshimura, Hitoshi Suzuki, Hnin Nway San Nang, Kazuya Arai, Kei Fukui, Shinpei Ikegami, Yasuhito Takahashi
Принадлежит: Fujitsu Ltd

A semiconductor chip mounting layer of a package substrate unit includes an insulation layer, a conductive seed metal layer formed on the top surface of the insulation layer, conductive pads formed on the top surface of the conductive seed metal layer, metal posts formed substantially in the central portion on the top surface of the conductive pads, and a solder resist layer that is formed to surround the conductive pads and the metal posts.

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Номер записи: 12
22-03-2012 дата публикации

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

Номер: US20120068319A1
Автор: Daesik Choi, Oh Han Kim, SangMi Park
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate.

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Номер записи: 13
22-03-2012 дата публикации

Integrated circuit packaging system with active surface heat removal and method of manufacture thereof

Номер: US20120068328A1
Автор: Hin Hwa Goh, KANG Chen, Rui Huang, Xusheng Bao, Yung Kuan Hsiao
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.

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Номер записи: 14
22-03-2012 дата публикации

Microsprings Partially Embedded In A Laminate Structure And Methods For Producing Same

Номер: US20120068331A1
Автор: Eric Peeters, Eugene M. Chow
Принадлежит: Palo Alto Research Center Inc

At least one microspring has applied thereover a laminate structure to provide: mechanical protection during handling and wafer processing, a spring spacer layer, strengthening of the anchor between spring and substrate, provision of a gap stop during spring deflection, and moisture and contaminant protection. A fully-formed laminate structure may be applied over the microspring structure or a partly-formed laminate structure may be applied over the microspring structure then cured or hardened. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may remain in place in the final microspring structure or be removed in whole or in part. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structure, forming for example additional structural elements such as a gap stop for the microspring.

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Номер записи: 15
22-03-2012 дата публикации

Semiconductor device having semiconductor member and mounting member

Номер: US20120068362A1
Автор: Syuuichi Kariyazaki
Принадлежит: Renesas Electronics Corp

A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased.

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Номер записи: 16
29-03-2012 дата публикации

Methods of fabricating package stack structure and method of mounting package stack structure on system board

Номер: US20120074586A1
Автор: Eun-Jin Choi, Sun-Kyoung SEO
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

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Номер записи: 17
12-04-2012 дата публикации

Integrated circuit packaging system with interposer interconnections and method of manufacture thereof

Номер: US20120086115A1
Автор: A Leam Choi, HanGil Shin, In Sang Yoon, Kenny Lee
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure; mounting a first-external-package-component to the routing structure; and forming a first-external-package-encapsulation covering the first-external-package-component.

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Номер записи: 18
12-04-2012 дата публикации

Package with embedded chip and method of fabricating the same

Номер: US20120086117A1
Автор: Chiang-Cheng Chang, Hsin-Yi Liao, Shih-Kuang Chiu
Принадлежит: Siliconware Precision Industries Co Ltd

A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified.

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Номер записи: 19
19-04-2012 дата публикации

Pass-through 3d interconnect for microelectronic dies and associated systems and methods

Номер: US20120094443A1
Автор: David S. Pratt, Dewali Ray, Kyle K. Kirby
Принадлежит: Micron Technology Inc

Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.

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Номер записи: 20
17-05-2012 дата публикации

Semiconductor Device And Method Of Manufacturing Semiconductor Device

Номер: US20120119338A1
Автор: Shintaro Yamamichi, Takahito Watanabe, Yoshitaka USHIYAMA
Принадлежит: Renesas Electronics Corp

A semiconductor chip includes a magnetic storage device and includes an electrode pad on a first face. The semiconductor chip is coated with a magnetic shield layer in a state in which at least the electrode pad is exposed. The semiconductor chip is mounted on an interconnect substrate through a bump. At least one of the semiconductor chip and the interconnect substrate includes a convex portion, and the bump is disposed over the convex portion.

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Номер записи: 21
17-05-2012 дата публикации

Microelectronic devices and methods for manufacturing microelectronic devices

Номер: US20120119344A1
Автор: Teck Kheng Lee
Принадлежит: Micron Technology Inc

Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. One such method includes forming a plurality of apertures in a substrate with the apertures arranged in an array, and, after forming the apertures, attaching the substrate to a lead frame having a plurality of pads with the apertures in the substrate aligned with corresponding pads in the lead frame. Another method includes providing a partially cured substrate, coupling the partially cured substrate to a plurality of leads, attaching a microelectronic die to the leads, and electrically connecting the microelectronic die to the leads.

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Номер записи: 22
17-05-2012 дата публикации

Integrated circuit packaging system with connection structure and method of manufacture thereof

Номер: US20120119360A1
Автор: DeokKyung Yang, In Sang Yoon, Jaehyun Lee, Ki Youn Jang, KyungHoon Lee, Seong Won Park, Sungeun Park, YoungChul KIM
Принадлежит: Stats Chippac Pte Ltd

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.

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Номер записи: 23
24-05-2012 дата публикации

Connecting and Bonding Adjacent Layers with Nanostructures

Номер: US20120125537A1
Автор: Andrzej Brud, Mohammad Shafiqul Kabir
Принадлежит: Smoltek AB

An apparatus, comprising two conductive surfaces or layers and a nanostructure assembly bonded to the two conductive surfaces or layers to create electrical or thermal connections between the two conductive surfaces or layers, and a method of making same.

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Номер записи: 24
14-06-2012 дата публикации

Semiconductor Device and Method of Forming an Inductor Within Interconnect Layer Vertically Separated from Semiconductor Die

Номер: US20120146181A1
Автор: Jianmin Fang, KANG Chen, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer.

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Номер записи: 25
21-06-2012 дата публикации

Packaged semiconductor chips with array

Номер: US20120153443A1
Автор: Andrey Grinman, Charles Rosenstein, David Ovrutsky, Vage Oganesian
Принадлежит: Tessera LLC

A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

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Номер записи: 26
21-06-2012 дата публикации

Lead pin for package substrate and semiconductor package printed circuit board including the same

Номер: US20120153473A1
Автор: Sang Yul Lee
Принадлежит: Samsung Electro Mechanics Co Ltd

Disclosed herein is a lead pin for a package substrate including a connection pin, and a head part including a flange part formed at one end of the connection pin and having one surface bonded to the connection pin and a flat part formed at the other surface of the flange part and having at least one groove formed along an outer circumference thereof. According to the present invention, the grooves are formed along the outer circumference of the flat part of the head part of the lead pin to increase a bonding area, thereby making it possible to increase bonding strength of the lead pin.

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Номер записи: 27
21-06-2012 дата публикации

Integrated millimeter wave transceiver

Номер: US20120154238A1
Автор: Jean-François Carpentier, Patrice Garcia, Pierre Busson, Pierre Dautriche, Sebastien Pruvost
Принадлежит: STMICROELECTRONICS SA

A millimeter wave transceiver including a plate forming an interposer having its upper surface supporting an interconnection network and having its lower surface intended to be assembled on a printed circuit board by bumps; an integrated circuit chip assembled on the upper surface of the interposer; antennas made of tracks formed on the upper surface of the interposer; and reflectors on the upper surface of the printed circuit board in front of each of the antennas, the effective distance between each antenna and the reflector plate being on the order of one quarter of the wavelength, taking into account the dielectric constants of the interposed materials.

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Номер записи: 28
21-06-2012 дата публикации

Semiconductor chip assembly and method for making same

Номер: US20120155055A1
Автор: Belgacem Haba, Hiroaki Sato, Ilyas Mohammed, Kiyoaki Hashimoto, Norihito Masuda, Philip Damberg, Teck-Gyu Kang, Wei-Shun Wang, Yoshikuni Nakadaira
Принадлежит: Tessera LLC

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

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Номер записи: 29
28-06-2012 дата публикации

Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution Layer

Номер: US20120161279A1
Автор: Kai Liu, KANG Chen, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die.

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Номер записи: 30
05-07-2012 дата публикации

Semiconductor package and method of fabricating the same

Номер: US20120168919A1
Автор: Joo-yang Eom, Joon-Seo Son
Принадлежит: Individual

A semiconductor package and a method of manufacturing the same, and more particularly, to a package of a power module semiconductor and a method of manufacturing the same. The semiconductor package includes a substrate including a plurality of conductive patterns spaced apart from one another; a plurality of semiconductor chips disposed on the conductive patterns; a connecting member for electrically connecting the conductive patterns to each other, for electrically connecting the semiconductor chips to each other, or for electrically connecting the conductive pattern and the semiconductor chip; and a sealing member for covering the substrate, the semiconductor chips, and the connecting member, wherein a lower surface of the substrate and an upper surface of the connecting member are exposed to the outside by the sealing member.

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Номер записи: 31
05-07-2012 дата публикации

Low cost thermally enhanced hybrid bga and method of manufacturing the same

Номер: US20120168929A1
Автор: Kim-yong Goh
Принадлежит: STMICROELECTRONICS PTE LTD

A semiconductor package is formed having a substrate juxtaposed on at least two sides of a semiconductor die. Both the substrate and the semiconductor die are affixed to a conductive layer that draws heat generated during use of the semiconductor package away from the semiconductor die and the substrate. There are also electrical contacts affixed to the substrate and the semiconductor die. The electrical contacts facilitate electrical connection between the semiconductor die, the substrate, and any external devices or components making use of the semiconductor die. The substrate, semiconductor die, and at least a portion of some of the electrical contacts are enclosed by an encapsulating layer insulating the components. Portions of the electrical contacts not enclosed by the encapsulating layer are affixed to an outside device, such as a printed circuit board.

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Номер записи: 32
19-07-2012 дата публикации

Packaging substrate with conductive structure

Номер: US20120181688A1
Автор: Shih-Ping Hsu
Принадлежит: Individual

A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

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Номер записи: 33
19-07-2012 дата публикации

Interposer

Номер: US20120184116A1
Автор: George Jyh-Shann Chou, Gregory Thomas PAWLIKOWSKI
Принадлежит: Tyco Electronics Corp

An interposer includes a substrate having a first surface and a second surface with vias extending between the first and second surfaces. The interposer also includes a contact array mounted to the first surface that has a plurality of coil-shaped contacts. The contacts have heels terminated to corresponding vias. The contacts have beams defining a mating interface of the interposer configured for mating with an electronic component. The contacts may be conic helix shaped. The beams may include at least one turn. The beams may be free standing from the heel and may be compressible along contact axes toward the first surface of the substrate.

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Номер записи: 34
26-07-2012 дата публикации

Semiconductor chip module, semiconductor package having the same and package module

Номер: US20120187560A1
Автор: Hyeon Ji BAEK, Hyung Ju CHOI, Jong Hyun Kim, Mun Aun HYUN
Принадлежит: Hynix Semiconductor Inc

A semiconductor module comprising a plurality of semiconductor chips where at least one semiconductor chip is laterally offset with respect to a second semiconductor chip, and substantially aligned with a third semiconductor chip such that an electrical connection can be made between an electrical contact in the first semiconductor chip and an electrical contact in the third semiconductor chip.

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Номер записи: 35
02-08-2012 дата публикации

Heatsink for led array light

Номер: US20120193085A1
Автор: Allen Raymond Whittle, James Eldred Whittle
Принадлежит: Individual

A heatsink that includes a plurality of thermally conductive plates coupled to each other in a stacked configuration. Each plate includes a core section and a plurality of protrusions extending radially outwardly from the core section in a direction substantially parallel to the core section. The core section of each plate is in direct contact with the core section of an adjacent plate.

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Номер записи: 36
02-08-2012 дата публикации

Compliant spring interposer for wafer level three dimensional (3d) integration and method of manufacturing

Номер: US20120193776A1
Автор: Koji Shiozaki, Sang Won Yoon
Принадлежит: Toyota Motor Engineering and Manufacturing North America Inc

The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.

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Номер записи: 37
02-08-2012 дата публикации

Semiconductor Package with Embedded Die

Номер: US20120196406A1
Автор: Rajendra D. Pendse
Принадлежит: Stats Chippac Pte Ltd

A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.

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Номер записи: 38
23-08-2012 дата публикации

Electroconductive bonding material, method for bonding conductor, and method for manufacturing semiconductor device

Номер: US20120211549A1
Автор: Kuniko Ishikawa, Masayuki Kitajima, Takashi Kubota, Takatoyo Yamakami
Принадлежит: Fujitsu Ltd

An electro-conductive bonding material includes: metal components of a high-melting-point metal particle that have a first melting point or higher; a middle-melting-point metal particle that has a second melting point which is first temperature or higher, and second temperature or lower, the second temperature is lower than the first melting point and higher than the first temperature; and a low-melting-point metal particle that has a third melting point or lower, the third melting point is lower than the first temperature.

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Номер записи: 39
30-08-2012 дата публикации

Semiconductor device and noise suppressing method

Номер: US20120217653A1
Автор: Hisashi Ishida, Koichi Takemura
Принадлежит: NEC Corp

A first semiconductor chip ( 200 ) is mounted on a second semiconductor chip ( 100 ). The first semiconductor chip ( 200 ) has a first conductor pattern ( 222 ). The second semiconductor chip ( 100 ) has a second conductor pattern ( 122 ). The second conductor pattern ( 122 ) is formed at a region overlapping the first conductor pattern ( 222 ) in a plan view. At least one element selected from a group consisting of the first conductor pattern ( 222 ) and the second conductor pattern ( 122 ) has a repetitive structure.

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Номер записи: 40
06-09-2012 дата публикации

Package 3D Interconnection and Method of Making Same

Номер: US20120225522A1
Автор: Rezaur Rahman Khan, Sam Ziqun Zhao
Принадлежит: Broadcom Corp

A method of manufacturing an integrated circuit (IC) package is provided. The method includes stacking an interposer substrate and a device structure, the interposer substrate having a first plurality of contact members formed on a first surface of the interposer substrate and the device structure having a second plurality of contact members that are exposed at a surface of the device structure, and laminating the interposer substrate and the device structure such that the first plurality of contact members are physically and electrically coupled to the second plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the second plurality of contact members.

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Номер записи: 41
06-09-2012 дата публикации

Method for Attaching Wide Bus Memory and Serial Memory to a Processor within a Chip Scale Package Footprint

Номер: US20120225523A1
Автор: Kurt Wachtler, Margaret Rose Simmons-Matthews
Принадлежит: Texas Instruments Inc

A method for forming a semiconductor device includes physically attaching a first semiconductor die to front surface of a first substrate. The first die is electrically connected to routings on front surface of the first substrate. The routings are electrically connected with conductive pads on back surface of the first substrate. A second semiconductor die is physically attached to front surface of a second substrate. The die is electrically connected to routings on front surface of second substrate. These routings are electrically connected with conductive pads on front surface of the second substrate. A third semiconductor die is physically attached to the second die. The third die is electrically attached to the second die through a plurality of through substrate vias (TSVs) within the second die. The conductive pads on back surface of first substrate are electrically connected to the conductive pads on front surface of second substrate.

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Номер записи: 42
20-09-2012 дата публикации

Wiring substrate and method of manufacturing the same

Номер: US20120234589A1
Автор: Akihiko Tateiwa, Jun Furuichi, Naoyuki Koizumi
Принадлежит: Shinko Electric Industries Co Ltd

A wiring substrate includes a structure in which a plurality of wiring layers are stacked through insulating layers intervening therebetween, and which has a first surface side and a second surface side, the first surface side where a semiconductor element is to be mounted, the second surface side being located at an opposite side to the first surface side, an interposer buried in an outermost one of the insulating layers located at the first surface side, and electrically connected to the semiconductor element to be mounted, and a sheet-shaped member buried in an outermost one of the insulating layers located at the second surface side, wherein, the interposer and the sheet-shaped member are disposed at symmetrical positions symmetrical each other.

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Номер записи: 43
27-09-2012 дата публикации

Signal routing Optimized IC package ball/pad layout

Номер: US20120241208A1
Автор: Holger Petersen
Принадлежит: Dialog Semiconductor GmbH

This invention provides layout schemes for ball/pad regions on a printed circuit board for a small regular ball/pad region grid that provides additional space between ball/pad regions for increased wiring capability. The layout scheme is consistent with printed circuit board manufacturing requirements and minimum wiring channel requirements demanded by high density integrated circuit chips.

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Номер записи: 44
27-09-2012 дата публикации

System and method for improving frequency response

Номер: US20120241876A1
Автор: Charles A. Still
Принадлежит: Autoliv ASP Inc

An electrical system and method for making the same includes a main circuit board and a plurality of contact pads located on a surface of the main circuit board. The contact pads are electrically conductive. Additionally, an integrated circuit package having at least one electrical device is attached to the surface of the main circuit board. A ball grid array made from a plurality of solder balls is located on a bottom side of the integrated circuit package. The ball grid array has a plurality of solder balls being electrically conductive and in electrical communication with the at least one electrical device. The solder balls further include solder balls of different material properties.

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Номер записи: 45
04-10-2012 дата публикации

Coreless layer laminated chip carrier having system in package structure

Номер: US20120247822A1
Автор: James W. Fuller, Jr., Jeffrey Knight, Kostas I. Papathomas, Voya R. Markovich
Принадлежит: Endicott Interconnect Technologies Inc

A substrate for use in a laminated chip carrier (LCC) and a system in package (SiP) device having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can include thermoset and thermoplastic resin.

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Номер записи: 46
01-11-2012 дата публикации

Chip-packaging module for a chip and a method for forming a chip-packaging module

Номер: US20120273957A1
Автор: Thorsten Meyer
Принадлежит: INFINEON TECHNOLOGIES AG

A chip-packaging module for a chip is provided, the chip-packaging module including an isolation material configured to cover a chip on at least one side, the isolation material having a first surface proximate to a first side of a chip, and said isolation material having a second surface facing an opposite direction to the first surface; and at least one layer in connection with the chip first side, the at least one layer further configured to extend from the chip first side to the second surface of the isolation material.

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Номер записи: 47
08-11-2012 дата публикации

Manufacturing method of semiconductor device

Номер: US20120282737A1
Автор: Tetsuharu TANOUE
Принадлежит: Individual

Performing electrolysis plating to a wiring is made possible, aiming at the increasing of pin count of a semiconductor device. Package substrate 3 by which ring shape common wiring 3 p for electric supply was formed in the inner area of bonding lead 3 j in device region 3 v of main surface 3 a is used. Since a plurality of first plating lines 3 r and fourth plating lines 3 u for electric supply connected to common wiring 3 p can be arranged by this, the feeder for electrolysis plating can be arranged to all the land parts on the back. Hereby, it becomes possible to perform electrolysis plating to the wiring of main surface 3 a of package substrate 3 , and the back surface.

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Номер записи: 48
22-11-2012 дата публикации

Stacked semiconductor package

Номер: US20120292787A1
Автор: Jong Hyun Nam
Принадлежит: Hynix Semiconductor Inc

A stacked semiconductor package includes a substrate having an upper surface and a lower surface, and divided into a first region and a second region that adjoins the first region; a support member formed in the second region on the upper surface of the substrate; and a semiconductor chip module including a plurality of semiconductor chips each of which has bonding pads near one edge of a first surface thereof and which are stacked on the support member in a step-like shape such that their bonding pads face the first region and are bent such that the bonding pads are electrically connected with the substrate.

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Номер записи: 49
29-11-2012 дата публикации

Pad structure, circuit carrier and integrated circuit chip

Номер: US20120299192A1
Автор: Yeh-Chi Hsu, Yu-Kai Chen
Принадлежит: Via Technologies Inc

A pad structure is suitable for a circuit carrier or an integrated circuit chip. The pad structure includes an inner pad, a conductive via and an outer pad. The conductive via connects the inner pad. The outer pad connects the conductive via and further connects a conductive ball or a conductive bump. The outer diameter of the outer pad is greater than the outer diameter of the inner pad.

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Номер записи: 50
13-12-2012 дата публикации

Impedence controlled packages with metal sheet or 2-layer rdl

Номер: US20120313228A1
Автор: Belgacem Haba, Ellis Chau, Philip Damberg, Richard DeWitt Crisp, Wael Zohni
Принадлежит: Tessera LLC

A microelectronic assembly includes an interconnection element, a conductive plane, a microelectronic device, a plurality of traces, and first and second bond elements. The interconnection element includes a dielectric element, a plurality of element contacts, and at least one reference contact thereon. The microelectronic device includes a front surface with device contacts exposed thereat. The conductive plane overlies a portion of the front surface of the microelectronic device. Traces overlying a surface of the conductive plane are insulated therefrom and electrically connected with the element contacts. The traces also have substantial portions spaced a first height above and extending at least generally parallel to the conductive plane, such that a desired impedance is achieved for the traces. First bond element electrically connects the at least one conductive plane with the at least one reference contact. Second bond elements electrically connect device contacts with the traces.

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Номер записи: 51
13-12-2012 дата публикации

Semiconductor package

Номер: US20120313265A1
Автор: Norio Yamanishi
Принадлежит: Shinko Electric Industries Co Ltd

A semiconductor package includes a plurality of connection pads, which are electrically connected to connection terminals of a mounted component that is mounted on the semiconductor package, and recognition marks. The recognition marks are formed respectively within the area of each of at least two of the connection pads. Each recognition mark has an area that is smaller than the area of the connection mark in which it is formed.

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Номер записи: 52
20-12-2012 дата публикации

Flip chip assembly process for ultra thin substrate and package on package assembly

Номер: US20120319276A1
Автор: A. Vethanayagam Rudge, Bok Sim Lim, Kang Eu Ong, Mun Leong Loke, Sih Fei Lim, Tean Wee One, Weng Khoon Mong
Принадлежит: Individual

In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.

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Номер записи: 53
20-12-2012 дата публикации

Module substrate, module-substrate manufacturing method, and terminal connection substrate

Номер: US20120320536A1
Автор: Issei Yamamoto
Принадлежит: Murata Manufacturing Co Ltd

In a module substrate, a plurality of terminal connection substrates each including an insulator and a plurality of columnar terminal electrodes arranged on a single lateral surface or both lateral surfaces of the insulator is mounted on a single side of a composite substrate such that at least one of the terminal connection substrates extends over a border between a plurality of neighboring module substrates. The composite substrate, in which the plurality of terminal connection substrates is mounted on the single side and a plurality of electronic components is mounted on at least the single side, is divided at a location where the module substrates are to be cut from the composite substrate.

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Номер записи: 54
27-12-2012 дата публикации

Integrated circuit packaging system with interconnects and method of manufacture thereof

Номер: US20120326281A1
Автор: Reza Argenty Pagaila
Принадлежит: Stats Chippac Pte Ltd

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit to the substrate; attaching a vertical interconnect over the substrate; forming an encapsulation on the substrate and covering the vertical interconnect; and forming a rounded cavity, having a curved side, in the encapsulation with the vertical interconnect exposed in the rounded cavity.

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Номер записи: 55
27-12-2012 дата публикации

Low profile package and method

Номер: US20120326300A1
Автор: Anindya Poddar, Ashok S. Prabhu, Hau T. Nguyen, Tao Feng, Will K. Wong
Принадлежит: National Semiconductor Corp

In a method aspect, a multiplicity of ICs are attached to routing on a structurally supportive carrier (such as a wafer). The dice are encapsulated and then both the dice and the encapsulant layer are thinned with the carrier in place. A second routing layer is formed over the first encapsulant layer and conductive vias are provided to electrically couple the first and second routing layers as desired. External I/O contacts (e.g. solder bumps) are provided to facilitate electrical connection of the second routing layer (or a subsequent routing layer in stacked packages) to external devices. A contact encapsulant layer is then formed over the first encapsulant layer and the second routing layer in a manner that embeds the external I/O contacts at least partially therein. After the contact encapsulant layer has been formed, the carrier itself may be thinned significantly and singulated to provide a number of very low profile packages. The described approach can also be used to form stacked multi-chip packages.

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Номер записи: 56
03-01-2013 дата публикации

Method of manufacturing semiconductor device

Номер: US20130001274A1
Автор: Jumpei Konno, Kazunori Hasegawa, Michiaki Sugiyama, Nobuhiro Kinoshita, Takafumi Nishita
Принадлежит: Renesas Electronics Corp

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W 1 and a narrow part (a second portion) with a second width W 2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

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Номер записи: 57
03-01-2013 дата публикации

Bump-on-trace (bot) structures

Номер: US20130001778A1
Автор: Han-Ping Pu, Tin-Hao Kuo, Yu-feng Chen, Yuh Chern Shieh
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

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Номер записи: 58
17-01-2013 дата публикации

Circuit board, semiconductor device, process for manufacturing circuit board and process for manufacturing semiconductor device

Номер: US20130015582A1
Автор: Daisuke Fujiwara, Masayoshi Kondo, Natsuki Makino, Yuka Ito
Принадлежит: Sumitomo Bakelite Co Ltd

A circuit board ( 1 ) exhibits an average coefficient of thermal expansion (A) of the first insulating layer ( 21 ) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point of equal to or higher than 3 ppm/degrees C. and equal to or lower than 30 ppm/degrees C. Further, an average coefficient of thermal expansion (B) of the second insulating layer ( 23 ) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point is equivalent to an average coefficient of thermal expansion (C) of the third insulating layer ( 25 ) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point. (B) and (C) are larger than (A), and a difference between (A) and (B) and a difference between (A) and (C) are equal to or higher than 5 ppm/degrees C. and equal to or lower than 35 ppm/degrees C.

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Номер записи: 59
31-01-2013 дата публикации

Integrated circuit package including a direct connect pad, a blind via, and a bond pad electrically coupled to the direct connect pad

Номер: US20130026642A1
Автор: Kenneth Robert Rhyner, Peter R. Harper
Принадлежит: Texas Instruments Inc

An integrated circuit package including a semiconductor die and a flexible circuit (flex circuit), and a method for forming the integrated circuit package. The flex circuit can include a direct connect pad which is not electrically coupled to an active trace, a blind via electrically coupled to the direct connect pad, and a semiconductor die having a bond pad which is electrically coupled to the direct connect pad using a conductor. The bond pad, the conductor, the direct connect pad, and the blind via can all be vertically aligned, each with the other.

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Номер записи: 60
31-01-2013 дата публикации

Semiconductor device

Номер: US20130026652A1
Автор: Seiya Fujii
Принадлежит: Elpida Memory Inc

A semiconductor device which has a plurality of semiconductor chips stacked on a substrate. The semiconductor device includes semiconductor chip 2 , semiconductor chip 3 a stacked on substrate 4 together with semiconductor chip 2 , and having a foot print larger than semiconductor chip 2 , through electrode 22 extending through semiconductor chip 2 only in a central portion of semiconductor chip 2 , through electrode 32 extending through semiconductor chip 3 a at a position facing to through electrode 22 , and conduction bump 7 b arranged between through electrode 22 and through electrode 32 , and conductively connecting through electrode 22 with through electrode 32.

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Номер записи: 61
31-01-2013 дата публикации

TCE Compensation for Package Substrates for Reduced Die Warpage Assembly

Номер: US20130029457A1
Автор: Margaret Simmons-Matthews
Принадлежит: Texas Instruments Inc

A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages.

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Номер записи: 62
14-02-2013 дата публикации

Semiconductor assemblies with multi-level substrates and associated methods of manufacturing

Номер: US20130037949A1
Автор: Chin Hui Chong, Hong Wan Ng
Принадлежит: Micron Technology Inc

Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. In one embodiment, a substrate for carrying a semiconductor die includes a first routing level, a second routing level, and a conductive via between the first and second routing levels. The conductive via has a first end proximate the first routing level and a second end proximate the second routing level. The first routing level includes a terminal and a first trace between the terminal and the first end of the conductive via. The second routing level includes a second trace between the second end of the conductive via and a ball site. The terminal of the first routing level and the ball site of the second routing level are both accessible for electrical connections from the same side of the substrate.

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Номер записи: 63
14-02-2013 дата публикации

Fabrication method of packaging substrate having through-holed interposer embedded therein

Номер: US20130040427A1
Автор: Dyi-chung Hu, Tzyy-Jang Tseng, Yu-Shan Hu
Принадлежит: Unimicron Technology Corp

A packaging substrate having a through-holed interposer embedded therein and a fabrication method of the packaging substrate are provided, where the packaging substrate includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer.

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Номер записи: 64
28-02-2013 дата публикации

Power Module and Manufacturing Method Thereof

Номер: US20130049201A1
Автор: Akihiro Muramoto, Isamu Yoshida, Michiaki Hiyoshi, Takehide Yokozuka
Принадлежит: HITACHI LTD

A power module includes a substrate having a surface on which a plurality of wiring patterns are formed, a semiconductor device mounted on the substrate and electrically connected to a part of the plurality of wiring patterns, and a terminal portion with a lead electrically connected to the other part of the plurality of wiring patterns, and is configured that the lead of the terminal portion is formed by laminating a plurality of metal members which contain a material substantially the same as or softer than the material for forming the other part of wiring patterns, and the material of the plurality of metal members, which is the same as or softer than the material for forming the other part of wiring patterns is electrically connected to the other part of wiring patterns through ultrasonic bonding.

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Номер записи: 65
28-02-2013 дата публикации

Substrate Dicing

Номер: US20130049234A1
Автор: Chen-Hua Yu, Chih-Wei Wu, Jing-Cheng Lin, Shin-puu Jeng, Szu Wei Lu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method and apparatus for separating a substrate into individual dies and the resulting structure is provided. A modification layer, such as an amorphous layer, is formed within the substrate. A laser focused within the substrate may be used to create the modification layer. The modification layer creates a relatively weaker region that is more prone to cracking than the surrounding substrate material. As a result, the substrate may be pulled apart into separate sections, causing cracks the substrate along the modification layers. Dice or other components may be attached to the substrate before or after separation.

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Номер записи: 66
28-02-2013 дата публикации

Method for manufacturing a circuit device

Номер: US20130052796A1
Автор: Koichi Saito, Yasuyuki Yanase, Yoshio Okayama
Принадлежит: Sanyo Electric Co Ltd

A semiconductor substrate and a copper sheet stacked with an insulating resin layer are bonded together at a temperature of 130° C. or below (first temperature) so that an element electrode provided on the semiconductor substrate connects to the copper sheet before a thinning process. Then the semiconductor substrate and the copper sheet, on which the insulating resin layer has been stacked, are press-bonded at a high temperature of 170° C. or above (second temperature) with the copper sheet thinned to thickness of a wiring layer. Then the wiring layer (rewiring) is formed by patterning the thinned copper sheet.

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Номер записи: 67
07-03-2013 дата публикации

Thermally Enhanced Structure for Multi-Chip Device

Номер: US20130056871A1
Автор: Chen-Hua Yu, Chih-Hang Tung, Tung-Liang Shao
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.

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Номер записи: 68
07-03-2013 дата публикации

System in package and method of fabricating same

Номер: US20130056880A1
Автор: Chien-Hsiun Lee, Tsung-Ding Wang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An assembly has at least one integrated circuit (IC) die fixed in a medium. The assembly has a redistribution layer over the IC die. The redistribution layer has conductors connecting first pads on active faces of the IC die to second pads at an exposed surface of the assembly. A die unit is provided over the IC die. The die unit has a bottom die interconnected to a package substrate. Respective portions of the redistribution layer corresponding to each of the at least one IC die partially underlie the bottom die, and extend beyond the bottom die. The package substrate has contacts connected to the ones of the second pads corresponding to the at least one IC die.

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Номер записи: 69
07-03-2013 дата публикации

Surface acoustic wave device and production method therefor

Номер: US20130057361A1
Автор: Kiwamu Sakano, Shu Yamada
Принадлежит: Murata Manufacturing Co Ltd

A surface acoustic wave device includes a surface acoustic wave element including a plurality of electrode pads, and a mount substrate. The surface acoustic wave element is flip-chip mounted on a die-attach surface of the mount substrate by bumps made of Au. The mount substrate includes at least one resin layer including via-holes, a plurality of mount electrodes provided on the die-attach surface of the mount substrate, and via-hole conductors. The mount electrodes are bonded to the electrode pads via the bumps. The via-hole conductors are provided in the via-holes. At least one of each of the electrode pads and each of the mount electrodes includes a front layer made of Au. At least one of the via-hole conductors is located below the corresponding bump.

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Номер записи: 70
21-03-2013 дата публикации

High io substrates and interposers without vias

Номер: US20130068516A1
Автор: Ilyas Mohammed
Принадлежит: TESSERA RESEARCH LLC

An interconnection component includes a substrate having first and second opposed major surfaces defining a thickness of less than 1000 microns and a first slot extending between the first and second surfaces, the first slot being enclosed by the substrate at the first and second surfaces. The first slot defines an edge surface between the first surface and the second surface. First conductive traces extend along the first surface and are electrically connected with first contact pads that overlie the first surface. Second conductive traces extend along the second surface and electrically connected with second contact pads that overlie the second surface. Interconnect traces extend along the edge surface of the first slot. Each interconnect trace directly connects at least one first trace with at least one second trace.

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Номер записи: 71
28-03-2013 дата публикации

Semiconductor Package and Method of Forming Z-Direction Conductive Posts Embedded in Structurally Protective Encapsulant

Номер: US20130075899A1
Автор: Chow Seng Guan, Huang Rui, Kuan Heap Hoe, Shim Il Kwon
Принадлежит: STATS CHIPPAC, LTD.

A semiconductor package is made using a prefabricated post carrier including a base plate and plurality of conductive posts. A film encapsulant is disposed over the base plate of the post carrier and around the conductive posts. A semiconductor die is mounted to a temporary carrier. The post carrier and temporary carrier are pressed together to embed the semiconductor die in the film encapsulant. The semiconductor die is disposed between the conductive posts in the film encapsulant. The temporary carrier and base plate of the post carrier are removed. A first circuit build-up layer is formed over a first side of the film encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. A second circuit build-up layer is formed over a second side of the film encapsulant opposite the first side. The second circuit build-up layer is electrically connected to the conductive posts. 1. A method of making a semiconductor device , comprising:providing a base plate including a plurality of conductive posts extending from the base plate;depositing a film encapsulant over the base plate and around the conductive posts;embedding a semiconductor die within the film encapsulant with major surfaces of the semiconductor die disposed within a height of the conductive posts;removing the base plate; andforming a first interconnect structure over a first surface of the film encapsulant, the first interconnect structure being electrically connected to the conductive posts.2. The method of claim 1 , further including forming a second interconnect structure over a second surface of the film encapsulant opposite the first surface of the film encapsulant.3. The method of claim 1 , further including planarizing the film encapsulant to the semiconductor die.4. The method of claim 1 , wherein depositing the film encapsulant includes:depositing a first film encapsulant over the base plate and around the conductive posts; anddepositing a second film encapsulant ...

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Номер записи: 72
28-03-2013 дата публикации

Semiconductor Device and Method of Forming Conductive Posts Embedded in Photosensitive Encapsulant

Номер: US20130075902A1
Автор: Chow Seng Guan, Huang Rui, Kuan Heap Hoe, Shim Il Kwon
Принадлежит: STATS CHIPPAC, LTD.

A semiconductor package includes a post carrier having a base plate and plurality of conductive posts. A photosensitive encapsulant is deposited over the base plate of the post carrier and around the conductive posts. The photosensitive encapsulant is etched to expose a portion of the base plate of the post carrier. A semiconductor die is mounted to the base plate of the post carrier within the etched portions of the photosensitive encapsulant. A second encapsulant is deposited over the semiconductor die. A first circuit build-up layer is formed over the second encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. The base plate of the post carrier is removed and a second circuit build-up layer is formed over the semiconductor die and the photosensitive encapsulant opposite the first circuit build-up layer. The second circuit build-up layer is electrically connected to the conductive posts. 1. A method of making a semiconductor device , comprising:providing a substrate including a plurality of conductive posts extending from the substrate;disposing a photosensitive material over the substrate and around the conductive posts;forming an opening in the photosensitive material to expose a portion of the substrate between the conductive posts;disposing a semiconductor die over the substrate within the opening in the photosensitive material; anddepositing an encapsulant over the semiconductor die within the opening in the photosensitive material.2. The method of claim 1 , further including forming a first interconnect structure over the photosensitive material and encapsulant claim 1 , the first interconnect structure being electrically connected to the conductive posts.3. The method of claim 2 , further including forming a second interconnect structure over the photosensitive material and encapsulant opposite the first interconnect structure.4. The method of claim 1 , further including planarizing the photosensitive material and ...

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Номер записи: 73
28-03-2013 дата публикации

Semiconductor Device and Method of Forming Different Height Conductive Pillars to Electrically Interconnect Stacked Laterally Offset Semiconductor Die

Номер: US20130075903A1
Автор: Chow Seng Guan, Pagaila Reza A., Yoon Seung Uk
Принадлежит: STATS CHIPPAC, LTD.

A semiconductor device has a first semiconductor die mounted over a carrier. Wettable contact pads can be formed over the carrier. A second semiconductor die is mounted over the first semiconductor die. The second die is laterally offset with respect to the first die. An electrical interconnect is formed between an overlapping portion of the first die and second die. A plurality of first conductive pillars is disposed over the first die. A plurality of second conductive pillars is disposed over the second die. An encapsulant is deposited over the first and second die and first and second conductive pillars. A first interconnect structure is formed over the encapsulant, first conductive pillars, and second die. The carrier is removed. A second interconnect structure is formed over the encapsulant, second conductive pillars, and first die. A third conductive pillar is formed between the first and second build-up interconnect structures. 1. A semiconductor device , comprising:a first semiconductor die;a second semiconductor die disposed over a portion of the first semiconductor die and laterally offset from the first semiconductor die;a plurality of first conductive pillars disposed over the first semiconductor die or second semiconductor die; andan encapsulant deposited around the first semiconductor die and second semiconductor die and first conductive pillars.2. The semiconductor device of claim 1 , further including an electrical interconnect formed between an overlapping portion of the first semiconductor die and second semiconductor die.3. The semiconductor device of claim 2 , wherein the electrical interconnect includes a bump claim 2 , stud bump claim 2 , or second conductive pillar.4. The semiconductor device of claim 1 , further including a plurality of second conductive pillars disposed around the first semiconductor die or second semiconductor die.5. The semiconductor device of claim 1 , further including an interconnect structure formed over the ...

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Номер записи: 74
28-03-2013 дата публикации

Integrated circuit packaging system with external wire connection and method of manufacture thereof

Номер: US20130075916A1
Автор: Daesik Choi
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing a package carrier; mounting an integrated circuit to the package carrier; forming an external wire on the package carrier and adjacent to the integrated circuit; forming an encapsulation on the package carrier over the external wire; and forming a hole in the encapsulation with the external wire and a portion of the package carrier exposed from the encapsulation.

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Номер записи: 75
28-03-2013 дата публикации

Forming Packages Having Polymer-Based Substrates

Номер: US20130075921A1
Автор: Chih-Wei Lin, Chun-Cheng Lin, Chung-Shi Liu, Meng-Tse Chen, Ming-Da Cheng, Wen-Hsiung LU
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method includes applying a polymer-comprising material over a carrier, and forming a via over the carrier. The via is located inside the polymer-comprising material, and substantially penetrates through the polymer-comprising material. A first redistribution line is formed on a first side of the polymer-comprising material. A second redistribution line is formed on a second side of the polymer-comprising material opposite to the first side. The first redistribution line is electrically coupled to the second redistribution line through the via.

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Номер записи: 76
28-03-2013 дата публикации

Integrated circuit packaging system with encapsulation and method of manufacture thereof

Номер: US20130075923A1
Автор: HeeJo Chi, Hyungmin Lee, YeongIm Park
Принадлежит: Stats Chippac Pte Ltd

A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate first side and a substrate second side opposite the substrate first side; attaching a base integrated circuit to the substrate first side; attaching a mountable integrated circuit to the substrate second side; attaching a via base to the substrate second side adjacent the mountable integrated circuit; forming a device encapsulation surrounding the via base and the mountable integrated circuit; and forming a via extension through the device encapsulation and attached to the via base, the via extension exposed from the device encapsulation.

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Номер записи: 77
28-03-2013 дата публикации

Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP

Номер: US20130075924A1
Автор: Gu Yu, KANG Chen, Rui Huang, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.

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Номер записи: 78
28-03-2013 дата публикации

Integrated circuit packaging system with encapsulation and method of manufacture thereof

Номер: US20130075927A1
Автор: HanGil Shin, HeeJo Chi, NamJu Cho
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; forming a base encapsulation, having a base encapsulation top side, on the base substrate and around the base integrated circuit; forming a base conductive via, having a base via head, through the base encapsulation and attached to the base substrate adjacent to the base integrated circuit, the base via head exposed from and coplanar with the base encapsulation top side; mounting an interposer structure over the base encapsulation with the interposer structure connected to the base via head; and forming an upper encapsulation on the base encapsulation top side and partially surrounding the interposer structure with a side of the interposer structure facing away from the base encapsulation exposed.

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Номер записи: 79
04-04-2013 дата публикации

Wiring substrate and method of manufacturing the same

Номер: US20130081862A1
Автор: Seiji Mori, Takahiro Hayashi, Tatsuya Ito
Принадлежит: NGK Spark Plug Co Ltd

Embodiments of the present invention provide a wiring substrate which is excellent in terms of the reliability of connection between the wiring substrate and a semiconductor chip. In some embodiments the wiring substrate comprises a first build-up layer in which resin insulation layers and conductor layers are laminated alternately. The outermost conductor layer can include a plurality of connection terminal portions to which a semiconductor chip is flip-chip connected. The plurality of connection terminal portions can be exposed through openings of a solder resist layer. Each of the connection terminal portions includes a connection region to which a connection terminal of the semiconductor chip is to be connected, and a wiring region which extends in a planar direction from the connection region and which is narrower than the connection region. The surface of the wiring region has a solder wettability lower than that of the surface of the connection region.

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Номер записи: 80
04-04-2013 дата публикации

Semiconductor package including an integrated waveguide

Номер: US20130082379A1
Автор: Ahmadreza Rofougaran, Arya Reza Behzad, Jesus Alfonso Castaneda, Michael BOERS, Sam Ziqun Zhao
Принадлежит: Broadcom Corp

Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.

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Номер записи: 81
04-04-2013 дата публикации

Power semiconductor arrangement and method for producing a power semiconductor arrangement

Номер: US20130082387A1
Автор: Guido Strotmann, Karsten Guth, Thilo Stolze
Принадлежит: INFINEON TECHNOLOGIES AG

In a method for producing a power semiconductor arrangement, an insulation carrier with a top side, a metallization, and a contact pin with a first end are provided. The metallization is attached to the top side and a target section of the metallization is determined. After the metallization is attached to the top side of the insulation carrier, the first end of the contact pin is pressed into the target section such that the first end is inserted in the target section. Thereby, an interference fit and an electrical connection are established between the first end of the contact pin and the target section of the metallization.

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Номер записи: 82
04-04-2013 дата публикации

Stub minimization for wirebond assemblies without windows

Номер: US20130082391A1
Автор: Belgacem Haba, Frank Lambrecht, Richard DeWitt Crisp, Wael Zohni
Принадлежит: Invensas LLC

A microelectronic assembly can include a circuit panel having first and second surfaces and panel contacts at each surface, and first and second microelectronic packages having terminals mounted to the panel contacts at the first and second surfaces, respectively. The circuit panel can electrically interconnect terminals of the first package with corresponding terminals of the second package. Each package can include a substrate having first and second surfaces, a microelectronic element, conductive structure extending above a front face of the microelectronic element, and parallel columns of terminals at the second surface. The terminals of each package can include first terminals in a central region of the respective second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the respective microelectronic element. Each central region can have a width within three and one-half times a minimum pitch between adjacent terminals.

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Номер записи: 83
04-04-2013 дата публикации

Method Of Manufacturing Package-On-Package (Pop)

Номер: US20130084678A1
Автор: Byeong Ho JEONG
Принадлежит: STS Semiconductor and Telecommunications Co Ltd

A method of manufacturing package-on-packages (POPs) includes: forming a plurality of internal connection members that are separated from each other on a first circuit substrate; forming a first package by attaching a plurality of first chips between the internal connection members on the first circuit substrate; forming a second package by attaching a plurality of second chips that are separated from each other on a second circuit substrate; electrically connecting the first circuit substrate and the second circuit substrate by stacking the internal connection members onto the second circuit substrate; forming an encapsulant to encapsulate the first package and the second package; and forming the POPs in which the first chips and the second chips are respectively formed by cutting the first circuit substrate, the second circuit substrate, and the encapsulant.

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Номер записи: 84
11-04-2013 дата публикации

Interposer, circuit board module, and method for manufacturing interposer

Номер: US20130087376A1
Автор: Yasuo Moriya
Принадлежит: Fujitsu Ltd

An interposer includes a substrate having first and second opposing surfaces, the substrate having a sheet shape; and a plurality of spring electrodes fixed to the substrate in a certain arrangement, each of the plurality of the spring electrodes including a first pad disposed opposite the first surface of the mesh and extending in a first direction, a second pad disposed opposite the second surface of the mesh and extending in the first direction, and a post extending through the substrate between the first and second surfaces and connecting an end of the first pad to an end of the second pad.

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Номер записи: 85
11-04-2013 дата публикации

Semiconductor device, electronic device, and semiconductor device manufacturing method

Номер: US20130087912A1
Автор: Kozo Shimizu, Seiki Sakuyama, Toshiya Akamatsu
Принадлежит: Fujitsu Ltd

A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on witch a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration.

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Номер записи: 86
11-04-2013 дата публикации

Semiconductor Device and Method of Forming Bump on Substrate to Prevent ELK ILD Delamination During Reflow Process

Номер: US20130087913A1
Автор: Choi DaeSik, Jang KiYoun, Kim OhHan, Moon Dongsoo
Принадлежит: STATS CHIPPAC, LTD.

A semiconductor device that has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer. 1. A semiconductor device , comprising:a substrate;a first insulating layer formed over the substrate including an opening extending through the first insulating layer to the substrate;a first bump material disposed in the opening and electrically connected to the substrate; anda semiconductor die disposed over the substrate and electrically connected to the first bump material.2. The semiconductor device of claim 1 , further including:a second insulating layer formed over the first insulating layer including an opening extending through the second insulating layer to the first bump material; anda second bump material disposed within the opening in the second insulating layer over the first bump material.3. The semiconductor device of claim 1 , further including a second bump material disposed over the first bump material.4. The semiconductor device of claim 3 , wherein the first bump material includes a non-fusible material and the second bump material includes a fusible material.5. The semiconductor device of claim 1 , wherein the first bump material includes a conductive pillar or stacked ...

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Номер записи: 87
11-04-2013 дата публикации

Methods of Packaging Semiconductor Devices and Structures Thereof

Номер: US20130087916A1
Автор: Jing-Cheng Lin, Jui-Pin Hung, Tsan-Hua Tung, Yi-Hang Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

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Номер записи: 88
11-04-2013 дата публикации

Ball Grid Array with Improved Single-Ended and Differential Signal Performance

Номер: US20130087918A1
Автор: Weekly Roger D., Zhou Yaping
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns. 13-. (canceled)4. An integrated circuit package comprising a plurality of pins comprising:a plurality of pins, the plurality of pins comprising a first pin, a second pin, a third pin, and a fourth pin, each of the first, second, third, and fourth extending externally to the integrated circuit package, being linearly arranged in a first row and being equally spaced from each other;a fifth pin, a sixth pin, a seventh pin, an eighth pin and a ninth pin extending externally to the integrated circuit package, linearly arranged in a second row separated vertically from the first row and offset horizontally from the first row such that sixth, seventh, eighth and ninth pins are offset from the pins in the first row;wherein said third and seventh pins comprise power/ground pins; andwherein the remaining pins are configured for use as signal pins.5. The integrated circuit package of wherein:an arrangement of the plurality of pins is repeated within the integrated circuit package;the arrangement of the plurality of pins provides equally spaced sets of the plurality of pins.6. The integrated circuit package of wherein:the arrangement of the plurality of pins provides power/ground pins positioned substantially zigzagged across a plurality of rows.7. The integrated circuit package of wherein:the arrangement of the plurality of pins provides power/ground pins positioned substantially diagonally across a plurality of rows.8. The integrated circuit package of wherein:the arrangement of the plurality of pins provides power/ground pins positioned such that each power/ground pin is offset from a group of hexagonally configured signal pins.9. An integrated circuit package comprising: a first ...

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Номер записи: 89
18-04-2013 дата публикации

SEMICONDUCTOR DEVICE, ELECTRODE MEMBER, AND ELECTRODE MEMBER FABRICATION METHOD

Номер: US20130093082A1
Автор: OKUMURA Katsuya, TAKAHASHI Yoshikazu, Takenouchi Kazunori
Принадлежит:

A semiconductor device that improves the heat cycle resistance and power cycle resistance of a power module. An electrode member in which copper posts are formed in a plurality of perforations cut in a support made of a ceramic material is soldered onto a side of an IGBT where an emitter electrode is formed. By soldering the copper posts onto the electrode, heat generated in the IGBT is transferred to the electrode member and is radiated. In addition, even if a material of which the IGBT is made and copper differ in thermal expansivity, stress on a soldered interface is reduced and distortion is reduced. This suppresses the appearance of a crack. As a result, the heat cycle resistance and power cycle resistance of a power module can be improved. 1. A semiconductor device having a semiconductor element with an electrode on a surface , the device comprising an electrode member including:a plurality of first holes made in one principal plane of an insulating support;first metal posts located in the plurality of first holes;a plurality of second holes made in another principal of the insulating support; andsecond metal posts which are located in the plurality of second holes and which are electrically insulated from the first metal posts,wherein at least one of the first metal posts and the second metal posts are joined to the electrode.2. The semiconductor device according to claim 1 , wherein a conductor layer is formed on a principal plane of the electrode member joined to the electrode.3. The semiconductor device according to claim 1 , wherein in the electrode member claim 1 , end portions of the first and second metal posts protrude from at least one principal plane of the insulating support.4. The semiconductor device according to claim 3 , wherein a cooling medium is configured to be passed between the first and second metal posts which protrude from the insulating support and a surface in which the first and second metal posts are joined to the electrode.5. An ...

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Номер записи: 90
18-04-2013 дата публикации

SEMICONDUCTOR DEVICE AND STACKED SEMICONDUCTOR DEVICE

Номер: US20130093083A1
Автор: KATAGIRI Mitsuaki, SASAKI Dai, TANIE Hisashi
Принадлежит: ELPIDA MEMORY, INC.

A semiconductor device according to one embodiment has a wiring circuit board, a semiconductor chip, a die attach material and bumps. The semiconductor chip is mounted on the wiring circuit board. The die attach material is provided between the wiring circuit board and the semiconductor chip. A wiring layer is provided on one surface of the wiring circuit board. Leads are extended from the wiring layer and connected to the semiconductor chip. The bumps are provided at outer positions relative to the region where the semiconductor chip of the wiring circuit board is mounted. The wiring layer in the wiring circuit board is formed on the surface opposite from the surface on which the semiconductor chip is mounted. 1. A semiconductor device comprising:a first core member including a first surface and a second surface opposite to the first surface;a first semiconductor chip mounted over the first surface of the first core member;a plurality of first bumps provided on the second surface of the first core member;a second core member including a third surface and a fourth surface opposite to the third surface, the second core member being stacked over the first semiconductor chip so that the fourth surface faces the first semiconductor chip;a second semiconductor chip mounted over the third surface of the second core member; anda plurality of second bumps provided on the fourth surface of the second core member, the plurality of second bumps being arranged at positions that are outside of a region overlapping the first semiconductor chip, and the plurality of second bumps are smaller in diameter than the plurality of first bumps.2. The semiconductor device as claimed in claim 1 , wherein the second semiconductor chip is electrically coupled to the first bumps via the second bumps.3. The semiconductor device as claimed in claim 1 , wherein the second bumps are arranged at positions that are overlapped to the first bumps in plan view.4. The semiconductor device as claimed in ...

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Номер записи: 91
25-04-2013 дата публикации

PACKAGE OF ELECTRONIC DEVICE INCLUDING CONNECTING BUMP, SYSTEM INCLUDING THE SAME AND METHOD FOR FABRICATING THE SAME

Номер: US20130099374A1
Автор: HAN Kwon Whan
Принадлежит: SK HYNIX INC.

A package of an electronic device, a system including the same and a method for fabricating the same are provided. The package of the electronic device includes a substrate, a step difference layer and a connecting bump. The substrate allows a connecting contact part to be exposed on a surface thereof. The step difference layer covers the substrate so as to leave the connecting contact part exposed. The connecting bump is connected to the connecting contact part so that one end part of the connecting bump is extended on the step difference layer, and has a sloped upper surface formed by a step difference formed by the step difference layer. 1. A package of an electronic device , comprising:a substrate configured to allow a connecting contact part to be exposed on a surface thereof;a step difference layer configured to cover the substrate so as leave the connecting contact part exposed; anda connecting bump configured to be connected to the connecting contact part so that one end part of the connecting bump is extended on the step difference layer, and have a sloped upper surface formed by a step difference formed by the step difference layer.2. The package of claim 1 , wherein the substrate is a semiconductor substrate of a semiconductor chip claim 1 , on which an integrated circuit is integrated claim 1 , a printed circuit board (PCB) on which the semiconductor chip is to be mounted claim 1 , or a package substrate including an interposer substrate.3. The package of claim 2 , wherein the semiconductor substrate comprises a through electrode providing the connecting contact part as an exposed surface.4. The package of claim 3 , further comprising a conductive layer configured to be connected to the exposed surface of the through electrode on the substrate so as to be used as a contact pad or redistribution layer (RDL).5. The package of claim 1 , wherein the step difference layer comprises an insulating layer having an opening through which the connecting contact ...

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Номер записи: 92
25-04-2013 дата публикации

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

Номер: US20130099378A1
Автор: HanGil Shin, HeeJo Chi, NamJu Cho
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

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Номер записи: 93
25-04-2013 дата публикации

Semiconductor device and connection checking method for semiconductor device

Номер: US20130099381A1
Автор: Naoto Akiyama, Toshiaki Umeshima
Принадлежит: Renesas Electronics Corp

A semiconductor device includes a substrate, a first land formed in a first surface of the substrate, a second land formed in a second surface of the substrate, a first terminal coupled to the second land, a line coupled to the first land and the second land, a second terminal formed in the second surface of the substrate and a branch line coupled to the line and the second terminal. The second terminal is coupled to the first land and the second land and is not coupled to other lands in the first surface. The second surface is different surface from the first surface.

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Номер записи: 94
25-04-2013 дата публикации

Multiple die stacking for two or more die

Номер: US20130100616A1
Автор: Belgacem Haba, Wael Zohni
Принадлежит: Tessera LLC

A microelectronic package can include a substrate having first and second opposed surfaces, and first and second microelectronic elements having front surfaces facing the first surface. The substrate can have a plurality of substrate contacts at the first surface and a plurality of terminals at the second surface. Each microelectronic element can have a plurality of element contacts at the front surface thereof. The element contacts can be joined with corresponding ones of the substrate contacts. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto. The element contacts of the first microelectronic element can be arranged in an area array and are flip-chip bonded with a first set of the substrate contacts. The element contacts of the second microelectronic element can be joined with a second set of the substrate contacts by conductive masses.

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Номер записи: 95
02-05-2013 дата публикации

Method to form solder deposits and non-melting bump structures on substrates

Номер: US20130105329A1
Автор: Catherine Schoenenberger, Ingo Ewert, Jürgen Kress, Kai-Jens Matejat, Sven Lamprecht
Принадлежит: Atotech Deutschland GmbH and Co KG

Described is a method of forming a metal or metal alloy layer onto a substrate comprising the following steps i) provide a substrate including a permanent resin layer on top of at least one contact area and a temporary resin layer on top of the permanent resin layer, ii) contact the entire substrate area including the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface and i) electroplate a metal or metal alloy layer onto the conductive layer.

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Номер записи: 96
02-05-2013 дата публикации

Semiconductor Device and Method of Forming Conductive Posts and Heat Sink Over Semiconductor Die Using Leadframe

Номер: US20130105970A1
Автор: Chi HeeJo, Cho NamJu, Shin HanGil
Принадлежит: STATS CHIPPAC, LTD.

A semiconductor device has a prefabricated multi-die leadframe with a base and integrated raised die paddle and a plurality of bodies extending from the base. A thermal interface layer is formed over a back surface of a semiconductor die or top surface of the raised die paddle. The semiconductor die is mounted over the raised die paddle between the bodies of the leadframe with the TIM disposed between the die and raised die paddle. An encapsulant is deposited over the leadframe and semiconductor die. Vias can be formed in the encapsulant. An interconnect structure is formed over the leadframe, semiconductor die, and encapsulant, including into the vias. The base is removed to separate the bodies from the raised die paddle. The raised die paddle provides heat dissipation for the semiconductor die. The bodies are electrically connected to the interconnect structure. The bodies operate as conductive posts for electrical interconnect. 1. A method of making a semiconductor device , comprising:providing a substrate including a raised die area and a plurality of conductive bodies extending from the substrate;disposing a semiconductor die over the raised die area between the conductive bodies of the substrate;depositing an encapsulant over the substrate and semiconductor die;forming an interconnect structure over the encapsulant, the interconnect structure being electrically connected to the conductive bodies; andremoving a portion of the substrate to separate the conductive bodies from the raised die area.2. The method of claim 1 , wherein the raised die area provides heat dissipation for the semiconductor die.3. The method of claim 1 , further including disposing a thermal interface material between the semiconductor die and raised die area.4. The method of claim 1 , further including forming a plurality of bumps over the semiconductor die.5. The method of claim 1 , further including:forming a plurality of vias in the encapsulant extending to the conductive bodies; ...

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Номер записи: 97
02-05-2013 дата публикации

SEMICONDUCTOR PACKAGE FEATURING FLIP-CHIP DIE SANDWICHED BETWEEN METAL LAYERS

Номер: US20130105974A1
Автор: Tsui Anthony C.
Принадлежит: GEM Services, Inc.

Embodiments in accordance with the present invention relate to flip-chip packages for semiconductor devices, which feature a die sandwiched between metal layers. One metal layer comprises portions of the lead frame configured to be in electrical and thermal communication with various pads on a first surface of the die (e.g. IC pads or MOSFET gate or source pads) through a solder ball contact. The other metal layer is configured to be in at least thermal communication with the opposite side of the die. Embodiments of packages in accordance with the present invention exhibit superior heat dissipation qualities, while avoiding the expense of wire bonding. Embodiments of the present invention are particularly suited for packaging of power devices. 1. A package for a semiconductor device , the package comprising:a first metal layer configured to be in thermal and electrical communication with a power device die; anda second metal layer disposed on an opposite side of the power device die from the first metal layer, the second metal layer configured to be in electrical and thermal communication with a pad on a surface of the power device die through physical contact with a solder ball contact, the first metal layer comprising integral leads projecting from a plastic package body encapsulating the power device die, the solder ball contact, and at least a part of the first and second metal layers;wherein the first metal layer is configured to be in electrical communication with the power device die through a second solder ball contact.2. A package for a semiconductor device , the package comprising:a first metal layer configured to be in thermal and electrical communication with a MOSFET die; a first portion configured to be in electrical communication with a gate pad on a surface of the MOSFET die, and', 'a second portion configured to be in electrical and thermal communication with a source pad on the surface of the MOSFET die through physical contact with a solder ball ...

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Номер записи: 98
02-05-2013 дата публикации

Semiconductor package including semiconductor chip with through opening

Номер: US20130105988A1
Автор: Chang-Cheol Lee, Hyun-Jun Kim, In-Young Lee, Ki-Kwon Jeong
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package comprises a substrate having a first opening formed therethrough, a first semiconductor chip stacked on the substrate in a flip chip manner and having a second opening formed therethrough, a second semiconductor chip stacked on the first semiconductor chip in a flip chip manner and having a third opening formed therethrough, and a molding material covering the first semiconductor chip and the second semiconductor chip and filling up a space between the substrate and the first semiconductor chip, a space between the first semiconductor chip and the second semiconductor chip, and filling each of the first opening, the second opening, and the third opening.

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Номер записи: 99
02-05-2013 дата публикации

Multi-piece substrate

Номер: US20130107481A1
Автор: Keisuke Shimizu, Yasuyuki Kurabe
Принадлежит: Ibiden Co Ltd

A multi-piece substrate includes a frame portion, and a unit portion in which multiple wiring boards is arrayed. The frame portion is formed on the periphery of the unit portion, the wiring boards have semiconductor elements built in the wiring boards, respectively, and the frame portion has multiple slits formed such that the slits have openings on the periphery of the frame portion.

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Номер записи: 100