SEMICONDUCTOR STRUCTURE HAVING CONDUCTIVE VIAS AND METHOD FOR MANUFACTURING THE SAME

This application claims the benefit of Taiwan application Serial No. 99129126, filed Aug. 30, 2010, the subject matter of which is incorporated herein by reference.

1. Field of the Invention

The present invention relates to the field of semiconductor packaging, and, more particularly, to thermal management of stacked-chip packages.

2. Description of Related Art

In stacked-chip packaging, multiple integrated circuit chips can be packaged in a single package structure in a vertically stacked manner. This increases stack density, making the package structure smaller, and often reduces the length of the path that signals must traverse between chips. Thus, stacked-chip packaging tends to increase the speed of signal transmission between or among chips. Additionally, stacked-chip packaging allows chips having different functions to be integrated in a single package structure. Use of through silicon vias (TSV) has been a key technology in realizing stacked-chip packaging integration due to the ability to provide short vertical conductive paths between chips.

However, thermal management of 3-D designs has been challenging. To maintain normal operation of the chip, the chip must be maintained within a limited operation temperature range. Operating temperatures in excess of the limited operation temperature range results in chip performance drop, reduced reliability or damage. Existing stacked-chip packages usually include a heat sink, which is bonded to a lower chip using adhesives and that covers the upper chips of the package.

In current chip processing the surface of the chip is covered with a protective layer, which has a low thermal conductivity and therefore hinders conducting of the heat from the chip interior, where it is produced, to the surrounding environment. Even if the heat sink is disposed on the lower chip of the stacked-chip package structure, the protective layer likewise hinders thermal conductance between the lower chip and the heat sink, thus affecting operation and reliability of the stacked-chip package structure.

One aspect of the disclosure relates to a semiconductor structure that includes a first chip; a redistribution layer disposed on a first surface of the first chip, the redistribution layer including at least one thermal via contacting the first surface of the first chip; a second chip coupled to the first surface of the first chip; and a heat sink thermally coupled to the at least one thermal via and the second chip.

Another aspect of the disclosure relates to a semiconductor structure that includes a first chip having an active surface and a back surface opposite to the active surface, the first chip having a plurality of through silicon vias; a first wiring layer disposed on the active surface of the first chip, the first wiring layer comprising a first interconnect, the first interconnect connected to one end of each of the through silicon vias; a second wiring layer disposed on the back surface of the first chip, the second wiring layer comprising a second interconnect and at least one thermal via, the second interconnect connected to the other end of each of the through silicon vias, the at least one thermal via electrically insulated from the second interconnect and contacting the back surface of the first chip; a plurality of bump pads disposed on the second wiring layer, each of the bump pads connected to the second interconnect; and a heat dissipation layer disposed on the second wiring layer in an area where the bump pads are not located, the heat dissipation layer connected to the thermal via.

Another aspect of the disclosure relates to manufacturing methods. In one embodiment, a manufacturing method includes providing a semiconductor wafer, the semiconductor wafer having an active surface, the semiconductor wafer having a plurality through silicon vias, a first wiring layer formed on the active surface of the semiconductor structure, the first wiring layer comprising a first interconnect, the first interconnect connected to one end of each of the through silicon vias; thinning the semiconductor wafer from a back surface of the semiconductor wafer opposite to the active surface to expose the other end of each of the through silicon vias and a back surface of the semiconductor wafer; forming a second wiring layer on the back surface of the semiconductor wafer, the second wiring layer comprising a second interconnect and a thermal via, the second interconnect connected to the other end of each of the through silicon vias, the thermal via electrically insulated from the second interconnects and contacting the back surface of the semiconductor structure; and forming a plurality of bump pads and a heat dissipation layer, each of the bump pads connected to the second interconnect, the heat dissipation layer connected to the thermal via.

Common reference numerals are used throughout the drawings and the detailed description to indicate the same elements. The present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Referring to FIG. 1, there is shown a semiconductor structure 100 according to one embodiment of the present invention. The semiconductor structure 100 includes a first chip 110 having a plurality of through silicon vias (TSV) 112 in the semiconductor substrate thereof. It is to be appreciated that although silicon is the preferred semiconductor substrate material, the invention applies to any semiconductor material used in semiconductor chip fabrication, such as germanium, silicon germanium, gallium arsenide, or other III-V and II-IV compounds and the term is used generically throughout the disclosure regardless of the semiconductor material.

TSV fabrication can be placed into two main categories: “Via-First” processing and “Via-Last” processing. Via-First processing means that the through silicon vias are formed early in the manufacturing process, before the “back-end-of-line” (BEOL) processing. For Via-Last processing, the through silicon vias are fabricated after the BEOL processing.

For Via-First, since the through silicon vias are buried inside the substrate material before the BEOL processing, the wafer requires an additional thinning process to expose the vias on the wafer back surface and an additional passivation step to isolate the substrate material from an electrical redistribution layer on the back surface.

A first wiring layer 120 or redistribution layer, commonly referred to as “RDL” is disposed on an active surface 110a of the first chip 110. The various wiring layers or RDL disclosed below are typically include one or more layers of dielectric or passivation material and one or more layers of conductive material for routing, and under bump metallurgy. The first wiring layer 120 includes a first interconnect 122. The first interconnect 122 may, for example, be an interconnect formed during the back end of line of the wafer process. The first interconnect 122 is, for example, connected between end 112a of each of the through silicon vias 112 and a second bump 184 disposed at a bottom side of the first chip 110. In addition, other active or passive elements (not shown) may exist in the first chip 110 and, therefore, the first interconnect 122 may be also connected with these active or passive elements.

A second wiring layer 130 or RDL is disposed at a back side 110b of the first chip 110. The second wiring layer 130 includes a second interconnect 132 and a plurality of thermal vias 134. The second interconnect 132 is connected to the other end 112b of each of the through silicon vias 112. As shown, the thermal vias 134 are electrically insulated from the second interconnect 132 and contacts the back side 110b of the first chip 110. Here, the thermal vias 134 are mainly used for thermal conduction.

A plurality of bump pads 142 is disposed on the second wiring layer 130. Each bump pad 142 is connected to the second interconnect 132. In addition, a heat dissipation layer 144 is disposed on the second wiring layer 130 in the area where the bump pads 142 are not located. The heat dissipation layer 144 is connected to the thermal vias 134.

A second chip 150 is disposed above the first chip 110 and is connected with the bump pads 142 via a plurality of first bumps 182, such that the second chip 150 is electrically connected to the through silicon vias 112 of the first chip 110 via the first bumps 182, the bump pads 142 and the second interconnect 132. In order to protect the first bumps 182, a first underfill 162 is filled between the second chip 150 and the second wiring layer 130 to enclose the first bumps 182. The second chip 150 may also have an RDL formed on the active surface to facilitate patterning of the bumps.

As shown in FIG. 1, the foregoing structure may be disposed on a carrier substrate 170. The carrier substrate 170 may, for example, be a common printed circuit board, a ceramic substrate, a metal substrate, or another suitable type of carrier substrate for supporting the first chip 110. A plurality of second bumps 184 is disposed between the first wiring layer 120 and the carrier substrate 170 to electrically connect the first wiring layer 120 to the carrier substrate 170. In order to protect the second bumps 184, a second underfill 164 may be filled between the first wiring layer 120 and the carrier substrate 170 to enclose the second bumps 184. In addition, a plurality of solder balls 186 may be disposed on a bottom of the carrier substrate 170 as a path along which the entire semiconductor structure 100 is connected to an external circuit.

A heat sink 190 may be disposed on the first chip 110 to enhance heat dissipation efficiency. The heat sink 190 covers the second chip 150 and is coupled to the heat dissipation layer 144 on the first chip 110, such that heat generated by the first chip 110 and second chip 150 during operation can be dissipated to the surrounding environment by the heat sink 190. In order to position the heat sink 190 and enhance the efficiency of thermal conduction between the heat sink 190 and the first chip 110/second chip 150, a first thermally conductive adhesive 192 may be disposed between the heat sink 190 and the heat dissipation layer 144, and a second thermally conductive adhesive 194 may be disposed between the heat sink 190 and the second chip 150.

In the present embodiment, the second wiring layer 130 is provided with the thermal vias 134, such that a large part of the heat generated by the first chip 110 can be transferred to a thermal conductive path comprising the thermal vias 134, the heat dissipation layer 144, and the heat sink 190, without being hindered by the dielectric material, having a lower thermal conductance, in the second wiring layer 130. As a result of adding the thermal conductive path, the semiconductor structure 100 of the present embodiment has improved heat dissipation efficiency and operation reliability in comparison with existing structures.

In addition, in the present embodiment, the heat dissipation layer 144 and the bump pads 142 may be fabricated using the same or similar materials. For example, the surface layer of the bump pad 142 can be a nickel-gold stack layer 140b, which has good wettability. Likewise, the heat dissipation layer 144 also can have this nickel-gold stack layer 140b as its surface layer, thus improving the solderability between the heat sink 190 and the heat dissipation layer 144.

Furthermore, in the present embodiment, a thermal path which includes the heat sink 190, the heat dissipation layer 144 and the thermal vias 134 can also form a ground path through additional TSV's in the first chip 110 (not shown) so as to electrically interconnect with the substrate 170 and a ground plane external to the structure 100 thereby forming an electromagnetic interference shield and preventing external electromagnetic fields from interfering with electrical performance of the first chip 110 and the second chip 150.

Referring to FIG. 2A, a semiconductor wafer 110′ is first provided. The semiconductor wafer 110′ is used to form the first chip 110 of FIG. 1 after a subsequent dicing process. The semiconductor wafer 110′ includes an active surface 110a, and the plurality of through silicon vias 112 formed in an interior thereof. In addition, the active surface 110a of the semiconductor wafer 110′ includes the first wiring layer 120. The first wiring layer 120 includes a first interconnect (e.g., back-end-of-line interconnect) 122, and the first interconnect 122 is connected to one end of each of the through silicon vias 112.

As shown in FIG. 2B, the semiconductor wafer 110′ is thinned from a back side of the semiconductor wafer 110′ opposite to the active surface 110a so as to expose the other end 112b of each of the through silicon vias 112 and the back surface 110b of the semiconductor wafer 110′.

As shown in FIG. 2C, a second wiring layer 130 is then formed on the back surface 110b of the semiconductor wafer 110′. The second wiring layer 130 includes therein a second interconnect 132 and the thermal vias 134. The second interconnect 132 is connected to the other end 112b of each of the through silicon vias 112. The thermal vias 134 are electrically insulated from the second interconnect 132 and contact the back surface 110b of the semiconductor wafer 110′. Here, the second wiring layer 130 may be a stack of a single or multiple metal layers 130a and a dielectric layer 130b. The uppermost dielectric layer 130b has a plurality of openings 139 to expose the second interconnect 132 and the thermal vias 134.

As shown in FIG. 2D, a plating seed layer 140 is then formed over the entire area of the second wiring layer 130. The plating seed layer 140 is electrically connected to the second interconnect 132 and the thermal vias 134 through the openings 139. As shown in FIG. 2E, a mask 210 is then formed over the plating seed layer 140 to define a plurality of pad regions 212 and a heat dissipation region 214 on the plating seed layer 140. The pad regions 212 are positioned in correspondence with the second interconnect 132, and the heat dissipation region 214 is positioned in correspondence with the thermal vias 134.

In FIG. 2F, a plating process is performed on the plating seed layer 140 to form a plurality of bump pads 142 within the pad regions 212 and, at the same time, form a heat dissipation layer 144 within the heat dissipation region 214. Each bump pad 142 is connected to the second interconnect 132, and the heat dissipation layer 144 is connected to the thermal vias 134. In the plating process, in order to increase the solderability between the bump pads 142 and the subsequently bonded second bumps 184 and the solderability between the heat dissipation layer 144 and the subsequently bonded heat sink 190, a copper layer 140 and the nickel-gold stack layer 140b may be formed by plating. A gold layer is used as the surface layer of the plated structure, which has good wettability, thus increasing the yield of the subsequent soldering process.

As shown in FIG. 2G, the mask 210 and the portion of the plating seed layer 140 covered by the mask 210 are then removed. The structure shown in FIG. 2G is a semi-finished product of the semiconductor structure 100, which may be shipped in the form of wafers or individual chips after a sawing process.

The following description explains a subsequent process of stacking chips on the semi-product in the form of a wafer after the step of FIG. 2G.

As shown in FIG. 2H, multiple second chips 150 (only one shown in FIG. 2H) are flip-chip bonded to the semiconductor wafer 110′. Each of the second chip 150 is connected to a corresponding one of the bump pads 142 through a corresponding first bump 182. Additionally, in the present embodiment, the first underfill 162 is optionally applied between the second chips 150 and the second wiring layer 130, with the first underfill 162 enclosing the first bumps 182. The step of filling underfill 162 may be performed before or after the second chips 150 are flip-chip bonded to the semiconductor wafer 110′. That is, the first underfill 162 may be formed on the second wiring layer 130 before each of the second chips 150 is bonded to the semiconductor wafer 110′, or may be filled between the second chips 150 and the second wiring layer 130, after each of the second chips 150 is bonded to the semiconductor wafer 110′.

As shown in FIG. 2I, after the second chips 150 are flip-chip bonded to the semiconductor wafer 110′, the semiconductor wafer 110′ is sawed into a plurality of individual first chips 110.

As shown in FIG. 2J, the first chip 110 is flip-chip bonded to the carrier substrate 170. The through silicon vias 112 of the first chip 110 are electrically connected to the carrier substrate 170 via the second bumps 184. Additionally, in the present embodiment, the second underfill 164 may also be filled between the first chip 110 and the carrier substrate 170 to enclose the second bumps 184. The second underfill 164 may be pre-formed on the carrier substrate 170 before the first chip 110 is bonded to the carrier substrate 170, or filled between the first chip 110 and the carrier substrate 170 after the first chip 110 is bonded to the carrier substrate 170.

FIG. 2H′ and 2I′ depicts a subsequent process of sawing the semi-finished product in the form of individual chips, and then stacking the individual chip on a carrier substrate.

As shown in FIG. 2H′, the semiconductor wafer 110′ is sawed into a plurality of the individual first chips 110. As shown in FIG. 2I′, after the semiconductor wafer 110′ is sawed, one of the individual first chips 110 is flip-chip bonded to the carrier substrate 170. Then, as shown in 2J, the second chip 150 is flip-chip bonded to the individual first chip 110.

In addition, as shown in FIG. 2K, the heat sink 190 may be disposed on the first chip 110, substantially completing the fabrication of the semiconductor structure 100. The heat sink 190 covers the second chip 150 and is thermally coupled to the heat dissipation layer 144.

While the invention has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the invention. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The illustrations may not be necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present invention which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the invention. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the invention. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the invention.