СПОСОБ ИЗГОТОВЛЕНИЯ ГИБКИХ ЭЛЕКТРОННЫХ СХЕМ, ИМЕЮЩИХ КОНФОРМНЫЕ МАТЕРИАЛЬНЫЕ ПОКРЫТИЯ

Предложен способ изготовления гибкой электронной схемы. Способ включает образование формы из позитивного фоторезиста на гибкой полимерной подложке, имеющей множество металлических дорожек, нанесение конформного материального покрытия поверх формы из позитивного фоторезиста, гибкой полимерной подложки и металлических дорожек, удаление излишка конформного материального покрытия путем выполнения прохода ножевого полотна над формой из позитивного фоторезиста, удаление формы из позитивного фоторезиста для открывания полости, заданной конформным материальным покрытием, подачу анизотропной проводящей пасты в полость, вставление кристалла в полость и присоединение кристалла к проводящим дорожкам. Изобретение обеспечивает более точный контроль толщины конформного материального покрытия. 3 н. и 15 з.п. ф-лы, 14 ил.

Repeated firing resistant ceramic circuit substrate

A low temperature fired ceramic circuit substrate has laminated insulating layers of ceramic fired at 800-1000 deg C, a silver-based conductive wiring in the inner insulating layer and a gold-based conductive wiring on the surface insulating layer, the novelty being that a metallic interlayer (16), formed from a gold/silver-based thick film paste, is provided between the inner layer wiring (15) and the surface layer wiring (17). Preferably, the gold-silver material contains 10-80 wt.% Au and 90-20 wt.% Ag.

Verfahren zur Herstellung einer Halbleitervorrichtung mit einem keramischen Substrat und einem integrierten Schaltungskreis

Verfahren zur Herstellung einer elektrischen Verbindung für eine integrierte Schaltung.

Verfahren zur Bildung einer Drahtbondelektrode auf einer Dickschichtleiterplatte

Verfahren zum Herstellen einer Drahtbondelektrode auf einer Dickschichtleiterplatte, bei welcher eine Kupfer-Dickschicht (2) als Verdrahtungsschicht auf einem isolierenden Substrat (1) gebildet ist und ein auf dem isolierenden Substrat angebrachtes Teil (7) elektrisch mit der Kupfer-Dickschicht (2) über einen Golddraht (8) verbunden ist, mit: einem Schritt des Druckens der Kupfer-Dickschicht (2) auf das isolierende Substrat und des Sinterns der Kupfer-Dickschicht zur Bildung der Verdrahtungsschicht; und einem Schritt des Druckens einer Gold-Dickschicht, welcher vor dem Drucken Kupfer hinzugefügt worden ist, auf das isolierende Substrat und des Sinterns der Gold-Dickschicht als Drahtbondelektrode, um wenigstens partiell die Kupfer-Dickschicht zu überlappen, welche auf dem isolierenden Substrat gebildet ist.

Designmethode für auf einem Träger angeordnete VLSI-Chips und resultierender Modul

Laminat mit integriertem elektronischen Bauteil

Die Erfindung betrifft Verfahren zur Herstellung eines Laminats zur Kontaktierung wenigstens eines elektronischen Bauteils, bei dem zwischen einer ersten Metallschicht und einer zweiten Metallschicht eine isolierende Schicht angeordnet wird, die Metallschichten in zumindest einem Kontaktbereich miteinander kontaktiert werden, in der isolierenden Schicht zumindest eine Aussparung erzeugt wird oder erzeugt werden, die Metallschichten mit der isolierenden Schicht laminiert werden, in der ersten Metallschicht im Kontaktbereich zumindest eine Ausnehmung zur Aufnahme wenigstens eines elektronischen Bauteils erzeugt wird, zumindest ein elektronisches Bauteil in wenigstens eine, durch eine Ausnehmung und eine Aussparung gebildete Vertiefung im Laminat eingesetzt und leitend mit der zweiten Metallschicht verbunden wird, so dass das elektronische Bauteil vollumfänglich in der Aussparung und/oder der Ausnehmung aufgenommen wird und, bezogen auf die Höhe (H) des elektronischen Bauteils, zumindest teilweise ...

VERBESSERTE POLYARYLENETHERZUSAMMENSETZUNGEN UND VERFAHREN ZU IHRER HERSTELLUNG

Method for increasing thermal mechanical resistance of ceramic substrate for mounting electrical components, involves covering edges of metallization layer by applying electrical isolation fill material between edges and substrate

The method involves forming a metallization layer (6) of thickness of 100mu m, on a substrate (5) made of ceramic material. The edges of the metallization layer are patterned. The edges of the metallization layer are covered by applying electrical isolation fill material (8) between the edges of the metallization layer and substrate. An independent claim is included for material composite of ceramic substrate.

Optoelektronisches Bauelement und Verfahren zur Herstellung von optoelektronischen Halbleiterbauelementen

Es wird ein optoelektronisches Halbleiterbauelement (1) mit einem Träger (5) und einem Halbleiterkörper (2) angegeben, wobei der Halbleiterkörper an dem Träger befestigt ist und eine Halbleiterschichtenfolge mit einem zum Erzeugen und/oder zum Empfangen von Strahlung vorgesehenen aktiven Bereich (20), einer ersten Halbleiterschicht (21) und einer zweiten Halbleiterschicht (22) aufweist. Der aktive Bereich ist zwischen der ersten Halbleiterschicht und der zweiten Halbleiterschicht angeordnet. Der Träger ist elektrisch leitfähig und in einen ersten Trägerkörper (51) und einen zweiten Trägerkörper (52) unterteilt, wobei der erste Trägerkörper und der zweite Trägerkörper voneinander elektrisch isoliert sind. Der erste Trägerkörper weist auf der dem Halbleiterkörper abgewandten Seite einen ersten externen Kontakt (61) des Halbleiterbauelements auf, wobei der erste Kontakt über den ersten Trägerkörper mit der ersten Halbleiterschicht elektrisch leitend verbunden ist. Der zweite Trägerkörper weist ...

SEMICONDUCTOR PACKAGE

Manufacturing ceramic multilayer circuit of green ceramic foils

Into the green ceramic foils are stamped through contact apertures (1) and filled with an A6 conductive paste. Then A6 etc. conductive path (2) are printed onto the foils. The ceramic foils are assembled into a stack (3) and interconnected by compression, followed by sintering. During and/or after sintering outer A6 conductive paths (4) and/or contacts (5) are deposited onto the outer sides (10) of the foil stack and a metal protection layer, preferably of Ni and/or Au is coated onto the outer conductive paths and/or contacts, i.e. the latter are first coated with an Ni layer and then with an Au film.

Input/output architecture for mounted processors, and methods of using same

Semiconductor chip housing and method of manufacture

A semiconductor chip housing provides hermetic sealing and appropriate electrical characteristics for use at high frequencies. The housing comprises a substrate in which the chip is mounted and a cylindrical tube having a top cover and extending above the substrate which impinges on a base and thus hermetically seals the chip. Microthin leads extend from the substrate periphery to the chip. The leads carrying high frequency signals have notches therein to compensate for the impedance introduced by the tube and to enable the microstrip to present a constant impedance at high frequencies throughout its length.

Nput/output architechture for mounted processors, and methods of using same

Method for manufacturing an electronic module

Die vorliegende Erfindung betrifft em elektronisches Modul mit zumindest emer Komponente, die in Isoliermaterial eingebettet ist. Das elektronische Modul umfasst ein erstes Isoliermaterial mit einer ersten Oberfläche und einer zweiten Oberfläche und einer Dicke zwischen der ersten Oberfläche und der zweiten Oberfläche, zumindest eine Öffnung durch das erste Isoliermaterial, ein zweites Isoliermaterial auf der zweiten Oberfläche des ersten Isoliermaterials, zumindest eine Komponente, die in das zweite Isoliermaterial eingebettet ist, zumindest eine leitende Struktur in der zumindest einen Öffnung, wobei die zumindest eine leitende Struktur eine erste Oberfläche und eine zweite Oberfläche hat, wobei die zweite Oberfläche dem zweiten Isoliermaterial zugewandt ist und die erste Oberfläche vom zweiten Isoliermaterial abgewandt ist und eine Distanz zwischen der ersten Oberfläche des ersten Isoliermaterials und der zweiten Oberfläche der zumindest einen leitenden Struktur geringer oder größer ...

PROCEDURE FOR THE ESTABLISHMENT OF AN ELECTRONIC CONSTRUCTION UNIT ON A PRINTED CIRCUIT BOARD, PRODUCTION PROCEDURE OF A TRÄGERLAGE AND A SPAN, AS WELL AS SYSTEM CONSISTING OF A PRINTED CIRCUIT BOARD AND AT LEAST AN ELECTRONIC CONSTRUCTION UNIT

HERMETIC PACKAGE FOR INTEGRATED CIRCUIT CHIPS

Tab tape ball grid array package with vias laterally offset from solder ball bond sites

CIRCUIT BOARD, METHOD FOR MANUFACTURING SAME, AND HIGH-OUTPUT MODULE

A circuit board comprising a patterned first metal layer 14 formed on a ceramic substrate 11, a patterned second metal layer 16 formed on the first metal layer, and a third metal layer 17 formed covering the entire upper surface and side surfaces of the second metal layer and a part of the upper surface of the first metal layer, wherein portions of the first metal layer not covered by the third metal layer are reduced in width by etching. The circuit board has thick-film fine wiring patterns with high bonding strength between the wiring patterns and the substrate and high reliability and enables realization of high-output modules which are small in size and high in performance, by mounting at least one high-output semiconductor element thereon.

INTEGRATED CIRCUIT CHIPS MOUNTING AND PACKAGING ASSEMBLY

SEMICONDUCTOR DEVICE PACKAGE

APPARATUS FOR MOUNTING A SEMICONDUCTOR CHIP AND MAKING ELECTRICAL CONNECTIONS THERETO

METHOD FOR FIXING AN ELECTRONIC COMPONENT ON A PRINTED CIRCUIT BOARD AND SYSTEM COMPRISING A PRINTED CIRCUIT BOARD AND AT LEAST ONE ELECTRONIC COMPONENT

In a method for fixing an electronic component (3) on a printed circuit board (2), and contact-connecting the electronic component (3) to the printed circuit board (2), the following steps are provided: - providing the printed circuit board (2) having a plurality of contact and connection pads (8), - providing the electronic component (3) having a number of contact and connection locations (5) corresponding to the plurality of contact and connection pads (8) of the printed circuit board (2), with a mutual spacing reduced in comparison with the spacing of the contact and connection pads (8) of the printed circuit board (2), and ~ arranging or forming at least one interlayer (4) for routing the contact and connection locations (5) of the electronic component (3) between the contact and connection pads (8) of the printed circuit board (2) and the contact and connection locations (5) of the electronic component (3). A method for producing an interlayer (4) for routing and a system having a ...

SEMICONDUCTOR DEVICE

Provided is a technology of suppressing semiconductor breakage due to a temperature change. For flip chip mounting a silicon chip on a build-up multilayer substrate employing a structure having a thinned core material, t he core material having a small linear expansion coefficient is used for the multilayer substrate, the linear expansion coefficient of an underfill material and a glass transition point are suitably designed, corresponding t o the thickness and the linear expansion coefficient of the core material. Thu s, a stress inside a semiconductor package generated by deformation or the like of the multilayer substrate due to the temperature change is modified, and breakage of the semiconductor package due to the temperature change is suppressed.

SEMICONDUCTOR DEVICE

The invention offers technology for suppressing damage to semiconductor devices due to temperature changes. When flip-chip mounting a silicon chip on a buildup type multilayer substrate having a structure with a thinned core, a core having a small coefficient of thermal expansion is used in the multilayer substrate, and the coefficient of thermal expansion and glass transition point of the underfill are appropriately designed in accordance with the thickness and coefficient of thermal expansion of the core. By doing so, it is possible to relieve stresses inside the semiconductor package caused by deformation of the multilayer substrate due to temperature changes, and thereby to suppress damage to the semiconductor package due to temperature changes.

A SOC DESIGN WITH CRITICAL TECHNOLOGY PITCH ALIGNMENT

An SOC apparatus includes a plurality of gate interconnects with a minimum pitch g, a plurality of metal interconnects with a minimum pitch m, and a plurality of vias interconnecting the gate interconnects and the metal interconnects. The vias have a minimum pitch v. The values m, g, and v are such that g 2+m 2=v 2 and an LCM of g and m is less than 20g. The SOC apparatus may further include a second plurality of metal interconnects with a minimum pitch of m2, where m2 > m and the LCM of g, m, and m 2 is less than 20g.

APPLICANT SCREENING

Systems (100, 2700) and methods (3400) for screening applicants (102, 2702) are disclosed herein. A method (3400) of screening applicants (102, 2702) is performed by a screening server (112, 2712). The server (112, 2712) begins by receiving (3402) a selection of screening services and an applicant profile that identifies an applicant (102, 2702). The screening continues by generating (3404) screening results specified by the selection of screening services based on the applicant profile. A property manager (120, 2720) is then notified (3406) that the screening results are available for the applicant (102, 2702) based upon the applicant profile. The screening results are then provided (3410) to the property manager (120, 2720) based upon the applicant profile. Based on these screening results, the screener or property manager (120, 2720) can make a decision about the applicant (102, 2702) and communicate a decision action to the applicant (102, 2702).

SUBSTRATE WITH CONDUCTOR FORMED OF LOW-RESISTANCE ALUMINUM ALLOY

A wiring substrate is disclosed, which has optimal characteristics for, for example, an active matrix type liquid crystal display device with a thin film transistor. Wiring formed of an Al-Nd-Ti alloy thin film is formed on a glass substrate, and if necessary, a semiconductor element which is electrically connected to the wiring is formed. In this case, the specific resistance of the Al-Nd-Ti alloy thin film is about 8 .mu..OMEGA. cm if the Nd concentration is 0.75 at % and the Ti concentration is 0.5 at %. Further, even if the resultant substrate is heated at 240 - 270 ~C after the formation of the wiring, occurrence of a hillock and a pinhole is substantially completely suppressed.

TAB TAPE BALL GRID ARRAY PACKAGE WITH VIAS LATERALLY OFFSET FROM SOLDER BALL BOND SITES

A ball grid array (BGA) package is provided in which the stiffener of the BGA may also be utilized as a conductive layer. A TAB tape is adhered to the stiffener by an adhesive and both the TAB tape and the adhesive may have vias which open to the stiffener. Conductive plugs which may be formed of solder paste, conductive adhesives, or the like may then be filled in the vias to provide electrical connection from the TAB tape to the stiffener. The vias may be located adjacent to solder ball locations. The TAB tape may include multiple conductor layers or multiple layers of single conductive layer TAB tape may be stacked upon each other to provide additional circuit routing. Further, the TAB tape layers may also be combined with the use of metal foil layers.

THERMOSETTING ENCAPSULANTS FOR ELECTRONICS PACKAGING

An electronic package is provided wherein a semiconductor device on a substrate is encapsulated with a thermally reworkable encapsulant composition comprising: (a) a thermally reworkable cross-linked resin produced by reacting at least one dienophile having a functionality greater than one and at least one 2,5-dialkyl substituted furan-containing polymer, and (b) at least one filler present from 25 to 75 percent by weight based upon the amount of components (a) and (b). Such a process provides a readily reworkable electronic package.

Verfahren zur Herstellung einer Halbleitervorrichtung

GRAPHITE-LAMINATED CHIP-ON-FILM-TYPE SEMICONDUCTOR PACKAGE HAVING IMPROVED HEAT DISSIPATION AND ELECTROMAGNETIC WAVE SHIELDING FUNCTIONS

Chip package and method for forming the same

The present invention provides a chip package and a method for forming the same. The chip package includes a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface; and a conducting pad structure disposed in the dielectric layer and electrically connected to the device region; a cover substrate disposed between the chip and the cover substrate, wherein the spacer layer, a cavity is created an surrounded by the chip and the cover substrate on the device region, and the spacer layer is in direct contact with the chip without any adhesion glue disposed between the chip and the spacer layer. The chip package technology provided in the invention can reduce the size of the chip package, facilitate large-scale production of chip packages, and ensure the quality of the chip packages, and/or reduce the process cost and time.

Semiconductor device packages with electromagnetic interference shielding

Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit defining a cut-out portion disposed adjacent to a periphery of the substrate unit; (2) a grounding element disposed in the cut-out portion and at least partially extending between an upper surface and a lower surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device and the grounding element; and (5) an EMI shield disposed adjacent to exterior surfaces of the package body. The EMI shield is electrically connected to a connection surface of the grounding element, such that the grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.

Device and method for aligning substrates

Semiconductor package comprising the aerial and its manufacturing method

Package carrier plate and its manufacturing method

STRUCTURE DE MONTAGE POUR CIRCUITS INTEGRES RAPIDES

L'INVENTION CONCERNE LA TECHNOLOGIE DES CIRCUITS INTEGRES. UNE STRUCTURE DE MONTAGE POUR UN CIRCUIT INTEGRE COMPREND NOTAMMENT UN SUBSTRAT SEMI-CONDUCTEUR 34 SUR LEQUEL EST MONTE UN CIRCUIT INTEGRE 28. DANS CE SUBSTRAT SONT FORMES DES LIGNES DE TRANSMISSION A IMPEDANCE DEFINIE 20, 36, 42, DES LIGNES D'ALIMENTATION ET DE MASSE ET DES COMPOSANTS ELECTRONIQUES 14, 16, 26 CONNECTES AU CIRCUIT INTEGRE. CETTE STRUCTURE DE MONTAGE EVITE LA DEGRADATION DES CARACTERISTIQUES DE VITESSE DU CIRCUIT INTEGRE 28. APPLICATION AUX CIRCUITS INTEGRES A L'ARSENIURE DE GALLIUM.

SUBSTRAT DE CONNEXION EN CERAMIQUE MUNI DE PROTUBERANCES DE RACCORDEMENT A LA PASTILLE DE CIRCUIT INTEGRE

Ce dispositif à semiconducteurs comporte un motif de circuit 14, sur un film conducteur fin formé sur un substrat 11 en céramique au moyen d'une gravure, et une pastille 15, de circuit intégré connectée au motif de circuit gravé par l'intermédiaire d'une liaison par couplage dans laquelle les plots respectifs 17 des parties de conduction du motif de circuit et de la pastille de circuit intégré viennent directement en contact les uns avec les autres. Par conséquent, le motif de circuit peut être conçu de façon à être dense, et contribuer à une plus grande intégration de la pastille de circuit intégré.

SEMICONDUCTOR DEVICE PACKAGE

CASE OF ELECTRONIC CIRCUITS HAS SEMICONDUCTOR PASTILLES ROWS AND SUPERPOSEES

PROCESS AND DEVICE Of ASSEMBLY AND TEST OF JUST CIRCUITS

TRANSMISSION DEVICE RF INTEGRATED ELECTROMAGNETIC WAVE REFLECTOR

Dispositif de transmission RF (100) comprenant au moins : - un substrat (102) comportant des première et deuxième faces (104, 106) opposées l'une de l'autre ; - un premier circuit électronique de transmission RF (108) disposé sur et/ou dans le substrat ; - une première antenne (112a) disposée du côté de la première face du substrat, espacée de la première face du substrat et reliée électriquement au premier circuit électronique de transmission RF ; - un premier réflecteur d'ondes électromagnétiques couplé à la première antenne et comprenant : - une première surface à haute impédance (114a) comportant au moins plusieurs premiers éléments électriquement conducteurs (118) formant une première structure périodique et disposés sur la première face du substrat en regard de la première antenne ; - un premier plan de masse électriquement conducteur (116a) disposé au moins partiellement en regard de la première antenne.

반도체 패키지 및 그 형성 방법

... 본 발명의 실시예들은 반도체 패키지 및 그 형성 방법을 포함한다. 일실시예는, 제1 다이, 제1 전기 연결부, 및 제1 다이와 제1 전기 연결부에 연결된 제1 재배선층을 포함하는 제1 다이 패키지를 형성하는 단계, 제1 다이 패키지 위에 언더필을 형성하는 단계, 제1 전기 연결부의 일부분을 노출시키기 위해 개구부를 갖도록 언더필을 패터닝하는 단계, 상기 언더필의 개구부 내에서 제1 전기 연결부에 연결된 접합 구조체에 의해 제1 다이 패키지에 제2 다이 패키지를 접합하는 단계를 포함하는 방법이다.

STACKED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING STACKED MICROELECTRONIC DEVICES

WIRING BOARD IN WHICH A PAD FOR MOUNTING A SEMICONDUCTOR DEVICE IS INSTALLED AND A MANUFACTURING METHOD THEREOF

PURPOSE: A wiring board is provided to maintain reliability of connection and not to obstruct the miniaturization of wiring and not to cause performance degradation of the wiring board by including a pad for outside connection. CONSTITUTION: A wiring board comprises: Insulating layer(7); a wiring layer installed at the single-side of the insulating layer; a pad for outside connection(1) installed at the other surface of the insulating layer; a surface coating layer(2), which is formed on the outside pad, for connection with the external circuit; a plurality of wiring layers; and a plurality of insulating layers installed between a plurality of wiring layers. The area of the pad for outside connection is smaller than the area of the surface coating layer. The pad for outside connection characterizes to be the pad for mounting the electronic component including the semiconductor device etc. in the wiring board. © KIPO 2009 ...

FLEXIBLE LIGHT EMITTING SEMICONDUCTOR DEVICE

CONJUNTO HERMETICAMENTE SELADO

Semiconductor device

Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip.

Chip on flex tape

To provide a chip on flex (COF) tape having an improved precision of cumulative pitches while retaining bending properties. A chip on flex (COF) tape having a wiring pattern comprising a plurality of wirings arranged in parallel formed on the surface of a flexible insulating film, wherein a dimension retention pattern is formed on said surface of said flexible insulating film and/or the surface of the side of the film opposite thereto so as to cross the width direction of at least two of said wirings arranged in parallel in the vicinity of the connecting portion of said wiring pattern with a semiconductor chip and/or the connecting portion with an external device.

Microelectronic conductive routes and methods of making the same

A conductive route structure may be formed comprising a conductive trace and a conductive via, wherein the conductive via directly contacts the conductive trace. In one embodiment, the conductive route structure may be formed by forming a dielectric material layer on the conductive trace. A via opening may be formed through the dielectric material layer to expose a portion of the conductive trace and a blocking layer may be from only on the exposed portion of the conductive trace. A barrier line may be formed on sidewalls of the via opening and the blocking layer may thereafter be removed. A conductive via may then be formed within the via opening, wherein the conductive via directly contacts the conductive trace.

Integrated fan-out package

An integrated fan-out package including a die attach film, an integrated circuit component, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component is disposed on the die attach film and includes a plurality of conductive terminals. The die attach film includes an uplifted edge which raises toward sidewalls of the integrated circuit component. The insulating encapsulation encapsulates the uplifted edge and the integrated circuit component. The redistribution circuit structure is disposed on the integrated circuit component and the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals of the integrated circuit component. A method of fabricating the integrated fan-out package is also provided.

Method for producing a semiconductor device and corresponding semiconductor device

The present invention provides a method for producing a semiconductor device, with the steps of: applying an interconnect level (11, 12) to a semiconductor substrate (10); structuring the interconnect level (12); and applying a solder layer (13) on the structured interconnect level (11, 12) in such a way that the solder layer ...

Metal duplex and method

Semiconductor package and manufacturing method thereof

CERAMIC SUBSTRATE, ELECTRONIC DEVICE AND METHOD FOR PRODUCING CERAMIC SUBSTRATE

... [PROBLEMS] To provide a ceramic substrate excellent in bonding reliability of an external electrode to a substrate main body and in high density mounting performance of mounting components, and to provide an electronic device employing it and a method for producing a ceramic multilayer substrate for producing the ceramic substrate efficiently. [MEANS FOR SOLVING PROBLEMS] An external electrode (6) has a surface portion (4) formed on the major surface of a substrate body (1), and an anchor portion (5) extending from the circumferential edge of the surface portion in the direction perpendicular to the major surface of the substrate main body and engaging with the substrate main body under a state embedded in the substrate body. The anchor portion is formed on the entire circumference at the circumferential edge of the surface portion. At least a part of the circumferential edge in the surface portion forming region of an unburnt ceramic molding is irradiated with a laser beam to form a groove ...

FLIP-CHIP MODULE AND METHOD FOR THE PRODUCTION THEREOF

The invention relates to a flip-chip module comprising a semiconductor chip provided with contact columns, which are electrically and mechanically connected to a substrate. A spacer is provided between the substrate and the semiconductor chip and mechanically coupled with the substrate and/or the chip. Thermal stresses in the flip chip module are absorbed by the spacer and are kept away from the semiconductor chip. Said invention also relates to a method for producing a flip chip module consisting in placing the spacer between the semiconductor chip and the substrate and in soldering the contact columns with the substrate contact points. The use of the spacer makes it possible to accurately adjust the distance between the semiconductor chip and the substrate, thereby improving the quality of the soldering points.

DISTRIBUTED CLOCK TREE SCHEME IN SEMICONDUCTOR PACKAGES

A clock plane (80) is embedded in the housing of a semiconductor chip package (14) where the plane (80) is connected to two or more clock pads (54, 56) on the semiconductor die (52) through vias, bonding fingers (62, 64) and bonding wires (72, 74). The two or more clock pads (54, 56) are connected by one or more clock lines (58). The clock plane (80) is connected by means of a via (112) to a clock input pin (116). In this manner, a clock signal fed to the clock input pin (116) is driven through the one or more clock line (58) with its tributaries from two separate locations by two or more input clock pads (54, 56). This reduces clock skew and permits a smaller area of the die surface (52) to be taken up by the clock lines.

Wiring substrate and process for manufacturing the same

A wiring substrate incorporating nickel-plated copper terminal pads for solder bumps, wherein a nickel plating layer constituting the nickel plated copper terminal pads has a phosphorus content of 8.5 to 15.0% by mass and is covered with a gold plating layer.

Semiconductor device

A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.

Metal duplex method

Methods and articles are disclosed. The methods are directed to depositing nickel duplex layers on substrates to inhibit corrosion and improve solderability of the substrates. The substrates have a gold or gold alloy finish.

Semiconductor chip housing

A semiconductor chip housing provides hermetic sealing and appropriate electrical characteristics for use at high frequencies. The housing comprises a substrate in which the chip is mounted and a cylindrical tube having a top cover and extending above the substrate which impinges on a base and thus hermetically seals the chip. Microthin leads extend from the substrate periphery to the chip. The leads carrying high frequency signals have notches therein to compensate for the impedance introduced by the tube and to enable the microstrip to present a constant impedance at high frequencies throughout its length.

PACKAGING SEMICONDUCTOR CHIPS

Dual electronic component assembly

Two related miniature components are attached to opposite sides of an insulating base member. There are conductive pads and through-holes in the base member. The conductive areas on each component are wire-bonded to adjacent conductive areas on the base member. Some of the latter are coupled to the bottom surface of the assembly but the connections between the two components are made via metallization in the through-holes. Insulating covers seal each side of the assembly and the entire assembly may be reflow soldered to external circuitry.

Semiconductor device, methods of production of the same, and method of mounting a component

A semiconductor device including a package board having interconnection patterns on one main surface, a semiconductor chip electrically connected through internal terminations to the interconnection patterns of the package board and having an element forming surface facing the package board across a space, and a conductive plate connected to a back surface of the semiconductor chip of a side opposite to the element forming surface through a conductive bonding layer, the semiconductor chip being sealed in a resin formed in a circumferential direction in the space between the package board and the conductive plate, one main surface of the package board being provided with a depression enlarging the space in the thickness direction of the package board.

Thermal Vias In An Integrated Circuit Package With An Embedded Die

In a multi-module integrated circuit package having a package substrate and package contacts, a die is embedded in the package substrate with thermal vias that couple hotspots on the embedded die to some of the package contacts.

Circuit assemblies with multiple interposer substrates, and methods of fabrication

A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.

PRODUCTION OF A CHIP MODULE

A method of producing a chip module includes providing a carrier; arranging semiconductor chips on the carrier; applying an electrically insulating material on the carrier; and structuring the carrier such that the chip module is provided, wherein the chip module includes separate carrier sections produced by structuring the carrier, the carrier sections of the chip module connected by the electrically insulating material.

Substrate for semiconductor package and method of manufacturing thereof

Disclosed is a substrate for a semiconductor package in which leakage of radiation noise from a gap between a semiconductor element and a mounting substrate can be prevented. The substrate for the semiconductor package includes a coplanar waveguide including a signal and ground electrodes on the mounting substrate, the signal electrode flip-chip connected to the semiconductor element, the ground electrodes arranged on both sides of the signal electrode with intervals therebetween. A step part is formed in the ground electrodes in an outer circumferential part of a mounting region of the semiconductor element, the step part having a larger distance between upper surfaces of the mounting substrate and the ground electrode in the outer circumferential part of the mounting region than such distance in the mounting region, and an insulator for covering the signal electrode in the outer circumferential part of the mounting region is formed.

High density ball grid array (BGA) package capacitor design

A circuit package is provided that includes a substrate having a first side and a second side, an integrated circuit component coupled to the second side of the substrate, and a ball grid array formed on the first side of the substrate, the ball grid array including multiple contact balls arranged in a pattern. Each of a first subset of the contact balls is electrically coupled to a first voltage input of an integrated circuit component, and each of a second subset of the contact balls is electrically coupled to a second voltage input of the integrated circuit component. The package also includes a capacitor mounted to the first side and having a first terminal coupled to a first contact ball in the first subset of the contact balls and a second terminal coupled to a second contact ball in the second subset of the contact balls.

Air trench in packages incorporating hybrid bonding

A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.

INTERPOSER HAVING MOLDED LOW CTE DIELECTRIC

A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel.

3D stacked semiconductor memory architecture with conductive layer arrangement

According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.

Semiconductor packages and methods of forming the same

Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including forming a first die package, the first die package including a first die, a first electrical connector, and a first redistribution layer, the first redistribution layer being coupled to the first die and the first electrical connector, forming an underfill over the first die package, patterning the underfill to have an opening to expose a portion of the first electrical connector, and bonding a second die package to the first die package with a bonding structure, the bonding structure being coupled to the first electrical connector in the opening of the underfill.

Wireless Charging Package with Chip Integrated in Coil Center

A package includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar with a top surface of the device die. A coil extends from the top surface to a bottom surface of the encapsulating material, and the device die is in the region encircled by the coil. At least one dielectric layer is formed over the encapsulating material and the coil. A plurality of redistribution lines is in the at least one dielectric layer. The coil is electrically coupled to the device die through the plurality of redistribution lines.

Printed wiring board

A method of manufacturing a printed wiring board includes preparing a wiring substrate having a conductive circuit, coating a solder-resist layer over the conductive circuit, leveling a surface of the solder-resist layer so as to obtain a maximum surface roughness in a predetermined range, removing the resin film from the surface of the solder-resist layer, and forming multiple openings in the surface of the solder-resist layer to expose multiple portions of the conductive circuit so as to form multiple conductive pads for mounting an electronic components.

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device package is provided that includes a substrate, a first support structure disposed on the substrate and a first antenna. The first support structure includes a first surface spaced apart from the substrate by a first distance. The first antenna is disposed above the first surface of the first support structure. The first antenna has a first surface, a second surface opposite the first surface and a third surface extending from the first surface to the second surface, wherein the first surface and the second surface of the first antenna are exposed.

STACKED MICROELECTRONIC DEVICES AND METHODS FOR MANUFATURING STAKED MICROELECTRONIC DEVICES

CdTe CRYSTAL OR CdZnTe CRYSTAL AND METHOD FOR PREPARING THE SAME

A process for manufacturing a chip carrier substrate, the process including the steps of providing a first layer of copper conductor on a substrate, forming a first layer of barrier metal on the first layer of copper conductor, forming a layer of aluminum on the first layer of barrier metal, forming a second barrier metal on the aluminum layer, patterning the top barrier metal in the form of studs, anodizing the aluminum unprotected by the top barrier metal, removing the aluminum oxide and patterning the first copper layer, removing all the exposed barrier metal; surrounding the studs and the copper conductor with a polymeric dielectric; polishing the polymeric dielectric to expose the studs; and forming a second layer of copper conductor on the planar polymeric dielectric.

ПЕРСОНАЛЬНЫЙ НОСИТЕЛЬ ДАННЫХ

Изобретение относится к способам защиты носителя данных от несанкционированного использования и подделки. Техническим результатом является увеличение защищенности от несанкционированного использования и подделки чип-карты. Носитель данных включает: корпус носителя, выполненный в виде уникальной пространственно развитой объемной фигуры, и в качестве элементов персонализации и защиты содержит визуально распознаваемые первые элементы защиты в виде элементов, идентифицирующих владельца носителя данных; чип-модуль, выполненный быстросъемным с возможностью его установки во внутренней полости корпуса носителя и содержащим в качестве элементов персонализации и защиты визуально распознаваемые вторые элементы защиты; при этом каждый из первых и вторых элементов защиты содержит, по меньшей мере, один фрагмент, приспособленный для предварительного сканирования в определенной, известной владельцу позиции; чип-модуль содержит необходимую информацию о признаках платежной системы. 2 н. и 28 з.п. ф-лы, ...

НЕСУЩИЙ ЭЛЕМЕНТ ДЛЯ ПОЛУПРОВОДНИКОВОЙ МИКРОСХЕМЫ

Использование: для монтажа в карточке с встроенным микропроцессором, для пайки на печатных схемах. Сущность изобретения: медное покрытие пластмассовой пленки структурируют с помощью травления так, что контактные поверхности выполнены как одно целое с заканчивающимися на кромке несущего элемента проводниками, которые обеспечивают надежную пайку. Техническим результатом изобретения является создание несущего элемента для полупроводниковой микросхемы, который выполняет как распространяющиеся на карточки с встроенным микропроцессором нормы ISO, так и пригоден для монтажа на поверхности. 11 з.п. ф-лы, 7 ил.

Mehrschicht-Schaltkreiskarte mit verbesserter Stromführungskapazität und Verfahren zu ihrer Herstellung

Beschrieben wird eine Mehrschicht-Schaltkreiskarte (100), bei der eine Mehrzahl von isolierenden Schichten und eine Mehrzahl von leitfähigen Schichten, von denen jede ein leitfähiges Muster (22, 22a) beinhaltet, aufeinanderlaminiert werden. Die Mehrschicht-Schaltkreiskarte beinhaltet wenigstens eine der besagten isolierenden Schichten, einen leitfähigen Bestandteil (51) und wenigstens eines der leitfähigen Muster (22a). Die isolierende Schicht weist wenigstens einen Graben auf. Der isolierende Bestandteil (51) wird in dem Graben angeordnet. Das leitfähige Muster (22a) grenzt an den Graben an und ist elektrisch in Verbindung mit dem leitfähigen Bestandteil (51). Das leitfähige Muster (22a) und der leitfähige Bestandteil (51) bilden zusammen einen elektrisch leitfähigen Leiter, der eine höhere Stromkapazität hat als das leitfähige Muster (22a) alleine.

Method for manufacturing circuit device, involves making contact portion of semiconductor chip to project into contacting tub of strip guard

The adhesive (3) is coated on contacting region (4) of a semiconductor substrate (1), and a strip guard pattern (2) is formed in contacting region. The solder material (17) is brought in contact with contacting tubs (6) in strip guard, and applied on a contact portion (12) of a semiconductor chip (9). The contact portion of chip is made to project into contacting tub. The chip and contacting region of substrate are heated such that the chip is adhered with the substrate, and the chip contact portions are made to contact with contact surface (2.1) of strip guard pattern. An independent claim is included for circuit device.

Verfahren und Herstellung eines Elektronikmoduls und Elektronikmodul

KURZDARSTELLUNG DER OFFENBARUNG Eine Anzahl von Halbleiterchips beinhaltet jeweils eine erste Hauptseite und eine der ersten Hauptseite gegenüberliegende zweite Hauptseite. Die zweite Hauptseite beinhaltet mindestens ein elektrisches Kontaktelement. Die Halbleiterchips werden auf einen Träger platziert. Eine Materialschicht wird in die Zwischenräume zwischen benachbarten Halbleiterchips eingebracht. Der Träger wird entfernt, und eine erste elektrische Kontaktschicht wird auf die ersten Hauptseiten der Halbleiterchips aufgebracht, so dass die elektrische Kontaktschicht elektrisch mit jedem der elektrischen Kontaktelemente verbunden ist.

Versorgungs-/Erdungskonfiguration für impedanzarme integrierte Schaltung

Integrierte Schaltung, welche umfasst: ein Substrat, einen Chip, der auf dem Substrat angebracht ist, einen ersten Versorgungsanschluss, der auf dem Substrat angebracht und elektrisch mit dem Chip verbunden ist, wobei der erste Versorgungsanschluss einen Hauptteil und eine erste Erweiterung, die von dem Hauptteil vorsteht, aufweist, und einen ersten Erdungsanschluss, der auf dem Substrat angebracht und elektrisch mit dem Chip verbunden ist, wobei der erste Erdungsanschluss einen Hauptteil und eine zweite Erweiterung, die von dem Hauptteil vorsteht, aufweist, wobei die zweite Erweiterung an dem ersten Erdungsanschluss neben der ersten Erweiterung an dem ersten Versorgungsanschluss liegt.

Packung von Halbleiterchips

Input/output architecture for mounted processors, and methods of using same

Improvements in and relating to Semiconductor Devices

... 1,176,326. Semi-conductor devices; semiconductor circuit assemblies. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 13 Sept., 1966 [24 March, 1966], No. 40804/66. Headings H1K and H1R. A semi-conductor device comprises an insulating substrate 1 (Fig. 1) with metallization at three levels 10, 16, 15. An active semiconductor device, e.g. the planar silicon transistor shown, is mounted on the metallization at the lowest (or the intermediate) level which is connected to metallization at the upper level to provide an external collector connection. The interdigitated emitter 21 and base 22 are connected to metallization at the intermediate (or lowest) level which extends on to the top level to provide external connections 13, 15. In the embodiment the substrate is of alumina, beryllia or boron nitride extruded and cut to the form shown, or of moulded glass. The contoured surface is metallized overall by sputtering with titanium and then vapour depositing first platinum and then gold, which is ...

INTEGRATED CIRCUIT PACKAGE

In the fabrication of an integrated circuit package, leads 10 that carry an electrical signal from integrated circuits inside of the package to the outside are connected to conductors 70 inside the package prior to encapsulation in plastic. The conductors 70 are initially formed on a multilayer metal foil 40 by a photoresist method. The leads are soldered thereto at 75 and the package is placed in a mould 80. Thermoplastic is then injection moulded around the package and the metal foil 40 is finally removed from the package by etching. Integrated circuits may then be attached to the exposed conductors 70 within the package. ...

Circuit module and method of manufacturing the same

Input/output architecture for mounted processors including high-speed input/output trace

A high-speed input/output (I/O) trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate 112 includes an integrated heat spreader (IHS) footprint 118 on a die-side 130 and the I/O trace 134 to couple with an IC device 110 to be disposed inside the IHS footprint 118. The I/O trace 134 includes a pin-out terminal 136 outside the IHS footprint 118 to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s. The pin-out terminal 136 may be a detachable connector terminal for a flexible signal-transmission cable.

OVER/UNDER DUAL IN-LINE CHIP PACKAGE

SYSTEM AND PROCEDURE FOR MANUFACTURING A SOLAR CELL ARRAY

POLYMERE STUD GRID ARRAY PACKAGE

CARRIER ELEMENT FOR A SEMICONDUCTOR CHIP

OVER/UNDER DUAL IN-LINE CHIP PACKAGE

... : The present invention relates to an electronic circuit package for encapsulating and interconnecting two or more semiconductor chips. A vertically stacked array of substrate wafers form a support core in which windows are formed for receiving the chips. Device support surfaces and device lead connecting surfaces are exposed by each cavity on one or more of the substrate wafers. Intralevel conductive strips are separately deposited on each lead connecting surface for attachment to the input/output leads of the circuit devices and extend along the interface of one or more superposed pairs of substrate wafers for connection to external connector pins. Inter-level conductive interconnects are embedded in one or more of the substrates for interconnecting the intra-level conductive strips of one substrate level with the intralevel conductive strips of a different level. In a preferred embodiment, four identical RAM chips are encapsulated and interconnected for multiplex operation in an over ...

Driving circuit and liquid crystal display device including the same

A tape carrier package (TCP) includes a film, a plurality of output leads and a plurality of input leads on the film, the plurality of output leads and the plurality of input leads being disposed on different sides, first and second TCP alignment marks arranged on opposing sides of the plurality of output leads, and a third TCP alignment mark at a central portion of the plurality of output leads.

Wiring board and method for manufacturing the same

A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

Microelectronic packages with dual or multiple-etched flip-chip connectors

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Semiconductor device and package

A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate.

Methods of forming semiconductor chip underfill anchors

Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.

Conductive Sidewall for Microbumps

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

Ceramic electronic component and wiring board

A ceramic electronic component includes a ceramic element body having a substantially rectangular parallelepiped shape, and first and second external electrodes. The first and second external electrodes are provided on a first principal surface. Portions of the first and second external electrodes project further than the other portions in a thickness direction. A projecting portion of the first external electrode is provided at one end of the first external electrode in a length direction and a second projecting portion of the second external electrode is provided at another end of the second external electrode in the length direction. Thus, a concave portion is provided between the projecting portions, and a portion of the first principal surface provided between the first and second external electrodes is exposed.

Methods of forming semiconductor elements using micro-abrasive particle stream

A method of fabricating a microelectronic unit includes providing a semiconductor element having a front surface and a rear surface remote from the front surface, forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface by directing a jet of fine abrasive particles towards the semiconductor element, and forming at least one conductive contact and at least one conductive interconnect coupled thereto. The semiconductor element can include a plurality of active semiconductor devices therein. The semiconductor element can include a plurality of conductive pads exposed at the front surface. Each conductive interconnect can extend within one or more of the first openings and can be coupled directly or indirectly to at least one of the conductive pads. Each of the conductive contacts can be exposed at the rear surface of the semiconductor element for electrical connection to an external device.

Electronic module with vertical connector between conductor patterns

The present invention generally relates to a new structure to be used with electronic modules such as printed circuit boards and semiconductor package substrates. Furthermore there are presented herein methods for manufacturing the same. According to an aspect of the invention, the aspect ratio of through holes is significantly improved. Aspect ratio measures a relationship of a through hole or a micro via conductor in the direction of height divided width. According to the aspect of the invention, the aspect ratio can be increased over that of the prior art solution by a factor of ten or more.

Method of fabricating film circuit substrate and method of fabricating chip package including the same

A method of fabricating a film circuit substrate and a method of fabricating a chip package. The method of fabricating a film circuit substrate can include providing a base film including a chip packaging area to package a chip and a separation area to separate the two chip packaging areas from each other, the separation area including a cut area and an uncut area; forming a reserve interconnection pattern having a first height on the base film; and forming an interconnection pattern having a second height that is lower than the first height on the out area by selectively etching the reserve interconnection pattern of the cut area.

Chip package and fabricating method thereof

A chip package and a fabrication method thereof are provided. The chip package includes a substrate and a chip disposed over the substrate. A solder layer is disposed between the chip and the substrate. A conductive pad is disposed between the solder layer and the substrate, wherein the conductive pad includes a first portion disposed under the solder layer, a second portion disposed away from the first portion and a connective portion disposed between the first portion and the second portion. The connective portion has a width which is narrower than a width of the first portion along a first direction perpendicular to a second direction extending from the first portion to the connective portion.

Multi-Layer Circuit Assembly And Process For Preparing The Same

A process for fabricating a multi-layer circuit assembly is provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; (c) removing the dielectric coating in a predetermined pattern to expose sections of the substrate; (d) applying a layer of metal to all surfaces to form metallized vias through and/or to the electrically conductive core; (e) applying a resist to the metal layer to form a photosensitive layer thereon; (f) imaging resist in predetermined locations; (g) developing resist to uncover selected areas of the metal layer; and (h) etching uncovered areas of metal to form an electrical circuit pattern connected by the metallized vias.

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

Circuit substrate and manufacturing method thereof and package structure and manufacturing method thereof

A circuit substrate includes the following elements. A conductive layer and a dielectric layer are disposed on an inner circuit structure in sequence, and a plurality of conductive blind vias are embedded in the dielectric layer and connected to a portion of the conductive layer. A plating seed layer is disposed between each of the first blind vias and the first conductive layer. Another conductive layer is disposed on the dielectric layer, wherein a portion of the another conductive layer is electrically connected to the conductive layer through the conductive blind vias. A third plating seed layer is disposed between the third conductive layer and each of the first blind vias and on the first dielectric layer.

Energy Conditioning Circuit Arrangement for Integrated Circuit

The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.

Flexible circuit structure with stretchability and method of manufacturing the same

In one example embodiment, a flexible circuit structure with stretchability is provided that includes a flexible substrate, a plurality of flexible bumps formed on the flexible substrate, and a metal layer formed on the plurality of flexible bumps and the flexible substrate.

Semiconductor structure having conductive vias and method for manufacturing the same

A semiconductor structure includes a plurality of thermal vias and a heat dissipation layer disposed at a periphery of a back surface of a lower chip in a stacked-chip package. This arrangement improves solderability of a subsequently-bonded heat sink. Additionally, the thermal vias and the heat dissipation layer provide an improved thermal conduction path for enhancing heat dissipation efficiency of the semiconductor structure. A method for manufacturing the semiconductor structure is also provided.

Electronic component mounting method and electronic component mount structure

A challenge to be met by the present invention is to provide an electronic component mounting method and an electronic component mount structure that make it possible to assure bonding strength for an electronic component whose underside is provided with bumps. In electronic component mounting operation during which an electronic component ( 6 ) whose underside is provided with bumps ( 7 ) with solder is mounted on a substrate ( 1 ), a solder bonding material ( 3 ) including solder particles contained in a first thermosetting resin is used for bonding the bumps ( 7 ) to an electrode ( 2 ) formed on the substrate ( 1 ), thereby forming a solder bonding area ( 7 *) where the solder particles and the bumps ( 7 ) are fused and solidified and a first resin reinforcement area ( 3 a *) that reinforces the solder bonding area ( 7 *). Further, an adhesive ( 4 ) containing as a principal component a second thermosetting resin not including solder particles is used for fixing an outer edge ( 6 a ) of the electronic component ( 6 ) to reinforcement points set on the substrate ( 1 ). Even when the solder bonding material ( 3 ) and the bonding agent ( 4 ) are blended together, normal thermal curing of the thermosetting resin is not hindered. Bonding strength can thereby be assured for the electronic component ( 6 ) whose underside is provided with the bumps ( 7 ).

Semiconductor package

A semiconductor package includes a radiator plate including a stress alleviation section, a resin sheet arranged on the radiator plate, a pair of bus bars joined to the radiator plate through the resin sheet at positions at which the stress alleviation section is interposed between the bus bars, and a semiconductor device joined to the pair of bus bars by being sandwiched between the bus bars, and energized from outside through the pair of bus bars.

Multi-chip package with offset die stacking

A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed.

Semiconductor chip device with polymeric filler trench

A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package

A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.

Package substrate unit and method for manufacturing package substrate unit

A semiconductor chip mounting layer of a package substrate unit includes an insulation layer, a conductive seed metal layer formed on the top surface of the insulation layer, conductive pads formed on the top surface of the conductive seed metal layer, metal posts formed substantially in the central portion on the top surface of the conductive pads, and a solder resist layer that is formed to surround the conductive pads and the metal posts.

Crosslinkable dielectrics and methods of preparation and use thereof

The present invention relates to an electronic device comprising at least one dielectric layer, said dielectric layer comprising a crosslinked organic compound based on at least one compound which is radically crosslinkable and a method of making the electronic device.

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate.

Multi-function and shielded 3d interconnects

A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element.

Integrated circuit packaging system with active surface heat removal and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.

Microsprings Partially Embedded In A Laminate Structure And Methods For Producing Same

At least one microspring has applied thereover a laminate structure to provide: mechanical protection during handling and wafer processing, a spring spacer layer, strengthening of the anchor between spring and substrate, provision of a gap stop during spring deflection, and moisture and contaminant protection. A fully-formed laminate structure may be applied over the microspring structure or a partly-formed laminate structure may be applied over the microspring structure then cured or hardened. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may remain in place in the final microspring structure or be removed in whole or in part. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structure, forming for example additional structural elements such as a gap stop for the microspring.

Semiconductor device having semiconductor member and mounting member

A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased.

Multilayer printed wiring board and method for manufacturing multilayer printed wiring board

A method for manufacturing a multilayer printed wiring board includes preparing a first resin insulative material having a first conductive circuit on or in the first resin insulative material, forming a second resin insulative material on the first resin insulative material and the first conductive circuit, forming on a surface of the second resin insulative material a first concave portion to be filled with a conductive material for formation of a second conductive circuit, forming on the surface of the second resin insulative material a pattern having a second concave portion and post portions to be filled with the conductive material for formation of a plane conductor, and filling the conductive material in the first concave portion and the second concave portion such that the second conductive circuit and the plane conductor are formed.

Interposer including air gap structure, methods of forming the same, semiconductor device including the interposer, and multi-chip package including the interposer

Example embodiments of the present invention relate to an interposer of a semiconductor device having an air gap structure, a semiconductor device using the interposer, a multi-chip package using the interposer and methods of forming the interposer. The interposer includes a semiconductor substrate including a void, a metal interconnect, provided within the void, thereby forming an air gap insulating the metal interconnect. The metal interconnect may be connected to a contact element, and may be maintained within the air gap using the contact element.

Circuit Board Packaged with Die through Surface Mount Technology

A package of a circuit board and a die are packed through surface mount technology (SMT). The shortest circuit is formed with at a low cost. Thus, the package can work in high speed and high frequency applications.

Methods of fabricating package stack structure and method of mounting package stack structure on system board

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

Chip Capacitor Precursors

A capacitive precursor includes electrically conductive material layers stacked on a substrate. The electrically conductive layers provide first and second patterns. The patterns each include overlaying areas free of the electrically conductive material. The first pair of areas overlay areas of the second pattern having the electrically conductive material and the second pair of areas overlay areas of the first pattern having the electrically conductive material. Dielectric layers are interposed between neighboring electrically conductive material layers for electrical isolation. One or more capacitive precursors can be dropped onto or into a board and during assembly of a packaged semiconductor device and have electrically conducting layers associated with its respective plates connected together to form a capacitor during assembly using conventional assembly steps.

Integrated circuit packaging system with interposer interconnections and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure; mounting a first-external-package-component to the routing structure; and forming a first-external-package-encapsulation covering the first-external-package-component.

Package with embedded chip and method of fabricating the same

A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified.

Semiconductor assembly and semiconductor package including a solder channel

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Package systems and manufacturing methods thereof

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

Pass-through 3d interconnect for microelectronic dies and associated systems and methods

Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.

Through wiring substrate and manufacturing method thereof

A through wiring substrate includes a substrate having a first face and a second face; and a through-wire formed by filling, or forming a film of, an electrically-conductive substance into a through-hole, which penetrates between the first face and the second face. The through-hole has a bend part comprising an inner peripheral part that is curved in a recessed shape and an outer peripheral part that is curved in a protruding shape, in a longitudinal cross-section of the through-hole, and at least the inner peripheral part is formed in a circular arc shape in the longitudinal cross-section.

Miniature surface mount device with large pin pads

One embodiment of the surface mount LED package includes a lead frame and a plastic casing at least partially encasing the lead frame. The lead frame includes a plurality of electrically conductive chip carriers. There is an LED disposed on each one of the plurality of electrically conductive chip carriers. A profile height of the surface mount LED package is less than about 1.0 mm.

Wiring Substrate, Imaging Device and Imaging Device Module

A imaging device includes a first insulating substrate having a through hole, a connection electrode and a first wiring conductor, a second insulating substrate having outside terminals and a second wiring conductor, and an imaging element including a light-receiving portion arranged at a center portion on an upper surface thereof and a connection terminal arranged at an outer peripheral portion thereof, at least one of the lower surface of the first insulating substrate and the upper surface of the second insulating substrate including a recess portion, the through hole being located on an inner side thereof, the imaging element being arranged below the first insulating substrate such that the light-receiving portion is located within the through hole, the connection terminal being electrically connected to the connection electrode, the imaging element being accommodated inside the recess portion, outer peripheral portions of the first insulating substrate and the second insulating substrate being electrically connected to each other.

Semiconductor package module

There is provided a semiconductor package module capable of minimizing a thickness of the module in spite of including an electronic element having a large size. The semiconductor package module includes: a semiconductor package having a shield formed on an outer surface and a side thereof and at least one receiving part provided in a lower surface thereof, the receiving part having a groove shape; and a main substrate having at least one large element and the semiconductor package mounted on one surface thereof, wherein the large element is received in the receiving part of the semiconductor package and is mounted on the main substrate.

Thermal Power Plane for Integrated Circuits

A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Method for Producing an Electrical Circuit and Electrical Circuit

A method for producing an electrical circuit includes providing a main printed circuit board having a plurality of metalized plated-through holes through the main printed circuit board along at least one separating line between adjacent printed circuit board regions of the main printed circuit board. Each printed circuit board region has electrical contact connection pads on at least the main surface of the printed circuit board region that is to be populated, electrical lines for connection between the plurality of plated-through holes and the contact connection pads, and at least one semiconductor chip electrically contact-connected by means of the contact connection pads. The main printed circuit board is covered with a potting compound across the printed circuit board regions with the semiconductor chips.

Method of manufacturing circuit board

Disclosed herein is a method of manufacturing a circuit board. The method of manufacturing a circuit board according to a preferred embodiment of the present invention is configured to include (A) forming a cavity 115 for a bump on one surface 111 of a carrier 110, (B) forming a bump 130 in the cavity 115 for the bump through an electroplating process, (C) laminating an insulating layer 140 on one surface 111 of the carrier 110 so as to apply the bump 130, (D) forming a circuit layer 150 including a via 155 connected with the bump 130 on the insulating layer 140, and (E) removing the carrier 110, whereby the process of forming separate solder balls is removed by forming the cavities 111 for the bumps in the carriers 110 to form the bumps, thereby simplifying the process of manufacturing a circuit board and reducing the lead time.

Printed circuit board and method for manufacturing the same

Disclosed herein are a printed circuit board and a method for manufacturing the same. The method for manufacturing a printed circuit board includes: (a) forming at least one plate through hole penetrating through an insulating layer; (b) forming pattern grooves for implementing inner layer circuits on both surfaces of the insulating layer; and (c) filling the plate through hole and the pattern grooves with a conductive material. The method for manufacturing a printed circuit board may provide the printed circuit board having excellent heat radiating characteristics and reduce process cost.

Semiconductor Device And Method Of Manufacturing Semiconductor Device

A semiconductor chip includes a magnetic storage device and includes an electrode pad on a first face. The semiconductor chip is coated with a magnetic shield layer in a state in which at least the electrode pad is exposed. The semiconductor chip is mounted on an interconnect substrate through a bump. At least one of the semiconductor chip and the interconnect substrate includes a convex portion, and the bump is disposed over the convex portion.

Microelectronic devices and methods for manufacturing microelectronic devices

Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. One such method includes forming a plurality of apertures in a substrate with the apertures arranged in an array, and, after forming the apertures, attaching the substrate to a lead frame having a plurality of pads with the apertures in the substrate aligned with corresponding pads in the lead frame. Another method includes providing a partially cured substrate, coupling the partially cured substrate to a plurality of leads, attaching a microelectronic die to the leads, and electrically connecting the microelectronic die to the leads.

Integrated circuit packaging system with connection structure and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.

Semiconductor package and semiconductor system including the same

Provided are a semiconductor package and a semiconductor system including the semiconductor package. The semiconductor package includes a semiconductor device and an interconnect structure electrically connected to the semiconductor device and delivering a signal from the semiconductor device, wherein the interconnect structure includes an anodized insulation region and an interconnect adjacent to and defined by the anodized insulation region.

Connecting and Bonding Adjacent Layers with Nanostructures

An apparatus, comprising two conductive surfaces or layers and a nanostructure assembly bonded to the two conductive surfaces or layers to create electrical or thermal connections between the two conductive surfaces or layers, and a method of making same.

Laser processing method

A laser processing method of converging a laser light into an object to be processed made of glass so as to form a modified region and etching the object along the modified region so as to form a through hole in the object comprises a browning step of discoloring at least a part of the object by browning; a laser light converging step of forming the modified region in the discolored part of the object by converging the laser light into the object after the browning step; and an etching step of etching the object after the laser light converging step so as to advance the etching selectively along the modified region and form the through hole.

Laminated wiring board

In a multilayer wiring board 1, a low resistance silicon substrate 2 having a predetermined resistivity and a high resistance silicon substrate 4 having a resistivity higher than the predetermined resistivity are stacked while interposing an insulating layer 3 therebetween. The low resistance silicon substrate 2 is provided with an electric passage part 6 surrounded by a ring-shaped groove 5, while a wiring film 13 electrically connected to the electric passage part 6 through an opening 8 of the insulating layer 3 is disposed on a rear face 4 b of the high resistance silicon substrate 4 and an inner face 11 a of a recess 11. Since the high resistance silicon substrate 4 is thus provided with the wiring film 13, an optical semiconductor element 20 and an electronic circuit element 30 which differ from each other in terms of the number and positions of electrode pads can be electrically connected to each other on the front and rear face sides of the multilayer wiring board 1.

Semiconductor Device and Method of Forming an Inductor Within Interconnect Layer Vertically Separated from Semiconductor Die

A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer.

Semiconductor device and substrate

A semiconductor device of the invention include a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element comprises, a plurality of first electrodes formed along a first edge of a surface thereof, a plurality of second electrodes formed along an edge opposite to the first edge of the surface, a plurality of third electrodes formed in the neighborhood of a functional block, and an internal wiring for connecting the first electrodes and the third electrodes. The substrate comprises, a first wiring pattern for connecting the external input terminal and the first electrodes, a second wiring pattern for connecting the external output terminal and the second electrodes, and a third wiring pattern for connecting the first electrodes and the third electrodes.

Packaged semiconductor chips with array

A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

Lead pin for package substrate and semiconductor package printed circuit board including the same

Disclosed herein is a lead pin for a package substrate including a connection pin, and a head part including a flange part formed at one end of the connection pin and having one surface bonded to the connection pin and a flat part formed at the other surface of the flange part and having at least one groove formed along an outer circumference thereof. According to the present invention, the grooves are formed along the outer circumference of the flat part of the head part of the lead pin to increase a bonding area, thereby making it possible to increase bonding strength of the lead pin.

Reduced pth pad for enabling core routing and substrate layer count reduction

Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.

Microelectronic package and method of manufacturing same

A microelectronic package includes a substrate ( 110, 210 ), an interposer ( 120, 220 ) having a first surface ( 121 ) and an opposing second surface ( 122 ), a microelectronic die ( 130, 230 ) attached to the substrate, and a mold compound ( 140 ) over the substrate. The interposer is electrically connected to the substrate using a wirebond ( 150 ). The first surface of the interposer is physically connected to the substrate with an adhesive ( 160 ), and the second surface has an electrically conductive contact ( 126 ) formed therein. The mold compound completely encapsulates the wirebond and partially encapsulates the interposer such that the electrically conductive contact in the second surface of the interposer remains uncovered by the mold compound.

Integrated millimeter wave transceiver

A millimeter wave transceiver including a plate forming an interposer having its upper surface supporting an interconnection network and having its lower surface intended to be assembled on a printed circuit board by bumps; an integrated circuit chip assembled on the upper surface of the interposer; antennas made of tracks formed on the upper surface of the interposer; and reflectors on the upper surface of the printed circuit board in front of each of the antennas, the effective distance between each antenna and the reflector plate being on the order of one quarter of the wavelength, taking into account the dielectric constants of the interposed materials.

Flexible circuit board and manufacturing method thereof

The present invention provides a high-performance flexible circuit board having excellent flexibility, a fine wiring pattern, and fine electric contacts, and a manufacturing method thereof. In a flexible circuit board ( 20 ), a second insulating layer ( 24 ) made of an inorganic material is positioned between a wiring layer ( 25 ) and a first insulating layer ( 23 ) made of an inorganic material.

Semiconductor chip assembly and method for making same

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution Layer

A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die.

Composition for filling through silicon via (tsv), tsv filling method and substrate including tsv plug formed of the composition

Provided is a composition for filling a Through Silicon Via (TSV) including: a metal powder; a solder powder; a curable resin; a reducing agent; and a curing agent. A TSV filling method using the composition and a substrate including a TSV plug formed of the composition are also provided.

Semiconductor package and method of fabricating the same

A semiconductor package and a method of manufacturing the same, and more particularly, to a package of a power module semiconductor and a method of manufacturing the same. The semiconductor package includes a substrate including a plurality of conductive patterns spaced apart from one another; a plurality of semiconductor chips disposed on the conductive patterns; a connecting member for electrically connecting the conductive patterns to each other, for electrically connecting the semiconductor chips to each other, or for electrically connecting the conductive pattern and the semiconductor chip; and a sealing member for covering the substrate, the semiconductor chips, and the connecting member, wherein a lower surface of the substrate and an upper surface of the connecting member are exposed to the outside by the sealing member.

Low cost thermally enhanced hybrid bga and method of manufacturing the same

A semiconductor package is formed having a substrate juxtaposed on at least two sides of a semiconductor die. Both the substrate and the semiconductor die are affixed to a conductive layer that draws heat generated during use of the semiconductor package away from the semiconductor die and the substrate. There are also electrical contacts affixed to the substrate and the semiconductor die. The electrical contacts facilitate electrical connection between the semiconductor die, the substrate, and any external devices or components making use of the semiconductor die. The substrate, semiconductor die, and at least a portion of some of the electrical contacts are enclosed by an encapsulating layer insulating the components. Portions of the electrical contacts not enclosed by the encapsulating layer are affixed to an outside device, such as a printed circuit board.

Semiconductor package and method of manufacturing the same

Provided are a semiconductor package and a method of manufacturing the same. a substrate including a first face and a second face, wherein the first and second faces face each other; a first ground pattern disposed on the first face; a second ground pattern disposed on the second face; a plurality of ground via plugs which connect the first ground pattern and the second ground pattern, wherein the plurality of ground via plugs penetrate the substrate; and a first aluminum oxide film interposed between the plurality of ground via plugs, wherein a ground voltage is applied to the plurality of ground via plugs. The semiconductor package may be manufactured using an anodic oxidation process.

Method And System For A Photonic Interposer

Methods and systems for a photonic interposer are disclosed and may include receiving one or more continuous wave (CW) optical signals in a silicon photonic interposer from an external optical source, either from an optical source assembly or from optical fibers coupled to the silicon photonic interposer. The received CW optical signals may be processed based on electrical signals received from the electronics die. The modulated optical signals may be received in the silicon photonic interposer from optical fibers coupled to the silicon photonic interposer. Electrical signals may be generated in the silicon photonic interposer based on the received modulated optical signals, and may then be communicated to the electronics die via copper pillars. Optical signals may be communicated into and/or out of the silicon photonic interposer utilizing grating couplers. The electronics die may comprise one or more of: a processor core, a switch core, or router.

Packaging substrate with conductive structure

A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices

A method is for making an electronic device and includes forming an interconnect layer stack on a sacrificial substrate and having a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers. The method also includes laminating and electrically joining through an intermetallic bond a liquid crystal polymer (LCP) substrate to the interconnect layer stack on a side thereof opposite the sacrificial substrate. The method further includes removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at least one first device to the lowermost patterned electrical conductor layer.

Surface coating method, semiconductor device, and circuit board package

To provide a surface coating method, which contains applying a surface coating material to a layered structure so as to cover at least a surface of an insulating film of the layered structure, to form a coating on the surface of the insulating film, wherein the surface coating material contains a water-soluble resin, an organic solvent, and water, and wherein the layered structure contains the insulating film exposed to an outer surface, and a patterned metal wiring exposed to an outer surface.

Interposer

An interposer includes a substrate having a first surface and a second surface with vias extending between the first and second surfaces. The interposer also includes a contact array mounted to the first surface that has a plurality of coil-shaped contacts. The contacts have heels terminated to corresponding vias. The contacts have beams defining a mating interface of the interposer configured for mating with an electronic component. The contacts may be conic helix shaped. The beams may include at least one turn. The beams may be free standing from the heel and may be compressible along contact axes toward the first surface of the substrate.

Carrier tape for tab-package and manufacturing method thereof

The present invention relates to a method for manufacturing a TAB tap. The method includes forming a circuit pattern region having input/output terminal pattern on a base film, and forming an exposing region at a convey region having a sprocket hole for exposing the base film. Accordingly, the present invention provides a TAB tape that improves reliability of a product by fundamentally preventing the generation of metal particles by forming exposing regions that expose a base film through selectively etching and removing a metal layer of a convey region formed at both side of a TAB tape and having a sprocket hole, and that prevents short-circuit by partially removing a base film at a predetermined region not having a circuit pattern formed thereon through etching.

Semiconductor chip module, semiconductor package having the same and package module

A semiconductor module comprising a plurality of semiconductor chips where at least one semiconductor chip is laterally offset with respect to a second semiconductor chip, and substantially aligned with a third semiconductor chip such that an electrical connection can be made between an electrical contact in the first semiconductor chip and an electrical contact in the third semiconductor chip.

Packaged semiconductor device for high performance memory and logic

A packaged semiconductor device is disclosed. The device comprises a substrate having multiple layers between first and second oppositely disposed faces, and a cavity with an opening at the first face to nest at least one integrated circuit memory device. Logic circuitry is disposed on the second face and includes contacts for electrically coupling to the stacked integrated circuit memory devices. The logic circuitry is coupled to electrical contacts formed on the first face through first electrical paths formed in the multiple layers of the substrate, the first electrical paths including conductive traces and vias.

Manufacturing method of semiconductor device, semiconductor device and mobile communication device

A manufacturing method of a semiconductor device includes: sealing a semiconductor chip with a sealing resin containing a filler; exposing a part of the filler; etching at least a part of the exposed filler; and forming a metal film at least at a part of a surface of the sealing resin including inner surfaces of holes formed at the surface of the sealing resin by the etching.

Integrated structures of high performance active devices and passive devices

Integrated structures having high performance CMOS active devices mounted on passive devices are provided. The structure includes an integrated passive device chip having a plurality of through wafer vias, mounted to a ground plane. The structure further includes at least one CMOS device mounted on the integrated passive device chip using flip chip technology and being grounded to the ground plane through the through wafer vias of the integrated passive device chip.

Heatsink for led array light

A heatsink that includes a plurality of thermally conductive plates coupled to each other in a stacked configuration. Each plate includes a core section and a plurality of protrusions extending radially outwardly from the core section in a direction substantially parallel to the core section. The core section of each plate is in direct contact with the core section of an adjacent plate.

Compliant spring interposer for wafer level three dimensional (3d) integration and method of manufacturing

The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.

Semiconductor Package with Embedded Die

A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.

Device mounting board and method of manufacturing the same, semiconductor module, and mobile device

A device mounting board includes: an insulating resin layer; a wiring layer formed on one of the principal surfaces of the insulating resin layer; a protection layer covering the insulating resin layer and the wiring layer; a protruding electrode electrically connected to the wiring layer, the protruding electrode protruding from the wiring layer toward the insulating resin layer and penetrating through the insulating resin layer; a wiring-layer-side convex portion protruding from the wiring layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer; and a resin-layer-side convex portion protruding from the protection layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer.

Electroconductive bonding material, method for bonding conductor, and method for manufacturing semiconductor device

An electro-conductive bonding material includes: metal components of a high-melting-point metal particle that have a first melting point or higher; a middle-melting-point metal particle that has a second melting point which is first temperature or higher, and second temperature or lower, the second temperature is lower than the first melting point and higher than the first temperature; and a low-melting-point metal particle that has a third melting point or lower, the third melting point is lower than the first temperature.

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Semiconductor device and noise suppressing method

A first semiconductor chip ( 200 ) is mounted on a second semiconductor chip ( 100 ). The first semiconductor chip ( 200 ) has a first conductor pattern ( 222 ). The second semiconductor chip ( 100 ) has a second conductor pattern ( 122 ). The second conductor pattern ( 122 ) is formed at a region overlapping the first conductor pattern ( 222 ) in a plan view. At least one element selected from a group consisting of the first conductor pattern ( 222 ) and the second conductor pattern ( 122 ) has a repetitive structure.

Semiconductor apparatus, method for manufacturing the same and electric device

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Package 3D Interconnection and Method of Making Same

A method of manufacturing an integrated circuit (IC) package is provided. The method includes stacking an interposer substrate and a device structure, the interposer substrate having a first plurality of contact members formed on a first surface of the interposer substrate and the device structure having a second plurality of contact members that are exposed at a surface of the device structure, and laminating the interposer substrate and the device structure such that the first plurality of contact members are physically and electrically coupled to the second plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the second plurality of contact members.

Method for Attaching Wide Bus Memory and Serial Memory to a Processor within a Chip Scale Package Footprint

A method for forming a semiconductor device includes physically attaching a first semiconductor die to front surface of a first substrate. The first die is electrically connected to routings on front surface of the first substrate. The routings are electrically connected with conductive pads on back surface of the first substrate. A second semiconductor die is physically attached to front surface of a second substrate. The die is electrically connected to routings on front surface of second substrate. These routings are electrically connected with conductive pads on front surface of the second substrate. A third semiconductor die is physically attached to the second die. The third die is electrically attached to the second die through a plurality of through substrate vias (TSVs) within the second die. The conductive pads on back surface of first substrate are electrically connected to the conductive pads on front surface of second substrate.

Chip-last embedded interconnect structures and methods of making the same

The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.

Wiring substrate and method of manufacturing the same

A wiring substrate includes a structure in which a plurality of wiring layers are stacked through insulating layers intervening therebetween, and which has a first surface side and a second surface side, the first surface side where a semiconductor element is to be mounted, the second surface side being located at an opposite side to the first surface side, an interposer buried in an outermost one of the insulating layers located at the first surface side, and electrically connected to the semiconductor element to be mounted, and a sheet-shaped member buried in an outermost one of the insulating layers located at the second surface side, wherein, the interposer and the sheet-shaped member are disposed at symmetrical positions symmetrical each other.

Signal routing Optimized IC package ball/pad layout

This invention provides layout schemes for ball/pad regions on a printed circuit board for a small regular ball/pad region grid that provides additional space between ball/pad regions for increased wiring capability. The layout scheme is consistent with printed circuit board manufacturing requirements and minimum wiring channel requirements demanded by high density integrated circuit chips.

System and method for improving frequency response

An electrical system and method for making the same includes a main circuit board and a plurality of contact pads located on a surface of the main circuit board. The contact pads are electrically conductive. Additionally, an integrated circuit package having at least one electrical device is attached to the surface of the main circuit board. A ball grid array made from a plurality of solder balls is located on a bottom side of the integrated circuit package. The ball grid array has a plurality of solder balls being electrically conductive and in electrical communication with the at least one electrical device. The solder balls further include solder balls of different material properties.

Multilayer resin sheet and method for producing the same, method for producing cured multilayer resin sheet, and highly thermally conductive resin sheet laminate and method for producing the same

A multilayer resin sheet is constituted by including a resin layer containing an epoxy resin having a mesogenic skeleton, a curing agent and an inorganic filler, and an insulating adhesive layer formed on at least either of the surfaces of the resin layer. A cured multilayer resin sheet originated from the multilayer resin sheet has high thermal conductivity, good insulation and adhesive strength, and, further, superior thermal shock resistance, and is suitable as an electric insulating material to be used for an electric or electronic device.

Coreless layer laminated chip carrier having system in package structure

A substrate for use in a laminated chip carrier (LCC) and a system in package (SiP) device having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can include thermoset and thermoplastic resin.

Electromagnetic interference shielding structure for integrated circuit substrate and method for fabricating the same

An electromagnetic interference (EMI) shielding structure for integrated circuit (IC) substrate includes a plurality of conductive contacts, a covering layer, and a sputtered layer. The conductive contacts are formed at the perimeter of a chip area on the IC substrate. The covering layer is formed on the conductive contacts and covers the chip area. A groove is formed on the covering layer for exposing the conductive contacts. The sputtered layer is formed on the covering layer and connected to the conductive contacts. The EMI shielding structure can restrain the interference in the chip area.

Packaging substrate and method of fabricating the same

A packaging substrate includes a core board having a first surface and an opposite second surface; at least a conic through hole formed in the core board and penetrating the first and second surfaces; a plurality of conductive paths formed on a wall of the conic through hole, free from being electrically connected to one another in the conic through hole; and a plurality of first circuits and second circuits disposed on the first and second surfaces of the core board, respectively, and being in contact with peripheries of two ends of the conic through hole, wherein each of the first circuits is electrically connected through each of the conductive paths to each of the second circuits. Compared to the prior art, the packaging substrate has a reduced number of through holes or vias and an increased overall layout density.

Semiconductor device

A semiconductor device includes a first semiconductor chip provided with a first semiconductor element including a plurality of element electrodes; and a first substrate having an element mounting surface on which the first semiconductor chip is mounted. The first substrate includes a plurality of first electrodes, each formed on the element mounting surface; a plurality of first interconnects connected to the first electrodes; a plurality of second electrodes formed on a surface opposite to the element mounting surface; a plurality of second interconnects connected to the second electrodes; a plurality of through-hole interconnects penetrating the first substrate and connecting the first interconnects to the second interconnects; and a third semiconductor element. The first side of the first substrate is shorter than the first side of the first semiconductor chip.

Through-silicon vias for semicondcutor substrate and method of manufacture

A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.

Wiring Board, Semiconductor Device, and Method for Manufacturing Wiring Board

A wiring board provided with a silicon substrate including a through hole that communicates a first surface and a second surface of the silicon substrate. A capacitor is formed on an insulating film, which is applied to the silicon substrate, on the first surface and a wall surface defining the through hole. A capacitor part of the capacitor includes a first electrode, a dielectric layer, and a second electrode that are sequentially deposited on the insulating film on the first surface and the wall surface of the through hole. A penetration electrode is formed in the through hole covered by the first electrode, the dielectric layer, and the second electrode of the capacitor part.

Test structure and methodology for three-dimensional semiconductor structures

A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.