Die stacking techniques in bga memory package for small footprint cpu and memory motherboard design

Circuit assemblies with multiple interposer substrates, and methods of fabrication

A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.

ULTRA HIGH PERFORMANCE INTERPOSER

An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via. 1. A microelectronic interconnection component , comprising:a semiconductor material layer including a first surface and a second surface that is substantially parallel to the first surface and is spaced apart therefrom in a first direction, the semiconductor material layer having a bulk dielectric constant;at least two metalized vias each extending through the semiconductor material layer and having a first end at the first surface and a second end at the second surface, a first pair of the at least two metalized vias being spaced apart from each other at a distance in a second direction orthogonal to the first direction; andan insulating via in the semiconductor layer extending from the first surface toward the second surface and defining an interior volume, the insulating via being positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias; andwherein a dielectric constant of the interior volume is less than the bulk dielectric constant.2. The microelectronic ...

Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates

In a microelectronic component having conductive vias ( 114 ) passing through a substrate ( 104 ) and protruding above the substrate, conductive features ( 120 E.A, 120 E.B) are provided above the substrate that wrap around the conductive vias' protrusions ( 114 ′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

Method for reduced load memory module

A method for reducing load in a memory module. In such a method, a plurality of memory chips are coupled to a circuit platform. Each memory chip of the plurality of memory chips each has a plurality of memory dies. At least one controller is coupled to the circuit platform and further coupled to the plurality of memory chips for communication with the plurality of memory dies thereof. The at least one controller is for receiving chip select signals to provide a plurality of rank select signals in excess of the chip select signals. The plurality of memory dies are coupled with wire bonds within the plurality of memory chips for a reduced load for coupling the circuit platform for communicating via a memory channel. The load is sufficiently reduced for having at least two instances of the memory module share the memory channel.

Contact arrangements for stackable microelectronic package structures with multiple ranks

An apparatus relates generally to a microelectronic assembly. In this apparatus, a first substrate and a second substrate each have opposing surfaces. Contact arrangements are disposed on a surface of the first substrate, including: first contacts disposed as a ring to provide a first array of the contact arrangements on such surface; and second contacts disposed interior to the ring of the first contacts to provide a second array of the contact arrangements on the first surface. The first contacts and the second contacts are for interconnection with first microelectronic dies and second microelectronic dies. The second microelectronic dies are disposed below the first microelectronic dies in same a package as the first microelectronic dies. The first microelectronic dies and the second microelectronic dies include at least two ranks thereof for commonly sharing the first contacts and the second contacts among the first microelectronic dies and the second microelectronic dies.

High-bandwidth memory application with controlled impedance loading

A microelectronic assembly can include an address bus comprising a plurality of signal conductors each passing sequentially through first, second, third, and fourth connection regions, and first and second microelectronic packages. The first microelectronic package can include first and second microelectronic elements, and the second microelectronic package can include third and fourth microelectronic elements. Each microelectronic element can be electrically coupled to the address bus via the respective connection region. An electrical characteristic between the first and second connection regions can be within a same tolerance of the electrical characteristic between the second and third connection regions.

Via structure for signal equalization

An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has a first surface and a second surface opposite the first surface. The first surface and the second surface define a thickness of the substrate. A via structure extends from the first surface of the substrate to the second surface of the substrate. The via structure has a first terminal at or proximate to the first surface and a second terminal at or proximate to the second surface provided by a conductive member of the via structure extending from the first terminal to the second terminal. A barrier layer of the via structure is disposed between at least a portion of the conductive member and the substrate. The barrier layer has a conductivity configured to offset a capacitance between the conductive member and the substrate when a signal is passed through the conductive member of the via structure.

Ultra high performance interposer

An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.

Wire bond wires for interference shielding

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates

In a microelectronic component having conductive vias ( 114 ) passing through a substrate ( 104 ) and protruding above the substrate, conductive features ( 120 E.A, 120 E.B) are provided above the substrate that wrap around the conductive vias' protrusions ( 114 ′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

WIRE BOND WIRES FOR INTERFERENCE SHIELDING

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

HIGH-BANDWIDTH MEMORY APPLICATION WITH CONTROLLED IMPEDANCE LOADING

A microelectronic assembly can include an address bus comprising a plurality of signal conductors each passing sequentially through first, second, third, and fourth connection regions, and first and second microelectronic packages. The first microelectronic package can include first and second microelectronic elements, and the second microelectronic package can include third and fourth microelectronic elements. Each microelectronic element can be electrically coupled to the address bus via the respective connection region. An electrical characteristic between the first and second connection regions can be within a same tolerance of the electrical characteristic between the second and third connection regions.

Single package dual channel memory with co-support

A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements.

CIRCUIT ASSEMBLIES WITH MULTIPLE INTERPOSER SUBSTRATES, AND METHODS OF FABRICATION

Single package dual channel memory with co-support

VIA STRUCTURE FOR SIGNAL EQUALIZATION

An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has a first surface and a second surface opposite the first surface. The first surface and the second surface define a thickness of the substrate. A via structure extends from the first surface of the substrate to the second surface of the substrate. The via structure has a first terminal at or proximate to the first surface and a second terminal at or proximate to the second surface provided by a conductive member of the via structure extending from the first terminal to the second terminal. A barrier layer of the via structure is disposed between at least a portion of the conductive member and the substrate. The barrier layer has a conductivity configured to offset a capacitance between the conductive member and the substrate when a signal is passed through the conductive member of the via structure.

SINGLE PACKAGE DUAL CHANNEL MEMORY WITH CO-SUPPORT

A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements. 1. A microelectronic package , comprising:a support element having first and second oppositely-facing surfaces and a plurality of substrate contacts at the first surface or the second surface, the support element having oppositely-facing north and south edges adjacent to oppositely-facing east and west edges each extending between the north and south edges, the second surface having a southwest region encompassing entire lengths of the south and west edges and extending in orthogonal directions from each of the south and west edges one-third of each distance toward the north edge and toward the east edge, respectively;zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, each microelectronic element having a memory storage array and first and second columns of element contacts extending along a front face thereof adjacent and parallel to first and second opposite edges of the front face, respectively, the first and second ...

MICROELECTRONIC COMPONENTS WITH FEATURES WRAPPING AROUND PROTRUSIONS OF CONDUCTIVE VIAS PROTRUDING FROM THROUGH-HOLES PASSING THROUGH SUBSTRATES

In a microelectronic component having conductive vias () passing through a substrate () and protruding above the substrate, conductive features (E.A, E.B) are provided above the substrate that wrap around the conductive vias' protrusions (′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided. 1. A microelectronic component comprising:a substrate comprising one or more first through-holes;one or more conductive vias, each conductive via comprising a portion inside a corresponding first through-hole, and comprising a conductive protrusion protruding from the corresponding first through-hole for attachment to one or more contact pads of one or more other components;for each conductive protrusion:a first dielectric region wrapping around the conductive protrusion and covering the corresponding first through-hole adjacent to the conductive protrusion; anda first conductive sleeve region wrapping around the conductive protrusion, the first conductive sleeve region being separated from the corresponding first through-hole and the conductive protrusion by the corresponding first dielectric region.2. The microelectronic component of further comprising said one or more other components comprising said one or more contact pads attached to the one or more conductive protrusions.3. The microelectronic component of wherein said one or more other components comprise a printed circuit board.4. The microelectronic component of wherein each said conductive protrusion is on a first side of the substrate claim 1 , and the substrate comprises a second side opposite to the first side;wherein the microelectronic component further comprises one or more integrated circuits attached to the second side of the substrate.5. The microelectronic component of wherein at least one said conductive protrusion is for carrying a signal other than power and other than ground.6. The microelectronic component of further comprising ...

Compact microelectronic assembly having reduced spacing between controller and memory packages

A microelectronic package has terminals at a surface of a substrate having first and second half areas, each half area extending from a diagonal that bisects the first surface and a respective opposite corner of the first surface. Terminals for carrying data and address information in the first half area provide first memory channel access to a first memory storage array, and terminals for carrying data and address information in the second half area provide second memory channel access to a second memory storage array. The package may include first and second microelectronic elements overlying a same surface of the substrate which may be stacked in transverse orientations.

CIRCUIT ASSEMBLIES WITH MULTIPLE INTERPOSER SUBSTRATES, AND METHODS OF FABRICATION

A combined interposer () includes multiple constituent interposers (), each with its own substrate (S) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (R.B). The constituent interposer substrates (S) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided. 1. A circuit assembly comprising:a combined interposer comprising a plurality of constituent interposers, each constituent interposer comprising a substrate, the substrates being laterally spaced from each other;wherein the combined interposer comprises a first circuit layer comprising circuitry and physically contacting a top surface of two or more of the substrates, the circuitry comprising a circuit extending over at least two of said two or more of the substrates;wherein for each of two or more of the constituent interposers, the constituent interposer comprises a first constituent circuit layer which is part of the first circuit layer, the first constituent circuit layer being present on a top surface of the constituent interposer's substrate, the first constituent circuit layer comprising circuitry;wherein the first circuit layer comprises first contact pads on top;wherein the circuit assembly further comprises one or more circuit modules at least one of which comprises an integrated circuit, the one or more circuit modules overlying the first circuit layers, each circuit module comprising one or more contact pads attached to one or more first contact pads.2. The circuit assembly of wherein at least a portion of at least one first contact pad overlies a gap ...

Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces

In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.

Via structure for signal equalization

Wire bond wires for interference shielding

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Single package dual channel memory with co-support

MICROELECTRONIC COMPONENTS WITH FEATURES WRAPPING AROUND PROTRUSIONS OF CONDUCTIVE VIAS PROTRUDING FROM THROUGH-HOLES PASSING THROUGH SUBSTRATES

In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, one or more conductive features (120E.A, 120E.B, or both) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

Wire bond wires for interference shielding

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Planar inductor devices

A planar inductor device includes a ferrite body and a conductive pathway, The ferrite body extends around an opening in the ferrite body. The conductive pathway includes an input section, a current-splitting section, a coil section, a current-combining section, and an output section connected with each other, the input section extending toward the opening in the ferrite body. The current-splitting section includes a plurality of conductive coils joined with the conductive pathway and electrically disposed parallel to each other. The coil section includes the conductive coils helically wrapped around the ferrite body. The current-combining section includes the conductive coils joined with each other. The output section includes the joined conductive coils extending out of the ferrite body.

DUAL-CHANNEL DIMM

A dual inline memory module can include a module card having first and second opposed surfaces and a plurality of microelectronic elements each having a surface facing a surface of the module card. The module card can have a plurality of parallel edge contacts, the edge contacts including first and second contacts, the first and second contacts configured to carry command and address information and data signals corresponding to first and second memory channels, respectively, the first memory channel being independent from the second memory channel. Each microelectronic element can have memory storage array function being of type LPDDRx and being configured to sample the command and address information at least twice per clock cycle. The plurality of microelectronic elements can be configured to implement the first and second memory channels. The first and second microelectronic elements can be configured for communication via the first and second contacts, respectively. 1. A dual inline memory module (“DIMM”) , comprising:a module card having first and second opposed surfaces, and a plurality of parallel edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of a socket when the module is inserted in the socket, the edge contacts including first contacts and second contacts, the first contacts configured to carry command and address information and data signals corresponding to a first memory channel, and the second contacts configured to carry command and address information and data signals corresponding to a second memory channel independent from the first memory channel; anda plurality of microelectronic elements each having a surface facing a surface of the first and second surfaces of the module card, each microelectronic element having memory storage array function being of type LPDDRx and being configured to sample the command and address information at least twice per clock cycle, the ...

Ultra high performance interposer

An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.

Enhanced density assembly having microelectronic packages mounted at substantial angle to board

A microelectronic assembly includes a plurality of stacked microelectronic packages, each comprising a dielectric element having a major surface, an interconnect region adjacent an interconnect edge surface which extends away from the major surface, and plurality of package contacts at the interconnect region. A microelectronic element has a front surface with chip contacts thereon coupled to the package contacts, the front surface overlying and parallel to the major surface. The microelectronic packages are stacked with planes defined by the dielectric elements substantially parallel to one another, and the package contacts electrically coupled with panel contacts at a mounting surface of a circuit panel via an electrically conductive material, the planes defined by the dielectric elements being oriented at a substantial angle to the mounting surface.

Package on-package devices with upper RDL of WLPS and methods therefor

Package-on-package (“PoP”) devices with upper RDLs of WLP (“WLP”) components and methods therefor are disclosed. In a PoP device, a first IC die is surface mount coupled to an upper surface of the package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with reference to the first IC. A molding layer is formed over the upper surface of the package substrate. A first and a second WLP microelectronic component is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. Each of the first and the second WLP microelectronic components have a second IC die located below a first RDL respectively thereof. A third and a fourth IC die are respectively surface mount coupled over the first and the second WLP microelectronic components.

ULTRA HIGH PERFORMANCE INTERPOSER

An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.

REDUCED LOAD MEMORY MODULE

An apparatus relates generally to a reduced load memory module. In such an apparatus, there is a circuit platform with a plurality of memory chips coupled to the circuit platform. Each memory chip of the plurality of memory chips each has a plurality of memory dies. At least one controller is coupled to the circuit platform and further coupled to the plurality of memory chips for communication with the plurality of memory dies thereof. The at least one controller is for receiving chip select signals to provide a plurality of rank select signals in excess of the chip select signals. The plurality of memory dies are coupled with wire bonds within the plurality of memory chips for a reduced load for coupling the circuit platform for communicating via a memory channel. The load is sufficiently reduced for having at least two instances of the memory module share the memory channel.

Package on-package devices with multiple levels and methods therefor

Package-on-package (“PoP”) devices with multiple levels and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. First and second conductive lines are coupled to the upper surface of the package substrate respectively at different heights in a fan-out region. A first molding layer is formed over the upper surface of the package substrate. A first and a second wafer-level packaged microelectronic component are located above an upper surface of the first molding layer respectively surface mount coupled to a first and a second set of upper portions of the first conductive lines. A third and a fourth wafer-level packaged microelectronic component are located above the first and the second wafer-level packaged microelectronic component respectively surface mount coupled to a first and a second set of upper portions of the second conductive lines.

Ultra High Performance Interposer

An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via. 1a semiconductor material layer including a first surface and a second surface that is substantially parallel to the first surface and is spaced apart therefrom in a first direction, the semiconductor material layer having a bulk dielectric constant;at least two metalized vias each extending through the semiconductor material layer and having a first end at the first surface and a second end at the second surface, a first pair of the at least two metalized vias being spaced apart from each other at a distance in a second direction orthogonal to the first direction; andan insulating via in the semiconductor layer extending from the first surface toward the second surface and defining an interior volume, the insulating via being positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias; andwherein a dielectric constant of the interior volume is less than the bulk dielectric constant.. A microelectronic interconnection component, comprising: This application is a ...

Single package dual channel memory with co-support

A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements.

WIRE BOND WIRES FOR INTERFERENCE SHIELDING

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region. 1. An apparatus , comprising:a substrate having an upper surface and a lower surface opposite the upper surface;a microelectronic device coupled to the upper surface of the substrate; andwire bond wires having first ends coupled to the upper surface and second ends extending away therefrom, the wire bond wires arranged to shield one or more frequencies.2. The apparatus according to claim 1 , wherein the first ends and the second ends respectively are lower ends and upper ends claim 1 , the apparatus further comprising a conductive layer positioned above the upper ends of the wire bond wires for covering at least a portion of a region to be shielded.3. The apparatus according to claim 2 , wherein the first ends are lower ends claim 2 , and wherein the upper ends of the wire bond wires are bonded to the conductive layer.4. The apparatus according to claim 3 , wherein the conductive layer is a first conductive layer claim 3 , the apparatus further comprising a second conductive layer formed on or in the substrate.5. The apparatus according to claim 4 , wherein ...

Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates

In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, one or more conductive features (120E.A, 120E.B, or both) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

Ultra High Performance Interposer

An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via. 1. A method for making a microelectronic interconnection component , comprising: a plurality of first via openings spaced apart from each other in a first direction; and', 'at least one second via opening in the semiconductor material layer having an entrance at the first surface and extending in the first direction toward the second surface and defining an interior volume, the at least one second via opening being positioned between two planes that are orthogonal to the first direction and that pass through each of a pair of adjacent ones of the plurality of first via openings; and, 'selectively etching a semiconductor material layer having first and second opposed surfaces to simultaneously formforming electrically conductive vias within the plurality of first via openings, and providing a dielectric material within at least the entrance of the at least one second via opening so as to close the at least one second via opening.2. The method of claim 1 , further including plugging the at least one second via opening with a high-pressure TEOS plug prior to the step of filling the plurality of first via openings.3. The ...

Flexible I/O partition of multi-die memory solution

A method of testing a microelectronic package configured to provide memory access can include energizing terminals of the microelectronic package, the terminals including first terminals configured to carry address information and second terminals configured to carry data signals. The method can also include applying read and write test data signals simultaneously to the first and second sets of second terminals, so as to simultaneously test read and write operation in first and second microelectronic elements of the microelectronic package. The first and second microelectronic elements can be configured to provide access to memory storage array locations in the first and second microelectronic elements. The terminals can also include third terminals configured to receive a test mode input that reconfigures the first and second microelectronic elements to permit simultaneous access to memory storage array locations in the first and second microelectronic elements.

Via structure for signal equalization

An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has a first surface and a second surface opposite the first surface. The first surface and the second surface define a thickness of the substrate. A via structure extends from the first surface of the substrate to the second surface of the substrate. The via structure has a first terminal at or proximate to the first surface and a second terminal at or proximate to the second surface provided by a conductive member of the via structure extending from the first terminal to the second terminal. A barrier layer of the via structure is disposed between at least a portion of the conductive member and the substrate. The barrier layer has a conductivity configured to offset a capacitance between the conductive member and the substrate when a signal is passed through the conductive member of the via structure.

Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces

In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.

Ultra high performance interposer

An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.

Ultra high performance interposer

Circuit assemblies with multiple interposer substrates, and methods of fabrication

A combined interposer ( 120 ) includes multiple constituent interposers ( 120. i ), each with its own substrate ( 120. i S) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer ( 120 R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer ( 120 R.B). The constituent interposer substrates ( 120. i S) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.

High-bandwidth memory application with controlled impedance loading

A microelectronic assembly can include an address bus comprising a plurality of signal conductors each passing sequentially through first, second, third, and fourth connection regions, and first and second microelectronic packages. The first microelectronic package can include first and second microelectronic elements, and the second microelectronic package can include third and fourth microelectronic elements. Each microelectronic element can be electrically coupled to the address bus via the respective connection region. An electrical characteristic between the first and second connection regions can be within a same tolerance of the electrical characteristic between the second and third connection regions.

Contact arrangements for stackable microelectronic package structures

An apparatus relates generally to a microelectronic assembly. In such an apparatus, a contact arrangements are disposed on a first surface of a first substrate, including first contacts disposed as a first ring array; second contacts disposed interior to the first contacts as a second ring array; third contacts disposed interior to the second contacts as a third ring array; and fourth contacts disposed interior to the third contacts on the first surface as an innermost array. The first ring array, the second ring array, and the third ring array are concentric rings with the innermost array in a central region of the concentric rings. The first contacts and the fourth contacts are for interconnection with first microelectronic dies. The second contacts and the third contacts are for interconnection with second microelectronic dies.

Wire bond wires for interference shielding

Circuit assemblies with multiple interposer substrates, and methods of fabrication

Ultra high performance interposer

Microelectronic packages and assemblies with improved flyby signaling operation

A microelectronic unit includes microelectronic elements having memory storage arrays. First terminals and second terminals at a surface of the microelectronic unit are configured for connection with corresponding first and second sets of circuit panel contacts which are coupled with conductors of a common signaling bus on the circuit panel. Front surfaces of first and second microelectronic elements define a plurality of first planes at a substantial angle to a second plane defined by the major surface of the circuit panel. Each of a plurality of delay elements within the microelectronic unit is electrically coupled with a signaling path of the common signaling bus between one of the first terminals and a corresponding second terminal. In such way, the delay elements may reduce adverse effects of additive signal energy reflected from the microelectronic packages back towards the common signaling bus.

Package-on-package devices with same level WLP components and methods therefor

Package-on-package (“PoP”) devices with same level wafer-level packaged (“WLP”) components and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region. The first conductive lines extend away from the upper surface of the package substrate. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the conductive lines. WLP microelectronic components are located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines.

Wire bond wires for interference shielding

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Wafer-level packaged components and methods therefor

Wafer-level packaged components are disclosed. In a wafer-level-packaged, an integrated circuit die has first contacts in an inner third region of a surface of the integrated circuit die. A redistribution layer has second contacts in an inner third region of a first surface of the redistribution layer and third contacts in an outer third region of a second surface of the redistribution layer opposite the first surface thereof. The second contacts of the redistribution layer are coupled for electrical conductivity to the first contacts of the integrated circuit die with the surface of the integrated circuit die face-to-face with the first surface of the redistribution layer. The third contacts are offset from the second contacts for being positioned in a fan-out region for association at least with the outer third region of the second surface of the redistribution layer, the third contacts being surface mount contacts.

Dies-on-package devices and methods therefor

Dies-on-package devices and methods therefor are disclosed. In a dies-on-package device, a first IC die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with respect to the first IC die. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first IC die, and around bases and shafts of the conductive lines. A plurality of second IC dies is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. The plurality of second IC dies are respectively coupled to the sets of the conductive lines in middle third portions respectively of the plurality of second IC dies for corresponding fan-in regions thereof.

WIRE BOND WIRES FOR INTERFERENCE SHIELDING

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

TFD I/O partition for high-speed, high-density applications

A microelectronic package can include a substrate having first and second surfaces, first, second, and third microelectronic elements each having a surface facing the first surface, terminals exposed at the second surface, and leads electrically connected between contacts of each microelectronic element and the terminals. The substrate can have first, second, and third spaced-apart apertures having first, second, and third parallel axes extending in directions of the lengths of the apertures. The contacts of the first, second, and third microelectronic elements can be aligned with one of the first, second, or third apertures. The terminals can include first and second sets of first terminals configured to carry address information. The first set can be connected with the first and third microelectronic elements and not with the second microelectronic element, and the second set can be connected with the second microelectronic element and not with the first or third microelectronic elements.

Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces

In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.

ELECTRONIC DEVICE FOR EVENT ALERT AND NOTIFICATION

The electronic device of this invention is generally for an event alert and notification. The electronic device provides a new concept wherein the electronic device is light weight, wearable, attachable to other accessories such as a backpack, is specifically designed for calendaring, event viewing, graphical notification, and alarm. The general purpose of the present invention is to provide an electronic device for calendaring, alert, and event notification, that has many advantages and novel features over existing technology and devices. To attain this, the electronic device generally comprises an electronic screen, an optional memory storing an event, and a circuit connecting the display and the memory. A frame, made of a flexible material, has a means for attaching such a device to attach the device to typical accessories such as a handbag, a backpack, or a refrigerator. 1. An electronic device , comprising:a frame having a first side and a second side;an electronic screen, installed on said first side of said frame, wherein said electronic screen displays a notification in a graphic manner;a power supply to provide electricity to said electronic device;a user interface for a user to input a schedule and set up an alert;an integrated circuit, wherein said integrated circuit is electronically connected to said power supply, said user interface, and said electronic screen; andan attachment layer to attach said electronic device to a surface, wherein said attachment layer is interchangeably installed on said second side of said frame.2. The electronic device of claim 1 , further comprising displaying an upcoming event where an alarm is set.3. The electronic device of claim 2 , wherein said electronic device is flexible.4. The electronic device of claim 2 , wherein said electronic device is water-proof.5. The electronic device of claim 2 , wherein said attachment layer is a Velcro tape.6. The electronic device of claim 2 , wherein said attachment layer is a magnetic ...

BGA ballout partition techniques for simplified layout in motherboard with multiple power supply rail

A microelectronic package can include a substrate and a microelectronic element. The substrate can include terminals comprising at least first power terminals and other terminals in an area array at a surface of the substrate. The substrate can also include a power plane element electrically coupled to the first power terminals. The area array can have a peripheral edge and a continuous gap between the terminals extending inwardly from the peripheral edge in a direction parallel to the surface. The terminals on opposite sides of the gap can be spaced from one another by at least 1.5 times a minimum pitch of the terminals. The power plane element can extend within the gap from at least the peripheral edge at least to the first power terminals. Each first power terminal can be separated from the peripheral edge by two or more of the other terminals.

MICROELECTRONIC COMPONENTS WITH FEATURES WRAPPING AROUND PROTRUSIONS OF CONDUCTIVE VIAS PROTRUDING FROM THROUGH-HOLES PASSING THROUGH SUBSTRATES

In a microelectronic component having conductive vias ( 114 ) passing through a substrate ( 104 ) and protruding above the substrate, conductive features ( 120 E.A, 120 E.B) are provided above the substrate that wrap around the conductive vias' protrusions ( 114 ′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

Ultra high performance interposer

An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.

TFD I/O partition for high-speed, high-density applications

A microelectronic package can include a substrate having first and second surfaces, first, second, and third microelectronic elements each having a surface facing the first surface, terminals exposed at the second surface, and leads electrically connected between contacts of each microelectronic element and the terminals. The substrate can have first, second, and third spaced-apart apertures having first, second, and third parallel axes extending in directions of the lengths of the apertures. The contacts of the first, second, and third microelectronic elements can be aligned with one of the first, second, or third apertures. The terminals can include first and second sets of first terminals configured to carry address information. The first set can be connected with the first and third microelectronic elements and not with the second microelectronic element, and the second set can be connected with the second microelectronic element and not with the first or third microelectronic elements.

Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates

In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

Reduced load memory module using wire bonds and a plurality of rank signals

An apparatus for reducing load in a memory module. In such an apparatus, there is a circuit platform with a plurality of memory chips coupled to the circuit platform. Each memory chip of the plurality of memory chips each has a plurality of memory dies. At least one controller is coupled to the circuit platform and further coupled to the plurality of memory chips for communication with the plurality of memory dies thereof. The at least one controller is for receiving chip select signals to provide a plurality of rank select signals in excess of the chip select signals. The plurality of memory dies are coupled with wire bonds within the plurality of memory chips for a reduced load for coupling the circuit platform for communicating via a memory channel. The load is sufficiently reduced for having at least two instances of the memory module share the memory channel.

Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates

In a microelectronic component having conductive vias ( 114 ) passing through a substrate ( 104 ) and protruding above the substrate, conductive features ( 120 E.A, 120 E.B) are provided above the substrate that wrap around the conductive vias' protrusions ( 114 ′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

PLANAR INDUCTOR DEVICES

A planar inductor device includes a ferrite body and a conductive pathway. The ferrite body extends around an opening in the ferrite body. The conductive pathway includes an input section, a current-splitting section, a coil section, a current-combining section, and an output section connected with each other, the input section extending toward the opening in the ferrite body. The current-splitting section includes a plurality of conductive coils joined with the conductive pathway and electrically disposed parallel to each other. The coil section includes the conductive coils helically wrapped around the ferrite body. The current-combining section includes the conductive coils joined with each other. The output section includes the joined conductive coils extending out of the ferrite body.

Package-on-package devices with WLP components with dual RDLs for surface mount dies and methods therefor

Package-on-package (“PoP”) devices with WLP (“WLP”) components with dual RDLs (“RDLs”) for surface mount dies and methods therefor. In a PoP, a first IC die surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region. A molding layer is formed over the upper surface of the package substrate. A first and a second WLP microelectronic component are located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. Each of the first and the second WLP microelectronic components have a second IC die located between a first RDL and a second RDL. A third and a fourth IC die are respectively surface mount coupled over the first and the second WLP microelectronic components.

Method for Reduced Load Memory Module

A method for reducing load in a memory module. In such a method, a plurality of memory chips are coupled to a circuit platform. Each memory chip of the plurality of memory chips each has a plurality of memory dies. At least one controller is coupled to the circuit platform and further coupled to the plurality of memory chips for communication with the plurality of memory dies thereof. The at least one controller is for receiving chip select signals to provide a plurality of rank select signals in excess of the chip select signals. The plurality of memory dies are coupled with wire bonds within the plurality of memory chips for a reduced load for coupling the circuit platform for communicating via a memory channel. The load is sufficiently reduced for having at least two instances of the memory module share the memory channel.

PLANAR ELECTRONIC DEVICE

A planar electronic device includes top conductors on a top side of a planar substrate connected to conductive vias and defining top conductor groups and bottom conductors on a bottom side connected to corresponding vias and defining bottom conductor groups. The conductors and vias define primary and secondary conductive loops with the top conductor group including at least one primary top conductor and at least one secondary top conductor and with the bottom conductor group including at least one primary bottom conductor and at least one secondary bottom conductor. The top conductors within each group have substantially similar layouts that are different from layouts of the immediately adjacent groups, and the bottom conductors within each group have substantially similar layouts that are different from layouts of the immediately adjacent groups. 1. A planar electronic device comprising:a planar substrate having a cavity configured to receive a ferrite material body therein, the planar substrate having a top side and a bottom side;conductive vias extending through the substrate;top conductors on the top side of the planar substrate and electrically connected to corresponding conductive vias, adjacent top conductors defining top conductor groups; andbottom conductors on the bottom side of the planar substrate and electrically connected to corresponding conductive vias, adjacent bottom conductors defining bottom conductor groups;wherein the top conductors, bottom conductors and conductive vias define a primary conductive loop and a secondary conductive loop, the top conductor group including at least one top conductor of the primary conductive loop and at least one top conductor of the secondary conductive loop, the bottom conductor group including at least one bottom conductor of the primary conductive loop and at least one bottom conductor of the secondary conductive loop;wherein the top conductors within each group have substantially similar layouts that are ...

Planar electronic device

A planar electronic device includes a planar substrate having a cavity configured to receive a ferrite material body therein. The planar substrate has an upper side and a lower side and conductive vias extending through the substrate. Top conductors are provided on the upper side of the planar substrate and are electrically connected to corresponding conductive vias. Bottom conductors are provided on the lower side of the planar substrate and are electrically connected to corresponding conductive vias. The bottom conductors, top conductors and conductive vias define a primary conductive loop and a secondary conductive loop. An upper cover layer covers the upper side and has a high permittivity. The upper cover layer is positioned relative to the top conductors to increase capacitance between the primary and secondary loops.

Wafer-Level Packaged Components and Methods Therefor

Wafer-level packaged components are disclosed. In a wafer-level-packaged, an integrated circuit die has first contacts in an inner third region of a surface of the integrated circuit die. A redistribution layer has second contacts in an inner third region of a first surface of the redistribution layer and third contacts in an outer third region of a second surface of the redistribution layer opposite the first surface thereof. The second contacts of the redistribution layer are coupled for electrical conductivity to the first contacts of the integrated circuit die with the surface of the integrated circuit die face-to-face with the first surface of the redistribution layer. The third contacts are offset from the second contacts for being positioned in a fan-out region for association at least with the outer third region of the second surface of the redistribution layer, the third contacts being surface mount contacts. 1. A wafer-level packaged microelectronic component , comprising:an integrated circuit die of a wafer having first contacts in an inner third region of a surface of the integrated circuit die;a first redistribution layer having second contacts in an inner third region of a first surface of the first redistribution layer and third contacts in an outer third region of a second surface of the first redistribution layer opposite the first surface thereof;the second contacts of the first redistribution layer coupled for electrical conductivity to the first contacts of the integrated circuit die with the surface of the integrated circuit die face-to-face with the first surface of the redistribution layer;a second redistribution layer having fourth contacts in an inner third region of a first surface of the second redistribution layer and interconnects in an outer third region of a second surface of the second redistribution layer opposite the first surface thereof; andthe third contacts offset from the second contacts for being positioned in a fan-out region ...

Package-on-Package Devices with Same Level WLP Components and Methods Therefor

Package-on-package (“PoP”) devices with same level wafer-level packaged (“WLP”) components and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region. The first conductive lines extend away from the upper surface of the package substrate. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the conductive lines. WLP microelectronic components are located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. 1. A package-on-package device , comprising:a package substrate;a first integrated circuit die surface mount coupled to an upper surface of the package substrate;conductive lines coupled to the upper surface of the package substrate in a fan-out region, the first conductive lines extending away from the upper surface of the package substrate;a molding layer formed over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the conductive lines; andwafer-level packaged microelectronic components located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines.2. The package-on-package device according to claim 1 , wherein the conductive lines are wire bond wires.3. The package-on-package device according to claim 1 , wherein the package substrate is a laminate substrate having at least two layers.4. The package-on-package device according to claim 1 , wherein the package substrate includes a fan-out wafer-level redistribution layer.5. The package-on-package device according to claim 4 , wherein:the first ...

Package-on-Package Devices with Upper RDL of WLPS and Methods Therefor

Package-on-package (“PoP”) devices with upper RDLs of WLP (“WLP”) components and methods therefor are disclosed. In a PoP device, a first IC die is surface mount coupled to an upper surface of the package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with reference to the first IC. A molding layer is formed over the upper surface of the package substrate. A first and a second WLP microelectronic component is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. Each of the first and the second WLP microelectronic components have a second IC die located below a first RDL respectively thereof. A third and a fourth IC die are respectively surface mount coupled over the first and the second WLP microelectronic components. 1. A package-on-package device , comprising:a package substrate;a first integrated circuit die surface mount coupled to an upper surface of the package substrate;conductive lines coupled to the upper surface of the package substrate in a fan-out region with reference to the first integrated circuit, the first conductive lines extending away from the upper surface of the package substrate;a molding layer formed over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the conductive lines;a first and a second wafer-level packaged microelectronic component located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines;each of the first and the second wafer-level packaged microelectronic components having a second integrated circuit die located below a first redistribution layer respectively thereof; anda third and a fourth integrated circuit die respectively surface mount coupled over the first and the second wafer-level ...

Dies-on-Package Devices and Methods Therefor

Dies-on-package devices and methods therefor are disclosed. In a dies-on-package device, a first IC die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with respect to the first IC die. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first IC die, and around bases and shafts of the conductive lines. A plurality of second IC dies is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. The plurality of second IC dies are respectively coupled to the sets of the conductive lines in middle third portions respectively of the plurality of second IC dies for corresponding fan-in regions thereof. 1. A dies-on-package device , comprising:a package substrate;a first integrated circuit die surface mount coupled to an upper surface of the package substrate;conductive lines coupled to the upper surface of the package substrate in a fan-out region with respect to the first integrated circuit die, the first conductive lines extending away from the upper surface of the package substrate;a molding layer formed over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the conductive lines; anda plurality of second integrated circuit dies located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines;the plurality of second integrated circuit dies respectively coupled to the sets of the conductive lines in middle third portions respectively of the plurality of second integrated circuit dies for corresponding fan-in regions thereof.2. The dies-on-package device according to claim 1 , wherein the conductive lines are wire bond wires.3. The dies- ...

Package-on-Package Devices with Multiple Levels and Methods Therefor

Package-on-package (“PoP”) devices with multiple levels and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. First and second conductive lines are coupled to the upper surface of the package substrate respectively at different heights in a fan-out region. A first molding layer is formed over the upper surface of the package substrate. A first and a second wafer-level packaged microelectronic component are located above an upper surface of the first molding layer respectively surface mount coupled to a first and a second set of upper portions of the first conductive lines. A third and a fourth wafer-level packaged microelectronic component are located above the first and the second wafer-level packaged microelectronic component respectively surface mount coupled to a first and a second set of upper portions of the second conductive lines. 1. A package-on-package device , comprising:a package substrate;a first integrated circuit die surface mount coupled to an upper surface of the package substrate;first conductive lines coupled to the upper surface of the package substrate, the first conductive lines extending away from the upper surface of the package substrate to terminate at a first height;second conductive lines coupled to the upper surface of the package substrate, the second conductive lines extending away from the upper surface of the package substrate to terminate at a second height greater than the first height;the first conductive lines and the second conductive lines located in a fan-out region;a first molding layer formed over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the first conductive lines and the second conductive lines;a first wafer-level packaged microelectronic component and a second wafer-level packaged microelectronic component located above an upper ...

Package-on-Package Devices with WLP Components with Dual RDLS for Surface Mount Dies and Methods Therefor

Package-on-package (“PoP”) devices with WLP (“WLP”) components with dual RDLs (“RDLs”) for surface mount dies and methods therefor. In a PoP, a first IC die surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region. A molding layer is formed over the upper surface of the package substrate. A first and a second WLP microelectronic component are located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. Each of the first and the second WLP microelectronic components have a second IC die located between a first RDL and a second RDL. A third and a fourth IC die are respectively surface mount coupled over the first and the second WLP microelectronic components. 1. A package-on-package device , comprising:a package substrate;a first integrated circuit die surface mount coupled to an upper surface of the package substrate;conductive lines coupled to the upper surface of the package substrate in a fan-out region, the first conductive lines extending away from the upper surface of the package substrate;a molding layer formed over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the conductive lines;a first and a second wafer-level packaged microelectronic component located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines;each of the first and the second wafer-level packaged microelectronic components having a second integrated circuit die located between a first redistribution layer and a second redistribution layer; anda third and a fourth integrated circuit die respectively surface mount coupled over the first and the second wafer-level packaged microelectronic components.2. The package-on-package ...

Die stacking techniques in bga memory package for small footprint cpu and memory motherboard design

A microelectronic package can include a substrate comprising a dielectric element having first and second opposite surfaces, and a microelectronic element having a face extending parallel to the first surface. The substrate can also include a plurality of peripheral edges extending between the first and second surfaces defining a generally rectangular or square periphery of the substrate. The substrate can further include a plurality of contacts and terminals, the contacts being at the first surface, the terminals being at at least one of the first or second surfaces. The microelectronic elements can have a plurality of edges bounding the face, and a plurality of element contacts at the face electrically coupled with the terminals through the contacts of the substrate. Each edge of the microelectronic element can be oriented at an oblique angle with respect to the peripheral edges of the substrate.

ULTRA HIGH PERFORMANCE INTERPOSER

An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via. 1. An interconnection component for use in a microelectronic assembly , comprising:a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction therefrom by a thickness of the semiconductor material layer;at least two metalized vias, each extending through the semiconductor material layer and having a first end at the first surface and a second end at the second surface, a first pair of the at least two metalized vias being spaced apart from each other in a second direction orthogonal to the first direction; anda first insulating via in the semiconductor layer extending from the first surface toward the second surface, the insulating via being positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias; anda dielectric material at least partially filling the first insulating via or at least partially enclosing a void in the insulating via.2. The interconnection component of claim 1 , wherein no ...

Vertical Memory Module Enabled by Fan-Out Redistribution Layer

Vertical memory modules enabled by fan-out redistribution layer(s) (RDLs) are provided. Memory dies may be stacked with each die having a signal pad directed to a sidewall of the die. A redistribution layer (RDL) is built on sidewalls of the stacked dies and coupled with the signal pads. The RDL may fan-out to UBM and solder balls, for example. An alternative process reconstitutes dies on a carrier with a first RDL on a front side of the dies. The dies and first RDL are encapsulated, and the modules vertically disposed for a second reconstitution on a second carrier. A second RDL is applied to exposed contacts of the vertically disposed modules and first RDLs. The vertical modules and second RDL are encapsulated in turn with a second mold material. The assembly may be singulated into individual memory modules, each with a fan-out RDL on the sidewalls of the vertically disposed dies. 1. A method , comprising:disposing multiple memory dies to make a vertical stack, each memory die having a respective signal pad directed to an edge of the memory die in a common direction with the signal pads of the multiple memory dies; andbuilding a redistribution layer (RDL) on a sidewall of the stack of memory dies, the redistribution layer (RDL) perpendicular to the vertical stack and communicatively coupled with the signal pads.2. The method of claim 1 , wherein building the RDL on the sidewall includes communicatively coupling the RDL to the signal pads with solderless connections claim 1 , or includes applying a solderless process to communicatively couple the RDL to the signal pads.3. The method of claim 1 , further comprising building the RDL as a fan-out of conductive lines from the signal pads.4. The method of claim 1 , further comprising building the RDL to fan-out conductive lines from the signal pads to under ball metallization or to solder balls.5. The method of claim 1 , further comprising building multiple redistribution layers (RDLs) on the sidewall.6. The method of ...

MICROELECTRONIC PACKAGES AND ASSEMBLIES WITH REPEATERS

A microelectronic assembly includes a circuit panel having a plurality of first contacts at a major surface thereof. One or more microelectronic packages comprise a plurality of microelectronic elements, the one or more packages having terminals electrically coupled with the first contacts, wherein each package includes at least one microelectronic element having a face, and element contacts at the face which are electrically coupled with the plurality of terminals. A repeater (redriver or retimer) assembly is configured to condition one or more signals received from a memory channel control element including one or more signals selected from: an address signal, a command signal, or a data signal, such that the plurality of the microelectronic elements are coupled to the at least one repeater assembly to receive the conditioned signals. 1. A microelectronic assembly , comprising:a circuit panel having a plurality of first contacts at a major surface of the circuit panel; a dielectric element having a major surface that defines a first plane, the dielectric element having one or more layers of dielectric material and one or more electrically conductive layers thereon;', 'a plurality of electrically conductive package terminals disposed at an interconnect region of the dielectric element adjacent an interconnect edge of the dielectric element, the package terminals being electrically coupled with the first contacts;', 'a plurality of stacked microelectronic elements, each of the microelectronic elements having a respective front face and respective element contacts at the front face which are electrically coupled with the package terminals of the respective microelectronic package through electrically conductive leads extending from the element contacts to the package terminals, each microelectronic element comprising a memory storage array; and', 'an encapsulant region that contacts the element contacts at the front face of each of the microelectronic elements and ...

Wire Bond Wires for Interference Shielding

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region. 1. An apparatus for a microelectronic package having interference protection , comprising:a substrate having an upper surface and a lower surface opposite the upper surface and having bond pads on the upper surface;a microelectronic device coupled to the upper surface of the substrate;wire bond wires having lower ends coupled to the bond pads, the wire bond wires extending away from the upper surface of the substrate and placed for one or more frequencies associated with the interference;the wire bond wires positioned on at least one side of the microelectronic device to provide a shielding region with respect to the interference;a conductive surface positioned above the wire bond wires for covering the shielding region; andthe wire bond wires having upper ends coupled to the conductive surface.2. The apparatus according to claim 1 , wherein the wire bond wires are place to shield the microelectronic device from the interference.3. The apparatus according to claim 2 , wherein the microelectronic device is an active device.4. The apparatus according to claim 2 ...

COMPACT MICROELECTRONIC ASSEMBLY HAVING REDUCED SPACING BETWEEN CONTROLLER AND MEMORY PACKAGES

A microelectronic package has terminals at a surface of a substrate having first and second half areas, each half area extending from a diagonal that bisects the first surface and a respective opposite corner of the first surface. Terminals for carrying data and address information in the first half area provide first memory channel access to a first memory storage array, and terminals for carrying data and address information in the second half area provide second memory channel access to a second memory storage array. The package may include first and second microelectronic elements overlying a same surface of the substrate which may be stacked in transverse orientations. 1. A microelectronic package configured to provide multiple channel memory access , comprising:a substrate having first and second opposite surfaces, the first surface having third and fourth corners opposite one another along a first diagonal of the first surface, and first and second corners opposite one another along a second diagonal of the first surface transverse to the first diagonal, the first diagonal dividing the first surface in first and second half areas each extending from the first diagonal to one of the first corner or the second corner, the substrate including a plurality of terminals at the first surface, the terminals including first terminals configured to carry data and second terminals configured to carry address information, the first terminals and the second terminals in the first half area providing access to a first memory storage array corresponding to a first memory channel, and the first terminals and the second terminals in the second half area providing access to a second memory storage array corresponding to a second memory channel different from the first memory channel; andfirst and second microelectronic elements overlying the second surface and stacked in first and second orientations transverse to one another, the first and second microelectronic elements ...

BGA BALLOUT PARTITION TECHNIQUES FOR SIMPLIFIED LAYOUT IN MOTHERBOARD WITH MULTIPLE POWER SUPPLY RAIL

A microelectronic package can include a substrate and a microelectronic element. The substrate can include terminals comprising at least first power terminals and other terminals in an area array at a surface of the substrate. The substrate can also include a power plane element electrically coupled to the first power terminals. The area array can have a peripheral edge and a continuous gap between the terminals extending inwardly from the peripheral edge in a direction parallel to the surface. The terminals on opposite sides of the gap can be spaced from one another by at least 1.5 times a minimum pitch of the terminals. The power plane element can extend within the gap from at least the peripheral edge at least to the first power terminals. Each first power terminal can be separated from the peripheral edge by two or more of the other terminals. 1. A microelectronic package , comprising:a substrate comprising a dielectric element having a surface, terminals comprising at least first power terminals and other terminals in an area array at the surface, contacts coupled with the terminals, and traces electrically coupling at least some of the terminals with at least some of the contacts, each trace having a minimum lateral dimension parallel to the surface, the substrate further comprising a power plane element electrically coupled to the first power terminals and having a minimum lateral dimension parallel to the surface substantially greater than the minimum lateral dimension of each trace; anda microelectronic element having element contacts electrically coupled with the terminals through the traces and the contacts of the substrate,wherein the area array has a peripheral edge and a continuous gap between the terminals extending inwardly from the peripheral edge in a direction parallel to the surface, the terminals on opposite sides of the gap being spaced from one another by at least 1.5 times a minimum pitch of the terminals, and the power plane element extends ...

Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates

In a microelectronic component having conductive vias ( 114 ) passing through a substrate ( 104 ) and protruding above the substrate, conductive features ( 120 E.A, 120 E.B) are provided above the substrate that wrap around the conductive vias' protrusions ( 114 ′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

Embedded Wire Bond Wires for Vertical Integration With Separate Surface Mount and Wire Bond Mounting Surfaces

In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires. 1. A vertically integrated microelectronic package , comprising:a circuit platform having an upper surface and a lower surface opposite the upper surface thereof, the upper surface of the circuit platform having a wire bond-only surface area;a first microelectronic device coupled to the upper surface of the circuit platform;first wire bond wires coupled to and extending away from an upper surface of the first microelectronic device;second wire bond wires coupled to the upper surface of the circuit platform in the wire bond-only surface area and coupled to the upper surface of the first microelectronic device;a protective layer disposed over the circuit platform and the first microelectronic device, the protective layer having a lower surface and an upper surface opposite the lower surface thereof with the lower surface of the protective layer being in contact with the upper surface of the circuit platform, the upper surface of the protective layer having a surface mount-only area; anda second microelectronic device in a face-down orientation coupled to upper ...

VIA STRUCTURE FOR SIGNAL EQUALIZATION

An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has a first surface and a second surface opposite the first surface. The first surface and the second surface define a thickness of the substrate. A via structure extends from the first surface of the substrate to the second surface of the substrate. The via structure has a first terminal at or proximate to the first surface and a second terminal at or proximate to the second surface provided by a conductive member of the via structure extending from the first terminal to the second terminal. A barrier layer of the via structure is disposed between at least a portion of the conductive member and the substrate. The barrier layer has a conductivity configured to offset a capacitance between the conductive member and the substrate when a signal is passed through the conductive member of the via structure. 1. An apparatus , comprising:a substrate having a first surface and a second surface opposite the first surface, the first surface and second surface defining a thickness of the substrate;a via structure extending from the first surface of the substrate to the second surface of the substrate;wherein the via structure has a first terminal at or proximate to the first surface and a second terminal at or proximate to the second surface provided by a conductive member of the via structure extending from the first terminal to the second terminal;wherein a barrier layer of the via structure is disposed between at least a portion of the conductive member and the substrate; andwherein the barrier layer has a conductivity configured to offset a capacitance between the conductive member and the substrate when a signal is passed through the via structure.2. The apparatus according to claim 1 , wherein the barrier layer has a film resistivity equal to or less than approximately 0.5 Ohm-cm.3. The apparatus according to claim 1 , wherein:the conductive member, the barrier layer, and the ...

SINGLE PACKAGE DUAL CHANNEL MEMORY WITH CO-SUPPORT

A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements. 1a support element having first and second oppositely-facing surfaces and a plurality of substrate contacts at the first surface or the second surface, the support element having oppositely-facing north and south edges adjacent to oppositely-facing east and west edges each extending between the north and south edges, the second surface having a southwest region encompassing entire lengths of the south and west edges and extending in orthogonal directions from each of the south and west edges one-third of each distance toward the north edge and toward the east edge, respectively;zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, each microelectronic element having a memory storage array and first and second columns of element contacts extending along a front face thereof adjacent and parallel to first and second opposite edges of the front face, respectively, the first and second edges of the zeroth microelectronic element ...

CIRCUIT ASSEMBLIES WITH MULTIPLE INTERPOSER SUBSTRATES, AND METHODS OF FABRICATION

A combined interposer () includes multiple constituent interposers (i), each with its own substrate (iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (R.B). The constituent interposer substrates (iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided. 1. A circuit assembly comprising:a combined interposer comprising a plurality of constituent interposers, each constituent interposer comprising a substrate, the substrates being laterally spaced from each other;wherein the combined interposer comprises a first circuit layer comprising circuitry and physically contacting a top surface of two or more of the substrates, the circuitry comprising a circuit extending over at least two of said two or more of the substrates;wherein for each of two or more of the constituent interposers, the constituent interposer comprises a first constituent circuit layer which is part of the first circuit layer, the first constituent circuit layer being present on a top surface of the constituent interposer's substrate, the first constituent circuit layer comprising circuitry;wherein the first circuit layer comprises first contact pads on top;wherein the circuit assembly further comprises one or more circuit modules at least one of which comprises an integrated circuit, the one or more circuit modules overlying the first circuit layers, each circuit module comprising one or more contact pads attached to one or more first contact pads.2. The circuit assembly of wherein at least a portion of at least one first contact pad overlies a gap ...

TFD I/O Partition for High-Speed, High-Density Applications

A microelectronic package can include a substrate having first and second surfaces, first, second, and third microelectronic elements each having a surface facing the first surface, terminals exposed at the second surface, and leads electrically connected between contacts of each microelectronic element and the terminals. The substrate can have first, second, and third spaced-apart apertures having first, second, and third parallel axes extending in directions of the lengths of the apertures. The contacts of the first, second, and third microelectronic elements can be aligned with one of the first, second, or third apertures. The terminals can include first and second sets of first terminals configured to carry address information. The first set can be connected with the first and third microelectronic elements and not with the second microelectronic element, and the second set can be connected with the second microelectronic element and not with the first or third microelectronic elements.

Planar inductor devices

A planar inductor device (1000) comprises a ferrite body (1016) and a conductive pathway (1002). The ferrite body extends around an opening (1014) in the ferrite body. The conductive pathway includes an input section (1004), a current-splitting section (1016), a coil section (1008), a current-combining section (1010), and an output section (1012) connected with each other, the input section extending toward the opening in the ferrite body. The current- splitting section includes a plurality of conductive coils (1018) joined with the conductive pathway and electrically disposed parallel to each other. The coil section includes the conductive coils helically wrapped around the ferrite body. The current-combining section includes the conductive coils joined with each other, and the output section includes the joined conductive coils extending out of the ferrite body.

Planar inductor devices

A planar inductor device (1000) comprises a ferrite body (1016) and a conductive pathway (1002). The ferrite body extends around an opening (1014) in the ferrite body. The conductive pathway includes an input section (1004), a current-splitting section (1016), a coil section (1008), a current-combining section (1010), and an output section (1012) connected with each other, the input section extending toward the opening in the ferrite body. The current- splitting section includes a plurality of conductive coils (1018) joined with the conductive pathway and electrically disposed parallel to each other. The coil section includes the conductive coils helically wrapped around the ferrite body. The current-combining section includes the conductive coils joined with each other, and the output section includes the joined conductive coils extending out of the ferrite body.

Wire bond wires for interference shielding

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

High-bandwidth memory application with controlled impedance loading

A microelectronic assembly can include an address bus comprising a plurality of signal conductors each passing sequentially through first, second, third, and fourth connection regions, and first and second microelectronic packages. The first microelectronic package can include first and second microelectronic elements, and the second microelectronic package can include third and fourth microelectronic elements. Each microelectronic element can be electrically coupled to the address bus via the respective connection region. An electrical characteristic between the first and second connection regions can be within a same tolerance of the electrical characteristic between the second and third connection regions.

High-bandwidth memory application with controlled impedance loading

A microelectronic assembly can include an address bus comprising a plurality of signal conductors each passing sequentially through first, second, third, and fourth connection regions, and first and second microelectronic packages. The first microelectronic package can include first and second microelectronic elements, and the second microelectronic package can include third and fourth microelectronic elements. Each microelectronic element can be electrically coupled to the address bus via the respective connection region. An electrical characteristic between the first and second connection regions can be within a same tolerance of the electrical characteristic between the second and third connection regions.

High-bandwidth memory application with controlled impedance loading

Wire bond wires for interference shielding

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Bond wires for interference shielding

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Wire bond wires for interference shielding

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Bond wires for interference shielding

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Microelectronic components with features wrapping around protrusions of conductive vias protruding prom through-holes passing through substrates

In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114') to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.