GRAPHITE-LAMINATED CHIP-ON-FILM-TYPE SEMICONDUCTOR PACKAGE HAVING IMPROVED HEAT DISSIPATION AND ELECTROMAGNETIC WAVE SHIELDING FUNCTIONS

Technical Field

The invention relates to a as a driving display device, display the main parts of the laminated graphite of chip-on-film semiconductor package.

The application requests submitted to the Korean Patent office 21 August 2017 of the Korean Patent application number 10 - 2017 - 0105442 priority, all of its elements are included in the specification.

Background Art

In recent years, as the attention degree of large high resolution displays, in the operation of the drive integrated circuit, in particular, in the operation display drive integrated circuit chip (Display Driver Integrated circuit Chip) when, with the calorific value of the increase, the temperature rises to more than the operation range, thereby affecting the quality of the display, or to hinder the normal operation of the display, or damage due to high temperature, so also will shorten the service life.

In response to the large resolution display, so far attempts to heat dissipation effect is achieved in other ways, but its effect gradually reach the bottleneck, therefore require more innovative way.

And, in order to intelligent mobile phone is representative of the performance of the mobile telephone and television (TV) of which the height and in the computer, the corresponding module in the radio frequency (RF) of the relevant module electromagnetic interference generated by (electromagnetic interference, EMI) or in the high speed operation of the integrated circuit chip is generated in the electromagnetic wave interference affecting the drive integrated circuit, thus the liquid crystal panel or the organic light-emitting diode (OLED) panel in noise, or often the problem of discolored, and, compared with the previous, liquid crystal display (LCD) screen is very large, picture frequency becomes very high speed, therefore, due to the influence of the fine interference of electromagnetic wave, may be on the picture the generation of considerable noise source.

And, the liquid crystal display drive integrated circuit compared with the previous, characteristic variable height in order to form the high-speed and high frequency operation, therefore generating by the drive integrated circuit EMI generated by the impact of the Image quality of the display or the impact of other integrated circuit chip.

Therefore, a need for a shielding technique, so as to protect the display driving integrated circuit from electromagnetic interference, or the protection of other integrated circuit chips from display drive integrated circuit generated in the electromagnetic wave interference.

Content of the invention

(A) technical problem to be solved

The present invention is to improve the operation and solve the large resolution display driving integrated circuit chip and the heat dissipation problem generated when the electromagnetic wave interference to the question, and its object is to provide a drive integrated circuit chip can be generated in the effective heat dissipation of the chip-on-film semiconductor package and display device including the same.

(B) the technical proposal

The present invention provides a chip-on-film semiconductor package, comprising: integrated circuit chip; the printed circuit board layer; and the graphite layer, the integrated circuit chip directly or through the mount device is connected to the one side of the printed circuit board layer, the graphite layer between said printed circuit board layer on the opposite side.

And, the present invention provides a display apparatus, including: the membrane on chip type semiconductor package; the base plate; and a display panel.

(C) the beneficial effect

The membrane of this invention on chip type semiconductor package and display device including the same can be will affect the display quality of the operation of the integrated circuit chip and the heat to the outside of the emitted, so as to minimize the impact.

And, by preventing the temperature of the integrated circuit chip is too high to make the stable operation in the best state, display quality is also retained in the best state, and, reduce the temperature of the drive integrated circuit chip damage caused by too high, to increase the service life of the drive integrated circuit chip, thus also can prolong the service life of the display.

In particular, graphite laminated in the printed circuit board, and therefore will not only the heat generated by the circuit component to the direction of the opposite surface of the fast dissipation of the excellent effect, but also because the conductive characteristics of the graphite itself, the shielding effect is excellent electromagnetic wave interference, so that the display drive integrated circuit will not be deterioration of the function of the chip is kept constant, and, also can prevent the other integrated circuit deterioration of the function of the chip.

Therefore, to keep the quality of the display at the same time, increase the service life of the drive integrated circuit chip, thus also can prolong the service life of the display.

And, the invention one embodiment of chip-on-film of the semiconductor device when the linkage is operated, even if the graphite has been laminated, by improving the membrane on the opposite side of the visual appearance of, in the direction of the graphite can be confirmed with the naked eye on the opposite side of the film of the external lead wire linkage pad, thus in the chip-on-film semiconductor packaging and display substrate such as when bonding process, can improve the adhesion of the adhesive of the accuracy and strength.

Description of drawings

Figure 1 is the diagram of shown printed circuit board layer 202 of substrate Department 103 direction is laminated on one surface of the graphite layer 106 in the film, in the printed circuit board layer 202 of the circuit pattern layer 102 is arranged on one surface in the direction of the direction mount device 109, and in the gap filler 110 after, stacked integrated circuit chip 101 of the chip-on-film semiconductor package with the cross section of an example.

Figure 2 is the plan view of the integrated circuit chip 101 either directly or through the mount device 109 is connected to the printed circuit board layer 202 of one surface of the structure of the chip-on-film in the direction of the upper portion of the semiconductor package.

Figure 3 is the plan view of the graphite film laminated on the lower part of the chip type semiconductor package of the direction.

Figure 4 is the diagram of showing substrate Department 103 arranged on one side of the circuit pattern layer 102 general printed circuit board layer 202.

Figure 5 is the diagram of showing as shown in Figure 4 of the printed circuit board layer 202 of substrate Department 103 on one side of the direction, the graphite powder 302 is arranged on the adhesive layer 104 after, using roller 301 to the circuit pattern layer 102 and substrate Department 103 two direction pressure, so that the graphite layer 106 is laminated on the printed circuit board layer 202 on one side of the process.

Figure 6 is the diagram of showing as shown in Figure 4 of the printed circuit board layer 202 of substrate Department 103 direction on one side, the membrane 401 is arranged on the adhesive layer 104 after, using roller 301 to the circuit pattern layer 102 and substrate Department 103 two direction pressure, so that the graphite layer 106 is laminated on the printed circuit board layer 202 on one side of the process.

Figure 7 is the diagram of showing the printed circuit board layer 202 of substrate Department 103 direction is laminated on one surface of the graphite layer 106 of the chip-on-film semiconductor package manufacturing process of the film in the one example of the profile.

Figure 8 is the diagram of showing the printed circuit board layer 202 of substrate Department 103 direction on one surface of the adhesive layer are sequentially laminated 104 and graphite layer 106 of the chip-on-film semiconductor package manufacturing process of the film in the one example of the profile.

Figure 9 is the diagram of showing the printed circuit board layer 202 of substrate Department 103 direction is laminated on one surface of the graphite layer 106, in the graphite layer 106 of the substrate Department 103 of the opposite direction are successively stacked on one surface of the adhesive layer 107 and a protecting film 108 of the chip-on-film semiconductor package manufacturing process of the film in the one example of the profile.

Figure 10 is the diagram of showing the printed circuit board layer 202 of substrate Department 103 direction are laminated on one surface of the adhesive layer 104 and the graphite layer 106, in the graphite layer 106 of the substrate Department 103 of the opposite direction are successively stacked on one surface of the adhesive layer 107 and a protecting film 108 of the chip-on-film semiconductor package manufacturing process of the film in the one example of the profile.

Figure 11 is the diagram of the printed circuit board layer 202 of substrate Department 103 direction laminated on one surface of the adhesive layer 104, the protective film layer 105, in the protective film layer 105 of the substrate Department 103 direction is laminated on one surface of the graphite layer 106 of the chip-on-film semiconductor package manufacturing process of the film in the one example of the profile.

Figure 12 is the chart of Figure 8 of the printed circuit board layer 202 of substrate Department 103 direction on one surface of the adhesive layer are sequentially laminated 104 and graphite layer 106 in the film, in the printed circuit board layer 202 of the circuit pattern layer 102 is arranged on one surface in the direction of the direction mount device 109, and in the gap filler 110 after the, stacked integrated circuit chip 101 of the chip-on-film semiconductor package with the cross section of an example.

Figure 13 is the graph of Figure 9 of the printed circuit board layer 202 of substrate Department 103 direction is laminated on one surface of the graphite layer 106 in the film, in the printed circuit board layer 202 of the circuit pattern layer 102 is arranged on one surface in the direction of the direction mount device 109, and in the gap filler 110 after the, stacked integrated circuit chip 101 of the chip-on-film semiconductor package with the cross section of an example.

Figure 14 is the graph of shown Figure 10 of the printed circuit board layer 202 of substrate Department 103 direction on one surface of the adhesive layer are sequentially laminated 104 and graphite layer 106, the graphite layer 106 of the substrate Department 103 of the opposite direction are successively stacked on one surface of the adhesive layer 107 and a protecting film 108 in the film, in the printed circuit board layer 202 of the circuit pattern layer 102 is arranged on one surface in the direction of the direction mount device 109, and in the gap filler 110 after the, stacked integrated circuit chip 101 of the chip-on-film semiconductor package with the cross section of an example.

Figure 15 is the chart of shown Figure 11 of the printed circuit board layer 202 of substrate Department 103 direction laminated on one surface of the adhesive layer 104, the protective film layer 105, the protective film layer 105 of the substrate Department 103 direction is laminated on one surface of the graphite layer 106 in the film, in the printed circuit board layer 202 of the circuit pattern layer 102 is arranged on one surface in the direction of the direction mount device 109, and in the gap filler 110 after the, stacked integrated circuit chip 101 of the chip-on-film semiconductor package with the cross section of an example.

Figure 16 is the plan view of the printed circuit board layer 202 on one side directly or through the mount device 109 is connected with the integrated circuit chip 101 and the outer lead linkage pad 204 to the integrated circuit is arranged in the direction perpendicular to the length direction of the chip-on-film in the direction of the upper part of the semiconductor package.

Figure 17 is the floorplan of the external lead wire linkage pad 204 to the integrated circuit chip 101 in a direction perpendicular to the direction of the length of the set, the graphite layer 106 is provided in addition to the external lead wire linkage pad of the printed circuit board layer 202 of the other side of the area in the area, to separate two above laminated film on the laminated graphite chip type semiconductor package of the lower direction.

Figure 18 is the plan view of the printed circuit board layer 202 of the graphite to separate two above laminated on one surface of the directly or through the mount device 109 is connected with the integrated circuit chip 101 and the outer lead linkage pad 204 to the integrated circuit is arranged in the direction perpendicular to the length direction of the chip-on-film in the direction of the upper part of the semiconductor package.

Mode of execution

Below, with reference to the Figures of the present invention film chip-on-semiconductor package and method of manufacturing the same of the detailed description of the embodiment, in order to make the invention belongs to the technical field of ordinary technical personnel which is capable of easy implementation.

Below, with reference to the Figures of the present invention film chip-on-semiconductor package and method for manufacturing the same description.

Below, by embodiments of the present invention structure and characteristics, however, the described embodiment only instantiates the invention, but not limit the invention.

Below, with reference to Figure 1 description of the chip-on-film semiconductor package structure.

The invention of the semiconductor package includes a chip-on-film: integrated circuit chip 101; the printed circuit board layer 202; and the graphite layer 106.

The integrated circuit chip 101 either directly or through the mount device 109 is connected to the printed circuit board layer 202 of a surface. The wires arranged device 109 as long as it is to the printed circuit board layer 202 circuit of the integrated circuit chip 101 is electrically connected to the, do not limit, the wires arranged device and in particular can be adopts a lug, its material can be gold, copper, nickel or a combination thereof.

The invention in one embodiment, the printed circuit board layer 202 can include a circuit pattern layer 102 and substrate Department 103. The circuit pattern layer 102 can be the integrated circuit chip 101 form a circuit pattern, as long as the circuit is composed of the material, not be placed, its material can be gold, copper, nickel or a combination thereof. The substrate Department 103 as long as it is an insulating material, and is not to be placed, the substrate Department 103 can be a flexible film, can be structure through of transparent film, in particular, can be a polyimide thin film.

The invention in one embodiment, the printed circuit board layer 202 can be a thickness of 25 μm to 50 μm. When the thickness is smaller than 25 μm when, anti-bending or tearing the reduction in strength, when the thickness is more than 50 μm when, reduced flexibility, which could result in poor flexibility.

The invention in one embodiment, the integrated circuit chip 101 with the printed circuit board layer 202 between the wires of the installed device 109 can be filler used for the exposed area 110 to the landfill. For the filler 110, as long as capable of suppressing the used and installed device 109 is exposed to the air and cause oxidation, then do not attempt to limit, said fillers in particular can be liquid resin, epoxy resin.

Figure 2 is the plan view of the integrated circuit chip 101 either directly or through the mount device 109 is connected to the printed circuit board layer 202 on one side of the film structure on the upper part of the chip type semiconductor package of the direction.

The invention in one embodiment, the integrated circuit chip 101 can be a display drive integrated circuit chip (Display Driver Integrated Circut chip, DDI chip).

The graphite layer 106 is laminated on the printed circuit board layer 202 on the opposite side.

Figure 3 is the plan view of the graphite film laminated on the lower part of the chip type semiconductor package of the direction.

The invention in one embodiment, the graphite layer 106 can be carbonized high molecular film or a film formed by the graphite powder.

Figure 4 is the diagram of shown substrate Department 103 arranged on one side of the circuit pattern layer 102 general printed circuit board layer 202.

Figure 5 is the diagram of showing as shown in Figure 4 of the printed circuit board layer 202 of substrate Department 103 on one side of the direction, the graphite powder 302 is arranged on the adhesive layer 104 after, using roller 301 to the pattern layer 102 and substrate Department 103 two direction pressure, so that the graphite layer 106 is laminated on the printed circuit board layer 202 on one side of the process.

Figure 6 is the diagram of showing as shown in Figure 4 of the printed circuit board layer 202 of substrate Department 103 direction on one side, the membrane 401 is arranged on the adhesive layer 104 after, using roller 301 to the circuit pattern layer 102 and substrate Department 103 two direction pressure, thus the graphite 106 is laminated on the printed circuit board layer 202 on one side of the process.

The invention in one embodiment, the membrane 401 can be artificial graphite, in particular can be carbonized high molecular film.

The invention in one embodiment, the polymer film can be a polyimide film.

The invention in one embodiment, the carbonized is implementation includes carbonization step and graphite step heat treatment method.

The invention in one embodiment, the carbonized polyimide film includes the step of introducing into having 1st 1st section of temperature in the heater, so that said high molecular film carbonized and converted into carbon membrane step.

The invention in one embodiment, the 1st temperature interval is 500 ± 50 °C to 1000 °C section of rise sequentially.

The invention in one embodiment, the graphite includes the step of introducing into having the carbon membrane as a linear temperature rise interval of the 2nd 2nd section of temperature in the heater, and the step is converted into graphite.

The invention in one embodiment, the 2nd heater of a length of 4000 mm to 6000 mm.

The invention in one embodiment, the 2nd temperature interval is 1000 °C to 2800 °C section of rise sequentially.

The invention in one embodiment, the 2nd temperature range including 1000 °C to 1500 °C section 2 - 1 temperature interval, 1500 °C to 2200 °C section 2 - 2 temperature interval and 2200 °C to 2800 °C section 2 - 3 temperature interval.

The invention in one embodiment, the graphite comprises the steps in the section 2 - 1 in the temperature interval, in order to 0.33 mm/seconds to 1.33 mm/seconds, the transverse movement of the carbon membrane, and make the 2nd heater internal temperature rise per minute 1 °C to 5 °C at the same time, the carbon membrane to the heat treatment to the 1 to 4 hour steps.

The invention in one embodiment, the graphite layer 106 can be a thickness of 5 μm to 40 μm. When the thickness is less than 5 μm when, the heat dissipation effect is reduced, when the thickness is more than 40 μm when, the heat dissipation effect a similar decline.

The invention in one embodiment, the graphite layer 106 with the printed circuit board layer 202 also may be included between the adhesive layer 104, 107.

The invention in one embodiment, the adhesive layer 104, 107 can be upon application of pressure to appear or enhance the binding activity of the pressure-sensitive adhesive (Pressure sensitive adhesive, PAS), and in particular can be is acrylic adhesive or polyimide, polyethylene glycol terephthalate, the double-sided adhesive.

The invention in one embodiment, the adhesive layer 104, 107 can include conductive particles.

The invention in one embodiment, the adhesive layer 104, 107 of the thickness may be 3.5 μm to 5 μm.

Figure 7 is the diagram of showing the printed circuit board layer 202 of substrate Department 103 direction is laminated on one surface of the graphite layer 106 of the chip-on-film semiconductor package manufacturing process of the film in the one example of the profile.

Figure 8 is the diagram of showing the printed circuit board layer 202 of substrate Department 103 direction on one surface of the adhesive layer are sequentially laminated 104 and graphite layer 106 of the chip-on-film semiconductor package manufacturing process of the film in the one example of the profile.

The invention in one embodiment, the graphite layer 106 on one side may also include a protection layer 108.

The invention in one embodiment, the protective film layer 108 can be stacked in the graphite layer 106 of the printed circuit board layer 202 of substrate Department 103 on one side of the direction.

The invention in one embodiment, the protective film layer 108 can be a insulating film, in particular can be a polyester resin film, and can include polyethylene terephthalate (PET), polybutylene terephthalate (PBT), polytrimethylene terephthalate (PTET), cyclohexyl terephthalate (PCHT) and polyethylene naphthalate (PEN) or a combination thereof.

The invention in one embodiment, the protective film layer 108 can be as the thickness of 1.5 μm to 3.0 μm.

Figure 9 is the diagram of showing the printed circuit board layer 202 of substrate Department 103 direction on one side of the laminated graphite layer 106, of the graphite substrate Department 103 of the opposite direction are successively stacked on one surface of the adhesive layer 107 and a protecting film 108 of the chip-on-film semiconductor package manufacturing process of the film in the one example of the profile.

Figure 10 is the diagram of showing the printed circuit board layer 202 of substrate Department 103 direction on one surface of the adhesive layer are sequentially laminated 104 and graphite layer 106, in the graphite layer 106 of the substrate Department 103 of the opposite direction are successively stacked on one surface of the adhesive layer 107 and a protecting film 108 of the semiconductor package of chip-on-film in the manufacturing process of one example of the membrane section.

The invention in one embodiment, the protective film layer 108 can be stacked in the graphite layer 106 of the printed circuit board layer 202 of substrate Department 103 of on one side in the opposite direction.

Figure 11 is the diagram of showing the printed circuit board layer 202 of substrate Department 103 direction are stacked on one side of the adhesive layer 104, the protective film layer 105, in the protective film layer 105 of the substrate Department 103 direction is laminated on one surface of the graphite layer 106 of the chip-on-film semiconductor package manufacturing process of the film in the one example of the profile.

Figure 1 is the diagram of shown Figure 7 of the printed circuit board layer 202 of substrate Department 103 direction is laminated on one surface of the graphite layer 106 in the film, in the printed circuit board layer 202 of the circuit pattern layer 102 is arranged on one surface in the direction of the direction mount device 109, and in the gap filler 110 after the, stacked integrated circuit chip 101 of the chip-on-film semiconductor package with the cross section of an example.

Figure 12 is the chart of Figure 8 of the printed circuit board layer 202 of substrate Department 103 direction on one surface of the adhesive layer are sequentially laminated 104 and graphite layer 106 in the film, in the printed circuit board layer 202 of the circuit pattern layer 102 is arranged on one surface in the direction of the direction mount device 109, and in the gap filler 110 after the, stacked integrated circuit chip 101 of the chip-on-film semiconductor package with the cross section of an example.

Figure 13 is the graph of Figure 9 of the printed circuit board layer 202 of substrate Department 103 direction on one side of the laminated graphite layer 106 in the film, in the printed circuit board layer 202 of the circuit pattern layer 102 is arranged on one surface in the direction of the direction mount device 109, and in the gap filler 110 after the, stacked integrated circuit chip 101 of the chip-on-film semiconductor package with the cross section of an example.

Figure 14 is the graph of shown Figure 10 of the printed circuit board layer 202 of substrate Department 103 direction are laminated on one surface of the adhesive layer 104 and the graphite layer 106, the graphite layer 106 of the substrate Department 103 of the opposite direction are successively stacked on one surface of the adhesive layer 107 and a protecting film 108 in the film, in the printed circuit board layer 202 of the circuit pattern layer 102 is arranged on one surface in the direction of the direction mount device 109, and in the gap filler 110 after the, stacked integrated circuit chip 101 of the chip-on-film semiconductor package with the cross section of an example.

The invention in one embodiment, the protective film layer 108 can be stacked in the graphite layer 106 of the printed circuit board layer 202 of substrate Department 103 of on one side in the opposite direction.

Figure 15 is the chart of shown Figure 11 of the printed circuit board layer 202 of substrate Department 103 direction are stacked on one side of the adhesive layer 104, the protective film layer 105, the protective film layer 105 of the substrate Department 103 direction is laminated on one surface of the graphite layer 106 in the film, in the printed circuit board layer 202 of the circuit pattern layer 102 is arranged on one surface in the direction of the direction mount device 109, and in the gap filler 110 after the, stacked integrated circuit chip 101 of the chip-on-film semiconductor package with the cross section of an example.

The invention in one embodiment, the printed circuit board layer 202 on one side can also include external lead wire linkage pad (Outer Lead Bonder pad) 204.

The external lead wire linkage pad 204 as long as it is electrically connected with the printed circuit board layer 202 of the circuit and the display panel, then do not attempt to limit, the external lead wire linkage pad can be made of gold, copper, nickel or a combination thereof.

The invention in one embodiment, the external lead wire linkage pad 204 can be perpendicular to the length direction of the integrated circuit is arranged in the direction.

Figure 16 is the plan view of the printed circuit board layer 202 on one side directly or through the mount device 109 is connected with the integrated circuit chip 101 and the outer lead linkage pad 204 in order to perpendicular to the length direction of the integrated circuit is arranged in the direction of the chip-on-film in the direction of the upper part of the semiconductor package.

The invention in one embodiment, the graphite layer 106 can be laminated in the apart from which is provided with said external lead wire linkage pad of the printed circuit board layer 202 of the area of the area of the opposite side of the upper. This structure of the semiconductor package for chip-on-film, improves the arranged on a printed circuit board layer 202 is formed on a linkage pad 204 in the laminated graphite layer 203 in the direction of the visual appearance, thus in the graphite layer 203 direction can also be confirmed by the naked eye of the outer line linkage pad 204, thereby improving the visual appearance, and the external lead wire bonding technology (Outer Lead Bonding process, OLB process) when the accuracy of the improved adhesion and bonding strength.

The invention in one embodiment, the graphite layer 106 can be composed of two or more separated and laminated. At this moment, in the graphite layer 203 also distinguish the direction of the individual units of the integrated circuit chip area, thus the outer lead bonding process (Outer Lead Bondig process, OLB process) when the accuracy of the improved adhesion and bonding strength.

Figure 17 is the floorplan of the external lead wire linkage pad 204 to the integrated circuit chip 101 in a direction perpendicular to the direction of the length of the set, the graphite layer 106 is provided in addition to the external lead wire linkage pad of the printed circuit board layer 202 of the area of the area of the plane on the opposite, by two or more separated and laminated on a film chip type semiconductor package of the lower part of the graphite layer of the laminated direction.

Figure 18 is the plan view of the printed circuit board layer 202 of the graphite by more than two separated and laminated on one surface of the directly or through the mount device 109 is connected with the integrated circuit chip 101 and the outer lead linkage pad 204 to the integrated circuit is arranged in the direction perpendicular to the length direction of the chip-on-film in the direction of the upper part of the semiconductor package.

The invention in one embodiment, the integrated circuit chip 101 can be with the printed circuit board layer 202 in a direction perpendicular to the direction of the length of the set.

The invention in one embodiment, the printed circuit board layer 202 and the graphite layer 106 are respectively in the form of film winding under the state, the two surface is two roller 301 pressure, and can be adopted for the roll (roll to roll)/(reel to reel) process to carry out the lamination 1st. At this time, the pressure of the roll can be 3 - 3 kg. And, in the graphite layer 106 on one side of the, carrier film (carrier film) can be through the web to supply and laminated, the laminated film can be 1st to the printed circuit board layer 202/graphite layer 106/bearing layer (not shown) or printed circuit board layer 202/adhesive layer 104/graphite layer 106/bearing layer (not shown) of the stacked in sequence.

The invention in one embodiment, the 1st lamination film layer and the adhesive layer 104, 107 are respectively in the shape of the winding by membrane under the state, the two surface is two roller 301 pressure, and can be adopted for the roll (roll to roll)/(reel to reel) 2nd process to carry out the lamination. At this time, the pressure of the roll can be 3 - 20 kg. And, in the graphite layer 106 on one side, release film (release film) can be through the web to supply and laminated, 2nd lamination film can be printed circuit board layer 202/adhesive layer 104/graphite layer 106/adhesive layer 107/release film layer (not shown) or printed circuit board layer 202/adhesive layer 107/graphite layer 106/release film layer (not shown) of the stacked in sequence.

The invention in one embodiment, the 2nd time laminated film and a protecting film 105, 108 are respectively in the form of film winding under the state, the two surface is two roller 301 pressure, and can be adopted for the roll (roll to roll)/(reel to reel) 2nd process to carry out the lamination. At this time, the pressure of the roll can be 3 - 20 kg, the temperature of the roll can be 70 - 90 °C. And, the laminated film can be 3rd printed circuit board layer 202/adhesive layer 104/graphite layer 106/adhesive layer 107/protective film layer 108 or the printed circuit board layer 202/adhesive layer 107/graphite layer 106/protective film layer 108 of the stacked in sequence.

Below, which includes the membrane on the chip type semiconductor package, the base plate and a display panel of the display device a description of the.

The invention in one embodiment, the base plate can be with said chip-on-semiconductor package of the external lead wire linkage pad 204 is electrically connected.

The invention in one embodiment, the base plate also includes the external lead wire linkage pad (not shown), and can be connected with the membrane on chip type semiconductor package external lead wire linkage pad 204 is electrically connected.

The invention in one embodiment, the base plate also includes the external lead wire linkage pad (not shown), and may be combined with the membrane on chip type semiconductor package external lead wire linkage pad 204 is electrically connected. At this time, the lead-in of the substrate linkage pad (not shown) and the chip-on-film semiconductor package external lead wire linkage pad 204 also may be included between the anisotropic conductive adhesive film (Anisotropic Conductive Film, ACF) layer. The base plate of the outer line linkage pad (not shown)/the anisotropic conductive film of the chip-on-film/semiconductor package of the external lead wire linkage pad 204 can be sequentially arranged through the outer lead bonding process after (OLB process) laminated.

The invention in one embodiment, the display panel can be a liquid crystal display or a light emitting element display, the structure of the module may include a commonly used display panel module.

The chip-on-film semiconductor package with the base plate and the display panel is electrically connected with, can be according to the driving signal of the integrated circuit chip, and the electric signal drives and controls the corresponding pixel of the display panel.

The above description should be understood as an example of a preferred embodiment, rather than limiting the scope of this invention. Therefore the invention should be determined by the claims and equivalent of the claims rather than by the determined above to determine the content of the narratives.

The Figure mark note

101: Drive integrated circuit chip

102: Printed circuit layer of the circuit pattern layer

103: Printed circuit layer of the substrate layer

104. 107: Adhesive layer

105. 108: Protective film layer

106: Graphite layer

109: Used for connecting electrically the driving integrated circuit chip and a printed circuit film projection

110: Filler

202: Printed circuit film

301: Roller

302: Graphite powder

401: Graphite