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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Форма поиска

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Применить Всего найдено 168120. Отображено 100.
05-01-2012 дата публикации

Double molded chip scale package

Номер: US20120001322A1
Автор: Luke England, Yong Liu
Принадлежит: Fairchild Semiconductor Corp

Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure. With such a configuration, the second molding layer helps control warpage during the manufacturing process and no printed circuit board (PCB) substrate is needed when the package is used in an electronic device since the signal routing is performed by the second interconnect structure. Other embodiments are described.

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Номер записи: 1
05-01-2012 дата публикации

Semiconductor device

Номер: US20120001341A1
Автор: Akihiro Niimi, Shigeo Ide
Принадлежит: Denso Corp

The semiconductor device has a unit stack body including a plurality of units stacked on one another. Each unit includes a power terminal constituted of a lead part and a connection part. The connection part is formed with a projection and a recess. When the units are stacked on one another, the projection of one unit is fitted to the recess of the adjacent unit, so that the power terminals of the respective unit are connected to one another.

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Номер записи: 2
05-01-2012 дата публикации

Driving circuit and liquid crystal display device including the same

Номер: US20120002146A1
Автор: Jin-Cheol Hong, Min-Hwa Kim
Принадлежит: Individual

A tape carrier package (TCP) includes a film, a plurality of output leads and a plurality of input leads on the film, the plurality of output leads and the plurality of input leads being disposed on different sides, first and second TCP alignment marks arranged on opposing sides of the plurality of output leads, and a third TCP alignment mark at a central portion of the plurality of output leads.

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Номер записи: 3
11-07-2017 дата публикации

Выводная рамка мощной интегральной микросхемы

Номер: RU0000172495U1
Автор: Александр Владимирович Минин, Евгений Викторович Абашин, Константин Львович Афанасьев, Николай Александрович Брюхно
Принадлежит: Закрытое акционерное общество "ГРУППА КРЕМНИЙ ЭЛ"

Использование: для создания выводных рамок мощных интегральных схем. Сущность полезной модели заключается в том, что выводная рамка мощной интегральной микросхемы содержит теплорастекатель с участком присоединения кристалла с рифлением, и траверсы для присоединения гибких выводов, рифление теплорастекателя выполено виде сетки из канавок, расположенных в двух взаимоперпендикулярных направлениях с шагомпричем:где- наибольший диаметр гибкого вывода, соединяющий контактную площадку с теплорастекателем,наименьший линейный размер кристалла. Технический результат: обеспечение возможности повышения качества мощной микросхемы. 2 ил. Ц 1 172495 ко РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ 27; 22, 7 р», 77 8? аа) ил < < $ >< оо п РЦ ‘’ (50) МПК НО. 23/495 (2006.01) (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (21)(22) Заявка: 2017109009, 17.03.2017 (24) Дата начала отсчета срока действия патента: 17.03.2017 Дата регистрации: 11.07.2017 Приоритет(ы): (22) Дата подачи заявки: 17.03.2017 (45) Опубликовано: 11.07.2017 Бюл. № 20 Адрес для переписки: 241037, г. Брянск, ул. Красноармейская, 103, ЗАО "ГРУППА КРЕМНИЙ ЭЛ", Технический отдел (72) Автор(ы): Абашин Евгений Викторович (КО), Афанасьев Константин Львович (КО), Брюхно Николай Александрович (КО), Минин Александр Владимирович (КО) (73) Патентообладатель(и): Закрытое акционерное общество "ГРУ1ИТА КРЕМНИЙ ЭЛ" (ВО) (56) Список документов, цитированных в отчете о поиске: ВО 2040075 С1, 20.07.1995. ВЧ 2222074 СТ, 20.01.2004. ВО 2193260 СТ, 20.11.2002. 05 5299091 АТ, 29.03.1994. 05 5633528 А1, 27.05.1997 . (54) ВЫВОДНАЯ РАМКА МОЩНОЙ ИНТЕГРАЛЬНОЙ МИКРОСХЕМЫ (57) Реферат: Использование: для создания выводных рамок мощных интегральных схем. Сущность полезной модели заключается в том, что выводная рамка мощной интегральной микросхемы содержит теплорастекатель с участком присоединения кристалла с рифлением, и траверсы для присоединения гибких выводов, рифление теплорастекателя выполено виде сетки из канавок, ...

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Номер записи: 4
21-05-2018 дата публикации

Устройство для формовки и обрезки выводов микросхем

Номер: RU0000179618U1
Автор: Владислав Алексеевич Трегубов, Елена Владимировна Короткова, Иван Иванович Зайченко
Принадлежит: Акционерное общество &#34;Научно-исследовательский институт Приборостроения имени В.В. Тихомирова&#34;

Полезная модель относится к радиоэлектронике, в частности к средствам подготовки интегральных микросхем к монтажу, а именно для формовки и обрезки их выводов. Технической проблемой, решаемой предлагаемой полезной моделью, является создание приспособления для формовки и обрезки выводов, расположенных в два ряда по стороне корпуса (корпуса типа 4229.132-3 микросхем 1986 ВЕ91Т и др.). Технический результат предлагаемой полезной модели заключается в предотвращении деформации и разрушения выводов микросхем, расположенных в два ряда по стороне ее корпуса, в результате чрезмерного давления на них в процессе формовки и обрезки. Для достижения указанного технического результата устройство выполнено следующим образом. Устройство содержит основание (1), на котором закреплен матрицедержатель (2). В матрицедержатель (2) установлены направляющие колонки (13) и матрица (3), в которой выполнено углубление (4) для размещения микросхемы (14). Верхняя плита (12) подвижно установлена на направляющие колонки (13). К верхней плите (12) прикреплен держатель (11), в котором жестко закреплен пуансон обрезки (7). В пуансоне обрезки (7) установлен по скользящей посадке формовочный пуансон (6). В формовочный пуансон (6) подвижно установлен прижим (5). Прижим (5) и формовочный пуансон (6) выступают из пуансона обрезки (7). Боковые стороны прижима (5) выполнены ступенчатыми. На верхней стороне прижима (5) в формовочном пуансоне (6) расположен первый буфер (8). Первый буфер (8) закреплен крышкой (9), которая жестко установлена в формовочном пуансоне (6). На крышке (9) расположен второй буфер (10), более твердый, чем первый. Кроме того, на боковых сторонах матрицы (3) выполнены ступеньки (16), таким образом, что при формовке они устанавливаются между ступеньками прижима (5). 2 з.п.4 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 179 618 U1 (51) МПК H05K 13/00 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК H01L 21/4842 (2006.01); H01L 23/ ...

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Номер записи: 5
21-03-2019 дата публикации

Затравочный слой медной металлизации интегральных схем

Номер: RU0000187908U1
Автор: Алина Юрьевна Фроликова, Евгений Александрович Чирков, Евгений Викторович Абашин, Николай Александрович Брюхно
Принадлежит: Закрытое акционерное общество &#34;ГРУППА КРЕМНИЙ ЭЛ&#34;

Областью применения данной полезной модели является микроэлектроника, а именно - конструкции современных интегральных схем с применением силовой металлизации на основе меди. Техническим результатом данной полезной модели является повышение качества толстого слоя медной металлизации. Указанный технический результат достигается тем, что в отличие от известного затравочного слоя медной металлизации, состоящего из адгезионного слоя, затравочного слоя из меди, в предлагаемом затравочный слой меди дополнительно покрыт защитным слоем из ванадия, толщиной 10-20 нм. 4 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 187 908 U1 (51) МПК H01L 23/48 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК H01L 23/48 (2018.08) (21)(22) Заявка: 2018146672, 25.12.2018 (24) Дата начала отсчета срока действия патента: Дата регистрации: 21.03.2019 (56) Список документов, цитированных в отчете о поиске: RU 163838 U1, 10.08.2016. RU (45) Опубликовано: 21.03.2019 Бюл. № 9 (54) ЗАТРАВОЧНЫЙ СЛОЙ МЕДНОЙ МЕТАЛЛИЗАЦИИ ИНТЕГРАЛЬНЫХ СХЕМ (57) Реферат: Областью применения данной полезной технический результат достигается тем, что в модели является микроэлектроника, а именно отличие от известного затравочного слоя медной конструкции современных интегральных схем с металлизации, состоящего из адгезионного слоя, применением силовой металлизации на основе затравочного слоя из меди, в предлагаемом меди. Техническим результатом данной полезной затравочный слой меди дополнительно покрыт модели является повышение качества толстого защитным слоем из ванадия, толщиной 10-20 нм. слоя медной металлизации. Указанный 4 ил. R U 1 8 7 9 0 8 2420827 C1, 10.06.2011. RU 161515 U1, 20.04.2016. EP 1849885 A1, 31.10.2007. Стр.: 1 U 1 U 1 Адрес для переписки: 241037, г. Брянск, ул. Красноармейская, 103, ЗАО "ГРУППА КРЕМНИЙ ЭЛ", Технический отдел 1 8 7 9 0 8 (73) Патентообладатель(и): Закрытое акционерное общество "ГРУППА КРЕМНИЙ ЭЛ" (RU) Приоритет(ы): (22) Дата подачи ...

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Номер записи: 6
13-05-2019 дата публикации

Металлокерамический корпус

Номер: RU0000189084U1
Автор: Алексей Викторович Горьков, Вячеслав Сергеевич Серегин, Елена Сергеевна Пилавова, Лариса Владимировна Пилавова, Николай Александрович Нагаев, Петр Иванович Козлов, Шамиль Наильевич Шугаепов
Принадлежит: Акционерное общество &#34;НПО &#34;НИИТАЛ&#34;

Данная полезная модель относится к области электронной техники и может быть использована при разработке корпусов силовых полупроводниковых приборов. Металлокерамический корпус представляет собой конструкцию, состоящую из керамического основания 1, с монтажными окнами 2 и 3 для припайки кристаллодержателя 4 и силовых выводов 5, а также ободка 6 и крышки 7. Во внутренней полости корпуса, по обе стороны окна 2, расположены контакты 8 управляющих выводов, а на тыльной стороне корпуса - выводные контакты 9, которые могут быть выполнены в виде накладок 10, мини столбиков 11 или балочного типа 12. Предложенные металлокерамические корпуса расширяют возможности применения данных типов корпусов для силовых полупроводниковых приборов и отличаются более равномерным распределением тепловой нагрузки, а также упрощенным монтажом приборов на коммутационную плату 2 з.п. ф-лы, 7 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 189 084 U1 (51) МПК H01L 23/48 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК H01L 23/48 (2019.02) (21) (22) Заявка: 2018146018, 25.12.2018 (24) Дата начала отсчета срока действия патента: 25.12.2018 13.05.2019 (45) Опубликовано: 13.05.2019 Бюл. № 14 1 8 9 0 8 4 R U (54) МЕТАЛЛОКЕРАМИЧЕСКИЙ КОРПУС (57) Реферат: Данная полезная модель относится к области электронной техники и может быть использована при разработке корпусов силовых полупроводниковых приборов. Металлокерамический корпус представляет собой конструкцию, состоящую из керамического основания 1, с монтажными окнами 2 и 3 для припайки кристаллодержателя 4 и силовых выводов 5, а также ободка 6 и крышки 7. Во внутренней полости корпуса, по обе стороны окна 2, расположены контакты 8 управляющих Стр.: 1 (56) Список документов, цитированных в отчете о поиске: RU 161815 U1, 10.05.2016. SU 1746438 A1, 07.07.1992. RU 2016121698 A, 06.12.2017. US 20060180925 A1, 17.08.2006. US 7498610 B2, 03.03.2009. выводов, а на тыльной стороне корпуса выводные ...

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Номер записи: 7
12-01-2012 дата публикации

Nanofluids for Thermal Management Systems

Номер: US20120006509A1
Автор: Andrew M. Hayes, Dale A. McCants
Принадлежит: UNIVERSITY OF SOUTH CAROLINA

A nanofluid is generally provided for use in a heat transfer system. The nanofluid can include nanoparticles suspended in a base liquid at a nanoparticle concentration in the nanofluid of about 0.01% to about 5% by volume. The nanoparticles can include zinc-oxide nanoparticles. The nanofluid for use in a heat transfer system can, in one embodiment, further include a surfactant. Thermal management systems configured to cool a computer having integrated circuits that generate heat during use are also provided. The thermal management system can include a zinc-oxide nanofluid circulated through a series of tubes via a pump such that heat produced by electronic components of the computer can be captured by the circulating nanofluid and then removed from the nanofluid by a radiator.

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Номер записи: 8
12-01-2012 дата публикации

Wiring board and method for manufacturing the same

Номер: US20120006592A1
Автор: Makoto Terui, Shigeru Yamada, Shinji OUCHI, Yoshinori Shizuno
Принадлежит: Ibiden Co Ltd

A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

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Номер записи: 9
29-09-2021 дата публикации

Устройство для отвода тепла

Номер: RU0000206828U1
Автор: Анатолий Николаевич Копейкин, Иван Иванович Зайченко, Константин Вадимович Мазикин, Рудольф Константинович Денисов
Принадлежит: Акционерное общество &#34;Научно-исследовательский институт Приборостроения имени В.В. Тихомирова&#34;

Полезная модель относится к радиоэлектронике и предназначена для отвода тепла от теплонагруженных элементов электронной аппаратуры. Технический результат - повышение эффективности охлаждения теплонагруженных элементов. Достигается тем, что корпус выполнен разъемным с крышкой, имеющей охлаждающие ребра, плата закреплена на корпусе. Упругий узел с ограничительными пластинами выполнен составным, в виде двух фигурных частей, причем одна из фигурных частей неподвижно закреплена на внутренней стороне крышки корпуса, а вторая подвижная, имеющая упоры, прилегает к теплонагруженному элементу на плате. В полость, образованную фигурными частями упругого узла, установлены подпружиненные клиновидные элементы с дополнительными упорами и фиксатор. Дополнительные упоры выполнены в виде подпружиненных шариков, установленных в отверстия подвижной части упругого узла. Упоры выполнены в виде подпружиненных шариков, установленных в отверстие каждого клиновидного элемента. Фиксатор закреплен между клиновидными элементами и выполнен имеющим с обеих продольных сторон несквозные прямоугольные отверстия для установки пружин. 4 з.п. ф-лы, 4 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 206 828 U1 (51) МПК G12B 15/06 (2006.01) H05K 7/20 (2006.01) H01L 23/433 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК H05K 7/2049 (2021.08); H01L 23/4338 (2021.08) (21)(22) Заявка: 2021114006, 17.05.2021 (24) Дата начала отсчета срока действия патента: Дата регистрации: 29.09.2021 (45) Опубликовано: 29.09.2021 Бюл. № 28 2 0 6 8 2 8 R U (54) Устройство для отвода тепла (57) Реферат: Полезная модель относится к радиоэлектронике и предназначена для отвода тепла от теплонагруженных элементов электронной аппаратуры. Технический результат - повышение эффективности охлаждения теплонагруженных элементов. Достигается тем, что корпус выполнен разъемным с крышкой, имеющей охлаждающие ребра, плата закреплена на корпусе. Упругий узел с ограничительными ...

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Номер записи: 10
12-01-2012 дата публикации

Heat dissipating material and semiconductor device using same

Номер: US20120007017A1
Автор: Chisato Hoshino, Shingo Tabei
Принадлежит: MOMENTIVE PERFORMANCE MATERIALS JAPAN LLC

Disclosed is a heat dissipating material which is interposed between a heat-generating electronic component and a heat dissipating body. This heat dissipating material contains (A) 100 parts by weight of a silicone gel cured by an addition reaction having a penetration of not less than 100 (according to ASTM D 1403), and (B) 500-2000 parts by weight of a heat conductive filler. Also disclosed is a semiconductor device comprising a heat-generating electronic component and a heat dissipating body, wherein the heat dissipating material is interposed between the heat-generating electronic component and the heat dissipating body.

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Номер записи: 11
12-01-2012 дата публикации

Semiconductor device structures including damascene trenches with conductive structures and related method

Номер: US20120007209A1
Автор: Howard E. Rhodes
Принадлежит: Micron Technology Inc

A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an insulation layer with at least one damascene conductive structure formed therein, wherein the at least one damascene conductive structure includes an insulative, protective layer disposed thereon. The insulative material of the protective layer is able to resist removal by at least some suitable etchants for the insulative material of the insulation layer adjacent to the at least one damascene conductive structure. A self-aligned opening is formed by removing a portion of an insulation layer adjacent the at least one damascene conductive structure. The self-aligned opening is then filled with a conductive material to thereby provide another conductive structure adjacent to the at least one damascene conductive structure.

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Номер записи: 12
12-01-2012 дата публикации

Semiconductor device

Номер: US20120007224A1
Автор: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
Принадлежит: Hitachi Hokkai Semiconductor Ltd, Renesas Electronics Corp

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

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Номер записи: 13
12-01-2012 дата публикации

Microelectronic packages with dual or multiple-etched flip-chip connectors

Номер: US20120007232A1
Автор: Belgacem Haba
Принадлежит: TESSERA RESEARCH LLC

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

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Номер записи: 14
12-01-2012 дата публикации

Semiconductor device and package

Номер: US20120007236A1
Автор: Jin Ho Bae
Принадлежит: Hynix Semiconductor Inc

A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate.

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Номер записи: 15
12-01-2012 дата публикации

Resin-Encapsulated Semiconductor Device

Номер: US20120007247A1
Автор: Motoharu Haga, Shoji Yasunaga, Yasumasa Kasuya
Принадлежит: ROHM CO LTD

A resin-sealed semiconductor device includes a semiconductor chip including a silicon substrate; a die pad on which the semiconductor chip is secured via a solder layer; a sealing resin layer sealing the semiconductor chip; and lead terminals connected electrically with the semiconductor chip. One end portion of the lead terminals is covered by the sealing resin layer. The die pad and the lead terminals are formed of copper and a copper alloy, and the die pad is formed with a thickness larger than a thickness of the lead terminals, which is a thickness of 0.25 mm or more.

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Номер записи: 16
19-01-2012 дата публикации

Methods of forming semiconductor chip underfill anchors

Номер: US20120012987A1
Автор: Neil McLellan, Roden R. Topacio
Принадлежит: Individual

Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.

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Номер записи: 17
19-01-2012 дата публикации

Conductive Sidewall for Microbumps

Номер: US20120012998A1
Автор: Arvind Chandrasekaran, Christine S. Hay-Riege, Shiqun Gu
Принадлежит: Qualcomm Inc

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

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Номер записи: 18
26-01-2012 дата публикации

Thermal siphon structure

Номер: US20120018130A1
Автор: Kuei-feng Chiang, Shyy-Woei Chang
Принадлежит: Asia Vital Components Co Ltd

A thermal siphon structure includes a main body, a chamber disposed therein, an evaporation section, a condensation section and a connection section positioned between the evaporation section and condensation section. The evaporation section and condensation section are respectively arranged in the chamber on two sides thereof. The connection section has a set of first communication holes and a set of second communication holes in communication with the evaporation section and condensation section. The evaporation section and condensation section respectively have multiple first and second flow guide bodies, which are arranged at intervals to define therebetween first and second flow ways. Each of the first and second flow ways has a narrower end and a wider end. The first flow ways communicate with a free area. The condensation section is designed with a low-pressure end to create a pressure gradient for driving a working fluid to circulate without any capillary structure.

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Номер записи: 19
26-01-2012 дата публикации

Heat-dissipating assembly

Номер: US20120018137A1
Автор: Kuei-feng Chiang, Shyy-Woei Chang
Принадлежит: Asia Vital Components Co Ltd

A heat-dissipating assembly includes a body and a bottom plate. The body has a heat-absorbing portion. The interior of the heat-absorbing portion is provided with a chamber covered by the bottom plate. The chamber has an evaporating region for generating a high pressure, and a condensing region for generating a low pressure. The pressure gradient between the evaporating region and the condensing region is used to drive the circulation of liquid/vapor phase of a working fluid. With this structure, heat can be conducted rapidly without providing any wick structure.

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Номер записи: 20
26-01-2012 дата публикации

Ceramic electronic component and wiring board

Номер: US20120018204A1
Автор: Koji Sato, Yasuhiro Nishisaka, Yukio Sanada
Принадлежит: Murata Manufacturing Co Ltd

A ceramic electronic component includes a ceramic element body having a substantially rectangular parallelepiped shape, and first and second external electrodes. The first and second external electrodes are provided on a first principal surface. Portions of the first and second external electrodes project further than the other portions in a thickness direction. A projecting portion of the first external electrode is provided at one end of the first external electrode in a length direction and a second projecting portion of the second external electrode is provided at another end of the second external electrode in the length direction. Thus, a concave portion is provided between the projecting portions, and a portion of the first principal surface provided between the first and second external electrodes is exposed.

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Номер записи: 21
26-01-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120018742A1
Автор: Masahiro Nishi
Принадлежит: Sumitomo Electric Device Innovations Inc

A semiconductor device includes a SiC substrate, a semiconductor layer formed on the SiC substrate, a via hole penetrating through the SiC substrate and the semiconductor layer, a Cu pad that is formed on the semiconductor layer and is in contact with the via hole, and a barrier layer covering an upper face and side faces of the Cu pad, and restrains Cu diffusion.

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Номер записи: 22
26-01-2012 дата публикации

Substrate for semiconductor element, method for manufacturing substrate for semiconductor element, and semiconductor device

Номер: US20120018867A1
Автор: Junko Toda, Susumu Maniwa, Takehito Tsukamoto
Принадлежит: Toppan Printing Co Ltd

Provided is a manufacturing method of a semiconductor element substrate including: a step of forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; a step of forming a second photoresist pattern on the second surface of the metallic plate; a step of forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; a step of forming a plurality of concaved parts on the second surface of the metallic plate; a step of forming a resin layer by injecting a resin to the plurality of concaved parts; and a step of etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.

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Номер записи: 23
26-01-2012 дата публикации

Methods of forming semiconductor elements using micro-abrasive particle stream

Номер: US20120018893A1
Автор: Belgacem Haba, Craig Mitchell, Ilyas Mohammed, Piyush Savalia, Vage Oganesian
Принадлежит: TESSERA RESEARCH LLC

A method of fabricating a microelectronic unit includes providing a semiconductor element having a front surface and a rear surface remote from the front surface, forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface by directing a jet of fine abrasive particles towards the semiconductor element, and forming at least one conductive contact and at least one conductive interconnect coupled thereto. The semiconductor element can include a plurality of active semiconductor devices therein. The semiconductor element can include a plurality of conductive pads exposed at the front surface. Each conductive interconnect can extend within one or more of the first openings and can be coupled directly or indirectly to at least one of the conductive pads. Each of the conductive contacts can be exposed at the rear surface of the semiconductor element for electrical connection to an external device.

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Номер записи: 24
26-01-2012 дата публикации

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

Номер: US20120018904A1
Автор: Jianmin Fang, KANG Chen, Xia Feng, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

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Номер записи: 25
26-01-2012 дата публикации

Electronic module with vertical connector between conductor patterns

Номер: US20120020044A1
Автор: Antti Iihola, Petteri Palm
Принадлежит: IMBERA ELECTRONICS OY

The present invention generally relates to a new structure to be used with electronic modules such as printed circuit boards and semiconductor package substrates. Furthermore there are presented herein methods for manufacturing the same. According to an aspect of the invention, the aspect ratio of through holes is significantly improved. Aspect ratio measures a relationship of a through hole or a micro via conductor in the direction of height divided width. According to the aspect of the invention, the aspect ratio can be increased over that of the prior art solution by a factor of ten or more.

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Номер записи: 26
26-01-2012 дата публикации

Method of fabricating film circuit substrate and method of fabricating chip package including the same

Номер: US20120021600A1
Автор: Dae-Woo Son, Jeong-kyu Ha, Kwan-Jai Lee, Sang-uk Han, Ye-Chung Chung, Yun-young Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of fabricating a film circuit substrate and a method of fabricating a chip package. The method of fabricating a film circuit substrate can include providing a base film including a chip packaging area to package a chip and a separation area to separate the two chip packaging areas from each other, the separation area including a cut area and an uncut area; forming a reserve interconnection pattern having a first height on the base film; and forming an interconnection pattern having a second height that is lower than the first height on the out area by selectively etching the reserve interconnection pattern of the cut area.

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Номер записи: 27
02-02-2012 дата публикации

Semiconductor device and semiconductor package including the same

Номер: US20120025349A1
Автор: Hyun-seok Kim, Hyung-Dong Lee, Jun-Ho Lee
Принадлежит: Individual

Provided is a semiconductor device capable of removing a power ground grid noise using a small area. The semiconductor device includes a first chip including at least one decoupling capacitor; and a second semiconductor chip stacked over the first semiconductor chip, including internal circuits.

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Номер записи: 28
02-02-2012 дата публикации

Leadframe for ic package and method of manufacture

Номер: US20120025357A1
Автор: Tunglok Li
Принадлежит: Kaixin Inc

A leadframe for use in an integrated circuit (IC) package comprising a metal strip partially etched on a first side. In some embodiments, the leadframe may be selectively plated on the first side and/or on a second side. The leadframe may be configured for an IC chip to be mounted thereon and for a plurality of electrical contacts to be electrically coupled to the leadframe and the IC chip.

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Номер записи: 29
02-02-2012 дата публикации

Semiconductor device

Номер: US20120025367A1
Автор: Akio Katsumata, Goshi Kawazu, Isao Kudo, Yoichi Hiruta, Yukari Imaizumi
Принадлежит: J Devices Corp, Toshiba Corp

A semiconductor device which includes a substrate, a semiconductor element arranged on the substrate, a heat dissipation component arranged on the semiconductor element, and a mold component covering an upper part of the substrate, the semiconductor element and the heat dissipation component, wherein an area of a surface on the semiconductor element of the heat dissipation component is larger than an area of a surface on which the heat dissipation component of the semiconductor element is arranged.

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Номер записи: 30
02-02-2012 дата публикации

Semiconductor device and method of designing a wiring of a semiconductor device

Номер: US20120025377A1
Автор: Hideaki Ikuma, Shoji Seta, Yukihito Oowaki
Принадлежит: Toshiba Corp

A semiconductor device has an LSI chip including a semiconductor substrate, an LSI core section provided at a center portion of the semiconductor substrate and serving as a multilayered wiring layer of the semiconductor substrate, a first rewiring layer provided adjacent to an outer periphery of the LSI core section on the semiconductor substrate and including a plurality of wiring layers, a first pad electrode disposed at an outer periphery of the first rewiring layer, and an insulation layer covering the first pad electrode. The semiconductor device includes a second rewiring layer provided on the LSI chip and including a rewiring connected to the first pad electrode. The semiconductor device includes a plurality of ball electrodes provided on the second rewiring layer. The first rewiring layer is electrically connected to the LSI core section and the first pad electrode.

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Номер записи: 31
02-02-2012 дата публикации

Chip package and fabricating method thereof

Номер: US20120025387A1
Автор: Kuo-Ching Chang, Tzu-Han Lin, Wu-Cheng Kuo
Принадлежит: Individual

A chip package and a fabrication method thereof are provided. The chip package includes a substrate and a chip disposed over the substrate. A solder layer is disposed between the chip and the substrate. A conductive pad is disposed between the solder layer and the substrate, wherein the conductive pad includes a first portion disposed under the solder layer, a second portion disposed away from the first portion and a connective portion disposed between the first portion and the second portion. The connective portion has a width which is narrower than a width of the first portion along a first direction perpendicular to a second direction extending from the first portion to the connective portion.

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Номер записи: 32
02-02-2012 дата публикации

Electronics substrate with enhanced direct bonded metal

Номер: US20120026692A1
Автор: Donald Lynn Smith, Sy-Jenq Loong
Принадлежит: Wolverine Tube Inc

A substrate for electronic components includes a ceramic tile and a cooling metal layer. The cooling metal layer can include copper, aluminum, nickel, gold, or other metals. The cooling metal layer has an enhanced surface facing away from the ceramic tile, where the enhanced surface includes either fins or pins. Electronic components can be connected to the substrate on a surface opposite the cooling metal layer.

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Номер записи: 33
02-02-2012 дата публикации

Methods of operating electronic devices, and methods of providing electronic devices

Номер: US20120028582A1
Автор: Patrick W. Tandy
Принадлежит: Round Rock Research LLC

Some embodiments include a method disposing an integrated circuit die within a housing, the integrated circuit die having integrated circuitry formed thereon, the integrated circuitry including first transponder circuitry configured to transmit and receive radio frequency signals, wherein the integrated circuit die is void of external electrical connections for anything except power supply external connections; and disposing second transponder circuitry, discrete from the first transponder circuitry, within the housing, the second transponder circuitry being configured to transmit and receive radio frequency signals, wherein the first and second transponder circuitry are configured to establish wireless communication between one another within the housing, the second transponder circuitry being disposed within 24 inches of the first transponder circuitry within the housing.

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Номер записи: 34
09-02-2012 дата публикации

Multi-Layer Circuit Assembly And Process For Preparing The Same

Номер: US20120031655A1
Автор: Alan G. Wang, Kevin C. Olson
Принадлежит: PPG Industries Ohio Inc

A process for fabricating a multi-layer circuit assembly is provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; (c) removing the dielectric coating in a predetermined pattern to expose sections of the substrate; (d) applying a layer of metal to all surfaces to form metallized vias through and/or to the electrically conductive core; (e) applying a resist to the metal layer to form a photosensitive layer thereon; (f) imaging resist in predetermined locations; (g) developing resist to uncover selected areas of the metal layer; and (h) etching uncovered areas of metal to form an electrical circuit pattern connected by the metallized vias.

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Номер записи: 35
09-02-2012 дата публикации

Metal semiconductor alloy structure for low contact resistance

Номер: US20120032275A1
Автор: Balasubramanian S. Haran, Sivananda K. Kanakasabapathy
Принадлежит: International Business Machines Corp

Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.

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Номер записи: 36
09-02-2012 дата публикации

Method for fabrication of a semiconductor device and structure

Номер: US20120032294A1
Автор: Brian Cronquist, Deepak C. Sekar, Israel Beinglass, Jan Lodewijk de Jong, Zvi Or-Bach
Принадлежит: Monolithic 3D Inc

A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.

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Номер записи: 37
09-02-2012 дата публикации

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

Номер: US20120032298A1
Автор: Hideki Fujii, Kenji Furuya, Yuichi Miyagawa
Принадлежит: Renesas Electronics Corp

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

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Номер записи: 38
09-02-2012 дата публикации

High-voltage packaged device

Номер: US20120032319A1
Автор: Richard A. Dunipace
Принадлежит: Individual

Packaged devices and methods for making and using the same are described. The packaged devices contain one or more circuit components, such as a die, that is attached to a leadframe having a first lead, a second lead, and a third lead (although, higher lead counts may be employed in some implementations). A portion of the circuit component and the leadframe are encapsulated in a molded housing so that the first lead is exposed from a first end of the housing while the second and third leads are exposed from a second end of the housing. In some configurations, the packaged device does not contain a fourth lead that is both electrically connected to the first lead and that is exposed from the second end of the molded housing. In other configurations, an area extending from the second lead to the third lead in the molded housing comprises an insulating material having a substantially uniform conductivity. Thus, the packaged devices have relatively large creepage and clearance distances between the first lead and the second and third leads. As a result, the packaged devices are able to operate at relatively high operating voltages without experiencing voltage breakdown. Other embodiments are described.

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Номер записи: 39
09-02-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120032323A1
Автор: Akihiro Osaki, Atsushi Ishii, Masahiko Fujisawa, Masahiro Matsumoto
Принадлежит: Renesas Electronics Corp

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

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Номер записи: 40
09-02-2012 дата публикации

Circuit substrate and manufacturing method thereof and package structure and manufacturing method thereof

Номер: US20120032331A1
Автор: Chih-Cheng LEE
Принадлежит: Advanced Semiconductor Engineering Inc

A circuit substrate includes the following elements. A conductive layer and a dielectric layer are disposed on an inner circuit structure in sequence, and a plurality of conductive blind vias are embedded in the dielectric layer and connected to a portion of the conductive layer. A plating seed layer is disposed between each of the first blind vias and the first conductive layer. Another conductive layer is disposed on the dielectric layer, wherein a portion of the another conductive layer is electrically connected to the conductive layer through the conductive blind vias. A third plating seed layer is disposed between the third conductive layer and each of the first blind vias and on the first dielectric layer.

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Номер записи: 41
09-02-2012 дата публикации

Systems and Methods for Heat Dissipation Using Thermal Conduits

Номер: US20120032350A1
Автор: Jianjun Li, Nic Rossi, Robert W. Warren
Принадлежит: Conexant Systems LLC

The addition of thermal conduits by bonding bond wires to bond pads either in a wire loop configuration or a pillar configuration can improve thermal dissipation of a fabricated die. The thermal conduits can be added as part of the normal packaging process of a semiconductor die and are electrically decoupled from the circuitry fabricated on the fabricated die. In an alternative, a dummy die is affixed to the fabricated die and the thermal conduits are affixed to the dummy die. Additionally, thermal conduits can be used in conjunction with a heat spreader.

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Номер записи: 42
09-02-2012 дата публикации

Energy Conditioning Circuit Arrangement for Integrated Circuit

Номер: US20120034774A1
Автор: Anthony A. Anthony, William M. Anthony
Принадлежит: X2Y Attenuators LLC

The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.

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Номер записи: 43
16-02-2012 дата публикации

Semiconductor device

Номер: US20120038033A1
Автор: Akira Oga, Masanori Minamio, YOSHIHIRO Tomita
Принадлежит: Panasonic Corp

A semiconductor device includes a first semiconductor chip 1 , a second semiconductor chip 4 , a first lead frame 3 including a first die pad 9 on which the first semiconductor chip 1 is mounted, and a second lead frame 5 including a second die pad 11 on which the second semiconductor chip 4 is mounted. A sealing structure 6 covers the first semiconductor chip 1 and the second semiconductor chip 4 . A noise shield 7 is disposed between the first semiconductor chip 1 and the second semiconductor chip 4.

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Номер записи: 44
16-02-2012 дата публикации

Structure for Multi-Row Leadframe and Semiconductor Package Thereof and Manufacture Method Thereof

Номер: US20120038036A1
Автор: Hyuk Soo Lee, Hyun A. Chun, Jae Bong Choi, Sai Ran Eom, Sung Won Lee, Sung Wuk Ryu
Принадлежит: LG Innotek Co Ltd

The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.

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Номер записи: 45
16-02-2012 дата публикации

Stitch bump stacking design for overall package size reduction for multiple stack

Номер: US20120038059A1
Автор: Foong Yue Ho, Kevin Guan, Koo Eng LUON, Lai Nguk Chin, Sally Foong, Wong Kwet Nam
Принадлежит: Individual

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

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Номер записи: 46
23-02-2012 дата публикации

Flexible circuit structure with stretchability and method of manufacturing the same

Номер: US20120043115A1
Автор: Ying-Ching Shih, Yu-Hua Chen
Принадлежит: Industrial Technology Research Institute ITRI

In one example embodiment, a flexible circuit structure with stretchability is provided that includes a flexible substrate, a plurality of flexible bumps formed on the flexible substrate, and a metal layer formed on the plurality of flexible bumps and the flexible substrate.

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Номер записи: 47
23-02-2012 дата публикации

Semiconductor device and method for forming the same

Номер: US20120043592A1
Автор: Chao Zhao, Huilong Zhu, Wenwu Wang
Принадлежит: Institute of Microelectronics of CAS

The present invention provides a semiconductor device. The semiconductor device comprises contact plugs that comprise a first contact plug formed by a first barrier layer arranged on the source and drain regions and a tungsten layer arranged on the first barrier layer; and second contact plugs comprising a second barrier layer arranged on both of the metal gate and the first contact plug and a conductive layer arranged on the second barrier layer. The conductivity of the conductive layer is higher than that of the tungsten layer. A method for forming the semiconductor device is also provided. The present invention provides the advantage of enhancing the reliability of the device when using the copper contact technique.

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Номер записи: 48
23-02-2012 дата публикации

Packaging Integrated Circuits

Номер: US20120043650A1
Автор: Liang Kng Ian Koh, Richard Mangapul Sinaga
Принадлежит: INFINEON TECHNOLOGIES AG

An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

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Номер записи: 49
23-02-2012 дата публикации

Method of making interconnect structure

Номер: US20120045893A1
Автор: Heinrich Koerner
Принадлежит: Individual

One or more embodiments relate to a method of forming a semiconductor device having a substrate, comprising: providing a Si-containing layer; forming a barrier layer over the Si-containing layer, the barrier layer comprising a compound including a metallic element; forming a metallic nucleation_seed layer over the Si-containing layer, the nucleation_seed layer including the metallic element; and forming a metallic interconnect layer over the nucleation_seed layer, wherein the barrier layer and the nucleation_seed layer are formed without exposing the semiconductor device substrate to the ambient atmosphere.

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Номер записи: 50
01-03-2012 дата публикации

Thermally conductive foam product

Номер: US20120048528A1
Автор: Christopher Severance, Gary Rosa, Jonathan Bergin, Victoria Santa Fe
Принадлежит: Parker Hannifin Corp

A compressible, thermally conductive foam interface pad is adapted for emplacement between opposed heat transfer surfaces in an electronic device. One heat transfer surface can be part of a heat-generating component of the device, while the other heat transfer surface can be part of a heat sink or a circuit board. An assembly including the foam interface pad and the opposed electronic components is also provided.

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Номер записи: 51
01-03-2012 дата публикации

Semiconductor structure having conductive vias and method for manufacturing the same

Номер: US20120049347A1
Автор: Meng-Jen Wang
Принадлежит: Advanced Semiconductor Engineering Inc

A semiconductor structure includes a plurality of thermal vias and a heat dissipation layer disposed at a periphery of a back surface of a lower chip in a stacked-chip package. This arrangement improves solderability of a subsequently-bonded heat sink. Additionally, the thermal vias and the heat dissipation layer provide an improved thermal conduction path for enhancing heat dissipation efficiency of the semiconductor structure. A method for manufacturing the semiconductor structure is also provided.

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Номер записи: 52
01-03-2012 дата публикации

Semiconductor Device and Semiconductor Process for Making the Same

Номер: US20120049358A1
Автор: Bin-Hong Cheng
Принадлежит: Advanced Semiconductor Engineering Inc

The present invention relates to a semiconductor device and a semiconductor process for making the same. The semiconductor device of the present invention includes a semiconductor substrate, at least one conductive via and at least one insulation ring. The semiconductor substrate has a first surface. The conductive via is disposed in the semiconductor substrate. Each conductive via has a conductor and an insulation wall disposed the peripheral of the conductor, and the conductive via is exposed on the first surface of the semiconductor substrate. The insulation ring is disposed the peripheral of the conductive via, and the depth of the insulation ring is smaller than that of the insulation wall. Since the insulation ring is disposed the peripheral of the conductive via, the insulation ring can protect the end of the conductive via from being damaged. Furthermore, the size of the insulation ring and the conductive via is larger than the conventional conductive via, the semiconductor device of the invention can utilize surface finish layer, RDL or UBM to easily connect the other semiconductor device.

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Номер записи: 53
01-03-2012 дата публикации

Bumpless build-up layer package with pre-stacked microelectronic devices

Номер: US20120049382A1
Автор: Pramod Malatkar
Принадлежит: Intel Corp

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

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Номер записи: 54
01-03-2012 дата публикации

Flexible-to-rigid tubing

Номер: US20120050994A1
Автор: Dylan J. Boday, Joseph Kuczynski, Robert E. Meyer, III
Принадлежит: International Business Machines Corp

A flexible-to-rigid tube is flexible when routed and is then rigidized to increase burst strength. According to the preferred embodiments of the present invention, the flexible-to-rigid tube is included in a cooling plate assembly for transferring heat from electronic components mounted on a circuit board. In one embodiment, the flexible-to-rigid tube (while in a flexible state) includes a polydimethylsiloxane (PDMS) or other silicone containing pendant or terminal epoxy, vinyl and/or acrylate functional groups and an initiator (e.g., a sulfonium salt photoinitiator, a free radical photoinitiator, or a thermal initiator). In another embodiment, triallyl isocyanurate (TAIC) and an initiator are incorporated into a conventional PVC-based tubing material. The flexible-to-rigid tube changes from the flexible state to a rigid state via formation of a cross-linked network upon exposure to actinic radiation or heat.

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Номер записи: 55
01-03-2012 дата публикации

Electronic component mounting method and electronic component mount structure

Номер: US20120052633A1
Автор: Shoji Sakemi
Принадлежит: Panasonic Corp

A challenge to be met by the present invention is to provide an electronic component mounting method and an electronic component mount structure that make it possible to assure bonding strength for an electronic component whose underside is provided with bumps. In electronic component mounting operation during which an electronic component ( 6 ) whose underside is provided with bumps ( 7 ) with solder is mounted on a substrate ( 1 ), a solder bonding material ( 3 ) including solder particles contained in a first thermosetting resin is used for bonding the bumps ( 7 ) to an electrode ( 2 ) formed on the substrate ( 1 ), thereby forming a solder bonding area ( 7 *) where the solder particles and the bumps ( 7 ) are fused and solidified and a first resin reinforcement area ( 3 a *) that reinforces the solder bonding area ( 7 *). Further, an adhesive ( 4 ) containing as a principal component a second thermosetting resin not including solder particles is used for fixing an outer edge ( 6 a ) of the electronic component ( 6 ) to reinforcement points set on the substrate ( 1 ). Even when the solder bonding material ( 3 ) and the bonding agent ( 4 ) are blended together, normal thermal curing of the thermosetting resin is not hindered. Bonding strength can thereby be assured for the electronic component ( 6 ) whose underside is provided with the bumps ( 7 ).

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Номер записи: 56
08-03-2012 дата публикации

Device for exchanging heat comprising a plate stack and method for producing said device

Номер: US20120055659A1
Автор: Armin Rastogi, Karsten Rechenberg, Michael Meinert, Norbert Hubert
Принадлежит: SIEMENS AG

A device for exchanging heat has a plate stack of at least a first, a second, and a third plate. The three or more plates are stacked one on top of the other and have recesses which are arranged in a regular pattern on a plane of the respective plates. The first and the second plates as well as the second and the third plates are stacked in such a manner that each adjacent plate forms at least one common cooling channel, which is accessible to a fluid, running in a direction on the plane of plates. The two or more cooling channels are formed by way of recesses, which partially but not entirely overlap, in the adjacent plates. The one or more cooling channels of the first and second plates are entirely spatially separated from at least one cooling channel of the second and third plates.

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Номер записи: 57
08-03-2012 дата публикации

Semiconductor package and manufacturing method for a semiconductor package as well as optical module

Номер: US20120056292A1
Автор: Masami Suzuki, Masayuki Nagao, Yasuyuki Ito
Принадлежит: Sony Corp

A semiconductor package includes: a supporting substrate; a functioning element and a first joining element formed on a first principal surface of the supporting substrate; a sealing substrate disposed in an opposing relationship to the supporting substrate with the functioning element and the first joining element interposed therebetween; a second joining element provided on a second principal surface of the supporting substrate; a through-electrode provided in and extending through the supporting substrate and adapted to electrically connect the first and second joining elements; and a first electromagnetic shield film coated in an overall area of a side face of the supporting substrate which extends perpendicularly to the first and second principal surfaces.

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Номер записи: 58
08-03-2012 дата публикации

Semiconductor package

Номер: US20120056313A1
Автор: Jun Morimoto, Masashi AIZAWA, Masayuki Kato
Принадлежит: Individual

A semiconductor package includes a radiator plate including a stress alleviation section, a resin sheet arranged on the radiator plate, a pair of bus bars joined to the radiator plate through the resin sheet at positions at which the stress alleviation section is interposed between the bus bars, and a semiconductor device joined to the pair of bus bars by being sandwiched between the bus bars, and energized from outside through the pair of bus bars.

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Номер записи: 59
08-03-2012 дата публикации

Multi-chip package with offset die stacking

Номер: US20120056335A1
Автор: Peter B. Gillingham
Принадлежит: Mosaid Technologies Inc

A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed.

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Номер записи: 60
08-03-2012 дата публикации

Method of Fabricating A Semiconductor Device Having A Resin With Warpage Compensated Structures

Номер: US20120058606A1
Автор: Chai Wei Heng, Gerhard Deml, Khai Huat Jeffrey Low, Stanley Job Doraisamy, Wae Chet YONG
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device including: a die pad, a die on the die pad, and resin encapsulating the die and forming an isolation thickness over the die pad, the resin including a mounting aperture and a major surface configured for mounting to an external device, the major surface having a non warpage compensation portion adjacent the die and a warpage compensation portion in a relatively thermally inactive zone with an approximate discontinuity and/or abrupt change in gradient between the non warpage compensation portion and the warpage compensation portion.

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Номер записи: 61
15-03-2012 дата публикации

Control device of semiconductor device

Номер: US20120061722A1
Автор: Masahiro MASUNAGA, Takayuki Hashimoto
Принадлежит: Renesas Electronics Corp

A control device of a semiconductor device is provided. The control device of a semiconductor device is capable of reducing both ON resistance and feedback capacitance in a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided. In the control device controlling driving of a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided, a signal of tuning ON or OFF is outputted to a gate electrode in a state of outputting a signal of turning OFF to the second gate electrode.

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Номер записи: 62
15-03-2012 дата публикации

Power Semiconductor Chip Package

Номер: US20120061812A1
Автор: Ralf Otremba
Принадлежит: INFINEON TECHNOLOGIES AG

A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad.

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Номер записи: 63
15-03-2012 дата публикации

Semiconductor device and manufacturing method of the same

Номер: US20120061817A1
Автор: Mamoru SHISHIDO, Noriyuki Takahashi
Принадлежит: Renesas Electronics Corp

A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.

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Номер записи: 64
15-03-2012 дата публикации

Semiconductor chip with redundant thru-silicon-vias

Номер: US20120061821A1
Автор: Bryan Black, Gamal Refai-Ahmed, Joe Siegel, Michael Z. Su, Seth Prejean
Принадлежит: Advanced Micro Devices Inc, ATI TECHNOLOGIES ULC

A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

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Номер записи: 65
15-03-2012 дата публикации

Semiconductor device having pad structure with stress buffer layer

Номер: US20120061823A1
Автор: Chao-Wen Shih, Shang-Yun Hou, Shin-puu Jeng, Tzu-Wei Chiu, Tzuan-Horng LIU, Wei-Cheng Wu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

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Номер записи: 66
15-03-2012 дата публикации

Semiconductor chip, stacked chip semiconductor package including the same, and fabricating method thereof

Номер: US20120061834A1
Автор: Tae Min Kang
Принадлежит: Hynix Semiconductor Inc

A semiconductor chip includes a silicon wafer formed with a via hole, a metal wire disposed in the via hole, and a filler that exposes a part of an upper portion of the metal wire while filing the via hole.

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Номер записи: 67
15-03-2012 дата публикации

Semiconductor chip device with polymeric filler trench

Номер: US20120061852A1
Автор: Bryan Black, Gamal Refai-Ahmed, Michael Z. Su
Принадлежит: Advanced Micro Devices Inc, ATI TECHNOLOGIES ULC

A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

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Номер записи: 68
15-03-2012 дата публикации

Semiconductor package integrated with conformal shield and antenna

Номер: US20120062439A1
Автор: Chi-Hong Chan, Kuo-Hsien Liao, Shih Fuyu
Принадлежит: Advanced Semiconductor Engineering Inc

A semiconductor package integrated with conformal shield and antenna is provided. The semiconductor package includes a semiconductor element, an electromagnetic interference shielding element, a dielectric structure, an antenna element and an antenna signal feeding element. The electromagnetic interference shielding element includes an electromagnetic interference shielding film and a grounding element, wherein the electromagnetic interference shielding film covers the semiconductor element and the grounding element is electrically connected to the electromagnetic interference shielding layer and a grounding segment of the semiconductor element. The dielectric structure covers a part of the electromagnetic interference shielding element and has an upper surface. The antenna element is formed adjacent to the upper surface of the dielectric structure. The antenna signal feeding element passing through the dielectric structure electrically connects the antenna element and the semiconductor element.

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Номер записи: 69
15-03-2012 дата публикации

Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package

Номер: US20120064666A1
Автор: Shigeru Hosomomi, Yoichiro Hamada
Принадлежит: SUMITOMO METAL MINING CO LTD

A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.

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Номер записи: 70
15-03-2012 дата публикации

Method of manufacture of integrated circuit packaging system with stacked integrated circuit

Номер: US20120064668A1
Автор: Henry Descalzo Bathan, Jairus Legaspi Pisigan, Zigmund Ramirez Camacho
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.

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Номер записи: 71
22-03-2012 дата публикации

Package substrate unit and method for manufacturing package substrate unit

Номер: US20120067635A1
Автор: Hideaki Yoshimura, Hitoshi Suzuki, Hnin Nway San Nang, Kazuya Arai, Kei Fukui, Shinpei Ikegami, Yasuhito Takahashi
Принадлежит: Fujitsu Ltd

A semiconductor chip mounting layer of a package substrate unit includes an insulation layer, a conductive seed metal layer formed on the top surface of the insulation layer, conductive pads formed on the top surface of the conductive seed metal layer, metal posts formed substantially in the central portion on the top surface of the conductive pads, and a solder resist layer that is formed to surround the conductive pads and the metal posts.

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Номер записи: 72
22-03-2012 дата публикации

Monolithic magnetic induction device

Номер: US20120068301A1
Автор: Johnny Kin On Sin, Ron Shu Yuen Hui, Rongxiang Wu
Принадлежит: Hong Kong University of Science and Technology HKUST

Providing for a monolithic magnetic induction device having low DC resistance and small surface area is described herein. By way of example, the magnetic induction device can comprise a substrate (e.g., a semiconductor substrate) having trenches formed in a bottom layer of the substrate, and holes formed in the substrate between the trenches and an upper layer of the substrate. Additionally, the magnetic induction device can comprise a conductive coil embedded or deposited within the trenches. The magnetic induction device can further comprise a set of conductive vias formed in the holes that electrically connect the bottom layer of the substrate with the upper layer. Further, one or more integrated circuit components, such as active devices, can be formed in the upper layer, at least in part above the conductive coil. The vias can be utilized to connect to integrated circuit components with the conductive coil, where suitable.

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Номер записи: 73
22-03-2012 дата публикации

Crosslinkable dielectrics and methods of preparation and use thereof

Номер: US20120068314A1
Автор: Marcel Kastler, Silke Annika Koehler
Принадлежит: BASF SE, Polyera Corp

The present invention relates to an electronic device comprising at least one dielectric layer, said dielectric layer comprising a crosslinked organic compound based on at least one compound which is radically crosslinkable and a method of making the electronic device.

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Номер записи: 74
22-03-2012 дата публикации

Tsop with impedance control

Номер: US20120068317A1
Автор: Belgacem Haba, Brian Marcucci
Принадлежит: TESSERA RESEARCH LLC

A semiconductor device of an illustrative embodiment includes a die, a lead frame including a plurality of leads having substantial portions arranged in a lead plane and electrically connected to the die. Most preferably, the package includes at least a substantial portion of one conductive element arranged in a plane positioned adjacent the lead frame and substantially parallel to the lead plane, the conductive element being capacitively coupled to the leads such that the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path, and an encapsulant which encapsulates the leads and the conductive element. The leads and, desirably, the conductive element have respective connection regions which are not covered by the encapsulant.

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Номер записи: 75
22-03-2012 дата публикации

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

Номер: US20120068319A1
Автор: Daesik Choi, Oh Han Kim, SangMi Park
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate.

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Номер записи: 76
22-03-2012 дата публикации

Integrated Power Converter Package With Die Stacking

Номер: US20120068320A1
Автор: Eric Yang, Hunt Hang Jiang, Jinghai Zhou
Принадлежит: Monolithic Power Systems Inc

An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry.

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Номер записи: 77
22-03-2012 дата публикации

Anti-tamper microchip package based on thermal nanofluids or fluids

Номер: US20120068326A1
Автор: James J. McNamara, Jr., Mark D. Poliks, Rabindra N. Das, Voya R. Markovich
Принадлежит: Endicott Interconnect Technologies Inc

A tamper-resistant microchip package contains fluid- or nanofluid-filled capsules, channels, or reservoirs, wherein the fluids, either alone or in combination, can destroy circuitry by etching, sintering, or thermally destructing when reverse engineering of the device is attempted. The fluids are released when the fluid-filled cavities are cut away for detailed inspection of the microchip. Nanofluids may be used for the sintering process, and also to increase the thermal conductivity of the fluid for die thermal management. Through-vias and micro vias may be incorporated into the design to increase circuitry destruction efficacy by improving fluid/chip contact. Thermal interface materials may also be utilized to facilitate chip cooling.

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Номер записи: 78
22-03-2012 дата публикации

Multi-function and shielded 3d interconnects

Номер: US20120068327A1
Автор: Belgacem Haba, Craig Mitchell, Ilyas Mohammed, Piyush Savalia, Vage Oganesian
Принадлежит: TESSERA RESEARCH LLC

A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element.

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Номер записи: 79
22-03-2012 дата публикации

Integrated circuit packaging system with active surface heat removal and method of manufacture thereof

Номер: US20120068328A1
Автор: Hin Hwa Goh, KANG Chen, Rui Huang, Xusheng Bao, Yung Kuan Hsiao
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.

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Номер записи: 80
22-03-2012 дата публикации

Microsprings Partially Embedded In A Laminate Structure And Methods For Producing Same

Номер: US20120068331A1
Автор: Eric Peeters, Eugene M. Chow
Принадлежит: Palo Alto Research Center Inc

At least one microspring has applied thereover a laminate structure to provide: mechanical protection during handling and wafer processing, a spring spacer layer, strengthening of the anchor between spring and substrate, provision of a gap stop during spring deflection, and moisture and contaminant protection. A fully-formed laminate structure may be applied over the microspring structure or a partly-formed laminate structure may be applied over the microspring structure then cured or hardened. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may remain in place in the final microspring structure or be removed in whole or in part. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structure, forming for example additional structural elements such as a gap stop for the microspring.

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Номер записи: 81
22-03-2012 дата публикации

Semiconductor device having semiconductor member and mounting member

Номер: US20120068362A1
Автор: Syuuichi Kariyazaki
Принадлежит: Renesas Electronics Corp

A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased.

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Номер записи: 82
22-03-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120069530A1
Автор: Kazushige Kanda, Satoshi Inoue, Yuui Shimizu
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor device includes a stacked chip includes semiconductor chips which are stacked, the semiconductor chips comprises semiconductor substrates and through electrodes formed in the semiconductor substrates, respectively, the through electrodes being electrically connected, and deactivating circuits provided in the semiconductor chips, respectively, and configured to deactivate a failed semiconductor chip.

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Номер записи: 83
22-03-2012 дата публикации

Semiconductor device having decreased contact resistance

Номер: US20120070987A1
Автор: David Wu, Donna Michael, MARK Michael, Zhonghai Shi
Принадлежит: Globalfoundries Inc

Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.

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Номер записи: 84
29-03-2012 дата публикации

Multilayer printed wiring board and method for manufacturing multilayer printed wiring board

Номер: US20120073868A1
Автор: Takeshi Nakamura, Yoshinori Takenaka
Принадлежит: Ibiden Co Ltd

A method for manufacturing a multilayer printed wiring board includes preparing a first resin insulative material having a first conductive circuit on or in the first resin insulative material, forming a second resin insulative material on the first resin insulative material and the first conductive circuit, forming on a surface of the second resin insulative material a first concave portion to be filled with a conductive material for formation of a second conductive circuit, forming on the surface of the second resin insulative material a pattern having a second concave portion and post portions to be filled with the conductive material for formation of a plane conductor, and filling the conductive material in the first concave portion and the second concave portion such that the second conductive circuit and the plane conductor are formed.

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Номер записи: 85
29-03-2012 дата публикации

Semiconductor package with through electrodes and method for manufacturing the same

Номер: US20120074529A1
Автор: Jin-Ho Bae, Ki-Young Kim, Myung-Geun PARK
Принадлежит: Hynix Semiconductor Inc

A semiconductor package may include a substrate with a first surface over which bond fingers are formed. At least two semiconductor chips may be stacked on the first surface of the substrate and each chip may have via holes. The semiconductor chips may be stacked such that the respective via holes expose the respective bond fingers of the substrate. Through electrodes may be formed in the via holes. The through electrodes may comprise carbon nanotubes grown from the exposed bond fingers of the substrate, where the through electrodes may be electrically connected with the semiconductor chips.

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Номер записи: 86
29-03-2012 дата публикации

Interposer including air gap structure, methods of forming the same, semiconductor device including the interposer, and multi-chip package including the interposer

Номер: US20120074530A1
Автор: Chang-Hyun Kim, Kyung-Ho Kim
Принадлежит: Individual

Example embodiments of the present invention relate to an interposer of a semiconductor device having an air gap structure, a semiconductor device using the interposer, a multi-chip package using the interposer and methods of forming the interposer. The interposer includes a semiconductor substrate including a void, a metal interconnect, provided within the void, thereby forming an air gap insulating the metal interconnect. The metal interconnect may be connected to a contact element, and may be maintained within the air gap using the contact element.

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Номер записи: 87
29-03-2012 дата публикации

Semiconductor device with exposed pad

Номер: US20120074549A1
Автор: Kai Yun Yow, Poh Leng EU
Принадлежит: FREESCALE SEMICONDUCTOR INC

A semiconductor device has a die attached to a die pad and electrically connected to lead fingers. The die, a top surface of the die pad, and a first portion of the lead fingers are covered with a mold compound. A second portion of the lead fingers project from the mold compound and allow for external electrical connection to the die. The mold compound around the die and lead fingers is extended such that a cavity is formed below the die pad. The die pad is exposed via the cavity. A heat sink may be inserted into the cavity and attached to the bottom surface of the die pad.

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Номер записи: 88
29-03-2012 дата публикации

Circuit Board Packaged with Die through Surface Mount Technology

Номер: US20120074558A1
Автор: Hsuan Yu LU, Kuei-Wu Chu, Tse Ming Chu
Принадлежит: Mao Bang Electronic Co Ltd

A package of a circuit board and a die are packed through surface mount technology (SMT). The shortest circuit is formed with at a low cost. Thus, the package can work in high speed and high frequency applications.

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Номер записи: 89
29-03-2012 дата публикации

Semiconductor structure having a through substrate via (tsv) and method for forming

Номер: US20120074583A1
Автор: Thuy B. Dao
Принадлежит: Individual

A structure having a substrate includes an opening in the substrate having depth from a top surface of the substrate to a bottom surface of the substrate. A conductive material fills the opening. The opening has a length direction and a width direction and a first and second feature. The first feature and the second feature are spaced apart by a first length. The first feature has first width as a maximum width of the first feature, and the second feature has a second width as the maximum width of the second feature. The opening has a minimum width between the first feature and the second feature that is no more than one fifth the first length. The first width and the second width are each at least twice the minimum width.

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Номер записи: 90
29-03-2012 дата публикации

Methods of fabricating package stack structure and method of mounting package stack structure on system board

Номер: US20120074586A1
Автор: Eun-Jin Choi, Sun-Kyoung SEO
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

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Номер записи: 91
29-03-2012 дата публикации

Integrated circuit packaging system with warpage control and method of manufacture thereof

Номер: US20120074588A1
Автор: Hin Hwa Goh, KANG Chen, Rui Huang, Xusheng Bao, Yung Kuan Hsiao
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier.

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Номер записи: 92
05-04-2012 дата публикации

Chip Capacitor Precursors

Номер: US20120081832A1
Автор: Azuma Chikara
Принадлежит: Texas Instruments Inc

A capacitive precursor includes electrically conductive material layers stacked on a substrate. The electrically conductive layers provide first and second patterns. The patterns each include overlaying areas free of the electrically conductive material. The first pair of areas overlay areas of the second pattern having the electrically conductive material and the second pair of areas overlay areas of the first pattern having the electrically conductive material. Dielectric layers are interposed between neighboring electrically conductive material layers for electrical isolation. One or more capacitive precursors can be dropped onto or into a board and during assembly of a packaged semiconductor device and have electrically conducting layers associated with its respective plates connected together to form a capacitor during assembly using conventional assembly steps.

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Номер записи: 93
05-04-2012 дата публикации

Semiconductor die package including low stress configuration

Номер: US20120083071A1
Автор: Maria Clemens Y. Quinones, Maria Cristina B. Estacio
Принадлежит: Individual

A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.

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Номер записи: 94
12-04-2012 дата публикации

Monolithic cold plate configuration

Номер: US20120085523A1
Автор: Mark A. Zaffetti, Michael B. Laurin
Принадлежит: Hamilton Sundstrand Space System International Inc

A cold plate assembly includes a monolithic cold plate which defines a trough located to intersect a fluid path.

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Номер записи: 95
12-04-2012 дата публикации

Heat spreader with mechanically secured heat coupling element

Номер: US20120085527A1
Автор: Konrad Pfaffinger
Принадлежит: Congatec GmbH

A heat spreader for dissipating heat generated by at least one heat-generating power semiconductor device. Such a heat spreader comprises a base plate ( 11 ) which is connectable in a heat-conducting manner to the at least one power semiconductor device ( 2 ), and at least one heat coupling element ( 4 ) which is connected in a heat conducting manner to the at least one power semiconductor device ( 2 ) on the one hand and to the base plate ( 11 ) on the other hand and comprises at least one elastic layer ( 5 ). The heat coupling element ( 4 ) comprises at least one holding element for mechanically fixing the heat coupling element ( 4 ) relative to a plane defined by the base plate ( 11 ).

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Номер записи: 96
12-04-2012 дата публикации

Integrated circuit packaging system with interposer interconnections and method of manufacture thereof

Номер: US20120086115A1
Автор: A Leam Choi, HanGil Shin, In Sang Yoon, Kenny Lee
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure; mounting a first-external-package-component to the routing structure; and forming a first-external-package-encapsulation covering the first-external-package-component.

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Номер записи: 97
12-04-2012 дата публикации

Package with embedded chip and method of fabricating the same

Номер: US20120086117A1
Автор: Chiang-Cheng Chang, Hsin-Yi Liao, Shih-Kuang Chiu
Принадлежит: Siliconware Precision Industries Co Ltd

A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified.

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Номер записи: 98
12-04-2012 дата публикации

Semiconductor assembly and semiconductor package including a solder channel

Номер: US20120086123A1
Автор: Jeong-Woo Park, Moon-Gi Cho, Sun-Hee Park, Ui-Hyoung Lee
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

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Номер записи: 99
12-04-2012 дата публикации

Package systems and manufacturing methods thereof

Номер: US20120086127A1
Автор: Chia-Pao SHU, Chun-Wen Cheng, Hsin-Ting HUANG, Jung-Huei Peng, Kuei-Sung CHANG, Shang-Ying Tsai
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

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Номер записи: 100