МНОГОСЛОЙНАЯ КОРПУСНАЯ СБОРКА СО ВСТРОЕННОЙ АНТЕННОЙ

Использование: для создания многослойной корпусной сборки. Сущность изобретения заключается в том, что корпусная сборка интегральной микросхемы (IC) содержит первый слой, имеющий первую сторону и вторую сторону, расположенную напротив первой стороны; второй слой, соединенный с первой стороной первого слоя; один или более антенных элементов, соединенных со вторым слоем; и третий слой, соединенный со второй стороной первого слоя, при этом первый слой представляет собой армирующий слой, имеющий модуль упругости при растяжении больше, чем модуль упругости при растяжении второго слоя и третьего слоя, при этом первый слой образует плоскость, проходящую в горизонтальном направлении; и никакие металлизированные элементы для маршрутизации электрических сигналов в горизонтальном направлении не расположены непосредственно на первом слое. Технический результат - обеспечение возможности уменьшения потерь в проводниках. 3 н. и 16 з.п. ф-лы, 9 ил.

Verbesserte Mehrschichtverpackung

Gehäuse einer integrierten Schaltung.

Gehäuse einer integrierten Schaltung.

Method for manufacturing DCB substrate for e.g. power semiconductor component in power converter, involves electroplating metal film on metallization layer and around cover so as to form pocket at desired position of power component

The method involves providing an electrically non-conductive insulating material body (1). A structured electrically conductive metallization layer (2a) is applied on a side (15a) of the body. An electrically non-conductive cover (3) is applied on the metallization layer at a desired position of a power semiconductor component. A metal film is electroplated on the metallization layer and around the cover so as to form a pocket at a desired position of the semiconductor component. The cover is removed. Independent claims are also included for the following: (1) a substrate for a power semiconductor component (2) a power semiconductor module.

Bondhügellose Aufbauschicht- und Laminatkernhybridstrukturen und Verfahren für ihre Montage

Eine Struktur enthält ein Hybridsubstrat zum Stützen eines Halbleiterbauelements, das eine bondhügellose Aufbauschicht, in die das Halbleiterbauelement eingebettet ist, und eine Laminatkernstruktur enthält. Die bondhügellose Aufbauschicht und die Laminatkernstruktur werden durch eine Verstärkungsplattierung, die mit einem plattierten Durchgangsloch in der Laminatkernstruktur und einer anschließenden Bondinsel der bondhügellosen Aufbauschichtstruktur verbunden ist, zu einer integralen Vorrichtung gemacht.

Leiterplatte, Hochfrequenzmodul und Radarvorrichtung

Die Erfindung bezieht sich auf eine Leiterplatte. Die Leiterplatte (10) umfasst ein Substrat (1), eine Wellenleiterleitung (2) und einen laminierten Wellenleiter (3). Die Wellenleiterleitung (2) ist zumindest teilweise auf einer ersten Oberfläche des Substrats (1) angeordnet. Die Wellenleiterleitung (2) überträgt ein Hochfrequenzsignal. Der laminierte Wellenleiter (3) ist innerhalb des Substrats (1) ausgebildet. Der laminierte Wellenleiter (3) ist mit der Wellenleiterleitung (2) elektromagnetisch gekoppelt und weist einen Ausleitungsabschnitt (3a) auf, der vom Inneren des Substrats (1) zu einer anderen Oberfläche als der ersten Oberfläche ausgeleitet ist. Der laminierte Wellenleiter (3) umfasst eine dielektrische Schicht (31), zwei Hauptleiterschichten (32) und eine Durchgangsleitergruppe (33). Die zwei Hauptleiterschichten (32) legt die dielektrische Schicht (31) in einer Dickenrichtung davon ein. In der Durchgangsleitergruppe (34) sind mehrere Durchgangsleiter (33) entlang einer Hochfrequenzsignal-Übertragungsrichtung ...

Integration von Silicium-Photonik-IC für hohe Datenrate

Integrierte Komponentenbaugruppe, die umfasst:eine Leiterplatte (PCB);eine integrierte Photonikschaltung (PIC), die mit der PCB auf einer ersten Seite der PIC mechanisch gekoppelt ist; undeine Treiber-IC mit einer ersten Seite, wobei die erste Seite der Treiber-IC(i) mit einer zweiten Seite der PIC über einen ersten Satz von Höcker-Bondverbindungen direkt mechanisch und elektrisch gekoppelt ist, und(ii) mit der PCB über einen zweiten Satz von Höcker-Bondverbindungen elektrisch gekoppelt ist.

STRUKTUR UND FERTIGUNGSVERFAHREN EINES DREIDIMENSIONALEN SYSTEMS EINER METALL-LEITERPLATTE, DIE VOR DEM HORIZONTALEN BESTÜCKEN GEÄTZT WIRD

Gegenstand ist eine horizontal bestückte, dreidimensionale, vor dem Bestücken geätzte System-Level-Metall-Leiterplatte, charakterisiert durch einen Metallsubstrat-Rahmen (1). Dieser Metallsubstrat-Rahmen (1) weist Basisbereiche (2) und Stifte (3) auf. Die Frontseiten der Basisbereiche (2) werden mit Chips (5) bestückt, die Frontseiten der Chips (5) sind über Metalldrähte (6) mit den Frontseiten der Stifte (3) verbunden. Auf den Front- oder den Rückseiten der Stifte (3) befinden sich Leitungspunkte (7). Die peripheren Bereiche der Basisbereiche (2), die Bereiche zwischen den Basisbereichen (2) und den Stiften (3), die Bereiche zwischen den Stiften (3), über den Basisbereichen (2) und den Stiften (3) und den Außenbereichen der Chips (5), die Metalldrähte (6) und die Leitungspunkte (7) sind mit Formmasse (8) vergossen und die Oberflächen des Rahmens aus Metall-Substrat (1), der Stifte (3) und der Leitungspunkte (7), die aus der Formmasse (8) herausragen, sind mit einer oxidationsbeständigen ...

Parallelchip-Eingebettete gedruckte Schaltungsplatine und Herstellungsverfahren dafür

Eine Parallelchip-eingebettete Schaltungsplatine und ein Herstellungsverfahren dafür sind offenbart. Mit einem Verfahren zum Herstellen einer Parallelchip-eingebetteten, gedruckten Schaltungsplatine, welches umfasst: a) Bilden eines Parallelchips durch ein Verbinden einer Mehrzahl von Einheitschips, die Elektroden oder elektrisch verbundene Elemente aufweisen, die auf den oberen und unteren Flächen davon gebildet sind, parallel unter Verwendung von zumindest einem leitfähigen Element; (b) Verbinden einer Elektrode auf einer Seite des Parallelchips mit einer ersten Platine; und (c) Verbinden einer Elektrode auf der anderen Seite des Parallelchips mit einer zweiten Platine, können Chips in einer Schaltungsplatine zu geringe Kosten eingebettet werden, da eine Mehrzahl von Einheitschips auf einmal eingebettet und ein mechanischer Bohrer oder Fräser anstelle eines Laserbohrers beim Ausstanzen der Kavität oder von Durchlöchern verwendet werden kann.

Microwave module comprising substrate with HF and LF layers forming distribution network structures, includes intervening insulating layer

The high frequency structure layer (4) is separated from the low frequency structure layer (3) by the insulating layer (1). An Independent claim is included for the method of manufacture, which especially employs fine pitch flip-chip technology for bonding to the substrate.

Laminierte Leiterplatte und Herstellungsverfahren

Überspritzte Substrat-Chip-Anordnung mit Wärmesenke

Eine elektronische Vorrichtung umfasst ein Substrat, mindestens einen elektronischen Chip, der auf dem Substrat montiert und elektrisch damit verbunden ist und als Systemsteuereinheit zum Steuern eines verbunden Systems konfiguriert ist, eine Wärmeableitstruktur, die thermisch mit dem mindestens einen elektronischen Chip verbunden ist und zum Ableiten von Wärme, die von dem mindestens einen elektronischen Chip bei Betrieb der elektronischen Vorrichtung erzeugt wird, konfiguriert ist, und eine Überspritzstruktur, die zum mindestens teilweisen Verkapseln des mindestens einen elektronischen Chips und des Substrats konfiguriert ist.

PACKAGES FOR ENCLOSING SEMICONDUCTOR ELEMENTS

Packungen für drahtlose Signalübertragung mit integrierter Antennengruppe

Antennenpackungsstrukturen werden bereitgestellt, um Packungen für drahtlose Signalübertragung zu implementieren. Eine Antennenpackung enthält zum Beispiel ein mehrschichtiges Packungssubstrat, eine ebene Antennengruppe, Antennenspeiseleitungen und Widerstandsübertragungsleitungen. Die ebene Antennengruppe beinhaltet eine Gruppe von aktiven Antennenelementen und künstliche Antennenelemente, die die Gruppe von aktiven Antennenelementen umgeben. Jedes aktive Antennenelement ist mit einer entsprechenden Antennenspeiseleitung verbunden, und jedes künstliche Antennenelement ist mit einer entsprechenden Widerstandsübertragungsleitung verbunden. Jede Widerstandsübertragungsleitung verläuft durch das mehrschichtige Packungssubstrat und endet in derselben Metallisierungsschicht des mehrschichtigen Packungssubstrats.

Halbleiter-Bauelement und Verfahren

Ein Halbleiter-Bauelement weist Folgendes auf: ein Substrat; eine erste Umverteilungsschicht (RDL) über einer ersten Seite des Substrats; eine oder mehrere Halbleiter-Dies, die über der ersten RDL angeordnet sind und mit dieser elektrisch verbunden sind; und ein Verkapselungsmaterial über der ersten RDL und um den einen oder die mehreren Halbleiter-Dies. Das Halbleiter-Bauelement weist weiterhin Anschlüsse auf, die an einer zweiten Seite des Substrats befestigt sind, die der ersten Seite gegenüberliegt, wobei die Anschlüsse elektrisch mit der ersten RDL verbunden sind. Das Halbleiter-Bauelement weist weiterhin eine Polymerschicht auf der zweiten Seite des Substrats auf, wobei die Anschlüsse von der Polymerschicht her über eine erste Oberfläche der Polymerschicht überstehen, die von dem Substrat entfernt ist. Ein erster Teil der Polymerschicht, der die Anschlüsse kontaktiert, hat eine erste Dicke, und ein zweiter Teil der Polymerschicht zwischen benachbarten Anschlüssen hat eine zweite Dicke ...

ABSCHIRMLÖSUNGEN FÜR DIRECT-CHIP-ATTACHKONNEKTIVITÄTSMODULPACKUNGSSTRUKTUREN

Es werden Verfahren zum Ausbilden von Packungsstrukturen und Strukturen, die dadurch ausgebildet werden, beschrieben. Diese Verfahren/Strukturen können eine Abschirmstruktur aufweisen, die auf einer Oberfläche einer Packungsstruktur angeordnet ist, wobei die Abschirmstruktur eine Folie, ein leitfähiges Material, das auf einer Oberfläche der Folie angeordnet ist, und mehrere leitfähige Stäbe aufweist, wobei jeder individuelle leitfähige Stab der mehreren leitfähigen Stäbe durch die Folie angeordnet ist und zumindest ein Anteil der mehreren leitfähigen Stäbe physikalisch mit Erdungsbahnen verkoppelt ist, die auf der Oberfläche der Packungsstruktur angeordnet sind.

Laminierter Kondensator und Montageanordnung

Laminierter Kondensator mit folgenden Merkmalen: einem Kondensatorkörper (43) mit einem laminierten Stapel einer Mehrzahl von dielektrischen Schichten (42); zumindest einem Paar einer ersten und einer zweiten inneren Elektrode (44, 45), die sich gegenüberliegen, wobei zumindest eine der dielektrischen Schichten (42) zwischen denselben angeordnet ist, in dem Kondensatorkörper (43); einer Mehrzahl von ersten Durchführungsleitern (46), die zumindest eine der dielektrischen Schichten (42) durchdringen und die innerhalb des Kondensatorkörpers (43) vorgesehen sind, wobei die ersten Durchführungsleiter (46) von den zweiten inneren Elektroden (45) elektrisch isoliert und mit den ersten inneren Elektroden (44) elektrisch verbunden sind, und einer Mehrzahl von zweiten Durchführungsleitern (47), die den Kondensatorkörper (43) durchdringen und innerhalb des Kondensatorkörpers (43) vorgesehen sind, wobei die zweiten Durchführungsleiter (47) von den ersten inneren Elektroden (44) elektrisch isoliert ...

Electronic component, for use as ceramic module in mobile radio equipment, comprises covering unit and semiconductor chip and/or passive component arranged between substrate and upper covering plate of covering unit

An electronic component comprises a covering unit (3) and a semiconductor chip and/or passive component arranged between a substrate and an upper covering plate (2) of the covering unit. The covering unit is supported on the surface of the substrate via a spacer (5). The substrate has metal-coated corner regions (6, 7, 8, 9) electrically or mechanically connected to corresponding molded corner region (10-13) of the covering unit. An Independent claim is also included for the production of an electronic component. Preferred Features: A metal layer (14-17) is applied to the corner regions in a thickness of 0.5-500 microns m.

Multilayer circuit module for wireless communication system has passive high frequency components and passive base component layer

A connection integration region includes at least one connecting layer (404,408) for electrically coupling the circuit components (409). A passive base component integration region has a passive base component layer (405,407). A passive high frequency component integration region comprises passive high frequency components. An Independent claim is included for a method of manufacturing a multilayer circuit module.

Input/output architecture for mounted processors, and methods of using same

Hybrid electronic circuit

Substrate for integrated circuit devices including multi-layer glass core and methods of making the same

CIRCUIT ARRANGEMENT

Reconstituted device including die and functional material

Dies from a wafer are reassembled with passive components and encapsulated to form a reconstituted electronic device 10 comprising a die 11, a passive, functioning component 13 and a metallic redistribution layer 15 which defines an electronic component in an area at least partially above the functioning material. The electronic component may be a metal-oxide-metal capacitor, an inductor or an antenna. The functioning material may be ceramic or it may be a ferrite. The functioning material may surround the die. In one embodiment the functioning material is a ceramic body with a metallic coating 110 (figure 10) on a face opposite that of the surface of the substrate on which the die and functioning material are embedded, a metallic via 102 (figure 9) is included through the ceramic body to contact the metal coating, the redistribution layer/ceramic body/metal coating structure forms a capacitor. In another embodiment the functioning material may be a metal carrier 120 (figure 11) with an ...

Transferring logging data from an offset well location to a target well location

Systems and methods for transferring logging data from an offset well location to a target well location by adjusting the logging data to account for the difference in correlated depths between the target well and the offset well where logging data is acquired.

Transferring logging data from an offset well location to a target well location

Nput/output architechture for mounted processors, and methods of using same

Transferring logging data from an offset well location to a target well location

Multilayer circuit component and method for manufacturing the same

DISTRIBUTED CAPACITY

ELECTRONIC PACKING WITH EMBEDDED CONDENSER AND THEIR MANUFACTURING PROCESSES

EMBEDDED SUPPORT DISKS FOR RELIABLE PILE PATHS IN ELECTRONIC SUBSTRATES

ELECTRONIC COMPOSITE CONSTRUCTION PART AND PROCEDURE FOR ITS PRODUCTION

PROCEDURE FOR THE PRODUCTION OF A LAMINATED PRINTED CIRCUIT BOARD

IC HOUSING, CONSISTING OF THREE COATED DIELECTRIC PLATES.

SEMICONDUCTOR ARRANGEMENT.

Annular capacitor RF, microwave and MM wave systems

The present invention includes a method for creating an annular capacitor adjacent to via or imbedded metal structure allowing for device to be made in close proximity to the via connecting to a ground plane. The annular capacitor in close proximity to the metal filled via or imbedded metal structure allows the construction of capacitors, filters, or active devices enabling a smaller RF device and/or to shunt a signal to the integrated ground plane. This reduces the RF, Electronic noise and results in a reduced device size.

FARADAY WELL AND MICROCHIP

EMBEDDED TOROIDAL INDUCTORS

A method for making an embedded toroidal inductor (118) includes forming in a ceramic substrate (100) a first plurality of conductive vias (102) radially spaced a first distance from a central axis (101) so as to define an inner circumference. A second plurality of conductive vias (104) is formed radially spaced a second distance about the central axis so as to define an outer circumference. A first plurality of conductive traces (110) forming an electrical connection between substantially adjacent ones of the first and second plurality of conductive vias is formed on a first surface (106) of the ceramic substrate. Further, a second plurality of conductive traces (110) forming an electrical connection between circumferentially offset ones of the first and second plurality of conductive vias is formed on a second surface of the ceramic substrate opposed from the first surface to define a three dimensional toroidal coil.

EMBEDDED TOROIDAL INDUCTORS

A method for making an embedded toroidal inductor (118) includes forming in a ceramic substrate (100) a first plurality of conductive vias (102) radially spaced a first distance from a central axis (101) so as to define an inner circumference. A second plurality of conductive vias (104) is formed radially spaced a second distance about the central axis so as to define an outer circumference. A first plurality of conductive traces (110) forming an electrical connection between substantially adjacent ones of the first and second plurality of conductive vias is formed on a first surface (106) of the ceramic substrate. Further, a second plurality of conductive traces (110) forming an electrical connection between circumferentially offset ones of the first and second plurality of conductive vias is formed on a second surface of the ceramic substrate opposed from the first surface to define a three dimensional toroidal coil.

METAL BASE CIRCUIT BOARD AND ITS PRODUCTION PROCESS

A metal base circuit board to be used for a hybrid integrated circuit is provided. The circuit board comprises a metal plate and an insulating layer provided on the metal plate. Circuits are provided on the insulating layer and a plurality of semiconductors are mounted on the circuits. A low dielectric constant portion is provided on the metal plate under a part of the circuits on which no semiconductor is mounted. The low dielectric constant portion may be formed by providing a dent portion on the surface of the metal plate and filling the dent portion with a resin containing an inorganic filler. The side wall of the dent portion may have a gradient from 35 to 65°.

APPLICANT SCREENING

Systems (100, 2700) and methods (3400) for screening applicants (102, 2702) are disclosed herein. A method (3400) of screening applicants (102, 2702) is performed by a screening server (112, 2712). The server (112, 2712) begins by receiving (3402) a selection of screening services and an applicant profile that identifies an applicant (102, 2702). The screening continues by generating (3404) screening results specified by the selection of screening services based on the applicant profile. A property manager (120, 2720) is then notified (3406) that the screening results are available for the applicant (102, 2702) based upon the applicant profile. The screening results are then provided (3410) to the property manager (120, 2720) based upon the applicant profile. Based on these screening results, the screener or property manager (120, 2720) can make a decision about the applicant (102, 2702) and communicate a decision action to the applicant (102, 2702).

HIGH DENSITY ELECTRICAL CONNECTORS

The present invention relates to self-aligned, flexible high density and impedance adjusted electrical connectors used in microelectronic systems. This invention solves the problem of having electrical connection and alignment at the same time. One connector (200) having a first part (204) consists of two metal layer structures, a first signal path (212) and a first ground path (210), covering the V-groove (202). The connector also has a second part (208) consisting of corresponding metal layers, a second signal path (224) covering the elastic bump (206) and a second signal ground plane (226), which fits into the V-groove (202). The first and the second signal path (212, 224) are in contact with each other when the first and the second part (204, 208) are brought together. The contact is self-aligned when put together. The electrical contact will remain even if displaced due to the thermal expansion.

Semiconductor device and manufacturing method thereof

Semiconductor device

A semiconductor device which can reduce a noise current without depending upon the mounting layout of a circuit board by matching the impedance of the power supply line and that of the GND line in the semiconductor device. In a typical embodiment of this invention, the semiconductor device having a package substrate, a semiconductor chip, a power supply line and a GND line is further provided with a conduction board and first and second impedance adjustment elements. The conduction board determines the parasitic capacitance of the power supply line and the GND line, and the first and second impedance adjustment elements adjust the impedance of the power supply line and the GND line.

Capacitor with a dielectric between a via and a plate of the capacitor

PACKAGING SUBSTRATE AND PACKAGE STRUCTURE

Printed circuit board

The present invention provides a printed wiring board. In a multilayer printed wiring board, a contact area (side area of a hole (41b) in a lower electrode) of a lower electrode (41) of a thin film capacitor (40) and a lower via hole conductor (45) is larger than a contact area (bottom area of the hole (41b)) when the via hole conductor is formed to abut to the lower electrode (41), and the lowerelectrode (41) is thicker than a BU conductor layer (32) of a build up section (30). Furthermore, the lower via hole conductor (45) is bent at a connecting section (J) of the hole (41b) in the lower electrode and a hole (26b) in an insulating layer. Thus, peeling is not easily generated between the lower via hole conductor (45) and the lower electrode (41) after heat cycle test.

A base plate for mounting the pick-up element and the imaging device

APPARATUS WITH 3D WIREWOUND INDUCTOR INTEGRATED WITHIN A SUBSTRATE

Semiconductor device and manufacturing method of semiconductor device

Electronic package

Integrated fan-out package

薄膜电容器和电子电路部件

... 在具有在规定面上形成的下部电极、在上述下部电极上形成的电介质层和在上述电介质层上形成的上部电极的薄膜电容器中，其特征在于：用电介质层以外的绝缘体覆盖了上述下部电极的端部。 ...

Electrolytic depositon and via filling in coreless substrate processing

Electronic assemblies including coreless substrates and their manufacture using electrolytic plating are described. One method includes providing a core comprising a metal, and forming a dielectric material on the core. The method also includes forming vias in the dielectric material, the vias positioned to expose metal regions. The method also performs an electrolytic plating of metal into the vias and on the metal regions, wherein the core is electrically coupled to a power supply during the electrolytic plating of metal into the vias and delivers current to the metal regions. The method also includes removing the metal core after the electrolytic plating of metal into the vias. Other embodiments are described and claimed.

Semiconductor package comprising the aerial and its manufacturing method

Printed circuit board and method for producing the printed circuit board

For through the use of backside molding configuration (BSMC) to improve the package warping and the connection reliability of the process

Provided for the semiconductor chip are connected with each other intermediary substrate method and apparatus

Wiring board and manufacturing method thereof

For flip chip package structure

Manufacturing method of semiconductor device and semiconductor device

Semiconductor device and manufacturing method of semiconductor device

Printed wiring board

A printed wiring board comprises a wiring substrate provided with at least one conductor circuit, a solder resist layer formed on the surface of the wiring substrate, covering the at least one conductor circuit, conductor pads formed on a part of the at least one conductor circuit exposed from respective openings provided in the solder resist layer for mounting electronic parts, and solder bumps formed on the respective conductor pads. Connection reliability and insulation reliability are easily improved by making the ratio (H/D) of a height H from solder resist layer surface the solder bump to an opening diameter of the opening about 0.55 to about 1.0 even in narrow pitch structure under the pitch of the opening provided in the solder resist layer of about 200 mum or less.

High frequency package

Electronic package having embedded capacitors and method of fabrication therefor

Interposer substrate and method of fabricating same

Electromagnetic-interference (EMI)-shielding semiconductor element

The invention provides an electromagnetic-interference (EMI)-shielding semiconductor element, which comprises a substrate having a plurality of first conductive through holes and second conductive through holes formed therein; a redistribution layer formed on the substrate and having a plurality of conductive pads electrically connected to the first conductive through holes; and a metal layer formed on the redistribution layer and electrically connected to the second conductive through holes. The metal layer further has a plurality of openings for the conductive pads of the redistribution layer to be exposed from the openings without electrically connecting the first metal layer. As such, the metal layer and the second conductive through holes form a shielding structure that can prevent passage of electromagnetic waves into or out of the redistribution layer or side surfaces of the semiconductor element, thereby effectively shield electromagnetic interference.

Improved integrated circuit structure

MULTILAYER CERAMIC PACKAGE

INTEGRATED CIRCUIT PACKAGE OF HIGH DENSITY

ELECTRONIC DEVICE HAVING AN INTEGRATED PASSIVE COMPONENTS

Packaging device for integrated circuits

Dispositif de conditionnement de circuits intégrés, caractérisé en ce qu'il comporte au moins une plaquette de circuit imprimé (11, 12) sur laquelle est fixée une plaquette de rehausse (15) comportant au moins une fenêtre, pour former avec la surface de la plaquette de circuit imprimé (12) se trouvant en regard de la fenêtre, le fond et les parois latérales d'un logement pour au moins un circuit intégré, connecté avec le circuit imprimé porté par la plaquette définissant le fond du logement à l'aide de fils conducteurs, le logement contenant le circuit intégré étant rempli d'une résine recouvrant totalement le circuit intégré, et en ce que ladite plaquette de circuit imprimé (11, 12) est découpée à sa périphérie selon une ligne de trous de traversée (23) pourvus d'un revêtement métallique (24) et connectés à des conducteurs imprimés de la plaquette, les rainures métallisées (23, 24) résultant du découpage constituant des bornes de connexion du dispositif.

METHOD FOR REALIZATION Of a DEPOSIT ON a REMOVABLE SUPPORT, AND DEPOSIT CARRIED out ON a SUPPORT

L'invention concerne un procédé de réalisation d'un dépôt électrochimique (8-1, ..., 8-4), à l'aide d'un substrat (2) comportant des plots (4-1, ..., 4-5) de connexion, ces plots étant utilisés comme électrodes, le dépôt étant réalisé à la surface d'un support (6), amovible et apte à être ultérieurement séparé par rapport au substrat, sur des zones de ladite surface en contact électrique avec les plots du substrat.

Multilayer Wiring Substrate

CONDENSER BUILT IN WIRING BOARD, MANUFACTRUING METHOD OF THE CONDENSER AND THE WIRING BOARD

핫 스팟 열 관리 특징부를 갖춘 3ＤＩＣ 패키징

... 패키지는 전도성 층을 갖는 기판을 포함하며, 전도성 층은 노출된 부분을 포함한다. 다이 스택은 기판 위에 배치되며, 전도성 층에 전기적으로 접속된다. 고 열전도성 재료가 기판 위에 배치되며 전도성 층의 노출된 부분과 접촉한다. 패키지는 또한, 고 열전도성 재료 위에 있고 고 열전도성 재료와 접촉하는 콘투어 링을 포함한다.

METHOD FOR FORMING A CORELESS SUBSTRATE

... 전해 도금을 이용하는 코어리스 기판, 및 그들의 제품을 포함하는 전자 어셈블리가 기술된다. 한 방법은 금속을 포함하는 코어를 제공하는 단계, 및 코어 위에 유전 재료를 형성하는 단계를 포함한다. 이 방법은 또한 금속 영역을 노출하도록 배치되는 비아를 유전 재료에 형성하는 단계를 포함한다. 이 방법은 또한 비아 내에 그리고 금속 영역 위에 금속의 전해 도금을 수행하는 단계를 포함하고, 코어는 비아 내에의 전해 도금 동안에 전원에 전기적으로 결합되어 금속 영역에 전류를 전달한다. 이 방법은 또한 비아 내에의 금속의 전해 도금 이후에 금속 코어를 제거하는 단계를 포함한다. 다른 실시예들이 기술되고 청구된다.

METHOD FOR MANUFACTURING WIRING BOARD

SEMICONDUCTOR PACKAGE

이중 랜드를 갖는 반도체패키지 및 관련된 장치

... 이중 랜드(dual land)를 갖는 반도체패키지를 제공한다. 상기 반도체패키지는 다수의 내부 패드들을 갖는 기판을 구비한다. 반도체 칩이 상기 기판에 부착된다. 상기 반도체 칩은 상기 내부 패드들에 전기적으로 접속된다. 상기 기판에 형성되고 상기 내부 패드들에 전기적으로 접속된 다수의 랜드들을 제공한다. 상기 기판에 형성된 적어도 하나의 우회배선을 제공한다. 상기 우회배선은 제 1 랜드 및 제 2 랜드에 접속된다. 상기 제 1 랜드는 상기 랜드들 중 선택된 하나이고, 상기 제 2 랜드는 상기 랜드들 중 선택된 다른 하나이다. 상기 제 1 랜드 및 상기 제 2 랜드는 상기 랜드들 사이의 평균거리보다 3배 이상 떨어진다.

LEAD-FREE STRUCTURES IN A SEMICONDUCTOR DEVICE

BURIED THERMALLY CONDUCTIVE LAYER FOR EXTRACTING AND SHIELDING HEAT WITH HIGH THERMAL CONDUCTIVITY

PURPOSE: A buried thermally conductive layer for extracting and shielding heat is provided to function as an efficient heat spreading machine for extracting heat which is generated during a circuit operation. CONSTITUTION: Buried heat conductive layers(230) are deposited on a layer(210). The buried heat conductive layers are made of materials with high thermal conductivity. At least one vertical via(240) is connected to the buried heat conductive layers. The vertical via connects all buried heat conductive layers each other wherein all buried heat conductive layers are placed in a device. A heat insulating layer(250) is formed on the buried heat conductive layers. COPYRIGHT KIPO 2012 ...

WIRING BOARD IN WHICH A PAD FOR MOUNTING A SEMICONDUCTOR DEVICE IS INSTALLED AND A MANUFACTURING METHOD THEREOF

PURPOSE: A wiring board is provided to maintain reliability of connection and not to obstruct the miniaturization of wiring and not to cause performance degradation of the wiring board by including a pad for outside connection. CONSTITUTION: A wiring board comprises: Insulating layer(7); a wiring layer installed at the single-side of the insulating layer; a pad for outside connection(1) installed at the other surface of the insulating layer; a surface coating layer(2), which is formed on the outside pad, for connection with the external circuit; a plurality of wiring layers; and a plurality of insulating layers installed between a plurality of wiring layers. The area of the pad for outside connection is smaller than the area of the surface coating layer. The pad for outside connection characterizes to be the pad for mounting the electronic component including the semiconductor device etc. in the wiring board. © KIPO 2009 ...

THERMAL-CONDUCTIVE SUBSTRATE PACKAGE

A substrate material (130) for mounting an integrated circuit (100) contains a non-electrically-conductive mesh (135) of thermally-conductive material. Because the mesh is electrically- non-conductive, it can purposely be configured to contact any and all of the circuit traces (155) that are proximate to the substrate, thereby using the circuit traces (155) as thermally-coupled heat sinks. In a preferred embodiment, the thermally-conductive mesh (135) replaces the structural fiberglass mesh that is conventionally used in substrates, thereby allowing the mesh (135) to serve a dual structural and thermal function. © KIPO & WIPO 2007 ...

COMPOSITION FOR INSULATING CERAMICS AND INSULATING CERAMICS USING THE SAME

A composition for an insulating ceramic which is prepared by mixing a ceramic powder containing MgAl2 O4 and a glass powder containing a silicon oxide in an amount of 30 to 60 mole % in terms of SiO2 and a magnesium oxide in an amount of 20 to 55 mole % in terms of MgO, characterized in that the ceramic powder further comprises Mg2SiO4 or TiO2. The composition for an insulating ceramic is capable of being sintered at a temperature of 1000 °C or lower and can be sintered together with Au or Cu, and the sintering of the composition provides an insulating ceramic which has a high Q value and is suitable for a ceramic multi-layer substrate to be used in a high frequency region. © KIPO & WIPO 2007 ...

전자 소자 및 이의 제조 방법

... 개시된 전자 소자 및 제조 방법은 일면에는 제1 전기 배선이 형성되고, 타면은 두께를 감소시킴에 의해 접었다 펼칠 수 있는 플렉시블한 구조를 갖도록 구비되는 플렉시블 칩; 상기 플렉시블 칩이 손상되는 것을 방지하도록 상기 플렉시블 칩의 타면에 구비되는 보호 필름; 및 제2 전기 배선이 형성된 일면을 갖고, 플렉시블한 구조를 갖도록 구비되는 플렉시블 기판을 포함하고, 상기 플렉시블 칩의 제1 전기 배선과 상기 플렉시블 기판의 제2 전기 배선을 서로 마주보게 배치하도록 구비시킴으로써 상기 제1 전기 배선과 상기 제2 전기 배선 사이를 전기적으로 연결시킬 수 있다.

PRINTED WIRING BOARD, A SEMICONDUCTOR PACKAGE, AND A MANUFACTURING METHOD THEREOF, CAPABLE OF PREVENTING DAMAGE TO A SOLDER BUMP OF A SEMICONDUCTOR CHIP

PURPOSE: A printed wiring board, a semiconductor package, and a manufacturing method thereof are provided to suppress breakdown of a solder bump by uniformly distributing mechanical stress into a connection pad and an under bump metal. CONSTITUTION: A printed wiring board comprises a dielectric layer(26a) and a connection pad(24). A dielectric layer has a main surface. A connection pad is buried in the dielectric layer. The connection pad includes a plate part(36) and a contact part(38). The plate part has a front side and a rear side. The contact part is positioned on the front side of the plate part. The main surface of the contact part is exposed to the main surface of the dielectric layer. COPYRIGHT KIPO 2010 ...

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Disclosed is a semiconductor package where a semiconductor chip and a mounting device are packaged together. The semiconductor package according to the embodiment of the present invention includes a semiconductor chip, a mounting block where a first mounting device is mounted on a substrate having a circuit, and a wiring part which electrically connects the semiconductor chip and the mounting block. So, the semiconductor chip can be separated from the substrate having the mounting device. COPYRIGHT KIPO 2016 ...

MULTILAYER WIRING SUBSTRATE AND A MANUFACTURING METHOD THEREOF, USING AN INORGANIC INSULATION FILM WITH A HIGH WITHSTAND VOLTAGE

PURPOSE: A multilayer wiring substrate and a manufacturing method thereof are provided to increase a wiring density of the multilayer wiring substrate by minimizing a thermal stress applied to a via. CONSTITUTION: A multilayer wiring substrate includes plural wiring layers(13a-13e), interlayer dielectrics(15ab,15bc,15cd,15de), and a via(17'). The via couples upper and lower wiring layers with each other through at least two interlayer dielectrics. At least some of the interlayer dielectrics are made of an inorganic insulation film. The via couples the upper and lower wiring layers through at least two interlayer dielectrics. The via between the upper and lower wiring layers is made of a single via which penetrates the inorganic interlayer dielectrics. All of the interlayer dielectrics are made of the inorganic insulation films according to a cold CVD(Chemical Vapor Deposition) process. © KIPO 2008 ...

표면 상호 연결부 및 무전해 충진물을 포함하는 캐비티를 포함하는 패키지 기판

... 일부 신규한 특징들은, 제 1 유전체 층, 제 1 상호연결부, 제 1 캐비티 및 제 1 무전해 금속 층을 포함하는 기판과 관련된다. 제 1 유전체 층은 제 1 표면 및 제 2 표면을 포함한다. 제 1 상호연결부는 제 1 유전체 층의 제 1 표면 상에 있다. 제 1 캐비티는 제 1 유전체 층의 제 1 표면을 관통한다. 제 1 무전해 금속 층은 적어도 부분적으로 제 1 캐비티에 형성된다. 제 1 무전해 금속 층은 제 1 유전체 층 내에 매립되는 제 2 상호연결부를 정의한다. 일부 구현들에서, 기판은 코어 층을 더 포함한다. 코어 층은 제 1 표면 및 제 2 표면을 포함한다. 코어 층의 제 1 표면은 제 1 유전체 층의 제 2 표면에 커플링된다. 일부 구현들에서, 기판은 제 2 유전체 층을 더 포함한다.

집적 회로 패키지 기판

... 본 개시 내용의 실시예는 이중 표면 마감 패키지 기판 어셈블리를 위한 기술 및 구성에 관한 것이다. 일 실시예에서, 방법은 패키지 기판의 제1 측부 상에 제1 라미네이션층을 증착 및 패키지 기판의 제2 측부 상에 배치된 하나 이상의 전기 콘택트 상에 제1 표면 마감재를 증착하고, 패키지 기판의 제1 측부로부터 제1 라미네이션층을 제거하고, 패키지 기판의 제2 측부 상에 제2 라미네이션층을 증착 및 패키지 기판의 제1 측부 상에 배치된 하나 이상의 전기 콘택트 상에 제2 표면 마감재를 증착하고, 패키지 기판의 제2 측부로부터 제2 라미네이션층을 제거하는 것을 포함한다. 다른 실시예들이 기술되고/되거나 청구될 수 있다.

Printed circuit board and method of manufacturing printed circuit board

Chip capacitors are arranged in a core board for a printed wiring board. This makes it possible to reduces the distance between an IC chip and the chip capacitor and to reduce the loop inductance. The core board, which is a lamination consisting of a first resin board, a second resin board, and a third resin board, has a sufficient strength. COPYRIGHT KIPO & WIPO 2010 ...

CRACK RESISTANT INTERCONNECT MODULE

A laminated flip-chip interconnect package comprising a substrate having a chip attach surface and a board attach surface that define contact pads for attachment to corresponding pads on the chip and board wherein the substrate board surface comprises at least one solid plane covering the chip attach surface region near at least one chip corner. In one embodiment, the solid plane comprises a dielectric material, optionally covered with a soldermask or coverlay material. In an alternate embodiment, the solid plane comprises a metal, optionally covered with a soldermask or coverlay material. © KIPO & WIPO 2007 ...

PACKAGE METHOD FOR ELECTRONIC COMPONENTS BY THIN SUBSTRATE

FAN-OUT SEMICONDUCTOR PACKAGE

The present disclosure relates to a fan-out semiconductor package which includes a first connection member with a through hole, first and second semiconductor chips arranged in the through hole, a sealing member for sealing at least a part of the first and second semiconductor chips, and a second connection member arranged on the first connection member and the active surfaces of the first and second semiconductor chips. A rewiring layer of the second connection member is connected to a first connection pad and a second connection pad through a first conductor and a second conductor, respectively. The second conductor is higher than the first conductor. Accordingly, the present invention can obtain high reliability and high performance. COPYRIGHT KIPO 2018 ...

INSULATING SHEET, PROCESS FOR PRODUCING SAME, AND PROCESS FOR PRODUCING STRUCTURE USING THE INSULATING SHEET

SEMICONDUCTOR DEVICE

An objective of the present invention is to improve the performance of a semiconductor device. A high-speed transmission path (SGP1) of a semiconductor device (PKG1) includes a connection portion (CP1) for electrically connecting a semiconductor chip (10) and an interposer (40); a connection portion (CP2) for connecting the interposer (40) and a wiring substrate (30); and an external terminal portion (CP3) formed on the lower surface (3b) of the wiring substrate (30). In addition, the high-speed transmission path (SGP1) includes a transmission portion (TP1) installed in the interposer (40) and electrically connecting the connection portion (CP1) and the connection portion (CP2), and a transmission portion (TP2) installed on the wiring substrate (30) and electrically connecting the connection portion (CP2) and the external terminal portion (CP3). Moreover, in the high-speed transmission path (SGP1), one end portion thereof is connected to a branch portion (BR1) in the middle of the transmission ...

Wiring board and method for manufacturing the same

A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

Microelectronic packages with dual or multiple-etched flip-chip connectors

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Ceramic electronic component and wiring board

A ceramic electronic component includes a ceramic element body having a substantially rectangular parallelepiped shape, and first and second external electrodes. The first and second external electrodes are provided on a first principal surface. Portions of the first and second external electrodes project further than the other portions in a thickness direction. A projecting portion of the first external electrode is provided at one end of the first external electrode in a length direction and a second projecting portion of the second external electrode is provided at another end of the second external electrode in the length direction. Thus, a concave portion is provided between the projecting portions, and a portion of the first principal surface provided between the first and second external electrodes is exposed.

Circuit substrate and manufacturing method thereof and package structure and manufacturing method thereof

A circuit substrate includes the following elements. A conductive layer and a dielectric layer are disposed on an inner circuit structure in sequence, and a plurality of conductive blind vias are embedded in the dielectric layer and connected to a portion of the conductive layer. A plating seed layer is disposed between each of the first blind vias and the first conductive layer. Another conductive layer is disposed on the dielectric layer, wherein a portion of the another conductive layer is electrically connected to the conductive layer through the conductive blind vias. A third plating seed layer is disposed between the third conductive layer and each of the first blind vias and on the first dielectric layer.

Energy Conditioning Circuit Arrangement for Integrated Circuit

The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.

Semiconductor chip device with polymeric filler trench

A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Package substrate unit and method for manufacturing package substrate unit

A semiconductor chip mounting layer of a package substrate unit includes an insulation layer, a conductive seed metal layer formed on the top surface of the insulation layer, conductive pads formed on the top surface of the conductive seed metal layer, metal posts formed substantially in the central portion on the top surface of the conductive pads, and a solder resist layer that is formed to surround the conductive pads and the metal posts.

Multilayer printed wiring board and method for manufacturing multilayer printed wiring board

A method for manufacturing a multilayer printed wiring board includes preparing a first resin insulative material having a first conductive circuit on or in the first resin insulative material, forming a second resin insulative material on the first resin insulative material and the first conductive circuit, forming on a surface of the second resin insulative material a first concave portion to be filled with a conductive material for formation of a second conductive circuit, forming on the surface of the second resin insulative material a pattern having a second concave portion and post portions to be filled with the conductive material for formation of a plane conductor, and filling the conductive material in the first concave portion and the second concave portion such that the second conductive circuit and the plane conductor are formed.

Chip Capacitor Precursors

A capacitive precursor includes electrically conductive material layers stacked on a substrate. The electrically conductive layers provide first and second patterns. The patterns each include overlaying areas free of the electrically conductive material. The first pair of areas overlay areas of the second pattern having the electrically conductive material and the second pair of areas overlay areas of the first pattern having the electrically conductive material. Dielectric layers are interposed between neighboring electrically conductive material layers for electrical isolation. One or more capacitive precursors can be dropped onto or into a board and during assembly of a packaged semiconductor device and have electrically conducting layers associated with its respective plates connected together to form a capacitor during assembly using conventional assembly steps.

Method of manufacturing circuit board

Disclosed herein is a method of manufacturing a circuit board. The method of manufacturing a circuit board according to a preferred embodiment of the present invention is configured to include (A) forming a cavity 115 for a bump on one surface 111 of a carrier 110, (B) forming a bump 130 in the cavity 115 for the bump through an electroplating process, (C) laminating an insulating layer 140 on one surface 111 of the carrier 110 so as to apply the bump 130, (D) forming a circuit layer 150 including a via 155 connected with the bump 130 on the insulating layer 140, and (E) removing the carrier 110, whereby the process of forming separate solder balls is removed by forming the cavities 111 for the bumps in the carriers 110 to form the bumps, thereby simplifying the process of manufacturing a circuit board and reducing the lead time.

Integrated circuit packaging system with connection structure and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.

Laminated wiring board

In a multilayer wiring board 1, a low resistance silicon substrate 2 having a predetermined resistivity and a high resistance silicon substrate 4 having a resistivity higher than the predetermined resistivity are stacked while interposing an insulating layer 3 therebetween. The low resistance silicon substrate 2 is provided with an electric passage part 6 surrounded by a ring-shaped groove 5, while a wiring film 13 electrically connected to the electric passage part 6 through an opening 8 of the insulating layer 3 is disposed on a rear face 4 b of the high resistance silicon substrate 4 and an inner face 11 a of a recess 11. Since the high resistance silicon substrate 4 is thus provided with the wiring film 13, an optical semiconductor element 20 and an electronic circuit element 30 which differ from each other in terms of the number and positions of electrode pads can be electrically connected to each other on the front and rear face sides of the multilayer wiring board 1.

Semiconductor Device and Method of Forming an Inductor Within Interconnect Layer Vertically Separated from Semiconductor Die

A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer.

Reduced pth pad for enabling core routing and substrate layer count reduction

Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.

Semiconductor chip assembly and method for making same

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

Semiconductor package and method of manufacturing the same

Provided are a semiconductor package and a method of manufacturing the same. a substrate including a first face and a second face, wherein the first and second faces face each other; a first ground pattern disposed on the first face; a second ground pattern disposed on the second face; a plurality of ground via plugs which connect the first ground pattern and the second ground pattern, wherein the plurality of ground via plugs penetrate the substrate; and a first aluminum oxide film interposed between the plurality of ground via plugs, wherein a ground voltage is applied to the plurality of ground via plugs. The semiconductor package may be manufactured using an anodic oxidation process.

Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices

A method is for making an electronic device and includes forming an interconnect layer stack on a sacrificial substrate and having a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers. The method also includes laminating and electrically joining through an intermetallic bond a liquid crystal polymer (LCP) substrate to the interconnect layer stack on a side thereof opposite the sacrificial substrate. The method further includes removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at least one first device to the lowermost patterned electrical conductor layer.

Packaged semiconductor device for high performance memory and logic

A packaged semiconductor device is disclosed. The device comprises a substrate having multiple layers between first and second oppositely disposed faces, and a cavity with an opening at the first face to nest at least one integrated circuit memory device. Logic circuitry is disposed on the second face and includes contacts for electrically coupling to the stacked integrated circuit memory devices. The logic circuitry is coupled to electrical contacts formed on the first face through first electrical paths formed in the multiple layers of the substrate, the first electrical paths including conductive traces and vias.

Semiconductor apparatus, method for manufacturing the same and electric device

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Wiring substrate and method of manufacturing the same

A wiring substrate includes a structure in which a plurality of wiring layers are stacked through insulating layers intervening therebetween, and which has a first surface side and a second surface side, the first surface side where a semiconductor element is to be mounted, the second surface side being located at an opposite side to the first surface side, an interposer buried in an outermost one of the insulating layers located at the first surface side, and electrically connected to the semiconductor element to be mounted, and a sheet-shaped member buried in an outermost one of the insulating layers located at the second surface side, wherein, the interposer and the sheet-shaped member are disposed at symmetrical positions symmetrical each other.

Multilayer resin sheet and method for producing the same, method for producing cured multilayer resin sheet, and highly thermally conductive resin sheet laminate and method for producing the same

A multilayer resin sheet is constituted by including a resin layer containing an epoxy resin having a mesogenic skeleton, a curing agent and an inorganic filler, and an insulating adhesive layer formed on at least either of the surfaces of the resin layer. A cured multilayer resin sheet originated from the multilayer resin sheet has high thermal conductivity, good insulation and adhesive strength, and, further, superior thermal shock resistance, and is suitable as an electric insulating material to be used for an electric or electronic device.

Coreless layer laminated chip carrier having system in package structure

A substrate for use in a laminated chip carrier (LCC) and a system in package (SiP) device having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can include thermoset and thermoplastic resin.

Wiring Board, Semiconductor Device, and Method for Manufacturing Wiring Board

A wiring board provided with a silicon substrate including a through hole that communicates a first surface and a second surface of the silicon substrate. A capacitor is formed on an insulating film, which is applied to the silicon substrate, on the first surface and a wall surface defining the through hole. A capacitor part of the capacitor includes a first electrode, a dielectric layer, and a second electrode that are sequentially deposited on the insulating film on the first surface and the wall surface of the through hole. A penetration electrode is formed in the through hole covered by the first electrode, the dielectric layer, and the second electrode of the capacitor part.

Low-noise flip-chip packages and flip chips thereof

A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down manner onto the first main face of the carrier substrate via a connection array, wherein: the flip-chip substrate comprises at least first and second circuitry portions spaced apart from one another; the flip-chip substrate comprises a substrate-contact boundary located between the first and second circuitry portions; and each of the first circuitry portion, the second circuitry portion and the substrate-contact boundary has its own separate signal-reference connection extending via a respective connection of the connection array through the carrier substrate to a respective electrical contact at the second main face of the carrier substrate for connection to a common signal-reference element in an external circuit.

Semiconductor package including an external circuit element

Circuit elements such as DC blocking capacitors used in communication such as a serial communication link between two or more electrical components are disposed in pre-existing openings in a support structure that supports at least one of the two electrical components. The openings may be plated and used for signal transmission from the one electrical component to a printed circuit board (PCB) supporting the substrate. The DC blocking capacitors may be oriented substantially vertically, and a non-conducting material may be disposed in each opening in the substrate such that the non-conducting material at least partially surrounds and fixes the orientation of the DC blocking capacitor disposed in the opening.

Circuit module

A circuit module includes a substrate that has a substantially rectangular parallelepiped shape and includes a plurality of inner conductive layers, an electronic component disposed on a first main surface of the substrate, an insulating layer disposed on the first main surface of the substrate so as to cover the electronic component, a shielding layer disposed on a surface of the insulating layer, and a ground electrode connected to the plurality of inner conductive layers. At least two of the inner conductive layers are directly connected to the shielding layer.

Thermal substrate

An organic substrate capable of providing effective heat transfer through its entire thickness by the use of parallel, linear common thermally conductive openings that extend through the substrate, the substrate having thin dielectric layers bonded together to form an integral substrate structure. The structure is adapted for assisting in providing cooling of high temperature electrical components on one side by effectively transferring heat from the components to a cooling structure positioned on an opposing side. Methods of making the substrate are also provided, as is an electrical assembly including the substrate, component and cooling structure.

Laminated and sintered ceramic circuit board, and semiconductor package including the circuit board

A circuit board that can decrease thermal stress acting between a semiconductor element and a board in association with temperature alteration and has high mechanical strength (rigidity) as a whole board (including a multilayer wiring layer) is provided. Ceramic base material having a coefficient of thermal expansion close to that of a semiconductor element and inner layer wiring are integrally sintered, and the circuit board is configured so that fine-lined conductor structure corresponding to a multilayer wiring layer in the inner layer wiring has predetermined width, intralayer interval and interlayer interval. Thereby, thermal stress acting between a semiconductor element and the board when the board is exposed to temperature alteration in a condition where it is joined with the semiconductor element is suppressed, rigidity of the board is maintained, and its reliability against temperature cycle is increased.

Substrate Dicing

A method and apparatus for separating a substrate into individual dies and the resulting structure is provided. A modification layer, such as an amorphous layer, is formed within the substrate. A laser focused within the substrate may be used to create the modification layer. The modification layer creates a relatively weaker region that is more prone to cracking than the surrounding substrate material. As a result, the substrate may be pulled apart into separate sections, causing cracks the substrate along the modification layers. Dice or other components may be attached to the substrate before or after separation.

Surface acoustic wave device and production method therefor

A surface acoustic wave device includes a surface acoustic wave element including a plurality of electrode pads, and a mount substrate. The surface acoustic wave element is flip-chip mounted on a die-attach surface of the mount substrate by bumps made of Au. The mount substrate includes at least one resin layer including via-holes, a plurality of mount electrodes provided on the die-attach surface of the mount substrate, and via-hole conductors. The mount electrodes are bonded to the electrode pads via the bumps. The via-hole conductors are provided in the via-holes. At least one of each of the electrode pads and each of the mount electrodes includes a front layer made of Au. At least one of the via-hole conductors is located below the corresponding bump.

High io substrates and interposers without vias

An interconnection component includes a substrate having first and second opposed major surfaces defining a thickness of less than 1000 microns and a first slot extending between the first and second surfaces, the first slot being enclosed by the substrate at the first and second surfaces. The first slot defines an edge surface between the first surface and the second surface. First conductive traces extend along the first surface and are electrically connected with first contact pads that overlie the first surface. Second conductive traces extend along the second surface and electrically connected with second contact pads that overlie the second surface. Interconnect traces extend along the edge surface of the first slot. Each interconnect trace directly connects at least one first trace with at least one second trace.

SURFACE DEPRESSIONS FOR DIE-TO-DIE INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS

Stacked microelectronic dies employing die-to-die interconnects and associated systems and methods are disclosed herein. In one embodiment, a stacked system of microelectronic dies includes a first microelectronic die, a second microelectronic die attached to the first die, and a die-to-die interconnect electrically coupling the first die with the second die. The first die includes a back-side surface, a surface depression in the back-side surface, and a first metal contact located within the surface depression. The second die includes a front-side surface and a second metal contact located at the front-side surface and aligned with the first metal contact of the first die. The die-to-die interconnect electrically couples the first metal contact of the first die with the second metal contact of the second die and includes a flowable metal layer that at least partially fills the surface depression of the first die. 1. An interconnect structure for electrically coupling a first microelectronic die with a second microelectronic die , comprising:a metal interconnect extending through the first die to a back-side of the first die and projecting beyond a recessed surface at the back-side of the die;a metal contact of the second die aligned with the interconnect; anda layer of reflowed metal at least partially surrounding the interconnect and electrically coupling the interconnect to the metal contact of the second die, the layer of reflowed metal conforming to a shape defined by the recessed surface, the interconnect, and the metal contact of the second die.2. The interconnect structure of claim 1 , further comprising a dielectric layer positioned between the layer of reflowed metal and the recessed surface of the substrate.3. The interconnect structure of claim 1 , further comprising an under bump metallization layer positioned between the layer of reflowed metal and a portion of the interconnect.4. The interconnect structure of wherein the recessed surface claim 1 , the ...

Wiring substrate and method of manufacturing the same

Embodiments of the present invention provide a wiring substrate which is excellent in terms of the reliability of connection between the wiring substrate and a semiconductor chip. In some embodiments the wiring substrate comprises a first build-up layer in which resin insulation layers and conductor layers are laminated alternately. The outermost conductor layer can include a plurality of connection terminal portions to which a semiconductor chip is flip-chip connected. The plurality of connection terminal portions can be exposed through openings of a solder resist layer. Each of the connection terminal portions includes a connection region to which a connection terminal of the semiconductor chip is to be connected, and a wiring region which extends in a planar direction from the connection region and which is narrower than the connection region. The surface of the wiring region has a solder wettability lower than that of the surface of the connection region.

Radiation-shielded semiconductor device

A semiconductor device is disclosed including an electromagnetic radiation shield. The device may include a substrate having a shield ring defined in a conductance pattern on a surface of the substrate. One or more semiconductor die may be affixed and electrically coupled to the substrate. The one or more semiconductor die may then be encapsulated in molding compound. Thereafter, a metal may be plated around the molding compound and onto the shield ring to form an EMI/RFI shield for the device.

Multi-piece substrate

A multi-piece substrate includes a frame portion, and a unit portion in which multiple wiring boards is arrayed. The frame portion is formed on the periphery of the unit portion, the wiring boards have semiconductor elements built in the wiring boards, respectively, and the frame portion has multiple slits formed such that the slits have openings on the periphery of the frame portion.

System in package process flow

A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.

Package Structures and Methods for Forming the Same

A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A solder region is disposed in the polymer region and electrically coupled to the redistribution line. The solder region includes a second flat top surface not higher than the first flat top surface.

Packages with Passive Devices and Methods of Forming the Same

A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM.

Package carrier and manufacturing method thereof

A manufacturing method of a package carrier is provided. A supporting board having an upper surface which a patterned circuit layer formed thereon is provided. A portion of the upper surface is exposed by the patterned circuit layer. An insulating layer and a conducting layer located at a first surface of the insulating layer are laminated onto the patterned circuit layer. The patterned circuit layer and the exposed portion of the upper surface are covered by the insulating layer. Plural conductive connection structures are formed on the patterned circuit layer. Plural of pads respectively connecting the conductive connection structures and exposing a portion of the first surface of the insulating layer is defined by patterning the conductive layer. The supporting board is removed so as to expose a second surface of the insulating layer. The second surface and a bonding surface of the patterned circuit layer are coplanar.

Methods and Apparatus for Thinner Package on Package Structures

Methods and apparatus for thinner package on package (“PoP”) structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate and a plurality of package on package connectors extending from a bottom surface; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface; wherein at least the second substrate is formed of a plurality of layers of laminated dielectric and conductors. In another embodiment a cavity is formed on the bottom surface of the first substrate and a portion of the another integrated circuit extends partially into the cavity. Methods for making the PoP structures are disclosed.

Transmission line transition having vertical structure and single chip package using land grip array coupling

An apparatus for a single chip package using Land Grid Array (LGA) coupling is provided. The apparatus includes a multi-layer substrate, at least one integrated circuit chip, and a Printed Circuit Board (PCB). The a multi-layer substrate has at least one substrate layer, has at least one first chip region and at least one second chip region in a lowermost substrate layer, configures a transmission line transition of a vertical structure for transmitting a signal from at least one integrated circuit chip coupled in the first chip region in a coaxial shape or in a form of a Co-Planar Waveguide guide (CPW), and has an LGP coupling pad for connecting with a Printed Circuit Board (PCB) in the lowermost layer. The at least one integrated circuit chip is coupled in the first chip region and the second chip region. The PCB is connected with the multi-layer substrate using the LGA coupling via the LGA coupling pad.

SEMICONDUCTOR DEVICE WITH DIE STACK ARRANGEMENT INCLUDING STAGGERED DIE AND EFFICIENT WIRE BONDING

A semiconductor die package is disclosed. An example of the semiconductor package includes a first group of semiconductor die interspersed with a second group of semiconductor die. The die from the first and second groups are offset from each other along a first axis and staggered with respect to each other along a second axis orthogonal to the first axis. A second example of the semiconductor package includes an irregular shaped edge and a wire bond to the substrate from a semiconductor die above the lowermost semiconductor die in the package. 1. A semiconductor device , comprising:a substrate;a first semiconductor die mounted on the substrate, an x-axis and a y-axis being defined parallel with orthogonal edges of the first semiconductor die;a second semiconductor die mounted on top of the first semiconductor die, the second semiconductor die being offset along the x-axis with respect to the first semiconductor die, and the second semiconductor die being staggered along the y-axis with respect to the first semiconductor die; anda third semiconductor die mounted on top of the second semiconductor die, the third semiconductor die being offset along the x-axis with respect to the second semiconductor die, and the third semiconductor die being staggered along the y-axis to align with the first semiconductor die along the y-axis.2. The semiconductor device of claim 1 , further comprising a fourth semiconductor die mounted on top of the third semiconductor die claim 1 , the fourth semiconductor die being offset along the x-axis with respect to the third semiconductor die claim 1 , and the fourth semiconductor die being staggered along the y-axis to align with the second semiconductor die along the y-axis.3. The semiconductor device of claim 2 , further comprising:die bond pads on each of the first, second, third and fourth semiconductor die;a first set of bond wires connecting corresponding die bond pads on the first and third semiconductor die with the substrate; anda ...

Electronic component element housing package

An electronic component element housing package is produced by firing a ceramic substrate for housing an electronic component element and a metal layer for bonding to the ceramic substrate to form an electrical path, simultaneously in a reducing atmosphere. The ceramic substrate comprises alumina (Al 2 O 3 ), a partially stabilized zirconia by forming solid solution with yttria (Y 2 O 3 ) and a sintering agent. The sintering agent comprises magnesia (MgO), and at least 1 type selected from silica (SiO 2 ), calcia (CaO), or manganese oxides (MnO, MnO 2 , Mn 2 O 3 , Mn 3 O 4 ).

Semiconductor Device and Method of Forming a Robust Fan-Out Package including Vertical Interconnects and Mechanical Support Layer

A semiconductor device has a semiconductor die. An encapsulant is deposited around the semiconductor die. An interconnect structure having a conductive bump is formed over the encapsulant and semiconductor die. A mechanical support layer is formed over the interconnect structure and around the conductive bump. The mechanical support layer is formed over a corner of the semiconductor die and over a corner of the interconnect structure. An opening is formed through the encapsulant that extends to the interconnect structure. A conductive material is deposited within the opening to form a conductive through encapsulant via (TEV) that is electrically connected to the interconnect structure. A semiconductor device is mounted to the TEV and over the semiconductor die to form a package-on-package (PoP) device. A warpage balance layer is formed over the encapsulant opposite the interconnect structure.

Electronic device

An electronic device comprising a laminate comprising pluralities of insulator layers each provided with conductor patterns, and an amplifier-constituting semiconductor device mounted to a mounting electrode formed on an upper surface of the laminate, a first ground electrode being formed on an insulator layer near an upper surface of the laminate; a second ground electrode being formed on an insulator layer near a lower surface of the laminate; the first ground electrode being connected to the mounting electrode through pluralities of via-holes; conductor patterns constituting the first circuit block being disposed in a region below the amplifier-constituting semiconductor device between the first ground electrode and the second ground electrode; and at least part of a conductor pattern for a line connecting the first circuit block to the amplifier-constituting semiconductor device being disposed on an insulator layer sandwiched by the mounting electrode and the first ground electrode.

Wiring substrate and method of manufacturing the same

There is provided a wiring substrate. The wiring substrate includes: an insulating layer; first electrode pads having first exposed surfaces, the first exposed surfaces being exposed from the insulating layer; and second electrode pads having second exposed surfaces, the second exposed surfaces being exposed from the insulating layer. There is a level difference between the first exposed surfaces and the second exposed surfaces.

Power line filter for multidimensional integrated circuits

An interposer element in a multidimensional integrated circuit with stacked elements has one or more conductors, especially power supply lines, coupled through decoupling networks defining low impedance shunts for high frequency signals to ground. The interposer has successive tiers including silicon, metal and dielectric deposition layers. The decoupling network for a conductor has at least one and preferably two reactive transmission lines. A transmission line has an inductor in series with the conductor and parallel capacitances at the inductor terminals. The inductors are formed by traces in spaced metal deposition layers forming coil windings and through vias connecting between layers to permit conductor crossovers. The capacitances are formed by MOScaps in the interposer layers. An embodiment has serially coupled coils with capacitances at the input, output and junction between the coils, wherein the coils are magnetically coupled to form a transformer.

Stacked module

A stacked module includes a first multilayer substrate including an opening having a stepwise wall face, and a first transmission line including a first grounding conductor layer, a second multilayer substrate supported on a stepped portion of the stepwise wall face and including a second transmission line including a second grounding conductor layer, a first chip mounted on a bottom of the opening and coupled to a third transmission line provided on the first multilayer substrate, and a second chip mounted on the front face of the second multilayer substrate and coupled to the second transmission line. A face to which the second grounding conductor layer or a fourth grounding conductor layer coupled thereto is exposed is joined to the stepped portion to which the first grounding conductor layer or a third grounding conductor layer coupled thereto is exposed, and the first and second grounding conductor layers are coupled.

Wiring substrate, manufacturing method thereof, and semiconductor package

A disclosed wiring substrate includes an insulating layer, a recess formed on a surface of the insulating layer, and an alignment mark formed inside of the recess, wherein a face of the alignment mark is roughened, recessed from the surface of the insulating layer, and exposed from the recess.

Semiconductor device and production method of the same

A semiconductor device capable of performing sufficient power supply while suppressing an increase in a manufacturing cost. The semiconductor device has a semiconductor substrate, a multilayer interconnection layer provided over the semiconductor substrate, an Al wiring layer that is provided over the multilayer interconnection layer and has pad parts, and a redistribution layer that is provided over the Al wiring layer and is coupled with the Al wiring layer, in which the redistribution layer is comprised of a metal material whose electric resistivity is lower than that of Al and is not formed over the pad parts.

FAN-OUT HIGH-DENSITY PACKAGING METHODS AND STRUCTURES

A fan-out high-density packaging method includes providing a packaging substrate, forming a stripping film on the packaging substrate, and forming a first protection layer on the stripping film and pre-designed photolithography pattern openings on the first protection layer. The method also includes forming a metal redistribution layer on the surface of the first protection layer and in the photolithography pattern openings, forming a second protection layer on the first protection layer and partially exposing the metal redistribution layer, and forming at least one package layer on the second protection layer. Each of at least one package layer includes a straight mounting layer, a sealant layer, and a wiring layer formed in sequence, and the package layer connects the metal redistribution layer through the wiring layer. Further, the method includes forming at least one top-level package layer on top of the at least one package layer, removing the packaging substrate and the stripping film to expose the metal redistribution layer in the first protection layer, and planting metal solder balls on the exposed metal redistribution layer. 1. A method for fan-out high-density packaging , comprising:providing a packaging substrate;forming a stripping film on the packaging substrate;forming a first protection layer on the stripping film and pre-designed photolithography pattern openings on the first protection layer;forming a metal redistribution layer on the surface of the first protection layer and in the photolithography pattern openings;forming a second protection layer on the first protection layer and partially exposing the metal redistribution layer;forming at least one package layer on the second protection layer, wherein each of at least one package layer includes a straight mounting layer, a sealant layer, and a wiring layer formed in sequence, and the package layer connects the metal redistribution layer through the wiring layer;forming at least one top-level ...

Copper Feature Design for Warpage Control of Substrates

An approach is provided in which a laminate substrate includes top layers, bottom layers, and a core layer. The top layers are positioned between the core layer and a top surface metallurgy (TSM) layer and include at least one top conductive layer. The bottom layers are positioned between the core layer and a bottom surface metallurgy (BSM) layer and include at least one bottom conductive layer includes a material void pattern that is based upon the top conductive layer and reduces warpage of the laminate substrate.

Package substrate and die spacer layers having a ceramic backbone

A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.

Alignment between layers of multilayer electronic support structures

A process for alignment a subsequent layer over a previous layer comprising metal features or vias encapsulated in dielectric material comprising the steps of: thinning and planarizing the dielectric material to create a smooth surface of dielectric material and coplanar exposed ends of the via posts; imaging the smooth surface; discerning the position of the end of at least one feature, and using the position of the end of at least one via feature as a registration mark for aligning the subsequent layer.

WIRING BOARD

A wiring board in which a semiconductor element connection pad formed on a strip-shaped wiring conductor and an electrode of a semiconductor element are firmly connected together, the wiring board having excellent electrical insulation between the semiconductor element connection pads which are adjacent to each other. 1. A wiring board comprising:an insulating board having, on an upper surface thereof, a mounting portion in which a semiconductor element is mounted;a plurality of strip-shaped wiring conductors arranged side by side on the upper surface of the insulating board, and extending in an outer peripheral portion of the mounting portion in a manner to be perpendicular to an outer periphery of the semiconductor element;a semiconductor element connection pad formed, on each of the strip-shaped wiring conductors, in a protruding shape and in a width identical with a width of the strip-shaped wiring conductor; anda solder resist layer adhered to the upper surface of the insulating board, and having a slit-like opening along the outer periphery of the semiconductor element, so that the semiconductor element connection pad and a part of the strip-shaped wiring conductor are exposed in the slit-like opening,wherein the semiconductor element connection pad is formed of a first conductor layer which is adhered onto the strip-shaped wiring conductor and has poor solder wettability, and a second conductor layer which is adhered onto an upper surface of the first conductor layer and has solder wettability.2. The wiring board according to claim 1 ,wherein the first conductor layer is made of nickel or chrome, andthe second conductor layer is made of gold or palladium.3. The wiring board according to claim 2 ,wherein the first conductor layer and the second conductor layer are plating layers.4. The wiring board according to claim 1 ,wherein an oxide film is formed on at least a surface of the strip-shaped wiring conductor that is exposed in the opening.5. The wiring board ...

Stackable semiconductor assemblies and methods of manufacturing such assemblies

Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die.

Method of Packaging a Die

A method of attaching a die to a substrate is disclosed. A major surface of the die has an array of electrical contacts, and is covered with a tape segment having an array of apertures in register with the contacts. Solder balls are inserted into the apertures. The die is positioned against a substrate with the solder balls in register with the die pads on the surface of the substrate, and a heat treatment process is performed to bond the conductive elements to the corresponding bond pads.

Emi shielding semiconductor element and semiconductor stack structure

A semiconductor element is provided, including: a substrate having a plurality of first conductive through holes and second conductive through holes formed therein; a redistribution layer formed on the substrate and having a plurality of conductive pads electrically connected to the first conductive through holes; and a metal layer formed on the redistribution layer and electrically connected to the second conductive through holes. The metal layer further has a plurality of openings for the conductive pads of the redistribution layer to be exposed from the openings without electrically connecting the first metal layer. As such, the metal layer and the second conductive through holes form a shielding structure that can prevent passage of electromagnetic waves into or out of the redistribution layer or side surfaces of the semiconductor element, thereby effectively shield electromagnetic interference.

Semiconductor package with single sided substrate design and manufacturing methods thereof

A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.

Method of fabricating a semiconductor package

A method of fabricating a semiconductor package is provided, including: disposing a semiconductor element on a carrier; forming an encapsulant on the carrier to encapsulant the semiconductor element; forming at least one through hole penetrating the encapsulant; forming a hollow conductive through hole in the through hole and, at the same time, forming a circuit layer on an active surface of the semiconductor element and the encapsulant; forming an insulating layer on the circuit layer; and removing the carrier. By forming the conductive through hole and the circuit layer simultaneously, the invention eliminates the need to form a dielectric layer before forming the circuit layer and dispenses with the conventional chemical mechanical polishing (CMP) process, thus greatly improving the fabrication efficiency.

Wiring board and method for manufacturing wiring board

A wiring board includes a substrate having a cavity, and an electronic component accommodated in the cavity of the substrate. The substrate has a thickness which is greater than a thickness of the electronic component such that a ratio of the thickness of the substrate to the thickness of the electronic component is set in a range of 0.3 or greater and 0.7 or less.

Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device

In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

Passive Devices in Package-on-Package Structures and Methods for Forming the Same

A device includes a polymer. A device die is disposed in the polymer. A passive device includes three Through Assembly Vias (TAVs) penetrating through the polymer, wherein the TAVs are coupled in series. A Redistribution Line (RDL) is underlying the polymer. The RDL electrically couples a first one of the TAVs to a second one of the TAVs.

Method for producing multi-layer substrate and multi-layer substrate

A mounting-completed core parent substrate in which surface mount devices are mounted on both principal surfaces of the core parent substrate including a plurality of the core individual substrates and having a through hole formed in each core individual substrate so as to extend therethrough is formed. Then, resin layers in a partially cured state are formed on both the principal surfaces of the core parent substrate and the resin layers on both the principal surfaces are joined through the through holes so that the resin layers on both principal surfaces of each core individual substrate are joined and integrated to each other at a predetermined region, each core individual substrate being obtained by dividing the core parent substrate. After that, the resin layers are subjected to main curing. Thereafter, the core parent substrate is divided at a predetermined position and separated into the core individual substrates.

Method of manufacturing wiring substrate

A method of manufacturing a wiring substrate, includes, forming an etching stop layer and a first wiring layer on a supporting member, forming a first insulating layer on the first wiring layer, forming a via hole reaching the first wiring layer, and forming the wiring layers of an n-layer and the insulating layers of an n-layer, removing the supporting member and the etching stop layer, thereby forming a build-up intermediate body, forming a second insulating layer on the wiring layer of an n-th layer, and forming a third insulating layer on first wiring layer, forming a via hole reaching the wiring layer of the n-th layer, and forming a via hole reaching the first wiring layer, forming a roughened face to the third insulating layer, and forming a second wiring layer connected to the wiring layer, and forming a third wiring layer connected to the first wiring layer.

Land side and die side cavities to reduce package z-height

A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.

Methods of providing dielectric to conductor adhesion in package structures

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a CVD dielectric material on a package dielectric material, and then forming a conductive material on the CVD dielectric material.

Novel three dimensional integrated circuits stacking approach

A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer die are provided. By forming a first redistribution structure over the interposer die with TSVs, the die(s) bonded to the interposer die can have edge(s) beyond the boundary of the interposer die. In addition, a second redistribution structure may be formed on the opposite surface of the interposer die from the redistribution structure. The second redistribution structure enables reconfiguration and fan-out of bonding structures for external connectors of the interposer die.

Wiring substrate

A wiring substrate includes a first wiring layer, a first insulating layer, a second wiring layer, and a first wiring pattern. The second wiring layer includes a first metal foil that is thinner than the first wiring layer. A first via in the first insulating layer connects the first and second wiring layers. The first via is arranged to fill a first through hole and a first recess. The first through hole extends through the first insulating layer and has a first open end with a first opening diameter and a second open end with a smaller second opening diameter. The first recess is in communication with the first through hole. The first recess has a larger diameter than the second opening diameter. The first metal foil includes a first opening communicating with the first through hole and having a larger opening diameter larger than the first opening diameter.

Thermally Enhanced Package-on-Package (PoP)

A method and structure for providing improved thermal management in multichip and package on package (PoP) applications. A first substrate attached to a second smaller substrate wherein the second substrate is encircled by a heat ring attached to the first substrate, the heat ring comprising heat conducting materials and efficient heat dissipating geometries. The first substrate comprises a heat generating chip and the second substrate comprises a heat sensitive chip. A method is presented providing the assembled structure with increased heat dissipation away from the heat sensitive chip.

Reduced pth pad for enabling core routing and substrate layer count reduction

Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.

Wiring board, semiconductor device, and method of manufacturing wiring board

A wiring board includes a first via hole in a first insulating layer to expose a first wiring layer. A first via in the first via hole includes an end surface. A second wiring layer is arranged on the first insulating layer and the end surface of the first via. A second insulating layer covers the second wiring layer. A second via hole in the second insulating layer exposes the second wiring layer. A second via in the second via hole is arranged above the first via through the second wiring layer. The outer surface of the first insulating layer is lower in surface roughness than an inner surface of the first via hole.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor module having a wiring board, semiconductor assemblies that include a multilayer substrate on which semiconductor elements are mounted, and a sealing part; a cooler; and a heat conduction sheet which is placed between the semiconductor module and the mounting surface of the cooler and which is in contact with the bottom surfaces of the multilayer substrates. The heat conduction sheet has recesses corresponding to at least parts of the outer edges of second electrically conductive plates provided on the bottoms of the multilayer substrates. 1. A semiconductor device comprising:a semiconductor module having at least one semiconductor assembly composed of a multilayer substrate which has an electrically conductive plate provided on a bottom surface side of an insulating substrate and a semiconductor element mounted on the multilayer substrate, and a sealing part which seals the at least one semiconductor assembly except a bottom part of the electrically conductive plate;a cooler which has a mounting surface on which the semiconductor module is mounted; anda heat conduction sheet which is placed between the semiconductor module and the mounting surface of the cooler and is in contact with a bottom surface of the multilayer substrate,wherein the heat conduction sheet has a recess corresponding to at least a part of an outer edge of the bottom part of the electrically conductive plate.2. The semiconductor device according to claim 1 ,wherein the semiconductor module has an M number (M: even number) of the semiconductor assemblies,each of the electrically conductive plates of the M number of semiconductor assemblies has an edge that extends in a lateral direction of the semiconductor module, andthe recess has a shape that corresponds to the edges of the electrically conductive plate of the semiconductor assembly, the edges opposing each other.3. The semiconductor device according to claim 2 ,wherein the mutually opposing ...

WIRING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers, a plurality of circuit layers in contact with the dielectric layers, and a plurality of dam portions in contact with the dielectric layers. The dam portions are stacked on and contact one another. The conductive through via extends through the dam portions. 1. A wiring structure , comprising:a conductive structure including a plurality of dielectric layers, a plurality of circuit layers in contact with the dielectric layers, and a plurality of dam portions in contact with the dielectric layers, wherein the dam portions are stacked on and contact one another; andat least one conductive through via extending through the dam portions;wherein each of the dam portions includes a main portion and an extending portion, the main portion extends through a dielectric layers, the extending portion is disposed on a surface of the dielectric layer, and a width of the main portion gradually increases toward the extending portion.2. The wiring structure of claim 1 , wherein the dam portions and the circuit layers are formed concurrently.3. The wiring structure of claim 1 , wherein each of the dam portions defines a through hole claim 1 , and the at least one conductive through via is disposed in the through holes of the dam portions.4. The wiring structure of claim 1 , wherein each of the dam portions is in a substantially closed ring shape.5. (canceled)6. The wiring structure of claim 1 , wherein each of the dam portions defines a through hole claim 1 , and the extending portion includes an inner extending portion extending inwardly toward the through hole claim 1 , and an outer extending portion extending opposite to the inner extending portion.7. The wiring structure of claim 1 , wherein each of the dam portions includes a seed layer and a conductive material disposed on the seed layer claim 1 , and the seed layer is ...

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

In one example, a semiconductor device comprises a first base substrate comprising a first base conductive structure, a first encapsulant contacting a lateral side of the first base substrate, a redistribution structure (RDS) substrate over the base substrate and comprising an RDS conductive structure coupled with the first base conductive structure, a first electronic component over the RDS substrate and over a first component terminal coupled with the RDS conductive structure, and a second encapsulant over the RDS substrate and contacting a lateral side of the first electronic component. Other examples and related methods are also disclosed herein. 1. A semiconductor device , comprising:a first base substrate comprising a first base conductive structure;a first encapsulant contacting a lateral side of the first base substrate;a redistribution structure (RDS) substrate over the base substrate and comprising an RDS conductive structure coupled with the first base conductive structure;a first electronic component over the RDS substrate and over a first component terminal coupled with the RDS conductive structure; anda second encapsulant over the RDS substrate and contacting a lateral side of the first electronic component.2. The semiconductor device of claim 1 , wherein:the first encapsulant further contacts a top side of the first base substrate.3. The semiconductor device of claim 1 , wherein the first base substrate comprises:a base dielectric structure; andan embedded component in the base dielectric structure.4. The semiconductor device of claim 1 , wherein the first base substrate comprises a coreless substrate.5. The semiconductor device of claim 1 , further comprising:a second electronic component over the RDS substrate and over a second component terminal coupled with the RDS conductive structure.6. The semiconductor device of claim 5 , further comprising:a second base substrate laterally adjacent to the first base substrate and comprising a second base ...

METHODS OF FORMING HIGH DENSITY METAL WIRING FOR FINE LINE AND SPACE PACKAGING APPLICATIONS AND STRUCTURES FORMED THEREBY

Methods of forming microelectronic device structures are described. Those methods may include forming at least one opening through a build up structure and a photo sensitive material disposed on the build up structure, wherein the build up structure comprises a portion of a package substrate, filling the at least one opening with a metal containing nanopaste, and sintering the metal containing nanopaste to form a bulk property metal structure in the at least one opening. 1. A method comprising:forming at least one opening through a build up structure and a photosensitive material disposed on the build up structure, wherein the build up structure comprises a portion of a package substrate wherein forming said at least one opening includes forming a line portion through said photosensitive material and into said buildup structure with a first opening process and forming a via contact portion in said build up structure with a second opening process, wherein the line portion is entirely formed with a single patterning operation, wherein said line portion is wider than said via contact portion;applying a hydrophobic material to a top surface of the photosensitive material;filling the line portion in said photosensitive material and the via contact portion in said build up structure with a metal containing nanopaste, wherein the metal containing nanopaste comprises metal nanoparticles, dispersants, reaction rate control agents, and additives; andsintering the metal containing nanopaste without the application of external pressure to form a bulk property metal structure in the at least one opening, wherein a sintering temperature is less than about 280 degrees Celsius, and wherein sintering the metal containing nanopaste substantially removes the dispersants, reaction rate control agents, and additives from the metal containing nanopaste.23-. (canceled)4. The method of further comprising wherein the single patterning operation of the first opening process is nano ...

SUBSTRATE, LIGHT-EMITTING DEVICE WITH SUBSTRATE, METHOD OF MANUFACTURING SUBSTRATE ASSEMBLY AND METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE WITH SUBSTRATE

A substrate includes a first electrode layer including a first electrode and a second electrode; a second electrode layer including a first electrode and a second electrode; a third electrode layer including a first electrode and a second electrode; and a resin layer. The first electrode layer is arranged on a first side of the resin layer, the third electrode layer is arranged on a second side of the resin layer opposed to the first side, the second electrode layer is positioned in the resin layer, and the first electrode layer is thicker than the second electrode layer. The first and second electrodes of the first electrode layer are positioned inside a peripheral edge of the first side of the resin layer, and the first and second electrodes of the third electrode layer are positioned inside a peripheral edge of the second side of the resin layer. 1. A substrate comprising:a first electrode layer comprising a first electrode and a second electrode;a second electrode layer comprising a first electrode and a second electrode;a third electrode layer comprising a first electrode and a second electrode; anda resin layer, whereinthe first electrode layer is arranged on a first side of the resin layer, the third electrode layer is arranged on a second side that is an opposite side of the first side of the resin layer,the second electrode layer is positioned in the resin layer,the first electrode layer is greater in thickness than the second electrode layer,the first electrode and the second electrode of the first electrode layer are positioned inside a peripheral edge of the first side of the resin layer, andthe first electrode and the second electrode of the third electrode layer are positioned inside a peripheral edge of the second side of the resin layer.2. The substrate according to claim 1 ,wherein the third electrode layer is greater in thickness than the second electrode layer.3. The substrate according to claim 1 ,wherein the first electrode layer is one and half ...

CHIP PACKAGE

An embedded die package and method of manufacture, the die package comprising a die having I/O contact pads in a passivation layer wherein the die contact pads are coupled to a first side of a feature layer by an adhesion/barrier layer, and a layer of pillars extends from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material and wherein the feature layer comprises routing lines that are individually drawn by laser exposure of photoresist under guidance of an optical imaging system for good alignment with both the I/O contact pads of the die and with the subsequently to be deposited pillars that are positioned with respect to the package edges. 1. An embedded die package comprising a die having I/O contact pads in a passivation layer , the die contact pads being coupled to a first side of a feature layer by an adhesion/barrier layer , and a layer of pillars extending from a second side of the feature layer , the die , feature layer and the layer of pillars being encapsulated by a dielectric material wherein the feature layer comprises routing lines that are individually drawn for good alignment with the I/O contact pads of the die and with pillars.2. The embedded die package of wherein the die is misaligned with sides and edges of the package by more than acceptable tolerances for subsequent reliable deposition of routing lines by stencil exposure of a photoresist.3. The embedded die package of wherein sides of the die are angled to sides of the package by an angle of several degrees.4. The embedded die package of wherein one pair of sides of the die are displaced by 3 to 8 microns from a symmetrical position with regards to one pair of parallel sides of the package.5. The embedded die package of wherein each of two pairs of sides of the die are displaced by 3 to 8 microns from a symmetrical position with regards to each of two pairs pair of parallel sides of the package.6. The embedded die ...

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

Provided is a package structure including a composite wafer, a plurality of dies, an underfill, and a plurality of dam structures. The composite wafer has a first surface and a second surface opposite to each other. The composite wafer includes a plurality of seal rings dividing the composite wafer into a plurality of packages; and a plurality of through holes respectively disposed between the seal rings and penetrating through the first and second surfaces. The dies are respectively bonded onto the packages at the first surface by a plurality of connectors. The underfill laterally encapsulates the connectors. The dam structures are disposed on the first surface of the composite wafer to separate the underfill from the through holes. 1. A package structure , comprising: a plurality of seal rings, dividing the composite wafer into a plurality of packages; and', 'a plurality of through holes, respectively disposed between the plurality of seal rings and penetrating through the first and second surfaces;, 'a composite wafer, having a first surface and a second surface opposite to each other, wherein the composite wafer comprisesa plurality of dies, respectively bonded onto the plurality of packages at the first surface by a plurality of connectors;an underfill, laterally encapsulating the plurality of connectors; anda plurality of dam structures, disposed on the first surface of the composite wafer to separate the underfill from the plurality of through hole.2. The package structure of claim 1 , wherein a perimeter of one of the plurality of dies is located within a region enclosed by an inner sidewall of an underlying seal ring.3. The package structure of claim 1 , wherein one of the plurality of seal rings has an outer sidewall closer to an adjacent through hole than an outer sidewall of a corresponding dam structure.4. The package structure of claim 1 , wherein one of the plurality of dam structures surrounds a corresponding through hole.5. The package structure of ...

INTERPOSER AND SEMICONDUCTOR PACKAGE INCLUDING SAME

An interposer including a base layer, a redistribution structure on a first surface of the base layer and including a conductive redistribution pattern, a first lower protection layer on a second surface of the base layer, a lower conductive pad on the first lower protection layer, a through electrode connecting the conductive redistribution pattern and the lower conductive pad, a second lower protection layer on the first lower protection layer, including a different material than the first lower protection layer, and contacting at least a portion of the lower conductive pad, and an indentation formed in an outer edge region of the interposer to provide a continuous angled sidewall extending entirely through the second lower protection layer and through at least a portion of the first protection layer. 1. A semiconductor package comprising:a package substrate;an interposer mounted on the package substrate; anda semiconductor chip mounted on the interposer, a base layer including a first surface and a second surface opposite the first surface;', 'a redistribution structure on the first surface of the base layer, configured to mount the semiconductor chip and including a conductive redistribution pattern;', 'a first lower protection layer on the second surface of the base layer;', 'a lower conductive pad on the first lower protection layer;', 'a through electrode passing through the base layer and the first lower protection layer to electrically connect the conductive redistribution pattern to the lower conductive pad;', 'a second lower protection layer on the first lower protection layer and contacting at least a portion of the lower conductive pad; and', 'an indentation formed in an outer edge region of the interposer to provide a continuous sidewall extending through at least a portion of the second lower protection layer., 'wherein the interposer comprises2. The semiconductor package of claim 1 , wherein the continuous sidewall extends entirely through the second ...

PRINTED CIRCUIT BOARD FOR SEMICONDUCTOR PACKAGE

A printed circuit board for a semiconductor package including a printed circuit board body, a plurality of ball lands on one surface of the printed circuit board body, a first plating layer on a portion of each of the ball lands, and a second plating layer on another portion of each of the ball lands may be provided. An upper surface of the first plating layer may be coplanar with an upper surface of the second plating layer. 2. The printed circuit board of claim 1 , wherein the first plating layer or the second plating layer has a single-layered structure or a multi-layered structure.3. The printed circuit board of claim 1 , wherein at least one of the first plating layer and the second plating layer is made of a plurality of materials.4. The printed circuit board of claim 1 , wherein the first plating layer includes at least one selected from the group consisting of Ni/Au claim 1 , Ni/Pd/Au claim 1 , Ni/Ag claim 1 , Ni/Pd/Ag claim 1 , Ni/Sn claim 1 , Ni/Cu claim 1 , and Ni/Pd.5. The printed circuit board of claim 1 , wherein the second plating layer includes at least one selected from the group consisting of organic solderability preservative (OSP) claim 1 , Ag claim 1 , Au claim 1 , Pd claim 1 , and Sn.6. The printed circuit board of claim 1 , wherein when the printed circuit board is viewed from above claim 1 , the first plating layer and the second plating layer are alternately arranged in a checkerboard pattern.7. The printed circuit board of claim 1 , wherein when the printed circuit board is viewed from above claim 1 , the first plating layer and the second plating layer have a circular shape.8. The printed circuit board of claim 1 , wherein a surface where the first plating layer and the second plating layer form a concave-convex shape when viewed laterally.9. The printed circuit board of claim 1 , wherein the ball lands claim 1 , the first plating layer claim 1 , and the second plating layer are electrically connected to one another.10. The printed circuit ...

WIRING SUBSTRATE

A wiring substrate includes a wiring layer. Metal posts are arranged on the wiring layer. The metal posts are used to mount an electronic component. A protective layer covers a surface of the wiring layer on which the metal posts are arranged. The wiring layer includes a seed layer and a metal plating layer. The metal plating layer has a size that is the same as that of the seed layer in a plan view. The metal posts each include an upper end, which projects from the protective layer, and a lower end, which has a width that is the same as that of the upper end or greater. The protective layer includes a fillet for each metal post. The fillet extends toward an upper end surface of the corresponding metal post and contacts a side surface of the corresponding metal posts. 1. A wiring substrate comprising:a wiring layer;metal posts arranged on the wiring layer, wherein the metal posts are used to mount an electronic component; anda protective layer that covers a surface of the wiring layer on which the metal posts are arranged;wherein the wiring layer includes a seed layer and a metal plating layer formed on the seed layer, wherein the metal plating layer has a size that is the same as that of the seed layer in a plan view;the metal posts each include an upper end, which projects from the protective layer, and a lower end, which has a width that is the same as that of the upper end or greater; andthe protective layer includes a fillet for each of the metal posts, wherein the fillet extends toward an upper end surface of the corresponding one of the metal posts and contacts a side surface of the corresponding one of the metal posts.2. The wiring substrate according to claim 1 , further comprising a surface-processed layer that covers the upper end surface of each of the metal posts.3. The wiring substrate according to claim 1 , wherein the upper end surface of each of the metal posts is roughened.4. The wiring substrate according to claim 1 , further comprising an ...

Planar integrated circuit package interconnects

Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.

FAN-OUT PACKAGE STRUCTURE AND METHOD

A method includes attaching a semiconductor structure on a carrier, depositing a molding compound layer over the carrier, wherein the semiconductor structure is embedded in the molding compound layer, exposing a first photo-sensitive material layer and a second photo-sensitive material layer to light, developing the first photo-sensitive material layer and the second photo-sensitive material layer to form an opening having a first portion in the first photo-sensitive material layer and a second portion in the second photo-sensitive material layer, wherein a width of the second portion is greater than a width of the first portion, filling the opening with a conductive material to form a via in the first photo-sensitive material layer and a redistribution layer in the second photo-sensitive material layer and forming a bump over the redistribution layer. 1. A method comprising:attaching a semiconductor structure on a carrier, wherein the semiconductor structure comprises a plurality of connectors;depositing a molding compound layer over the carrier, wherein the semiconductor structure is embedded in the molding compound layer;depositing a first photo-sensitive material layer on the molding compound layer;exposing the first photo-sensitive material layer to light according to a first pattern;depositing a second photo-sensitive material layer on the first photo-sensitive material layer;exposing the second photo-sensitive material layer to light according to a second pattern;developing the first photo-sensitive material layer and the second photo-sensitive material layer to form a plurality of openings;filling the plurality of openings with a conductive material to form a first redistribution layer; andforming a plurality of bumps over the first redistribution layer.2. The method of claim 1 , further comprising:after the step of depositing the molding compound layer over the carrier, applying a grinding process to the molding compound layer until a top surface of the ...

CIRCUIT REDISTRIBUTION STRUCTURE UNIT AND METHOD FOR MANUFACTURING CIRCUIT REDISTRIBUTION STRUCTURE

A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias are formed in the first dielectric. A first circuit redistribution layer is formed on the first dielectric. A second dielectric is formed on the first dielectric. First and second holes are formed on the second dielectric. A trench is formed in the second dielectric to divide the second dielectric into first and second portions. A first portion of the first circuit redistribution layer and the first hole are disposed in the first portion of the second dielectric, and a second portion of the first circuit redistribution layer and the second hole are disposed in the second portion of the second dielectric. Conductive blind vias are formed in the first and second holes, and a second circuit redistribution layer is formed on the second dielectric. 1. A method for manufacturing a circuit redistribution structure , the method comprising:forming a first dielectric layer on a carrier;forming a plurality of first holes and a plurality of second holes in the first dielectric layer;respectively forming a plurality of first conductive vias and a plurality of second conductive vias in the first holes and the second holes, and forming a first circuit redistribution layer on the first dielectric layer, wherein a first portion of the first circuit redistribution layer is electrically connected to the first conductive vias, and a second portion of the first circuit redistribution layer is electrically connected to the second conductive vias;forming a second dielectric layer on the first dielectric layer and the first circuit redistribution layer;forming a plurality of third holes and a plurality of fourth holes in the second dielectric layer to respectively expose the first portion and the second portion of the first circuit redistribution layer, and forming a trench in the second dielectric layer to expose the first dielectric ...

MANUFACTURING METHOD OF A CIRCUIT BOARD HAVING A GLASS FILM

Provided is a manufacturing method of a circuit board structure including steps as below. A glass film is provided on an electrostatic chuck (E-chuck). A plurality of first conductive vias are formed in the glass film. A first circuit layer is formed on an upper surface of the glass film, such that the first circuit layer is electrically connected with the first conductive vias. A first polymer layer is formed on the first circuit layer. The first polymer layer covers a surface of the first circuit layer and the upper surface of the glass film. A plurality of second conductive vias are formed in the first polymer layer. A second circuit layer is formed on the first polymer layer, such that the second circuit layer is electrically connected with the second conductive vias. The E-chuck is removed. 1. A manufacturing method of a circuit board structure , comprising:providing a glass film having an upper surface and a lower surface, and the lower surface of the glass film being disposed on an electrostatic chuck;forming a plurality of first conductive vias in the glass film, and the plurality of the first conductive vias penetrate the upper surface and the lower surface of the glass film;forming a first circuit layer on the upper surface of the glass film, such that the first circuit layer is electrically connected with the first conductive vias;forming a first polymer layer on the first circuit layer, and the first polymer layer covering a surface of the first circuit layer and the upper surface of the glass film;forming a plurality of second conductive vias in the first polymer layer, wherein the second conductive vias are electrically connected with the first circuit layer;forming a second circuit layer on the first polymer layer, such that the second circuit layer is electrically connected with the second conductive vias; andremoving the electrostatic chuck, so as to form a first circuit board structure.2. The manufacturing method of the circuit board structure ...

Circuitized substrate with electronic components mounted on transversal portion thereof

A circuitized substrate for mounting at least one electronic component having a plurality of terminals. The circuitized substrate includes a first portion of electrical insulating material embedding a first electric circuit for coupling a first subset of the terminals. The first electric circuit including one or more patterned conductive layers of electrically conductive material extending parallel to a plane of the circuitized substrate. The circuitized substrate further includes a second portion of electrically conductive material. One or more insulating elements of electrical insulating material cross the second portion transversally to the plane to insulate a plurality of conductive elements thereof for coupling a second subset of the terminals. One or more auxiliary components of the electronic component are mounted on the second portion. Each auxiliary component having a first terminal and a second terminal coupled with a first one and a second one, respectively, of a pair of the conductive elements.

Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same

Semiconductor assemblies including thermal management configurations for reducing heat transfer between vertically stacked devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise at least one memory device mounted over a logic device with a thermally conductive layer, a thermal-insulator interposer, or a combination thereof disposed between the memory device and the logic device. The thermally conductive layer includes a structure configured to transfer the thermal energy across a horizontal plane. The thermal-insulator interposer includes a structure configured to reduce heat transfer between the logic device and the memory device.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface; a heat dissipation member disposed on the inactive surface of the semiconductor chip and including a graphite material; an adhesive member disposed between the semiconductor chip and the heat dissipation member; an encapsulant covering at least a portion of each of the semiconductor chip and the heat dissipation member; and an interconnect structure disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad. The encapsulant covers at least a portion of aside surface of the adhesive member. 1. A semiconductor package , comprising:a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface;a heat dissipation member disposed on the inactive surface of the semiconductor chip and including a graphite material;an adhesive member disposed between the semiconductor chip and the heat dissipation member;an encapsulant covering at least a portion of each of the semiconductor chip and the heat dissipation member; andan interconnect structure disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad,wherein the encapsulant covers at least a portion of a side surface of the adhesive member.2. The semiconductor package of claim 1 , wherein the heat dissipation member includes a pyrolytic graphite sheet.3. The semiconductor package of claim 1 , wherein the adhesive member includes an epoxy resin and an (meth)acrylate-based resin.4. The semiconductor package of claim 3 , wherein the adhesive member includes one or more selected from the group consisting of cross-linking between the epoxy resin and the (meth)acrylate-based resin claim 3 , cross-linking between the epoxy resins claim 3 ...

SEMICONDUCTOR PACKAGE HAVING DUMMY PADS AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE HAVING DUMMY PADS

A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the second semiconductor chip, and a plurality of dummy pads disposed outside of an area occupied by the first semiconductor chip or the second semiconductor chip from a top-down view and disposed on the top surface of the interposer substrate. Each pad of the first plurality of signal pads and the second plurality of signal pads is configured to transfer signals between the interposer substrate and a respective semiconductor chip, and each pad of the dummy pads is not configured to transfer signals between the interposer substrate and any semiconductor chip disposed thereon. 1. A semiconductor package comprising:a package substrate having a bottom surface and a top surface;a plurality of package terminals disposed on the bottom surface of the package substrate;an interposer substrate disposed on the top surface of the package substrate, the interposer substrate having a bottom surface facing the package substrate and a top surface opposite the bottom surface;a ...

SEMICONDUCTOR STRUCTURES

A semiconductor structure includes a semiconductor package and a connector. The semiconductor package includes a die and a redistribution structure. The redistribution structure is disposed over the die, and includes a plurality of conductive patterns stacking on one another and electrically connected to the die. The connector is disposed on the redistribution structure, and includes a connecting element. The connecting element penetrates the conductive patterns and is electrically connected to the die. 1. A semiconductor structure , comprising: a die; and', 'a redistribution structure disposed over the die, comprising a plurality of conductive patterns stacking on one another and electrically connected to the die; and, 'a semiconductor package, comprisinga connector on the redistribution structure, comprising a connecting element, wherein the connecting element penetrates the conductive patterns and is electrically connected to the die.2. The semiconductor structure of claim 1 , wherein the conductive patterns are overlapped with one another.3. The semiconductor structure of claim 1 , wherein a portion of the connecting element is in direct contact with an inner sidewall of at least one of the conductive patterns.4. The semiconductor structure of claim 1 , wherein a portion of the connecting element is physically separated from an inner sidewall of at least one of the conductive patterns.5. The semiconductor structure of claim 1 , wherein the connecting element comprises a top portion claim 1 , a bottom portion and a middle portion between the top portion and the bottom portion claim 1 , and the middle portion is in direct contact with an inner sidewall of at least one of the conductive patterns.6. The semiconductor structure of claim 1 , wherein the connector further comprises a connecting housing and a connecting portion claim 1 , wherein the connecting element is disposed at a first side of the connecting housing claim 1 , and the connecting portion is disposed ...

Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate

A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first interconnect structure over the substrate;disposing a first semiconductor die over the first interconnect structure;disposing the substrate over a carrier with the first semiconductor die oriented away from the carrier;depositing an encapsulant over the carrier, substrate, and first semiconductor die;forming a second interconnect structure over the encapsulant and semiconductor die; andremoving the substrate to expose the first interconnect structure after forming the second interconnect structure.2. The method of claim 1 , further including forming a conductive column over the first interconnect structure.3. The method of claim 2 , wherein the conductive column extends from the first interconnect structure to the second interconnect structure ...

MAGNETIC ENCAPSULANT FOR PACKAGE MAGNETIC INDUCTORS

Embodiments herein relate to a magnetic encapsulant composite, comprising a mixture of a first material that is a soft magnetic filler, a second material that is a polymer matrix, and a third material that is a process ingredient. The magnetic encapsulant composite may then encapsulate or partially encapsulate a magnetic inductor coupled to a substrate to increase the inductance of the magnetic inductor and/or to strengthen the substrate to which the magnetic inductor and the composite are coupled. 1. A magnetic encapsulant composite , comprising a mixture of:a first material that is a soft magnetic filler;a second material that is a polymer matrix; anda third material that is a process ingredient.2. The magnetic encapsulant composite of claim 1 , wherein the first material includes at least a selected one of: a metallic magnetic material or a soft ferrite magnetic material.3. The magnetic encapsulant composite of claim 2 , wherein the metallic magnetic material includes at least a selected one of: Fe claim 2 , oriented FeSi claim 2 , unoriented FeSi claim 2 , FeNi claim 2 , FeCo claim 2 , FeSiBNbCu claim 2 , or CoZrTa.4. The magnetic encapsulant composite of claim 2 , wherein the soft ferrite magnetic material includes at least a selected one of: MnZn claim 2 , NiZn claim 2 , or FeO.5. The magnetic encapsulant composite of claim 1 , wherein the second material includes at least a selected one of: an acrylate claim 1 , a methacrylate claim 1 , an epoxy claim 1 , a urethane claim 1 , a cyano-acrylate claim 1 , a cyano-urethane claim 1 , or a silicone.6. The magnetic encapsulant composite of claim 1 , wherein the third material includes at least a selected one of: a resin claim 1 , a catalyst claim 1 , an initiator claim 1 , a polymer claim 1 , a toughening agent claim 1 , a surfactant claim 1 , an adhesion promotor claim 1 , a thixotropic index modifier claim 1 , or a reactive diluent.7. The magnetic encapsulant composite of claim 1 , wherein the composite is to be ...

STRUCTURES WITHIN A SUBSTRATE LAYER TO CURE MAGNETIC PASTE

Embodiments herein relate to systems, apparatuses, or processes for embedding a magnetic core or a magnetic inductor in a substrate layer by applying a copper layer to a portion of the substrate layer, creating a structure in the substrate layer on top of at least part of the copper layer to identify a defined region within the substrate layer, and inserting a magnetic paste into the defined region where the copper layer identifies a side of the defined region and where the structure is to contain the magnetic paste within the defined region while the magnetic paste cures. 1. A package comprising:a substrate having a first side and a second side opposite the first side; andan inductor embedded within the substrate, wherein the inductor is disposed between a first substrate layer adjacent to the first side of the substrate and a second substrate layer adjacent to the second side of the substrate.2. The package of claim 1 , wherein the substrate is a coreless substrate.3. The package of claim 1 , wherein the inductor includes a magnetic core and a copper (Cu) winding inductor structure.4. The package of claim 3 , wherein the magnetic core includes at least one of: a Fe—Co or Fe—Ni based nano ferromagnetic alloy powder claim 3 , or nano flakes that include CoFeO claim 3 , CoNiFe claim 3 , NiFeMo or NiFe.5. The package of claim 3 , wherein the magnetic core is in physical contact with the Cu winding inductor structure.6. The package of claim 1 , wherein the magnetic core comprises two coupled magnetic cores.7. The package of claim 1 , further comprising a die coupled to the first side of the substrate.8. A method for embedding a magnetic inductor in a substrate layer claim 1 , the method comprising:creating a structure within the substrate layer that identifies a defined region within the substrate layer;inserting a magnetic paste into the defined region; andwherein the structure is to contain the magnetic paste within the defined region while the magnetic paste cures.9 ...

Substrate assembly with encapsulated magnetic feature

Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.

Chip package structure with molding layer and method for forming the same

A method for forming a chip package structure is provided. The method includes disposing a chip over a redistribution structure. The method includes forming a molding layer over the redistribution structure adjacent to the chip. The method includes partially removing the molding layer to form a trench in the molding layer, and the trench is spaced apart from the chip.

CORE-SHELL PARTICLES FOR MAGNETIC PACKAGING

A package substrate may include a build-up layer. The build-up layer may include a dielectric material and one or more microspheres. The one or more microspheres may include a magnetic core that includes a first material that is a first oxidation-resistant material. Further, the one or more microspheres may include a shell to encapsulate the core, and the shell may include a second material that is a second oxidation-resistant material. The package substrate may further include a metal layer coupled with the build-up layer. 1. A package substrate , comprising: a dielectric material; and', 'one or more microspheres, wherein the one or more microspheres include a magnetic core that includes a first material that is a first oxidation-resistant material,, 'a build-up layer comprisingwherein the one or more microspheres include a shell to encapsulate the core, andwherein the shell includes a second material that is a second oxidation-resistant material; anda metal layer coupled with the build-up layer.2. The package substrate of claim 1 , wherein the first material is cobalt-tantalum-zirconium claim 1 , neodymium-iron-carbon claim 1 , or cobalt-iron-carbon.3. The package substrate of claim 1 , wherein the first material is iron claim 1 , cobalt claim 1 , or nickel.4. The package substrate of claim 1 , wherein the first material is a polymer that includes iron claim 1 , and wherein the polymer is a polyimide claim 1 , polyester claim 1 , polyphenol claim 1 , or poly cyclic-olefin.5. The package substrate of claim 1 , wherein the second material is copper claim 1 , silver claim 1 , gold claim 1 , platinum claim 1 , palladium claim 1 , titanium claim 1 , or chromium.6. The package substrate of claim 1 , wherein the build-up layer further comprises silica filler material.7. The package substrate of claim 1 , wherein the metal layer is copper claim 1 , tungsten claim 1 , or aluminum.8. A build-up layer claim 1 , comprising:a dielectric material; andone or more microspheres, ...

CHIP PACKAGE AND METHOD OF MANUFACTURING

A chip package that includes a die coupled to a package substrate. The substrate includes a first ground layer and a dielectric material engaging the first ground layer. A solder resist layer engages the dielectric material and a routing layer is disposed at least partially within the solder resist layer. A second ground layer engages the solder resist layer. 1. A chip package comprising:a die coupled to a package substrate, the package substrate including;a first ground layer;a dielectric material engaging the first ground layer;a solder resist layer engaging the dielectric material;a routing layer disposed at least partially within the solder resist layer;an elecroplated conductive layer engaging the solder resist layer.2. The chip package of claim 1 , wherein the conductive layer is a second ground layer that is coupled to the first ground layer through one or more vias.3. The chip package of claim 1 , wherein the conductive layer only covers selected regions of the solder resist layer.4. The chip package of claim 3 , wherein the conductive layer comprises one of copper claim 3 , tin claim 3 , gold claim 3 , palladium claim 3 , nickel claim 3 , or an alloy.5. The chip package of claim 1 , wherein the routing layer is one of multiple routing layers located between the first ground layer and the conductive layer.6. The chip package of claim 1 , wherein the solder resist layer includes a controlled collapse chip connection (C4) area including one or more C4 structures formed at least partially within the solder resist layer.7. The chip package of claim 6 , wherein the conductive layer engages the solder resist layer outside the C4 area of the solder resist layer.8. The chip package of claim 7 , wherein the conductive layer includes multiple claim 7 , physically separate portions that are located over routing layer regions and not over the C4 area.9. A chip package comprising:a die coupled to a package substrate, the package substrate including;a first ground layer;a ...

SUBSTRATE ASSEMBLY REGION WITH CERAMIC OR BORON FIBER

Apparatuses, systems and methods associated with substrate assemblies for computer devices are disclosed herein. In embodiments, a core for a substrate assembly includes a first metal region, a second metal region, and a dielectric region located between the first metal region and the second metal region. The dielectric region includes one or more fibers, wherein each of the one or more fibers includes aluminum, boron, silicon, or oxide. Other embodiments may be described and/or claimed. 1. A core for a substrate assembly , comprising:a first metal region;a second metal region; anda dielectric region located between the first metal region and the second metal region, wherein the dielectric region includes one or more fibers, wherein each of the one or more fibers includes aluminum, boron, silicon, or oxide.2. The core of claim 1 , wherein each of the one or more fibers comprises aluminoborosilicate claim 1 , aluminosilicate claim 1 , or alumina.3. The core of claim 1 , wherein each of the one or more fibers further includes:a nucleus formed of an electrically non-conductive material; andan outer layer that encircles the nucleus, the outer layer formed of boron.4. The core of claim 3 , wherein the electrically non-conductive material comprises aluminoborosilicate claim 3 , aluminosilicate claim 3 , or alumina.5. The core of claim 1 , wherein the one or more fibers comprise a plurality of fibers claim 1 , wherein the plurality of fibers are woven to produce a fabric.6. The core of claim 5 , wherein the dielectric region further includes resin claim 5 , and wherein the fabric is impregnated with the resin.7. The core of claim 6 , wherein the resin comprises a dielectric material or a ceramic-based material.8. The core of claim 5 , wherein the fabric has a tensile modulus between 240 gigapascals (GPa) and 400 GPa.9. The core of claim 5 , wherein the fabric has a tensile strength between 3.6 gigapascals (GPa) and 4 GPa.10. A substrate assembly claim 5 , comprising:one or ...

SEMICONDUCTOR PRODUCT SUBSTRATE INCLUDING STRESS RELIEF LAYER

A substrate is disclosed having a stress relief layer. The stress relief layer may be applied to a dielectric core of the substrate, beneath a conductive layer in which electrical traces and contact pads are formed. The substrate including the stress relief layer may be incorporated into a semiconductor product which may, for example, be mounted on a host printed circuit board using solder balls on a surface of the substrate. The stress relief layer helps dissipate stresses within the substrate and improves the board level reliability. 1. A substrate for use in a semiconductor product , comprising:a dielectric core having first and second major planar surfaces;a stress relief layer applied onto the first major planar surface of the dielectric core, the stress relief layer having a modulus less than a modulus of the dielectric core;a first conductive layer applied onto the second major planar surface of the dielectric core, the first conductive layer formed into a first conductive pattern; anda second conductive layer applied onto the stress relief layer, the second conductive layer formed into a second conductive pattern.2. The substrate of claim 1 , wherein the stress relief layer is formed of a dielectric film.3. The substrate of claim 1 , wherein the stress relief layer is formed of one of polyimide claim 1 , Polybenzoxazole claim 1 , Benzocyclobutene claim 1 , compound of silicone and rubber.4. The substrate of claim 1 , wherein the stress relief layer has a modulus of 100 MPa to 1000 MPa.5. The substrate of claim 1 , wherein the stress relief layer has a modulus of 300 MPa to 500 MPa.6. The substrate of claim 1 , wherein the stress relief layer is a solid layer applied continuously over the dielectric core.7. The substrate of claim 1 , wherein the stress relief layer reduces warping of the substrate.8. The substrate of claim 1 , wherein the stress relief layer dissipates mechanical stresses within the substrate.9. The substrate of claim 1 , wherein the second ...