CRACK RESISTANT INTERCONNECT MODULE

From cracks and herein generates tendency reduced or no a flip-chip integrated circuit (IC) provides. A flip chip package a, integrated chip (IC, also wsahing "die (die)") of at least of four corners of one or "die shadow (die shadow)" BGA (Ball Grid Array) substrate the package that surrounds the light around areas of at least one side of the chip carrier includes (solid plane) solid plane. If matching of the form and size of an area covered with the covering film (the plane) of the package than θ1. based on the characteristics another design. These surfaces are on the face using solder mask (soldermask) by defining BGA pad use as power or ground connections can be. 2001 aspect herein, die corner BGA in the region near geometric on the surface side (geometric discontinuity) free disconnected electrode 104 is provided under the areas of which.

In at least one embodiment of the present invention, a laminated flip-chip interconnect package the chip and board for attachment to a corresponding pads on a surface that define contact pads chip attach surface and a board attach includes a substrate having a surface, where the substrate board surface comprises near chip corner covering the chip attach surface region includes at least one solid plane. A solder solid plane (coverlay material) or coverlay material, optionally covered with a by includes dielectric material.

In at least one embodiment of the present invention, at least one flip chip package includes solid plane, wherein the area of the near chip corner or coverlay material, optionally covered with a metal solid plane constitution :.

In another embodiment of the present invention, the solid plane defining pad BGA solder-contact element is slidably received in metal covered by mask material includes solid plane.

A flip-chip IC. many aspects of the other package. However package a relatively a thin flexible it is preferable that the remain.

Then as was employed in the excitation term the meaning:

1. To the "conductive (conductive)" is electrically conductive term meaning that the..

2. "Geometric disconnected (geometric discontinuity)" is the contact pads term continuous material, such as the openings or blocking region features..

3. Wherein "interconnection substrate (interconnect substrate)" used "package substrate (package substrate)" that term, "flexible fixing a package substrate (flexible package substrate)", "(rigid package substrate) rigid package substrate". equivalents and the like.

4. "Solid plane (solid plane)" term is of a single material disconnection-free function a geometry which substantially. area of.

Also as shown in 1, interconnect module that incorporates (100) comprises alternately stacked together a series of dielectric film and metal layers integrally interconnection substrate (unitary interconnect substrate; 110) (single material shown) is formed on. Stacked interconnection substrate (110) in the interconnect module that incorporates chip (120), printed wiring board (130), interconnect electrical conductivity between the various layers and thus providing a path for a plurality of non-and patterned signal layers (not shown) may include a. Also 3 and also Figure 4 shows a stacked interconnection substrate a title of contents stored in the is coarse. Solder balls interconnect module that incorporates (128, 138) through, chip and board corresponding pads on each surface that define contact pads for gluing a chip attach surface (125) and a board attach surface (135) including, chip and interconnects substrate and between the interconnection substrate and printed wiring board (PWB) between provides electrical interconnections and mechanical connection. Chip and reliable with PWB interconnect that facilitate so as to have a coefficient of thermal expansion (CTE), where the different layers is selected. The interconnect module that incorporates chip attach surface (125) on adhesive (145) interconnected by substrate (110) with self-adhesion to reinforcing member (stiffening member; 140) may also comprise a since, chip a stiffening member positioned at the center of the in. Underfill adhesive (unterfill adhesive; 170) the interconnects substrate (110) chip attach surface (125) and the chip the inferior side of the located between the, inspecting substrate using cos manner and solder ball (128) (encapsulating). surrounds. Eventually, lid assembly (lid assembly; 150) further an adhesive layer (155) the bearing upper side of the. can be adhered to. Thermally conductive adhesive or an elastomer chip material (elastomer; 160) (120) for emitting second light including Image information lid assembly (150) is interposed between the, during operation caused by chip helps for the dissipation of heat.

Low coefficient of thermal expansion (CTE) (-2.6 PPM / °C respect to silicon) integrated circuit with a (IC), relative thin (°C/<0.75mm) 이로 인해 유연하며 상승한 온도에서 상대적으로 높은 CTE(>15 PPM) package having substrate (110) after gluing the to, at a low temperature substrate cooling plane package specific capacities under significant mellitus, tensile stress and deformation. force is generated. Some of them, two adhesive components of occurs directly from. Remainder, such direct response to force or modified stress intrinsic point defects, and a outside wall of the casing to prevent is bent in a collision package substrate is translucent or partially. arises from to control. Such inhibitors (constraints) a ring or lid assembly (150) such as package the reinforcing member (140) when an can generate a.

Such a package substrate, a specific region in an a dielectric substrate comprises a force or modified and/or conducting material inducing cracks in the modified mullite coating can be raised to level. The, 1 through (fracture) gap exposed low temperature times by efficiently in the visual recognition direction of subsequent or fatigue process (fatigue process) after exposures can generate a.

-55 ° C or -40 ° C and a + 125 °C and thermal gradient of the concrete during cycling between 2 portion interconnect module that incorporates two regions is found to formed in. Also 2a and 2b of a crack has BGA interconnect module that incorporates (200) formed on a map of position. shown. Also door has 2b 2a gray in a circular area is extended, so that the is drawing. A predetermined drawing of interconnect module that incorporates BGA side solder ball pads (240) array of. shown. Number 1 the die region (220) shown by a black edge of a die is shown lines corners (210) directly the outside and , when over an extreme range of part which the dies edges of. also the second insulating layer are formed thereon. Crack (230) adjacent to the corner of the die appearance of solder ball pads (240) of hope appeared. in.

Empirically evidence fatigue of the existing method crack formation layer formed on the blades, presenting a. And thermal gradient of the concrete, metallic from an edge of a, more generally layer on which a metal layer (metal layer of Figure 4 or of Figure 3 350 (440)) adjacent to the interconnect module that incorporates (of Figure 4 402 and of Figure 3 302) on the surface of BGA of BGA pad (of Figure 4 490 and of Figure 3 390) is found to start from the. They are adjacent metallic and the dielectric layer (of Figure 4 435, 463, 464 and of Figure 3 345, 365, 366) can be propagate into the. For example, a dielectric growth cracks signal on metal layer prior to layer if encountered trace, trace electrical as-cleaved can be opening. Metal in Figure 3 they often and thermal gradient of the power surface (340) or of Figure 4 metal "core" surface (430) such as, until it reaches a solid plane will propagated. These surfaces are easily cracks acceptable in such a way that a geometry which substantially not through discharging a composition, a second "crack paper machine (crack stoppers)" role of to make. To form surface papermaking crack dielectric material may be used; however, compared to the material of dielectric predetermined essentially copper since the reverse link has a higher a high durability often a metal, such as copper is preferred.

Figure 3 shows a herein described herein also can be used with a combinations one possible symbol of the for a portion of the interconnect substrate is coarse. Also Figure 3 shows a 7 layer interconnection substrate (300) to a, series of the substrate metal layer (320 (pad and/or planar), 325 (signal), 330 (power or ground), 335 (core), 340 (power or ground), 345 (signal), and 350 (pad and/or planar)) and the dielectric layer (361, 362, 363, 364, 365 and 366) consists of by a coil is constituted by alternately laminating. Also 3 dielectric layer metals and shown in core metal layer (335) is disposed symmetrically with respect to the. I.e., core layer (335) is formed on one side of core layer ply of or metal dielectric layer each hole have a corresponding the same material.

Also further drive the discharge lamp 3, number 1 via (380) has a metal layer (320) from dielectric layer (361) extend through, metal layer (325). terminates at. Number 2 via (375) has a metal layer (325) begins at a, dielectric layer (362, 363, 364 and 365) expand through, metal layer (345). terminates at. Number 3 via (370) has a metal layer (345) from dielectric layer (366) extend through, metal layer (350) terminates at.. Each via (370, 375, 380) in the microelectronic fabrication techniques publicly known deposition techniques (microelectronic fabrication art) using any of a conductive material is plated. Alternatively, each via (370, 375, 380) converts the electric conductive material defined a column current source and at the conductive path. A one skilled in the art, any combination of die attach surface (304) bond pads on (357) and a BGA attach surface (302) bond pads on (390) for providing electrical connection between may be used to, blind (blind vias), buried via (buried vias) and through via (through vias) recognizing that that will.

Chip attach surface (304) and BGA attach surface (302) to solder mask (310, 315) are adjusted.. Solder mask are typically filled honeycomb or epoxy material is made in. Each solder mask (310, 315) each via (370, 375, 380) bond pads contact or adjacent to. exposing a. For example, solder mask (310) the contact pad (357) while exposing a, solder mask (315) the contact pad (390) exposing a.. Solder balls associated with chip (355) contact pad (357) is aligned over and is heated are reflowed to, contact pads with the chip form for the electrical and mechanical adhesion. Similarly, solder balls associated with board (not shown) contact pad (390) is aligned over and is heated are reflowed to contact pads and the PWB for the electrical and mechanical adhesion between form.

Dielectric layer (361, 362, 363, 364, 365 and 366) (polyimides) are polyimide (polyimide laminates) stacks and the polyimide, epoxy resins (epoxy resins), liquid crystal polymers (liquid crystal polymers), organic materials (organic materials), or at least part is polytetrafluoroethylene (polytetrafluoroethylene) (dielectric materials) materials such as a dielectric consisting of high-temperature organic dielectric substrate being a stack of material, charging without number charging or, in the alternative, with and a number (filler), can be formed. In one in the embodiment, dielectric layer (361, 362, 363, 364, 365, 366) the organic which is such as PTFE (polytetrafluoroethylene), more specifically, cyanate ester and epoxy (cyanate ester and epoxy) containing an expanded PTFE or "ePTFE" 14.. PTFE material, in particular, mixed cyanate ester adhesive and an inorganic filler in an amount of including as expanded [...] can be matrix.

Metal layer (320, 325, 330, 335, 340, 345, 350) can be formed from copper. Aluminum, gold, or, such as silver, and a other suitable metal may be used.. In such, metal layers (320, 325, 330, 340, 345 and 350) 5-14 micron range in approximately each may have a thickness of. To variations of one, each metal layer (320, 325, 330, 340, 345 and 350) is approximately thickness of 12 microns. Core metal layer (335) in about 5-50 micron range may have a thickness of. Dielectric layer (361, 362, 363, 364, 364 and 366) 20-70 micron range in approximately each may have a thickness of. In one example, each dielectric layer (361, 362, 363, 364, 365 and 366) is the thickness of the approximately 36 microns.

Interconnection substrate (300) where the different layers of heat and pressure are the materials together using (stacked) can be (laminated) laminate. For example, all layers can be stacked stack simultaneously are.. Alternatively, layers are metallic core layer (335) on and can be mounted one at a time, or each lamination steps in one or two additional layers, additional (incrementally) is cached to one set of can be provided. During lamination, dielectric layer (361, 362, 363, 364, 365 and 366) is melted and the flows is, integrated bulk dielectric material provides (monolithic bulk dielectric material; 360).

Interconnection substrate (300) deposition of a ear, through via are can be formed. In particular, via for example for the, U. S. Call patent number 6,021,564 described drill or laser ablation process can be formed by (drilling or laser ablation processes). Subsequent to the laminate, interconnection substrate (300) to solder mask (310 and 315). is added. Furthermore, chip (355) and PWB (not shown) for accommodating said light sources and solder balls from each, contact pads (357, 390) solder mask to define (310 and 315) is patterned.

Figure 4 shows a herein described herein also can be used with a combinations one possible symbol of the for a portion of the interconnect substrate is coarse. Also Figure 4 shows a series of metal layer ((core) 420, 425, 430, 435, 440) and the dielectric layer (461, 462, 463, 464) obtained by alternately a 5 layer interconnection substrate (400) is a. Also 4 core layer dielectric layer a metal layer shown in (430) is disposed symmetrically with respect to the. I.e., core layer (430) is formed on one side of core layer each dielectric layer or metal layer hole have a corresponding the same material.

Also further drive the discharge lamp 4, via number 1 (480) has a metal layer (420) from dielectric layer (461) extend through metal layer (425) terminates at.. Number 2 via (475) has a metal layer (425) starting at dielectric layer (462, 463) extend through metal layer (435) terminates at.. Number 3 via (470) has a metal layer (435) from dielectric layer (464) extend through metal layer (440). terminates at. Each via (470, 475, 480) in the microelectronic fabrication techniques publicly known deposition techniques using any of a conductive material is plated. Alternatively, each via (470, 475, 480) are electrically conductive material defined a column current source and at the conductive path. A one skilled in the art, any combination of die attach surface (404) bond pads on (457) and a BGA attach surface (402) bond pads on (490) for providing electrical connection between may be used to, blind, buried via and through vias for recognizing that that will.

Chip attach surface (404) and BGA attach surface (402) to solder mask (410, 415) are adjusted.. Each solder mask (410, 415) each via (470, 480) bond pads contact or adjacent to. exposing a. For example, solder mask (410) the contact pad (457) while exposing a, solder mask (415) the contact pad (490) exposing a.. Solder balls associated with chip (455) contact pad (457) is aligned over and is heated are reflowed to, contact pads with the chip form for the electrical and mechanical adhesion. Similarly, solder balls associated with board (not shown) contact pad (490) is aligned over and is heated are reflowed to contact pads and the PWB for the electrical and mechanical adhesion between form.

Dielectric layer (461, 462, 463, 464) (polyimides) are polyimide (polyimide laminates) stacks and the polyimide, epoxy resins (epoxy resins), liquid crystal polymers (liquid crystal polymers), organic materials (organic materials), or at least part is polytetrafluoroethylene (polytetrafluoroethylene) (dielectric materials) materials such as a dielectric consisting of high-temperature organic dielectric substrate being a stack of material, charging without number charging or, in the alternative, with and a number (filler), can be formed. In one in the embodiment, dielectric layer (461, 462, 463, 464) the organic which is such as PTFE (polytetrafluoroethylene), more specifically, cyanate ester and epoxy (cyanate ester and epoxy) containing an expanded PTFE or "ePTFE" 14.. PTFE material, in particular, mixed cyanate ester epoxy adhesive (mixed cyanate ester-epoxy adhesive) as expanded including a number (inorganic filler) and an inorganic filler can be matrix [...].

Metal layer (420, 425, 430, 435, 440) can be formed from copper. Aluminum, gold, or, such as silver, and a other suitable metal may be used.. In such, metal layers (420, 425, 435, 440) 5-14 micron range in approximately each may have a thickness of. To variations of one, each metal layer (420, 425, 435, 440) is approximately thickness of 12 microns. Core metal layer (430) in about 5-50 micron range may have a thickness of. Dielectric layer (461, 462, 463, 464) each in approximately 20-70 micron range may have a thickness of. In one example, each dielectric layer (461, 462, 463, 464) is the thickness of the approximately 36 microns.

Interconnection substrate (400) using heat and pressure are where the different layers of the materials together (stacked) can be (laminated) laminate. For example, another in the stack are all layers can be stacked at the same time as.. Alternatively, layers are metallic core layer (430) on and can be mounted one at a time, or each lamination steps in one or two additional layers, additional is cached to one set of can be provided. During lamination, dielectric layer (461, 462, 463, 464) is melted and the flows is, integrated bulk dielectric material provides (monolithic bulk dielectric material; 460).

Interconnection substrate (400) deposition of a ear, through via are can be formed. In particular, via for example for the, U. S. Call patent number 6,021,564 described drill or laser ablation process can be formed by (drilling or laser ablation processes). Subsequent to the laminate, interconnection substrate (400) to solder mask (410 and 415). is added. Furthermore, chip (455) and PWB (not shown) for accommodating said light sources and solder balls from each, contact pads (457, 490) solder mask to define (410 and 415) is patterned.

Interconnection substrate (300 or 400) the "flip-chip" can be accepts the integrated circuit. The step flip-chip is mounted, die (i.e., chip) and that features positioning solder balls on, and over is chip, the chip interconnecting substrate (300, 400) on a substrate such as and the step of aligning the contact pads and the of, between a chip and substrate to adhesion solder balls for establishing a furnace (furnace) to reflow for. involves. In this way, the contact pads are provided to interconnect the, peripheral, such as techniques TAB (tape-automated bonding) adhesion and wiring (periphery) dielectric chip rather than being limited to, is distribution over the surface. As a result, available I/O and power/grounding terminal can increases the maximum number of, signal and power/grounding interconnect route more effectively on the chip may be.

One skilled in the art in said in the embodiment shown types of interconnected substrates the embedded second electrode, metal layer, dielectric layer or the like may include additional layer including it should be realized that a. Furthermore, connection module a final interconnect small number of which depends on the requirements of a dielectric layer and metal layer an interconnect substrate may be made.

Die corner crack are stiffener ring and/or a lid imposed by the mechanical constraint is formed primarily from. Also as shown in 5a, e.g., assembly process (assembly process) (gel) and adhesive material various during bending colloid a temperature used in elevated temperature close to, assembled module (500a) is the absence of a stress mainly. As shown in 5b also however, when cooling at a temperature lower than, die (510b) and a assembled module (500b) among components of the other, in particular, die interconnection substrate (520b) (mismatch) imbalance in CTE between the package below so shape is formed on an. However stiffener ring (530) prevents such phenomenon is prevented, a flat instead holds the region of a substrate. Is formed on an underside of region die stiffener ring profile and flat profiles sufficiently under door has (transition) transition between a coarse to 5b shown as gap between reinforcement die which results in the formation. A short over a result these changes in the shape, BGA side of substrate (540) (tensile bending strains) power warp deformation tension on which has a weight corresponding to weight. The, in particular x y and curved simultaneously in in both warp in the presence of co, die corner (550) near 2000 from the bottom.

Surface easily changed sudden than shape, die corner and die (510) and a stiffener ring (530) gap between (560) than in is there will be a large deformation force. Vice versa, is changes in shape to take place slowly, if can be embodiment, modified will reduced force. Therefore, problems to alleviate may be obtained one measures require that die stiffener ring. is to increase the space between. For a larger space between stiffener ring die, threshold modified smaller than force. Threshold modified solid plane if it is less than force less area of. may be used.

For example, DE, Newark, W. Liter Gore and Assoc. From available in the MICROLAM brand names, as expanded polytetrafluoroethylene in the case of substrate used for the dielectric material, and method for application of variable charging MICROLAM mechanical properties to compute the force modification of the determination should are in consideration for. First, the (flexural breaking strain) stress destruction of curved MICROLAM is measured as 0.47% ± 0.15%. Next, fracture toughness of MICROLMA (fracture toughness) is measured and, in Figure 6 is shown as a function temperature. Finally, material fatigue attribute (fatigue properties) is measured and is shown in Figure 7.

(Stress intensity) intensity stress data to the quotient Q I law. is shown that dependent (power law).

Wherein, N_f has cycle life (cycles to failure), K_I has stress intensity coefficient (stress intensity factor), K_IC. toughness critical stress intensity or destruction.

The traditional for electronics industry the (cycles-to-failure) is 10000 cycle life cycle. From 7 also, the K_I/K_IC. leading to 0.7 approximately ratio. K_I ∝σ_I ∝ε_I (isotropic, homogeneous material) if implementing a, local modified force fatigue strain should is maintained in 0.33% or 0.7 hereinafter.

Figure 8 shows a 9 millimeter × 9 millimeter surface of the package substrate, a layer layer metal 7 also inhibit the growth of hematopoietic stem cell section is a finite element models (finite element model). Figure 9 shows a also, uniform model is of Figure 8 when subjected to the (uniform biaxial strain) stress shrinkable 2, single BGA is a BGA side dielectric stresses at the around. White ring (1010) as that is represented as BGA pad (1000) directly peripheral edge of a large stress region is present. These Figure 10 shows a localized large stress region is in degree. Only region stress or stress large coarse micro 75 width and depth and m is m micro 25. Region size combustion in a large-stress or strain approximately twice the nominal stress or modified force..

Die corner region in nominal to 0.17% hereinafter and thermal gradient of the concrete in the material dielectric MICROLAM deflection can be eliminated by maintaining as publicly known is that, the thicker corner die as well as solution possible can be. However BGA pad or other layers have a geometrical thickness of at disconnect are provided to realize the centralization of stress caused by if is seen in the, nominal stress during the thermal cycle which is not subject to cracking acceptable advantageously as high as 0.34%.

According to the present invention, in the region of near corner die BGA attach surface geometric on it is intended to provide a the area to which disconnection-free function. The, the system includes one or more dies BGA attach surface region near corner dielectric material is, additionally, solder mask or coverlay material complete covered by a layer of dielectric material is a solid plane and/or at least two different embodiment can be achieved.

In another in the embodiment, metal region near corner the system includes one or more dies, additionally, solder mask or coverlay material complete covered by a layer of metal solid of fishingrod demodulating can be constructed.

In another in the embodiment, metal region near corner the system includes one or more dies, i.e., a semiconductor layer is formed on defined BGA solder mask having apertures that metal covered by material solid of fishingrod demodulating can be constructed. Near corner die relate such embodiment provides gain for region solid plane while, as well as prior to and is in that region to allows to do all function. Compared to the material of dielectric most most due and ductility a durable high of a metal material, higher than the dielectric using metal surfaces. is more preferred to set a. First, PWB mechanical to form the interconnections the pad so as to position since the allows the use of part of, coating solder mask opening having preferably using metal surfaces (higher than for a reinforced and support). Second, positions these pads bonded metal plane allows the type to be used the, power or ground to the socket and also make electrical connection and, thus, valuable I/O complete contact list can be composed. Next, the, dimensions of package increases, and a since the help to prevent, as a result manufacturer and user for both is enabled avoid with cost increases.

A die the lateral dimensions of the nanostructure solid plane sizes and thicknesses, substrate thickness, dielectric material attributes, reinforcement thickness and materials, die-reinforcement gap, lead thickness and materials, and underfill attribute (coefficient, glass transition temperature, gel temperature, such as) such as. factors.

Finite element models the solid plane suitable to determine a size of may be used in. Figure 11 shows a also several die-reinforcement intervals (3 millimeter (also 11a), 5 millimeter (also 11b), and (also 11c) 7 millimeter) 18.5 millimeter die has 1.0 millimeter thickness leads in the results from a package including 40 millimeter square. Large stress region (1210) the, modified corner die greater than stress threshold force (1200) the present near the, wherein will is common for cracking to occur. One aspect of excitation disclosure herein, due to geometric disconnected, assembly, testing, or end during usage of the interconnect module that incorporates solid plane formed from cracking and regulate the area of solid plane in. is permitted, and if the means. Solid plane edge of itself, threshold deflection disclosure cracking the CPU can be broken since (discontinuities) points, edges of solid plane a large stress region it is preferable that the expands beyond the. Analysis results for this specific the, threshold stress level contents address memory relative the material dielectric MICROLAM discernable gap stress (fracture strain) in 95% confidence interval of 1/3 or 0.11% confidence interval been set a value equal to the.

As depicted at 11a -11c also, die-reinforcement increases gap is, request this markedly reduces the zone be used. Herein described herein one aspect of general which permits created by design rules, respective design complete finite element models details need for an IC package design of this activity reducing will simplified.

In at least one embodiment, metal surface comprises at least one die at their corners on pad layer BGA (e.g., in Figure 3 metal layer (350), in Figure 4 metal layer (440)). Such that each metal surface, again using the next shape varied in size and shape defined by elliptical 15 surrounding all BGA pad for a first contact to the first regions.

Wherein, the y and x unit is millimeter. Element a and b has door 12 such as shown in is measurements. Furthermore, also as shown in 12, specified structure in that an oval a die corner (1210) and danger detector or an actuator a, die stiffener ring (1250) (starting edge) edge disclosure of that match the line which extends from the lower end to having a short axis of the ellipse along a diagonal die corner member is positionable between the engine distance "d" away 2000. Die stiffener ring (1250) metal or the dielectric can be made.. Predetermined parameter dielectric or metal material is solid plane depending on whether will other. Furthermore, large stress region the material constituting the solid plane also may depend on. Figure 12 shows a region of the first active die corner region is a region the elliptic type subject to the. In an elliptical outer region, i.e. to of BGA side a normalized average stress levels in disclosure cracking conditions thermal cycling or propagating the regains a level sufficient to has it desirably will not reach the.

A, b, and the value of d as depicted at list, (in Figure 12 S) stiffener ring die than θ1. gap between the.

A particular the application in, and and if the corners are die BGA pad position is, the solid plane of BGA die edge over at least 2 low (rows) and a die at the same distance of rows and one below by will should extend.

Also the die edge 13a (1320) of interconnect a die corner (1310) to cover the pad layer BGA near solid plane for embodiment. shown thereby, the cold air flows. In such embodiment, the die solid plane around corner die and at their corners not dimensions BGA pad layer for patterning (1330) (i.e., solder ball (1340) and the amorphous layer not having any) is formed by providing.

Door 13a 13b has also described are the same as those alternate embodiment. shown thereby, the cold air flows. However also in 13b, patterning not dimensions (1330) the channel (1335) by physical BGA pad layer from the rest of the. as to be isolated at. Channel (1335) the BGA pad layer from formed by removing the material can be, in addition BGA pad layer the material for forming the channel in when is deposited can be formed by mask.

Furthermore, one or more solid plane around and at their corners die BGA pad layer (if the BGA pad layer is patterned) non-patterned on by adding layer of material can be formed.

Below the die extra layer or die corner interfaces extending an adjacent portion of the die edge and can be. Layers or dielectric material.

Illustratively,

2 of package, i.e., the above-mentioned metallic surface comprises (package A) and would otherwise (package B) the design, manufacturing, and assembled and to.. Crack reducing properties except that the they are the same. 10.6 millimeter × 12.0 millimeter die these both use an layer layer metal 7. Said two internal circuit design, but, package of BGA side metal layout in the stomach A described the resulting corner at die designed as a but using metal surface, the otherwise not go B package. Furthermore, package A die-reinforcement of the 6.6 millimeter × 6.9 millimeter gap to impart reinforcing material and having an opening larger than that of the lead is used 0.5 millimeter thickness. The 2.8 millimeter × 3.5 millimeter die-reinforcement B package having a film supporting instrument includes a gap are provided, and the reinforcement for 1.0 millimeter thickness lead is used. Therefore, package A herein while using metallic surface for two 4 of, package B using any of them does not.

Said two package of samples is the same assembly is assembled together die using recipe. After assembly, samples during cycle 1500 to -55 ° C -125 °C embodiment the thermal cycling. After thermal cycling, a the experiments has A package BGA side in a dielectric one of the sample 35 any cracking got out of sight. , By using a time hopping code, the B package 9 in sample of two 35 two eyes from any observable die corner cracks shown.

Various herein include substracte although the embodiment described herein, then are such in the embodiment the recording operation. within a range of claim. For example, in the embodiment herein of U then are described herein. S patent described an additional structure or process for any of may be used in combinations: U. S. Patent number 5,888,630 call, U. S. Patent number 6,018,196 call, U. S. Call patent number 5,983,974, U. S. Patent number 5,836,063 call, U. S. Patent number 5,731,047 call, U. S. Patent number 5,841,075 call, U. S. Patent number 5,868,950 call, U. S. Patent number 5,888,631 call, U. S. Patent number 5,900,312 call, U. S. Patent number 6,011,697 call, U. S. Call patent number 6,021,564, U. S. Patent number 6,103,992 call, U. S. Patent number 6,127,250 call, U. S. Patent number 6,143,401 call, U. S. Patent number 6,183,592 call, U. S. Patent number 6,203,891 call, U. S. Patent number 6,248,959 call.