МНОГОКРИСТАЛЬНЫЙ КОРПУС И СПОСОБ ПРЕДОСТАВЛЕНИЯ В НЕМ ВЗАИМНЫХ СОЕДИНЕНИЙ МЕЖДУ КРИСТАЛЛАМИ

Изобретение относится к микроэлектронике, к структурам взаимного соединения в многокристальных корпусах. Сущность изобретения: многокристальный корпус включает в себя подложку, имеющую первую сторону, противоположную вторую сторону и третью сторону, которая продолжается от первой стороны до второй стороны, первый кристалл, закрепленный на первой стороне подложки, и второй кристалл, также закрепленный на первой стороне подложки, и мост, расположенный рядом с третьей стороной подложки и соединенный с первым кристаллом и со вторым кристаллом. Никакой из участков подложки не находится под мостом. Мост формирует соединение между первым кристаллом и вторым кристаллом. В качестве альтернативы мост может быть расположен в полости на подложке или между подложкой и слоем кристалла. Мост может составлять активный кристалл и может быть закреплен на подложке с использованием проводных соединений. Изобретение позволяет получить структуры взаимных соединений между кристаллами в корпусах с большой плотностью ...

КОНСТРУКТИВНЫЙ ЭЛЕМЕНТ

... 1. Конструктивный элемент, в частности полупроводниковый компонент, содержащий первую микросхему (10), размещенную на второй микросхеме (20), в котором первая и вторая микросхемы (10, 20) имеют соответственно на одной из своих основных поверхностей (13, 23) первую, соответственно, вторую металлизации (12, 22), которые обращены одна к другой, при этом первые участки металлизаций (12, 22) предусмотрены для выполнения электрического соединения между первой и второй микросхемами (10, 20), а вторые участки металлизации (12, 22) предусмотрены как дополнительная электрическая функциональная поверхность вне первой и второй микросхем (10, 20). 2. Конструктивный элемент по п. 1, отличающийся тем, что первая и/или вторая металлизация (12, 22) через контактные элементы (14, 24) соединены с контактными площадками (11, 21), расположенными в верхнем слое металлизации. 3. Конструктивный элемент по п.1 или 2, отличающийся тем, что первая или вторая микросхема (10, 20) в местах, в которых противолежащая ...

Gestapelte Mehrchip-Module und Verfahren zur Herstellung

Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung

Halbleitervorrichtung, die Folgendes aufweist: – ein Halbleiterelement (1), bei dem eine Metallisierungsschicht (2) auf der Rückseite gebildet ist; – einen metallischen Leiterrahmen (4), der parallel zu dem Halbleiterelement (1) und in einem Abstand von diesem angeordnet ist; – eine erste Bondverbindungsschicht (3), die zwischen dem Halbleiterelement (1) und dem Leiterrahmen (4) vorgesehen ist und an die Metallisierungsschicht (2) gebondet ist; und – eine zweite Bondverbindungsschicht (6), die zwischen dem Halbleiterelement (1) und dem Leiterrahmen (4) vorgesehen ist und die erste Bondverbindungsschicht (3) an den Leiterrahmen (4) bondet, – wobei die erste Bondverbindungsschicht (3) in einem zentralen Bereich in Richtung auf den Leiterrahmen (4) erweitert ist und einen höheren Schmelzpunkt aufweist als die zweite Bondverbindungsschicht (6).

Halbleitervorrichtung

Eine Halbleitervorrichtung weist auf: einen Halbleiterchip (12), der unter Verwendung eines Siliziumkarbids gebildet ist und Elektroden auf einer ersten Oberfläche 12a sowie einer zweiten, der ersten Oberfläche gegenüberliegenden Oberfläche, einen Anschluss (14), der benachbart zu der ersten Oberfläche angeordnet ist und mit der Elektrode auf der ersten Oberfläche durch ein Bond-Element verbunden ist, und einen Kühlkörper (22) der benachbart zu der zweiten Oberfläche angeordnet ist und mit der Elektrode auf zweiten Oberfläche mittels eines Bond-Elements verbunden ist. Die erste Oberfläche (12a) ist eine (0001) Ebene und eine Dickenrichtung des Halbleiterchips entspricht einer [0001] Richtung. Von den Abständen zwischen dem Endabschnitt des Halbleiterchips (12) mit einer quadratischen, zweidimensionalen Form und dem Endabschnitt des Anschlusses (14) mit einer rechteckigen, zweidimensionalen Form ist der kürzeste Abstand L1 in einer [1-100] Richtung kürzer als der kürzeste Abstand L2 in einer ...

Bondpads mit unterschiedlich dimensionierten Öffnungen

Integrierter-Schaltkreis-Die (400), der Folgendes umfasst:mehrere Bondpads (401); undeine Die-Passivierungsschicht mit mehreren unterschiedlich dimensionierten Öffnungen (411, 421, 431, 441), die mehrere der Bondpads (401) freilegen, wobei die mehreren unterschiedlich dimensionierten Öffnungen (411, 421, 431, 441) zwei oder mehr Gruppen von Öffnungen umfassen, wobei jede Gruppe relativ zu der/den anderen Gruppe(n) eine unterschiedliche durchschnittliche Öffnungsgröße aufweist; und wobei Größen der mehreren unterschiedlich dimensionierten Öffnungen auf eine solche Weise variieren, dass Spannungen auf dem Die (400) aufgrund einer asymmetrischen Verteilung der mehreren Bondpads (401) wenigstens teilweise kompensiert werden.

Elektrischer Schaltungsapparat

Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung

Compensating circular lamination for power semiconductor modules

Use is made in power semiconductor modules of compensating circular laminations which absorb thermal stresses due to unequal coefficients of expansion of silicon semiconductor chips and metal parts connected thereto, e.g. copper connecting parts or copper/ceramic substrates. The compensating circular laminations are intended, moreover, to exhibit good electrical and thermal conductivity. The object of the invention is to specify a compensating circular lamination which by comparison with known compensating circular laminations leads to a reduction in the thermal stresses occurring during operation. This object is achieved by means of a compensating circular lamination in which a powdery mixture of different materials, e.g. molybdenum and copper, is sintered to produce a moulded part, the concentration of the powder components used varying by location. The circular lamination exhibits a high molybdenum concentration, e.g. on the side facing a silicon chip, and a high copper fraction on the ...

STRUKTUR UND FERTIGUNGSVERFAHREN EINES DREIDIMENSIONALEN SYSTEMS EINER METALL-LEITERPLATTE, DIE VOR DEM HORIZONTALEN BESTÜCKEN GEÄTZT WIRD

Gegenstand ist eine horizontal bestückte, dreidimensionale, vor dem Bestücken geätzte System-Level-Metall-Leiterplatte, charakterisiert durch einen Metallsubstrat-Rahmen (1). Dieser Metallsubstrat-Rahmen (1) weist Basisbereiche (2) und Stifte (3) auf. Die Frontseiten der Basisbereiche (2) werden mit Chips (5) bestückt, die Frontseiten der Chips (5) sind über Metalldrähte (6) mit den Frontseiten der Stifte (3) verbunden. Auf den Front- oder den Rückseiten der Stifte (3) befinden sich Leitungspunkte (7). Die peripheren Bereiche der Basisbereiche (2), die Bereiche zwischen den Basisbereichen (2) und den Stiften (3), die Bereiche zwischen den Stiften (3), über den Basisbereichen (2) und den Stiften (3) und den Außenbereichen der Chips (5), die Metalldrähte (6) und die Leitungspunkte (7) sind mit Formmasse (8) vergossen und die Oberflächen des Rahmens aus Metall-Substrat (1), der Stifte (3) und der Leitungspunkte (7), die aus der Formmasse (8) herausragen, sind mit einer oxidationsbeständigen ...

Halbleitervorrichtung mit Wärmeabstrahlplatte und Anheftteil

Eine Halbleitervorrichtung mit: einem Wärmeerzeugungselement (10), das durch einen IGBT bereitgestellt wird; einem Anheftteil (50); ersten und zweiten Wärmeabstrahlplatten (20, 30), welche auf ersten und zweiten Seiten (12, 13) des Wärmeerzeugungselementes (10) entsprechend über das Anheftteil (50) angeordnet sind; einem Wärmeabstrahlblock (40), der zwischen der ersten Wärmeabstrahlplatte (30) und dem Wärmeerzeugungselement (10) über das Anheftteil (50) angeordnet ist; und einem Kunstharzverguss (60), der praktisch die gesamte Vorrichtung eingießt, wobei die ersten und zweiten Wärmeabstrahlplatten (20, 30) in der Lage sind, von dem Wärmeerzeugungselement (10) erzeugte Wärme abzustrahlen; das Wärmeerzeugungselement (10) elektrisch und thermisch mit der ersten Wärmeabstrahlplatte (30) über das Anheftteil (50) und den Wärmeabstrahlblock (40) verbunden ist; das Wärmeerzeugungselement (10) elektrisch und thermisch mit der zweiten Wärmeabstrahlplatte (20) über das Anheftteil (50) verbunden ist ...

Halbleiterbauelement mit Verbindungselementen und Verfahren zur Herstellung desselben

Halbleiterbauelement mit Verbindungselementen (6) zur Herstellung einer Verbindung zwischen einem Halbleiterchip (7) aus einem Halbleiterwafer (8) mit diskreten Halbleiterbauelementen (1 bis 5) und einem übergeordneten Schaltungsträger, wobei das Halbleiterbauelement (1 bis 5) eine koplanare Fläche (9) aus Oberseiten (10) der Verbindungselemente (6) und einer Kunststoffmasse (11) aufweist, und wobei das Verbindungselement (6) eine Mesastruktur (12) oder eine Pilzform (13) für eine Oberflächenmontage aufweist und ein Lotdepot in Form einer strukturierten bleifreien Kontaktbeschichtung (14) umfasst, wobei die Verbindungselemente (6) auf Kontaktflächen (15) der Halbleiterchips (7) angeordnet sind, die flächige Erstreckung der Verbindungselemente (6) den Kontaktflächen (15) des Halbleiterchips (7) entsprechen und alle Verbindungselemente (6) auf einer aktiven Oberseite des Halbleiterchips (7) angeordnet sind.

SCHEIBENFOERMIGES HALBLEITERBAUELEMENT GROSSER LEISTUNGSFAEHIGKEIT MIT KUNSTSTOFFUMMANTELUNG

Gehäuseanordnung für elektronische Bauelemente und Verfahren zum Verpacken elektronischer Bauelemente

Gehäuseanordnung für mindestens ein elektronisches Bauelement, mit: – einem Substrat mit einer ersten und einer zweiten Oberfläche, wobei die erste Oberfläche mehrere erste und zweite Kontaktanschlüsse aufweist, die zweite Oberfläche mehrere Verbindungsanschlüsse aufweist und die ersten Kontaktanschlüsse mit den Verbindungsanschlüssen über Durchgangslöcher verbunden sind, – einer elastischen Pufferschicht zwischen der ersten Substratoberfläche und elektronischen Bauelement, wobei eine Oberfläche des elektronischen Bauelementes mit Elektroden gegenüber der ersten Oberfläche des Substrats angeordnet ist, die Pufferschicht mindestens eine Öffnung aufweist, um die mehreren ersten Kontaktanschlüsse freizulassen, die Pufferschicht den Rand des elektronischen Bauelementes umgibt und die einander zugewandten Befestigungsseiten des Randes des elektronischen Bauelementes und der Pufferschicht Schultern und Ecken/Zacken aufweisen und der Rand des elektronischen Bauelementes in die Pufferschicht eingedrückt ...

Anschlusskoerper fuer Halbleiterbauelemente

Verfahren zum Herstellen einer Halbleiteranordnung sowie entsprechende Halbleiteranordnung

Die Erfindung betrifft ein Verfahren zum Herstellen einer Halbleiteranordnung (1), mit wenigstens einem Basiselement (2) und einem Halbleiter (3), wobei der Halbleiter (3) mittels einer Sinterschicht (4) an dem Basiselement (2) befestigt wird. Dabei ist vorgesehen, dass ein an der Sinterschicht (4) unmittelbar anliegender Bereich (9) des Basiselements (2) zumindest bereichsweise perforiert wird. Die Erfindung betrifft weiterhin eine Halbleiteranordnung (1).

HERSTELLUNGSVERFAHREN EINES VERTIKAL INTEGRIERTEN HALBLEITERBAUELEMENTS

HALBLEITERBAUELEMENT IM CHIP-FORMAT UND VERFAHREN ZU SEINER HERSTELLUNG

Halbleitereinheit

Eine Halbleitereinheit umfasst eine Basis, die eine Oberfläche aufweist, auf der eine erste Isolationsschicht angeordnet ist, eine zweite Isolationsschicht, die von der ersten Isolationsschicht getrennt ist, um einen Bereich dazwischen auszubilden, und die parallel zu der Oberfläche der Basis angeordnet ist, auf der die erste Isolationsschicht angeordnet ist, eine einzelne leitfähige Schicht, die über der ersten Isolationsschicht und der zweiten Isolationsschicht angeordnet ist, und eine Halbleitervorrichtung, die mit der leitfähigen Schicht verbunden ist.

Leistungsmodul

Ein Leistungsmodul umfasst eine Leistungshalbleitervorrichtung und eine Chip-Komponente, die auf einem ersten und einem zweiten Schaltungsmuster angeordnet ist, welche elektrisch mit der Leistungshalbleitervorrichtung verbunden sind, und die derart angeordnet ist, dass sie das erste und das zweite Schaltungsmuster überbrückt. Die Chip-Komponente ist derart angeordnet, dass jeweils eine erste und eine zweite Elektrode auf dem ersten und dem zweiten Schaltungsmuster positioniert sind, und die erste und die zweite Elektrode und das erste und das zweite Schaltungsmuster sind jeweils mit Lotschichten verbunden. Zwischen einer unteren Fläche der Chip-Komponente und dem ersten Schaltungsmuster und zwischen der unteren Fläche der Chip-Komponente und dem zweiten Schaltungsmuster sind zwei Abstandhalter vorgesehen, die an Positionen nahe der ersten und der zweiten Elektrode jeweils parallel zueinander liegen. Die Lotschichten existieren nicht auf einer inneren Seite der beiden parallel zueinander ...

TESTSYSTEM VON INTEGRIERTEN SCHALTUNGEN

Halbleiter-Motorantriebsschaltung mit Erkennung des Endes der Lebensdauer

Halbleitervorrichtung mit Abstrahlungsbauteilen

High-density mounting method for and structure of elctronic circuit board

Multi-chip package and method of die-to-die interconnects in same

Semiconductor devices

... 1,104,515. Semi-conductor devices. SIEMENS-SCHUCKERTWERKE A.G. 9 Aug., 1965 [8 Aug., 1964], No. 34085/65. Heading H1K. A semi-conductor body is clamped between pressure members via members the expansion coefficient of which matches that of the body. The members are bonded to the body and a synthetic resin covering extends around the periphery of the member-body assembly on to opposite end faces of the members. In an embodiment the semi-conductor body is of lightlydoped P-type silicon with heavily doped P and N type surface zones. The members are mushroom-shaped and after their attachment, by alloying or soldering, to the surface zones the silicon body is peripherally etched and the resulting recess between the heads of the members filled with alizarin in a synthetic resin. The resin covering, e.g. of epoxy, polyester or silicone which is then applied to form a U-section ring about the device may be keyed to the outer faces of the mushroom heads with the aid of grooves, elevations or depressions ...

A printed circuit board assembly including an interposer

A printed circuit board assembly includes a printed circuit board 22 having a first coefficient of thermal expansion, an integrated circuit die 24 having a base formed from a material having a second coefficient of thermal expansion, and an interposer 30 having a coefficient of thermal expansion intermediate the first and second coefficients of thermal expansion for electrically connecting the board 22 and the die 24. The interposer may be formed from a sheet of material with through holes 32 for electrically connecting the die to the board when a conductive material 26, 28 fills the holes. Alternatively, the interposer may have legs for connecting the die to the board (figure 5). The interposer may be formed from a powdered metal injection molding compound or a polyimide of bismuth telluride. The interposer may be used to connect a silicon based switch such as a field effect transistor to a glass epoxy based PCB.

Semiconductor device and production method

Integral copper column withsolder bump flip-chip

High-density mounting method for and structure of elctronic circuit board

Method of attaching die to circuit board

A semi-conductor device

... 980,558. Semi-conductor devices. SIEMENSSCHUCKERTWERKE A.G. July 13, 1962 [July 21, 1961], No. 27119/62. Heading H1K. A semi-conductor device includes a semiconductor element enclosed in a gas-tight housing and held in electrical and thermal contact with a base portion of the housing by spring means. As shown, semi-conductor body 7 with alloyed-in electrodes 6, 8 of aluminium and goldantimony, respectively, has a plate 4 of molybdenum, tantalum or tungsten alloyed to electrode 6. Electrical contact is made with the device by base-plate 1, 3 and pin 9 which has a plate 9a, similar to plate 4, soldered to its head. A sleeve 24 is provided within a cylinder 11 and two sets of dished springs 27 to 30 and 20 to 22, respectively, press plate 4 on to base 1 and pin 9 on to electrode 8, an insulating disc 18 being provided to isolate pin 9 from the housing. Cylinder 11 is welded to iron ring 2 soldered to the base 1. Pin 9 is gripped at its upper end by spring clip 15 mounted in body 14 soldered ...

Multi-chip package and method of providing die-to-die interconnects in same

SEMICONDUCTOR DEVICE

Semiconductor device manufacture

Ohmic contact is made to an area of a silicon body exposed through an opening in a passivating oxide layer by cleaning the surface in hydrofluoric acid and then electroplating with gold to a thickness of 1000 A DEG from a solution containing specified amounts of potassium cyanide and potassium gold cyanide held at 55 DEG C. After heating to alloy the gold to the silicon, silver is electroplated on it from a solution containing potassium and silver cyanides, potassium hydroxide and carbonate held at 50 DEG C. After further heating additional layers of silver and gold may be plated on the contact.

Packaging system for semiconductor components

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

INTEGRATION OF OPTO-ELECTRONIC ELEMENTS

ADHESIVE, ADHESIVE ARTICLE, CIRCUIT SUBSTRATE FOR SEMICONDUCTOR ASSEMBLY WITH AN ADHESIVE AND A SEMICONDUCTOR ARRANGEMENT THESE CONTAINS

ADHESIVE FILM FOR CHIPBONDIERUNG

MANUFACTURING PROCESS FOR A MATRIXFÖRMIGEN RADIATION DETECTOR AS WELL AS PROCEDURE FOR THE CHANGE OF INDIVIDUAL DETECTION MODULES IN THIS MATRIX

BALL MATRIX HOUSING WITH HEAT DISTRIBUTOR AND ITS PRODUCTION

PROCEDURE FOR THE PRODUCTION OF AN ELECTRONIC BUILDING GROUP WITH AN ELECTRONIC CONSTRUCTION UNIT WITH HIGH-DENSITY ONE, ECONOMICAL MOUNTING

PROCEDURE FOR THE FLIP CHIP ASSEMBLY OF SEMICONDUCTOR DEVICES WITH ADHESIVES

Substrate composite, method and apparatus for bonding substrates

Die Erfindung betrifft ein Verfahren zum Bonden eines ersten Substrats (1) mit einem zweiten Substrat (7) mit folgenden Schritten, insbesondere folgendem Ablauf: - Kontaktierung einer ersten Kontaktfläche (lk) des ersten Substrats (1) mit einer parallel zur ersten Kontaktfläche (lk) ausgerichteten zweiten Kontaktfläche (18k) des zweiten Substrats (7), wodurch eine gemeinsame Kontaktfläche (22) gebildet wird, - Herstellung einer punktuellen, stoffschlüssigen Verbindung zwischen dem ersten Substrat (1) und dem zweiten Substrat (7) außerhalb der gemeinsamen Kontaktfläche (22). Weiterhin betrifft die Erfindung eine korrespondierende Vorrichtung und einen Substratverbund aus einem ersten Substrat (1) und einem zweiten Substrat (7), bei dem eine erste Kontaktfläche (lk) des ersten Substrats (1) mit einer parallel zur ersten Kontaktfläche (lk) ausgerichteten zweiten Kontaktfläche (18k) des zweiten Substrats (7) eine gemeinsame Kontaktfläche (22) bildet, wobei außerhalb der gemeinsamen Kontaktfläche ...

SEMICONDUCTOR RADIATION EMITTER PACKING

VERFAHREN ZUR INTEGRATION WENIGSTENS EINES ELEKTRONISCHEN BAUTEILS IN EINE LEITERPLATTE SOWIE LEITERPLATTE

TEST SYSTEM OF INTEGRATED CIRCUITS

DATA MEDIUM WITH INTEGRATED CIRCUIT AND PROCEDURE FOR THE PRODUCTION OF THE SAME.

SEMICONDUCTOR CHIP ARRANGEMENTS, MANUFACTURING METHODS AND COMPONENTS FOR THE SAME

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

Method for maintaining solder thickness in flipchip attach packaging processes

RAPID-CURING ADHESIVE FORMULATION FOR SEMICONDUCTOR DEVICES

Underfill film compositions

Semiconductor device, method of its manufacture, circuit substrate, and film carrier tape

Semiconductor package, semiconductor device, electronic device and production method for semiconductor package

FUNCTIONAL PACKAGE FOR COMPLEX ELECTRONIC SYSTEMS AND METHOD OF FABRICATION

LIQUID RESIN COMPOSITION AND SEMICONDUCTOR DEVICE USING THE SAME

Disclosed are a liquid resin composition which comprises a liquid epoxy resin (A), an amine hardener (B), core-shell rubber particles (C), and an inorganic filler (D), wherein the solid components account for 65 wt.% or more of the whole liquid resin composition, and a semiconductor device produced using the liquid resin composition.

HIGH PERFORMANCE INTEGRATED CIRCUIT CHIP PACKAGE AND METHOD OF MAKING SAME

A high performance integrated circuit chip package includes a support substrate having conductors extending from one face to the opposite face thereof and a multilayer wiring substrate on the opposite face of the support substrate for connecting chips mounted thereon to one another and to the conductors. A heat sink includes microchannels at one face thereof, with thermally conductive cushions connecting the one face of the heat sink with the exposed back sides of the chips, to provide a high density chip package with high heat dissipation. The multilayer wiring substrate may be formed by a self-aligned thin film wiring method, with a self-aligned lift off method being employed to form internal wiring planes. The support substrate and heat sink may be formed of blocks of material having thermal expansion matching silicon. The cushions are a low melting point solder, preferably pure indium, and are sufficiently thick to absorb thermal stresses, but sufficiently thin to efficiently conduct ...

METHOD FOR THE FORMATION OF CORROSION RESISTANT ELECTRONIC INTERCONNECTIONS

SEMICONDUCTOR CHIP PACKAGES HAVING SOLDER LAYERS OF ENHANCED DURABILITY

TRANSFER METHOD PROVIDING THERMAL EXPANSION MATCHED DEVICES

A method of transferring an integrated circuit (IC) onto an alternative substrate is provided at a wafer level to enable coefficient of thermal expansion (CTE) matching for a circuit layer to a different material. The method is executable relative to a wafer (11) with a circuit layer (12), a first major surface (121), a second major surface (122) opposite the first major surface, and a substrate (13) affixed to the first major surface. The method includes temporarily bonding a handle (14) to the second major surface, removing a majority of the substrate to expose the first major surface and bonding a second substrate (16) to the first major surface with deposited bonding material (15).

SEMICONDUCTOR ELEMENT MODULE AND METHOD FOR MANUFACTURING THE SAME

Provided are a semiconductor element module which is excellent in terms of thermal connection and electric connection, the cooling performance of which can be fully secured, and which is highly reliable, and a method for manufacturing the same. The semiconductor element module comprises an IGBT (2) and a diode (3) on both surfaces of which an electrode is formed, a ceramic substrate (7) on the surface of which wiring circuit layers (4, 5) which are bonded to one surface of the IGBT (2) and the diode (3) are formed and the thermal conductivity of which is high, a ceramic substrate (8) on the surface of which a wiring circuit layer (6) which is bonded to the other surfaces of the IGBT (2) and the diode (3) is formed and the thermal conductivity of which is high, and a sealing member (11) which is sandwiched between the outer edges of the ceramic substrates (7, 8) and with which the inside is sealed. These members are bonded by an ordinary temperature bonding method.

PH SENSOR WITH BONDING AGENT DISPOSED IN A PATTERN

Embodiments described herein provide for a pH sensor that comprises a substrate and an ion sensitive field effect transistor (ISFET) die. The ISFET die includes an ion sensing part that is configured to be exposed to a medium such that it outputs a signal related to the pH level of the medium. The ISFET die is bonded to the substrate with at least one composition of bonding agent material disposed between the ISFET die and the substrate. One or more strips of the at least one composition of bonding agent material is disposed between the substrate and the ISFET die in a first pattern.

PROCESS FOR BRAZING METALLIZED COMPONENTS TO CERAMIC SUBSTRATES

A process for brazing a metallized component to a metallized ceramic-based substrate comprising the steps of: a) applying a second conductor composition over the metallizations on the substrate such that the metallizations are covered by said second conductor composition which consists essentially of a metal powder and an organic medium; b) drying said second conductor composition; c) firing said second conductor composition at a temperature sufficient to sinter the metal powder of the second conductor composition and drive off said organic medium thereby forming a second metallization layer; d) forming an assembly by positioning at least one metallized component on said second metallization layer and a brazing composition at the component-second metallization layer interface; and e) heating said assembly at a temperature sufficient for said brazing composition to form a joint between said component and said second metallization layer.

A CHIP MODULE AND PROCESS FOR THE PRODUCTION THEREOF

A chip module (37) comprising a substrate (12) and at least one chip (38) arranged on the substrate, wherein the chip (11) is contacted via its terminal surfaces onto connecting leads (14, 15) of the substrate (12) and has a thickness d which is reduced compared to its original thickness D as a result of a removal of material on its rear side (39).

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device provided with: a semiconductor element forming an integrated circuit; a plurality of electrode pads formed on the integrating circuit forming surface side of the semiconductor element; bump electrodes for external units electrically connected to the electrode pads through conductive layers; and a stress relieving layer which is formed between the integrated circuit forming surface and electrode pads and between the bump electrodes and the conductive layers, is bonded to the surface, pads, electrodes, and layers, is cut off by at least l/3 from its surface, and is divided into a plurality of areas. The semiconductor device is highly reliable, and can be mounted at a high packing density and at a low cost.

Dispositif semi-conducteur et procédé de fabrication de celui-ci

Halbleiteranordnung

Verfahren zur Herstellung einer Halbleiteranordnung

Halbleiteranordnung

Halbleiteranordnung

Verfahren zum Herstellen einer Halbleiteranordnung und nach diesem Verfahren hergestellte Halbleiteranordnung

Halbleiteranordnung

Halbleiteranordnung

Siliziumgleichrichter

Halbleiteranordnung

Verfahren zur Herstellung einer Halbleiteranordnung

Halbleiteranordnung

Halbleiteranordnung

Halbleiterstromtor vom pnpn-Typ

Halbleiteranordnung

Verfahren zur Herstellung von mit ohmschen Kontakten versehenen Halbleitervorrichtungen

Halbleiteranordnung und Verfahren zum Herstellen derselben

Halbleiterbauelement

Method for molecular adhesion bonding with compensation for radial misalignment

A method for bonding a first wafer on a second wafer by molecular adhesion, where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment.

Wiring board and method for manufacturing the same

A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

Method for Reducing Chip Warpage

A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material.

Semiconductor device

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Resin-Encapsulated Semiconductor Device

A resin-sealed semiconductor device includes a semiconductor chip including a silicon substrate; a die pad on which the semiconductor chip is secured via a solder layer; a sealing resin layer sealing the semiconductor chip; and lead terminals connected electrically with the semiconductor chip. One end portion of the lead terminals is covered by the sealing resin layer. The die pad and the lead terminals are formed of copper and a copper alloy, and the die pad is formed with a thickness larger than a thickness of the lead terminals, which is a thickness of 0.25 mm or more.

Substrate for semiconductor element, method for manufacturing substrate for semiconductor element, and semiconductor device

Provided is a manufacturing method of a semiconductor element substrate including: a step of forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; a step of forming a second photoresist pattern on the second surface of the metallic plate; a step of forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; a step of forming a plurality of concaved parts on the second surface of the metallic plate; a step of forming a resin layer by injecting a resin to the plurality of concaved parts; and a step of etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.

Method of forming a packaged semiconductor device

A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.

Image Sensor Package with Dual Substrates and the Method of the Same

The image sensor package with dual substrates comprises a first substrate with a die receiving opening and a plurality of first through hole penetrated through the first substrate; a second substrate with a die opening window and a plurality of second through hole penetrated through the second substrate, formed on the first substrate. A part of the second wiring pattern is coupled to a part of the third wiring pattern; an image die having conductive pads and sensing array received within the die receiving opening and the sensing array being exposed by the die opening window; and a through hole conductive material refilled into the plurality of second through hole, some of the plurality of second through hole coupling to the conductive pads of the image sensor.

Semiconductor package

A semiconductor package includes a radiator plate including a stress alleviation section, a resin sheet arranged on the radiator plate, a pair of bus bars joined to the radiator plate through the resin sheet at positions at which the stress alleviation section is interposed between the bus bars, and a semiconductor device joined to the pair of bus bars by being sandwiched between the bus bars, and energized from outside through the pair of bus bars.

Light emitting device and manufacturing method of light emitting device

A light emitting device may include a base provided with a recess portion in a side surface thereof, a light emitting element mounted on a main surface of the base, a first resin body filled in an inside of the recess portion, and covering at least the main surface and the light emitting element, a second resin body covering an outside of the first resin body from the main surface side to at least a position of the lowermost end of the recess portion in a direction orthogonal to the main surface, and phosphor, provided in the second resin body, for absorbing light emitted from the light emitting element and then emitting light having a different wavelength.

Power Semiconductor Chip Package

A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad.

Semiconductor device and manufacturing method of the same

A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.

Semiconductor chip with redundant thru-silicon-vias

A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

Semiconductor device having pad structure with stress buffer layer

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Electronic Packaging With A Variable Thickness Mold Cap

An electronic package with improved warpage compensation. The electronic package includes a mold cap having a variable thickness. The variable thickness can have a mound or dimple design. In another embodiment, a method is provided for reducing unit warpage of an electronic package by designing the topography of a mold cap to compensate for warpage.

Semiconductor device including coupling conductive pattern

A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate.

Method of making a light emitting device having a molded encapsulant

Disclosed herein is a method of making a light emitting device having an LED die and a molded encapsulant made by polymerizing at least two polymerizable compositions. The method includes: (a) providing an LED package having an LED die disposed in a reflecting cup, the reflecting cup filled with a first polymerizable composition such that the LED die is encapsulated; (b) providing a mold having a cavity filled with a second polymerizable composition; (c) contacting the first and second polymerizable compositions; (d) polymerizing the first and second polymerizable compositions to form first and second polymerized compositions, respectively, wherein the first and second polymerized compositions are bonded together; and (e) optionally separating the mold from the second polymerized composition. Light emitting devices prepared according to the method are also described.

Methods of fabricating package stack structure and method of mounting package stack structure on system board

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

Integrated circuit packaging system with warpage control and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier.

Corner structure for ic die

One or more integrated circuit chips are flip-chip bonded to a first surface of a substrate. A contact array is fabricated on a second surface of the substrate. Corner structures attached to the integrated circuit chip cover at least two corners of the IC chip.

Flexible underfill compositions for enhanced reliability

Underfill materials for fabricating electronic devices are described. One embodiment includes an underfill composition including an epoxy mixture, an amine hardener component, and a filler. The epoxy mixture may include a first epoxy comprising a bisphenol epoxy, a second epoxy comprising a multifunctional epoxy, and a third epoxy comprising an aliphatic epoxy, the aliphatic epoxy comprising a silicone epoxy. The first, second, and third epoxies each have a different chemical structure. Other embodiments are described and claimed.

Wiring board and method for manufacturing the same

A wiring board including a core substrate having an accommodation portion, an electronic component in the accommodation portion having a substrate, a resin layer on a surface of the substrate and an electrode on the resin layer, a first interlayer resin insulation layer on a surface of the core substrate and a surface of the substrate of the component, and a second interlayer resin insulation layer on the opposite surface of the core substrate and a surface of the substrate having the resin layer and electrode. The first insulation layer has resin in the amount greater than the amount of resin in the second insulation layer such that the total amount of resin component including the resin in the first insulation layer is adjusted to be substantially the same as the total amount of resin component including the resin in the second insulation layer and resin in the resin layer.

Package with embedded chip and method of fabricating the same

A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified.

Microelectronic assemblies having compliancy and methods therefor

A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.

Integrated circuit packaging system with connection structure and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.

Electric part package and manufacturing method thereof

A disclosed electric part package includes a supporting member that includes a first area in which an electric part is arranged, and a second area in which a first opening is positioned, the second area being isolated from the first area; a resin part provided on the supporting member thereby to cover the electric part arranged in the first area, the resin part including an electric terminal exposed in the first opening of the supporting member; and a wiring structure provided on the resin part, the wiring structure being electrically connected to the electric part and the electric terminal of the resin part.

Semiconductor component, semiconductor wafer component, manufacturing method of semiconductor component, and manufacturing method of joining structure

A semiconductor component of the present invention includes a semiconductor element and a joining layer formed on one surface of the semiconductor element and consisting of a joining material containing Bi as an essential ingredient, and projecting sections are formed on a surface of the joining layer on a side opposite to a surface in contact with the semiconductor element. By joining the semiconductor component to an electrode arranged so as to face the joining layer, the generation of a void can be suppressed.

Semiconductor package and manufacturing method therefor

According to one embodiment, there is provided a semiconductor package including: a semiconductor chip; a resin portion formed to cover the semiconductor chip; a wiring structure formed on the resin portion and electrically connected to the semiconductor chip; and a warpage preventing member provided above the resin portion to have a thermal expansion coefficient closer to that of the semiconductor chip than to that of the wiring structure.

Flexible circuit board and manufacturing method thereof

The present invention provides a high-performance flexible circuit board having excellent flexibility, a fine wiring pattern, and fine electric contacts, and a manufacturing method thereof. In a flexible circuit board ( 20 ), a second insulating layer ( 24 ) made of an inorganic material is positioned between a wiring layer ( 25 ) and a first insulating layer ( 23 ) made of an inorganic material.

Semiconductor chip assembly and method for making same

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

Semiconductor device and assembling method thereof

A semiconductor device and an assembling method thereof are provided. The semiconductor device includes a chip, a carrier, a plurality of first conductive elements and a plurality of second conductive elements. The chip has a plurality of first pads. The carrier has a plurality of second pads. The second pads correspond to the first pads. Each first conductive element is disposed between one of the first pads and one of the second pads. Each second conductive element is disposed between one of the first pads and one of the second pads. A volume ratio of intermetallic compound of the second conductive elements is greater than a volume ratio of intermetallic compound of the first conductive elements.

Packaging substrate with conductive structure

A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

Semiconductor package and method for manufacturing semiconductor package

A semiconductor package includes a semiconductor chip including a circuit forming surface and a side surface, and a sealing insulation layer that seals the circuit forming surface and the side surface of the semiconductor chip, the sealing insulation layer having a first surface on a side of the circuit forming surface. At least one wiring layer and at least one insulation layer are formed one on top of the other on the first surface. The wiring layer formed on the first surface is electrically connected to the semiconductor chip. The insulation layer has a reinforcement member installed therein.

Methods and apparatuses to stiffen integrated circuit package

A dam stiffener for a package substrate is presented. In an embodiment, the dam stiffener comprises a thermally curable polymer, and is simultaneously cured with the underfill material to act as stiffener to the substrate. In another embodiment, a curable reservoir material can be dispensed to fill the space between the integrated circuit die and the dam stiffener, forming a thick reservoir layer, acting as an additional stiffener for the package substrate.

Compliant spring interposer for wafer level three dimensional (3d) integration and method of manufacturing

The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.

Semiconductor device and method of fabricating the same

A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip. The molding material may be on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, wherein, in view of a first cross sectional profile, the molding material is separated from sidewalls of the second chip by the homogeneous integral underfill material such that the molding material does not contact sidewalls of the second chip.

Semiconductor device and method of fabricating the semiconductor device

A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.

Device mounting board and method of manufacturing the same, semiconductor module, and mobile device

A device mounting board includes: an insulating resin layer; a wiring layer formed on one of the principal surfaces of the insulating resin layer; a protection layer covering the insulating resin layer and the wiring layer; a protruding electrode electrically connected to the wiring layer, the protruding electrode protruding from the wiring layer toward the insulating resin layer and penetrating through the insulating resin layer; a wiring-layer-side convex portion protruding from the wiring layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer; and a resin-layer-side convex portion protruding from the protection layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer.

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device includes: a support base material, and a semiconductor element bonded to the support base material with a binder, the binder including: a porous metal material that contacts the support base material and the semiconductor element, and a solder that is filled in at least one part of pores of the porous metal material.

Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier

A semiconductor device includes a first semiconductor die or component having a plurality of bumps, and a plurality of first and second contact pads. In one embodiment, the first and second contact pads include wettable contact pads. The bumps are mounted directly to a first surface of the first contact pads to align the first semiconductor die or component. An encapsulant is deposited over the first semiconductor die or component. An interconnect structure is formed over the encapsulant and is connected to a second surface of the first and second contact pads opposite the first surface of the first contact pads. A plurality of vias is formed through the encapsulant and extends to a first surface of the second contact pads. A conductive material is deposited in the vias to form a plurality of conductive vias that are aligned by the second contact pads to reduce interconnect pitch.

Multi-chip module package

A multi-chip module package is provided, which includes a first chip mounted on via a first conductive adhesive and electrically connected to a first chip carrier, a second chip mounted on via a second conductive adhesive and electrically connected to a second chip carrier which is spaced apart from the first chip carrier, wherein the second conductive adhesive is made of an adhesive material the same as that of the first conductive material, a plurality of conductive elements to electrically connect the first chip to the second chip and an encapsulant encapsulating the first chip, the first chip carrier, the second chip, the second chip carrier and the plurality of conductive elements, allowing a portion of both chip carriers to be exposed to the encapsulant, so that the first chip and second chip are able to be insulated by the separation of the first and second chip carriers.

Package 3D Interconnection and Method of Making Same

A method of manufacturing an integrated circuit (IC) package is provided. The method includes stacking an interposer substrate and a device structure, the interposer substrate having a first plurality of contact members formed on a first surface of the interposer substrate and the device structure having a second plurality of contact members that are exposed at a surface of the device structure, and laminating the interposer substrate and the device structure such that the first plurality of contact members are physically and electrically coupled to the second plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the second plurality of contact members.

Semiconductor apparatus and method for manufacturing the same

According to one embodiment, a semiconductor apparatus includes a semiconductor device, a heat spreader, a regulating unit, a containing unit, and a holding unit. The heat spreader is bonded to the semiconductor device with an interposed solder layer. The regulating unit is configured to regulate a dimension between the semiconductor device and the heat spreader. The containing unit is configured to contain melted solder in an interior of the containing unit. The holding unit is configured to allow melted solder held in an interior of the holding unit. The holding unit is configured to replenish the melted solder in the case where an amount of the melted solder contained in the containing unit is insufficient. The holding unit is configured to recover the melted solder in the case where the amount of the melted solder contained in the containing unit is excessive.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate. A heat radiator is disposed on the heat conductive member. The heat conductive member thermally connecting the semiconductor element to the heat radiator reduces the risk that electromagnetic noise may be emitted from or may be incident on the semiconductor element.

Chip-packaging module for a chip and a method for forming a chip-packaging module

A chip-packaging module for a chip is provided, the chip-packaging module including an isolation material configured to cover a chip on at least one side, the isolation material having a first surface proximate to a first side of a chip, and said isolation material having a second surface facing an opposite direction to the first surface; and at least one layer in connection with the chip first side, the at least one layer further configured to extend from the chip first side to the second surface of the isolation material.

Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP

A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer.

Semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device, includes temporarily fixing a semiconductor chip to a supporting member to direct a connection electrode toward the supporting member side, forming an insulating layer for preventing resin-permeation covering the semiconductor chip, on the supporting member and the semiconductor chip, forming a resin substrate sealing a periphery and a back surface side of the semiconductor chip, on the insulating layer, and removing the supporting member to expose the connection electrode of the semiconductor chip. A build-up wiring is connected directly to the connection electrode of the semiconductor chip.

Semiconductor package, electrical and electronic apparatus including the semiconductor package, and method of manufacturing the semiconductor package

In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring.

Method for producing reconstituted wafers and method for producing semiconductor devices

In order to provide a method for producing semiconductor devices that can use the highly productive W to W method, and achieve a high yield, a method for producing semiconductor devices comprises a step (S 401 ) in which a reconstituted wafer is prepared by replacing defective chips with non-defective chips, a step (S 403 ) in which the reconstituted wafer and the base wafer are connected to one another by laminating, a step (S 406 ) in which through-electrodes are formed in the reconstituted wafer, and a step (S 409 ) in which a separate reconstituted wafer is laminated onto and connected to the reconstituted wafer having through-electrodes.

Semiconductor module manufacturing method, semiconductor module, and manufacturing device

In the disclosed method for manufacturing a semiconductor module, a metal layer and a cooler, which have different coefficients of thermal expansion from each other, are joined into a single unit via an insulating resin sheet. A work, comprising a semiconductor element placed on the metal layer with solder interposed therebetween, is fed into a reflow furnace. The work, in that state, is heated in the reflow furnace, thereby mounting the semiconductor element to the metal layer. The heating is carried out such that the temperature of the cooler and the temperature of the metal layer differ by an amount that make the cooler and the metal layer undergo the same amount of thermal expansion as each other.

Enhanced Bump Pitch Scaling

An integrated circuit (IC) device is provided. In an embodiment the IC device includes an IC die configured to be bonded onto an IC routing member and a first plurality of pads that is located on a surface of the IC die, each pad being configured to be coupled to a respective pad of a second plurality of pads that is located on a surface of the IC routing member. A pad of the first plurality of pads is offset relative to a respective pad of the second plurality of pads such that the pad of the first plurality of pads is substantially aligned with the respective pad of the second plurality of pads after the IC die is bonded to the IC routing member.

Flip chip assembly process for ultra thin substrate and package on package assembly

In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.

Bond pad design for improved routing and reduced package stress

A bond pad design comprises a plurality of bond pads on a semiconductor chip and a plurality of under-bump metallurgy (UBM) layers formed on respective bond pads of the plurality. At least one of the bond pads has an elongated shape having an elongated portion and a contracted portion, the elongated portion oriented substantially along a stress direction radiating from a center to the periphery of the chip.

Semiconductor device and method for manufacturing same

A dug portion ( 50 ) in which a die-bonding material is filled is provided to a lower surface of a stamping nozzle ( 42 ) used in a step of applying the die-bonding material onto a chip mounting portion of a wiring board. Planar dimensions of the dug portion ( 50 ) are smaller than external dimensions of a chip to be mounted on the chip mounting portion. In addition, a depth of the dug portion ( 50 ) is smaller than a thickness of the chip. When the thickness of the chip is 100 μm or smaller, a problem of crawling up of the die-bonding material to an upper surface of the chip is avoided by applying the die-bonding material onto the chip mounting portion using the stamping nozzle ( 42 ).

Semiconductor element-embedded substrate, and method of manufacturing the substrate

A semiconductor element-embedded substrate includes a semiconductor element; a chip component; a peripheral insulating layer covering at least the outer circumferential side surfaces thereof; an upper surface-side wiring line provided on the upper surface side of the substrate; and a lower surface-side wiring line provided on the lower surface side of the substrate. The built-in semiconductor element includes a terminal on the upper surface side thereof, and this terminal is electrically connected to the upper surface-side wiring line. The built-in chip component includes an upper surface-side terminal electrically connected to the upper surface-side wiring line; a lower surface-side terminal electrically connected to the lower surface-side wiring line; and a through-chip via penetrating through the chip component to connect the upper surface-side terminal and the lower surface-side terminal.

Epoxy resin composition for semiconductor encapsulation and semiconductor device using the same

The present invention relates to an epoxy resin composition for semiconductor encapsulation, including the following components (A) to (D): (A) an epoxy resin; (B) a phenol resin; (C) an inorganic filler, and (D) a silicone compound containing an alkoxy group directly bonded to silicon atom in an amount of 10 to 45 wt % based on the entire silicone compound and having a specific gravity of 1.10 to 1.30.

TCE Compensation for Package Substrates for Reduced Die Warpage Assembly

A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages.

Three dimensional semiconductor assembly board with bump/flange supporting board, coreless build-up circuitry and built-in electronic device

A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.

Chip package structure

A chip package structure includes a chip, a flexible substrate, first leads and second leads. First bumps, second bumps and a seal ring are disposed on an active surface of the chip. The first and second bumps are respectively adjacent to first and second edges of the chip. The seal ring is located between the bumps and the edges. The chip is disposed in a chip mounting region of the flexible substrate. The first and second edges correspond to first and second sides of the chip mounting region respectively. The first leads disposed on the flexible substrate enter the chip mounting region through the first side and extend toward the second side to electrically connect the second bumps respectively. The second leads disposed on the flexible substrate enter the chip mounting region through the second side and extend toward the first side to electrically connect the first bumps respectively.

Stackable integrated circuit package system

A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.

Fabrication method of packaging substrate having through-holed interposer embedded therein

A packaging substrate having a through-holed interposer embedded therein and a fabrication method of the packaging substrate are provided, where the packaging substrate includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer.

Semiconductor device and communication method

A semiconductor device, includes a substrate with a first surface, a semiconductor chip disposed over the first surface of the substrate, the semiconductor chip including a first region and a second region, and an encapsulant resin formed over the first surface of the substrate and encapsulating the semiconductor chip. The encapsulant resin has a thickness that is less at the first region of the semiconductor chip than that at the second region.

Method for manufacturing semiconductor device and semiconductor device

According to one embodiment, between the mounting substrate and the semiconductor chip, there is a joint support layer including a metal or its alloy selected from the group of Cu, Al, Ag, Ni, Cr, Zr and Ti and a melt layer laminated across the joint support layer, and formed of a metal selected from the group of Sn, Zn and In or of an alloy of at least two metals selected from the same metals. The process of joining the mounting substrate and the semiconductor chip includes intervening a joining layer which is formed, at least for its outermost layer, by the melt layer, maintaining the temperature to be higher than the melting point of the melt layer, then forming an alloy layer which has a higher melting point than the melt layer by liquid phase diffusion.

Die package including encapsulated die and method of manufacturing the same

Disclosed herein is a die package including an encapsulated die, including: a die including pads on one side thereof; an encapsulation layer covering lateral sides of the die; a support layer covering the encapsulation layer and one side of the die; a passivation layer formed on the other side of the die such that the pads are exposed therethrough; and a redistribution layer formed on the passivation layer such that one part thereof is connected with the pad. Here, since one side of the die is supported by the support layer and the encapsulation layer is formed on only the lateral side of the die, the warpage of the die package due to the difference in thermal expansion coefficient can be minimized

Power Module and Power Converter Containing Power Module

A power module includes a semiconductor chip, a first coupling conductor with one main surface coupled to one main surface of the semiconductor chip, a second coupling conductor with one main surface coupled to the other main surface of the semiconductor chip, a coupling terminal supplied with electrical power from the direct current power source, and resin material to seal the semiconductor chip, and in which the resin member has a protruding section that protrudes from the space where the first and second coupling conductors are formed opposite each other, and the coupling terminal is clamped on the protruding section, and at least one of the first or second coupling conductors is coupled to a coupling terminal by way of a metallic material that melts at a specified temperature.

Semiconductor Device and Method of Forming a Reconfigured Stackable Wafer Level Package with Vertical Interconnect

A semiconductor device has a carrier with a semiconductor die mounting area. A plurality of conductive posts is formed in a periphery of the semiconductor die mounting area and in the carrier. A first portion of the carrier is removed to expose a first portion of the plurality of conductive posts such that a second portion of the plurality of conductive posts is embedded in a second portion of the carrier. A first semiconductor die is mounted to the semiconductor die mounting area and between the first portion of the plurality of conductive posts. A first encapsulant is deposited around the first semiconductor die and around the first portion of the plurality of conductive posts. A second portion of the carrier is removed to expose the second portion of the plurality of conductive posts. An interconnect structure is formed over the plurality of conductive posts and the first semiconductor die.

Discontinuous thin semiconductor wafer surface features

A semiconductor wafer has a semiconductor substrate and films on the substrate. The substrate and/or the films have at least one etch line creating a discontinuous surface that reduces residual stress in the wafer. Reducing residual stress in the semiconductor wafer reduces warpage of the wafer when the wafer is thin. Additionally, isolation plugs may be used to fill a portion of the etch lines to prevent shorting of the layers.

Interposer, circuit board module, and method for manufacturing interposer

An interposer includes a substrate having first and second opposing surfaces, the substrate having a sheet shape; and a plurality of spring electrodes fixed to the substrate in a certain arrangement, each of the plurality of the spring electrodes including a first pad disposed opposite the first surface of the mesh and extending in a first direction, a second pad disposed opposite the second surface of the mesh and extending in the first direction, and a post extending through the substrate between the first and second surfaces and connecting an end of the first pad to an end of the second pad.

Semiconductor device having multiple bump heights and multiple bump diameters

A semiconductor die includes a first contact stack including a first UBM pad on a first die pad, a second contact stack including a second UBM pad on a second die pad, and a third contact stack including a third UBM pad on a third die pad. The second UBM pad perimeter is shorter than the first UBM pad perimeter, and the third UBM pad perimeter is longer than the second UBM pad perimeter. A first solder bump is on the first UBM pad, a second solder bump is on the second UBM pad, and a third solder bump is on the third UBM pad. The first solder bump, second solder bump and third solder bump all have different sizes.

Semiconductor device, electronic device, and semiconductor device manufacturing method

A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on witch a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration.

Flat Laminate, Symmetrical Test Structures and Method of Use To Gauge White Bump Sensitivity

A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.

Method to form solder deposits and non-melting bump structures on substrates

Described is a method of forming a metal or metal alloy layer onto a substrate comprising the following steps i) provide a substrate including a permanent resin layer on top of at least one contact area and a temporary resin layer on top of the permanent resin layer, ii) contact the entire substrate area including the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface and i) electroplate a metal or metal alloy layer onto the conductive layer.

Methods of manufacturing stress buffer structures in a mounting structure of a semiconductor device

A mounting structure for a semiconductor device is formed to include a stepwise stress buffer layer under a stepwise UBM structure.

Connecting material, method for manufacturing connecting material and semiconductor device

In a connecting material of the present invention, a Zn series alloy layer is formed on an outermost surface of an Al series alloy layer. In particular, in the connecting material, an Al content of the Al series alloy layer is 99 to 100 wt.% or a Zn content of the Zn series alloy layer is 90 to 100 wt.%. By using this connecting material, the formation of an Al oxide film on the surface of the connecting material at the time of the connection can be suppressed, and preferable wetness that cannot be obtained with the Zn—Al alloy can be obtained. Further, a high connection reliability can be achieved when an Al series alloy layer is left after the connection, since the soft Al thereof functions as a stress buffer material.

Method for forming gallium nitride devices with conductive regions

Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.

METHOD OF MANUFACTURING GaN-BASED SEMICONDUCTOR DEVICE

A method of manufacturing a GaN-based semiconductor device includes the steps of: preparing a composite substrate including: a support substrate having a thermal expansion coefficient at a ratio of not less than 0.8 and not more than 1.2 relative to a thermal expansion coefficient of GaN; and a GaN layer bonded to the support substrate, using an ion implantation separation method; growing at least one GaN-based semiconductor layer on the GaN layer of the composite substrate; and removing the support substrate of the composite substrate by dissolving the support substrate. Thus, the method of manufacturing a GaN-based semiconductor device is provided by which GaN-based semiconductor devices having excellent characteristics can be manufactured at a high yield ratio.

Integrated Circuit Having Stress Tuning Layer and Methods of Manufacturing Same

Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

Solid state apparatus

A solid state apparatus comprising, a printed circuit board having a first and a second surface that are opposite surfaces, a semiconductor chip for imaging arranged on the first surface, a sealing resin arranged to cover the printed circuit board and the semiconductor chip, and a translucent member arranged on the sealing resin, the solid state apparatus having a first region located inward of an outer edge of the semiconductor chip, and a second region located outward of the outer edge, the printed circuit board comprising, on the first surface, a first terminal electrically connected to the semiconductor chip, and comprising, on the second surface, a second terminal electrically connected to the first terminal within the printed circuit board, the second terminal being arranged in the first region.

Packaging Process Tools and Systems, and Packaging Methods for Semiconductor Devices

Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

Semiconductor device

The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7 D 2 , a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

Semiconductor device and its manufacture method

A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.

Semiconductor package substrate and method, in particular for mems devices

A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.

Semiconductor chips including passivation layer trench structure

An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.

Semiconductor package having heat spreader and method of forming the same

A semiconductor chip and a first heat dissipation pattern are mounted on a substrate. The first heat dissipation pattern has an opening therein and exposes the semiconductor chip therethrough. A second heat dissipation pattern including a thermal interface material (TIM) is interposed between a side surface of the semiconductor chip and the first heat dissipation pattern.

Semiconductor package with integrated substrate thermal slug

To reduce the thermal stresses that may be caused by a difference in thermal expansion coefficients between a molded casing and an active side of a semiconductor device embedded in the molded casing, and thus reduce the number of corresponding failures caused by the thermal stresses, the active side of the semiconductor device is arranged face-down, towards a substrate supporting the semiconductor device. The semiconductor device includes a through via that electrically connects the active side of the semiconductor device to a passive side of the semiconductor device. A wire bond electrically connects the passive side of the semiconductor device to the substrate. To increase the dissipation of heat generated in the semiconductor device, a thermally conductive slug may be disposed in the substrate, and the active side of the semiconductor device may be attached to the thermally conductive slug.

Epoxy encapsulating and lamination adhesive and method of making same

An adhesive includes an epoxy resin and a hardener. The hardener includes trioxdiamine, diaminodicyclohexylmethane, toluene diamine, and bisphenol-A dianhydride.

Embedded Electrical Component Surface Interconnect

An electrical component package is disclosed comprising: an electrical component having an embedded surface, a structure attached to the electrical component opposite the embedded surface, a conductive adhesive directly attached to the embedded surface, where the conductive adhesive is shaped to taper away from the embedded surface, and an encapsulation material covering the conductive adhesive and the electrical component. In various embodiments, the tapered conductive adhesive facilitates the securing of the conductive adhesive to the electrical component by the encapsulation material. Also disclosed are various methods of forming an electrical component package having a single interface conductive interconnection on the embedded surface. The conductive interconnection is configured to maintain an interconnection while under stress forces. Further disclosed in a method of applied a conductive adhesive that enables design flexibility regarding the shape and depth of the conductive interconnection.

Starting material for a sintered bond and process for producing the sintered bond

The invention relates to a starter material for a sintering compound, said starter material comprising first particles of at least one metal having a first coating which is applied to the first particles and consists of an organic material, and second particles which contain an organic metal compound and/or a precious metal oxide, the organic metal compound and/or the precious metal oxide being converted during heat treatment of the starter material into the fundamental elemental metal and/or precious metal. The invention is characterized in that the second particles have a core of at least one metal and a second coating which is applied to the core and contains the organic metal compound and/or precious metal oxide. Furthermore, the first coating contains a reducing agent by means of which the organic metal compound and/or the precious metal oxide is/are reduced to the elemental metal and/or precious metal at a temperature below the sintering temperature of the elemental metal and/or precious metal.

Semiconductor Device and Method for Forming Semiconductor Package Having Build-Up Interconnect Structure Over Semiconductor Die with Different CTE Insulating Layers

A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.

Fully molded fan-out

A method for manufacturing a device package may include constructing a spacer element coupled with a surface of a semiconductor die unit, where the spacer element is configured to create a gap between the semiconductor die unit and a surface of a carrier, and encapsulating the semiconductor die unit within a mold compound, where the encapsulating includes introducing the mold compound into the gap.

Semiconductor package, semiconductor apparatus and method for manufacturing semiconductor package

A semiconductor package includes: a metal plate including a first surface, a second surface and a side surface; a semiconductor chip on the first surface of the metal plate, the semiconductor chip comprising a first surface, a second surface and a side surface; a first insulating layer that covers the second surface of the metal plate; a second insulating layer that covers the first surface of the metal plate, and the first surface and the side surface of the semiconductor chip; and a wiring structure on the second insulating layer and including: a wiring layer electrically connected to the semiconductor chip; and an interlayer insulating layer on the wiring layer. A thickness of the metal plate is thinner than that of the semiconductor chip, and the side surface of the metal plate is covered by the first insulating layer or the second insulating layer.

Semiconductor device and manufacturing method thereof

A semiconductor device includes an interlayer insulating film containing Si, O, C, and H, an under-bump metal film disposed over the interlayer insulating film and containing Ni, and a bump electrode disposed over the under-bump metal film. In the interlayer insulating film, a ratio of a peak height of Si—CH 3 near a wave number 1270 cm −1 to a peak height of Si—O near a wave number 1030 cm −1 obtained by Fourier-transform infrared spectroscopy (FTIR) is 0.15 or greater and 0.27 or less. A ratio of a peak height of Si—CH 2 —Si near a wave number 1360 cm −1 to the peak height of Si—CH 3 near the wave number 1270 cm −1 is 0.031 or greater.

Semiconductor Device and Method of Forming a Robust Fan-Out Package including Vertical Interconnects and Mechanical Support Layer

A semiconductor device has a semiconductor die. An encapsulant is deposited around the semiconductor die. An interconnect structure having a conductive bump is formed over the encapsulant and semiconductor die. A mechanical support layer is formed over the interconnect structure and around the conductive bump. The mechanical support layer is formed over a corner of the semiconductor die and over a corner of the interconnect structure. An opening is formed through the encapsulant that extends to the interconnect structure. A conductive material is deposited within the opening to form a conductive through encapsulant via (TEV) that is electrically connected to the interconnect structure. A semiconductor device is mounted to the TEV and over the semiconductor die to form a package-on-package (PoP) device. A warpage balance layer is formed over the encapsulant opposite the interconnect structure.

Wiring substrate and method of manufacturing the same

There is provided a wiring substrate. The wiring substrate includes: an insulating layer; first electrode pads having first exposed surfaces, the first exposed surfaces being exposed from the insulating layer; and second electrode pads having second exposed surfaces, the second exposed surfaces being exposed from the insulating layer. There is a level difference between the first exposed surfaces and the second exposed surfaces.

Semiconductor module

In the semiconductor module comprising a package substrate, a first semiconductor package, and a semiconductor bare chip, such problems as the occurrence of a wire short caused by warpage of the first semiconductor package and non-filling and the like at the time of resin sealing can be solved. A semiconductor module 10 , having: a semiconductor package 6 , which is obtained by mounting and resin-sealing a semiconductor bare chip on a first package substrate; a semiconductor bare chip 2 ; and a second package substrate 12 , the semiconductor module being characterized in that the semiconductor package 6 is mounted on the second package substrate 12 and the semiconductor bare chip 2 is mounted on the semiconductor package 6.

Bonded processed semiconductor structures and carriers

Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

Method and apparatus for reducing package warpage

Embodiments of mechanisms for flattening a packaged structure are provided. The mechanisms involve a flattening apparatus and the utilization of protection layer(s) between the packaged structure and the surface(s) of the flattening apparatus. The protection layer(s) is made of a soft and non-sticking material to allow protecting exposed fragile elements of the packaged structure and easy separation after processing. The embodiments of flattening process involve flattening the warped packaged structure by pressure under elevated processing temperature. Processing under elevated temperature allows the package structure to be flattened within a reasonable processing time.

Wiring substrate, manufacturing method thereof, and semiconductor package

A disclosed wiring substrate includes an insulating layer, a recess formed on a surface of the insulating layer, and an alignment mark formed inside of the recess, wherein a face of the alignment mark is roughened, recessed from the surface of the insulating layer, and exposed from the recess.

Semiconductor Method and Device of Forming a Fan-Out Device with PWB Vertical Interconnect Units

A semiconductor device has a modular interconnect unit or interconnect structure disposed in a peripheral region of the semiconductor die. An encapsulant is deposited over the semiconductor die and interconnect structure. A first insulating layer is formed over the semiconductor die and interconnect structure. A plurality of openings is formed in the first insulating layer over the interconnect structure. The openings have a pitch of 40 micrometers. The openings include a circular shape, ring shape, cross shape, or lattice shape. A conductive layer is deposited over the first insulating layer. The conductive layer includes a planar surface. A second insulating layer is formed over the conductive layer. A portion of the encapsulant is removed to expose the semiconductor die and the interconnect structure. The modular interconnect unit includes a vertical interconnect structure. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.