МНОГОСЛОЙНАЯ КОРПУСНАЯ СБОРКА СО ВСТРОЕННОЙ АНТЕННОЙ

Использование: для создания многослойной корпусной сборки. Сущность изобретения заключается в том, что корпусная сборка интегральной микросхемы (IC) содержит первый слой, имеющий первую сторону и вторую сторону, расположенную напротив первой стороны; второй слой, соединенный с первой стороной первого слоя; один или более антенных элементов, соединенных со вторым слоем; и третий слой, соединенный со второй стороной первого слоя, при этом первый слой представляет собой армирующий слой, имеющий модуль упругости при растяжении больше, чем модуль упругости при растяжении второго слоя и третьего слоя, при этом первый слой образует плоскость, проходящую в горизонтальном направлении; и никакие металлизированные элементы для маршрутизации электрических сигналов в горизонтальном направлении не расположены непосредственно на первом слое. Технический результат - обеспечение возможности уменьшения потерь в проводниках. 3 н. и 16 з.п. ф-лы, 9 ил.

СПОСОБ СОЕДИНЕНИЯ МНОГОУРОВНЕВЫХ ПОЛУПРОВОДНИКОВЫХ УСТРОЙСТВ

Изобретение относится к многоуровневым полупроводниковым приборам. Полупроводниковый узел содержит первый блок кристалла и второй блок кристалла. Первый блок кристалла включает в себя первый кристалл, имеющий верхнюю поверхность первого кристалла и нижнюю поверхность первого кристалла, и первую кромку, отходящую в поперечном направлении от первого кристалла, причем первая кромка включает в себя верхнюю поверхность первой кромки, расположенную вблизи верхней поверхности первого кристалла, и нижнюю поверхность первой кромки, расположенную вблизи нижней поверхности первого кристалла, при этом нижняя поверхность первого кристалла и нижняя поверхность первой кромки расположены вблизи входного и выходного массивов для полупроводникового узла. Второй блок кристалла включает в себя второй кристалл, имеющий верхнюю поверхность второго кристалла и нижнюю поверхность второго кристалла, и вторую кромку, отходящую в поперечном направлении от второго кристалла, причем вторая кромка включает в себя верхнюю ...

СПОСОБ И УСТРОЙСТВО ДЛЯ ОЧИСТКИ, РАЗДЕЛЕНИЯ, МОДИФИКАЦИИ И/ИЛИ ИММОБИЛИЗАЦИИ ХИМИЧЕСКИХ ИЛИ БИОЛОГИЧЕСКИХ ОБЪЕКТОВ, НАХОДЯЩИХСЯ В ТЕКУЧЕЙ СРЕДЕ, И ОПОРА ИЗ МИКРОПРОВОЛОКИ

... 1. Устройство для очистки, разделения, модификации и/или иммобилизации химических или биологических объектов, находящихся в текучей среде, посредством связывания химического или биологического объекта с функциональным покрытием или лигандами, находящимися на поверхности опор из микропроволоки при отсутствии воздействия магнитного поля, создаемого между опорами из микропроволоки и частицами, находящимися в текучей среде, на разделение названных частиц, которое содержит по меньшей мере одну опору из микропроволоки, закрепленную своими концами и имеющую многослойную структуру, состоящую из центрального стержня и по меньшей мере одного покрывающего слоя и пригодную для связывания химических или биологических объектов, при этом поверхность микропроволоки модифицирована путем присоединения лигандов или нанесением на нее функционального покрытия. ! 2. Устройство по п.1, в котором центральный стержень и покрывающие слои выполнены из материала, выбранного из группы, включающей стеклянный, металлический ...

АРХИТЕКТУРА СОЗДАНИЯ ГИБКИХ КОРПУСОВ

СПОСОБ ВСТРАИВАНИЯ СУЩЕСТВУЮЩЕГО КРЕМНИЕВОГО КРИСТАЛЛА В 3-МЕРНЫЙ ИНТЕГРИРОВАННЫЙ ПАКЕТ

... 1. Устройство, содержащее: ! первый кристалл, содержащий множество электропроводных, продолжающихся через подложку пропускных отверстий (ПОК), причем первый кристалл содержит площадь поверхности; и ! множество вторых кристаллов, каждый из которых содержит множество контактных точек, соединенных с ПОК первого кристалла, причем множество вторых кристаллов расположено так, что они совместно составляют площадь поверхности, приблизительно равную площади поверхности первого кристалла. !2. Устройство по п.1, в котором первый кристалл и множество вторых кристаллов соединены в конфигурации, в которой передняя сторона обращена к задней стороне. ! 3. Устройство по п.2, в котором первый кристалл содержит ЦПУ или логический кристалл. ! 4. Устройство по п.3, в котором множество вторых кристаллов содержит модули запоминающего устройства. ! 5. Устройство по п.3, в котором множество вторых кристаллов содержит модули динамического оперативного запоминающего устройства. ! 6. Устройство по п.1, в котором первый ...

Halbleiteranordnung mit Metallplatte

Verfahren zum Kapseln intergrierter Schaltungen und über das Verfahren hergestellte integrierte Schaltungsbausteine

Verfahren zum Kapseln integrierter Schaltungen, umfassend: Anbringen einer ersten integrierten Schaltung an einer ersten Fläche eines Substrats mit einer elektrischen Verbindung zwischen entsprechenden Kontakten des Substrats und der ersten integrierten Schaltung; Anbringen einer zweiten integrierten Schaltung an einer zweiten Fläche eines Substrats mit einer elektrischen Verbindung zwischen elektrischen Kontakten des Substrats und der zweiten integrierten Schaltung; und einen Ausformschritt, bei dem die erste und zweite integrierte Schaltung in Harz gekapselt werden.

Gestapelte Mehrchip-Module und Verfahren zur Herstellung

Leiterplatte für Plastikhalbleitergehäuse

MEHRSCHICHTIGE LEITERPLATTE

ELEKTRONISCHES BAUELEMENTGEHÄUSE

Die Technologie eines elektronischen Bauelementgehäuses ist offenbart. Ein elektronisches Bauelementgehäuse gemäß der vorliegenden Offenbarung kann ein Gehäusesubstrat, eine elektronische Komponente, eine Formmasse, die die elektronische Komponente einkapselt, und eine Redistributionsschicht umfassen, die derart angeordnet ist, dass die Formmasse zwischen dem Gehäusesubstrat und der Redistributionsschicht ist. Die Redistributionsschicht und das Gehäusesubstrat können elektrisch gekoppelt sein. Außerdem können die Redistributionsschicht und die elektronische Komponente elektrisch gekoppelt sein, um die elektronische Komponente und das Gehäusesubstrat elektrisch zu koppeln. Zugeordnete Systeme und Verfahren sind auch offenbart.

Semiconductor substrate with stackable semiconductor module

In the top middle section of the substrate main body is formed a cavity and coupling holes passing vertically through the edge sections of the substrate main body (21). In one cavity side wall is formed a stepped section (23). The ends of each conductive wire (22) is exposed on the top side of the stepped section, while the other wire ends extend into a coupling hole each. A conductive metal rod (26) is in each coupling hole, while a conductive terminal (27) is formed in top and bottom side of the main body for electric connections of both ends of each rod.

Halbleiterstruktur mit Passivierung durch Versatz zur Verringerung der Elektromigration

Es wird eine Halbleiterstruktur beschrieben, die eine Vielzahl übereinander gestapelter Halbleiterchips in einer dreidimensionalen Anordnung beinhaltet. Ein erster Halbleiterchip steht in Kontakt mit einem zweiten Halbleiterchip. Der erste Halbleiterchip beinhaltet eine Silicium-Durchkontaktierung (TSV), welche sich durch den ersten Halbleiterchip hindurch erstreckt; eine elektrisch leitende Kontaktfläche an einer Oberfläche des ersten Halbleiterchips, wobei die TSV in Kontakt mit einer ersten Seite der elektrisch leitenden Kontaktfläche endet; eine Passivierungsschicht, welche die elektrisch leitende Kontaktfläche bedeckt, wobei die Passivierungsschicht eine Vielzahl von Öffnungen aufweist; und eine Vielzahl elektrisch leitender Strukturen, welche in der Vielzahl von Öffnungen und in Kontakt mit einer zweiten Seite der elektrisch leitenden Kontaktfläche ausgebildet sind, wobei der Kontakt der Vielzahl elektrisch leitender Strukturen mit der elektrisch leitenden Kontaktfläche in Bezug auf ...

LOTTRAEGER, VERFAHREN ZU DESSEN HERSTELLUNG UND VERFAHREN ZUR MONTAGE VON HALBLEITERANORDNUNGEN UNTER DESSEN VERWENDUNG

Bauelement mit einem Halbleiterchip und Verfahren zur Herstellung eines Moduls mit gestapelten Bauelementen

Bauelement (300), umfassend: einen Träger (30), ein auf dem Träger (30) abgeschiedenes erstes Material (31), wobei das erste Material (31) einen Elastizitätsmodul von unter 100 MPa aufweist, einen über dem ersten Material (31) platzierten Halbleiterchip (11), ein auf dem Träger (30) und dem Halbleiterchip (11) abgeschiedenes zweites Material (12), wobei das zweite Material (12) einen Elastizitätsmodul von unter 100 MPa aufweist, eine Metallschicht (10) umfassend eine erste Fläche (13) und eine der ersten Fläche (13) gegenüberliegende zweite Fläche (14), wobei die Metallschicht (10) über dem zweiten Material (12) platziert ist und ihre erste Fläche (13) dem zweiten Material (12) zugewandt ist, und mindestens ein Durchgangsloch (38, 39), das von der ersten Fläche (13) der Metallschicht (10) durch das zweite Material (12) und den Träger (30) verläuft.

Integriertes Passivvorrichtungs-Package und Verfahren zum Ausbilden von diesem

Ein Vorrichtungs-Package umfasst einen ersten Die, einen zweiten Die und eine Moldmasse, die sich entlang von Seitenwänden des ersten Die und des zweiten Die erstreckt. Das Package umfasst ferner Umverteilungsschichten (RDLs), die sich seitlich über Kanten des ersten Die und des zweiten Die hinaus erstrecken. Die RDLs umfassen einen Eingabe-/Ausgabekontakt (I/O-Kontakt), der mit dem ersten Die und dem zweiten Die elektrisch verbunden ist, und der I/O-Kontakt ist an einer Seitenwand des Vorrichtungs-Package freigelegt, die im Wesentlichen senkrecht zu einer den RDLs entgegengesetzten Fläche der Moldmasse ist.

UND VERFAHREN ZU SEINER HERSTELLUNG

HF-Frontend für ein Automobilradarsystem

Es wird eine Anordnung (1) für ein HF-Frontend eines linsenbasierten 77-GHz Automobilradarsystems beschrieben, aufweisend ein HF-Substrat (3) aufweisend eine Oberseite (3a) und eine Unterseite (3b), und einen Halbleiterchip (2), wobei der Halbleiterchip (2) auf der Oberseite (3a) des HF-Substrats (3) angeordnet ist, und wobei das HF-Substrat (3) ein mechanisch festes Material aufweist. Ferner wird ein Verfahren zur Herstellung einer Anordnung (1) für ein HF-Frontend eines linsenbasierten 77-GHz Automobilradarsystems sowie eine Verwendung einer Anordnung (1) für ein HF-Frontend in einem linsenbasierten 77-GHz Automobilradarsystem beschrieben.

Eingebaute Multi-Package-Wellenleiter-Verbindungen

Ausführungsbeispiele können sich auf ein elektronisches Modul zur Verwendung in einer elektronischen Vorrichtung beziehen. Das elektronische Modul kann eine gedruckte Schaltungsplatine (PCB) mit einem ersten Die und einem zweiten Die umfassen. Ein Wellenleiterkanal kann kommunikativ mit dem ersten Die und dem zweiten Die gekoppelt sein und ausgebildet sein zum Übermitteln eines elektromagnetischen Signals von dem ersten Die zu dem zweiten Die. Bei Ausführungsbeispielen kann das elektromagnetische Signal eine Frequenz größer als 30 Gigahertz (GHz) aufweisen. Andere Ausführungsbeispiele können beschrieben oder beansprucht sein.

INTEGRIERTES SCHALTUNGSPACKAGE UND VERFAHREN

In einer Ausführungsform weist eine Struktur Folgendes auf: einen ersten integrierten Schaltungsdie, der erste Die-Anschlüsse aufweist; eine erste Dielektrikumsschicht auf den ersten Die-Anschlüssen; erste leitfähige Durchkontaktierungen, die sich durch die erste Dielektrikumsschicht hindurch erstrecken, wobei die ersten leitfähigen Durchkontaktierungen an eine erste Untergruppe der ersten Die-Anschlüsse angeschlossen sind; einen zweiten integrierten Schaltungsdie, der an eine zweite Untergruppe der ersten Die-Anschlüsse mit ersten aufschmelzbaren Anschlüssen gebondet ist; ein erstes Verkapselungsmaterial, das den zweiten integrierten Schaltungsdie und die ersten leitfähigen Durchkontaktierungen umgibt, wobei das erste Verkapselungsmaterial und der erste integrierte Schaltungsdie seitlich angrenzend sind; zweite leitfähige Durchkontaktierungen benachbart zu dem ersten integrierten Schaltungsdie; ein zweites Verkapselungsmaterial, das die zweiten leitfähigen Durchkontaktierungen, das erste ...

Bondhügellose Aufbauschicht- und Laminatkernhybridstrukturen und Verfahren für ihre Montage

Eine Struktur enthält ein Hybridsubstrat zum Stützen eines Halbleiterbauelements, das eine bondhügellose Aufbauschicht, in die das Halbleiterbauelement eingebettet ist, und eine Laminatkernstruktur enthält. Die bondhügellose Aufbauschicht und die Laminatkernstruktur werden durch eine Verstärkungsplattierung, die mit einem plattierten Durchgangsloch in der Laminatkernstruktur und einer anschließenden Bondinsel der bondhügellosen Aufbauschichtstruktur verbunden ist, zu einer integralen Vorrichtung gemacht.

Mehrchip-Halbleitermodul und Herstellungsverfahren dafür

Ein Mehrchip-Halbleitermodul weist auf: ein Chipmontageteil mit einem ersten und zweiten Substrat, wobei das erste Substrat hat: eine entgegengesetzte erste und zweite Oberfläche, mehrere erste leitende Kontaktlöcher, die sich durch die erste und zweite Oberfläche erstrecken, und eine erste Schaltungsanordnung, die auf der zweiten Oberfläche strukturiert und mit den ersten leitenden Kontaktlöchern elektrisch verbunden ist, wobei das zweite Substrat hat: eine entgegengesetzte erste und zweite Oberfläche, mehrere zweite leitende Kontaktlöcher, die sich durch die erste und zweite Oberfläche des zweiten Substrats erstrecken, eine zweite Schaltungsanordnung, die auf der zweiten Oberfläche des zweiten Substrats strukturiert und mit den zweiten leitenden Kontaktlöchern elektrisch verbunden ist, und eine darin ausgebildete erste Chipaufnahmeöffnung, wobei die erste Oberfläche des zweiten Substrats auf der zweiten Oberfläche des ersten Substrats verbunden ist, so daß die zweite Schaltungsanordnung ...

Integration von Silicium-Photonik-IC für hohe Datenrate

Integrierte Komponentenbaugruppe, die umfasst:eine Leiterplatte (PCB);eine integrierte Photonikschaltung (PIC), die mit der PCB auf einer ersten Seite der PIC mechanisch gekoppelt ist; undeine Treiber-IC mit einer ersten Seite, wobei die erste Seite der Treiber-IC(i) mit einer zweiten Seite der PIC über einen ersten Satz von Höcker-Bondverbindungen direkt mechanisch und elektrisch gekoppelt ist, und(ii) mit der PCB über einen zweiten Satz von Höcker-Bondverbindungen elektrisch gekoppelt ist.

Elektronisches Bauteil mit einem Halbleiterchip und Verfahren zu seiner Herstellung

Modul für elektronische Komponente

Semiconductor module, has semiconductor chip stack arranged on wiring substrate, where heat conducting layer e.g. foil with anisotropic heat conducting particles is arranged between semiconductor chips

The semiconductor module has a semiconductor chip stack (2) arranged on a wiring substrate (3), where a heat conducting layer e.g. a foil (19) with anisotropic heat conducting particles is arranged between semiconductor chips (4,5). The layer has anisotropic heat conducting particles in vertical direction to the layer and/or foil and lower heat conductivity towards the layer and/or the foil. Independent claims are also included for the following: (1) foil for heat dissipation of semiconductor chip stack (2) method for the production of a semiconductor module.

Mehrchipgehäuse und Verfahren zum Bilden von Mehrchipgehäusen für eine ausgeglichene Leistung

Ein Verfahren zum Bilden von Mehrchipgehäusen, mit folgenden Schritten: Positionieren einer ersten integrierten Schaltung (202) in einer mit der Vorderseite nach oben zeigenden Position über einem Substrat (204), das eine erste Substratoberfläche definiert und eine Mehrzahl von Kontaktbereichen (216, 218) aufweist, wobei in der mit der Vorderseite nach oben zeigenden Position eine erste Oberfläche der ersten integrierten Schaltung (202) und die erste Substratoberfläche in einer einander zugewandten Beziehung sind und eine zweite Oberfläche der ersten integrierten Schaltung (202) von dem Substrat (204) abgewandt ist; wobei die erste integrierte Schaltung (202) eine erste Mehrzahl von Anschlussflächen (312) aufweist, die auf der zweiten Oberfläche der ersten integrierten Schaltung (202) angeordnet sind; Positionieren zumindest eines Abschnitts einer zweiten integrierten Schaltung (206) über zumindest einem Abschnitt der ersten integrierten Schaltung (202), so dass die zweite Oberfläche der ...

Verfahren zum Herstellen eines gestapelten Chip-Paketes

Verfahren zum Herstellen eines gestapelten Chip-Paketes, mit den Schritten: Anbringen eines ersten Substrates einschließlich eines ersten zentralen Fensters auf einem ersten Halbleiter-Chip mit einer Vielzahl von auf dem zentralen Teil angeordneten Verbindungsplatten; Bilden einer ersten Verbindungsleitung, die den ersten Halbleiter-Chip und das erste Substrat verbindet; Anbringen eines zweiten ein zweites zentrales Fenster aufweisenden Substrates auf einem zweiten Halbleiter-Chip mit einer Vielzahl von auf dem zentralen Teil angeordneten Verbindungsplatten; Bilden einer zweiten Verbindungsleitung, die den zweiten Halbleiter-Chip und das zweite Substrat verbindet; Zusammenführen der Rückseiten des sich ergebenden ersten und des sich ergebenden zweiten Halbleiter-Chips; Bilden einer dritten Verbindungsleitung, die das erste und das zweite Substrat verbindet; Bilden eines Gusskörpers, welcher die erste, die zweite und die dritte Verbindungsleitung überdeckt; und Anbringen einer leitenden ...

Microwave module comprising substrate with HF and LF layers forming distribution network structures, includes intervening insulating layer

The high frequency structure layer (4) is separated from the low frequency structure layer (3) by the insulating layer (1). An Independent claim is included for the method of manufacture, which especially employs fine pitch flip-chip technology for bonding to the substrate.

Integrated circuit manufacturing method of chip scale package, involves attaching solder balls in area that is uncovered by resist element, of patterned rewriting element, in patterned form

Integrated circuit (14) is mounted upside down on carrier (10), such that connection element (15) contacts with insulator (17), through the hole of carrier. Patterned rewriting elements (18, 19) attached in insulator, are internally connected by patterned solder resist element (20). Solder balls (22) are attached in area that is uncovered by resist element, of rewriting element, in patterned form. An Independent claim is also included for integrated circuit.

Leiterplatte mit primären und sekundären Durchgangslöchern

Leiterplatte mit primären und sekundären Durchgangslöchern

HERSTELLUNG EINES BAUTEILS FÜR EINE HALBLEITERSCHALTUNG

GITTERANORDNUNG UND VERFAHREN ZU DEREN HERSTELLUNG

Anordnung einer Mehrzahl von Schaltungsmodulen

Zur zuverlässigen und gleichwohl einfachen Verschaltung übereinander angeordneter Schaltungsmodule (2) wird bei einer entsprechenden Anordnung (1) vorgeschlagen, eine elektrische Verbindung verschiedener Verbindungseinrichtungen (5) der übereinander angeordneten Schaltungsmodule (2) jeweils durch direkten mechanischen und elektrischen Kontakt zwischen Verbindungselementen (6) verschiedener Verbindungseinrichtungen (5) auszubilden.

Halbleiter-Bauelement und Verfahren

Ein Halbleiter-Bauelement weist Folgendes auf: ein Substrat; eine erste Umverteilungsschicht (RDL) über einer ersten Seite des Substrats; eine oder mehrere Halbleiter-Dies, die über der ersten RDL angeordnet sind und mit dieser elektrisch verbunden sind; und ein Verkapselungsmaterial über der ersten RDL und um den einen oder die mehreren Halbleiter-Dies. Das Halbleiter-Bauelement weist weiterhin Anschlüsse auf, die an einer zweiten Seite des Substrats befestigt sind, die der ersten Seite gegenüberliegt, wobei die Anschlüsse elektrisch mit der ersten RDL verbunden sind. Das Halbleiter-Bauelement weist weiterhin eine Polymerschicht auf der zweiten Seite des Substrats auf, wobei die Anschlüsse von der Polymerschicht her über eine erste Oberfläche der Polymerschicht überstehen, die von dem Substrat entfernt ist. Ein erster Teil der Polymerschicht, der die Anschlüsse kontaktiert, hat eine erste Dicke, und ein zweiter Teil der Polymerschicht zwischen benachbarten Anschlüssen hat eine zweite Dicke ...

Mehrchip-Gehäuse auf Glasbasis

In Ausführungsformen enthält das Mehrchip-Gehäuse auf Glasbasis ein photodefinierbares Substrat auf Glasbasis, mindestens ein elektronisches Bauteil, das auf dem photodefinierbaren Substrat auf Glasbasis angeordnet ist, und einen Teilbereich des photodefinierbaren Substrats auf Glasbasis, der mit ultraviolettem Licht belichtet wurde, wobei der Teilbereich des photodefinierbaren Substrats Keramik enthält. Außerdem kann das Sensorgehäuse zusätzliche elektronische Bauteile, ein gläsernes Touch Panel und/oder eine Leiterplatte enthalten. In Ausführungsformen enthält das Herstellen der Sensorgehäuse-Vorrichtung das Erhalten eines photodefinierbaren Substrats auf Glasbasis, das Ätzen des photodefinierbaren Substrats auf Glasbasis und das Ausbilden eines Keramik-Teilbereichs des photodefinierbaren Substrats auf Glasbasis.

Weichlotverbindung mit hoher Festigkeit

HALBLEITERGEHÄUSE, HALBLEITERVORRICHTUNG, ELEKTRONIKELEMENT UND HERSTELLUNG EINES HALBLEITERGEHÄUSES

PARALLELEBENENSUBSTRAT

Gehäuse eines integrierten Schaltkreises und Verfahren zum Bilden desselben

Eine Ausführungsform einer Gehäuse-auf-Gehäuse(PoP)-Vorrichtung umfasst eine Gehäusestruktur, einen Gehäuseträger und eine Vielzahl von Anschlüssen, die die Gehäusestruktur mit dem Gehäuseträger verbinden. Die Gehäusestruktur umfasst einen Logikchip, der mit einem Speicherchip verbunden ist, eine Formmasse, die den Speicherchip umschließt und eine Vielzahl leitfähiger Stifte, die sich durch die Formmasse hindurch erstrecken. Die Vielzahl der leitfähigen Stifte ist an Kontaktpolstern auf dem Logikchip befestigt.

Semiconductor device e.g. electro-mechanical control device for controlling motor used in vehicle, has first heat-conducting element that is laminated between metal element and second heat conducting elements

The semiconductor device (10a) has a first heat conducting element (5a) arranged between the semiconductor components (1a-1q) and the metallic element (4). Several second heat-conducting elements (6a) are arranged on second surface of semiconductor device. The heat generated by semiconductor component is discharged to metal element. The first heat-conducting element is laminated between metal element and second heat conducting elements, such that the distances (D) between all second heat-conducting elements and metallic element are equal. The second heat-conducting element has thermal conductivity higher than the first heat-conducting element. The printed circuit board (2a) is made of insulating resin material, and predetermined wiring pattern is composed of copper foil. An independent claim is included for method for manufacturing semiconductor device.

ABSCHIRMLÖSUNGEN FÜR DIRECT-CHIP-ATTACHKONNEKTIVITÄTSMODULPACKUNGSSTRUKTUREN

Es werden Verfahren zum Ausbilden von Packungsstrukturen und Strukturen, die dadurch ausgebildet werden, beschrieben. Diese Verfahren/Strukturen können eine Abschirmstruktur aufweisen, die auf einer Oberfläche einer Packungsstruktur angeordnet ist, wobei die Abschirmstruktur eine Folie, ein leitfähiges Material, das auf einer Oberfläche der Folie angeordnet ist, und mehrere leitfähige Stäbe aufweist, wobei jeder individuelle leitfähige Stab der mehreren leitfähigen Stäbe durch die Folie angeordnet ist und zumindest ein Anteil der mehreren leitfähigen Stäbe physikalisch mit Erdungsbahnen verkoppelt ist, die auf der Oberfläche der Packungsstruktur angeordnet sind.

Mikroelektronikgehäuse, das eine erhöhte Speicherkomponentendichte bereitstellt

Hier beschriebene Beispiele umfassen eine Mikroelektronikgehäuseanordnung eines Solid-State-Laufwerks, die ein Substrat und eine Vielzahl von Mikroelektronikkomponenten umfasst, die an das Substrat angeschlossen sind. Die Vielzahl von Mikroelektronikkomponenten kann durch eine Komponentenlücke durchgängig voneinander getrennt sein. Das Mikroelektronikgehäuse kann außerdem ein Die-Bauelement umfassen, das an das Substrat angeschlossen ist, wobei sich das Die-Bauelement über die Komponentenlücke erstreckt und vertikal zwischen der Vielzahl von Mikroelektronikkomponenten und dem Substrat angeordnet ist. Bei einigen Beispielen sind die Mikroelektronikkomponenten und das Die-Bauelement jeweils mithilfe einer Vielzahl von Verbindungskomponenten (z.B. einer Lötkugelmatrix) an das Substrat angeschlossen. Die Vielzahl von Verbindungskomponenten kann auf den Mikroelektronikkomponenten so angeordnet sein, dass sie einen oder mehrere offene Bereiche definieren, die frei von Verbindungskomponenten sind ...

Electronic component with semiconductor chip, has substrate attached via adhesive layer on to active chip surface

An electronic component with contact surfaces (3) in the region of a bond channel (5) or in bond surfaces in bonding pads and with a substrate (6) glued via an adhesive layer (14) on to the active chip surface, for wiring of the contact connection surfaces, and conductor paths (8), solder contact surfaces (9) and a solder stop layer (12), in which the substrate is provided with expansion joints (15) An Independent claim is given for a method of manufacturing an electronic component.

Stack arrangement for FBGA memory module, has encapsulation at central region of each memory chip, constituting spacer between chips, and metallization connected to carrier substrate

A metallization (4) is arranged on an active side of each memory chip, and connected to the bond pad (3) of the memory hip. The metallizations of each individual component (1) is identical. The central regions of each memory chip are provided with an encapsulation (7) which is stacked on the carrier substrate with the same alignment to each other. The encapsulation constitutes a spacer between the chips. Each metallization is connected electrically to the carrier substrate.

Semiconductor system comprises substrate with contact pad connected to e.g. solder beads, system being encapsulated on at least five sides and mechanical decoupling system mounted between encapsulation and semiconductor

Semiconductor system comprises a substrate (10) with a contact pad (11) which is connected by conductors (12) to connectors, e.g. solder beads (13). The system is encapsulated (14) on at least five sides and a mechanical decoupling system (15) is mounted between the encapsulation and the semiconductor. An independent claim is included for a method for making the semiconductor system.

ELECTRONISCHE EINRICHTUNG, INFORMATIONSPROZESSOR UND ANORDNUNG ZUM UNTERDRÜCKEN VON ELEKTROMAGNETISCHEN STÖRUNGEN

Verfahren zur Herstellung eines Halbleiterbauteils mit Durchkontakten zwischen Oberseite und Rückseite

Die Erfindung betrifft ein Verfahren zur Herstellung eines Halbleiterbauteils (1) mit Durchkontakten (2) zwischen Oberseite (3) und Unterseite (4), wobei die Durchkontakte (2) in mindestens einem Randbereich (5) des Halbleiterbauteils (1) angeordnet sind. Die Durchkontakte (2) verbinden elektrisch miteinander Außenkontaktflächen (7, 8) des Halbleiterbauteils (1) auf der Oberseite (3) und Unterseite (4). Eine Kunststoffgehäusemasse (10) umgibt mindestens einen Halbleiterchip (9) mit Kontaktflächen (11) auf der aktiven Oberseite (12) des Halbleiterchips (9). Die Kontaktflächen (11) stehen mit den Durchkontakten (2) über eine Verdrahtungsstruktur (14) elektrisch in Verbindung, wobei die Durchkontakte (2) in mindestens einer vorgefertigten Durchkontaktleiste (15) angeordnet sind, die in dem Randbereich (5) des Halbleiterbauteils (1) positioniert ist.

Halbleiterpackung und Herstellungsverfahren hierfür

Die Erfindung bezieht sich auf eine Halbleiterpackung und ein Verfahren zur Herstellung einer solchen. DOLLAR A Erfindungsgemäß beinhaltet die Halbleiterpackung einen Halbleiterchip (100) mit je einem integrierten Schaltungsaufbau auf beiden Seiten (A, B), ein Substrat (110), erste und zweite Bonddrähte (130, 132), ein erstes und zweites Abdichtungsmaterial (140, 142) und eine Mehrzahl von Lotkugeln (150). DOLLAR A Verwendung in der Halbleiterpackungstechnologie.

Semiconductor device has copper-tin alloy layer formed on junction portion of solder ball consisting of tin, and wiring consisting of copper

A copper-tin alloy layer (21) of about 1.87 micron thickness, is formed on the junction portion of tin solder ball (11) and copper wiring (2). The rate of content of tin and lead in solder ball is 63% and 37%, respectively. The wiring is connected to the semiconductor chip. The distributed density per lead lump unit cross section of 3 or more in solder ball, is 20\*10<4> pieces/mm. An Independent claim is also included for manufacturing method of semiconductor device.

Laminierter Kondensator und Montageanordnung

Laminierter Kondensator mit folgenden Merkmalen: einem Kondensatorkörper (43) mit einem laminierten Stapel einer Mehrzahl von dielektrischen Schichten (42); zumindest einem Paar einer ersten und einer zweiten inneren Elektrode (44, 45), die sich gegenüberliegen, wobei zumindest eine der dielektrischen Schichten (42) zwischen denselben angeordnet ist, in dem Kondensatorkörper (43); einer Mehrzahl von ersten Durchführungsleitern (46), die zumindest eine der dielektrischen Schichten (42) durchdringen und die innerhalb des Kondensatorkörpers (43) vorgesehen sind, wobei die ersten Durchführungsleiter (46) von den zweiten inneren Elektroden (45) elektrisch isoliert und mit den ersten inneren Elektroden (44) elektrisch verbunden sind, und einer Mehrzahl von zweiten Durchführungsleitern (47), die den Kondensatorkörper (43) durchdringen und innerhalb des Kondensatorkörpers (43) vorgesehen sind, wobei die zweiten Durchführungsleiter (47) von den ersten inneren Elektroden (44) elektrisch isoliert ...

Transpondersystem und Verfahren zur Entfernungsmessung

Die Erfindung bezieht sich auf ein Entfernungs-Bestimmungssystem zum Bestimmen der Entfernung zwischen einer Basisstation (BS) und einem Transponder (TR), wobei die Basisstation (BS) eine oszillierende Signalquelle (OSZ¶B¶) zum Erzeugen eines Signals (S¶tx¶(t)) und eine Sendeeinrichtung (ANT¶B¶) zum Aussenden des Signals (S¶tx¶(t)) aufweist, der Transponder (TR) eine Empfangseinrichtung (ANT¶T¶) zum Empfangen des Signals (e¶rxt¶(t)) von der Basisstation (BS), einen Oszillator (OSZ¶T¶) zum Erzeugen eines dazu phasenkohärenten Signals (S¶OSZ¶(t)) und eine Sendeeinrichtung (ANT¶T¶) zum Aussenden des phasenkohärenten Signals (S¶OSZ¶(t)) aufweist und die Basisstation (BS) außerdem eine Empfangseinrichtung (ANT¶B¶) zum Empfang des phasenkohärenten Signals (S¶OSZ¶(t)) von dem Transponder (TR) und eine Entfernungs-Bestimmungseinrichtung (RXMIX, FLT, DEMOD) zum Bestimmen der Entfernung (dist) zwischen Basisstation (BS) und Transponder (TR) aufweist. DOLLAR A Zur Verbesserung des Systems und der ...

Multilayer circuit module for wireless communication system has passive high frequency components and passive base component layer

A connection integration region includes at least one connecting layer (404,408) for electrically coupling the circuit components (409). A passive base component integration region has a passive base component layer (405,407). A passive high frequency component integration region comprises passive high frequency components. An Independent claim is included for a method of manufacturing a multilayer circuit module.

Verfahren zum Herstellen eines Halbleiterbauelements

Es wird ein Verfahren zum Herstellen eines Halbleiterbauelements (100) offenbart. Eine Ausführungsform stellt einen Träger (10) bereit. Halbleiterchips (11, 12) werden über dem Träger (10) platziert. Die Halbleiterchips (11, 12) enthalten Kontaktelemente (13). Ein Polymermaterial (15) wird über den Halbleiterchips (11, 12) und dem Träger (10) aufgebracht. Das Polymermaterial (15) wird entfernt, bis die Kontaktelemente (13) exponiert sind. Der Träger (10) wird von den Halbleiterchips (11, 12) entfernt.

Storage container

Carrier for multilayer semiconductor device and process for manufacturing multilayer semiconductor device

A method of manufacturing an integrated circuit package and an integrated circuit package

A method of manufacturing an integrated circuit package

Microwave circuit package

Method of manufacture of an integrated circuit package

CARRIER SUBSTRATE AND METHOD FOR PREPARING THE SAME

Microelectronic package and method of manufacturing same

"CARRIER SUBSTRATE FOR ELECTRICAL CIRCUIT ELEMENT "

PURPOSE:To form a thin film circuit element having required accuracy without necessitating trimming by providing an electrode layer for connection to the circuit element on the topmost layer of insulating films, providing an element layer having the thin film circuit on any of other insulating films, and providing conductor wirings for connecting the electrode layer and external connecting terminals through the element layer. CONSTITUTION:Insulating layers 9a, 9b and 9c are formed on an insulating board. A thin film circuit element such as a thin film resistor is formed thereon. Therefore, irregularities, warping and the like on the surface of the insulating board, e.g. a ceramic substrate 6 are absorbed with the insulating films. The thin film circuit element is formed without the effects of the roughness of the surface of the insulating board. Therefore, the circuit element having the desired constants can be formed accurately. As a result, correction such as trimming is not required.

Integrated circuit packaging for improving effective chip-bonding area

Stacked package structure of an image sensor having a substrate with a cavity stacked on another substrate

A stacked package structure of an image sensor for electrically connecting to a printed circuit board (20) includes first substrate (10) having a first surface (12) with signal input terminals (16), and a second surface (14) formed with signal output terminals (18) for electrical connection to the printed circuit board (20). A second substrate (22) adhered to the first surface (12) of the first substrate (10) has a cavity (28) containing an integrated circuit (30). The integrated circuit (30) is mounted on the first surface (12) of the substrate (10) and is connected to the signal input terminals (16). An image sensing chip (34) is located on the upper surface (24) of the second substrate (22) and is also connected to the signal input terminals (16). A transparent layer (40) is arranged above the image sensing chip (34) enabling the image sensing chip (34) to receive image signals through the layer (40).

Hermetically sealed wafer level packaging for optical MEMS devices

Optical MEMS chips 315 are assembled on a CMOS semiconductor wafer substrate 310 comprising integrated circuits 312 and interconnects 314. A transparent cover 337 having standoff portions 324 is mounted on the semiconductor wafer and seals the individual chips. The assembly can then be subdivided into individual device packages (see figure 3D).

Semiconductor device and production method

Ball grid array package

IC device with a metal thermal conductive layer having an opening for evacuating air

An IC device comprises an interconnection substrate 50 having at least one conductive layer 70 and at least one insulating layer 32, a first metal thermal conductive layer 70 and a second metal thermal conductive layer 83 having a surface exposed to an exterior. This second layer 83 has an opening 84 formed at a central portion, and a hole region 36 is formed within the interconnection substrate 50 and the first metal thermal conductive layer 70. An IC chip 40 is positioned with a first surface disposed at a central portion of the hole region 36. A second surface of the IC chip 40 has a plurality of bond pads 41. The chip 40 has a width larger than the diameter of the opening 84 in the second thermal conductive later 83 and is in contact with the second thermal conductive layer 83. A plurality of bond wires 9 electrically connect the bond pads 41 on the IC chip 40 with the first conductive trace layer 70, and an encapsulation material 42 fills the hole region 36 and encloses the bond wires ...

Circuit element

In a circuit element 300 having a heat-conducting body 301 having top and bottom surfaces, and a die having an electronic circuit thereon, the die includes first and second contact points for powering the electronic circuit. The die is in thermal contact with the heat-conducting body, the die having a bottom surface that is smaller than the top surface of the heat-conducting body. The first contact point on the die is connected to a first trace 308 bonded to the top surface of the heat-conducting body. An encapsulating cap 326 covers the die. The first trace has a first portion that extends outside of the encapsulating cap and a second portion that is covered by the encapsulating cap. The heat-conducting body is preferably constructed from copper or aluminum and includes a cavity having an opening on the first surface in which the die is mounted. The die preferably includes a light-emitting device 314.

Shielded semiconductor package

A Plastic Ball Grid Array package of the Cavity Down type comprises a Faraday Cage to protect the semiconductor chip from external HF wave interferences. The lateral sides of the Faraday Cage are constituted by a row of solder balls 303 connected in a zig-zag way to plated through holes 301 along the four edges of a plastics substrate on which the chip is mounted. The top side of the Cage is the metal plate of the Cavity Down package electrically connected to the through holes, while the bottom side is formed by the ground plane of the main board connected to the solder balls.

Hermetically sealed wafer level packaging for optical MEMS devices

Optical MEMS chips 315 are assembled on a CMOS semiconductor wafer substrate 310 comprising integrated circuits 312 and interconnects 314. A transparent cover 337 having standoff portions 324 is mounted on the semiconductor wafer and seals the individual chips. The assembly can then be subdivided into individual device packages. An optical stop or spatial filter 825 may be arranged on the transparent cover (figure 8).

Carrier for multilayer semiconductor device and process for manufacturing multilayer semiconductor device

A carrier for a multilayer semiconductor device comprising a lower stage carrier (3) having a first containing section (12) for containing a first semiconductor device (110) to be the lower side device, and an upper stage carrier (2) having a second containing section (14) for containing a second semiconductor device (120) to be stacked on the first semiconductor device (110) and arranging the second semiconductor device (120) at a specified position on the first semiconductor device (110). By having such a structure, no dedicated stacking device is required, and thus cost can be reduced.

Memory device indentification.

Flip chip package incorporating metallurgical bond to enhance thermal conduction

An integrated circuit device 10 incorporating a metallurgical bond to enhance thermal conduction to a heat sink 28. In a semiconductor device, a surface of an integrated circuit die 14 is metallurgically bonded to a surface of a heat sink 28. In an exemplary method of. manufacturing the device, the upper surface of a package substrate 12 includes an inner region and a peripheral region. The integrated circuit die 14 is positioned over the substrate surface and a active surface 16 of the integrated circuit die 14 is placed in contact with the package substrate 12. A metallic layer 30 is formed on a second opposing surface 18 of the integrated circuit die 14. A preform is positioned on the metallic layer and a heat sink 28 is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink 28 to the second surface 18 of the integrated circuit die 14.

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

Reconstituted device including die and functional material

Dies from a wafer are reassembled with passive components and encapsulated to form a reconstituted electronic device 10 comprising a die 11, a passive, functioning component 13 and a metallic redistribution layer 15 which defines an electronic component in an area at least partially above the functioning material. The electronic component may be a metal-oxide-metal capacitor, an inductor or an antenna. The functioning material may be ceramic or it may be a ferrite. The functioning material may surround the die. In one embodiment the functioning material is a ceramic body with a metallic coating 110 (figure 10) on a face opposite that of the surface of the substrate on which the die and functioning material are embedded, a metallic via 102 (figure 9) is included through the ceramic body to contact the metal coating, the redistribution layer/ceramic body/metal coating structure forms a capacitor. In another embodiment the functioning material may be a metal carrier 120 (figure 11) with an ...

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

Semiconductor devices

Method for the extrction of known ball grid array substate rejects

Memory device indenification

Method for interconnecting stacked semiconductor devices

Devices and methods related to radio-frequency filters on silicon-on-insulator substrate

Package structures including discrete antennas assembled on a device

Improved qfn package

Solder connect assembly and method of connecting a semiconductor package and a printed wiring board

Plastic ball grid array module

HEATCONDUCTIVE GREASE AND PROCEDURE AND DEVICES, WITH WHICH THE GREASE IS USED

ADHESIVE, ADHESIVE ARTICLE, CIRCUIT SUBSTRATE FOR SEMICONDUCTOR ASSEMBLY WITH AN ADHESIVE AND A SEMICONDUCTOR ARRANGEMENT THESE CONTAINS

FLIP CHIP ASSEMBLAGE PROTECTING OF MICRO MECHANISM PARTS

FLEXIBLE CONFORMAL ANTENNA

ELECTRONIC PACKING WITH EMBEDDED CONDENSER AND THEIR MANUFACTURING PROCESSES

ELECTRONIC BUILDING GROUP WITH COMPOUND ELECTRONIC CONTACTS FOR THE MOUNTING OF A PACKAGING SUBSTRATE AT A PRINTED CIRCUIT BOARD

AMIDE-SUBSTITUTED SILIKONE AND PROCEDURE FOR YOUR PRODUCTION AND USE

MANUFACTURING PROCESS FOR A MATRIXFÖRMIGEN RADIATION DETECTOR AS WELL AS PROCEDURE FOR THE CHANGE OF INDIVIDUAL DETECTION MODULES IN THIS MATRIX

BALL MATRIX HOUSING WITH HEAT DISTRIBUTOR AND ITS PRODUCTION

EMBEDDED SUPPORT DISKS FOR RELIABLE PILE PATHS IN ELECTRONIC SUBSTRATES

PROCEDURE FOR THE PRODUCTION OF CONDUCTIVE FOILS AS WELL AS IN THIS PROCEDURE MANUFACTURED ARTICLES

Double molded chip scale package

Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure. With such a configuration, the second molding layer helps control warpage during the manufacturing process and no printed circuit board (PCB) substrate is needed when the package is used in an electronic device since the signal routing is performed by the second interconnect structure. Other embodiments are described.

Semiconductor package having a stacked structure

A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.

Wiring board and method for manufacturing the same

A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

System-in-a-package based flash memory card

A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.

Methods of forming semiconductor chip underfill anchors

Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.

Method of forming a packaged semiconductor device

A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.

Semiconductor device comprising a passive component of capacitors and process for fabrication

A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block.

Semiconductor device and semiconductor package including the same

Provided is a semiconductor device capable of removing a power ground grid noise using a small area. The semiconductor device includes a first chip including at least one decoupling capacitor; and a second semiconductor chip stacked over the first semiconductor chip, including internal circuits.

Semiconductor device

A semiconductor device which includes a substrate, a semiconductor element arranged on the substrate, a heat dissipation component arranged on the semiconductor element, and a mold component covering an upper part of the substrate, the semiconductor element and the heat dissipation component, wherein an area of a surface on the semiconductor element of the heat dissipation component is larger than an area of a surface on which the heat dissipation component of the semiconductor element is arranged.

Image engine with integrated circuit structure for indicia reading terminal

Embodiments of the present invention comprise an image engine constructed as an IC structure that has one or more active regions for illuminating, imaging, and decoding a decodable indicia. In one embodiment of the image engine, the IC structure can comprise an imaging region, an aiming region, and an illumination region, all disposed on a single, contiguous substrate. The resultant constructed embodiment can fit within a form factor, wherein the form factor is less than about 500 mm 3 .

Method for fabrication of a semiconductor device and structure

A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

Semiconductor device and method of manufacturing the same

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

Circuit substrate and manufacturing method thereof and package structure and manufacturing method thereof

A circuit substrate includes the following elements. A conductive layer and a dielectric layer are disposed on an inner circuit structure in sequence, and a plurality of conductive blind vias are embedded in the dielectric layer and connected to a portion of the conductive layer. A plating seed layer is disposed between each of the first blind vias and the first conductive layer. Another conductive layer is disposed on the dielectric layer, wherein a portion of the another conductive layer is electrically connected to the conductive layer through the conductive blind vias. A third plating seed layer is disposed between the third conductive layer and each of the first blind vias and on the first dielectric layer.

Systems and Methods for Heat Dissipation Using Thermal Conduits

The addition of thermal conduits by bonding bond wires to bond pads either in a wire loop configuration or a pillar configuration can improve thermal dissipation of a fabricated die. The thermal conduits can be added as part of the normal packaging process of a semiconductor die and are electrically decoupled from the circuitry fabricated on the fabricated die. In an alternative, a dummy die is affixed to the fabricated die and the thermal conduits are affixed to the dummy die. Additionally, thermal conduits can be used in conjunction with a heat spreader.

Semiconductor Device and Power Supply Unit Utilizing the Same

A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.

Energy Conditioning Circuit Arrangement for Integrated Circuit

The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.

Composite Electronic Circuit Assembly

A composite electronic circuit assembly comprises two MOS or CMOS circuit dice ( 100, 200 ) superimposed inside a package. Different modules of the circuit assembly are distributed between the two dice based on the digital, analog, or hybrid nature of said modules. Such a distribution makes it possible to group together the digital modules of the circuit assembly in one of the die and the analog or hybrid modules in the other die. The production cost, development time, and electrical energy consumption of the circuit assembly may thus be reduced.

Memory systems and memory modules

One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

Image Sensor Package with Dual Substrates and the Method of the Same

The image sensor package with dual substrates comprises a first substrate with a die receiving opening and a plurality of first through hole penetrated through the first substrate; a second substrate with a die opening window and a plurality of second through hole penetrated through the second substrate, formed on the first substrate. A part of the second wiring pattern is coupled to a part of the third wiring pattern; an image die having conductive pads and sensing array received within the die receiving opening and the sensing array being exposed by the die opening window; and a through hole conductive material refilled into the plurality of second through hole, some of the plurality of second through hole coupling to the conductive pads of the image sensor.

Authentication device, authentication method, and an information storage medium storing a program

There is provided an authentication device including an authentication information storage unit that stores authentication information acquired from an authentication pattern including a part or the entirety of a mottled pattern or a dot pattern formed over an electronic component as information for indentifying each of a plurality of electronic components, an authentication information acquiring unit that acquires a first authentication information acquired from the authentication pattern formed over a first electronic component that is an object to be authenticated, a search unit that searches whether or not the authentication information storage unit stores the first authentication information by using the first authentication information as a search key, and an output unit that outputs a search result of the search unit.

Semiconductor structure having conductive vias and method for manufacturing the same

A semiconductor structure includes a plurality of thermal vias and a heat dissipation layer disposed at a periphery of a back surface of a lower chip in a stacked-chip package. This arrangement improves solderability of a subsequently-bonded heat sink. Additionally, the thermal vias and the heat dissipation layer provide an improved thermal conduction path for enhancing heat dissipation efficiency of the semiconductor structure. A method for manufacturing the semiconductor structure is also provided.

Bumpless build-up layer package with pre-stacked microelectronic devices

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

Electronic component mounting method and electronic component mount structure

A challenge to be met by the present invention is to provide an electronic component mounting method and an electronic component mount structure that make it possible to assure bonding strength for an electronic component whose underside is provided with bumps. In electronic component mounting operation during which an electronic component ( 6 ) whose underside is provided with bumps ( 7 ) with solder is mounted on a substrate ( 1 ), a solder bonding material ( 3 ) including solder particles contained in a first thermosetting resin is used for bonding the bumps ( 7 ) to an electrode ( 2 ) formed on the substrate ( 1 ), thereby forming a solder bonding area ( 7 *) where the solder particles and the bumps ( 7 ) are fused and solidified and a first resin reinforcement area ( 3 a *) that reinforces the solder bonding area ( 7 *). Further, an adhesive ( 4 ) containing as a principal component a second thermosetting resin not including solder particles is used for fixing an outer edge ( 6 a ) of the electronic component ( 6 ) to reinforcement points set on the substrate ( 1 ). Even when the solder bonding material ( 3 ) and the bonding agent ( 4 ) are blended together, normal thermal curing of the thermosetting resin is not hindered. Bonding strength can thereby be assured for the electronic component ( 6 ) whose underside is provided with the bumps ( 7 ).

Multi-chip package with offset die stacking

A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed.

Semiconductor device and manufacturing method of the same

A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.

Semiconductor chip device with polymeric filler trench

A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Semiconductor package integrated with conformal shield and antenna

A semiconductor package integrated with conformal shield and antenna is provided. The semiconductor package includes a semiconductor element, an electromagnetic interference shielding element, a dielectric structure, an antenna element and an antenna signal feeding element. The electromagnetic interference shielding element includes an electromagnetic interference shielding film and a grounding element, wherein the electromagnetic interference shielding film covers the semiconductor element and the grounding element is electrically connected to the electromagnetic interference shielding layer and a grounding segment of the semiconductor element. The dielectric structure covers a part of the electromagnetic interference shielding element and has an upper surface. The antenna element is formed adjacent to the upper surface of the dielectric structure. The antenna signal feeding element passing through the dielectric structure electrically connects the antenna element and the semiconductor element.

Method of manufacture of integrated circuit packaging system with stacked integrated circuit

A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.

Semiconductor device including coupling conductive pattern

A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.

Massively Parallel Interconnect Fabric for Complex Semiconductor Devices

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate.

Integrated circuit packaging system with active surface heat removal and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.

Semiconductor device having semiconductor member and mounting member

A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased.

Multilayer printed wiring board and method for manufacturing multilayer printed wiring board

A method for manufacturing a multilayer printed wiring board includes preparing a first resin insulative material having a first conductive circuit on or in the first resin insulative material, forming a second resin insulative material on the first resin insulative material and the first conductive circuit, forming on a surface of the second resin insulative material a first concave portion to be filled with a conductive material for formation of a second conductive circuit, forming on the surface of the second resin insulative material a pattern having a second concave portion and post portions to be filled with the conductive material for formation of a plane conductor, and filling the conductive material in the first concave portion and the second concave portion such that the second conductive circuit and the plane conductor are formed.

Semiconductor package with through electrodes and method for manufacturing the same

A semiconductor package may include a substrate with a first surface over which bond fingers are formed. At least two semiconductor chips may be stacked on the first surface of the substrate and each chip may have via holes. The semiconductor chips may be stacked such that the respective via holes expose the respective bond fingers of the substrate. Through electrodes may be formed in the via holes. The through electrodes may comprise carbon nanotubes grown from the exposed bond fingers of the substrate, where the through electrodes may be electrically connected with the semiconductor chips.

Methods of fabricating package stack structure and method of mounting package stack structure on system board

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

Integrated circuit packaging system with warpage control and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier.

Flexible underfill compositions for enhanced reliability

Underfill materials for fabricating electronic devices are described. One embodiment includes an underfill composition including an epoxy mixture, an amine hardener component, and a filler. The epoxy mixture may include a first epoxy comprising a bisphenol epoxy, a second epoxy comprising a multifunctional epoxy, and a third epoxy comprising an aliphatic epoxy, the aliphatic epoxy comprising a silicone epoxy. The first, second, and third epoxies each have a different chemical structure. Other embodiments are described and claimed.

Integrated circuit packaging system with a shield and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a first integrated circuit over the substrate; forming an encapsulant around the first integrated circuit and over the substrate; and forming a shield structure within and over the encapsulant while simultaneously forming a vertical interconnect structure.

Circuit board including embedded decoupling capacitor and semiconductor package thereof

A circuit board including an embedded decoupling capacitor and a semiconductor package thereof are provided. The circuit board may include a core layer including an embedded decoupling capacitor, a first build-up layer at one side of the core layer, and a second build-up layer at the other side of the core layer, wherein the embedded decoupling capacitor includes a first electrode and a second electrode, the first build-up layer includes a first via contacting the first electrode, and the second build-up layer includes a second via contacting the first electrode.

Off-chip vias in stacked chips

A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.

Chip Capacitor Precursors

A capacitive precursor includes electrically conductive material layers stacked on a substrate. The electrically conductive layers provide first and second patterns. The patterns each include overlaying areas free of the electrically conductive material. The first pair of areas overlay areas of the second pattern having the electrically conductive material and the second pair of areas overlay areas of the first pattern having the electrically conductive material. Dielectric layers are interposed between neighboring electrically conductive material layers for electrical isolation. One or more capacitive precursors can be dropped onto or into a board and during assembly of a packaged semiconductor device and have electrically conducting layers associated with its respective plates connected together to form a capacitor during assembly using conventional assembly steps.

Semiconductor device and test system for the semiconductor device

A semiconductor package including a stress mitigation unit that mitigates stress to the semiconductor chip. The semiconductor package includes a substrate, a semiconductor chip on the substrate, an encapsulation member formed on the substrate and covering the first semiconductor chip, and the stress mitigation unit mitigating stress from a circumference of the first semiconductor chip to the first semiconductor chip. The stress mitigation unit includes at least one groove formed in the encapsulation member.

Integrated circuit packaging system with interposer interconnections and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure; mounting a first-external-package-component to the routing structure; and forming a first-external-package-encapsulation covering the first-external-package-component.

Package with embedded chip and method of fabricating the same

A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified.

Semiconductor assembly and semiconductor package including a solder channel

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Integrated circuit tampering protection and reverse engineering prevention coatings and methods

A method of protecting an electronics package is discussed along with devices formed by the method. The method involves providing at least one electronic component that requires protecting from tampering and/or reverse engineering. Further, the method includes mixing into a liquid glass material at least one of high durability micro-particles or high-durability nano-particles, to form a coating material. Further still, the method includes depositing the coating material onto the electronic component and curing the coating material deposited.

Semiconductor package

A semiconductor package includes a memory controller chip, a plurality of first memory chips configured to store normal data, a second memory chip configured to store error information for correcting or detecting error of the normal data, and an interface unit configured to interface the memory controller chip, the plurality of first memory chips, and the second memory chip.

Chip package and manufacturing method thereof

A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure.

Thermosetting resin composition for sealing packing of semiconductor, and semiconductor device

A thermosetting resin composition for an underfilling of a semiconductor comprising, as essential components, a thermosetting resin, a curing agent, a flux agent and two or more inorganic fillers with different mean particle sizes, wherein the inorganic fillers include an inorganic filler with a mean particle size of no greater than 100 nm and an inorganic filler with a mean particle size of greater than 100 nm.

Memory module with memory stack and interface with enhanced capabilities

A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.

Semiconductor package device with a heat dissipation structure and the packaging method thereof

The present invention provide a heat dissipation structure on the active surface of the die to increase the performance of the heat conduction in longitude direction of the semiconductor package device, so that the heat dissipating performance can be improved when the semiconductor package device is associated with the exterior heat dissipation mechanism.

Semiconductor module having a semiconductor chip stack and method

A semiconductor module having a semiconductor chip stack and a method for producing the same is disclosed. In one embodiment, a thermally conductive layer with anisotropically thermally conductive particles is arranged between the semiconductor chips. The anisotropically thermally conductive particles have a lower thermal conductivity in a direction vertically with respect to the layer or the film than in a direction of the layer or the film.

Semiconductor module

A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.

Methods of manufacturing semiconductor chips

A method of manufacturing semiconductor chips includes providing a semiconductor substrate including circuit regions, irradiating the semiconductor substrate with a laser beam onto to form a frangible layer, and polishing the semiconductor substrate to separate the circuit regions of the semiconductor substrate from one another into semiconductor chips. The frangible layer may be removed completely during the polishing of the semiconductor substrate.

Semiconductor Device And Method Of Manufacturing Semiconductor Device

A semiconductor chip includes a magnetic storage device and includes an electrode pad on a first face. The semiconductor chip is coated with a magnetic shield layer in a state in which at least the electrode pad is exposed. The semiconductor chip is mounted on an interconnect substrate through a bump. At least one of the semiconductor chip and the interconnect substrate includes a convex portion, and the bump is disposed over the convex portion.

Microelectronic devices and methods for manufacturing microelectronic devices

Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. One such method includes forming a plurality of apertures in a substrate with the apertures arranged in an array, and, after forming the apertures, attaching the substrate to a lead frame having a plurality of pads with the apertures in the substrate aligned with corresponding pads in the lead frame. Another method includes providing a partially cured substrate, coupling the partially cured substrate to a plurality of leads, attaching a microelectronic die to the leads, and electrically connecting the microelectronic die to the leads.

Integrated circuit packaging system with connection structure and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.

Semiconductor package and semiconductor system including the same

Provided are a semiconductor package and a semiconductor system including the semiconductor package. The semiconductor package includes a semiconductor device and an interconnect structure electrically connected to the semiconductor device and delivering a signal from the semiconductor device, wherein the interconnect structure includes an anodized insulation region and an interconnect adjacent to and defined by the anodized insulation region.

System and method for multi-application socket

A processor module socket accommodates processor modules of different sizes with adapters that align smaller-sized modules so that module pins align with desired contact points. The largest supported processor module engages with the socket in a conventional manner without the use of an adapter. Smaller processor modules engage within an adapter that in turn engages in the socket in a manner similar to the largest supported processor module. The contact points of the socket support different sized processor modules by keying logical functions based upon the type of processor module installed in the socket.

3d optoelectronic packaging

An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with a wiring layer. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. One or more first OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the first OE elements positioned in optical alignment with the optical via for receiving the light. A second OE element embedded within the wiring layer. A carrier may be interposed between electrical interconnect elements and positioned between the wiring layer and a circuit board.

Multilayered printed circuit board and manufacturing method thereof

An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22 , the thickness of which is reduced (to 3 μm) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20 a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be prevented. Thus, the reliability of the connection of the via holes can be improved.

Semiconductor device and method of forming the same

A semiconductor device includes a wiring board; a stack of semiconductor chips disposed over the wiring board, each of the semiconductor chip comprising via electrodes, the semiconductor chips being electrically coupled through the via electrodes to each other, the semiconductor chips being electrically coupled through the via electrodes to the wiring board; a first seal that seals the stack of semiconductor chips; and a second seal that covers the first seal. The first seal is smaller in elastic modulus than the second seal.

System comprising a semiconductor device and structure

A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

Wafer mold material and method for manufacturing semiconductor apparatus

The invention provides a wafer mold material for collectively subjecting a wafer having semiconductor devices on a surface thereof to resin molding, wherein the wafer mold material has a resin layer containing a filler and at least any one of an acrylic resin, a silicone resin having an epoxy group, an urethane resin, and a polyimide silicone resin, and the wafer mold material is formed into a film-like shape. There can be a wafer mold material that enables collective molding (wafer molding) with respect to a wafer having semiconductor devices formed thereon, has excellent transference performance with respect to a large-diameter thin-film wafer, can provide a flexible hardened material with low-stress properties, and can be preferably used as a mold material in a wafer level package with less warp of a formed (molded) wafer.

Printed circuit board

A power source terminal and a ground terminal for a semiconductor integrated circuit are connected to a conductor pattern through a capacitor. The conductor pattern is connected, through a filter, to a plane conductor connected to neither a ground plane nor a power source plane. Thus, a common mode noise arising from between the power source and the ground is caused to flow into the plane conductor. This reduces the common mode noise flowing in the ground and the power source of the printed wiring board, which relatively act as antennas.

Integrated millimeter wave transceiver

A millimeter wave transceiver including a plate forming an interposer having its upper surface supporting an interconnection network and having its lower surface intended to be assembled on a printed circuit board by bumps; an integrated circuit chip assembled on the upper surface of the interposer; antennas made of tracks formed on the upper surface of the interposer; and reflectors on the upper surface of the printed circuit board in front of each of the antennas, the effective distance between each antenna and the reflector plate being on the order of one quarter of the wavelength, taking into account the dielectric constants of the interposed materials.

Semiconductor package and method of manufacturing the same

Provided are a semiconductor package and a method of manufacturing the same. a substrate including a first face and a second face, wherein the first and second faces face each other; a first ground pattern disposed on the first face; a second ground pattern disposed on the second face; a plurality of ground via plugs which connect the first ground pattern and the second ground pattern, wherein the plurality of ground via plugs penetrate the substrate; and a first aluminum oxide film interposed between the plurality of ground via plugs, wherein a ground voltage is applied to the plurality of ground via plugs. The semiconductor package may be manufactured using an anodic oxidation process.

Method of post-mold grinding a semiconductor package

A method of grinding a molded semiconductor package to a desired ultra thin thickness without damage to the package is disclosed. Prior to grinding a molded package to a desired package thickness, the package may be protected from excessive mechanical stress generated during grinding by applying a protective tape to enclose interconnects formed on the package. This way, the protective tape provides support to the semiconductor package during package grinding involving the mold material as well as the die. In the post-grind package, the grinded die surface may be exposed and substantially flush with the mold material. The protective tape may then be removed to prepare the post-grind package for connection with an external device or PCB.

Methods for vacuum assisted underfilling

Methods for applying an underfill with vacuum assistance. The method may include dispensing the underfill onto a substrate proximate to at least one exterior edge of an electronic device attached to the substrate. A space between the electronic device and the substrate is evacuated through at least one gap in the underfill. The method further includes heating the underfill to cause the underfill to flow into the space. Because a vacuum condition is supplied in the open portion of the space before flow is initiated, the incidence of underfill voiding is lowered.

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

Dram device with built-in self-test circuitry

A dynamic random access memory (DRAM) device includes a first and second integrated circuit (IC) die. The first integrated circuit die has test circuitry to generate redundancy information. The second integrated circuit die is coupled to the first integrated circuit die in a packaged configuration including primary storage cells and redundant storage cells. The second integrated circuit die further includes redundancy circuitry responsive to the redundancy information to substitute one or more of the primary storage cells with one or more redundant storage cells.

Semiconductor package and method for manufacturing semiconductor package

A semiconductor package includes a semiconductor chip including a circuit forming surface and a side surface, and a sealing insulation layer that seals the circuit forming surface and the side surface of the semiconductor chip, the sealing insulation layer having a first surface on a side of the circuit forming surface. At least one wiring layer and at least one insulation layer are formed one on top of the other on the first surface. The wiring layer formed on the first surface is electrically connected to the semiconductor chip. The insulation layer has a reinforcement member installed therein.

Semiconductor chip module, semiconductor package having the same and package module

A semiconductor module comprising a plurality of semiconductor chips where at least one semiconductor chip is laterally offset with respect to a second semiconductor chip, and substantially aligned with a third semiconductor chip such that an electrical connection can be made between an electrical contact in the first semiconductor chip and an electrical contact in the third semiconductor chip.

Packaged semiconductor device for high performance memory and logic

A packaged semiconductor device is disclosed. The device comprises a substrate having multiple layers between first and second oppositely disposed faces, and a cavity with an opening at the first face to nest at least one integrated circuit memory device. Logic circuitry is disposed on the second face and includes contacts for electrically coupling to the stacked integrated circuit memory devices. The logic circuitry is coupled to electrical contacts formed on the first face through first electrical paths formed in the multiple layers of the substrate, the first electrical paths including conductive traces and vias.

Methods and apparatuses to stiffen integrated circuit package

A dam stiffener for a package substrate is presented. In an embodiment, the dam stiffener comprises a thermally curable polymer, and is simultaneously cured with the underfill material to act as stiffener to the substrate. In another embodiment, a curable reservoir material can be dispensed to fill the space between the integrated circuit die and the dam stiffener, forming a thick reservoir layer, acting as an additional stiffener for the package substrate.

Manufacturing method of semiconductor device, semiconductor device and mobile communication device

A manufacturing method of a semiconductor device includes: sealing a semiconductor chip with a sealing resin containing a filler; exposing a part of the filler; etching at least a part of the exposed filler; and forming a metal film at least at a part of a surface of the sealing resin including inner surfaces of holes formed at the surface of the sealing resin by the etching.

Semiconductor device and method of fabricating the same

A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip. The molding material may be on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, wherein, in view of a first cross sectional profile, the molding material is separated from sidewalls of the second chip by the homogeneous integral underfill material such that the molding material does not contact sidewalls of the second chip.

Solder, soldering method, and semiconductor device

A solder includes Sn (tin), Bi (bismuth) and Zn (zinc), wherein the solder has a Zn content of 0.01% by weight to 0.1% by weight.

High Density Metal-Insulator-Metal Trench Capacitor

Higher capacitance density is achieved by increasing a surface area of a capacitor. A larger surface area may be obtained by forming isotropic ball shapes (a concave surface) in the trenches on the semiconductor die. The concave surfaces are fabricated by depositing bilayers of amorphous-silicon and silicon oxide. Openings are patterned in the silicon oxide hard mask for trenches. The openings are transferred to the amorphous-silicon layers through isotropic etching to form concave surfaces. Conducting, insulating, and conducting layers are deposited on the concave surfaces of the trenches by atomic layer deposition.

Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings

A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier

A semiconductor device includes a first semiconductor die or component having a plurality of bumps, and a plurality of first and second contact pads. In one embodiment, the first and second contact pads include wettable contact pads. The bumps are mounted directly to a first surface of the first contact pads to align the first semiconductor die or component. An encapsulant is deposited over the first semiconductor die or component. An interconnect structure is formed over the encapsulant and is connected to a second surface of the first and second contact pads opposite the first surface of the first contact pads. A plurality of vias is formed through the encapsulant and extends to a first surface of the second contact pads. A conductive material is deposited in the vias to form a plurality of conductive vias that are aligned by the second contact pads to reduce interconnect pitch.

Semiconductor Device and Method of Forming Bond Wires Between Semiconductor Die Contact Pads and Conductive TOV in Peripheral Area Around Semiconductor Die

A semiconductor wafer has a plurality of semiconductor die with contact pads. An organic material is deposited in a peripheral region around the semiconductor die. A portion of the organic material is removed to form a plurality of vias. A conductive material is deposited in the vias to form conductive TOV. The conductive TOV can be recessed with respect to a surface of the semiconductor die. Bond wires are formed between the contact pads and conductive TOV. The bond wires can be bridged in multiple sections across the semiconductor die between the conductive TOV and contact pads. An insulating layer is formed over the bond wires and semiconductor die. The semiconductor wafer is singulated through the conductive TOV or organic material between the conductive TOV to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically connected through the bond wires and conductive TOV.

Semiconductor device and noise suppressing method

A first semiconductor chip ( 200 ) is mounted on a second semiconductor chip ( 100 ). The first semiconductor chip ( 200 ) has a first conductor pattern ( 222 ). The second semiconductor chip ( 100 ) has a second conductor pattern ( 122 ). The second conductor pattern ( 122 ) is formed at a region overlapping the first conductor pattern ( 222 ) in a plan view. At least one element selected from a group consisting of the first conductor pattern ( 222 ) and the second conductor pattern ( 122 ) has a repetitive structure.

Integrated circuit package with molded cavity

An integrated circuit package system includes a base substrate, attaching a base die over the base substrate, attaching an integrated interposer having interposer circuit devices, over the base die, and forming a package system encapsulant having an encapsulant cavity over the integrated interposer.

Package 3D Interconnection and Method of Making Same

A method of manufacturing an integrated circuit (IC) package is provided. The method includes stacking an interposer substrate and a device structure, the interposer substrate having a first plurality of contact members formed on a first surface of the interposer substrate and the device structure having a second plurality of contact members that are exposed at a surface of the device structure, and laminating the interposer substrate and the device structure such that the first plurality of contact members are physically and electrically coupled to the second plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the second plurality of contact members.

Method for Attaching Wide Bus Memory and Serial Memory to a Processor within a Chip Scale Package Footprint

A method for forming a semiconductor device includes physically attaching a first semiconductor die to front surface of a first substrate. The first die is electrically connected to routings on front surface of the first substrate. The routings are electrically connected with conductive pads on back surface of the first substrate. A second semiconductor die is physically attached to front surface of a second substrate. The die is electrically connected to routings on front surface of second substrate. These routings are electrically connected with conductive pads on front surface of the second substrate. A third semiconductor die is physically attached to the second die. The third die is electrically attached to the second die through a plurality of through substrate vias (TSVs) within the second die. The conductive pads on back surface of first substrate are electrically connected to the conductive pads on front surface of second substrate.

Chip-last embedded interconnect structures and methods of making the same

The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.

Semiconductor device and manufacturing method of the same

A semiconductor device, includes: a wiring substrate, a stacked body mounted on the wiring substrate, an underfill layer filled into gaps between respective semiconductor chips of the stacked body; and a molding body made up of a molding resin covered and formed at outside of the stacked body and so on. The underfill layer is made up of a cured product of a resin material containing an amine-based curing agent, and the cured product has a Tg of 65° C. or more and 100° C. or less.

Semiconductor device

Disclosed is a semiconductor device configured by encapsulating a semiconductor element, partially or entirely covered with a polyimide, using an epoxy resin composition for encapsulating semiconductor device which contains an epoxy resin (A), a phenol resin (B), a curing accelerator (C), an inorganic filler (D), and a silane coupling agent (E) represented by the formula (1): (in the formula (1), each of R 1 , R 2 and R 3 represents a C 1-4 hydrocarbon group, all of them may be the same or different from each other, and n represents an integer from 0 to 2), and/or a hydrolytic condensate thereof.

Wiring substrate and method of manufacturing the same

A wiring substrate includes a structure in which a plurality of wiring layers are stacked through insulating layers intervening therebetween, and which has a first surface side and a second surface side, the first surface side where a semiconductor element is to be mounted, the second surface side being located at an opposite side to the first surface side, an interposer buried in an outermost one of the insulating layers located at the first surface side, and electrically connected to the semiconductor element to be mounted, and a sheet-shaped member buried in an outermost one of the insulating layers located at the second surface side, wherein, the interposer and the sheet-shaped member are disposed at symmetrical positions symmetrical each other.

Manufacturing method of semiconductor device, and semiconductor device

To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.

Semiconductor Device and Method of Forming a Thermally Reinforced Semiconductor Die

A semiconductor device includes a substrate with conductive traces. A semiconductor die is mounted with an active surface oriented toward the substrate. An underfill material is deposited between the semiconductor die and substrate. A recess is formed in an interior portion of the semiconductor die that extends from a back surface of the semiconductor die opposite the active surface partially through the semiconductor die such that a peripheral portion of the back surface of the semiconductor die is offset with respect to a depth of the recess. A thermal interface material (TIM) is deposited over the semiconductor die and into the recess such that the TIM in the recess is laterally supported by the peripheral portion of the semiconductor die to reduce flow of the TIM away from the semiconductor die. A heat spreader including protrusions is mounted over the semiconductor die and contacts the TIM.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate. A heat radiator is disposed on the heat conductive member. The heat conductive member thermally connecting the semiconductor element to the heat radiator reduces the risk that electromagnetic noise may be emitted from or may be incident on the semiconductor element.

Unpackaged and packaged IC stacked in a system-in-package module

There is provided a system and method for unpackaged and packaged IC stacked in a system-in-package module. There is provided a system-in-package module comprising a substrate including a first contact pad and a second contact pad disposed thereon, a packaged device disposed on the substrate, and an unpackaged device stacked atop the packaged device, wherein a first electrode of the packaged device is electrically and mechanically coupled to the first contact pad, and wherein a second electrode of the unpackaged device is electrically coupled to the second contact pad. The structure of the disclosed system-in-package module provides several advantages over conventional designs including increased yields, facilitated die substitution, enhanced thermal and grounding performance through direct connect vias, stacking of wider devices without a spacer, and a simplified single package structure for reduced fabrication time and cost.

Integrated circuit packaging system with collapsed multi-integration package and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a central integrated circuit over the base substrate; mounting a side package having a side package substrate along a peripheral region of the base substrate and laterally peripheral to the central integrated circuit with the side package substrate coplanar with the central integrated circuit; and encapsulating the central integrated circuit and the side package above the base substrate with a base encapsulation to form a planar surface over the central integrated circuit and the side package facing away from the base substrate.

Electromagnetic interference shielding structure for integrated circuit substrate and method for fabricating the same

An electromagnetic interference (EMI) shielding structure for integrated circuit (IC) substrate includes a plurality of conductive contacts, a covering layer, and a sputtered layer. The conductive contacts are formed at the perimeter of a chip area on the IC substrate. The covering layer is formed on the conductive contacts and covers the chip area. A groove is formed on the covering layer for exposing the conductive contacts. The sputtered layer is formed on the covering layer and connected to the conductive contacts. The EMI shielding structure can restrain the interference in the chip area.

Integrated circuit package including miniature antenna

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna.