МАТРИЦА ДЕТЕКТОРОВ ИЗЛУЧЕНИЯ

Изобретение относится к матрицам детекторов рентгеновского излучения для использования в системах компьютерной томографии. Технический результат - улучшение качества изображения, упрощение конструкции детектора. Модуль (22) детекторов излучения, особенно хорошо пригодный для использования в применениях компьютерной томографии (СТ), включает в себя сцинтиллятор (200), матрицу (202) фотодетекторов и электронику (205) сигнальной обработки. Матрица (202) фотодетекторов включает в себя полупроводниковую подложку (208), содержащую множество фотодетекторов и металлизацию (210), изготовленную на неосвещаемой стороне подложки (208). Металлизация трассирует электрические сигналы между фотодетекторами и электроникой (205) сигнальной обработки и между электроникой (205) сигнальной обработки и электрическим разъемом (209). 3 н. и 33 з.п. ф-лы, 11 ил.

ГИБРИДНАЯ ИНТЕГРАЛЬНАЯ СХЕМА

МНОГОКРИСТАЛЬНЫЙ КОРПУС И СПОСОБ ПРЕДОСТАВЛЕНИЯ В НЕМ ВЗАИМНЫХ СОЕДИНЕНИЙ МЕЖДУ КРИСТАЛЛАМИ

Изобретение относится к микроэлектронике, к структурам взаимного соединения в многокристальных корпусах. Сущность изобретения: многокристальный корпус включает в себя подложку, имеющую первую сторону, противоположную вторую сторону и третью сторону, которая продолжается от первой стороны до второй стороны, первый кристалл, закрепленный на первой стороне подложки, и второй кристалл, также закрепленный на первой стороне подложки, и мост, расположенный рядом с третьей стороной подложки и соединенный с первым кристаллом и со вторым кристаллом. Никакой из участков подложки не находится под мостом. Мост формирует соединение между первым кристаллом и вторым кристаллом. В качестве альтернативы мост может быть расположен в полости на подложке или между подложкой и слоем кристалла. Мост может составлять активный кристалл и может быть закреплен на подложке с использованием проводных соединений. Изобретение позволяет получить структуры взаимных соединений между кристаллами в корпусах с большой плотностью ...

СПОСОБ И УСТРОЙСТВО ДЛЯ ОЧИСТКИ, РАЗДЕЛЕНИЯ, МОДИФИКАЦИИ И/ИЛИ ИММОБИЛИЗАЦИИ ХИМИЧЕСКИХ ИЛИ БИОЛОГИЧЕСКИХ ОБЪЕКТОВ, НАХОДЯЩИХСЯ В ТЕКУЧЕЙ СРЕДЕ, И ОПОРА ИЗ МИКРОПРОВОЛОКИ

... 1. Устройство для очистки, разделения, модификации и/или иммобилизации химических или биологических объектов, находящихся в текучей среде, посредством связывания химического или биологического объекта с функциональным покрытием или лигандами, находящимися на поверхности опор из микропроволоки при отсутствии воздействия магнитного поля, создаемого между опорами из микропроволоки и частицами, находящимися в текучей среде, на разделение названных частиц, которое содержит по меньшей мере одну опору из микропроволоки, закрепленную своими концами и имеющую многослойную структуру, состоящую из центрального стержня и по меньшей мере одного покрывающего слоя и пригодную для связывания химических или биологических объектов, при этом поверхность микропроволоки модифицирована путем присоединения лигандов или нанесением на нее функционального покрытия. ! 2. Устройство по п.1, в котором центральный стержень и покрывающие слои выполнены из материала, выбранного из группы, включающей стеклянный, металлический ...

СИЛИКОНОВАЯ КЛЕЯЩАЯ КОМПОЗИЦИЯ ДЛЯ ТОНКОЙ ПОВЕРХНОСТИ СКЛЕИВАНИЯ И СПОСОБ ЕЕ ПОЛУЧЕНИЯ

... 1. Композиция теплового интерфейса (20), содержащая смесь полимерной матрицы и наполнителя, имеющего частицы, характеризующиеся максимальным диаметром частиц, меньшим приблизительно 25 микронов. 2. Композиция теплового интерфейса (20) по п.1, где полимерная матрица содержит отверждаемую полимерную композицию, выбирают из группы, состоящей из полидиметилсилоксановых смол, эпоксидных смол, акрилатных смол, органополисилоксановых смол, полиимидных смол, фторуглеродных смол, бензоциклобутеновых смол и фторированных простых полиаллиловых эфиров, полиамидных смол, полиимидоамидных смол, смол на основе цианатных сложных эфиров, фенолрезольных смол, смол на основе ароматических сложных полиэфиров, смол на основе полифениленового простого эфира (РРЕ), бисмалеимидтриазиновых смол, фторсмол, их комбинаций и любых других полимерных систем, известных специалисту в данной области техники. 3. Композиция теплового интерфейса (20) по п.1, где наполнитель выбирают из группы, состоящей из коллоидального диоксида ...

ELEKTRONISCHES BAUELEMENTGEHÄUSE

Die Technologie eines elektronischen Bauelementgehäuses ist offenbart. Ein elektronisches Bauelementgehäuse gemäß der vorliegenden Offenbarung kann ein Gehäusesubstrat, eine elektronische Komponente, eine Formmasse, die die elektronische Komponente einkapselt, und eine Redistributionsschicht umfassen, die derart angeordnet ist, dass die Formmasse zwischen dem Gehäusesubstrat und der Redistributionsschicht ist. Die Redistributionsschicht und das Gehäusesubstrat können elektrisch gekoppelt sein. Außerdem können die Redistributionsschicht und die elektronische Komponente elektrisch gekoppelt sein, um die elektronische Komponente und das Gehäusesubstrat elektrisch zu koppeln. Zugeordnete Systeme und Verfahren sind auch offenbart.

COOLING MEANS FOR INTEGRATED CIRCUIT CHIP DEVICE

Semiconductor assembly comprises (a) a substrate(12); (b) a semiconductor chip(10) having one surface bonded to the substrate, (c) a heat transfer element closely adjacent the second surface of the chip; (d) a thin layer(22) of heat conductive noneutectic alloy at the interface between heat transfer element and chip, pref. an alloy contg. Bi; and pref. (e) a spring type piston providing a load force to the heat transfer element, increasing contact between element and chip. The assembly pref. also includes a hat(20) providing a cover for the assembly and diffusing heat. A thin layer(22) of conductive noneutectic alloy is pref. provided at the interface between heat transfer element and hat surface. A diagonal spring type piston(16) pref. provides a load force increasing contact between heat transfer element and hat and chip surfaces. The thermal resistance of the chip interface is pref. 0.1-0.2 deg.C./W and of the heat interface is pref. 0.01-0.02 deg.C./W, both for contact load of 100g.

INTEGRIERTES SCHALTUNGSPACKAGE UND VERFAHREN

In einer Ausführungsform weist eine Struktur Folgendes auf: einen ersten integrierten Schaltungsdie, der erste Die-Anschlüsse aufweist; eine erste Dielektrikumsschicht auf den ersten Die-Anschlüssen; erste leitfähige Durchkontaktierungen, die sich durch die erste Dielektrikumsschicht hindurch erstrecken, wobei die ersten leitfähigen Durchkontaktierungen an eine erste Untergruppe der ersten Die-Anschlüsse angeschlossen sind; einen zweiten integrierten Schaltungsdie, der an eine zweite Untergruppe der ersten Die-Anschlüsse mit ersten aufschmelzbaren Anschlüssen gebondet ist; ein erstes Verkapselungsmaterial, das den zweiten integrierten Schaltungsdie und die ersten leitfähigen Durchkontaktierungen umgibt, wobei das erste Verkapselungsmaterial und der erste integrierte Schaltungsdie seitlich angrenzend sind; zweite leitfähige Durchkontaktierungen benachbart zu dem ersten integrierten Schaltungsdie; ein zweites Verkapselungsmaterial, das die zweiten leitfähigen Durchkontaktierungen, das erste ...

Vorrichtungen, Systeme und Verfahren zur Stromzufuhr

Vorrichtung, umfassend: einen Träger (110), der angrenzend an eine erste Seite (114) einer Leiterplatte (120) angeordnet ist, die ein Kontaktfeld (130) aufweist, das darin von einer Schaltung (140) der Leiterplatte (120) angeordnet ist, wobei das Kontaktfeld (130) einen äußeren Rand (160) und einen inneren Rand (152) aufweist, wobei die Schaltung (140) innerhalb des inneren Rands (152) des Kontaktfelds (130) einen Stromversorgungskontakt (148) aufweist, und wobei die Leiterplatte (120) außerhalb des äußeren Rands (160) des Kontaktfelds (130) einen Stromversorgungs-Anschlusspunkt (156) aufweist; und einen Leiter (170), der an dem Träger (110) befestigt ist, wobei der Leiter (170) einen ersten Anschlusspunkt (172) und einen zweiten Anschlusspunkt (174) aufweist, und wobei der erste Anschlusspunkt (172) durch einen ersten Stift (178) mit dem Stromversorgungskontakt (148) verbunden ist und der zweite Anschlusspunkt (174) durch einen zweiten Stift (178) mit dem Stromversorgungs-Anschlusspunkt ...

Elektrischer Schaltungsapparat

Mehrchip-Halbleitermodul und Herstellungsverfahren dafür

Ein Mehrchip-Halbleitermodul weist auf: ein Chipmontageteil mit einem ersten und zweiten Substrat, wobei das erste Substrat hat: eine entgegengesetzte erste und zweite Oberfläche, mehrere erste leitende Kontaktlöcher, die sich durch die erste und zweite Oberfläche erstrecken, und eine erste Schaltungsanordnung, die auf der zweiten Oberfläche strukturiert und mit den ersten leitenden Kontaktlöchern elektrisch verbunden ist, wobei das zweite Substrat hat: eine entgegengesetzte erste und zweite Oberfläche, mehrere zweite leitende Kontaktlöcher, die sich durch die erste und zweite Oberfläche des zweiten Substrats erstrecken, eine zweite Schaltungsanordnung, die auf der zweiten Oberfläche des zweiten Substrats strukturiert und mit den zweiten leitenden Kontaktlöchern elektrisch verbunden ist, und eine darin ausgebildete erste Chipaufnahmeöffnung, wobei die erste Oberfläche des zweiten Substrats auf der zweiten Oberfläche des ersten Substrats verbunden ist, so daß die zweite Schaltungsanordnung ...

Integration von Silicium-Photonik-IC für hohe Datenrate

Integrierte Komponentenbaugruppe, die umfasst:eine Leiterplatte (PCB);eine integrierte Photonikschaltung (PIC), die mit der PCB auf einer ersten Seite der PIC mechanisch gekoppelt ist; undeine Treiber-IC mit einer ersten Seite, wobei die erste Seite der Treiber-IC(i) mit einer zweiten Seite der PIC über einen ersten Satz von Höcker-Bondverbindungen direkt mechanisch und elektrisch gekoppelt ist, und(ii) mit der PCB über einen zweiten Satz von Höcker-Bondverbindungen elektrisch gekoppelt ist.

Wärmesenkenanordnung mit einer thermisch leitenden Platte für eine Mehrzahl von integrierten Schaltungen auf einem Substrat

BRÜCKE FÜR RADIOFREQUENZ- (RF) MULTI-CHIP-MODULE

Ausführungsbeispiele können sich auf ein Radiofrequenz- (RF) Multi-Chip-Modul beziehen, das einen ersten RF-Die und einen zweiten RF-Die umfasst. Der erste und zweite RF-Die können mit einem Package-Substrat an einer inaktiven Seite des jeweiligen Dies gekoppelt sein. Eine Brücke kann mit einer aktiven Seite des ersten und zweiten RF-Dies gekoppelt sein, sodass der erste und zweite RF-Die kommunikativ durch die Brücke gekoppelt sind und sodass sich der erste und zweite RF-Die zumindest teilweise zwischen dem Package-Substrat und der Brücke befinden. Andere Ausführungsbeispiele können beschrieben oder beansprucht sein.

Verfahren zum Montieren von Halbleiterelementen

Semiconductor module, has semiconductor chip stack arranged on wiring substrate, where heat conducting layer e.g. foil with anisotropic heat conducting particles is arranged between semiconductor chips

The semiconductor module has a semiconductor chip stack (2) arranged on a wiring substrate (3), where a heat conducting layer e.g. a foil (19) with anisotropic heat conducting particles is arranged between semiconductor chips (4,5). The layer has anisotropic heat conducting particles in vertical direction to the layer and/or foil and lower heat conductivity towards the layer and/or the foil. Independent claims are also included for the following: (1) foil for heat dissipation of semiconductor chip stack (2) method for the production of a semiconductor module.

Semiconductor component especially for low voltage power components has chip with contact bumps surrounded by conductive adhesive and electrodes shorted to a metal contact layer

A semiconductor component comprises housing (2) and chip (3) with a large surface contact between contact metal (5) on the chip and external contacts (6). Many small chip electrodes (7) are shorted to the contact metal and a transition layer (9) has contact bumps (11) surrounded by electrically conductive adhesive (12) on the contact metal.

Contacting electronic components on flexible substrates involves using substrate and other part elasticity and causing elastic deformation by contact force generating or introducing elements

The method involves making use of the elasticity of the substrate (4) and of other elastic auxiliary elements if appropriate to produce contact forces. The elastic deformation is caused by third components, generally described as contact force generating or introducing elements (3,6), so that an unrestrictedly reversible force or force and shape-locking contact joint exists between the chip (5) connection and the corresponding contact structure.

Leistungshalbleitermodul und Verfahren zur Herstellung eines Leistungshalbleitermoduls

Ein Leistungshalbleitermodul kann einen Träger, einen Leistungshalbleiterchip, der so über dem Träger angeordnet ist, dass eine erste Hauptseite des Leistungshalbleiterchips dem Träger zugewandt ist, einen Kontaktclip, der so über dem Leistungshalbleiterchip angeordnet ist, dass eine zweite, der ersten Hauptseite gegenüberliegende Hauptseite des Leistungshalbleiterchips; dem Kontaktclip zugewandt ist, und ein zwischen der zweiten Hauptseite und dem Kontaktclip angeordnetes Abstandshalterelement umfassen, wobei eine erste Lötverbindung die zweite Hauptseite und das Abstandshalterelement verbindet und wobei eine zweite Lötverbindung das Abstandshalterelement und den Kontaktclip verbindet.

Leistungshalbleiterbauelement mit großflächigen Außenkontakten sowie Verfahren zur Herstellung desselben

Halbleitervorrichtung mit Extraktionselektrode und Verfahren

Halbleitervorrichtung, die umfasst: ein Leistungshalbleiterelement (1), das eine erste Hauptelektrode (1PE1), die auf einer vorderen Oberfläche ausgebildet ist, und eine zweite Hauptelektrode (1PE2) umfasst, die auf einer hinteren Oberfläche des Leistungshalbleiterelements (1) ausgebildet ist; eine Metallplatte (3), die mit der zweiten Hauptelektrode (1PE2) des Leistungshalbleiterelements (1) elektrisch verbunden ist; eine erste Verbindungselektrode (10A) und eine zweite Verbindungselektrode (10B), die auf der ersten Hauptelektrode (1PE1) einander gegenüberliegend getrennt ausgebildet sind; und eine Extraktionselektrode (4), die ein erstes Elektrodenverdrahtungsteil (5A), das so ausgebildet ist, dass es von einem Seitenabschnitt der Extraktionselektrode (4) nach unten verläuft, und ein zweites Elektrodenverdrahtungsteil (5B), das getrennt von dem ersten Elektrodenverdrahtungsteil (5A) so ausgebildet ist, dass es von dem anderen Seitenabschnitt der Extraktionselektrode (4), der dem einen ...

Semiconductor device has copper-tin alloy layer formed on junction portion of solder ball consisting of tin, and wiring consisting of copper

A copper-tin alloy layer (21) of about 1.87 micron thickness, is formed on the junction portion of tin solder ball (11) and copper wiring (2). The rate of content of tin and lead in solder ball is 63% and 37%, respectively. The wiring is connected to the semiconductor chip. The distributed density per lead lump unit cross section of 3 or more in solder ball, is 20\*10<4> pieces/mm. An Independent claim is also included for manufacturing method of semiconductor device.

Semiconductor chip on a carrier and connection process has foil with structured metallization giving electrical contact between chip and carrier surfaces

A semiconductor chip (1) which is permanently attached to a carrier comprises a foil (2) having structured metallization (3) meeting the contact surfaces of the carrier and of the chip to provide electrical connection between them. An Independent claim is also included for a process for connecting the chip and carrier as above.

Input/output architecture for mounted processors, and methods of using same

Multi-chip package and method of die-to-die interconnects in same

A heat sink assembly for a multi-chip-module

Substrate for integrated circuit devices including multi-layer glass core and methods of making the same

Semiconductor device and production method

Flip chip package incorporating metallurgical bond to enhance thermal conduction

An integrated circuit device 10 incorporating a metallurgical bond to enhance thermal conduction to a heat sink 28. In a semiconductor device, a surface of an integrated circuit die 14 is metallurgically bonded to a surface of a heat sink 28. In an exemplary method of. manufacturing the device, the upper surface of a package substrate 12 includes an inner region and a peripheral region. The integrated circuit die 14 is positioned over the substrate surface and a active surface 16 of the integrated circuit die 14 is placed in contact with the package substrate 12. A metallic layer 30 is formed on a second opposing surface 18 of the integrated circuit die 14. A preform is positioned on the metallic layer and a heat sink 28 is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink 28 to the second surface 18 of the integrated circuit die 14.

Stacked wafer or die packaging with enhanced thermal and device performance

Multi-chip package and method of providing die-to-die interconnects in same

Nput/output architechture for mounted processors, and methods of using same

CONDUCTION-COLED CIRCUIT PACKAGE AND METHOD OF FABRICATION

ELECTRICAL COMPONENTS

HEATCONDUCTIVE GREASE AND PROCEDURE AND DEVICES, WITH WHICH THE GREASE IS USED

ELECTRONIC DEVICE WITH INTEGRATED CIRCUIT

CCU COOLING ARRANGEMENT WITH IMPROVED ACHIEVEMENT

HARDENABLE SILICONE COMPOSITION AND ELECTRONICS CONSTRUCTION UNIT

AMIDE-SUBSTITUTED SILIKONE AND PROCEDURE FOR YOUR PRODUCTION AND USE

BALL MATRIX HOUSING WITH HEAT DISTRIBUTOR AND ITS PRODUCTION

LIGHTING INSTALLATION WITH A MONOLITHIC CERAMIC COMPOUND LUMINESCENCE CONVERTER

PROCEDURE FOR THE PRODUCTION OF CONDUCTIVE FOILS AS WELL AS IN THIS PROCEDURE MANUFACTURED ARTICLES

HEAT SOFTENING OF THERMALLY CONDUCTIVE COMPOSITIONS AND PROCEDURE FOR YOUR PRODUCTION

VERFAHREN ZUM EINBETTEN ZUMINDEST EINER FLEXIBLEN LEITERBAHNFOLIE IN KUNSTSTOFF, LEITERBAHNENEINHEITSOWIE EINBETTUNGSEINHEIT HIEFÜR

EMV SCREEN WITH IMPROVED HEAT DISSIPATION

FLEXIBLE THERMAL LINKS AND BUILDING GROUPS

Method and apparatus for providing power to a microprocessor with integrated thermal and emi management

A combined heat sink/electromagnetic shield

COOLING SYSTEM FOR A SEMICONDUCTOR ELEMENT, SEMICONDUCTOR MODULE INCLUDING SUCH A SYSTEM AND A THERMALLY CONDUCTIVE MEMBER THEREFOR

Semiconductor device, wiring board for mounting semiconducto r and method of production of semiconductor device

Thin bond-line silicone adhesive composition and method for preparing the same

DIGITAL AND RF SYSTEM AND METHOD THEREFOR

Multichip module connected to flexible, film-like substrate

Method and apparatus for cooling a semiconductor die

Thermal management for solid-state drive

An electronic device including a printed circuit board (PCB) including a thermal conduction plane and at least one heat generating component mounted on the PCB and connected to the thermal conduction plane. A frame is connected to the PCB so as to define a first thermally conductive path between at least a portion of the frame and the at least one heat generating component. The electronic device further includes at least one thermally conductive layer between the frame and the at least one heat generating component so as to define a second thermally conductive path between at least a portion of the frame and the at least one heat generating component. WO 2014/169152 PCT/US2014/033699 1/5 -jD N >4 cc >o con, co >LL/- ±. I' / /1' 'KIca7 1 i/,'~ co : 1 ri ~YX, j c) If N CD, ...

METHOD AND APPARATUS FOR PROVIDING POWER TO A MICROPROCESSOR WITH INTEGRATED THERMAL AND EMI MANAGEMENT

A microprocessor packaging architecture using a modular circuit board assembly that provides power to a microprocessor while also providing for integrated thermal and electromagnetic interference (EMI) is disclosed. The modular circuit board assembly comprises a substrate, having a component mounted thereon, a circuit board, including a circuit for supplying power to the component, and at least one conductive interconnect device disposed between the substrate and the circuit board, the conductive interconnect device configured to electrically couple the circuit to the component.

ISLAND MATRIXED GALLIUM NITRIDE MICROWAVE AND POWER SWITCHING TRANSISTORS

A gallium nitride (GaN) device that has greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The layout scheme, which uses island electrodes rather than finger electrodes, is shown to increase the active area density over that of conventional interdigitated structures. Ultra low on resistance transistors can be built using the island topology. Specifically, the present invention, which uses conventional GaN lateral technology and electrode spacing, provides a means to enhance cost/effective performance of all lateral GaN structures.

HEAT TRANSFER MECHANISM FOR INTEGRATED CIRCUIT PACKAGE

HEAT TRANSFER MECHANISM FOR INTEGRATED CIRCUIT PACKAGE Heat is removed from silicon devices in an integrated circuit package by means of a thermal liquid material contained in a film mounted on the underside of a cover enclosing the integrated circuit device. The film is electrically non-conductive and the film with the enclosed thermal liquid material form a formable pillow such that after the chip/substrate are assembled, the cover with the film containing the thermal liquid material is placed over the substrate and sealed thereto in a manner such that the film comes into direct contact with the top of the chips mounted on the substrate. This provides a direct heat transfer from the chip through the film to the thermal liquid material out to the cover, which may be formed as a heat radiator.

HIGH PERFORMANCE INTEGRATED CIRCUIT CHIP PACKAGE AND METHOD OF MAKING SAME

A high performance integrated circuit chip package includes a support substrate having conductors extending from one face to the opposite face thereof and a multilayer wiring substrate on the opposite face of the support substrate for connecting chips mounted thereon to one another and to the conductors. A heat sink includes microchannels at one face thereof, with thermally conductive cushions connecting the one face of the heat sink with the exposed back sides of the chips, to provide a high density chip package with high heat dissipation. The multilayer wiring substrate may be formed by a self-aligned thin film wiring method, with a self-aligned lift off method being employed to form internal wiring planes. The support substrate and heat sink may be formed of blocks of material having thermal expansion matching silicon. The cushions are a low melting point solder, preferably pure indium, and are sufficiently thick to absorb thermal stresses, but sufficiently thin to efficiently conduct ...

CONDUCTION-COOLED CIRCUIT PACKAGE AND METHOD FOR MAKING SAME

REACTIVE FOIL ASSEMBLY

PACKAGE-ON-PACKAGE (POP) DEVICE COMPRISING BI-DIRECTIONAL THERMAL ELECTRIC COOLER

A package-on-package (PoP) device includes a first package, a second package, and a bi-directional thermal electric cooler (TEC). The first package includes a first substrate and a first die coupled to the first substrate. The second package is coupled to the first package. The second package includes a second substrate and a second die coupled to the second substrate. The TEC is located between the first die and the second substrate. The TEC is adapted to dynamically dissipate heat back and forth between the first package and the second package. The TEC is adapted to dissipate heat from the first die to the second die in a first time period. The TEC is further adapted to dissipate heat from the second die to the first die in a second time period. The TEC is adapted to dissipate heat from the first die to the second die through the second substrate.

A CONTACT PAD AND METHOD OF FORMING A CONTACT PAD FOR AN INTEGRATED CIRCUIT

A contact pad in an integrated circuit is disclosed. The contact pad comprises a flat portion comprising a base (302) of the contact pad; a plurality of projections (304, 306, 308, 310, 312) extending from and substantially perpendicular to the flat portion; and a solder ball (108, 124) attached to the projections and the flat portion. A method of forming a contact pad is also disclosed.

PACKAGED SEMICONDUCTOR DEVICE SUITABLE TO BE MOUNTED AND CONNECTED TO MICROSTRIP LINE STRUCTURE BOARD

A package semiconductor device comprises an insulating substrate having an upper surface formed with a plurality of connection pads and an under surface formed with a plurality of external connection members each of which is electrically connected to a corresponding one of the connection pads through a via hole formed through the insulating substrate. An integrated circuit chip is bonded facedown on the upper surface of the insulating substrate so that the integrated circuit chip is electrically connected to the connection pads through solder bumps. An electrically conductive cap is covered on the first surface of the insulating substrate so that the integrated circuit chip is encapsulated in a space defined by the insulating substrate and the conductive cap. A back electrode of the integrated circuit chip is electrically connected to the conductive cap through an electrically conducting element.

APPARATUS FOR HEATING AND COOLING AN ELECTRONIC DEVICE

A method and apparatus maintain the operating temperature of an electronic device within an acceptable operating range for a wide range of ambie nt temperatures. The apparatus includes a heat sink and a temperature dependent loading device which brings the heat sink into thermal contact with the electron ic device when the ambient temperature exceeds a threshold level.

CONDUCTIVE COMPOSITE ARTICLES BASED ON EXPANDABLE AND CONTRACTIBLE PARTICULATE MATRICES

The invention provides a composite article (24) whose electrical and/or thermal conductivity undergoes a significant change in response to variations in one of several externally controlled thermodynamic parameters, such as temperature, pH, ionic strength, and solvent composition. The composite article (24) is formed by at least three components: conductive filler particles (22), cross-linked polymeric particles (10/12) that are swellable and deswellable, and a solvent mix (20). In the deswollen state, the gel particles (10) occupy a relatively small volume fraction of the composite article (24), allowing the conductive filler particles (22) to be discrete, fully suspended and free flowing in the solvent mix (20). Upon switching to the swollen state, the interstitial volume of the composite article (24) between the cross-linked gel particles (12) diminishes, forcing the conductive filler particles (22) to come into intimate contact with one another, thus creating a conductive percolation ...

Heat-removing can for electronic component

Multichip package

Thermal interface material layer and includes a thermal interface material layer of the stacked package device

Semiconductor packaging structure and production method thereof

The invention provides a semiconductor packaging structure and a production method thereof. The method comprises steps of providing a substrate, arranging a plurality of grounding pads on the substrate, arranging a first semiconductor component and a second semiconductor component on the substrate, placing the grounding pads between the first semiconductor component and the second semiconductor component, and connecting a plurality of conductive welding lines to the grounding pads. By the aid of the structure, the conductive welding lines can shield electromagnetic interference effectively.

Thermoelectric cooler having solderless electrode

Stacked semiconductor architecture including semiconductor die and heat sink on a substrate die

Semiconductor packaging structure and cooling fin arrangement method thereof

The invention provides a semiconductor packaging structure and a cooling fin arrangement thereof. In the semiconductor packaging structure, an opening running through the upper surface and the lower surface is arranged on a cooling fin, and soldering tins are respectively arranged in the opening and on the upper surface and the lower surface of the cooling fin, wherein the soldering tin distributed in the opening is connected with the soldering tins on the upper surface and the lower surface.

Efficient heat radiation packaging structure based on graphene thermal interface layer and manufacturing method thereof

Chip stack package structure

A chip stack package structure comprises a substrate, a first chip, a plurality of conductors, a second chip and a plurality of conductive columns. The substrate includes a first surface, and the first chip is arranged on the first surface and forms a first orthographic projection on the first surface. The conductors are arranged and electrically connected between the first chip and the first surface. The second chip is arranged on the first surface and forms a second orthographic projection on the first surface, wherein at least a portion of the first chip is between the second chip and the substrate; and the first orthographic projection and the second orthographic projection partially overlap at least. Additionally, the conductive columns are arranged and electrically connected between the second chip and the first surface.

Light emitting device

使用波动焊接工艺固定母板芯片组散热器

... 提供一种电子器件和用于从产热部件交换热量的方法，该产热部件具有正面和背面，正面与背面相对设置，并且正面固定到包括多个孔的基板上。热界面材料设置在产热部件的背面上。包括对应基板中的多个孔的多个固定管脚的散热器设置在热界面材料上，以便固定管脚穿过这些孔设置。热界面材料熔化和湿润，以便在通过波动焊接机的预热器上时在背面和散热器之间形成热耦合。此外，当从波动焊接机中的焊接波上穿过时，焊接固定管脚，以便在各个固定管脚和基板之间形成焊接头，由此在热界面材料的预热期间形成的热耦合中锁定，以便提供低成本热解决方案。 ...

Semiconductor device and method for manufacturing the same

Method of making semiconductor package having exposed heat spreader

Group III nitride based flip-chip integrated circuit and method for fabricating

Chip-scale package

A method for manufacturing a semiconductor package that includes forming a frame inside a conductive can, the frame being unwettable by liquid solder.

Thermal interfacial material and radiating device combination using the same thermal interfacial material

Method, device and system for cooling heat source

Semiconductor device and manufacturing method thereof

半导体封装结构及其制造方法

... 一种半导体封装的结构及其制造方法，该结构包括：具有导体片的构架，每个导体片皆掩埋在通过该构架敞开且按一定间隔设置的数个小孔中的一个中；具有固定于夹具上并在四个方向上延伸的引线的TAB，每根引线用于电连接一个导体片。所说方法包括以下步骤：根据封装的形状提供构架；把引线贴装在夹具上，使之在四个方向上延伸，构成TAB；在构架上按一定间隔形成小孔；在每个小孔中掩埋一个导体片；回流TAB上的引线，电连接引线与各导体片，并把引线贴装到构架上。 ...

Semiconductor device

Semiconductor device and manufacture method therefor

EQUIPMENT HAS SEMICONDUCTOR

Assembly antenna-electronic circuit.

MODULE SEMI CONDUCTEUR REFROIDI PAR CONDUCTION ET SON PROCEDE DE FABRICATION

Dispositif permettant de transférer la chaleur engendrée par des blocs semi-conducteurs contenus dans un module de circuit électronique. Entre le bloc semi-conducteur 2 et le capot servant de puits de chaleur 8 est insérée une patte de métal 10 favorisant l'évacuation de la chaleur provenant du bloc semi-conducteur 2. La patte de métal 10 est liée par soudure au capot 8 soit directement soit par l'intermédiaire d'un film mince 9. Cette patte 10 est liée au bloc semi-conducteur 2 de façon séparable. Cette structure permet le retrait du capot et de la patte de métal 10 en cas de changement ou de réparation du bloc semi-conducteur 2. Utilisation dans la technologie des semi-conducteurs et des circuits intégrés.

ASSEMBLING AN INTEGRATED CIRCUIT DIE AND A PLATE

ELECTRONIC POWER MODULE AND ELECTRICAL CONVERTER INCLUDING POWER

MANUFACTORING PROCESS Of an ELECTRONICS COMPONENT OF POWER, ELECTRONIC ETCOMPOSANT OF POWER THUS OBTAINED

Electronic device including electrical connections on an encapsulation block

METHOD FOR REALIZATION Of ELEMENTS CHIP HAS PROVIDED WITH GROOVES Of INSERTION OF WIRE

L'invention concerne un procédé de réalisation d'éléments à puce (10) munis d'une rainure (14), comprenant les étapes suivantes : prévoir, sur un substrat d'interconnexion (22), une piste conductrice (26) agencée pour relier une plage de contact d'une face active d'une puce (20) à une zone correspondant à une première paroi de la rainure ; faire croître par électrodéposition un plot de contact (16) sur la piste conductrice au niveau de la zone correspondant à la première paroi de la rainure ; assembler la puce (20) sur le substrat par sa face active de manière qu'une paroi latérale de la puce forme le fond de la rainure ; usiner la puce par sa face arrière parallèlement au substrat en mesurant la distance entre la face arrière de la puce et le plot de contact ; arrêter l'usinage lorsque la distance mesurée atteint une valeur souhaitée ; et assembler par collage une plaque (24) sur la face arrière de la puce de manière à former une deuxième paroi de la rainure.

Electronic component e.g. microelectromechanical system type component, for use in e.g. three-dimensional heterogeneous electronic device, has conductor via comprising hollow space that forms fluid circulation zone extending between ends

Composant électronique (100) comportant au moins un via conducteur (106) réalisé dans au moins un substrat (101), dans lequel le via conducteur s'étend entre une première extrémité (105) qui forme une ouverture débouchant au niveau d'une face (104) du substrat et une seconde extrémité (107), le via conducteur comportant en outre au moins une portion de matériau électriquement conducteur (110) s'étendant depuis la première extrémité jusqu'à la seconde extrémité et au moins un espace vide (114) apte à former une zone de circulation d'un fluide s'étendant depuis la première extrémité jusqu'à la seconde extrémité ...

Semiconductor laser emitter has laser diode in stack with two heat dissipators for improved thermal properties

L'invention concerne un dispositif consistant en un assemblage comprenant un premier dissipateur (106), un composant laser (113), un deuxième dissipateur (109). Le premier dissipateur est un substrat semi-conducteur sur lequel est reporté le composant laser par des technologies de microbillage et sont intégrées les lignes d'interconnections permettant l'alimentation du composant laser. Ce même substrat peut intégrer les composants actifs (circuit de pilotage du laser, photodiode de contrôle par exemple) et passifs (inductances, capacités, résistances) de mise en oeuvre des composants actifs. Les composants actifs peuvent également reportés par des techniques soit de microbillage ou de soudure conventionnelles. Le deuxième dissipateur est, soit reporté sur le composant (113) soit directement réalisé sur la face arrière du composant laser par le procédé décrit dans l'invention.

MANUFACTORING PROCESS Of an OPTICAL SEMICONDUCTOR CASE AND OPTICAL BOITIERSEMI-CONDUCTEUR

Heat dissipating material and semiconductor device using same

Disclosed is a heat dissipating material which is interposed between a heat-generating electronic component and a heat dissipating body. This heat dissipating material contains (A) 100 parts by weight of a silicone gel cured by an addition reaction having a penetration of not less than 100 (according to ASTM D 1403), and (B) 500-2000 parts by weight of a heat conductive filler. Also disclosed is a semiconductor device comprising a heat-generating electronic component and a heat dissipating body, wherein the heat dissipating material is interposed between the heat-generating electronic component and the heat dissipating body.

Semiconductor device

A semiconductor device which includes a substrate, a semiconductor element arranged on the substrate, a heat dissipation component arranged on the semiconductor element, and a mold component covering an upper part of the substrate, the semiconductor element and the heat dissipation component, wherein an area of a surface on the semiconductor element of the heat dissipation component is larger than an area of a surface on which the heat dissipation component of the semiconductor element is arranged.

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

Semiconductor device and method of manufacturing the same

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

Semiconductor structure having conductive vias and method for manufacturing the same

A semiconductor structure includes a plurality of thermal vias and a heat dissipation layer disposed at a periphery of a back surface of a lower chip in a stacked-chip package. This arrangement improves solderability of a subsequently-bonded heat sink. Additionally, the thermal vias and the heat dissipation layer provide an improved thermal conduction path for enhancing heat dissipation efficiency of the semiconductor structure. A method for manufacturing the semiconductor structure is also provided.

Semiconductor chip device with polymeric filler trench

A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Thermal interface material application for integrated circuit cooling

Techniques provide improved thermal interface material application in an assembly associated with an integrated circuit package. For example, an apparatus comprises an integrated circuit module, a printed circuit board, and a heat transfer device. The integrated circuit module is mounted on a first surface of the printed circuit board. The printed circuit board has at least one thermal interface material application via formed therein in alignment with the integrated circuit module. The heat transfer device is mounted on a second surface of the printed circuit board and is thermally coupled to the integrated circuit module. The second surface of the printed circuit board is opposite to the first surface of the printed circuit board.

Semiconductor device including coupling conductive pattern

A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate.

Anti-tamper microchip package based on thermal nanofluids or fluids

A tamper-resistant microchip package contains fluid- or nanofluid-filled capsules, channels, or reservoirs, wherein the fluids, either alone or in combination, can destroy circuitry by etching, sintering, or thermally destructing when reverse engineering of the device is attempted. The fluids are released when the fluid-filled cavities are cut away for detailed inspection of the microchip. Nanofluids may be used for the sintering process, and also to increase the thermal conductivity of the fluid for die thermal management. Through-vias and micro vias may be incorporated into the design to increase circuitry destruction efficacy by improving fluid/chip contact. Thermal interface materials may also be utilized to facilitate chip cooling.

Semiconductor device having semiconductor member and mounting member

A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased.

Methods of fabricating package stack structure and method of mounting package stack structure on system board

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

Integrated circuit packaging system with warpage control and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier.

Integrated circuit packaging system with a shield and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a first integrated circuit over the substrate; forming an encapsulant around the first integrated circuit and over the substrate; and forming a shield structure within and over the encapsulant while simultaneously forming a vertical interconnect structure.

Heat spreader with mechanically secured heat coupling element

A heat spreader for dissipating heat generated by at least one heat-generating power semiconductor device. Such a heat spreader comprises a base plate ( 11 ) which is connectable in a heat-conducting manner to the at least one power semiconductor device ( 2 ), and at least one heat coupling element ( 4 ) which is connected in a heat conducting manner to the at least one power semiconductor device ( 2 ) on the one hand and to the base plate ( 11 ) on the other hand and comprises at least one elastic layer ( 5 ). The heat coupling element ( 4 ) comprises at least one holding element for mechanically fixing the heat coupling element ( 4 ) relative to a plane defined by the base plate ( 11 ).

Integrated circuit packaging system with interposer interconnections and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure; mounting a first-external-package-component to the routing structure; and forming a first-external-package-encapsulation covering the first-external-package-component.

Semiconductor module having a semiconductor chip stack and method

A semiconductor module having a semiconductor chip stack and a method for producing the same is disclosed. In one embodiment, a thermally conductive layer with anisotropically thermally conductive particles is arranged between the semiconductor chips. The anisotropically thermally conductive particles have a lower thermal conductivity in a direction vertically with respect to the layer or the film than in a direction of the layer or the film.

System for clamping heat sink

A system for clamping a heat sink that prevents excessive clamping force is provided. The system may include a heat sink, a semiconductor device, a printed circuit board, and a cover. The semiconductor device may be mounted onto the circuit board and attached to the cover. The heat sink may be designed to interface with the semiconductor device to transfer heat away from the semiconductor device and dissipate the heat into the environment. Accordingly, the heat sink may be clamped into a tight mechanical connection with the semiconductor device to minimize thermal resistance between the semiconductor device and the heat sink. To prevent excessive clamping force from damaging the semiconductor device, loading columns may extend between the cover and the heat sink.

System comprising a semiconductor device and structure

A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

Island matrixed gallium nitride microwave and power switching transistors

A gallium nitride (GaN) device that has greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The layout scheme, which uses island electrodes rather than finger electrodes, is shown to increase the active area density over that of conventional interdigitated structures. Ultra low on resistance transistors can be built using the island topology. Specifically, the present invention, which uses conventional GaN lateral technology and electrode spacing, provides a means to enhance cost/effective performance of all lateral GaN structures.

Low cost thermally enhanced hybrid bga and method of manufacturing the same

A semiconductor package is formed having a substrate juxtaposed on at least two sides of a semiconductor die. Both the substrate and the semiconductor die are affixed to a conductive layer that draws heat generated during use of the semiconductor package away from the semiconductor die and the substrate. There are also electrical contacts affixed to the substrate and the semiconductor die. The electrical contacts facilitate electrical connection between the semiconductor die, the substrate, and any external devices or components making use of the semiconductor die. The substrate, semiconductor die, and at least a portion of some of the electrical contacts are enclosed by an encapsulating layer insulating the components. Portions of the electrical contacts not enclosed by the encapsulating layer are affixed to an outside device, such as a printed circuit board.

Electronic device having liquid crystal polymer solder mask and outer sealing layers, and associated methods

An electronic device includes a substrate with a circuit layer thereon that has a solder pad. There is a liquid crystal polymer (LCP) solder mask on the substrate that has an aperture aligned with the solder pad. There is a fused seam between the substrate and the LCP solder mask. Solder is in the aperture, and a circuit component is electrically coupled to the solder pad via the solder. A first dielectric layer stack having a first plurality of dielectric layers is on the LCP solder mask and has an aperture aligned with the solder pad. There is a first LCP outer sealing layer on the first dielectric layer stack, and a second dielectric layer stack having a second plurality of dielectric layers on the substrate on a side thereof opposite the LCP solder mask. Further, there is a second LCP outer sealing layer on the second dielectric layer stack.

Semiconductor chip module, semiconductor package having the same and package module

A semiconductor module comprising a plurality of semiconductor chips where at least one semiconductor chip is laterally offset with respect to a second semiconductor chip, and substantially aligned with a third semiconductor chip such that an electrical connection can be made between an electrical contact in the first semiconductor chip and an electrical contact in the third semiconductor chip.

Packaged semiconductor device for high performance memory and logic

A packaged semiconductor device is disclosed. The device comprises a substrate having multiple layers between first and second oppositely disposed faces, and a cavity with an opening at the first face to nest at least one integrated circuit memory device. Logic circuitry is disposed on the second face and includes contacts for electrically coupling to the stacked integrated circuit memory devices. The logic circuitry is coupled to electrical contacts formed on the first face through first electrical paths formed in the multiple layers of the substrate, the first electrical paths including conductive traces and vias.

Semiconductor device and method of fabricating the same

A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip. The molding material may be on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, wherein, in view of a first cross sectional profile, the molding material is separated from sidewalls of the second chip by the homogeneous integral underfill material such that the molding material does not contact sidewalls of the second chip.

Chip package with plank stack of semiconductor dies

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Heat radiation material, electronic device and method of manufacturing electronic device

The electronic device includes a heat generator 54, a heat radiator 58, and a heat radiation material 56 disposed between the heat generator 54 and the heat radiator 58 and including a plurality of linear structures 12 of carbon atoms and a filling layer 14 formed of a thermoplastic resin and disposed between the plurality of linear structures 12.

Chip-last embedded interconnect structures and methods of making the same

The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.

Semiconductor Device and Method of Forming a Thermally Reinforced Semiconductor Die

A semiconductor device includes a substrate with conductive traces. A semiconductor die is mounted with an active surface oriented toward the substrate. An underfill material is deposited between the semiconductor die and substrate. A recess is formed in an interior portion of the semiconductor die that extends from a back surface of the semiconductor die opposite the active surface partially through the semiconductor die such that a peripheral portion of the back surface of the semiconductor die is offset with respect to a depth of the recess. A thermal interface material (TIM) is deposited over the semiconductor die and into the recess such that the TIM in the recess is laterally supported by the peripheral portion of the semiconductor die to reduce flow of the TIM away from the semiconductor die. A heat spreader including protrusions is mounted over the semiconductor die and contacts the TIM.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate. A heat radiator is disposed on the heat conductive member. The heat conductive member thermally connecting the semiconductor element to the heat radiator reduces the risk that electromagnetic noise may be emitted from or may be incident on the semiconductor element.

Integrated circuit packaging system with collapsed multi-integration package and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a central integrated circuit over the base substrate; mounting a side package having a side package substrate along a peripheral region of the base substrate and laterally peripheral to the central integrated circuit with the side package substrate coplanar with the central integrated circuit; and encapsulating the central integrated circuit and the side package above the base substrate with a base encapsulation to form a planar surface over the central integrated circuit and the side package facing away from the base substrate.

Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof

A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.

Semiconductor device

A semiconductor device includes a first structural body having first electrode pads; a second structural body disposed in a face-up type over the first structural body in such a way as to expose the first electrode pads, and having first connection members with at least two protrusions; and a third structural body disposed in a face-down type over the second structural body, and having second connection members with at least two protrusions, on a surface thereof facing the second structural body, wherein some of the protrusions of the second connection members are electrically connected with the exposed first electrode pads, and at least one of remaining protrusions of the second connection members is electrically connected with the first connection members.

Stacked semiconductor package

A stacked semiconductor package includes a substrate having an upper surface and a lower surface, and divided into a first region and a second region that adjoins the first region; a support member formed in the second region on the upper surface of the substrate; and a semiconductor chip module including a plurality of semiconductor chips each of which has bonding pads near one edge of a first surface thereof and which are stacked on the support member in a step-like shape such that their bonding pads face the first region and are bent such that the bonding pads are electrically connected with the substrate.

Memory module in a package

A microelectronic package can include a substrate having first and second opposed surfaces, at least two pairs of microelectronic elements, and a plurality of terminals exposed at the second surface. Each pair of microelectronic elements can include an upper microelectronic element and a lower microelectronic element. The pairs of microelectronic elements can be fully spaced apart from one another in a horizontal direction parallel to the first surface of the substrate. Each lower microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. A surface of each of the upper microelectronic elements can at least partially overlie a rear surface of the lower microelectronic element in its pair. The microelectronic package can also include electrical connections extending from at least some of the contacts of each lower microelectronic element to at least some of the terminals.

Multiple die in a face down package

A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements.

Package-on-package structures

Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.

Thermally Enhanced Structure for Multi-Chip Device

A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.

System in package and method of fabricating same

An assembly has at least one integrated circuit (IC) die fixed in a medium. The assembly has a redistribution layer over the IC die. The redistribution layer has conductors connecting first pads on active faces of the IC die to second pads at an exposed surface of the assembly. A die unit is provided over the IC die. The die unit has a bottom die interconnected to a package substrate. Respective portions of the redistribution layer corresponding to each of the at least one IC die partially underlie the bottom die, and extend beyond the bottom die. The package substrate has contacts connected to the ones of the second pads corresponding to the at least one IC die.

Multi-Chip and Multi-Substrate Reconstitution Based Packaging

Embodiments for multi-chip and multi-substrate reconstitution based packaging are provided. Example packages are formed using substrates from a reconstitution. substrate panel or strip. The reconstitution substrate panel or strip may include known good substrates of same or different material types and/or same of different layer counts and sizes. As such, different combinations of reconstitution substrates and chips can be used within the same package, thereby allowing substrate customization according to semiconductor chip block(s) and types contained in the package.

Integrated circuit packaging system with encapsulation and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; forming a base encapsulation, having a base encapsulation top side, on the base substrate and around the base integrated circuit; forming a base conductive via, having a base via head, through the base encapsulation and attached to the base substrate adjacent to the base integrated circuit, the base via head exposed from and coplanar with the base encapsulation top side; mounting an interposer structure over the base encapsulation with the interposer structure connected to the base via head; and forming an upper encapsulation on the base encapsulation top side and partially surrounding the interposer structure with a side of the interposer structure facing away from the base encapsulation exposed.

Stub minimization for wirebond assemblies without windows

A microelectronic assembly can include a circuit panel having first and second surfaces and panel contacts at each surface, and first and second microelectronic packages having terminals mounted to the panel contacts at the first and second surfaces, respectively. The circuit panel can electrically interconnect terminals of the first package with corresponding terminals of the second package. Each package can include a substrate having first and second surfaces, a microelectronic element, conductive structure extending above a front face of the microelectronic element, and parallel columns of terminals at the second surface. The terminals of each package can include first terminals in a central region of the respective second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the respective microelectronic element. Each central region can have a width within three and one-half times a minimum pitch between adjacent terminals.

Electronic device

An electronic device includes: a first plate; a wiring board arranged on the first plate and configured to have a plurality of first terminals on a surface opposite to a surface facing the first plate; an electronic component arranged above the wiring board and configured to have a plurality of second terminals on a surface facing the wiring board; a connecting unit arranged between the wiring board and the electronic component and configured to electrically couple the first terminals and the second terminals; a second plate arranged on the electronic component; a fixing unit arranged in an area outside of an area where the electronic component is placed and configured to pressurize the first plate and the second plate; and a pressing unit arranged below the area where the electronic component is placed and configured to press the wiring board toward the electronic component.

Multiple die stacking for two or more die

A microelectronic package can include a substrate having first and second opposed surfaces, and first and second microelectronic elements having front surfaces facing the first surface. The substrate can have a plurality of substrate contacts at the first surface and a plurality of terminals at the second surface. Each microelectronic element can have a plurality of element contacts at the front surface thereof. The element contacts can be joined with corresponding ones of the substrate contacts. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto. The element contacts of the first microelectronic element can be arranged in an area array and are flip-chip bonded with a first set of the substrate contacts. The element contacts of the second microelectronic element can be joined with a second set of the substrate contacts by conductive masses.

System in package process flow

A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.

Integrated circuit packaging system with conductive pillars and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system including: providing a package carrier; mounting an integrated circuit to the package carrier; mounting a circuit interposer above the integrated circuit; mounting a mounting integrated circuit above the circuit interposer; forming a conductive pillar to the circuit interposer adjacent to the mounting integrated circuit; connecting the circuit interposer to the package carrier; and forming an encapsulation on the package carrier.

Semiconductor Package with Conductive Heat Spreader

A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.

Molded interposer package and method for fabricating the same

The invention provides a molded interposer package and a method for fabricating the same. The molded interposer package includes a plurality of metal studs. A molding material encapsulates the metal studs leaving the bottom surfaces of the metal studs exposed. A first chip is disposed on the molding material, connecting to the top surfaces of the metal studs. A plurality of solder balls connects and contacts to the bottom surfaces of the metal studs.

Semiconductor Interposer Having a Cavity for Intra-Interposer Die

A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor interposer is situated over the substrate. An intra-interposer die is disposed within the cavity of the semiconductor interposer. A thermally conductive adhesive is disposed within the cavity and contacts the intra-interposer die. Additionally, a top die is situated over the semiconductor interposer. In one implementation, the semiconductor interposer is a silicon interposer. In another implementation, the semiconductor interposer is flip-chip mounted to the substrate such that the intra-interposer die disposed within the cavity faces the substrate. In yet another implementation, the cavity in the semiconductor interposer may extend from a top surface of the semiconductor interposer to a bottom surface of the semiconductor interposer and a thermal interface material may be disposed between the intra-interposer die and the substrate.

Methods and Apparatus for Thinner Package on Package Structures

Methods and apparatus for thinner package on package (“PoP”) structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate and a plurality of package on package connectors extending from a bottom surface; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface; wherein at least the second substrate is formed of a plurality of layers of laminated dielectric and conductors. In another embodiment a cavity is formed on the bottom surface of the first substrate and a portion of the another integrated circuit extends partially into the cavity. Methods for making the PoP structures are disclosed.

Integrated circuit package assembly and method of forming the same

An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package providing electrical signal connections between the first integrated circuit package and the second integrated circuit package. At least one support structure is disposed between the first integrated circuit package and the second integrated circuit package to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package without providing electrical signal connections.

Semiconductor package

A semiconductor package includes a substrate including a mounting surface having a plurality of ground pads, a semiconductor chip disposed on the mounting surface, a conductive connection part connected to at least one of the plurality of ground pads and having a greater width at a center than at an end, a molding member exposing a top surface of the conductive connection part while wrapping the mounting surface, the conductive connection part and the semiconductor chip, and a heat slug disposed on the molding member and connected to the top surface of the conductive connection part.

Package-on-package type semiconductor packages and methods for fabricating the same

A method of forming a semiconductor package may include providing a first package including a first semiconductor chip mounted on a first package substrate having a via-hole and molded by a first mold layer, providing a second package including a second semiconductor chip mounted on a second package substrate having a connection pad and molded by a second mold layer, stacking the first package on the second package to vertically align the via-hole with the connection pad, forming a through-hole penetrating the first and second packages and exposing the connection pad, and forming an electrical connection part in the through-hole. The electrical connection part may electrically connect the first package and the second package to each other.

Semiconductor package having heat spreader and method of forming the same

A semiconductor chip and a first heat dissipation pattern are mounted on a substrate. The first heat dissipation pattern has an opening therein and exposes the semiconductor chip therethrough. A second heat dissipation pattern including a thermal interface material (TIM) is interposed between a side surface of the semiconductor chip and the first heat dissipation pattern.

Semiconductor Packages with Integrated Heat Spreaders

One implementation of present disclosure includes a semiconductor package stack. The semiconductor package stack includes an upper package coupled to a lower package by a plurality of solder balls. The semiconductor package stack also includes a lower active die situated in a lower package substrate in the lower package. The lower active die is thermally coupled to a heat spreader in the upper package by a thermal interface material. An upper active die is situated in an upper package substrate in the upper package, the upper package substrate being situated over the heat spreader. The thermal interface material can include an array of aligned carbon nanotubes within a filler material. The heat spreader can include at least one layer of metal or metal alloy. Furthermore, the heat spreader can be connected to ground or a DC voltage source. The plurality of solder balls can be situated under the heat spreader.

Wiring substrate and method of manufacturing the same

There is provided a wiring substrate. The wiring substrate includes: an insulating layer; first electrode pads having first exposed surfaces, the first exposed surfaces being exposed from the insulating layer; and second electrode pads having second exposed surfaces, the second exposed surfaces being exposed from the insulating layer. There is a level difference between the first exposed surfaces and the second exposed surfaces.

Device

A semiconductor device includes a wiring board, a first semiconductor chip mounted on the wiring board via a first adhesive member, and second semiconductor chip stacked on the first semiconductor chip via a second adhesive member. The first adhesive member is a die attach film having an adhesive layer formed on both surfaces of an insulating base, and the second adhesive member is an adhesive paste.

Chip package and method for forming the same

An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

Package-on-package assembly with wire bond vias

A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer.

Electrical module for being received by automatic placement machines by means of generating a vacuum

The invention relates to an electrical module ( 100 ) for being received by automatic placement machines by means of generating a vacuum, comprising a carrier substrate ( 10 ), at least one component ( 20, 21 ) disposed on the carrier substrate ( 10 ), and a cover element ( 30 ) disposed above the at least one component ( 20, 21 ). A fixing component ( 40 ) by which the cover element ( 30 ) is attached to the at least one component ( 21 ) is disposed between the cover element ( 30 ) and the at least one component ( 21 ). The cover element can be implemented as a dimensionally stable, flat film by means of which it is possible to suction the module by means of vacuum for a placement method, and to place said module at a position on a circuit board.

Microelectronic package having direct contact heat spreader and method of manufacturing same

A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die.

Heatsink attachment module

An assembly process for a heatsink attachment module for a chip packaging apparatus is provided and includes attaching a semiconductor chip to a substrate to form a module subassembly, placing a load frame and shim in a fixture, dispensing adhesive to the load frame and loadably placing the module subassembly chip face down in the fixture.

Integrated heat spreader that maximizes heat transfer from a multi-chip package

In at least some embodiments, an electronic package to maximize heat transfer comprises a plurality of components on a substrate. A stiffener plate is installed over the components. The stiffener plate has openings to expose the components. A plurality of individual integrated heat spreaders are installed within the openings over the components. A first thermal interface material layer (TIM 1 ) is deposited between the components and the plurality of individual integrated heat spreaders. In at least some embodiments, the thickness of the TIM 1 is minimized for the components.

Interface Substrate with Interposer

An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided.

Multi-Chip Module with Multiple Interposers

A Multi-Chip Module is presented herein that comprises a package substrate, at least two integrated circuit devices, each of which is electrically coupled to the package substrate, and an interposer. Formed in the interposer are electrical connections which are predominantly horizontal interconnects. The first interposer is arranged to electrically couple the two integrated circuit devices to each other. Methods for manufacturing a Multi-Chip Module are also presented herein.

Stacked die power converter

A stacked die power converter package includes a lead frame including a die pad and a plurality of package pins, a first die including a first power transistor switch (first power transistor) attached to the die pad, and a first metal clip attached to one side of the first die. The first metal clip is coupled to at least one package pin. A second die including a second power transistor switch (second power transistor) is attached to another side on the first metal clip. A controller is provided by a controller die attached to a non-conductive layer on the second metal clip on one side of the second die.

Method of manufacturing semiconductor device

In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

Semiconductor Package with Heat Spreader

A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.

Package process and package structure

A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the sidewalls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the sidewalls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices.

Method and system for thermomechanically decoupling heatsink

A method of mounting a heat sink includes providing a heat sink having a plurality of mounting points, and attaching a plurality of mounting members to the heat sink at the plurality of mounting points, respectively, at least one of a combination of a mounting point of the mounting points and a mounting member of the mounting members being configured so as to have a stiffness in a thermally-induced expansion direction of the heat sink at the respective mounting point which is less than a stiffness in an other direction at the respective mounting point.

Matrix Lid Heatspreader for Flip Chip Package

A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array () designed for direct attachment to an array of integrated circuit die () by including a thermal interface adhesion layer () to each die () and encapsulating the attached heat spreader lid array () and array of integrated circuit die () with mold compound () except for planar upper lid surfaces of the heat spreader lids (). 110-. (canceled)11. A semiconductor package , comprising:a substrate having first and second surfaces;a die having first and second surfaces, where the first surface of the die is flip-chip bonded to the first surface of the substrate;a compressed, laterally expansive, thermally conductive interface layer formed to cover the second surface of the die; anda heat spreader lid comprising an exposed heat dissipation surface layer and a plurality of connection spars extending laterally from the heat dissipation surface layer, where the heat dissipation surface layer contacts the compressed, laterally expansive, thermally conductive interface layer and is positioned apart from the substrate to define an encapsulation molding region in which encapsulation mold compound material is located to permanently attach the substrate, die, and heat spreader lid.12. The semiconductor package of claim 11 , where the plurality of connection spars extend laterally to be co-planar with the exposed heat dissipation surface layer.13. The semiconductor package of claim 11 , where the plurality of connection spars extend laterally as downset connection spars that are not co-planar with the exposed heat dissipation surface layer.14. The semiconductor package of claim 11 , where the heat spreader lid is formed with a thermally conductive layer of copper claim 11 , nickel or an alloy thereof.15. The semiconductor package of claim 11 , where the exposed heat dissipation surface layer has a thermal contact surface that is at ...

Foam composite

Devices and methods disclosed herein can include a conductive foam having pores disposed within the conductive foam. The conductive foam can be compressible between an uncompressed thickness and a compressed thickness. The compressed thickness can be ninety-five percent or less of the uncompressed thickness. In one example, a filler can be disposed in the pores of the conductive foam. The filler can include a first thermal conductivity. The first thermal conductivity can be greater than a thermal conductivity of air.

SEMICONDUCTOR STRUCTURE AND ASSOCIATED METHOD FOR MANUFACTURING THE SAME

A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces beneath and between the dies; disposing a temporary carrier over the dies; thinning a thickness of the semiconductor substrate; performing back side metallization upon the thinned semiconductor substrate; removing the temporary carrier; and attaching a plate over the dies. An associated semiconductor structure is also disclosed. 1. A method for manufacturing a semiconductor structure , comprising:providing a semiconductor substrate having a plurality of dies thereon;dispensing a first underfill material and a molding compound to fill spaces beneath and between the dies;disposing a temporary carrier over the dies;thinning a thickness of the semiconductor substrate;performing back side metallization upon the thinned semiconductor substrate;removing the temporary carrier;attaching a plate over the dies;sawing the semiconductor substrate and the plate to obtain a singulated semiconductor structure;mounting the singulated semiconductor structure on a carrier; anddispensing a second underfill material between the singulated semiconductor structure and the carrier.2. The method of claim 1 , further comprising thinning the molding compound to expose the dies.3. (canceled)4. The method of claim 1 , wherein the attaching of the plate over the dies comprises attaching a metal plate over the dies.5. The method of claim 4 , wherein the attaching of the metal plate over the dies comprises attaching a Cu plate over the dies.6. The method of claim 4 , wherein the attaching of the metal plate over the dies comprises attaching a stainless steel plate over the dies.7. The method of claim 1 , wherein the attaching of the plate over the dies comprises attaching a ceramic plate over the dies.8. The method of claim 1 , wherein the attaching of the plate over the ...

SCALABLE PACKAGE ARCHITECTURE AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS

Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed. 111-. (canceled)12. A method for fabricating an integrated circuit (IC) assembly , comprising:providing a package substrate having a first side and a second side disposed opposite to the first side;coupling an active side of a first die with the first side of the package substrate, the first die including an inactive side disposed opposite to the active side and one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die; andforming a mold compound on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side;mounting ...

Semiconductor package

A semiconductor package includes a first die including a signal region and a peripheral region bordering the signal region and having first vias in the peripheral region, a second die stacked on the first die and having second vias at positions corresponding to the first vias in the peripheral region, and first connection terminals between the first die and the second die that are configured to connect the second vias to the first vias, respectively. The peripheral region includes first regions and second regions configured to transmit different signals, which are alternately arranged in a first direction. The first vias are arranged in at least two rows along a second direction intersecting the first direction in each of the first and second regions.

Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate

A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first interconnect structure over the substrate;disposing a first semiconductor die over the first interconnect structure;disposing the substrate over a carrier with the first semiconductor die oriented away from the carrier;depositing an encapsulant over the carrier, substrate, and first semiconductor die;forming a second interconnect structure over the encapsulant and semiconductor die; andremoving the substrate to expose the first interconnect structure after forming the second interconnect structure.2. The method of claim 1 , further including forming a conductive column over the first interconnect structure.3. The method of claim 2 , wherein the conductive column extends from the first interconnect structure to the second interconnect structure ...

3D SEMICONDUCTOR DEVICE AND STRUCTURE

A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written. 1. A 3D semiconductor device , the device comprising: 'wherein connections between said first transistors and first metal layer comprise said first contact plugs;', 'a first level comprising a single crystal layer, a plurality of first transistors, a plurality of first contact plugs and a first metal layer,'}memory control circuits comprising a portion of said connections and said plurality of first transistors;a second level overlaying said single crystal layer, said second level comprising a plurality of second transistors;a third level overlaying said second level, said third level comprising a plurality of third transistors;a second metal layer overlaying said third level; and wherein said second transistors are aligned to said first transistors with less than 40 nm alignment error,', 'wherein said third metal layer comprises bit lines,', 'wherein said second level comprises a plurality of first memory cells,', 'wherein said third level comprises a plurality of second memory cells,', 'wherein one of said second transistors is at least partially self-aligned to at least one of said third ...

SEMICONDUCTOR DEVICE

Reliability of a semiconductor device is improved. The semiconductor device PKG includes a wiring substrate SUB, a semiconductor chip CHP and a capacitor CDC mounted on the upper surface of the wiring substrate SUB, and a lid LD formed of a metallic plate covering the semiconductor chip CHP and the wiring substrate SUB. The semiconductor chip CHP is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP, is disposed in the cut off portion provided in the lid LD, and is exposed from the lid LD. 1. A semiconductor device comprising:a wiring substrate having a first main surface, a second main surface opposite the first main surface, and a first side extending in a first direction;a semiconductor chip having a front surface, a rear surface opposite the front surface and mounted on the first main surface of the wiring substrate;a first capacitor mounted on the first main surface of the wiring substrate except an area on which the semiconductor mounted; anda lid disposed on the rear surface of the semiconductor chip via a first adhesive layer and covering over the front surface of the wiring substrate,wherein the lid includes a second side extending in a first direction along the first side of the wiring substrate, andwherein the first capacitor is disposed in a cut-out portion formed on the second side of the lid.2. The semiconductor device according to claim 1 ,wherein a thickness of the semiconductor chip is thinner than a thickness of the first capacitor in a thickness direction of the wiring substrate, andwherein the first capacitor is exposed from the lid.3. The semiconductor device according to claim 2 ,Wherein the wiring substrate includes a first external electrode formed on the second main surface,wherein the semiconductor chip includes a front surface, a rear surface opposite the front surface and a first electrode arranged on the front surface,wherein the first capacitor ...

Heat Spreading Device and Method

In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die.

Semiconductor Package, and a Method for Forming a Semiconductor Package

A semiconductor package includes a semiconductor die arranged on a substrate. The semiconductor package includes a stiffener structure arranged on the substrate. The stiffener structure is spaced at a distance from the semiconductor die. The stiffener structure includes a molding compound material.

Platform with thermally stable wireless interconnects

Embodiments of the invention may include a packaged device that includes thermally stable radio frequency integrated circuits (RFICs). In one embodiment the packaged device may include an integrated circuit chip mounted to a package substrate. According to an embodiment, the package substrate may have conductive lines that communicatively couple the integrated circuit chip to one or more external components. One of the external components may be an RFIC module. The RFIC module may comprise an RFIC and an antenna. Additional embodiments may also include a packaged device that includes a plurality of cooling spots formed into the package substrate. In an embodiment the cooling spots may be formed proximate to interconnect lines the communicatively couple the integrated circuit chip to the RFIC.

Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same

An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs. 1. A package comprising: a first device die;', 'a first molding compound extending along sidewalls of the first device die; and', 'a first through intervia (TIV) extending through the first molding compound;, 'a first fan-out tier comprisingone or more first fan-out redistribution layers (RDLs) over the first fan-out tier and bonded to the first device die;a second fan-out tier over the one or more first fan-out RDLs, wherein the second fan-out tier comprises a second device die bonded to the one or more first fan-out RDLs, wherein the one or more first fan-out RDLs electrically connects the first device die to the second device die;one or more second fan-out RDLs on an opposing side of the first fan-out tier from the one or more first fan-out RDLs, wherein the first TIV electrically connects the one or more first fan-out RDLs to the one or more second fan-out RDLs; anda plurality of external connectors at least partially disposed in the one or more second fan-out RDLs, wherein the plurality of external connectors are further disposed on conductive features in the one or more second fan ...

Semiconductor chip and stacked type semiconductor package having the same

The disclosure relates to a semiconductor chip and a stacked type semiconductor package having the same. The semiconductor chip includes: a semiconductor chip body having a first surface formed with a plurality of bonding pads and a second surface which is opposite to the first surface, a plurality of first and second through electrodes that pass through the semiconductor chip body and one ends thereof are electrically connected to the bonding pads, an insulating layer formed over the second surface of the semiconductor chip body such that the other ends of the first and second through electrodes are not covered by the insulating layer, and a first heat spreading layer formed over the insulating layer.

Method for forming Board Assembly with Chemical Vapor Deposition Diamond (CVDD) Windows for Thermal Transport

A method for forming a board assembly includes identifying a location of a hot-spot on a semiconductor die and cutting an opening in a circuit board corresponding to the location of the identified hot-spot. A Chemical Vapor Deposition Diamond (CVDD) window is inserted into the opening. A layer of thermally conductive paste is applied over the CVDD window. The semiconductor die is placed over the layer of thermally conductive paste such that the CVDD window underlies the hot-spot and such that a surface of the semiconductor die is in direct contact with the layer of thermally conductive paste. 1. A method for forming a board assembly comprising:identifying a location of a hot-spot on a semiconductor die;cutting an opening in a circuit board corresponding to the location of the identified hot-spot;inserting a Chemical Vapor Deposition Diamond (CVDD) window into the opening;applying a layer of thermally conductive paste over the CVDD window; andplacing the semiconductor die over the layer of thermally conductive paste such that the CVDD window underlies the hot-spot and such that a surface of the semiconductor die is in direct contact with the layer of thermally conductive paste.2. The method of further comprising: attaching leads to the semiconductor die and the circuit board to electrically couple the die to the first circuit board.3. The method of further comprising: forming a dam around the semiconductor die and attaching an additional circuit board to the dam so as to enclose the semiconductor die within the dam and between the circuit board and the additional circuit board.4. The method of further comprising: dispensing filler material within the enclosure.5. The method of claim 4 , wherein the filler material comprises diamond paste.6. The method of claim 1 , wherein the CVDD window has a thickness that is the same as the thickness of the circuit board.7. The method of claim 1 , wherein the CVDD window has a thickness that is greater than a thickness of the ...

Electronic apparatus and method for fabricating the same

An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

SEMICONDUCTOR DEVICE

This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate. 1a wiring substrate having a first insulating layer which has a first main surface and a second main surface opposite the first main surface, a plurality of through-holes which penetrate the first main surface to the second main surface of the first insulating layer, a plurality of wirings being formed over the first main surface of the first insulating layer and electrically connected to the plurality of through-holes, respectively, a solder resist layer formed over the first main surface of the first insulating layer such that the solder resist layer covers a part arranged on the first main surface of each of the plurality of through-holes; anda semiconductor chip having an obverse surface over which a plurality of bump electrodes are formed and a reverse surface opposite the obverse surface and mounted over the first main surface of the first insulating layer of the wiring substrate such that the obverse surface thereof faces to the first main surface of the first insulating layer of the wiring substrate,wherein a plurality of openings are formed in the solder resist layer such that a part of each of the plurality of wirings is exposed from each of the plurality of openings, and therefore, the part exposed from each of the plurality of openings of the plurality of wirings is provided as an ...

Semiconductor Device and Method of Forming PoP Semiconductor Device with RDL Over Top Package

A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.

SEMICONDUCTOR PACKAGE WITH CONDUCTIVE CLIP

A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can. 117-. (canceled)18. A method comprising:forming at least one terminal for a semiconductor package;forming a dielectric body to electrically insulate said at least one terminal from a conductive clip of said semiconductor package;connecting a power electrode of a power semiconductor device to said conductive clip.19. The method of further comprising depositing a solder resist over at least a portion of said at least one terminal.20. The method of further comprising forming a conductive pad for said semiconductor package.21. The method of further comprising forming a track to connect said conductive pad to said at least one terminal.22. The method of claim 18 , wherein said conductive clip is plated with either gold or silver.23. The method of claim 18 , wherein said dielectric body comprises polymer.24. The method of claim 18 , wherein said dielectric body comprises dielectric particles in an organic base.25. The method of claim 24 , wherein said organic base comprises one of epoxy claim 24 , acrylate claim 24 , polyimide and organopolysiloxane.26. The method of claim 24 , wherein said dielectric particles comprise a metal oxide.27. The method of claim 26 , wherein said metal oxide is alumina. This application is a continuation of U.S. application Ser. No. 11/799,140, filed May 1, 2007, entitled Semiconductor Package which is a division of U.S. application Ser. No. 11/405,825, filed Apr. 18, 2006, entitled Semiconductor Package which is based on and claims benefit of U.S. Provisional Application No. 60/674,162, filed on Apr. 21, 2005, entitled Semiconductor Package, to which a claim of priority is hereby made and the disclosure of which is incorporated by reference.The present invention relates to semiconductor packages ...

Thermal transfer structures for semiconductor die assemblies

Several embodiments of the present technology are described with reference to a semiconductor die assembly and processes for manufacturing the assembly. In some embodiments of the present technology, a semiconductor die assembly includes a stack of semiconductor dies attached to a thermal transfer structure (also known as a “heat spreader,” “lid,” or “thermal lid”). The thermal transfer structure conducts heat away from the stack of semiconductor dies. Additionally, the assembly can include molded walls fabricated with molding material to support the thermal transfer structure.

Thermally enhanced package to reduce thermal interaction between dies

A method of reducing heat flow between IC chips and the resulting device are provided. Embodiments include attaching plural IC chips to an upper surface of a substrate; forming a lid over the IC chips; and forming a slit through the lid at a boundary between adjacent IC chips.

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A manufacturing method of a package structure is described. The method includes at least the following steps. A carrier is provided. A semiconductor die and a sacrificial structure are disposed on the carrier. The semiconductor die is electrically connected to the bonding pads on the sacrificial structure through a plurality of conductive wires. As encapsulant is formed on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires. The carrier is debonded, and at least a portion of the sacrificial structure is removed through a thinning process. A redistribution layer is formed on the semiconductor die and the encapsulant. The redistribution layer is electrically connected to the semiconductor die through the conductive wires. 1. A manufacturing method of a package structure , comprising:providing a carrier,disposing a semiconductor die and at least one sacrificial structure on the carrier;electrically connecting the semiconductor die to bonding pads on the sacrificial structure through a plurality of conductive wires;forming an encapsulant on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires;debonding the carrier,removing at least a portion of the sacrificial structure through a thinning process; andforming a redistribution layer on the semiconductor die and the encapsulant, the redistribution layer is electrically connected to the semiconductor die through the conductive wires.2. The manufacturing method of a package structure according to claim 1 , wherein the sacrificial structure is disposed on the carrier claim 1 , and the semiconductor die is disposed on the sacrificial structure.3. The manufacturing method of a package structure according to claim 2 , wherein a width of the sacrificial structure is greater than a width of the semiconductor die.4. The manufacturing method of a package structure according to claim 2 , wherein the redistribution layer is formed on the ...

Semiconductor package with dual sides of metal routing

A method includes forming a redistribution structure over a carrier, the redistribution structure having conductive features on a surface of the redistribution structure distal the carrier; forming a conductive pillar over the surface of the redistribution structure; attaching a die to the surface of the redistribution structure adjacent to the conductive pillar, where die connectors of the die are electrically coupled to the conductive features of the redistribution structure; and attaching a pre-made substrate to the conductive pillar through a conductive joint, where the conductive joint is on the conductive pillar and comprises a different material from the conductive pillar, where the conductive joint and the conductive pillar electrically couple the redistribution structure to the pre-made substrate.

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure. 1. A package structure , comprising:at least one semiconductor die;a redistribution circuit structure, located on and electrically connected to the at least one semiconductor die; andfirst reinforcement structures, embedded in the redistribution circuit structure,wherein a shape of the package structure comprises a polygonal shape on a vertical projection along a stacking direction of the at least one semiconductor die and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure.2. The package structure of claim 1 , wherein the redistribution circuit structure comprises conductive traces claim 1 , and each conductive trace comprises a first contact pad claim 1 , a second contact pad and a conductive structure connecting the first contact pad and the second contact pad claim 1 , wherein a width of the first reinforcement structures is greater than a width of the conductive structures.3. The package structure of claim 1 , wherein the first reinforcement structures are further located on and extended along diagonal lines of the at least one semiconductor die on the vertical projection.4. The package structure ...

Multi-metal package stiffener

A semiconductor package system includes a semiconductor package including at least one semiconductor device having a first side and a second side and a substrate having a first side and a second side. The second side of the at least one semiconductor device is positioned on the first side of the substrate. At least one stiffener element is provided on the semiconductor package. The at least one stiffener element includes at least two metal elements having different coefficients of thermal expansion joined together.

CHIP PACKAGE WITH LID

Structures and formation methods of a chip package are provided. The chip package includes a substrate and a semiconductor die over the substrate. The chip package also includes a lid covering a top surface of the semiconductor die. The lid has a first support structure and a second support structure, and the first support structure and the second support structure are positioned at respective corner portions of the substrate. An opening penetrates through the lid to expose a space containing the semiconductor die, and the lid has a side edge extending from an edge of the first support structure to an edge of the second support structure. 1. A chip package , comprising:a substrate;a semiconductor die over the substrate; anda lid covering a top surface of the semiconductor die, wherein the lid has a first support structure and a second support structure, the first support structure and the second support structure are positioned at respective corner portions of the substrate, an opening penetrates through the lid to expose a space containing the semiconductor die, and the lid has a side edge extending from an edge of the first support structure to an edge of the second support structure.2. The chip package as claimed in claim 1 , wherein at least one of the first support structure and the second support structure has a sidewall surface with an L-shaped profile.3. The chip package as claimed in claim 1 , wherein one of the support structures has a base portion and a side portion claim 1 , a bottom surface of the base portion is substantially parallel to a top surface of the substrate claim 1 , and the side portion is in direct contact with the base portion and an upper plate of the lid.4. The chip package as claimed in claim 3 , wherein the side portion has a slanted sidewall extending from the base portion to the upper plate of the lid.5. The chip package as claimed in claim 1 , wherein the first support structure has a first side and a second side opposite to the ...

Electronic module and electronic device

An electronic module includes: a plurality of heat generating members provided over a first surface of a board; a frame joined to the first surface of the board and provided between the plurality of heat generating members that are arranged; and a lid configured to cover the first surface of the board and thermally coupled to each of the plurality of heat generating members, the frame being a grid-shaped frame or a mesh-shaped frame.

Substrate design for semiconductor packages and method of forming same

A device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity.

METHODS AND APPARATUSES FOR PACKAGING AN ULTRASOUND-ON-A-CHIP

Described herein are methods and apparatuses for packaging an ultrasound-on-a-chip. An ultrasound-on-a-chip may be coupled to a redistribution layer and to an interposer layer. Encapsulation may encapsulate the ultrasound-on-a-chip device and first metal pillars may extend through the encapsulation and electrically couple to the redistribution layer. Second metal pillars may extend through the interposer layer. The interposer layer may include aluminum nitride. The first metal pillars may be electrically coupled to the second metal pillars. A printed circuit board may be coupled to the interposer layer. 1. An apparatus comprising:an ultrasound-on-a-chip comprising a top surface and a bottom surface;an interposer layer comprising a top surface and a bottom surface; anda redistribution layer; the top surface of the ultrasound-on-a-chip device is coupled to the redistribution layer; and', 'the bottom surface of the ultrasound-on-a chip device is coupled to the top surface of the interposer layer., 'wherein2. The apparatus of claim 1 , further comprising:encapsulation encapsulating the ultrasound-on-a-chip device; andfirst metal pillars extending through the encapsulation and electrically coupling to the redistribution layer.3. The apparatus of claim 2 , wherein the interposer layer comprises second metal pillars extending through the interposer layer.4. The apparatus of claim 3 , wherein the interposer layer comprises aluminum nitride.5. The apparatus of claim 3 , wherein the first metal pillars are electrically coupled to the second metal pillars.6. The apparatus of claim 3 , wherein the first metal pillars are aligned with the second metal pillars.7. The apparatus of claim 3 , wherein solder balls electrically couple the first metal pillars to the second metal pillars.8. The apparatus of claim 2 , further comprising a printed circuit board coupled to the bottom surface of the interposer layer.9. The apparatus of claim 3 , further comprising a printed circuit board ...

METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES

Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate. 1. A semiconductor structure , comprising:a substrate having an insulating layer thereon, the substrate having a perimeter, and the substrate comprising silicon;a metallization structure on the insulating layer, the metallization structure comprising conductive routing in a dielectric material stack;a first metal guard ring in the dielectric material stack and continuous around the conductive routing;a second metal guard ring in the dielectric material stack and continuous around the first metal guard ring;a plurality of staggered mini guard rings between the first metal guard ring and the second metal guard ring; anda metal-free region of the dielectric material stack surrounding the second metal guard ring, the metal-free region adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.2. The semiconductor structure of claim 1 , wherein at least one of the first metal guard ring or the second metal guard ring provides a hermetic seal for the metallization structure.3. The semiconductor structure of claim 1 , further comprising:a metal feature between the first metal ...