CHIP PACKAGE

An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device disposed at the first surface; a protection layer disposed on the second surface of the substrate, wherein the protection layer has an opening; a conducting bump disposed on the second surface of the substrate and filled in the opening; a conducting layer disposed between the protection layer and the substrate, wherein the conducting layer electrically connects the optoelectronic device to the conducting bump; and a light shielding layer disposed on the protection layer, wherein the light shielding layer does not contact with the conducting bump. 1. A chip package , comprising:a substrate having a first surface and a second surface;an optoelectronic device disposed at the first surface;a protection layer disposed on the second surface of the substrate, wherein the protection layer has an opening;a conducting bump disposed on the second surface of the substrate and filled in the opening;a conducting layer disposed between the protection layer and the substrate, wherein the conducting layer electrically connects the optoelectronic device to the conducting bump; anda light shielding layer disposed on the protection layer, wherein the light shielding layer does not contact with the conducting bump.2. The chip package as claimed in claim 1 , further comprising a through substrate conducting structure comprising:a through-hole extending from the second surface towards the first surface; andan insulating layer formed on a sidewall of the through-hole and extending on the second surface of the substrate,wherein the conducting layer extends on the insulating layer in the through-hole.3. The chip package as claimed in claim 2 , wherein a width of the through-hole increases along a direction from the second surface towards the first surface.4. The chip package as claimed in claim 2 , wherein at least a portion of the through- ...

CHIP PACKAGE AND METHOD FOR FORMING THE SAME

Embodiments of the present invention provide a chip package including: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface; and a conducting pad structure disposed in the dielectric layer and electrically connected to the device region; a cover substrate disposed between the chip and the cover substrate, wherein the spacer layer, a cavity is created an surrounded by the chip and the cover substrate on the device region, and the spacer layer is in direct contact with the chip without any adhesion glue disposed between the chip and the spacer layer. 1. A chip package , comprising: a semiconductor substrate having a first surface and a second surface;', 'a device region formed in the semiconductor substrate;', 'a dielectric layer disposed on the first surface; and', 'a conducting pad structure disposed in the dielectric layer and electrically connected to the device region;, 'a chip, comprisinga cover substrate disposed on the chip; anda spacer layer disposed between the chip and the cover substrate, wherein a plurality of cavities is created and surrounded by the spacer layer, the chip and the cover substrate on the device region, and wherein the spacer layer directly contacts the chip, and no adhesion glue is disposed between the chip and the spacer layer.2. The chip package as claimed in claim 1 , wherein the cover substrate is a transparent substrate.3. The chip package as claimed in claim 1 , wherein the projection of the spacer layer on the first surface is located between the projection of the conducting pad structure on the first surface and the projection of the device region on the first surface.4. The chip package as claimed in claim 1 , wherein the projection of the spacer layer on the first surface does not overlap the projection of the conducting pad structure on the first surface.5. The chip package as claimed in claim 1 , wherein ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor device. The semiconductor packaged device includes a first semiconductor die having a first surface. The semiconductor packaged device also includes a dielectric material surrounding the first semiconductor die, where the dielectric material comprises a surface substantially leveled with the first surface. The semiconductor packaged device further includes a capping layer covering the first surface of the first semiconductor die and the surface of the dielectric material. An adhesivity between the capping layer and a dicing tape is lower than an adhesivity between the dielectric material and the dicing tape. 1. A semiconductor packaged device , comprising:a first semiconductor die comprising a first surface;a dielectric material surrounding the first semiconductor die, the dielectric material comprising a surface substantially leveled with the first surface; anda metal layer contacting the first surface of the first semiconductor die and covering an entirety of the surface of the dielectric material, wherein an adhesivity between the metal layer and a dicing tape is lower than an adhesivity between the dielectric material and the dicing tape.2. The semiconductor packaged device of claim 1 , further comprising a first substrate and a plurality of connectors claim 1 , wherein the first semiconductor die is bonded to the first substrate through the connectors on a second surface opposite to the first surface.3. The semiconductor packaged device of claim 2 , wherein the dielectric material further surrounds the connectors and covers the substrate.4. The semiconductor packaged device of claim 2 , wherein the first substrate comprises a plurality of through vias electrically connecting the first semiconductor die with a second substrate.5. The semiconductor packaged device of claim 1 , further comprising a second semiconductor die having a first surface leveled with the first surface of the first semiconductor die claim 1 , ...

SEMICONDUCTOR STRUCTURE AND ASSOCIATED METHOD FOR MANUFACTURING THE SAME

A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces beneath and between the dies; disposing a temporary carrier over the dies; thinning a thickness of the semiconductor substrate; performing back side metallization upon the thinned semiconductor substrate; removing the temporary carrier; and attaching a plate over the dies. An associated semiconductor structure is also disclosed. 1. A method for manufacturing a semiconductor structure , comprising:providing a semiconductor substrate having a plurality of dies thereon;dispensing a first underfill material and a molding compound to fill spaces beneath and between the dies;disposing a temporary carrier over the dies;thinning a thickness of the semiconductor substrate;performing back side metallization upon the thinned semiconductor substrate;removing the temporary carrier;attaching a plate over the dies;sawing the semiconductor substrate and the plate to obtain a singulated semiconductor structure;mounting the singulated semiconductor structure on a carrier; anddispensing a second underfill material between the singulated semiconductor structure and the carrier.2. The method of claim 1 , further comprising thinning the molding compound to expose the dies.3. (canceled)4. The method of claim 1 , wherein the attaching of the plate over the dies comprises attaching a metal plate over the dies.5. The method of claim 4 , wherein the attaching of the metal plate over the dies comprises attaching a Cu plate over the dies.6. The method of claim 4 , wherein the attaching of the metal plate over the dies comprises attaching a stainless steel plate over the dies.7. The method of claim 1 , wherein the attaching of the plate over the dies comprises attaching a ceramic plate over the dies.8. The method of claim 1 , wherein the attaching of the plate over the ...

Metallization Patterns in Semiconductor Packages and Methods of Forming the Same

An embodiment method includes encapsulating a semiconductor die in an encapsulant, planarizing the encapsulant, and depositing a polymer material on the encapsulant. The method further includes planarizing the polymer material and forming a metallization pattern on the polymer material. The metallization pattern electrically connects a die connector of the semiconductor die to a conductive feature disposed outside of the semiconductor die. 1. A package comprising:an integrated circuit die comprising a die connector;an encapsulant disposed around the integrated circuit die;a polymer material over at least a portion of the encapsulant;an impurity disposed at a top surface of the polymer material, a material of the impurity being different than the polymer material; anda conductive line over the polymer material, the conductive line electrically connecting the die connector to a conductive feature, and a portion of the encapsulant is disposed between the die connector and the conductive feature.2. The package of claim 1 , further comprising a polymer layer disposed between the conductive line and the polymer material claim 1 , the impurity is disposed at an interface between the polymer material and the polymer layer.3. The package of claim 2 , wherein the polymer layer further forms an interface with the encapsulant.4. The package of claim 2 , wherein the polymer layer covers an entire top surface of the encapsulant.5. The package of claim 1 , wherein the impurity is disposed at an interface between the conductive line and the polymer material.6. The package of claim 1 , wherein a top surface of the die connector is disposed below a top surface of the encapsulant claim 1 , the polymer material extending from the top surface of the encapsulant to the top surface of the die connector.7. The package of claim 1 , wherein the impurity comprises silicon claim 1 , aluminum claim 1 , or a combination thereof.8. A package comprising:a semiconductor die;a molding material ...

Protrusion Bump Pads for Bond-on-Trace Processing

An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion having an exposed top surface, wherein the exposed top surface is recessed from a top surface of the dielectric layer. Furthermore, the bump pad is disposed over and is electrically connected to a second portion of the conductive trace. 1. An apparatus comprising:a dielectric layer;a conductive trace in the dielectric layer, wherein the conductive trace comprises a first portion having an exposed top surface, and wherein the exposed top surface is recessed from a top surface of the dielectric layer; anda bump pad over and electrically connected to a second portion of the conductive trace.2. The apparatus of claim 1 , wherein the bump pad and the conductive trace comprise different conductive materials.3. The apparatus of claim 2 , wherein the bump pad comprises nickel or tin claim 2 , and wherein the conductive trace comprises copper.4. The apparatus of claim 1 , wherein the conductive trace is connected to a contact pad in the dielectric layer claim 1 , and wherein the apparatus further comprises a conductive pillar extending from the contact pad through the dielectric layer.5. The apparatus of further comprising:an integrated circuit chip; anda conductive bump physically coupled between the integrated circuit chip and the bump pad.6. The apparatus of claim 5 , wherein there are no conductive bumps physically coupling the integrated circuit chip to the first portion of the conductive trace.7. The apparatus of claim 1 , wherein a top surface of the bump pad is substantially level with the top surface of the dielectric layer.8. A device comprising:a substrate;a dielectric layer over the substrate;a conductive trace in the dielectric layer and comprising a first material; anda bump pad over and electrically coupled to a first portion of the conductive trace, wherein the bump pad comprises a second material ...

Semiconductor structure and manufacturing method thereof

A method of manufacturing a semiconductor structure includes providing a substrate including a redistribution layer (RDL) disposed over the substrate, disposing a first patterned mask over the RDL, disposing a first conductive material over the RDL exposed from the first patterned mask to form a first conductive pillar, removing the first patterned mask, disposing a second patterned mask over the RDL, disposing a second conductive material over the RDL exposed from the second patterned mask to form a second conductive pillar, removing the second patterned mask, disposing a first die over the first conductive pillar, and disposing a second die over the second conductive pillar. A height of the second conductive pillar is substantially greater than a height of the first conductive pillar.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a manufacturing method are provided. The semiconductor package includes a die, a dummy cube, a stress relaxation layer, an encapsulant and a redistribution structure. The dummy cube is disposed beside the die. The stress relaxation layer covers a top surface of the dummy cube. The encapsulant encapsulates the die and the dummy cube. The redistribution structure is disposed over the encapsulant and is electrically connected to the die. The stress relaxation layer is interposed between the dummy cube and the redistribution structure. 1. A semiconductor package , comprising:a die;a dummy cube, disposed beside the die;a stress relaxation layer, covering a top surface of the dummy cube;an encapsulant encapsulating the die and the dummy cube; anda redistribution structure disposed over the encapsulant and electrically connected to the die,wherein the stress relaxation layer is interposed between the dummy cube and the redistribution structure.2. The semiconductor package of claim 1 , wherein the dummy cube is electrically isolated from the redistribution structure.3. The semiconductor package of claim 1 , wherein the stress relaxation layer comprises a portion of the encapsulant.4. The semiconductor package of claim 1 , wherein the stress relaxation layer comprises a polymeric layer claim 1 , and the polymeric layer is not in physical contact with the redistribution structure.5. The semiconductor package of claim 1 , wherein the stress relaxation layer comprises a first polymeric layer and a second polymeric layer claim 1 , and a material of the first polymeric layer is different from a material of the second polymeric layer.6. The semiconductor package of claim 1 , wherein the stress relaxation layer comprises a polymeric layer extending from the top surface of the dummy cube to the redistribution structure.7. The semiconductor package of claim 6 , wherein a material of the polymeric layer comprises polyimide claim 6 , polybenzooxazole claim 6 ...

PACKAGE-ON-PACKAGE STRUCTURE WITH ORGANIC INTERPOSER

A device comprises a substrate having a die mounted on the first side of the substrate and a moldable underfill (MUF) disposed on the first side of the substrate and around the die. An interposer is mounted on the first side of the substrate, with the interposer having lands disposed on a first side of the interposer. The interposer mounted to the substrate by connectors bonded to a second side of the interposer, the connectors providing electrical connectivity between the interposer and the substrate. A package is mounted on the first side of the interposer and is electrically connected to the lands. At least one of the lands is aligned directly over the die and wherein a pitch of the connectors is different than a pitch of the lands. 1. A device comprising:a substrate having a die mounted on a first side of the substrate;a moldable underfill (MUF) disposed on the first side of the substrate and around the die;an interposer mounted on the first side of the substrate, the interposer having lands disposed on a first side of the interposer, and the interposer mounted to the substrate by connectors bonded to a second side of the interposer, the connectors providing electrical connectivity between the interposer and the substrate; anda package mounted on the first side of the interposer and electrically connected to the lands; at least one of the lands is aligned directly over the die; and', 'a pitch of the connectors is different than a pitch of the lands., 'wherein2. The device of claim 1 , wherein the connectors comprise first pillars disposed on the first side of the substrate.3. The device of claim 2 , wherein:the connectors further comprise second pillars disposed on the second side of the interposer; andeach of the first pillars is bonded to a respective one of the second pillars.4. The device of claim 3 , wherein the second pillars have a first pitch between about 200 μm and about 400 μm; the lands have a second pitch between about 350 μm and about 650 μm; and', ...

Protrusion Bump Pads for Bond-on-Trace Processing

An embodiment apparatus includes a dielectric layer in a die, a conductive trace in the dielectric layer, and a protrusion bump pad on the conductive trace. The protrusion bump pad at least partially extends over the dielectric layer, and the protrusion bump pad includes a lengthwise axis and a widthwise axis. A ratio of a first dimension of the lengthwise axis to a second dimension of the widthwise axis is about 0.8 to about 1.2 1. A method comprising:forming an outermost dielectric layer;forming a conductive trace in the outermost dielectric layer; andforming a bump pad on the conductive trace, wherein the bump pad extends higher than a top surface of the outermost dielectric layer, wherein a surface of the bump pad opposite the conductive trace is substantially level, wherein the bump pad comprises a first lengthwise axis having a first dimension and a widthwise axis having a second dimension, and wherein a ratio of the first dimension to the second dimension is about 0.8 to about 1.2.2. The method of further comprising bonding a die to the conductive trace claim 1 , wherein bonding the die comprises bonding a conductive bump of the die to the bump pad.3. The method of claim 2 , wherein bonding the die comprises disposing a second lengthwise axis of the conductive bump to be substantially parallel with the first lengthwise axis of the bump pad.4. The method of claim 2 , wherein bonding the die comprises disposing a second lengthwise axis of the conductive bump to intersect the first lengthwise axis of the bump pad.5. The method of claim 2 , wherein the conductive bump comprises a solder region claim 2 , and wherein bonding the second die comprises disposing the solder region in contact with a top surface and sidewalls of the bump pad.6. The method of claim 2 , wherein the conductive bump completely overlaps the bump pad in a top-down view.7. The method of claim 1 , wherein a top surface of the conductive trace comprises:a first portion lower than the top surface ...

Semiconductor structure and method of manufacturing the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate comprising a recess portion filled with a conductive material; a conductive trace overlying and contacting the conductive material; a conductive pillar disposed on the conductive trace and over the recess portion of the substrate; and a semiconductor chip disposed on the conductive pillar, wherein the conductive trace comprises a width W T and a thickness T T , the recess portion of the substrate comprises a width W R in the width direction of the conductive trace and a depth D R , and the ratio of W R to W T ranges from about 0.25 to about 1.8 and the ratio of D R to T T ranges from about 0.1 to about 3.

Semiconductor structure and method of manufacturing the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate comprising a recess portion filled with a conductive material; a conductive trace overlying and contacting the conductive material; a conductive pillar disposed on the conductive trace and over the recess portion of the substrate; and a semiconductor chip disposed on the conductive pillar, wherein the elastic modulus of the substrate is of about 3 to about 10 GPa at about 20 to about 30° C. and of about 1 to about 5 GPa at about 250 to about 270° C.

SEMICONDUCTOR PACKAGE

A semiconductor package including a first semiconductor device, a second semiconductor device, an insulating encapsulant, a redistribution structure and a supporting element is provided. The insulating encapsulant encapsulates the first semiconductor device and the second semiconductor device. The redistribution structure is over the first semiconductor device, the second semiconductor device and the insulating encapsulant. The redistribution structure is electrically connected to the first semiconductor device and the second semiconductor device. The supporting element is embedded in one of the insulating encapsulant and the redistribution structure. 1. A semiconductor package , comprising:a first semiconductor device and a second semiconductor device;an insulating encapsulant, encapsulating the first semiconductor device and the second semiconductor device;a redistribution structure, over the first semiconductor device, the second semiconductor device and the insulating encapsulant, the redistribution structure electrically connected to the first semiconductor device and the second semiconductor device; anda supporting element, embedded in one of the insulating encapsulant and the redistribution structure.2. The semiconductor package as claimed in claim 1 , wherein the insulating encapsulant comprises a first portion and a second portion claim 1 , the first portion of the insulating encapsulant laterally encapsulates the first semiconductor device and the second semiconductor device claim 1 , the second portion of the insulating encapsulant is located on the first portion of the insulating encapsulant claim 1 , the first semiconductor device and the second semiconductor device claim 1 , and the supporting element is embedded in the second portion of the insulating encapsulant.3. The semiconductor package as claimed in claim 1 , wherein the supporting element comprises a semiconductor dummy pattern.4. The semiconductor package as claimed in claim 1 , wherein the ...

PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF

A package structure including a first circuit board structure, a redistribution layer structure, bonding elements, and a semiconductor package is provided. The redistribution layer structure is disposed over and electrically connected to the first circuit board structure. The bonding elements are disposed between and electrically connected to the redistribution layer structure and the first circuit board structure. Each of the bonding elements has a core portion and a shell portion surrounding the core portion. A stiffness of the core portion is higher than a stiffness of the shell portion. A semiconductor package is disposed over and electrically connected to the redistribution layer structure. 1. A package structure , comprising:a first circuit board structure;a redistribution layer structure, disposed over and electrically connected to the first circuit board structure;a plurality of first bonding elements, disposed between and electrically connected to the redistribution layer structure and the first circuit board structure, wherein each of the plurality of first bonding elements has a core portion and a shell portion surrounding the core portion, and a stiffness of the core portion is higher than a stiffness of the shell portion; anda semiconductor package, disposed over and electrically connected to the redistribution layer structure.2. The package structure according to claim 1 , further comprises:a plurality of conductive terminals on a surface of the first circuit board structure opposite to a surface on which the redistribution layer structure is disposed, wherein a diameter of each of the conductive terminals is larger than a diameter of each of the first bonding elements.3. The package structure according to claim 1 , further comprises:an insulating material disposed between the first bonding elements and surrounding sidewalls of the first circuit board structure.4. The package structure according to claim 1 , further comprises:a second circuit board ...

SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME

Semiconductor packages and methods of forming the same are disclosed. The semiconductor package includes a plurality of chips, a first molding compound, a first redistribution structure, a second molding compound and a second redistribution structure. The first molding compound encapsulates the chips. The first redistribution structure is disposed over the plurality of chips and the first molding compound. The second molding compound surrounds the first molding compound. The second redistribution structure is disposed over the first redistribution structure, the first molding compound and the second molding compound. 1. A semiconductor package , comprising:a plurality of chips, wherein one of the plurality of chips comprises a protection layer;a first molding compound, encapsulating the plurality of chips, and a material of the protection layer is different from a material of the first molding compound;a first redistribution structure, disposed over the plurality of chips and the first molding compound, wherein the first redistribution structure is in contact with the protection layer;a second molding compound, surrounding the first molding compound, wherein the second molding compound covers the first redistribution structure; anda second redistribution structure, disposed over the first redistribution structure, the first molding compound and the second molding compound.2. The semiconductor package of claim 1 , wherein the second molding compound is directly contact with the first molding compound claim 1 , and an interface is formed between the first molding compound and the second molding compound.3. The semiconductor package of claim 1 , wherein the second molding compound is not disposed between the plurality of chips.4. The semiconductor package of claim 1 , wherein the first redistribution structure comprises a plurality of connecting pads claim 1 , and the plurality of connecting pads is directly contact with the second redistribution structure.5. The ...

Substrate and Package Structure

According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area. 1. A device comprising:a substrate comprising a first pad and a second pad, the first pad being disposed in a first region of the substrate, the second pad being disposed in a second region of the substrate, the first region being in an inner region of the substrate, the second region extending from the first region to a first edge of the substrate, the first pad and the second pad having a same first height, a first width of the first pad being greater than a second width of the second pad;a chip comprising a first bump and a second bump, the first bump and the second bump having a same third width;a first connector coupling the first bump to the first pad; anda second connector coupling the second bump to the second pad.2. The device of claim 1 , wherein the substrate further comprises a third pad claim 1 , the third pad being disposed in a third region of the substrate claim 1 , the third region extending from the second region to a second edge of the substrate claim 1 , the third pad having the first width claim 1 , and wherein the chip further comprises a third bump claim 1 , the third bump having the third width.3. The device of further comprising:a third connector coupling the third bump to the third pad.4. The device of claim 1 , wherein the first connector and the second connector are solder connectors.5. The device of claim 1 , wherein the substrate further comprises a plurality of first pads in the first region and a plurality of second pads in the second region claim 1 , each of the first pads having the first width claim 1 , each of the second pads having the second width claim 1 , wherein a width of the first region is about 80% of a width of the substrate claim 1 , and a width of the second region ...

POP JOINT THROUGH INTERPOSER

A package includes a package component and an interposer over and bonded to the package component. The package component includes a solder region. The interposer includes a core dielectric material, a conductive pipe penetrating through the core dielectric material, with the first solder region in contact with a bottom end of the conductive pipe, and a through-opening in a center region of the interposer. 1. A package comprising:a package component comprising a first solder region; and a core dielectric material;', 'a conductive pipe penetrating through the core dielectric material, wherein the first solder region is in contact with a bottom end of the conductive pipe; and', 'a through-opening in a center region of the first interposer., 'a first interposer over and bonded to the package component, wherein the first interposer comprises2. The package of further comprising a device die bonded to the package component claim 1 , wherein the device die extends into the through-opening of the first interposer.3. The package of further comprising a second solder region in contact with a top end of the conductive pipe.4. The package of claim 3 , wherein the first solder region and the second solder region are spaced apart from each other claim 3 , with an unoccupied gap between the first solder region and the second solder region.5. The package of claim 1 , wherein the first solder region extends into the conductive pipe.6. The package of further comprising a second interposer over the first interposer claim 1 , wherein the second interposer comprises:a plurality of metal pads distributed substantially uniformly throughout a top surface of the second interposer; anda plurality of solder regions distributed in peripheral regions of a bottom surface of the second interposer, wherein no solder region is distributed to a center region of the bottom surface of the second interposer, and the plurality of solder regions is electrically coupled to the plurality of metal pads.7. ...

SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME

An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill. 1. A semiconductor package comprising:a bare semiconductor chip;a packaged semiconductor chip adjacent the bare semiconductor chip; a first redistribution layer having a first thickness;', 'a second redistribution layer having a second thickness; and', 'a third redistribution layer between the first redistribution layer and the second redistribution layer, the third redistribution layer having a third thickness greater than the first thickness and the second thickness;, 'a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip, wherein the redistribution structure comprisesan underfill disposed between the bare semiconductor chip and the redistribution structure; anda molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill, wherein a first surface of the bare semiconductor chip and a second surface of the packaged semiconductor chip are exposed by the molding compound.2. The semiconductor package of claim 1 , wherein the redistribution structure further comprises:a first conductive via electrically connected to the second ...

Semiconductor Packages and Method of Manufacture

A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.

Substrate Design with Balanced Metal and Solder Resist Density

A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1. 1. A package comprising: a middle layer selected from the group consisting of a core and a middle metal layer;', 'a top metal layer overlying the middle layer, wherein all metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer; and', 'a bottom metal layer underlying the middle layer, wherein all metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer, and wherein an absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1., 'a package substrate comprising2. The package of claim 1 , wherein the middle layer is a core layer comprising;a dielectric layer; andconductive pipes penetrating through the dielectric layer, wherein the top metal layer is electrically coupled to the bottom metal layer through the conductive pipes.3. The package of claim 1 , wherein the middle layer comprises a metal layer.4. The package of further comprising:a first solder resist comprising a first portion level with the top metal layer, wherein the first solder resist has a first solder resist density; anda second solder resist comprising a ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate. 1. A semiconductor package , comprising:a substrate;a semiconductor device disposed on the substrate; and a first portion bonded to the substrate; and', 'a second portion connecting to the first portion, wherein a cavity is between the second portion and the substrate, and the cavity is spaced apart from a space encircled by the first portion., 'a ring structure disposed on the substrate and surrounds the semiconductor device, the ring structure comprising2. The semiconductor package of claim 1 , wherein the first portion and the second portion are the same material.3. The semiconductor package of claim 1 , further comprising a bonding layer claim 1 , the bonding layer bonded the first portion of the ring structure to the substrate.4. The semiconductor package of claim 3 , wherein the bonding layer partially fills the cavity.5. The semiconductor package of claim 3 , wherein the bonding layer fills the cavity claim 3 , and the bonding layer contacts the second portion.6. The semiconductor package of claim 1 , wherein a first thickness of the first portion is greater than a second thickness of the second portion.7. The semiconductor package of claim 1 , wherein a top surface of the first portion is substantially coplanar with a top surface of the second portion.8. The semiconductor package of claim 1 , wherein the second portion extends outwardly from a top of the first portion.9. A semiconductor package claim 1 , comprising:a substrate;a semiconductor device disposed on the substrate;a first ring structure disposed on the ...

INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF

An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure. 1. An integrated fan-out package , comprising:a die;a seed layer and a conductive pillar sequentially stacked over the die; a conductive pattern directly in contact with the seed layer; and', 'a dielectric layer covering the conductive pattern, wherein the dielectric layer has a first opening exposing at least a portion of the conductive pattern, and a portion of the first opening is occupied by the seed layer and the conductive pillar; and, 'a redistribution structure over the die, comprisinga buffer layer disposed over the redistribution structure and extending into the opening to occupy the rest portion of the first opening, wherein the seed layer is separate from the dielectric layer by the buffer layer without directly contacting the dielectric layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.2. The integrated fan-out package according to claim 1 , further comprising a conductive bump disposed on the conductive pillar.3. The integrated fan-out package according to claim 1 , wherein the buffer layer has a second ...

Protrusion Bump Pads for Bond-on-Trace Processing

A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die. 1. A method of forming a semiconductor structure , the method comprising: a stack of dielectric layers;', 'a first conductive pillar embedded in the stack of dielectric layers;', 'a second conductive pillar embedded in the stack of dielectric layers; and', 'a metal layer extending along an outermost dielectric layer of the stack of dielectric layers, the metal layer disposed between the outermost dielectric layer and the patterned mask layer, wherein the patterned mask layer covers a first portion of the metal layer contacting a first surface of the first conductive pillar while exposing a second portion of the metal layer contacting a second surface of the second conductive pillar; and, 'forming a patterned mask layer on a first side of a build-up layer, wherein the build-up layer comprisesetching the metal layer using the patterned mask layer as an etching mask, wherein after the etching, the first portion of the metal layer remains and the second portion of the metal layer is removed, where etching the metal layer recesses the second surface of the second conductive pillar from a first side of the outermost dielectric layer facing the metal layer.2. The method of claim 1 , wherein each of the first conductive pillar and the second conductive pillar comprises alternating layers of conductive traces and vias claim 1 , wherein the first conductive pillar comprises a first conductive ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A method of manufacturing a semiconductor structure includes providing a substrate including a redistribution layer (RDL) disposed over the substrate, disposing a first patterned mask over the RDL, disposing a first conductive material over the RDL exposed from the first patterned mask to form a first conductive pillar, removing the first patterned mask, disposing a second patterned mask over the RDL, disposing a second conductive material over the RDL exposed from the second patterned mask to form a second conductive pillar, removing the second patterned mask, disposing a first die over the first conductive pillar, and disposing a second die over the second conductive pillar. A height of the second conductive pillar is substantially greater than a height of the first conductive pillar. 2. The method of claim 1 , wherein a thickness of the second patterned mask is substantially greater than a thickness of the first patterned mask.3. The method of claim 1 , further comprising:disposing a seed layer between the RDL and the first patterned mask or between the RDL and the second patterned mask;disposing a soldering material over the first conductive pillar or the second conductive pillar;bonding the first die with the first conductive pillar by a first conductive bump;bonding the second die with the second conductive pillar by a second conductive bump;disposing an underfill material to encapsulate the first conductive pillar and the second conductive pillar;disposing a molding to surround the underfill material, the first die and the second die; ordisposing a heat dissipation means over the first die and the second die.4. A method of manufacturing a semiconductor structure claim 1 , comprising:providing a substrate;disposing a first conductive pillar over the substrate, the first conductive pillar comprising a first height; anddisposing a second conductive pillar over the substrate after disposing the first conducive pillar, the second conductive pillar comprising a ...

Semiconductor structure and method of manufacturing the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate comprising a recess portion filled with a conductive material; a conductive trace overlying and contacting the conductive material; a conductive pillar disposed on the conductive trace and over the recess portion of the substrate; and a semiconductor chip disposed on the conductive pillar.

INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF

An integrated fan-out package includes a die, an encapsulant, a redistribution structure, a seed layer, conductive pillars, and a buffer layer. The encapsulant encapsulates the die. The redistribution structure is over the die and the encapsulant. The redistribution structure includes dielectric layers and conductive patterns. The dielectric layers are sequentially stacked and the conductive patterns are sandwiched between the dielectric layers. The seed layer and the conductive pillars are sequentially stacked over the redistribution structure. The seed layer is directly in contact with the conductive patterns closest to the conductive pillars. The buffer layer is disposed over the redistribution structure. The dielectric layer closest to the conductive pillars and the buffer layer are sandwiched between the seed layer and the conductive patterns closest to the conductive pillars. A Young's modulus of the buffer layer is higher than a Young's modulus of each of the dielectric layers of the redistribution structure. 1. An integrated fan-out package , comprising:a die;an encapsulant encapsulating the die; a plurality of dielectric layers that are sequentially stacked; and', 'a plurality of conductive patterns sandwiched between the plurality of dielectric layers;, 'a redistribution structure over the die and the encapsulant, comprisinga seed layer and a plurality of conductive pillars sequentially stacked over the redistribution structure, wherein the seed layer is directly in contact with the conductive patterns closest to the conductive pillars; anda buffer layer disposed over the redistribution structure, wherein the dielectric layer closest to the conductive pillars and the buffer layer are sandwiched between the seed layer and the conductive patterns closest to the conductive pillars, and a Young's modulus of the buffer layer is higher than a Young's modulus of each of the plurality of dielectric layers of the redistribution structure.2. The integrated fan-out ...

Protrusion Bump Pads for Bond-on-Trace Processing

An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion having an exposed top surface, wherein the exposed top surface is recessed from a top surface of the dielectric layer. Furthermore, the bump pad is disposed over and is electrically connected to a second portion of the conductive trace. 1. A device comprising:a substrate;an insulating layer on the substrate;a conductive line in the insulating layer; anda conductive pad in the insulating layer and directly over a first region of the conductive line, wherein the conductive pad has a different material composition than the conductive line, wherein a top surface of the conductive pad is not higher than a top surface of the insulating layer, wherein no portions of the insulating layer and no portions of the conductive pad extend directly over a second region of the conductive line.2. The device of claim 1 , wherein the conductive pad comprises nickel or tin claim 1 , and wherein the conductive line comprises copper.3. The device of claim 1 , wherein the conductive pad is connected to a contact pad through the conductive line claim 1 , wherein the conductive pad is disposed in the insulating layer claim 1 , and wherein the device further comprises a conductive pillar extending from the contact pad through the insulating layer.4. The device of claim 3 , wherein the contact pad and the conductive line have a same material composition.5. The device of claim 3 , wherein a top surface of the contact pad is lower than a top surface of the insulating layer.6. The device of further comprising:an integrated circuit chip; anda solder region physically coupling the integrated circuit chip to the conductive pad.7. The device of claim 1 , wherein a top surface of the conductive pad is substantially level with the top surface of the insulating layer.8. The device of claim 1 , wherein a top surface of the second region of the ...

Protrusion Bump Pads for Bond-on-Trace Processing

A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die. 1. An apparatus , comprising:a substrate;a plurality of conductive traces disposed on a side of the substrate;a plurality of conductive members each extending into the substrate from a corresponding one of the conductive traces; anda plurality of bump pads each protruding from one of a first subset of the conductive traces, wherein a second subset of the conductive traces are recessed within the side of the substrate.2. The apparatus of claim 1 , wherein the side is a first side claim 1 , and wherein ones of the plurality of conductive members are conductive pillars extending to corresponding conductive features disposed on a second side of the substrate.3. The apparatus of claim 1 , wherein the plurality of conductive traces are laterally offset from one another by a minimum trace pitch claim 1 , the plurality of bump pads are laterally offset from one another by a minimum bump pad pitch claim 1 , and the minimum bump pad pitch is substantially greater than the minimum trace pitch.4. The apparatus of claim 1 , wherein the plurality of conductive traces are laterally offset from one another by a minimum trace pitch claim 1 , the plurality of bump pads are laterally offset from one another by a minimum bump pad pitch claim 1 , and the minimum bump pad pitch is at least about twice the minimum trace pitch.5. The apparatus of claim 1 , wherein the plurality of conductive traces are ...

METALLIZATION PATTERNS IN SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME

An embodiment method includes encapsulating a semiconductor die in an encapsulant, planarizing the encapsulant, and depositing a polymer material on the encapsulant. The method further includes planarizing the polymer material and forming a metallization pattern on the polymer material. The metallization pattern electrically connects a die connector of the semiconductor die to a conductive feature disposed outside of the semiconductor die. 1. A method comprising:encapsulating a semiconductor die in an encapsulant;planarizing the encapsulant;depositing a polymer material on the encapsulant;planarizing the polymer material; andforming a metallization pattern on the polymer material, wherein the metallization pattern electrically connects a die connector of the semiconductor die to a conductive feature disposed outside of the semiconductor die.2. The method of claim 1 , wherein the encapsulant comprises a filler claim 1 , wherein planarizing the encapsulant exposes a hollow core of the filler claim 1 , and wherein depositing the polymer material comprises filling the hollow core with the polymer material.3. The method of further comprising forming a polymer layer between the polymer material and the metallization pattern.4. The method of claim 1 , wherein forming the metallization pattern comprises forming the metallization pattern in physical contact with the polymer material.5. The method of claim 4 , further comprising:patterning a first opening through the polymer material to expose the die connector of the semiconductor die; andpatterning a second opening through the polymer material to expose the conductive feature, wherein forming the metallization pattern comprises forming portions of the metallization pattern in the first opening and the second opening.6. The method of claim 5 , wherein patterning the first opening and patterning the second opening is performed prior to planarizing the polymer material.7. The method of further comprising prior to depositing ...

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, a second encapsulant, and a plurality of conductive terminals. The first encapsulant is at least disposed between the first die and the second die, and on the second die. The second encapsulant is aside the first die and the second die. The conductive terminals are electrically connected to the first die and the second die through a redistribution layer (RDL) structure. An interface is existed between the first encapsulant and the second encapsulant. 1. A package structure , comprising:a first die and a second die;a first encapsulant, at least disposed between the first die and the second die, and on the second die;a second encapsulant, aside the first die and the second die; anda plurality of conductive terminals, electrically connected to the first die and the second die through a redistribution layer (RDL) structure,wherein an interface is existed between the first encapsulant and the second encapsulant.2. The package structure of claim 1 , wherein the first encapsulant and the second encapsulant comprise different materials.3. The package structure of claim 1 , wherein the first encapsulant and the second encapsulant respectively comprise a filler claim 1 , and the particle size of the filler of the first encapsulant is smaller than the particle size of the filler of the second encapsulant.4. The package structure of claim 1 , wherein the first encapsulant is free of filler claim 1 , and the second encapsulant comprises a filler.5. The package structure of claim 1 , wherein the first encapsulant is further disposed on the first die.6. The package structure of claim 5 , wherein the first encapsulant laterally encapsulates and contacts with a first connector of the first die claim 5 , and a second connector of the second die.7. The package structure of claim 1 , wherein the second encapsulant is in contact with at least ...

DIE CORNER REMOVAL FOR UNDERFILL CRACK SUPPRESSION IN SEMICONDUCTOR DIE PACKAGING

A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion. 1. A chip package structure comprising:a fan-out package comprising at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure located on horizontal surfaces of the at least one semiconductor die and the EMC die frame, wherein the fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical;a package substrate that is attached to the fan-out package via an array of solder material portions; andan underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces.2. The chip package structure of claim 1 , wherein:the fan-out package comprises four chamfer regions located at four corners of a proximal horizontal surface of the fan-out package that faces the package substrate; andan entirety of each of the angled surfaces contacts the underfill material portion.3 ...

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING

Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface. 1. A method comprising:depositing a first dielectric layer over a carrier substrate;depositing a first conductive layer over the first dielectric layer;forming a first through via over the first conductive layer;attaching a local interconnect device to the first conductive layer adjacent to the first through via;encapsulating the local interconnect device and the first through via in a first molding compound;forming a second dielectric layer over the local interconnect device and the first molding compound;forming a second through via over a through interconnect via of the local interconnect device;forming a third through via over the first through via; andencapsulating the third through via and the second through via in a second molding compound.2. The method of claim 1 , further comprising:forming an opening in the second dielectric layer to expose the through interconnect via; anddepositing a second conductive layer at least partially in the second opening.3. The method of claim 1 , wherein the forming the first through via comprises plating a conductive fill material into a patterned photoresist.4. The method of claim 1 , further comprising depositing a second conductive layer over the second molding compound and in electrical connection with the second through via and the third through via.5. The ...

Package structure and method of manufacturing the same

A package structure and a method of forming the same are provided. The package structure includes a first die and a second die, a first encapsulant, a second encapsulant and a RDL structure. The first die includes a first connector and a first protection layer covering sidewalls of the first connector, and the second die includes a second connector. The first encapsulant is at least disposed laterally between the first die and the second die to encapsulate first sidewalls of the first die and the second die that faces each other. The second encapsulant encapsulates second sidewalls of the first die and the second die. The RDL structure is disposed on and electrically connected to the first die and the second die. The top surfaces of the first protection layer, the first encapsulant, and the second encapsulant are in contact with a bottom surface of the RDL structure.

Protrusion Bump Pads for Bond-on-Trace Processing

An embodiment apparatus includes a dielectric layer in a die, a conductive trace in the dielectric layer, and a protrusion bump pad on the conductive trace. The protrusion bump pad at least partially extends over the dielectric layer, and the protrusion bump pad includes a lengthwise axis and a widthwise axis. A ratio of a first dimension of the lengthwise axis to a second dimension of the widthwise axis is about 0.8 to about 1.2 1. An apparatus , comprising:a dielectric layer;a conductive trace in the dielectric layer, wherein the conductive trace comprises a conductive trace pad portion, and wherein the conductive trace pad portion is wider than another portion of the conductive trace; anda protrusion bump pad on the conductive trace pad portion, wherein the protrusion bump pad at least partially extends over the dielectric layer, wherein the protrusion bump pad comprises a first lengthwise axis and a widthwise axis, and wherein a ratio of a first dimension of the first lengthwise axis to a second dimension of the widthwise axis is about 0.8 to about 1.2.2. The apparatus of claim 1 , wherein the first dimension is substantially equal to the second dimension.3. The apparatus of claim 1 , wherein the protrusion bump pad is substantially circular claim 1 , substantially square claim 1 , hexagonal claim 1 , or octagonal.4. (canceled)5. The apparatus of claim 1 , wherein the conductive trace pad portion is circular claim 1 , ovular claim 1 , rectangular claim 1 , hexagonal claim 1 , or octagonal.6. The apparatus of further comprising a die bonded to the dielectric layer claim 1 , wherein the die comprises a conductive bump claim 1 , and wherein the conductive bump contacts the protrusion bump pad.7. The apparatus of claim 6 , wherein the conductive bump further contacts a sidewall of the protrusion bump pad.8. The apparatus of claim 6 , wherein a second lengthwise axis of the conductive bump is substantially parallel with the first lengthwise axis of the protrusion ...

Protrusion Bump Pads for Bond-on-Trace Processing

A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die. 1. An apparatus , comprising:a substrate;a plurality of conductive traces disposed on a side of the substrate;a plurality of conductive members each extending into the substrate from a corresponding one of the conductive traces; anda plurality of bump pads each protruding from one of a first subset of the conductive traces, wherein a second subset of the conductive traces are recessed within the side of the substrate.2. The apparatus of wherein the side is a first side claim 1 , and wherein ones of the plurality of conductive members are conductive pillars extending to corresponding conductive features disposed on a second side of the substrate.3. The apparatus of wherein the plurality of conductive traces are laterally offset from one another by a minimum trace pitch claim 1 , the plurality of bump pads are laterally offset from one another by a minimum bump pad pitch claim 1 , and the minimum bump pad pitch is substantially greater than the minimum trace pitch.4. The apparatus of wherein the plurality of conductive traces are laterally offset from one another by a minimum trace pitch claim 1 , the plurality of bump pads are laterally offset from one another by a minimum bump pad pitch claim 1 , and the minimum bump pad pitch is at least about twice the minimum trace pitch.5. The apparatus of wherein the plurality of conductive traces are laterally offset from one another by a minimum ...

Protrusion Bump Pads for Bond-on-Trace Processing

An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion having an exposed top surface, wherein the exposed top surface is recessed from a top surface of the dielectric layer. Furthermore, the bump pad is disposed over and is electrically connected to a second portion of the conductive trace. 1. An apparatus comprising:a dielectric layer;a conductive trace in the dielectric layer, wherein the conductive trace comprises a first portion having an exposed top surface, and wherein the exposed top surface is recessed from a top surface of the dielectric layer; anda bump pad over and electrically connected to a second portion of the conductive trace.2. The apparatus of claim 1 , wherein the bump pad and the conductive trace comprise different conductive materials.3. The apparatus of claim 2 , wherein the bump pad comprises nickel or tin claim 2 , and wherein the conductive trace comprises copper.4. The apparatus of claim 1 , wherein the conductive trace is connected to a contact pad in the dielectric layer claim 1 , and wherein the apparatus further comprises a conductive pillar extending from the contact pad through the dielectric layer.5. The apparatus of further comprising:an integrated circuit chip; anda conductive bump physically coupled between the integrated circuit chip and the bump pad.6. The apparatus of claim 5 , wherein there are no conductive bumps physically coupling the integrated circuit chip to the first portion of the conductive trace.7. The apparatus of claim 1 , wherein a top surface of the bump pad is substantially level with the top surface of the dielectric layer.8. A method comprising: a core; and', 'a first conductive layer on the core;, 'providing a carrier substrate comprisingforming a first bump pad on the first conductive layer, wherein the first bump pad and the first conductive layer comprise different conductive materials; a first portion ...

SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME

Semiconductor packages and methods of forming the same are disclosed. One of the semiconductor packages includes a first redistribution layer structure, a package structure, a bus die and a plurality of connectors. The package structure is disposed over the first redistribution layer structure, and includes a plurality of package components. The bus die and the connectors are encapsulated by a first encapsulant between the package structure and the first redistribution layer structure. The bus die is electrically connected to two or more of the plurality of package components, and the package structure are electrically connected to the first redistribution layer structure through the plurality of connectors. 1. A semiconductor package , comprising:a first redistribution layer structure;a package structure over the first redistribution layer structure, comprising a plurality of package components; anda bus die and a plurality of connectors, encapsulated by a first encapsulant between the package structure and the first redistribution layer structure, wherein the bus die is electrically connected to two or more of the plurality of package components, and the package structure are electrically connected to the first redistribution layer structure through the plurality of connectors.2. The semiconductor package according to claim 1 , further comprising a circuit board structure claim 1 , wherein the first redistribution layer structure is disposed over the circuit board structure claim 1 , and the circuit board structure includes a core layer claim 1 , a first build-up layer on a first surface of the core layer claim 1 , and a second build-up layer on a second surface of the core layer opposite to the first surface.3. The semiconductor package according to claim 1 , wherein the first encapsulant comprises a molding compound.4. The semiconductor package according to claim 1 , further comprising a second encapsulant claim 1 , wherein the plurality of package components ...

SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME

Semiconductor packages and methods of forming the same are disclosed. One of the semiconductor packages includes a circuit board structure, a first redistribution layer structure, a plurality of first bonding elements, a package structure and a plurality of second bonding elements. The first redistribution layer structure is disposed over and electrically connected to the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the circuit board structure. The package structure is disposed over and electrically connected to the first redistribution layer structure. The second bonding elements are disposed between and electrically connected to the first redistribution layer structure and the package structure. 1. A semiconductor package , comprising:a circuit board structure;a first redistribution layer structure, disposed over and electrically connected to the circuit board structure;a plurality of first bonding elements, disposed between and electrically connected to the first redistribution layer structure and the circuit board structure;a package structure, disposed over and electrically connected to the first redistribution layer structure; anda plurality of second bonding elements, disposed between and electrically connected to the first redistribution layer structure and the package structure.2. The semiconductor package according to claim 1 , wherein the first bonding elements and the second bonding elements are solder regions.3. The semiconductor package according to claim 1 , wherein a diameter of each of the first bonding elements is larger than a diameter of each of the second bonding elements.4. The semiconductor package according to claim 1 , further comprising a plurality of conductive terminals on a surface of the circuit board structure opposite to a surface on which the first redistribution layer structure is disposed claim 1 , wherein a diameter of each of ...

Package Having Substrate With Embedded Metal Trace Overlapped by Landing Pad

An embodiment package includes a conductive pillar mounted on an integrated circuit chip, the conductive pillar having a stepper shape, a metal trace partially embedded in a substrate, the metal trace having a bonding pad portion protruding from the substrate, and a solder feature electrically coupling the conductive pillar to the bonding pad portion of the metal trace. 1. A package , comprising:a conductive pillar mounted on an integrated circuit chip, the conductive pillar having a stepper shape;a metal trace partially embedded in a substrate, the metal trace having a bonding pad portion protruding from the substrate; anda solder feature electrically coupling the conductive pillar to the bonding pad portion of the metal trace.2. The package of claim 1 , wherein the bonding pad portion has a stepper shape.3. The package of claim 1 , wherein the bonding pad portion has an inverted stepper shape.4. The package of claim 1 , wherein a diameter of the bonding pad portion tapers from top to bottom.5. The package of claim 1 , wherein a diameter of the bonding pad portion tapers from bottom to top.6. The package of claim 1 , wherein a top width of the bonding pad portion is less than a bottom width of the bonding pad portion.7. The package of claim 1 , wherein a top width of the bonding pad portion is greater than a bottom width of the bonding pad portion.8. The package of claim 1 , wherein the bonding pad portion utilizes a stepper shape when a formula b−a>0.36h−0.1 is satisfied claim 1 , where b is a bottom width of the bonding pad portion claim 1 , a is a top width of the bonding pad portion claim 1 , and his a height of the bonding pad portion.9. The package of claim 1 , wherein the bonding pad portion utilizes an inverted stepper shape when a formula a−b>0.36h−0.1 is satisfied claim 1 , where a is a top width of the bonding pad portion claim 1 , b is a bottom width of the bonding pad portion claim 1 , and his a height of the bonding pad portion.10. The package of ...

Package Having Substrate With Embedded Metal Trace Overlapped by Landing Pad

An embodiment package includes a conductive pillar mounted on an integrated circuit chip, the conductive pillar having a stepper shape, a metal trace partially embedded in a substrate, the metal trace having a bonding pad portion protruding from the substrate, and a solder feature electrically coupling the conductive pillar to the bonding pad portion of the metal trace. 1. A method of forming a semiconductor device , the method comprising:forming a conductive trace on a first substrate, the conductive trace having a bonding pad portion protruding from the first substrate and a recessed portion recessed from an outermost surface of the first substrate, the first substrate not extending over the recessed portion, sidewalls of the recessed portion having a different profile than sidewalls of the bonding pad portion; andbonding the bonding pad portion to a conductive pillar on a second substrate, the conductive pillar having a decreasing width as the conductive pillar extends away from the second substrate.2. The method of claim 1 , wherein the bonding pad portion has a width that decreases as the bonding pad portion extends away from the first substrate.3. The method of claim 1 , wherein the bonding pad portion has a width that increases as the bonding pad portion extends away from the first substrate.4. The method of claim 1 , wherein a height of the bonding pad portion above the outermost surface of the first substrate is greater than a height of the conductive pillar.5. The method of claim 1 , wherein the bonding pad portion utilizes a stepper shape when a formula b-a>0.36 hs−0.1 μm is satisfied claim 1 , where b is a bottom width of the bonding pad portion claim 1 , a is a top width of the bonding pad portion claim 1 , and hs is a height of the bonding pad portion.6. The method of claim 1 , wherein the bonding pad portion utilizes an inverted stepper shape when a formula a-b>0.36 hs−0.1 μm is satisfied claim 1 , where a is a top width of the bonding pad portion ...

Package Substrates, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices

In some embodiments, a package substrate for a semiconductor device includes a substrate core and a material layer disposed over the substrate core. The package substrate includes a spot-faced aperture disposed in the substrate core and the material layer. 1. A method of packaging a semiconductor device , the method comprising:providing a package substrate including a substrate core and a material layer disposed over the substrate core; a first region having a first diameter; and', 'a second region connected to the first region and having a second diameter, the second diameter being less than the first diameter, and a center of the second region being offset from a center of the first region in a top-down view;, 'patterning an aperture in the substrate core and the material layer, wherein the aperture comprisescoupling an integrated circuit to the package substrate; anddispensing an underfill material between the package substrate and the integrated circuit through the aperture.2. The method of claim 1 , further comprising curing the underfill material.3. The method of claim 1 , wherein coupling the integrated circuit to the package substrate comprises coupling the integrated circuit to a side of the package substrate proximate the second region of the aperture.4. The method of claim 3 , wherein dispensing the underfill material comprises injecting the underfill material into the first region claim 3 , the underfill material flowing from the first region into the second region.5. The method of claim 1 , wherein providing the package substrate comprises providing a flip-chip package substrate.6. The method of claim 1 , wherein patterning the aperture comprises forming the first region such that the first region extends only partially through the substrate core.7. The method of claim 1 , wherein patterning the aperture comprises forming the first region to extend completely through the substrate core.8. The method of claim 1 , wherein the first region has slanted ...

Semiconductor structure and manufacturing method thereof

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first under-bump metallization (UBM) pattern covered by a first dielectric layer, and the first UBM pattern includes a surface substantially leveled with a surface of the first dielectric layer. The circuit substrate is electrically coupled to the redistribution structure through a conductive joint disposed on the surface of the first UBM pattern. The insulating encapsulation is disposed on the redistribution structure to cover the circuit substrate.

Substrate Design for Semiconductor Packages and Method of Forming Same

An embodiment device package includes a package substrate and a first and a second die bonded to the package substrate. The package substrate includes a build-up portion comprising a first contact pad and a plurality of bump pads. The package substrate further includes an organic core attached to the build-up portion, a through-via electrically connected to the first contact pad and extending through the organic core, a second contact pad on the through-via, a connector on the second contact pad, and a cavity extending through the organic core. The cavity exposes the plurality of bump pads, and the first die is disposed on the cavity and is bonded to the plurality of bump pads. 1. A device package comprising: a build-up portion comprising a first contact pad and a plurality of bump pads at a first surface;', 'an organic core attached to the build-up portion;', 'a through-via extending through the organic core, wherein the through-via is electrically connected to the first contact pad;', 'a second contact pad on the through-via;', 'a connector on the second contact pad; and', 'a cavity extending through the organic core, wherein the cavity exposes the plurality of bump pads;, 'a package substrate comprisinga first die disposed in the cavity, wherein the die is bonded to plurality of bump pads; anda second die bonded to the package substrate.2. The device package of claim 1 , wherein a second device package comprising the second die is bonded to package substrate by the connector.3. The device package of claim 1 , wherein the package substrate further comprises a third contact pad at an opposing surface of the build-up portion as the first surface claim 1 , and wherein a second device package comprising the second die is bonded to the third contact pad.4. The device package of claim 1 , further comprising an interposer bonded to the package substrate claim 1 , wherein the second die is bonded to an opposing side of the interposer as the package substrate.5. The device ...

SEMICONDUCTOR STRUCTURE AND ASSOCIATED METHOD FOR MANUFACTURING THE SAME

A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces beneath and between the dies; disposing a temporary carrier over the dies; thinning a thickness of the semiconductor substrate; performing back side metallization upon the thinned semiconductor substrate; removing the temporary carrier; and attaching a plate over the dies. An associated semiconductor structure is also disclosed. 1. A semiconductor structure , comprising:a semiconductor substrate having a front side and a back side opposite to the front side;a plurality of dies on the front side of the semiconductor substrate;a plate attached over the plurality of dies, wherein the plurality of dies is between the plate and the semiconductor substrate; andan adhesive used to bonding the plate and the plurality of dies;wherein edges of the adhesive are flush with edges of the plate.2. The semiconductor structure of claim 1 , further comprising an underfill material filling space between the plurality of dies and the semiconductor substrate.3. The semiconductor structure of claim 2 , further comprising a metallization layer on the back side of the semiconductor substrate.4. The semiconductor structure of claim 3 , further comprising a molding compound filling space between the metallization layer and the adhesive.5. The semiconductor structure of claim 4 , wherein the edges of the adhesive are flush with edges of the molding compound.6. The semiconductor structure of claim 1 , wherein the plate includes a Cu plate having a modulus from about 130 to about 118 GPa.7. The semiconductor structure of claim 1 , wherein the plate includes a stainless steel plate having a modulus from about 190 to about 203 GPa.8. The semiconductor structure of claim 1 , wherein the plate includes a ceramic plate having a modulus from about 100 to about 175 GPa.9. ...

SEMICONDUCTOR STRUCTURE AND ASSOCIATED METHOD FOR MANUFACTURING THE SAME

A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces beneath and between the dies; disposing a temporary carrier over the dies; thinning a thickness of the semiconductor substrate; performing back side metallization upon the thinned semiconductor substrate; removing the temporary carrier; and attaching a plate over the dies. An associated semiconductor structure is also disclosed. 1. A semiconductor structure , comprising:a semiconductor substrate having a front side and a back side opposite to the front side;a die on the front side of the semiconductor substrate;a plate attached over the die, wherein the die is between the plate and the semiconductor substrate; andan adhesive used to bonding the plate and the die.2. The semiconductor structure of claim 1 , wherein edges of the plate are flush with edges of the semiconductor substrate.3. The semiconductor structure of claim 2 , further comprising a metallization layer on the back side of the semiconductor substrate.4. The semiconductor structure of claim 3 , further comprising a molding compound filling space between the metallization layer and the adhesive.5. The semiconductor structure of claim 4 , wherein the edges of the adhesive are flush with edges of the molding compound.6. The semiconductor structure of claim 1 , wherein the plate includes a Cu plate.7. The semiconductor structure of claim 1 , wherein the plate includes a stainless steel plate.8. The semiconductor structure of claim 1 , wherein the plate includes a ceramic plate.9. The semiconductor structure of claim 1 , wherein the adhesive has a thickness of about 50 microns to about 150 microns.10. A semiconductor structure claim 1 , comprising:a first semiconductor substrate having a front side and a back side opposite to the front side;a die on the front side of the first ...

Substrate and package structure

According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.

SEMICONDUCTOR STRUCTURE AND ASSOCIATED METHOD FOR MANUFACTURING THE SAME

A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces beneath and between the dies; disposing a temporary carrier over the dies; thinning a thickness of the semiconductor substrate; performing back side metallization upon the thinned semiconductor substrate; removing the temporary carrier; and attaching a plate over the dies. An associated semiconductor structure is also disclosed. 1. A semiconductor structure , comprising:a semiconductor substrate having a front side and a back side opposite to the front side;a plurality of dies on the front side of the semiconductor substrate;a plate attached over the plurality of dies, wherein the plurality of dies is between the plate and the semiconductor substrate;an adhesive used to bonding the plate and the plurality of dies; andan underfill material covering at least a portion of a sidewall of the plate.2. The semiconductor structure of claim 1 , wherein edges of the plate are flush with edges of the semiconductor substrate.3. The semiconductor structure of claim 2 , further comprising a metallization layer on the back side of the semiconductor substrate.4. The semiconductor structure of claim 3 , further comprising a molding compound filling space between the metallization layer and the adhesive.5. The semiconductor structure of claim 4 , wherein the edges of the adhesive are flush with edges of the molding compound.6. The semiconductor structure of claim 1 , wherein the plate includes a Cu plate having a modulus from about 130 to about 118 GPa.7. The semiconductor structure of claim 1 , wherein the plate includes a stainless steel plate having a modulus from about 190 to about 203 GPa.8. The semiconductor structure of claim 1 , wherein the plate includes a ceramic plate having a modulus from about 100 to about 175 GPa.9. The semiconductor structure ...

Package Substrates, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices

In some embodiments, a package substrate for a semiconductor device includes a substrate core and a material layer disposed over the substrate core. The package substrate includes a spot-faced aperture disposed in the substrate core and the material layer. 1. A package substrate for a semiconductor device , comprising:a substrate core;a material layer disposed over the substrate core; anda spot-faced aperture disposed in the substrate core and the material layer.2. The package substrate according to claim 1 , wherein the spot-faced aperture comprises a tank region and a pin-hole region coupled to the tank region.3. The package substrate according to claim 2 , wherein the substrate core comprises a first side and a second side claim 2 , wherein the first side includes a region for mounting an integrated circuit thereon claim 2 , wherein the second side includes a region for coupling a plurality of connectors claim 2 , wherein the pin-hole region of the spot-faced aperture is disposed proximate the first side claim 2 , and wherein the tank region of the spot-faced aperture is disposed proximate the second side.4. The package substrate according to claim 2 , wherein the tank region comprises a first width claim 2 , wherein the pin-hole region comprises a second width claim 2 , and wherein the first width is greater than the second width.5. The package substrate according to claim 4 , wherein the first width is about two times or greater than the second width.6. The package substrate according to claim 1 , wherein the substrate core includes a plurality of the spot-faced apertures disposed therein.7. The package substrate according to claim 1 , wherein the substrate core comprises a plurality of plated-through holes (PTHs) disposed therein.8. The package substrate according to claim 1 , wherein the material layer comprises a build-up layer disposed on a side of the substrate core claim 1 , and wherein a portion of the spot-faced aperture is disposed in the build-up ...

Semiconductor package and manufacturing method thereof

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

Protrusion Bump Pads for Bond-on-Trace Processing

An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion having an exposed top surface, wherein the exposed top surface is recessed from a top surface of the dielectric layer. Furthermore, the bump pad is disposed over and is electrically connected to a second portion of the conductive trace. 1. A device comprising:a substrate;an insulating layer on the substrate;a conductive line in the insulating layer; anda conductive pad in the insulating layer and directly over a first region of the conductive line, wherein the conductive pad has a different material composition than the conductive line, wherein a top surface of the conductive pad is not higher than a top surface of the insulating layer, wherein no portions of the insulating layer and no portions of the conductive pad extend directly over a second region of the conductive line.2. The device of claim 1 , wherein the conductive pad comprises nickel or tin claim 1 , and wherein the conductive line comprises copper.3. The device of claim 1 , wherein the conductive pad is connected to a contact pad through the conductive line claim 1 , wherein the conductive pad is disposed in the insulating layer claim 1 , and wherein the device further comprises a conductive pillar extending from the contact pad through the insulating layer.4. The device of claim 3 , wherein the contact pad and the conductive line have a same material composition.5. The device of claim 3 , wherein a top surface of the contact pad is lower than a top surface of the insulating layer.6. The device of further comprising:an integrated circuit chip; anda solder region physically coupling the integrated circuit chip to the conductive pad.7. The device of claim 1 , wherein a top surface of the conductive pad is substantially level with the top surface of the insulating layer.8. The device of claim 1 , wherein a top surface of the second region of the ...

INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF

An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure. 1. An integrated fan-out package , comprising:a die;an encapsulant encapsulating the die;a seed layer and a conductive pillar sequentially stacked over the die and the encapsulant; a conductive pattern directly in contact with the seed layer; and', 'a dielectric layer covering the conductive pattern and surrounding the seed layer and the conductive pillar; and, 'a redistribution structure over the die and the encapsulant, comprisinga buffer layer disposed over the redistribution structure, wherein the seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.2. The integrated fan-out package according to claim 1 , further comprising a conductive bump disposed on the conductive pillar.3. The integrated fan-out package according to claim 1 , wherein the dielectric layer has a first opening exposing at least a portion of the conductive pattern claim 1 , and the buffer layer has a second opening located within the first opening.4. The integrated fan-out package ...

Package Structures and Methods for Forming the Same

A packaging structure and a method of forming a packaging structure are provided. The packaging structure, such as an interposer, is formed by optionally bonding two carrier substrates together and simultaneously processing two carrier substrates. The processing includes forming a sacrificial layer over the carrier substrates. Openings are formed in the sacrificial layers and pillars are formed in the openings. Substrates are attached to the sacrificial layer. Redistribution lines may be formed on an opposing side of the substrates and vias may be formed to provide electrical contacts to the pillars. A debond process may be performed to separate the carrier substrates. Integrated circuit dies may be attached to one side of the redistribution lines and the sacrificial layer is removed. 1. A semiconductor device comprising:an integrated circuit die; a first insulating layer;', 'a second insulating layer, the first insulating layer being interposed between the second insulating layer and the integrated circuit die;', 'a first via extending through the first insulating layer, the first via having a first width at a first surface of the first insulating layer and a second width at a second surface of the first insulating layer, wherein the second width of the first via less than the first width of the first via, the first surface of the first insulating layer being closer to the integrated circuit die than the second surface of the first insulating layer; and', 'a second via extending through the second insulating layer, the second via having a first width at a first surface of the second insulating layer and a second width at a second surface of the second insulating layer, wherein the second width of the second via less than the first width of the second via, the first surface of the second insulating layer being closer to the integrated circuit die than the second surface of the second insulating layer; and, 'an interconnect structure, the integrated circuit die being ...

Substrate and Package Structure

According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area. 1. A package structure , comprising:a chip comprising a plurality of pillar bumps, the plurality of pillar bumps having a respective bump size;a substrate, having a core area and a non-core area, and comprising at least one pad in the core area and at least one pad in the non-core area, the at least one pad in the core area and the at least one pad in the non-core area having a pad size, wherein a ratio of the pad size to the bump size of the at least one pad in the core area is larger than a ratio of the pad size to the bump size of the at least one pad in the non-core area.2. The structure of claim 1 , further comprising a plurality of solders claim 1 , electrically connecting the plurality of pillar bumps and the plurality of pads.3. The structure of claim 1 , wherein the ratio of the pad size to the bump size in the core area is about 0.75 to about 1.25.4. The structure of claim 1 , wherein the ratio of the pad size to the bump size in the non-core area is about 0.5.5. The structure of claim 1 , wherein the non-core area includes other areas in the substrate except the core area.6. The structure of claim 1 , wherein the non-core area includes other areas in the substrate except the corner area of the substrate and the core area of the substrate.7. The structure of claim 1 , wherein the non-core area includes other areas in the substrate except the area having loose traces and the core area of the substrate.8. The structure of claim 1 , wherein the non-core area includes other areas in the substrate except the core area of the substrate claim 1 , a corner area of the substrate and an area having loose traces.9. The structure of claim 1 , wherein a center of the core area is aligned to the center of the ...

Substrate Design with Balanced Metal and Solder Resist Density

A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1. 1. A package comprising: a first plurality of vias in a first via layer, wherein each of the first plurality of vias has a first top width and a first bottom width smaller than the first top width;', 'a first plurality of metal lines in a first metal layer, wherein each of the first plurality of metal lines overlies and contacts a respective underlying one of the first plurality of vias, wherein all metal layers over the first via layer in combination have a first total metal density;', 'a second plurality of vias in a second via layer, wherein each of the second plurality of vias has a second top width and a second bottom width greater than the second top width; and', 'a second plurality of metal lines in a second metal layer, wherein each of the second plurality of metal lines underlies and contacts a respective overlying one of the second plurality of vias, wherein all metal layers under the second via layer have a second total metal density, and wherein an absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1., 'a package substrate comprising2. The package of claim 1 , wherein a first total count of the all metal layers over the first via layer is equal to a second total count of the all metal layers under ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a substrate, a redistribution layer (RDL) including a dielectric layer disposed over the substrate and a plurality of conductive members surrounded by the dielectric layer, a first conductive pillar disposed over and electrically connected with one of the plurality of conductive members, a second conductive pillar disposed over and electrically connected with one of the plurality of conductive member, a first die disposed over the RDL and electrically connected with the first conductive pillar, and a second die disposed over the RDL and electrically connected with the second conductive pillar, wherein a height of the second conductive pillar is substantially greater than a height of the first conductive pillar, and a thickness of the first die is substantially greater than a thickness of the second die. 1. A semiconductor structure , comprising:a substrate;a redistribution layer (RDL) including a dielectric layer disposed over the substrate and a plurality of conductive members surrounded by the dielectric layer;a first conductive pillar disposed over and electrically connected with one of the plurality of conductive members;a second conductive pillar disposed over and electrically connected with one of the plurality of conductive member;a first die disposed over the RDL and electrically connected with the first conductive pillar; anda second die disposed over the RDL and electrically connected with the second conductive pillar,wherein a height of the second conductive pillar is substantially greater than a height of the first conductive pillar, and a thickness of the first die is substantially greater than a thickness of the second die, a total height of the first conductive pillar and the first die is substantially same as a total height of the second conductive pillar and the second die.2. The semiconductor structure of claim 1 , wherein a distance between the second die and the RDL is substantially greater than a distance ...

Substrate Design with Balanced Metal and Solder Resist Density

A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1. 1. A package comprising: a middle layer selected from the group consisting of a core and a middle metal layer;', 'a first plurality of metal layers overlying the middle layer, wherein the first plurality of metal layers has a first total metal density that is equal to a sum of metal densities of the first plurality of metal layers; and', 'a second plurality of metal layers underlying the middle layer, with a first total count of the first plurality of metal layers equal to a second total count of the second plurality of metal layers, wherein the second plurality of metal layers has a second total metal density that is equal to a sum of metal densities of the second plurality of metal layers, and wherein an absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1., 'a package substrate comprising2. The package of claim 1 , wherein the middle layer is a core layer comprising;a dielectric layer; andconductive pipes penetrating through the dielectric layer, wherein the first plurality of metal layers is electrically coupled to the second plurality of metal layers through the conductive pipes.3. The package of claim 1 , wherein the middle layer comprises a metal layer comprising metal traces claim 1 , wherein the first ...

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar. 1. A semiconductor package , comprising:a first semiconductor die and a second semiconductor die, wherein the first and second semiconductor dies are different types of dies and are disposed side by side;a molding compound, enclosing the first and second semiconductor dies;a heat dissipation module, located directly on and in contact with back sides of the first and second semiconductor dies; andan adhesive material, filled between and contacting the heat dissipation module and the molding compound,wherein the semiconductor package has a central region and a peripheral region surrounding the central region, the first and second semiconductor dies are located within the central region,wherein a sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar with one another,wherein the heat dissipation module comprises a thermal interfacial pattern in contact with the back sides of the first and second semiconductor dies, andwherein the ...

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a redistribution layer, a semiconductor die, conducting connectors, dummy bumps and an underfill. The semiconductor die is disposed on a top surface of the redistribution layer and electrically connected with the redistribution layer. The conducting connectors are disposed between the semiconductor die and the redistribution layer, and are physically and electrically connected with the semiconductor die and the redistribution layer. The dummy bumps are disposed on the top surface of the redistribution layer, beside the conducting connectors and under the semiconductor die. The underfill is disposed between the semiconductor die and the redistribution layer and sandwiched between the dummy bumps and the semiconductor die. The dummy bumps are electrically floating. The dummy bumps are in contact with the underfill without contacting the semiconductor die. 1. A semiconductor package comprising:a redistribution layer;a semiconductor die, disposed on a top surface of the redistribution layer and electrically connected with the redistribution layer;conducting connectors, disposed between the semiconductor die and the redistribution layer, and physically and electrically connected with the semiconductor die and the redistribution layer;dummy bumps, disposed on the top surface of the redistribution layer, beside the conducting connectors and under the semiconductor die; andan underfill, disposed between the semiconductor die and the redistribution layer and sandwiched between the dummy bumps and the semiconductor die,wherein the dummy bumps are electrically floating and the dummy bumps are in contact with the underfill without contacting the semiconductor die.2. The semiconductor package as claimed in claim 1 , wherein the dummy bumps are distributed over a distribution span claim 1 , and the distribution span is partially overlapped with a ...

Semiconductor Packages and Method of Manufacture

A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die. 1. A method comprising:bonding an interconnect device to a first surface of a first metallization pattern, the interconnect device is free of any transistors;bonding a passive device to the first surface of the first metallization pattern, the passive device is free of any active devices;burying the interconnect device and the passive device in a dielectric film;bonding a first device die to a second surface of the first metallization pattern, the second surface is opposite the first surface; andbonding a second device die to the second surface of the first metallization pattern, wherein the interconnect device electrically routes signals between the first device die and the second device die.2. The method of further comprising:forming a through via on the first metallization pattern;burying the through via in the dielectric film; andforming an interconnect structure over the dielectric film, wherein the through via electrically connects the first metallization pattern to the interconnect structure.3. The method of further comprising:bonding a core substrate to an opposing side of the interconnect structure as the dielectric film.4. The method of claim 3 , wherein the core substrate comprises:an insulating core material;a first metal cladding layer on a first side of the insulating core material, wherein the interconnect structure is directly bonded to the first metal cladding layer;a ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A method of manufacturing a semiconductor structure includes the following operations. A substrate is provided. A first conductive pillar, a second conductive pillar arid a third conductive pillar are disposed over the substrate. The first conductive pillar comprises a first height, the second conductive pillar comprises a second height, and the third conductive pillar comprises a third height. A first die is disposed over the first conductive pillar. A second die is disposed over the second conductive pillar. A first surface of the first die and a second surface of the second die are at substantially same level. 1. A method of manufacturing a semiconductor structure , comprising:providing a substrate;disposing a first conductive pillar, a second conductive pillar and a third conductive pillar over the substrate, the first conductive pillar comprising a first height, the second conductive pillar comprising a second height, and the third conductive pillar comprising a third height different from the first height and the second height;disposing a first die over the first conductive pillar, the first die comprising a first surface distal to the substrate; anddisposing a second die over the second conductive pillar, the second die comprising a second surface distal to the substrate, wherein the first surface of the first die and the second surface of the second die are at substantially same level.2. The method of claim 1 , wherein the substrate further comprises a redistribution layer (RDL) disposed over the substrate.3. The method of claim 2 , wherein a distance between the first surface of the first die and the RDL is substantially same as a distance between the second surface of the second die and the RDL.4. The method of claim 1 , wherein the substrate further comprises a via extending through the substrate.5. The method of claim 1 , further comprising disposing an underfill material over the substrate claim 1 , and the underfill material encapsulating the first ...

PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

A package structure includes a redistribution structure and a core substrate. The redistribution structure includes a plurality of connection pads. The core substrate is disposed on the redistribution structure and electrically connected to the plurality of connection pads. The core substrate includes a first interconnection layer and a plurality of conductive terminals. The first interconnection layer has a first region, a second region surrounding the first region, and a third region surrounding the second region, and includes a plurality of bonding pads located in the first region, the second region and the third region. The conductive terminals are electrically connecting the plurality of bonding pads to the plurality of connection pads of the redistribution structure, wherein the plurality of conductive terminals located over the first region, the second region and the third region of the first interconnection layer have different heights. 1. A package structure , comprising:a redistribution structure comprising a plurality of connection pads; a first interconnection layer having a first region, a second region surrounding the first region, and a third region surrounding the second region, wherein the first interconnection layer comprises a plurality of bonding pads located in the first region, the second region and the third region; and', 'a plurality of conductive terminals electrically connecting the plurality of bonding pads to the plurality of connection pads of the redistribution structure, wherein the plurality of conductive terminals located over the first region, the second region and the third region of the first interconnection layer have different heights., 'a core substrate disposed on the redistribution structure and electrically connected to the plurality of connection pads, wherein the core substrate comprises2. The package structure according to claim 1 , wherein the plurality of conductive terminals comprises:a plurality of first conductive ...

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

Provided are a package structure and a method of forming the same. The method includes: laterally encapsulating a device die and an interconnect die by a first encapsulant; forming a redistribution layer (RDL) structure on the device die, the interconnect die, and the first encapsulant; bonding a package substrate onto the RDL structure, so that the RDL structure is sandwiched between the package substrate and the device die, the interconnect die, and the first encapsulant; laterally encapsulating the package substrate by a second encapsulant; and bonding a memory die onto the interconnect die, wherein the memory die is electrically connected to the device die through the interconnect die and the RDL structure.

Semiconductor devices and methods of manufacturing

Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

Protrusion bump pads for bond-on-trace processing

An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion having an exposed top surface, wherein the exposed top surface is recessed from a top surface of the dielectric layer. Furthermore, the bump pad is disposed over and is electrically connected to a second portion of the conductive trace.

Semiconductor apparatus having protrusion bump pads and method for forming the same

實施例的裝置包括晶粒中的介電層、介電層中的導電線路、以及導電線路上的突出凸塊墊。突出凸塊墊至少部分地延伸過介電層，且突出凸塊墊包括長軸與寬軸。長軸的第一尺寸和寬軸的第二尺寸之比值為約0.8至約1.2。

Protrusion bump pads for bond-on-trace processing

An embodiment apparatus includes a dielectric layer in a die, a conductive trace in the dielectric layer, and a protrusion bump pad on the conductive trace. The protrusion bump pad at least partially extends over the dielectric layer, and the protrusion bump pad includes a lengthwise axis and a widthwise axis. A ratio of a first dimension of the lengthwise axis to a second dimension of the widthwise axis is about 0.8 to about 1.2.

Semiconductor structure and manufacturing method thereof

A method of manufacturing a semiconductor structure includes providing a substrate including a redistribution layer (RDL) disposed over the substrate, disposing a first patterned mask over the RDL, disposing a first conductive material over the RDL exposed from the first patterned mask to form a first conductive pillar, removing the first patterned mask, disposing a second patterned mask over the RDL, disposing a second conductive material over the RDL exposed from the second patterned mask to form a second conductive pillar, removing the second patterned mask, disposing a first die over the first conductive pillar, and disposing a second die over the second conductive pillar. A height of the second conductive pillar is substantially greater than a height of the first conductive pillar.

Projecting bump pads for connection-on-line processing

Es werden ein Halbleiterplättchen und ein Substrat bereitgestellt. Das Halbleiterplättchen umfasst zumindest einen integrierten Schaltungschip und das Substrat umfasst eine erste und eine zweite Untergruppe von leitfähigen Säulen, die sich zumindest teilweise durch das Substrat erstrecken. Jede leitfähige Säule der ersten Untergruppe umfasst ein vorstehendes Kontakthöckerpad, das von einer Fläche des Substrats vorsteht, und die leitfähigen Säulen der zweiten Untergruppe bilden jeweils einen Teil einer Leiterbahn, die in die Oberfläche des Substrats eingelassen ist. Das Halbleiterplättchen ist über mehrere leitfähige Kontakthöcker, die sich jeweils zwischen einem der vorstehenden Kontakthöckerpads und dem Halbleiterplättchen erstrecken, mit dem Substrat gekoppelt. A semiconductor die and a substrate are provided. The semiconductor die comprises at least one integrated circuit chip and the substrate comprises a first and a second subset of conductive pillars extending at least partially through the substrate. Each conductive pillar of the first subgroup includes a protrusion bump pad protruding from a surface of the substrate, and the conductive pillars of the second subgroup each form part of a conductive trace embedded in the surface of the substrate. The semiconductor die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the semiconductor die.

Bladeless fan structure

Chip stacking assembly

Semiconductor packages and methods of forming the same

Semiconductor packages and methods of forming the same are disclosed. The semiconductor package includes a plurality of chips, a first molding compound, a first redistribution structure, a second molding compound and a second redistribution structure. The first molding compound encapsulates the chips. The first redistribution structure is disposed over the plurality of chips and the first molding compound. The second molding compound surrounds the first molding compound. The second redistribution structure is disposed over the first redistribution structure, the first molding compound and the second molding compound.

Semiconductor packages and methods of manufacturing the same

Semiconductor packages and methods of forming the same are disclosed. One of the semiconductor packages includes a first redistribution layer structure, a package structure, a bus die and a plurality of connectors. The package structure is disposed over the first redistribution layer structure, and includes a plurality of package components. The bus die and the connectors are encapsulated by a first encapsulant between the package structure and the first redistribution layer structure. The bus die is electrically connected to two or more of the plurality of package components, and the package structure are electrically connected to the first redistribution layer structure through the plurality of connectors.

Semiconductor packages and methods of manufacturing the same

Semiconductor packages and methods of forming the same are disclosed. One of the semiconductor packages includes a circuit board structure, a first redistribution layer structure, a plurality of first bonding elements, a package structure and a plurality of second bonding elements. The first redistribution layer structure is disposed over and electrically connected to the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the circuit board structure. The package structure is disposed over and electrically connected to the first redistribution layer structure. The second bonding elements are disposed between and electrically connected to the first redistribution layer structure and the package structure.

Integrated fan-out package and manufacturing method thereof

An integrated fan-out package includes a die, an encapsulant, a redistribution structure, a plurality of conductive pillars, a seed layer, and a plurality of conductive bumps. The encapsulant encapsulates the die. The redistribution structure is over the die and the encapsulant. The redistribution structure is electrically connected to the die and includes a plurality of dielectric layers that are sequentially stacked and a plurality of conductive patterns sandwiched between the dielectric layers. A Young's modulus of the dielectric layer farthest away from the die is higher than a Young's modulus of each of the rest of the dielectric layers. The conductive patterns are electrically connected to each other. The conductive pillars are disposed on and electrically connected to the redistribution structure. The seed layer is located between the conductive pillars and the redistribution structure. The conductive bumps are disposed on the plurality of conductive pillars.

Semiconductor packages and methods of forming the same

A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a redistribution structure, topmost and bottom conductive terminals. The redistribution structure includes a topmost pad in a topmost dielectric layer, a topmost under-bump metallization (UBM) pattern directly disposed on the topmost pad and the topmost dielectric layer, a bottommost UBM pad embedded in a bottommost dielectric layer, and a bottommost via laterally covered by the bottommost dielectric layer. Bottom surfaces of the topmost pad and the topmost dielectric layer are substantially coplanar, bottom surfaces of the bottommost UBM pad and the bottommost dielectric layer are substantially coplanar, the bottommost via is disposed on a top surface of the bottommost UBM pad, top surfaces of the bottommost via and the bottommost dielectric layer are substantially coplanar. The topmost conductive terminal lands on a recessed top surface of the topmost UBM pattern, and the bottommost conductive terminal lands on the planar bottom surface of the bottommost UBM.

Package structure and fabricating method thereof

A package structure including a redistribution circuit structure, a wiring substrate, a conductive pillar and a solder material is provided. The redistribution circuit structure has a first surface and a second surface opposite to the first surface and includes a first insulating layer and a first redistribution pattern in the insulating layer. The first redistribution pattern comprises a first contact pad disposed at the first surface. The wiring substrate is disposed opposite the first surface of the redistribution circuit structure and includes a second insulating layer and a second redistribution pattern in the second insulating layer. The second redistribution pattern comprises a second contact pad. The conductive pillar is disposed between the first contact pad and the second contact pad. The solder material disposed between the conductive pillar and the second contact pad.

Die corner removal for underfill crack suppression in semiconductor die packaging

A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.

Semiconductor structure and method of manufacturing the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate comprising a recess portion filled with a conductive material; a conductive trace overlying and contacting the conductive material; a conductive pillar disposed on the conductive trace and over the recess portion of the substrate; and a semiconductor chip disposed on the conductive pillar.

Semiconductor packages and method of manufacture

A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.

Semiconductor package and methods of fabricating a semiconductor package

A semiconductor package provided herein includes a package substrate and a semiconductor device. The package substrate includes a redistribution structure, an interconnect structure bonded to the interconnect structure and an insulation material laterally surrounding the interconnect structure, wherein the redistribution structure has a reduced structure and the insulation material fills the reduced structure. The semiconductor device is bonded to the package substrate. In addition, a method of fabricating a semiconductor package is also provided and includes a precut process forming the reduced structure in the redistribution structure of the package substrate.

Semiconductor package and manufacturing method thereof

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

Semiconductor package and manufacturing method thereof

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

Die corner removal for underfill crack suppression in semiconductor die packaging

A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.

Package structure and method of forming the same

Provided are a package structure and a method of forming the same. The method includes: laterally encapsulating a device die and an interconnect die by a first encapsulant; forming a redistribution layer (RDL) structure on the device die, the interconnect die, and the first encapsulant; bonding a package substrate onto the RDL structure, so that the RDL structure is sandwiched between the package substrate and the device die, the interconnect die, and the first encapsulant; laterally encapsulating the package substrate by a second encapsulant; and bonding a memory die onto the interconnect die, wherein the memory die is electrically connected to the device die through the interconnect die and the RDL structure.

Substrate and package structure

According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.

Package structure and method of fabricating the same

A package structure includes a redistribution structure and a core substrate. The redistribution structure includes a plurality of connection pads. The core substrate is disposed on the redistribution structure and electrically connected to the plurality of connection pads. The core substrate includes a first interconnection layer and a plurality of conductive terminals. The first interconnection layer has a first region, a second region surrounding the first region, and a third region surrounding the second region, and includes a plurality of bonding pads located in the first region, the second region and the third region. The conductive terminals are electrically connecting the plurality of bonding pads to the plurality of connection pads of the redistribution structure, wherein the plurality of conductive terminals located over the first region, the second region and the third region of the first interconnection layer have different heights.

Semiconductor Package and Method of Forming the Same

A method includes forming a composite package substrate. The formation of the composite package substrate includes encapsulating an interconnect die in an encapsulant, with the interconnect die including a plurality of through-vias therein, and forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs on opposite sides of the interconnect die. The method further includes bonding an organic package substrate to the composite package substrate, and bonding a first package component and a second package component to the first plurality of RDLs. The first package component and the second package component are electrically interconnected through the interconnect die and the first plurality of RDLs.

Semiconductor structure and manufacturing method thereof

A method of manufacturing a semiconductor structure includes the following operations. A substrate is provided. A first conductive pillar, a second conductive pillar arid a third conductive pillar are disposed over the substrate. The first conductive pillar comprises a first height, the second conductive pillar comprises a second height, and the third conductive pillar comprises a third height. A first die is disposed over the first conductive pillar. A second die is disposed over the second conductive pillar. A first surface of the first die and a second surface of the second die are at substantially same level.

Semiconductor packages and method of manufacture

A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.

Probe card substrate, substrate structure and method of fabricating the same

A substrate structure includes a core substrate, a redistribution layer, a plurality of test pads, a first protective coating, at least one conductive pad and a passive device. The redistribution layer is disposed on and electrically connected to the core substrate. The test pads are disposed over the redistribution layer. The first protective coating is coated on the test pads. The conductive pad is d disposed on the redistribution layer aside the plurality of test pads. The passive device is disposed on and electrically connected to the at least one conductive pad.

Electronic component and manufacturing method thereof

An electronic component includes a board, an electronic device, and a stiffening structure is provided. The electronic device is disposed on the board. The stiffening structure is disposed on the board. The stiffening structure includes a ring portion corresponding the edge of the board. The stiffening structure includes a core base and a cladding layer. The cladding layer covers the core base.

Semiconductor Device Packages and Methods of Forming the Same

Semiconductor device packages and methods of forming the same are discussed. In an embodiment, a device includes: a redistribution structure comprising an upper dielectric layer and an under-bump metallization; a buffer feature on the under-bump metallization and the upper dielectric layer, the buffer feature covering an edge of the under-bump metallization, the buffer feature bonded to the upper dielectric layer; a reflowable connector extending through the buffer feature, the reflowable connector coupled to the under-bump metallization; an interposer coupled to the reflowable connector; and an encapsulant around the interposer and the reflowable connector, the encapsulant different from the buffer feature.

Package structure

A package structure including a redistribution circuit structure, a wiring substrate, first conductive terminals, an insulating encapsulation, and a semiconductor device is provided. The redistribution circuit structure includes stacked dielectric layers, redistribution wirings and first conductive pads. The first conductive pads are disposed on a surface of an outermost dielectric layer among the stacked dielectric layers, the first conductive pads are electrically connected to outermost redistribution pads among the redistribution wirings by via openings of the outermost dielectric layer, and a first lateral dimension of the via openings is greater than a half of a second lateral dimension of the outermost redistribution pads. The wiring substrate includes second conductive pads. The first conductive terminals are disposed between the first conductive pads and the second conductive pads. The insulating encapsulation is disposed on the surface of the redistribution circuit structure. The insulating encapsulation laterally encapsulates the wiring substrate.