Chip array with two-sided cooling

A semiconductor device including a substrate and a die supported thereon. The substrate has at least one electrical connection region on a first portion of a surface of the substrate. The die has a bottom surface portion supported by a second portion of the surface of the substrate. The die also includes a top surface portion comprising a metal layer and a number of semiconductor elements below the metal layer. The top and bottom surface portions of the die are separated by a die body portion which lies above the surface of the substrate. A conforming metal layer extends from at least a portion of the metal layer of the top surface of the die and electrically interfaces with the at least one electrical connection region on the first portion of the surface of the substrate.

III-Nitride device with solderable front metal

Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.

Stacked half-bridge package with a common conductive clip

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe.

Heat dissipating device package

A MOSFET die is mounted onto the bottom surface of a lead frame pad of a lead frame which has increased heat conducting capacity. The pad includes a plurality of at least four integral pins extending therefrom. The lead frame also includes isolated pins which are connected to the MOSFET source and drain using wire bonds. The lead frame and MOSFET are molded in a housing. The pins extend outside the molded housing for external connection, and the pins extending from the lead frame pad provide a path for heat removal from the MOSFET by a heat conduction path formed of the MOSFET drain electrode, the lead frame pad, their interconnection material and the pins.

Three commonly housed diverse semiconductor dice

A semiconductor device includes: at least first, second, and third semiconductor dice, each having opposing surfaces which contain respective electrodes; a conductive lead frame including first and second separate die pad areas, the first and second semiconductor dice being disposed on the first die pad, and the third semiconductor die being disposed on the second die pad; a first plurality of pins being integral with and extending from one edge of the first die pad; a second plurality of pins being integral with and extending from one edge of the second die pad; a third plurality of pins being separated from one another and from the first and second die pads; a first plurality of bonding wires connecting one surface of the first semiconductor die to at least one of the third plurality of pins; a second plurality of bonding wires connecting one surface of the third semiconductor die to at least another one of the third plurality of pins; and a housing for encapsulating the lead frame, semiconductor ...

Semiconductor package

A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.

Interdigitated conductive lead frame or laminate lead frame for GaN die

A GaN die having a plurality of parallel alternating and closely spaced source and drain strips is contacted by parallel coplanar comb-shaped fingers of source and drain pads. A plurality of enlarged area coplanar spaced gate pads having respective fingers contacting the gate contact of the die. The pads may be elements of a lead frame, or conductive areas on an insulation substrate. Other semiconductor die can be mounted on the pads and connected in predetermined circuit arrangements with the GaN die.

Interdigitated Conductive Support for GaN Semiconductor Die

A GaN die having a plurality of parallel alternating and closely spaced source and drain strips is contacted by parallel coplanar comb-shaped fingers of source and drain pads. A plurality of enlarged area coplanar spaced gate pads having respective fingers contacting the gate contact of the die. The pads may be elements of a lead frame, or conductive areas on an insulation substrate. Other semiconductor die can be mounted on the pads and connected in predetermined circuit arrangements with the GaN die.

Stacked half-bridge package with a current carrying layer

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source.

Semiconductor device module with flip chip devices on a common lead frame

The semiconductor portion of a circuit includes a plurality of flip chip devices which are arranged in a planar fashion in a common housing. The plurality of flip chip devices are connected to each other without wire bonding. The common housing includes a packaging structure, the packaging structure including a connective portion and at least one web portion, which aids in the thermal management of the heat emitted by the plurality of flip chip devices and which connects the flip chip devices to each other. Passive devices in the circuit may also be arranged in a planar fashion in the common housing.

Semiconductor package

A semiconductor package including a bidirectional compound semiconductor component and two power semiconductor devices connected in a cascode configuration.

Interdigitated conductive lead frame or laminate lead frame for GaN die

A GaN die having a plurality of parallel alternating and closely spaced source and drain strips is contacted by parallel coplanar comb-shaped fingers of source and drain pads. A plurality of enlarged area coplanar spaced gate pads having respective fingers contacting the gate contact of the die. The pads may be elements of a lead frame, or conductive areas on an insulation substrate. Other semiconductor die can be mounted on the pads and connected in predetermined circuit arrangements with the GaN die.

III-nitride rectifier package

Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing ...

Contact structure for semiconductor device

A power semiconductor package, comprising: a power MOSFET die having a bottom surface with a bottom electrode disposed for contacting a conductor on a support board, and having a top surface with a top electrode; a bump strap which bridges over the power MOSFET die, having mounting portions disposed respectively on opposite sides of the power MOSFET die and disposed for mounting on the support board, and a central portion which engages and is conductively connected to the top electrode of the power MOSFET die. The bottom electrode comprises at least one of a drain electrode and a gate electrode, and the top electrode comprises a source electrode. The bump strap extends upward from the mounting portions to define a respective pair of upper portions of the bump strap which are disposed above the power MOSFET die, the central portion of the bump strap being disposed lower than the upper portions so as to be adjacent to the top electrode of the power MOSFET die.

Stacked half-bridge package

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source.

Copper straps

A copper strap for a semiconductor device package having a contact electrically connected to a die electrode, a leg portion electrically connected to a lead frame, a web portion positioned between the contact and the leg portion and connected to the leg portion and a connection region connecting the web portion to the contact. The contact includes a body having a plurality of formations, each of the plurality of formations having a concavity and an opposing convexity positioned to generally face the die electrode.

Commonly housed diverse semiconductor

A MOSFET die and a Schottky diode die are mounted on a common lead frame pad and their drain and cathode, respectively, are connected together at the pad. The pad has a plurality of pins extending from one side thereof. The lead frame has insulated pins on its opposite side which are connected to the FET source, the FET gate and the Schottky diode anode respectively by wire bonds. The lead frame and die are molded in an insulated housing and the lead frame pins are bent downwardly to define a surface-mount package.

Stacked Half-Bridge Package

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source.

Power semiconductor package with a common conductive clip

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe.

Semiconductor package with multiple conductive clips

One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

III-NITRIDE Device with Solderable Front Metal

Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.

High Power Semiconductor Package with Conductive Clip and Flip Chip Driver IC with Integrated Control Transistor

One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a sync transistor with a top surface having a drain, a flip chip driver integrated circuit (IC) having an integrated control transistor, the flip chip driver IC driving the sync and control transistors, and a conductive clip electrically coupling the drain of the sync transistor to a common portion of the leadframe shared with a control source of the control transistor. In this manner, the leadframe and the conductive clip provide efficient current conduction by direct mechanical connection and large surface area conduction, significantly reducing package electrical resistance, form factor, complexity, and cost compared to conventional packages. Moreover, by integrating only the control transistor rather than both the control and sync transistor within the flip chip driver IC, the sync transistor may remain separate, simplifying manufacture and providing greater total surface area for thermal dissipation. 1. A high power semiconductor package comprising:a sync transistor disposed on a leadframe and including a bottom surface having a sync source and a sync gate and a top surface having a sync drain; a control transistor including a control source and a control gate;', 'a driver integrated circuit (IC) electrically coupled to said sync gate and said control gate;, 'a flip chip disposed on said leadframe, said flip chip comprisinga conductive clip electrically coupling said sync drain to said leadframe, said control source being electrically coupled to said sync drain by a common region of said leadframe.2. The high power semiconductor package of claim 1 , wherein said package does not include a wirebond.3. The high power semiconductor package of claim 1 , wherein said flip chip comprises a ball grid array (BGA) chip.4. The high power semiconductor package of claim 1 , wherein said sync source and said sync gate are arranged into a grid.5. The high ...

Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance

A multichip module has a substrate, which receives several flip chip and for other semiconductor die on one surface and has vias extending through the substrate from the flip chip bottom electrodes to solder ball electrodes on the bottom of the substrate. Passive components are also mounted on the top of the substrate and are connected to further vias which extend to respective ball contacts at the substrate bottom. In one embodiment, the bottom surfaces and electrodes of the die are insulated and their tops (and drain electrodes) are connected by a moldable conductive layer. In another embodiment the top surface of the substrate is covered by an insulation cap, which may be finned for improved thermal properties. The passives are upended to have their longest dimension perpendicular to the substrate surface and are between the fin valleys. The insulation cover is a cap which fits over the top of the substrate, with mold lock depressions contained in the junction between the cap peripheral ...

Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance

A multichip module has a substrate, which receives several flip chip and for other semiconductor die on one surface and has vias extending through the substrate from the flip chip bottom electrodes to solder ball electrodes on the bottom of the substrate. Passive components are also mounted on the top of the substrate and are connected to further vias which extend to respective ball contacts at the substrate bottom. In one embodiment, the bottom surfaces and electrodes of the die are insulated and their tops (and drain electrodes) are connected by a moldable conductive layer. In another embodiment the top surface of the substrate is covered by an insulation cap, which may be finned for improved thermal properties. The passives are upended to have their longest dimension perpendicular to the substrate surface and are between the fin valleys. The insulation cover is a cap which fits over the top of the substrate, with mold lock depressions contained in the junction between the cap peripheral ...

High Power Semiconductor Package with Conductive Clip

One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor, a sync transistor, a driver integrated circuit (IC) for driving the control and sync transistors, and a conductive clip electrically coupling a sync drain of the sync transistor to a first leadframe pad of the package, wherein the first leadframe pad of the package is electrically coupled to a control source of the control transistor using a wirebond. The conductive clip provides an efficient connection between the control source and the sync drain by direct mechanical connection and large surface area conduction. A sync source is electrically and mechanically coupled to a second leadframe pad providing a high current carrying capability, and high reliability. The resulting package has significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections ...

Stacked Half-Bridge Package with a Common Conductive Clip

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe. 1. A stacked half-bridge package comprising:a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC;a sync transistor having a sync drain for connection to said common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by said driver IC;said control and sync transistors being stacked on opposite sides of said common conductive clip, said common conductive clip electrically and mechanically coupling said control source with said sync drain, wherein said common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe.2. The stacked half-bridge package of claim 1 , wherein a conductive web of said common conductive clip provides said electrical and mechanical coupling of said control source with said sync drain.3. The stacked half-bridge package of claim 1 , wherein said conductive leg of said common conductive clip is of a thickness greater than that of said control transistor.4. The stacked half-bridge package ...

High voltage cascoded III-nitride rectifier package with stamped leadframe

Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package with a stamped leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked atop a source of the III-nitride transistor, and a stamped leadframe comprising a first bent lead coupled to a gate of the III-nitride transistor and the anode of the diode, and a second bent lead coupled to a drain of the III-nitride transistor. The bent leads expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.

Copper straps

A copper strap for a semiconductor device package having a contact electrically connected to a die electrode, a leg portion electrically connected to a lead frame, a web portion positioned between the contact and the leg portion and connected to the leg portion and a connection region connecting the web portion to the contact. The contact includes a body having a plurality of formations, each of the plurality of formations having a concavity and an opposing convexity positioned to generally face the die electrode.

Tin antimony solder for MOSFET with TiNiAg back metal

A semiconductor device is disclosed containing a semiconductor die having a trimetal electrode soldered to a substrate by a Sn—Sb solder.

Three commonly housed diverse semiconductor dice

An SO-8 type package contains a control MOSFET die mounted on one lead frame section and a synchronous MOSFET and Schottky diode die is mounted on a second lead frame pad section. The die are interconnected through the lead frame pads and wire bonds to define a buck converter circuit and the die and lead frame pads are overmolded with a common insulation housing.

Semiconductor package with metal straps

A copper strap for a semiconductor device package having a contact electrically connected to a die electrode, a leg portion electrically connected to a lead frame, a web portion positioned between the contact and the leg portion and connected to the leg portion and a connection region connecting the web portion to the contact. The contact includes a body having a plurality of formations, each of the plurality of formations having a concavity and an opposing convexity positioned to generally face the die electrode.

Stacked half-bridge package with a common leadframe

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal.

Solder-on back metal for semiconductor die

A solderable back contact for semiconductor die consists of a titanium layer bonded to the bottom of the die. The free surface of the titanium layer is coated with a copper layer. A soft solder layer joins the bottom of the die to a copper lead frame by first heating the die to below the melting point of the solder, and then ultrasonically “scrubbing” the solder to cause it to bond to the die and lead frame with a minimum sized solder fillet.

Cascoded rectifier package

A semiconductor package that includes a compound component and a diode arranged in a cascode configuration to function as a rectifier.

Bond pad and clip configuration for packaged semiconductor device

A semiconductor device package includes a die pad having a die attach surface, a first lead that is spaced apart and extends away from a first side of the die pad, and a semiconductor die mounted on the die attach surface. The semiconductor die includes a first bond pad disposed on an upper side of the semiconductor die that is opposite the die attach surface. A first clip electrically connects the first lead to the first bond pad. The first bond pad is elongated with first and second longer edge sides that are opposite one another and extend along a length of the first bond pad. The semiconductor die is oriented such that the first and second longer edge sides of the first bond pad are non-parallel to a first current flow direction of the first clip that extends between the first bond pad and the first lead.

Co-packaged MOS-gated device and control integrated circuit

An electronic package for an electronic device includes a substrate. A power transistor die has a lower surface and a upper surface, and the lower surface of the power transistor die is mounted on the substrate. A control circuit for controlling the power transistor is mounted to the upper surface of the power transistor die using an insulating epoxy.

Power Semiconductor Package with a Common Conductive Clip

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe. 140-. (canceled)41. A power semiconductor package comprising:a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate;a sync transistor having a sync drain for connection to said common conductive clip, a sync source coupled to a low voltage input, and a sync gate;said control and sync transistors being situated on opposite sides of said common conductive clip, said common conductive clip coupling said control source with said sync drain.42. The power semiconductor package of claim 41 , wherein a conductive web of said common conductive clip provides said coupling of said control source with said sync drain.43. The power semiconductor package of claim 41 , wherein a conductive leg of said common conductive clip is of a thickness greater than that of said control transistor.44. The power semiconductor package of claim 41 , wherein a control drain leadframe provides connection for said control drain.45. The power semiconductor package of claim 41 , wherein a conductive source clip provides connection between said sync source and a sync source ...

Semiconductor package with metal straps

A copper strap for a semiconductor device package having a contact electrically connected to a die electrode, a leg portion electrically connected to a lead frame, a web portion positioned between the contact and the leg portion and connected to the leg portion and a connection region connecting the web portion to the contact. The contact includes a body having a plurality of formations, each of the plurality of formations having a concavity and an opposing convexity positioned to generally face the die electrode.

BREAKABLE SUBSTRATE FOR SEMICONDUCTOR DIE

In some examples, a device includes a substrate and a conductive pad extending through the substrate, wherein the substrate is coupled to the conductive pad at an interface and the substrate extends laterally from the interface to define a substrate extension. In some examples, the device also includes a semiconductor die mounted on the first side of the substrate. In some examples, the device includes a breakpoint that defines a torque tolerance that is less than a torque tolerance of the device at other points. In some examples, the device is configured to break at the breakpoint in response to force being applied to the substrate extension on the first side of the substrate.

Commonly housed diverse semiconductor

A MOSFET die and a Schottky diode die are mounted on a common lead frame pad and their drain and cathode, respectively, are connected together at the pad. The pad has a plurality of pins extending from one side thereof. The lead frame has insulated pins on its opposite side which are connected to the FET source, the FET gate and the Schottky diode anode respectively by wire bonds. The lead frame and die are molded in an insulated housing and the lead frame pins are bent downwardly to define a surface-mount package.

High current lead electrode for semiconductor device

A semiconductor package that includes a lead frame riveted to pillars electrically connect to an electrode of a semiconductor die.

Multi-chip module

A multi-chip module that includes a conductive element connecting at least two semiconductor devices, the conductive element including enhancements for improving the mechanical coupling between the conductive element and the molded housing of the MCM.

Method for fabricating a semiconductor package

A method for fabricating an IC package that includes depositing conductive adhesive bodies on the leads, and then adhering the electrodes of an IC device to the so disposed conductive adhesive bodies.

Compact high-voltage semiconductor package

There are disclosed herein various implementations of a compact high-voltage semiconductor package. In one exemplary implementation, such a semiconductor package includes a power transistor, as well as a drain contact, a source contact, and a gate contact to provide external connections to the power transistor. The semiconductor package also includes a contour element formed between the drain contact and the source contact in the semiconductor package. The contour element increases a creepage distance between the drain contact and the source contact in the semiconductor package so as to increase a breakdown voltage of the semiconductor package.

Stacked Half-Bridge Package with a Common Leadframe

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal. 120-. (canceled)21. A stacked half-bridge package comprising:a control transistor having a control drain, a control source, and a control gate;a sync transistor having a sync drain, a sync source, and a sync gate;said control and sync transistors being stacked on opposite sides of a common leadframe, said common leadframe serving as an output terminal by coupling said control source with said sync drain.22. The stacked half-bridge package of claim 21 , wherein said common leadframe comprises a web portion and a leg portion.23. The stacked half-bridge package of claim 21 , wherein respective bottom surfaces of said sync transistor and a leg portion of said common leadframe are substantially flush with one another.24. The stacked half-bridge package of claim 21 , wherein a conductive clip provides connection between said control drain and a control drain leadframe.25. The stacked half-bridge package of claim 21 , comprising a conductive clip including a web portion that is coupled to said control drain and including a leg portion that is coupled to a control drain leadframe.26. The stacked half-bridge package of claim 21 , wherein a conductive clip is coupled to said control drain at a topside of said stacked half- ...

High Power Semiconductor Package with Multiple Conductive Clips

One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. 1. A high power semiconductor package comprising:a control transistor disposed on a leadframe and including a bottom surface having a control source and a control gate and a top surface having a control drain;a sync transistor disposed on said leadframe and including a bottom surface having a sync drain and a top surface having a sync source and a sync gate;a driver integrated circuit (IC) disposed on said leadframe and electrically coupled to said control gate and said sync gate;a control transistor conductive clip electrically coupling said control drain to a first pad of said leadframe;a sync transistor conductive clip electrically coupling said sync source to a second pad of said leadframe, said control source being electrically coupled to said sync drain by a common region of said leadframe.2. The high power semiconductor package of claim 1 , wherein said driver IC is electrically coupled to said sync gate using a wirebond.3. The high power semiconductor package of claim 1 , wherein said sync source and said sync gate are arranged into a grid.4. The high power semiconductor package of claim 1 , wherein said package is a leadless package.5. The high power semiconductor package of claim 1 , wherein ...

Method for fabricating a semiconductor package

A method for fabricating an IC package that includes depositing conductive adhesive bodies on the leads, and then adhering the electrodes of an IC device to the so disposed conductive adhesive bodies.

High power semiconductor package with conductive clips and flip chip driver IC

In one implementation, a high power semiconductor package is configured as a buck converter including a control transistor and a sync transistor disposed on a leadframe, a flip chip driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. The source of the control transistor is electrically coupled to the drain of the sync transistor using the leadframe and one of the transistor conductive clips. In this manner, the leadframe and the conductive clips provide efficient current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost.

Method of manufacturing a semiconductor chip array with two-sided cooling

A method of manufacturing a semiconductor device including a substrate and a die supported thereon. The substrate has at least one electrical connection region on a first portion of a surface of the substrate. The die has a bottom surface portion supported by a second portion of the surface of the substrate. The die also includes a top surface portion comprising a metal layer and a number of semiconductor elements below the metal layer. The top and bottom surface portions of the die are separated by a die body portion which lies above the surface of the substrate. A conforming metal layer extends from at least a portion of the metal layer of the top surface of the die and electrically interfaces with the at least one electrical connection region on the first portion of the surface of the substrate.

Semiconductor Package with Conductive Clips

One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadfirame and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. 138-. (canceled)39. A semiconductor package comprising:a control transistor disposed on a leadframe and including a bottom surface having a control source and a control gate and a top surface having a control drain;a sync transistor disposed on said leadframe and including a bottom surface having a sync drain and a top surface having a sync source and a sync gate;a conductive clip electrically coupling said control drain to a first pad of said leadframe, said control source being electrically coupled to said sync drain by a common region of said leadframe;said control gate electrically coupled to a second pad of said leadframe;a driver integrated circuit (IC) disposed on a third pad of said leadframe, said third pad isolated from said common region.40. The semiconductor package of claim 39 , wherein said driver IC is electrically coupled to said sync gate using a wirebond.41. The semiconductor package of claim 39 , wherein said sync source and said sync gate are arranged into a grid.42. The semiconductor package of claim 39 , wherein said semiconductor package is a leadless package.43. The semiconductor package of claim 39 , wherein said conductive clip is attached to said control drain by solder.44. ...

Package for monolithic compound semiconductor (CSC) devices for DC to DC converters

A multichip module defining a dc to dc converter employs a monolithic chip containing at least two III-nitride switches (a monolithic CSC chip) mounted on a conductive lead frame. The CSC chip is copacked with an IC driver for the switches and with the necessary passives. The module defines a buck converter; a boost converter, a buck boost converter, a forward converter and a flyback converter. The drain, source and gate pads of the monolithic CSC chip are connected to a lead frame by solder or epoxy or by bumping attach and a conductive connector or wire bonds connect the switch terminal to lead frame.

Power device with solderable front metal

Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.

Packaging of electronic circuitry

A circuit package includes: electronic circuitry, electrically conductive material forming multiple leads, and multiple connections between the electronic circuitry and the multiple leads. A portion of the electrically conductive material associated with the multiple leads (e.g., low impedance leads supporting high current throughput) is removed to accommodate placement of the electronic circuitry. Each of the multiple leads can support high current. The multiple connections between the, the multiple leads provide connectivity between circuit nodes on the electronic circuitry and pads disposed on a planar surface of the electronic circuit package.

High Power Semiconductor Package with Conductive Clip on Multiple Transistors

One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor, a sync transistor, a driver integrated circuit (IC) for driving the control and sync transistors, and a conductive clip extending from a sync drain on a top surface of the sync transistor to a control source on a top surface of the control transistor. The conductive clip may also connect to substrate pads such as a leadframe pad for current input and output. In this manner, the conductive clip provides an efficient connection between the control source and the sync drain by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. 1. A high power semiconductor package comprising:a control transistor including a control source and a control gate on a top surface thereof, and a control drain on a bottom surface thereof;a sync transistor including a sync drain on a top surface thereof and a sync gate and a sync source on a bottom surface thereof;a driver integrated circuit (IC) electrically coupled to said control gate and said sync gate;a conductive clip extending from said sync drain to said control source, and electrically shorting said sync drain to said control source.2. The high power semiconductor package of claim 1 , wherein said package comprises a buck converter.3. The high power semiconductor package of claim 1 , wherein said conductive clip is attached by solder.4. The high power semiconductor package of claim 1 , wherein said conductive clip is further attached to a first leadframe pad of said package.5. The high power semiconductor package of claim 1 , wherein said package is a leadless package.6. The high power semiconductor package of claim 1 , wherein said driver IC is electrically coupled to said control ...

Stacked Half-Bridge Package with a Current Carrying Layer

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source. 1. A stacked half-bridge package comprising:a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC;a sync transistor having a sync drain for connection to said output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by said driver IC;a current carrying layer situated on said sync drain, said control and sync transistors being stacked on one another, wherein said current carrying layer provides a high current connection between said sync drain and said control source.2. The stacked half-bridge package of claim 1 , wherein an output terminal leadframe provides mechanical and electrical connection for said current carrying layer.3. The stacked half-bridge package of claim 1 , comprising a solderable front metal (SFM) situated on said current carrying layer.4. The stacked half-bridge package of claim 1 , wherein a control drain leadframe provides mechanical and electrical connection for said control drain.5. The stacked half-bridge package of claim 1 , wherein a conductive source clip provides connection between said sync source and a sync source leadframe.6. The stacked half-bridge package ...

High power semiconductor package with conductive clip and flip chip driver IC with integrated control transistor

One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a sync transistor with a top surface having a drain, a flip chip driver integrated circuit (IC) having an integrated control transistor, the flip chip driver IC driving the sync and control transistors, and a conductive clip electrically coupling the drain of the sync transistor to a common portion of the leadframe shared with a control source of the control transistor. In this manner, the leadframe and the conductive clip provide efficient current conduction by direct mechanical connection and large surface area conduction, significantly reducing package electrical resistance, form factor, complexity, and cost compared to conventional packages. Moreover, by integrating only the control transistor rather than both the control and sync transistor within the flip chip driver IC, the sync transistor may remain separate, simplifying manufacture and providing greater total surface ...

III-Nitride Rectifier Package

Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing. 131-. (canceled)32. A high voltage semiconductor package comprising:a package support surface;a III-nitride transistor having a gate, a source, and a drain, said III-nitride transistor attached to said package support surface;a diode having an anode and a cathode, said diode stacked over said III-nitride transistor such that said cathode is coupled to said source;a conductive clip coupled to said drain of said III-nitride transistor;said conductive clip being configured for surface mounting said high voltage semiconductor package.33. The high voltage semiconductor package of further comprising another conductive clip coupled to said gate of said III-nitride transistor and said anode of said diode.34. The high voltage semiconductor package of claim 33 , wherein said another conductive clip is configured for surface mounting said high voltage semiconductor package.35. The high voltage semiconductor package of claim 33 , wherein said conductive clip and said another conductive clip ...

Half-bridge package with a conductive clip

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe.

High voltage cascoded III-nitride rectifier package utilizing clips on package support surface

Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing ...

Semiconductor Package with Heat Spreader

A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.

High power semiconductor package with multiple conductive clips

One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Semiconductor package

A semiconductor package including a bidirectional compound semiconductor component and two power semiconductor devices connected in a cascode configuration.

Semiconductor device module with flip chip devices on a common lead frame

The semiconductor portion of a circuit includes a plurality of flip chip devices which are arranged in a planar fashion in a common housing. The plurality of flip chip devices are connected to each other without wire bonding. The common housing includes a packaging structure, the packaging structure including a connective portion and at least one web portion, which aids in the thermal management of the heat emitted by the plurality of flip chip devices and which connects the flip chip devices to each other. Passive devices in the circuit may also be arranged in a planar fashion in the common housing.

Compact High-Voltage Semiconductor Package

There are disclosed herein various implementations of a compact high-voltage semiconductor package. In one exemplary implementation, such a semiconductor package includes a power transistor, as well as a drain contact, a source contact, and a gate contact to provide external connections to the power transistor. The semiconductor package also includes a contour element formed between the drain contact and the source contact in the semiconductor package. The contour element increases a creepage distance between the drain contact and the source contact in the semiconductor package so as to increase a breakdown voltage of the semiconductor package. 1. A semiconductor package comprising:a power transistor;a drain contact, a source contact, and a gate contact to provide external connections to said power transistor;a contour element formed between said drain contact and said source contact in said semiconductor package;said contour element increasing a creepage distance between said drain contact and said source contact in said semiconductor package so as to increase a breakdown voltage of said semiconductor package.2. The semiconductor package of claim 1 , wherein said contour element is an elongated element traversing substantially an entire length of said semiconductor package.3. The semiconductor package of claim 1 , wherein said contour element comprises a groove formed in a packaging dielectric.4. The semiconductor package of claim 1 , wherein said contour element comprises a ridge in a packaging dielectric.5. The semiconductor package of claim 1 , wherein said power transistor is a composite field-effect transistor (FET) including a group IV FET cascaded with a high-voltage (HV) group III-V transistor.6. The semiconductor package of claim 5 , wherein said HV group III-V transistor is die stacked over said group IV FET.7. The semiconductor package of claim 5 , wherein a drain of said HV group III-V transistor is coupled to said drain contact claim 5 , a source of ...

Stacked half-bridge package

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal.

Stacked half-bridge package with a common conductive leadframe

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal.

Semiconductor Package with Multiple Conductive Clips

One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. 120-. (canceled)21. A semiconductor package comprising:a control transistor disposed on a leadframe and including a bottom surface having a control source and a control gate and a top surface having a control drain;a sync transistor disposed on said leadframe and including a bottom surface having a sync drain and a top surface having a sync source and a sync gate;a conductive clip electrically coupling said sync source to a pad of said leadframe, said control source being electrically coupled to said sync drain by a common region of said leadframe;said driver IC disposed on another pad of said leadframe, said another pad isolated from said common region;said pad disposed on a common side of said leadframe opposite of said another pad.22. The semiconductor package of claim 21 , wherein said driver IC is electrically coupled to said sync gate using a wirebond.23. The semiconductor package of claim 21 , wherein said sync source and said sync gate are arranged into a grid.24. The semiconductor package of claim 21 , wherein said package is a leadless package.25. The semiconductor package of claim 21 , wherein said conductive clip is attached to said sync source by solder.26. The semiconductor package of claim ...

Breakable substrate for semiconductor die

In some examples, a device includes a substrate and a conductive pad extending through the substrate, wherein the substrate is coupled to the conductive pad at an interface and the substrate extends laterally from the interface to define a substrate extension. In some examples, the device also includes a semiconductor die mounted on the first side of the substrate. In some examples, the device includes a breakpoint that defines a torque tolerance that is less than a torque tolerance of the device at other points. In some examples, the device is configured to break at the breakpoint in response to force being applied to the substrate extension on the first side of the substrate.

Semiconductor package with conductive heat spreader

A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.

High Voltage Cascoded III-Nitride Rectifier Package

Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing. 111-. (canceled)12. A method for manufacturing a wire-bondless surface mountable high voltage semiconductor package , said method comprising:attaching, to a package support surface, a III-nitride transistor having a gate, a source, and a drain;stacking over said source of said III-nitride transistor a diode having a cathode and an anode;connecting a first conductive clip to said gate of said III-nitride transistor, said anode of said diode, and said package support surface;connecting a second conductive clip to said drain of said III-nitride transistor and said package support surface;said first conductive clip and second conductive clip each having respective flat portions for surface mounting said high voltage semiconductor package.13. The method of claim 12 , wherein said respective flat portions are substantially coplanar.14. The method of claim 12 , further comprising encapsulating said III-nitride transistor and said diode with a glob-top.15. The method of claim 12 , wherein ...

Multi-chip module

A multi-chip module that includes a conductive element connecting at least two semiconductor devices, the conductive element including enhancements for improving the mechanical coupling between the conductive element and the molded housing of the MCM.

Semiconductor package with conductive clips

One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Stacked Half-Bridge Package

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal. 140-. (canceled)41. A method for manufacturing a stacked half-bridge package , said method comprising:providing a control transistor having a control drain, a control source, and a control gate;providing a sync transistor having a sync drain, a sync source, and a sync gate;stacking said control and sync transistors on opposite sides of a common leadframe, said common leadframe serving as an output terminal by coupling said control source with said sync drain.42. The method of claim 41 , wherein said common leadframe comprises a web portion and a leg portion.43. The method of claim 41 , wherein respective bottom surfaces of said sync transistor and a leg portion of said common leadframe are substantially flush with one another.44. The method of claim 41 , further comprising connecting said control drain to a control drain leadframe by a conductive clip.45. The method of claim 41 , wherein said stacked half-bridge package further comprises a conductive clip including a web portion that is coupled to said control drain and including a leg portion that is coupled to a control drain leadframe.46. The method of claim 41 , further comprising coupling a conductive clip to said control drain at a topside of said stacked ...

High Voltage Cascoded III-Nitride Rectifier Package Utilizing Clips on Package Support Surface

Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing. 1. A wire-bondless surface mountable high voltage semiconductor package comprising:a package support surface;a III-nitride transistor having a gate, a source, and a drain, said III-nitride transistor attached to said package support surface;a diode having an anode and a cathode, said diode stacked over said III-nitride transistor such that said cathode is mechanically and electrically coupled to said source;a first conductive clip connected to said gate of said III-nitride transistor, said anode of said diode, and said package support surface;a second conductive clip connected to said drain of said III-nitride transistor, and said package support surface;said first conductive clip and second conductive clip each having respective flat portions for surface mounting said high voltage semiconductor package.2. The high voltage semiconductor package of claim 1 , wherein said respective flat portions are substantially coplanar.3. The high voltage semiconductor package of claim 1 , ...

Chip array with two-sided cooling

A semiconductor device including a substrate and a die supported thereon. The substrate has at least one electrical connection region on a first portion of a surface of the substrate. The die has a bottom surface portion supported by a second portion of the surface of the substrate. The die also includes a top surface portion comprising a metal layer and a number of semiconductor elements below the metal layer. The top and bottom surface portions of the die are separated by a die body portion which lies above the surface of the substrate. A conforming metal layer extends from at least a portion of the metal layer of the top surface of the die and electrically interfaces with the at least one electrical connection region on the first portion of the surface of the substrate.

Contact structure for semiconductor device

A power semiconductor package, comprising: a power MOSFET die having a bottom surface with a bottom electrode disposed for contacting a conductor on a support board, and having a top surface with a top electrode; a bump strap which bridges over the power MOSFET die, having mounting portions disposed respectively on opposite sides of the power MOSFET die and disposed for mounting on the support board, and a central portion which engages and is conductively connected to the top electrode of the power MOSFET die. The bottom electrode comprises at least one of a drain electrode and a gate electrode, and the top electrode comprises a source electrode. The bump strap extends upward from the mounting portions to define a respective pair of upper portions of the bump strap which are disposed above the power MOSFET die, the central portion of the bump strap being disposed lower than the upper portions so as to be adjacent to the top electrode of the power MOSFET die.

Stacked Half-Bridge Package with a Common Conductive Leadframe

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal. 1. A stacked half-bridge package comprising:a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC;a sync transistor having a sync drain for connection to said output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by said driver IC;said control and sync transistors being stacked on opposite sides of a common conductive leadframe, said common conductive leadframe electrically and mechanically coupling said control source with said sync drain, said common conductive leadframe thereby serving as said output terminal.2. The stacked half-bridge package of claim 1 , wherein said common conductive leadframe comprises a web portion and a leg portion.3. The stacked half-bridge package of claim 1 , wherein said common conductive leadframe comprises a leg portion that is of a thickness greater than said sync transistor.4. The stacked half-bridge package of claim 1 , wherein respective bottom surfaces of said sync transistor and a leg portion of said common conductive leadframe are substantially flush with one another.5. The stacked half-bridge package of ...

High power semiconductor package with conductive clip

One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor, a sync transistor, a driver integrated circuit (IC) for driving the control and sync transistors, and a conductive clip electrically coupling a sync drain of the sync transistor to a first leadframe pad of the package, wherein the first leadframe pad of the package is electrically coupled to a control source of the control transistor using a wirebond. The conductive clip provides an efficient connection between the control source and the sync drain by direct mechanical connection and large surface area conduction. A sync source is electrically and mechanically coupled to a second leadframe pad providing a high current carrying capability, and high reliability. The resulting package has significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections ...

COMPACT HIGH-VOLTAGE SEMICONDUCTOR PACKAGE

There are disclosed herein various implementations of a compact high-voltage semiconductor package. In one exemplary implementation, such a semiconductor package includes a power transistor, as well as a drain contact, a source contact, and a gate contact to provide external connections to the power transistor. The semiconductor package also includes a contour element formed between the drain contact and the source contact in the semiconductor package. The contour element increases a creepage distance between the drain contact and the source contact in the semiconductor package so as to increase a breakdown voltage of the semiconductor package. 110-: (canceled)11: A semiconductor package comprising:first and second power transistors;first and second drain contacts, first and second source contacts, and first and second gate contacts to provide respective external connections to said first and second power transistors;a first contour element formed between said first drain contact and said first source contact in said semiconductor package;a second contour element formed between said second drain contact and said second source contact in said semiconductor package;said first contour element increasing a first creepage distance between said first drain contact and said first source contact in said semiconductor package so as to increase a breakdown voltage of said semiconductor package;said second contour element increasing a second creepage distance between said second drain contact and said second source contact in said semiconductor package so as to increase said breakdown voltage of said semiconductor package.12: The semiconductor package of claim 11 , wherein at least one of said first contour element and said second contour element comprises a groove fanned in a packaging dielectric.13: The semiconductor package of claim 11 , wherein at least one of said first contour element and said second contour element comprises a ridge in a packaging dielectric.14: The ...

Semiconductor Package with Conductive Heat Spreader

A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.

High Power Semiconductor Package with Conductive Clips and Flip Chip Driver IC

One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a leadframe, a flip chip driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. The source of the control transistor is electrically coupled to the drain of the sync transistor using the leadframe and one of the transistor conductive clips. In this manner, the leadframe and the conductive clips provide efficient current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. 1. A high power semiconductor package comprising:a control transistor disposed on a leadframe and including a bottom surface having a control source and a control gate and a top surface having a control drain;a sync transistor disposed on said leadframe and including a bottom surface having a sync source and a sync gate and a top surface having a sync drain;a flip chip driver integrated circuit (IC) disposed on said leadframe and electrically coupled to said control gate and said sync gate;a control transistor conductive clip electrically coupling said control drain to a first pad of said leadframe;a sync transistor conductive clip electrically coupling said sync drain to a second pad of said leadframe, said control source being disposed on said second pad of said leadframe to electrically couple said control source to said sync drain.2. The high power semiconductor package of claim 1 , wherein said package is a leadless package.3. The high power semiconductor package of claim 1 , wherein said package does not include a wirebond.4. The high power semiconductor ...

High current lead electrode for semiconductor device

A semiconductor package that includes a lead frame riveted to pillars electrically connect to an electrode of a semiconductor die.

Insertable Power Unit with Mounting Contacts for Plugging into a Mother Board

In one implementation, an insertable power unit for plugging into a mother board includes a power module situated on a substrate, and a mounting contact on an extended side of the substrate away from the power module. The mounting contact is electrically coupled to the power module by electrical routing in the substrate. The mounting contact is configured to provide electrical connection between the power module and the mother board. 1. An insertable power unit for plugging into a mother board , said insertable power unit comprising:a power module situated on a substrate;said substrate having a mounting contact on an extended side of said substrate away from said power module;said mounting contact being electrically coupled to said power module by an electrical routing in said substrate;said mounting contact configured to provide electrical connection between said power module and said mother board.2. The insertable power unit of claim 1 , wherein said substrate comprises a printed circuit board (PCB) configured as a daughter board.3. The insertable power unit of claim 1 , wherein said extended side of said substrate is on an end of said substrate for end-mounting on said mother board.4. The insertable power unit of claim 1 , wherein said extended side of said substrate is on an edge of said substrate for edge-mounting on said mother board.5. The insertable power unit of claim 1 , wherein said substrate further comprises at least one through-substrate via.6. The insertable power unit of claim 1 , wherein said power module comprises a voltage converter including at least one silicon power transistor.7. The insertable power unit of claim 1 , wherein said power module comprises a voltage converter including at least one III-Nitride power transistor.8. The insertable power unit of claim 1 , wherein said power module comprises a buck converter.9. An insertable power unit for plugging into a mother board claim 1 , said insertable power unit comprising:a power module ...

Power Device with Solderable Front Metal

Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.

Three commonly housed diverse semiconductor dice

An SO-8 type package contains a control MOSFET die mounted on one lead frame section and a synchronous MOSFET and Schottky diode die is mounted on a second lead frame pad section. The die are interconnected through the lead frame pads and wire bonds to define a buck converter circuit and the die and lead frame pads are overmolded with a common insulation housing.

III-nitride power device with solderable front metal

Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.

PACKAGE FOR MONOLITHIC COMPOUND SEMICONDUCTOR (CSC) DEVICES FOR DC TO DC CONVERTERS

A multichip module defining a dc to dc converter employs a monolithic chip containing at least two III-nitride switches (a monolithic CSC chip) mounted on a conductive lead frame. The CSC chip is copacked with an IC driver for the switches and with the necessary passives. The module defines a buck converter; a boost converter, a buck boost converter, a forward converter and a flyback converter. The drain, source and gate pads of the monolithic CSC chip are connected to a lead frame by solder or epoxy or by bumping attach and a conductive connector or wire bonds connect the switch terminal to lead frame.

Semiconductor package with heat spreader

A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.

Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance

A multichip module has a substrate, which receives several flip chip and for other semiconductor die on one surface and has vias extending through the substrate from the flip chip bottom electrodes to solder ball electrodes on the bottom of the substrate. Passive components are also mounted on the top of the substrate and are connected to further vias which extend to respective ball contacts at the substrate bottom. In one embodiment, the bottom surfaces and electrodes of the die are insulated and their tops (and drain electrodes) are connected by a moldable conductive layer. In another embodiment the top surface of the substrate is covered by an insulation cap, which may be finned for improved thermal properties. The passives are upended to have their longest dimension perpendicular to the substrate surface and are between the fin valleys. The insulation cover is a cap which fits over the top of the substrate, with mold lock depressions contained in the junction between the cap peripheral interior edge and the substrate mating edge surfaces.

METHOD OF PROCESSING A SEMICONDUCTOR WAFER, SEMICONDUCTOR DIE, AND METHOD OF PRODUCING A SEMICONDUCTOR MODULE

A method of processing a semiconductor wafer includes: forming an electronic device at each die location of the semiconductor wafer; partially forming a frontside metallization over a frontside of the semiconductor wafer at each die location; partially forming a backside metallization over a backside of the semiconductor wafer at each die location; and after partially forming both the frontside metallization and the backside metallization but without completing either the frontside metallization or the backside metallization, singulating the semiconductor wafer between the die locations to form a plurality of individual semiconductor dies, wherein the partially formed frontside metallization and the partially formed backside metallization have a same composition. Semiconductor dies and methods of producing semiconductor modules are also described.

Cascoded rectifier package

A semiconductor package that includes a compound component and a diode arranged in a cascode configuration to function as a rectifier.

Tin antimony solder for MOSFET with TiNiAg back metal

A semiconductor device is disclosed containing a semiconductor die having a trimetal electrode soldered to a substrate by a Sn-Sb solder.

Power Unit with Conductive Slats

In one implementation, a power unit for plugging into a mother board includes a power module situated on a substrate. The substrate is situated on conductive slats, each having an extended end away from the power module. Each of the conductive slats provides a mounting contact of the power unit. Each mounting contact is electrically coupled to the power module by electrical routing in the substrate. The mounting contacts are configured to provide electrical connection between the power module and the mother board. 1. A power unit for plugging into a mother board , said power unit comprising:a power module situated on a substrate;said substrate being situated on a plurality of conductive slats each having an extended end away from said power module;each said extended end of said plurality of conductive slats being a mounting contact;each said mounting contact being electrically coupled to said power module by an electrical routing in said substrate;each said mounting contact configured to provide electrical connection between said power module and said mother board.2. The power unit of claim 1 , wherein said substrate comprises a printed circuit board (PCB) configured as a daughter board.3. The power unit of claim 1 , wherein said substrate comprises a molded interconnect system (MIS).4. The power unit of claim 1 , wherein each said mounting contact is at an end of said substrate for end-mounting on said mother board.5. The power unit of claim 1 , wherein each said mounting contact is at an edge of said substrate for edge-mounting on said mother board.6. The power unit of claim 1 , wherein said plurality of conductive slats are part of a lead frame.7. The power unit of claim 1 , wherein said power module comprises a voltage converter including at least one silicon power transistor.8. The power unit of claim 1 , wherein said power module comprises a voltage converter including at least one III-Nitride power transistor.9. The power unit of claim 1 , wherein said power ...

High Voltage Cascoded III-Nitride Rectifier Package with Stamped Leadframe

Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package with a stamped leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked atop a source of the III-nitride transistor, and a stamped leadframe comprising a first bent lead coupled to a gate of the III-nitride transistor and the anode of the diode, and a second bent lead coupled to a drain of the III-nitride transistor. The bent leads expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.

Half-Bridge Package with a Conductive Clip

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe.

Commonly housed diverse semiconductor die

A MOSFET die and a Schottky diode die are mounted on a common lead frame pad and their drain and cathode, respectively, are connected together at the pad. The pad has a plurality of pins extending from one side thereof. The lead frame has insulated pins on its opposite side which are connected to the FET source, the FET gate and the Schottky diode anode respectively by wire bonds. The lead frame and die are molded in an insulated housing and the lead frame pins are bent downwardly to define a surface-mount package.

III-Nitride Transistor with Solderable Front Metal

Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson. 160-. (canceled)61. A III-nitride semiconductor device comprising:a source and a drain over a III-nitride layer;a first metal layer over said III-nitride layer, said first metal layer including a source contact over said source;a via connecting said source contact to a second metal layer situated over said first metal layer;a solderable front metal over said second metal layer.62. The III-nitride semiconductor device of claim 61 , wherein said first metal layer includes a drain contact over said drain.63. The III-nitride semiconductor device of claim 62 , wherein said solderable front metal comprises spaced elongated digits configured for external circuit connection.64. The III-nitride semiconductor device of claim 61 , wherein said solderable front metal comprises solder bars.65. The III-nitride semiconductor device of claim 61 , wherein said III-nitride semiconductor device is a high electron mobility transistor (HEMT).66. The III-nitride semiconductor device of claim 63 , wherein said spaced elongated digits alternately expose said source contact and said drain contact.67. The III-nitride semiconductor device of claim 63 , comprising a first transistor and a second transistor ...

High Voltage Cascoded III-Nitride Rectifier Package with Etched Leadframe

Some exemplary embodiments of high voltage cascaded III-nitride semiconductor package with an etched leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked over a source of the III-nitride transistor, and a leadframe that is etched to form a first leadframe paddle portion coupled to a gate of the III-nitride transistor and the anode of the diode, and a second leadframe paddle portion coupled to a drain of the III-nitride transistor. The leadframe paddle portions enable the package to be surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.

Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance

A multichip module has a substrate, which receives several flip chip and for other semiconductor die on one surface and has vias extending through the substrate from the flip chip bottom electrodes to solder ball electrodes on the bottom of the substrate. Passive components are also mounted on the top of the substrate and are connected to further vias which extend to respective ball contacts at the substrate bottom. In one embodiment, the bottom surfaces and electrodes of the die are insulated and their tops (and drain electrodes) are connected by a moldable conductive layer. In another embodiment the top surface of the substrate is covered by an insulation cap, which may be finned for improved thermal properties. The passives are upended to have their longest dimension perpendicular to the substrate surface and are between the fin valleys. The insulation cover is a cap which fits over the top of the substrate, with mold lock depressions contained in the junction between the cap peripheral ...

High power semiconductor package with conductive clip on multiple transistors

In one implementation, a high power semiconductor package is configured as a buck converter including a control transistor, a sync transistor, a driver integrated circuit (IC) for driving the control and sync transistors, and a conductive clip extending from a sync drain on a top surface of the sync transistor to a control source on a top surface of the control transistor. The conductive clip may also connect to substrate pads such as a leadframe pad for current input and output. In this manner, the conductive clip provides an efficient connection between the control source and the sync drain by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost.

Bond Pad and Clip Configuration for Packaged Semiconductor Device

A semiconductor device package includes a die pad having a die attach surface, a first lead that is spaced apart and extends away from a first side of the die pad, and a semiconductor die mounted on the die attach surface. The semiconductor die includes a first bond pad disposed on an upper side of the semiconductor die that is opposite the die attach surface. A first clip electrically connects the first lead to the first bond pad. The first bond pad is elongated with first and second longer edge sides that are opposite one another and extend along a length of the first bond pad. The semiconductor die is oriented such that the first and second longer edge sides of the first bond pad are non-parallel to a first current flow direction of the first clip that extends between the first bond pad and the first lead.

Semiconductor package

A semiconductor package including a bidirectional compound semiconductor component and two power semiconductor devices connected in a cascode configuration.

Compact power semiconductor package

There are disclosed herein various implementations of a compact high-voltage semiconductor package. In one exemplary implementation, such a semiconductor package includes a power transistor, as well as a drain contact, a source contact, and a gate contact to provide external connections to the power transistor. The semiconductor package also includes a contour element formed between the drain contact and the source contact in the semiconductor package. The contour element increases a creepage distance between the drain contact and the source contact in the semiconductor package so as to increase a breakdown voltage of the semiconductor package.

Power unit with conductive slats

In one implementation, a power unit for plugging into a mother board includes a power module situated on a substrate. The substrate is situated on conductive slats, each having an extended end away from the power module. Each of the conductive slats provides a mounting contact of the power unit. Each mounting contact is electrically coupled to the power module by electrical routing in the substrate. The mounting contacts are configured to provide electrical connection between the power module and the mother board.

Stacked half-bridge package with a current carrying layer

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source.

High voltage cascoded III-nitride rectifier package comprising conductive clips between electrodes of components and the surface of a package support member

Interdigitated conductive lead frame or laminate lead frame for gan die

A GaN die having a plurality of parallel alternating and closely spaced source and drain strips is contacted by parallel coplanar comb-shaped fingers of source and drain pads. A plurality of enlarged area coplanar spaced gate pads having respective fingers contacting the gate contact of the die. The pads may be elements of a lead frame, or conductive areas on an insulation substrate. Other semiconductor die can be mounted on the pads and connected in predetermined circuit arrangements with the GaN die.

Verfahren zum bearbeiten eines halbleiterwafers, halbleiterchips und verfahren zum herstellen eines halbleitermoduls

Ein Verfahren zum Bearbeiten eines Halbleiterwafers (100) weist auf: Bilden einer elektronischen Vorrichtung (102) an jeder Chipstelle (104) des Halbleiterwafers (100); teilweises Bilden einer Vorderseitenmetallisierung (110) über einer Vorderseite (112) des Halbleiterwafers (100) an jeder Chipstelle (104); teilweises Bilden einer Rückseitenmetallisierung (114) über einer Rückseite (116) des Halbleiterwafers (100) an jeder Chipstelle (104); und nach dem teilweisen Ausbilden sowohl der Vorderseitenmetallisierung (110) als auch der Rückseitenmetallisierung (114), jedoch ohne die Vorderseitenmetallisierung (110) oder die Rückseitenmetallisierung (114) zu vervollständigen, Vereinzeln des Halbleiterwafers (100) zwischen den Chipstellen (104), um eine Vielzahl von einzelnen Halbleiterchips (122) zu bilden, wobei die teilweise ausgebildete Vorderseitenmetallisierung (110) und die teilweise ausgebildete Rückseitenmetallisierung (114) dieselbe Zusammensetzung aufweisen. Halbleiterchips (122) und Verfahren zum Herstellen von Halbleitermodulen werden ebenfalls beschrieben.

打抜きリードフレームを備えるカスコード接続された高電圧ｉｉｉ族窒化物整流器パッケージ

【課題】カスコード接続された高電圧III族窒化物整流器を一体化するパッケージの効率的な製造方法を提供する。 【解決手段】III族窒化物トランジスタ２３０の上にスタックしたダイオード２２０のアノードと、III族窒化物トランジスタのゲートおよびダイオードのアノードに結合した第１の屈曲リード２１２ｂおよびIII族窒化物トランジスタのドレインに結合した第２の屈曲リード２１２ａを含む打抜きリードフレームとを有するIII族窒化物トランジスタからなる。これら屈曲リードは、それぞれ表面実装用の平担部を露出する。 【選択図】図２Ｎ

Stacked half-bridge package with a common conductive clip

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe.

Stacked half-bridge package with a common conductive clip

Semiconductor package

Compact high-voltage semiconductor package

There are disclosed herein various implementations of a compact high-voltage semiconductor package. In one exemplary implementation, such a semiconductor package includes a power transistor, as well as a drain contact, a source contact, and a gate contact to provide external connections to the power transistor. The semiconductor package also includes a contour element formed between the drain contact and the source contact in the semiconductor package. The contour element increases a creepage distance between the drain contact and the source contact in the semiconductor package so as to increase a breakdown voltage of the semiconductor package.