Настройки

Укажите год
-

Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

Подробнее
-

Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

Подробнее

Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Укажите год
Укажите год

Применить Всего найдено 10676. Отображено 100.
12-01-2012 дата публикации

Heat dissipating material and semiconductor device using same

Номер: US20120007017A1

Disclosed is a heat dissipating material which is interposed between a heat-generating electronic component and a heat dissipating body. This heat dissipating material contains (A) 100 parts by weight of a silicone gel cured by an addition reaction having a penetration of not less than 100 (according to ASTM D 1403), and (B) 500-2000 parts by weight of a heat conductive filler. Also disclosed is a semiconductor device comprising a heat-generating electronic component and a heat dissipating body, wherein the heat dissipating material is interposed between the heat-generating electronic component and the heat dissipating body.

Подробнее
02-02-2012 дата публикации

Power Semiconductor Module, Method for Producing a Power Semiconductor Module and a Housing Element for a Power Semiconductor Module

Номер: US20120025393A1
Принадлежит: INFINEON TECHNOLOGIES AG

A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug.

Подробнее
09-02-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120032323A1
Принадлежит: Renesas Electronics Corp

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

Подробнее
09-02-2012 дата публикации

Systems and Methods for Heat Dissipation Using Thermal Conduits

Номер: US20120032350A1
Принадлежит: Conexant Systems LLC

The addition of thermal conduits by bonding bond wires to bond pads either in a wire loop configuration or a pillar configuration can improve thermal dissipation of a fabricated die. The thermal conduits can be added as part of the normal packaging process of a semiconductor die and are electrically decoupled from the circuitry fabricated on the fabricated die. In an alternative, a dummy die is affixed to the fabricated die and the thermal conduits are affixed to the dummy die. Additionally, thermal conduits can be used in conjunction with a heat spreader.

Подробнее
01-03-2012 дата публикации

Semiconductor structure having conductive vias and method for manufacturing the same

Номер: US20120049347A1
Автор: Meng-Jen Wang
Принадлежит: Advanced Semiconductor Engineering Inc

A semiconductor structure includes a plurality of thermal vias and a heat dissipation layer disposed at a periphery of a back surface of a lower chip in a stacked-chip package. This arrangement improves solderability of a subsequently-bonded heat sink. Additionally, the thermal vias and the heat dissipation layer provide an improved thermal conduction path for enhancing heat dissipation efficiency of the semiconductor structure. A method for manufacturing the semiconductor structure is also provided.

Подробнее
15-03-2012 дата публикации

Semiconductor chip device with polymeric filler trench

Номер: US20120061852A1

A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Подробнее
22-03-2012 дата публикации

Substrate bonding with metal germanium silicon material

Номер: US20120068325A1
Принадлежит: FREESCALE SEMICONDUCTOR INC

In one embodiment, a semiconductor structure including a first substrate, a semiconductor device on the first substrate, a second substrate, and a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate. The conductive bond comprises metal, silicon, and germanium. A percentage by atomic weight of silicon in the conductive bond is greater than 5%.

Подробнее
22-03-2012 дата публикации

Semiconductor device having semiconductor member and mounting member

Номер: US20120068362A1
Автор: Syuuichi Kariyazaki
Принадлежит: Renesas Electronics Corp

A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased.

Подробнее
03-05-2012 дата публикации

Semiconductor package and manufacturing method thereof

Номер: US20120104571A1
Автор: Jin O. YOO
Принадлежит: Samsung Electro Mechanics Co Ltd

There are provided a semiconductor package including an electromagnetic shielding structure having excellent electromagnetic interference (EMI) and electromagnetic susceptibility (EMS) characteristics, while protecting individual elements in an inner portion thereof from impacts, and a manufacturing method thereof. The semiconductor package includes: a substrate having ground electrodes formed on an upper surface thereof; at least one electronic component mounted on the upper surface of the substrate; an insulating molding part including an internal space in which the electronic component is accommodated, and fixed to the substrate such that at least a portion of the ground electrode is externally exposed; and a conductive shield part closely adhered to the molding part to cover an outer surface of the molding part and electrically connected to the externally exposed ground electrodes.

Подробнее
03-05-2012 дата публикации

Semiconductor package module

Номер: US20120104572A1
Автор: Jin O. YOO
Принадлежит: Samsung Electro Mechanics Co Ltd

There is provided a semiconductor package module capable of minimizing a thickness of the module in spite of including an electronic element having a large size. The semiconductor package module includes: a semiconductor package having a shield formed on an outer surface and a side thereof and at least one receiving part provided in a lower surface thereof, the receiving part having a groove shape; and a main substrate having at least one large element and the semiconductor package mounted on one surface thereof, wherein the large element is received in the receiving part of the semiconductor package and is mounted on the main substrate.

Подробнее
24-05-2012 дата публикации

System comprising a semiconductor device and structure

Номер: US20120129301A1
Принадлежит: Monolithic 3D Inc

A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

Подробнее
14-06-2012 дата публикации

Method to prevent metal pad damage in wafer level package

Номер: US20120149152A1

The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a bonding pad on a first substrate; forming wiring pads on the first substrate; forming a protection material layer on the first substrate, on sidewalls and top surfaces of the wiring pads, and on sidewalls of the bonding pad, such that a top surface of the bonding pad is at least partially exposed; bonding the first substrate to a second substrate through the bonding pad; opening the second substrate to expose the wiring pads; and removing the protection material layer.

Подробнее
28-06-2012 дата публикации

Method of bonding metal and glass using optical contact bonding, method of manufacturing display apparatus using the method of bonding, and display apparatus manufactured by the method of bonding

Номер: US20120161177A1
Автор: Joon-Hyung Kim
Принадлежит: Samsung Mobile Display Co Ltd

A method of bonding metal and glass using an optical contact bonding includes depositing an optical contact bonding medium on a surface of a metal substrate; and bonding the metal substrate on which the optical contact bonding medium is formed to a glass substrate using optical contact bonding.

Подробнее
02-08-2012 дата публикации

Power module and the method of packaging the same

Номер: US20120194148A1
Принадлежит: XinTec Inc

A power module includes a substrate; a conductive path layer formed on the substrate with a specific pattern as an inductor; a connection layer being formed on the substrate and electrically connected to a first terminal of the inductor; and a first transistor, electrically mounted on the substrate through the connection layer.

Подробнее
16-08-2012 дата публикации

Anodic bonding apparatus, method of manufacturing package, piezoelectric vibrator, oscillator, electronic apparatus, and radio timepiece

Номер: US20120206998A1
Принадлежит: Seiko Instruments Inc

An anodic bonding apparatus includes a first intermediate member that is disposed between an upper surface (an outer surface) of a lead substrate wafer and a first heater, has heat conductivity, and can be flexible; and a second intermediate member that is disposed between a lower surface (an outer surface) of a base substrate wafer and a second heater, has conductivity and heat conductivity, and can be flexible, wherein the first intermediate member is formed so that a central portion thereof bulges toward the base substrate wafer further than a periphery portion thereof, and the second intermediate member is formed so that a central portion thereof bulges toward the lead substrate wafer further than a periphery portion thereof, and, the first intermediate member and the second intermediate member are evenly deformed.

Подробнее
30-08-2012 дата публикации

Heat radiation material, electronic device and method of manufacturing electronic device

Номер: US20120218713A1
Принадлежит: Fujitsu Ltd

The electronic device includes a heat generator 54, a heat radiator 58, and a heat radiation material 56 disposed between the heat generator 54 and the heat radiator 58 and including a plurality of linear structures 12 of carbon atoms and a filling layer 14 formed of a thermoplastic resin and disposed between the plurality of linear structures 12.

Подробнее
20-09-2012 дата публикации

Manufacturing method of semiconductor device, and semiconductor device

Номер: US20120235308A1
Автор: Noriyuki Takahashi
Принадлежит: Renesas Electronics Corp

To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.

Подробнее
27-09-2012 дата публикации

Semiconductor Device and Method of Forming a Thermally Reinforced Semiconductor Die

Номер: US20120241941A1
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device includes a substrate with conductive traces. A semiconductor die is mounted with an active surface oriented toward the substrate. An underfill material is deposited between the semiconductor die and substrate. A recess is formed in an interior portion of the semiconductor die that extends from a back surface of the semiconductor die opposite the active surface partially through the semiconductor die such that a peripheral portion of the back surface of the semiconductor die is offset with respect to a depth of the recess. A thermal interface material (TIM) is deposited over the semiconductor die and into the recess such that the TIM in the recess is laterally supported by the peripheral portion of the semiconductor die to reduce flow of the TIM away from the semiconductor die. A heat spreader including protrusions is mounted over the semiconductor die and contacts the TIM.

Подробнее
27-09-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120241942A1
Автор: Takumi Ihara
Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate. A heat radiator is disposed on the heat conductive member. The heat conductive member thermally connecting the semiconductor element to the heat radiator reduces the risk that electromagnetic noise may be emitted from or may be incident on the semiconductor element.

Подробнее
25-10-2012 дата публикации

Sealed electronic housing and method for the sealed assembly of such a housing

Номер: US20120266462A1
Принадлежит: Thales SA

Method for the sealed assembly of an electronic housing containing one or more electronic components, the method including: assembling the housing by bringing a support, to which the electronic components are fixed, in contact with a cover by means of a mixture including a paste and nanoparticles in suspension in said paste, the size of the nanoparticles ranging from 10 to 30 nm; and closing the housing in a sealed manner by heating the housing to a temperature T of between 150° C. and 180° C. making it possible to sinter the metal nanoparticles, while subjecting the housing to a pressure greater than 2.5×10 5 Pa.

Подробнее
29-11-2012 дата публикации

Electronic component and production method thereof

Номер: US20120299665A1
Принадлежит: TAIYO YUDEN CO LTD

A production method of an electronic component includes: forming a sheet having a resin layer and a metal layer formed under the resin layer; bonding the sheet to a substrate so that the metal layer is arranged on a functional portion of an acoustic wave element formed on the substrate, a frame portion surrounding the functional portion is formed between the metal layer and the substrate, a cavity is formed on the functional portion by the metal layer and the frame portion, and the resin layer covers the metal layer and the frame portion.

Подробнее
31-01-2013 дата публикации

Saw device, saw oscillator, and electronic apparatus

Номер: US20130027144A1
Принадлежит: Seiko Epson Corp

A SAW device includes a SAW chip formed of a piezoelectric substrate and an IDT formed thereon, a base substrate that supports the SAW chip, and a fixing member that fixes the SAW chip to the base substrate. The SAW chip that forms a cantilever is supported by the base substrate via the fixing member in a position where the IDT does not overlap with the fixing member in a plan view of the SAW chip. The length W of the SAW chip in a y-axis direction and the length D of the fixing member in the y-axis direction satisfy 1<D/W1≦1.6. The fixing member bonds the lower surface and side surfaces of the fixed end of the SAW chip to the base substrate.

Подробнее
14-03-2013 дата публикации

Semiconductor device including cladded base plate

Номер: US20130062750A1
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device includes a semiconductor chip coupled to a substrate and a base plate coupled to the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure.

Подробнее
11-04-2013 дата публикации

Power management applications of interconnect substrates

Номер: US20130087366A1
Принадлежит: Volterra Semiconductor LLC

Various applications of interconnect substrates in power management systems are described.

Подробнее
16-05-2013 дата публикации

Miniaturized Electrical Component Comprising an MEMS and an ASIC and Production Method

Номер: US20130119492A1
Принадлежит: EPCOS AG

The invention relates to a miniaturized electrical component comprising an MEMS chip and an ASIC chip. The MEMS chip and the ASIC chip are disposed on top of each other; an internal mounting of MEMS chip and ASIC chip is connected to external electrical terminals of the electrical component by means of vias through the MEMS chip or the ASIC chip.

Подробнее
30-05-2013 дата публикации

Solid-state imaging device and imaging apparatus

Номер: US20130135505A1
Автор: Shinji Yoshida
Принадлежит: Panasonic Corp

A solid-state imaging device includes an imaging region having pixel units two-dimensionally arranged, each of the pixel units including a photoelectric converting device formed on a semiconductor substrate. The solid-state imaging device includes: an interlayer film made of a dielectric and formed above the photoelectric converting device; a light attenuation filter which is formed above the interlayer film for each of the pixel units or for each of pixel blocks, and changes a transmittance of light when a voltage is applied to the light attenuation filter, the pixel blocks each including a plurality of the pixel units; and a selecting transistor which is formed in the semiconductor substrate for each of the light attenuation filters, and connects or disconnects a path for applying the voltage to the light attenuation filter.

Подробнее
08-08-2013 дата публикации

Package manufacturing method and semiconductor device

Номер: US20130200505A1
Автор: Koji Ono
Принадлежит: Canon Inc

A method for manufacturing a package comprises a first step of forming a metal pattern including a frame and a plurality of leads extending inward from the frame, a second step of molding a resin pattern including a first resin portion which holds the plurality of leads from an inner side thereof, and second resin portions which cover bottom surfaces of peripheral portions, adjacent to portions to be removed, in the plurality of leads while exposing bottom surfaces of the portions to be removed in the plurality of leads, so as to hold the plurality of leads from a lower side thereof, and a third step of cutting the plurality of leads into a plurality of first leads and a plurality of second leads by removing the portions to be removed in the plurality of leads while the resin pattern keeps holding the peripheral portions in the plurality of leads.

Подробнее
05-09-2013 дата публикации

Workpiece with Semiconductor Chips, Semiconductor Device and Method for Producing a Workpiece with Semiconductor Chips

Номер: US20130228904A1
Принадлежит: Intel Mobile Communications GmbH

A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

Подробнее
19-09-2013 дата публикации

Magnetoresistive random access memory (mram) package including a multilayer magnetic security structure

Номер: US20130241014A1
Принадлежит: Honeywell International Inc

A magnetoresistive random access memory (MRAM) package may include an MRAM die, a package defining a cavity and an exterior surface, and a magnetic security structure disposed within the cavity or on the exterior surface of the package. The MRAM die may be disposed in the cavity of the package, and the magnetic security structure may include at least three layers including a permanent magnetic layer and a soft magnetic layer.

Подробнее
26-09-2013 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20130249084A1
Принадлежит: Renesas Electronics Corp

A semiconductor device includes an interlayer insulating film containing Si, O, C, and H, an under-bump metal film disposed over the interlayer insulating film and containing Ni, and a bump electrode disposed over the under-bump metal film. In the interlayer insulating film, a ratio of a peak height of Si—CH 3 near a wave number 1270 cm −1 to a peak height of Si—O near a wave number 1030 cm −1 obtained by Fourier-transform infrared spectroscopy (FTIR) is 0.15 or greater and 0.27 or less. A ratio of a peak height of Si—CH 2 —Si near a wave number 1360 cm −1 to the peak height of Si—CH 3 near the wave number 1270 cm −1 is 0.031 or greater.

Подробнее
03-10-2013 дата публикации

Wiring substrate and method of manufacturing the same

Номер: US20130256012A1
Автор: Kotaro Kodani
Принадлежит: Shinko Electric Industries Co Ltd

There is provided a wiring substrate. The wiring substrate includes: an insulating layer; first electrode pads having first exposed surfaces, the first exposed surfaces being exposed from the insulating layer; and second electrode pads having second exposed surfaces, the second exposed surfaces being exposed from the insulating layer. There is a level difference between the first exposed surfaces and the second exposed surfaces.

Подробнее
03-10-2013 дата публикации

Semiconductor devices including electromagnetic interference shield

Номер: US20130256847A1
Автор: Jong-ho Lee, Su-min Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided are a semiconductor device including an EMI shield, a method of manufacturing the same, a semiconductor module including the semiconductor device, and an electronic system including the semiconductor device. The semiconductor device includes a lower semiconductor package, an upper semiconductor package, a package bump, and an EMI shield. The lower semiconductor package includes a lower substrate, a lower semiconductor chip mounted on the lower substrate, and a ground wire separated from the lower semiconductor chip. The upper semiconductor package includes an upper substrate stacked on the lower semiconductor package, and an upper semiconductor chip stacked on the upper substrate. The package bump electrically connects the upper semiconductor package and the lower semiconductor package. The EMI shield covers the upper and lower semiconductor packages and is electrically connected to the ground wire.

Подробнее
03-10-2013 дата публикации

Power line filter for multidimensional integrated circuits

Номер: US20130257564A1

An interposer element in a multidimensional integrated circuit with stacked elements has one or more conductors, especially power supply lines, coupled through decoupling networks defining low impedance shunts for high frequency signals to ground. The interposer has successive tiers including silicon, metal and dielectric deposition layers. The decoupling network for a conductor has at least one and preferably two reactive transmission lines. A transmission line has an inductor in series with the conductor and parallel capacitances at the inductor terminals. The inductors are formed by traces in spaced metal deposition layers forming coil windings and through vias connecting between layers to permit conductor crossovers. The capacitances are formed by MOScaps in the interposer layers. An embodiment has serially coupled coils with capacitances at the input, output and junction between the coils, wherein the coils are magnetically coupled to form a transformer.

Подробнее
17-10-2013 дата публикации

Optical coupling device, opticalsystem and methods of assembly

Номер: US20130272647A1
Автор: Gert Droesbeke
Принадлежит: FCI SA

An optical coupling device comprises: a Z-reference part co-operating with a Z-reference of a first optical device, to define the location of a first optical interface of the coupling device along a direction (Z), fixation parts ( 17, 19 ), extending at different heights along this direction, adapted to be glued to the first optical device.

Подробнее
21-11-2013 дата публикации

Electronic device, electronic apparatus, method of manufacturing base substrate, and method of manufacturing electronic device

Номер: US20130306367A1
Автор: Yukihiro Hashi
Принадлежит: Seiko Epson Corp

An electronic device has a package and a piezoelectric element accommodated in an accommodating space formed inside the package. The package has a frame-like metallization layer bonding a base substrate and a lid together and electrodes formed on and in the base substrate and electrically connected with the piezoelectric element. The metallization layer is insulated from the electrodes.

Подробнее
21-11-2013 дата публикации

Wafer-level process for fabricating photoelectric modules

Номер: US20130309801A1
Принадлежит: CENTERA PHOTONICS Inc

A wafer-level process for fabricating a plurality of photoelectric modules is provided. The wafer-level process includes at least following procedures. Firstly, a wafer including a plurality of chips arranged in an array is provided. Next, a plurality of photoelectric devices are mounted on the chips. Next, a cover plate including a plurality of covering units arranged in an array is provided. Next, a plurality of light guiding mediums are formed over the cover plate. Next, the cover plate is bonded with the wafer by an adhesive, wherein each of the covering units covers and bonds with one of the chips, and the light guiding mediums are sandwiched between the cover plate and the wafer. Then, the wafer and the cover plate are diced to obtain the plurality of photoelectric modules.

Подробнее
28-11-2013 дата публикации

Electronic apparatus, a method for estimating a break, and a method for estimating a fatigue life

Номер: US20130312523A1
Принадлежит: Individual

According to one embodiment, a first joint unit and a second joint unit are disposed with space on a heat radiation substrate. A joint area of the second joint unit is larger than that of the first joint unit. An insulated substrate is disposed on the first joint unit and the second joint unit. A corner region of the insulated substrate contacts the first joint unit. A first sensor to measure an acceleration of vibration applied to the insulated substrate is disposed thereon. The first sensor is more adjacent to the first joint unit than the second joint unit. A response spectrum of the acceleration is calculated. An extension status of joint failure of the first joint unit is decided by comparing a frequency of a maximum peak of the response spectrum with a reference frequency. A break of the second joint unit is estimated based on the extension status

Подробнее
28-11-2013 дата публикации

Semiconductor power module and method of manufacturing the same

Номер: US20130313574A1
Автор: Toshio Hanada
Принадлежит: ROHM CO LTD

A semiconductor power module according to the present invention includes a base member, a semiconductor power device having a surface and a rear surface with the rear surface bonded to the base member, a metal block, having a surface and a rear surface with the rear surface bonded to the surface of the semiconductor power device, uprighted from the surface of the semiconductor power device in a direction separating from the base member and employed as a wiring member for the semiconductor power device, and an external terminal bonded to the surface of the metal block for supplying power to the semiconductor power device through the metal block.

Подробнее
26-12-2013 дата публикации

Method of manufacturing light emitting device

Номер: US20130344631A1
Принадлежит: Nichia Corp

A light emitting device is manufactured in which a cap having a frame portion is bonded to a package having a light emitting element mounted in a recess of the package to cover an opening of the recess. A method for manufacturing the light emitting device includes: partially disposing a metal bonding agent, having greater wettability to the frame portion than to the package, to one of the package and the frame portion; and bonding the package and the frame portion by extending the metal bonding agent along the frame portion so that ends of the metal bonding agent are joined to each other while defining a space at a joining portion where the ends of the metal bonding agent are joined.

Подробнее
06-02-2014 дата публикации

Housing And Method To Control Solder Creep On Housing

Номер: US20140037124A1
Автор: Kurt B. Friel, Tony K. LIM
Принадлежит: Knowles Electronics LLC

An acoustic device includes a substrate, a substrate cover, and a plurality of electrical and acoustic components. The substrate cover is disposed on the substrate and the plurality of electrical and acoustic components are disposed on the substrate and under the substrate cover. The substrate cover is constructed of a base metal and the substrate cover comprises a partially plating. The partial plating is arranged so as to prevent solder creep along a surface of the substrate cover.

Подробнее
06-03-2014 дата публикации

Multi-Chip Module and Method of Manufacture

Номер: US20140061895A1
Принадлежит: SPANSION LLC

A multi-chip module and a method for manufacturing the multi-chip module that mitigates wire breakage. A first semiconductor chip is mounted and wirebonded to a support substrate. A spacer is coupled to the first semiconductor chip. A support material is disposed on the spacer and a second semiconductor chip is positioned on the support material. The second semiconductor chip is pressed into the support material squeezing it into a region adjacent the spacer and between the first and second semiconductor chips. Alternatively, the support material is disposed on the first semiconductor chip and a die attach material is disposed on the spacer. The second semiconductor chip is pressed into the die attach material and the support material, squeezing a portion of the support material over the spacer edges. Wirebonds are formed between the support substrate and the first and second semiconductor chips.

Подробнее
03-04-2014 дата публикации

Solid-state image pickup element and solid-state image pickup element mounting structure

Номер: US20140091421A1
Принадлежит: Hamamatsu Photonics KK

A solid-state image pickup element is provided with a semiconductor substrate having a photosensitive region, a plurality of first electrode pads arrayed on a principal face of the semiconductor substrate, a plurality of second electrode pads arrayed in a direction along a direction in which the plurality of first electrode pads are arrayed, on the principal face of the semiconductor substrate, and a plurality of interconnections connecting the plurality of first electrode pads and the plurality of second electrode pads in one-to-one correspondence. The plurality of interconnections connect the first and second electrode pads so that each interconnection connects the first electrode pad and the second electrode pad in a positional relation of line symmetry with respect to a center line perpendicular to the array directions of the plurality of first and second electrode pads.

Подробнее
01-01-2015 дата публикации

Led device manufacturing method and fluorescent material-dispersed solution used in same

Номер: US20150004728A1
Автор: Yoshihito Taguchi
Принадлежит: KONICA MINOLTA INC

The present invention addresses the problem of providing an LED device having no color unevenness in light emission. In order to solve the problem, this LED device manufacturing method includes: a step of providing an LED chip-mounted package; a step of film-forming a fluorescent material layer by applying a fluorescent material-dispersed solution to a emission surface of the LED chip, said fluorescent material-dispersed solution containing a solvent, a fluorescent material, clay minerals and porous inorganic particles, and by drying the fluorescent material-dispersed solution; and a step of film-forming a wavelength conversion section by applying, to the fluorescent material layer, a precursor solution having a precursor of a light transmissive ceramic dispersed in a solvent, and by firing the layer, said wavelength conversion section being composed of a light transmissive ceramic layer having the fluorescent material, the clay minerals and the porous inorganic particles dispersed therein.

Подробнее
04-01-2018 дата публикации

MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING SUCH DEVICES

Номер: US20180005909A1
Принадлежит:

Microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a packaged microelectronic device can include an interposer substrate with a plurality of interposer contacts. A microelectronic die is attached and electrically coupled to the interposer substrate. The device further includes a casing covering the die and at least a portion of the interposer substrate. A plurality of electrically conductive through-casing interconnects are in contact with and projecting from corresponding interposer contacts at a first side of the interposer substrate. The through-casing interconnects extend through the thickness of the casing to a terminus at the top of the casing. The through-casing interconnects comprise a plurality of filaments attached to and projecting away from the interposer contacts in a direction generally normal to the first side of the interposer substrate. 1. A packaged microelectronic device , comprising:an interposer substrate having a first side with a plurality of interposer contacts and a second side opposite the first side, the second side including a plurality of interposer pads arranged in an array corresponding to a standard JEDEC pinout;a microelectronic die attached and electrically coupled to the interposer substrate;a casing covering the die and at least a portion of the interposer substrate, wherein the casing has a thickness and a top facing away from the interposer substrate; anda plurality of electrically conductive through-casing interconnects in contact with and projecting from corresponding interposer contacts, wherein the through-casing interconnects extend through the thickness of the casing to a terminus at the top of the casing, and wherein the through-casing interconnects are at least partially encapsulated in the casing,wherein the through-casing interconnects comprise a plurality of filaments attached to and projecting away from the interposer contacts in a direction generally normal to ...

Подробнее
03-01-2019 дата публикации

3D SEMICONDUCTOR DEVICE AND STRUCTURE

Номер: US20190006222A1
Принадлежит: MonolithIC 3D Inc.

A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written. 1. A 3D semiconductor device , the device comprising: 'wherein connections between said first transistors and first metal layer comprise said first contact plugs;', 'a first level comprising a single crystal layer, a plurality of first transistors, a plurality of first contact plugs and a first metal layer,'}memory control circuits comprising a portion of said connections and said plurality of first transistors;a second level overlaying said single crystal layer, said second level comprising a plurality of second transistors;a third level overlaying said second level, said third level comprising a plurality of third transistors;a second metal layer overlaying said third level; and wherein said second transistors are aligned to said first transistors with less than 40 nm alignment error,', 'wherein said third metal layer comprises bit lines,', 'wherein said second level comprises a plurality of first memory cells,', 'wherein said third level comprises a plurality of second memory cells,', 'wherein one of said second transistors is at least partially self-aligned to at least one of said third ...

Подробнее
03-01-2019 дата публикации

Heat Spreading Device and Method

Номер: US20190006263A1

In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die.

Подробнее
03-01-2019 дата публикации

Platform with thermally stable wireless interconnects

Номер: US20190006298A1
Принадлежит: Intel Corp

Embodiments of the invention may include a packaged device that includes thermally stable radio frequency integrated circuits (RFICs). In one embodiment the packaged device may include an integrated circuit chip mounted to a package substrate. According to an embodiment, the package substrate may have conductive lines that communicatively couple the integrated circuit chip to one or more external components. One of the external components may be an RFIC module. The RFIC module may comprise an RFIC and an antenna. Additional embodiments may also include a packaged device that includes a plurality of cooling spots formed into the package substrate. In an embodiment the cooling spots may be formed proximate to interconnect lines the communicatively couple the integrated circuit chip to the RFIC.

Подробнее
03-01-2019 дата публикации

PACKAGING STRUCTURE AND PACKAGING METHOD

Номер: US20190006404A1
Автор: Hong Fangyuan, Wang Zhiqi
Принадлежит: China Wafer Level CSP Co., Ltd.

A packaging structure and a packaging method are provided. The packaging structure includes: a chip unit, where a first surface of the chip unit includes a sensing region; and an upper cover plate structure, where a first surface of the upper cover plate structure is provided with a groove structure, the first surface of the chip unit is attached with the first surface of the upper cover plate structure, the sensing region is located within a cavity surrounded by the groove structure and the first surface of the chip unit, the upper cover plate structure further includes a second surface opposite to the first surface, and an area of the second surface of the upper cover plate structure is less than an area of the first surface of the upper cover plate structure. 1. A packaging structure , comprising:a chip unit, wherein a first surface of the chip unit comprises a sensing region; andan upper cover plate structure,wherein a first surface of the upper cover plate structure is provided with a groove structure, the first surface of the chip unit is attached with the first surface of the upper cover plate structure, the sensing region is located within a cavity surrounded by the groove structure and the first surface of the chip unit,wherein the upper cover plate structure further comprises a second surface opposite to the first surface, and an area of the second surface of the upper cover plate structure is less than an area of the first surface of the upper cover plate structure.2. The packaging structure according to claim 1 , wherein the upper cover plate structure further comprises a side wall comprising a vertical wall and an inclined wall claim 1 , a first end of the inclined wall is connected to an edge of the second surface of the upper cover plate structure claim 1 , and a second end opposite to the first end of the inclined wall is connected to the top of the vertical wall claim 1 , such that the area of the second surface of the upper cover plate structure is ...

Подробнее
12-01-2017 дата публикации

Ion sensor based on differential measurement, and production method

Номер: US20170010237A1

Ion sensor based on differential measurement comprising an ISFTET-REFET pair wherein the REFET is defined by a structure composed of an ISFET covered by a microreservoir where an internal reference solution is contained. The sensor comprises a first and a second ion-selective field effect transistor, an electrode, a substrate on the surface whereof are integrated the two transistors, connection tracks and the electrode and a structure adhered on the first ion-selective field effect transistor which creates a microreservoir on the gate of said first transistor, with the microreservoir having a microchannel which connects the microreservoir with the exterior and the microreservoir being filled with the reference solution.

Подробнее
12-01-2017 дата публикации

Electronic apparatus and method for fabricating the same

Номер: US20170012013A1
Принадлежит: Fujitsu Ltd

An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

Подробнее
11-01-2018 дата публикации

Thermal transfer structures for semiconductor die assemblies

Номер: US20180012865A1
Автор: Ed A. Schrock
Принадлежит: Micron Technology Inc

Several embodiments of the present technology are described with reference to a semiconductor die assembly and processes for manufacturing the assembly. In some embodiments of the present technology, a semiconductor die assembly includes a stack of semiconductor dies attached to a thermal transfer structure (also known as a “heat spreader,” “lid,” or “thermal lid”). The thermal transfer structure conducts heat away from the stack of semiconductor dies. Additionally, the assembly can include molded walls fabricated with molding material to support the thermal transfer structure.

Подробнее
11-01-2018 дата публикации

MANUFACTURABLE LASER DIODE FORMED ON C-PLANE GALLIUM AND NITROGEN MATERIAL

Номер: US20180013265A1
Принадлежит:

A method for manufacturing a laser diode device includes providing a substrate having a surface region and forming epitaxial material overlying the surface region, the epitaxial material comprising an n-type cladding region, an active region comprising at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active layer region. The epitaxial material is patterned to form a plurality of dice, each of the dice corresponding to at least one laser device, characterized by a first pitch between a pair of dice, the first pitch being less than a design width. Each of the plurality of dice are transferred to a carrier wafer such that each pair of dice is configured with a second pitch between each pair of dice, the second pitch being larger than the first pitch. 132.-. (canceled)33. A method for manufacturing a laser diode device , the method comprising:providing a gallium and nitrogen containing substrate having a surface region;forming an epitaxial material overlying the surface region, the epitaxial material comprising a release material overlying the surface region, an n-type gallium and nitrogen containing region overlying the release material, an active region comprising at least one quantum well layer overlying the n-type gallium and nitrogen containing region, a p-type gallium and nitrogen containing region overlying the active region; and an interface region overlying the p-type gallium and nitrogen containing region;forming a plurality of dies by patterning the epitaxial material, each pair of adjacent dies being characterized by a first pitch between the pair of dies, each of the dies corresponding to at least one laser diode device;bonding the interface region associated with a portion of the plurality of dies to a carrier substrate to form bonded dies;subjecting the release material of the bonded dies to an energy source to release the bonded dies from the gallium and nitrogen containing substrate and transfer ...

Подробнее
14-01-2021 дата публикации

Multi-metal package stiffener

Номер: US20210013155A1
Автор: Howard B. Osgood
Принадлежит: Flex Ltd

A semiconductor package system includes a semiconductor package including at least one semiconductor device having a first side and a second side and a substrate having a first side and a second side. The second side of the at least one semiconductor device is positioned on the first side of the substrate. At least one stiffener element is provided on the semiconductor package. The at least one stiffener element includes at least two metal elements having different coefficients of thermal expansion joined together.

Подробнее
14-01-2021 дата публикации

CHIP PACKAGE WITH LID

Номер: US20210013160A1
Принадлежит:

Structures and formation methods of a chip package are provided. The chip package includes a substrate and a semiconductor die over the substrate. The chip package also includes a lid covering a top surface of the semiconductor die. The lid has a first support structure and a second support structure, and the first support structure and the second support structure are positioned at respective corner portions of the substrate. An opening penetrates through the lid to expose a space containing the semiconductor die, and the lid has a side edge extending from an edge of the first support structure to an edge of the second support structure. 1. A chip package , comprising:a substrate;a semiconductor die over the substrate; anda lid covering a top surface of the semiconductor die, wherein the lid has a first support structure and a second support structure, the first support structure and the second support structure are positioned at respective corner portions of the substrate, an opening penetrates through the lid to expose a space containing the semiconductor die, and the lid has a side edge extending from an edge of the first support structure to an edge of the second support structure.2. The chip package as claimed in claim 1 , wherein at least one of the first support structure and the second support structure has a sidewall surface with an L-shaped profile.3. The chip package as claimed in claim 1 , wherein one of the support structures has a base portion and a side portion claim 1 , a bottom surface of the base portion is substantially parallel to a top surface of the substrate claim 1 , and the side portion is in direct contact with the base portion and an upper plate of the lid.4. The chip package as claimed in claim 3 , wherein the side portion has a slanted sidewall extending from the base portion to the upper plate of the lid.5. The chip package as claimed in claim 1 , wherein the first support structure has a first side and a second side opposite to the ...

Подробнее
14-01-2021 дата публикации

Electronic module and electronic device

Номер: US20210013178A1
Принадлежит: Fujitsu Ltd

An electronic module includes: a plurality of heat generating members provided over a first surface of a board; a frame joined to the first surface of the board and provided between the plurality of heat generating members that are arranged; and a lid configured to cover the first surface of the board and thermally coupled to each of the plurality of heat generating members, the frame being a grid-shaped frame or a mesh-shaped frame.

Подробнее
09-01-2020 дата публикации

Substrate design for semiconductor packages and method of forming same

Номер: US20200013635A1

A device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity.

Подробнее
14-01-2021 дата публикации

Semiconductor device package and method of manufacturing the same

Номер: US20210013375A1
Автор: Mei-Yi Wu
Принадлежит: Advanced Semiconductor Engineering Inc

A semiconductor device package includes a carrier, a conductive pillar, an adhesive layer and a package body. The conductive pillar is disposed on the carrier. The conductive pillar has a top surface facing away from the carrier. The adhesive layer is disposed on the top surface of the conductive pillar. The package body is disposed on the carrier. The package body has a top surface facing away from the carrier. The top surface has a first portion and a second portion. The first portion and the second portion of the top surface of the package body are discontinuous.

Подробнее
09-01-2020 дата публикации

Semiconductor device package with a cap to selectively exclude contact with mold compound

Номер: US20200013688A1
Принадлежит: Texas Instruments Inc

A described example includes: a die with an active surface; a cap mounted over a portion of the active surface of the die; and mold compound covering the cap and covering portions of the die, the cap excluding the mold compound from contact with the portion of the active surface of the die.

Подробнее
09-01-2020 дата публикации

PACKAGING STRUCTURES WITH IMPROVED ADHESION AND STRENGTH

Номер: US20200013689A1
Принадлежит:

According to various aspects and embodiments, a support structure for packaging an electronic device is provided. In one example, a packaged electronic device includes a substrate, at least one electronic device disposed on the substrate, an encapsulation structure disposed on the substrate and having a wall that forms a perimeter around the at least one electronic device, and at least one support structure formed from a photosensitive polymer and disposed adjacent the wall of the encapsulation structure. The at least one support structure has a configuration that provides at least one of increased adhesion and mechanical strength to the encapsulation structure. 1. A method of packaging an electronic device , the method comprising:depositing a layer of temporary bonding material onto a first substrate;depositing a layer of photosensitive polymer onto the temporary bonding material;masking at least a portion of the layer of photosensitive polymer to define an unmasked portion and a masked portion of the photosensitive polymer, the unmasked portion of the photosensitive polymer defining at least a portion of at least one support structure;performing at least a partial cure of the unmasked portion of the layer of photosensitive polymer;developing the masked portion of the layer of photosensitive polymer;attaching a second substrate to the unmasked portion of the photosensitive polymer, the second substrate including an electronic device and an encapsulation structure having a wall surrounding the electronic device, attaching the second substrate to the unmasked portion of the photosensitive polymer including aligning the at least one support structure with the encapsulation structure; andseparating the first substrate from the unmasked portion of the layer of photosensitive polymer.2. The method of further comprising forming at least one opening through the layer of photosensitive polymer.3. The method of further comprising depositing a bonding material into the at ...

Подробнее
17-01-2019 дата публикации

ION SENSOR BASED ON DIFFERENTIAL MEASUREMENT, AND PRODUCTION METHOD

Номер: US20190017958A1
Принадлежит:

Ion sensor based on differential measurement comprising an ISFTET-REFET pair wherein the REFET is defined by a structure composed of an ISFET covered by a microreservoir where an internal reference solution is contained. The sensor comprises a first and a second ion-selective field effect transistor, an electrode, a substrate on the surface whereof are integrated the two transistors, connection tracks and the electrode and a structure adhered on the first ion-selective field effect transistor which creates a microreservoir on the gate of said first transistor, with the microreservoir having a microchannel which connects the microreservoir with the exterior and the microreservoir being filled with the reference solution. 119-. (canceled)20. An ion sensor based on differential measurement comprising:a substrate whereon are integrated connection tracks;an electrode of a conductor material arranged to be in contact with a solution to measure;a first ion-selective field effect transistor and a second ion-selective field effect transistor electrically connected by the connection tracks to an ion measurement system, each of the first and second ion-selective field effect transistors being fixed on the substrate and having a gate;a structure coupled only on the first ion-selective field effect transistor configured to create a microreservoir on the gate of the first ion-selective field effect transistor, wherein the gate of the first ion-selective field effect transistor is arranged to be in contact with a reference solution and the gate of the second ion-selective field effect transistor is arranged to be in contact with the solution to measure; andat least one microchannel connecting the microreservoir with the exterior of the ion sensor through an outlet orifice of the at least one microchannel, the at least one microchannel configured to calibrate the ion sensor by filling or renewing the microreservoir with the reference solution and comprising a first longitudinal ...

Подробнее
21-01-2016 дата публикации

Radio frequency shielding cavity package

Номер: US20160020177A1
Автор: Ming-Wa TAM
Принадлежит: UBOTIC Co Ltd

A radio-frequency shielding cavity package is set forth along with a method of manufacturing thereof. According to one embodiment, the radio-frequency shielding cavity package comprises a metallic leadframe and plastic molded body. The leadframe has a plurality of contact pads extending from top to bottom surfaces thereof, at least one contact pad on the top surface being surrounded by metal for shielding the contact pad from external electric fields. A plated inner ring surrounds a die attach pad on the leadframe. The die attach pad receives a semiconductor die adapted to be wire bonded to the inner ring and plurality of contact pads. A plated outer ring defines a ground plane circumscribing the perimeter of the leadframe. A cap is connected to the ground plane for enclosing and protecting the wire bonded semiconductor device die and providing electrical grounding thereof.

Подробнее
03-02-2022 дата публикации

Semiconductor package and method of fabricating the same

Номер: US20220037255A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.

Подробнее
18-01-2018 дата публикации

FLEXIBLE CIRCUIT LEADS IN PACKAGING FOR RADIO FREQUENCY DEVICES AND METHODS THEREOF

Номер: US20180019222A1
Принадлежит: NXP USA, Inc.

A packaged RF device is provided that utilizes flexible circuit leads. The RF device includes at least one integrated circuit (IC) die configured to implement the RF device. The IC die is contained inside a package. In accordance with the embodiments described herein, a flexible circuit is implemented as a lead. Specifically, the flexible circuit lead is coupled to the at least one IC die inside the package and extends to outside the package, the flexible circuit lead thus providing an electrical connection to the at least one IC die inside the package. 1. A radio-frequency (RF) device comprising:an integrated circuit (IC) die, the IC die including at least one RF amplifier to implement the RF device;a package containing the IC die; anda flexible circuit lead coupled to the IC die inside the package, the flexible circuit lead extending from inside the package to outside the package, the flexible circuit lead comprising at least one flexible base layer and at least one conductor, the flexible circuit lead providing an electrical connection to the at least one RF amplifier on the IC die, wherein the at least one conductor is configured to form at least one passive device in a filter, with the filter electrically connected to the RF amplifier inside the package and through the flexible circuit lead.2. The RF device of wherein the at least one passive device formed with the least one conductor comprises a spiral inductor.3. The RF device of wherein the at least one passive device formed with the least one conductor comprises an inductor and a capacitor.4. The RF device of wherein the filter further includes at least one lumped passive element mounted on the flexible circuit lead.5. The RF device of wherein the at least one conductor in the flexible circuit lead is further configured to form a transmission line in the flexible circuit lead such that the transmission line is electrically connected to the RF amplifier claim 1 , and wherein the transmission line is formed ...

Подробнее
17-01-2019 дата публикации

High frequency module

Номер: US20190019738A1
Принадлежит: Mitsubishi Electric Corp

A high frequency module improved in heat dissipation performance includes: a dielectric multilayer substrate including a ground layer and a high frequency electronic component mounted thereon while being in contact with the ground layer, the high frequency electronic component including a heat generating portion; and a cutoff block formed of an upstanding wall portion and a cover portion covering the upstanding wall portion, the cutoff block housing the high frequency electronic component and including a hollow portion having a cutoff characteristic at a frequency of a high frequency signal used by the high frequency electronic component, and the upstanding wall portion of the cutoff block being in contact with the ground layer of the dielectric multilayer substrate.

Подробнее
22-01-2015 дата публикации

Techniques for bonding substrates using an intermediate layer

Номер: US20150022983A1
Принадлежит: MEDTRONIC INC

A method includes depositing a thin film on a first surface of a first substrate and moving a second surface of a second substrate into contact with the thin film such that the thin film is located between the first and second surfaces. The method further includes generating electromagnetic (EM) radiation of a first wavelength, the first wavelength selected such that the thin film absorbs EM radiation at the first wavelength. Additionally, the method includes directing the EM radiation through one of the first and second substrates and onto a region of the thin film until the first and second substrates are fused in the region.

Подробнее
21-01-2021 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20210020591A1
Принадлежит:

A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer. 120-. (canceled)21. A semiconductor device comprising: a first interposer side;', 'a second interposer side opposite the first interposer side;', 'a first dielectric layer at the first interposer side;', 'a first conductive via that extends through at least the first dielectric layer;', 'a second conductive via at the second interposer side; and', 'a redistribution structure in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via;, 'an interposer comprising a first die side that faces away from the first interposer side;', 'a second die side that faces toward the first interposer side and comprises a die connection terminal that is coupled to the first conductive via; and', 'a lateral die side that extends between the first die side and the second die side;, 'a semiconductor die comprising the encapsulating material comprises an uppermost surface facing away from the interposer, a lowermost surface facing the interposer, and a lateral surface that extends entirely between the uppermost surface and the lowermost surface;', 'no portion of the encapsulating material is substantially vertically higher than the ...

Подробнее
10-02-2022 дата публикации

Heat dissipation device having anisotropic thermally conductive sections and isotropic thermally conductive sections

Номер: US20220042750A1
Принадлежит: Intel Corp

A heat dissipation device may be formed having at least one isotropic thermally conductive section (uniformly high thermal conductivity in all directions) and at least one anisotropic thermally conductive section (high thermal conductivity in at least one direction and low thermal conductivity in at least one other direction). The heat dissipation device may be thermally coupled to a plurality of integrated circuit devices such that at least a portion of the isotropic thermally conductive section(s) and/or the anisotropic thermally conductive section(s) is positioned over at least one integrated circuit device. The isotropic thermally conductive section(s) allows heat spreading/removal from hotspots or areas with high-power density and the anisotropic thermally conductive section(s) transfers heat away from the at least one integrated circuit device predominately in a single direction with minimum conduction resistance in areas with uniform power density distribution, while reducing heat transfer in the other directions, thereby reducing thermal cross-talk.

Подробнее
25-01-2018 дата публикации

INTERCONNECT STRUCTURE WITH REDUNDANT ELECTRICAL CONNECTORS AND ASSOCIATED SYSTEMS AND METHODS

Номер: US20180026015A1
Автор: Chandolu Anilkumar
Принадлежит:

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film. 1. A semiconductor device , comprising:a semiconductor substrate;a dielectric material over the substrate;a conductive trace extending at least partially through the dielectric material; and a conductive member coupled to the conductive trace, and', 'a conductive bond material bonded to the conductive member,, 'a plurality of redundant electrical connectors extending from the conductive trace and through at least a portion of the dielectric material, wherein each of the redundant electrical connectors includes—'}wherein all of the redundant electrical connectors are coupled to the conductive trace.2. The semiconductor device of wherein the dielectric includes a plurality of openings exposing portions of the conductive trace claim 1 , wherein the redundant electrical connectors are formed in the openings.3. The semiconductor device of wherein the conductive member comprises copper and the bond material comprises a solder material.4. The semiconductor device of wherein the conductive member includes an end portion claim 1 , and wherein the conductive bond material and conductive member form a conductive joint at the end portion.5. The semiconductor device of claim 1 , further comprising a through-substrate via (TSV) extending at least partially through the substrate claim 1 , ...

Подробнее
23-01-2020 дата публикации

ION SENSOR BASED ON DIFFERENTIAL MEASUREMENT, AND PRODUCTION METHOD

Номер: US20200025710A1

Ion sensor based on differential measurement comprising an ISFTET-REFET pair wherein the REFET is defined by a structure composed of an ISFET covered by a microreservoir where an internal reference solution is contained. The sensor comprises a first and a second ion-selective field effect transistor, an electrode, a substrate on the surface whereof are integrated the two transistors, connection tracks and the electrode and a structure adhered on the first ion-selective field effect transistor which creates a microreservoir on the gate of said first transistor, with the microreservoir having a microchannel which connects the microreservoir with the exterior and the microreservoir being filled with the reference solution. 119-. (canceled)20. A device comprising an ion sensor based on differential measurement , wherein the sensor comprises:(i) a substrate whereon are integrated connection tracks;(ii) an electrode of a conductor material arranged to be in contact with a solution to measure;(iii) a first ion-selective field effect transistor and a second ion-selective field effect transistor electrically connected by the connection tracks to an ion measurement system, each of the first and second ion-selective field effect transistors being fixed on the substrate and having a gate;(iv) a structure coupled only on the first ion-selective field transistor configured to create a microreservoir on the gate of the first ion-selective field effect transistors, wherein the gate of the first ion-selective field effect transistor is arranged to be in contact with a reference solution and the gate of the second ion-selective field effect transistor is arranged to be in contact with the solution to measure; and,(v) at least one microchannel connecting the microreservoir with the exterior of the ion sensor through an outlet orifice of the at least one microchannel, the at least one microchannel configured to calibrate the ion sensor by filling or renewing the microreservoir with the ...

Подробнее
23-01-2020 дата публикации

DYNAMIC RANDOM ACCESS MEMORY (DRAM) MOUNTS

Номер: US20200027867A1
Принадлежит:

Donut-shaped Dynamic Random Access Memory (DRAM) includes a hole that fits around a processor, such that the DRAM and the processor are adjacent to one another on an Integrated Circuit (IC) package. In an embodiment, a heat spreader is mounted on top of the processor and covers a top of the DRAM without touching the DRAM. 1. (canceled).2. A circuit package , comprising:a first memory device situated to a first side of a processor in parallel to the processor and mounted on a package board of a processor assembly; anda second memory device situated to a second side of the processor in parallel to the processor and mounted on the package board of the processor assembly.3. The circuit package of claim 2 , wherein the first memory device and the second memory device are donut-shaped.4. The circuit package of further comprising a heat spreader mounted on top of the processor and extending past a first outer edge along the first side past the first memory device and the heat spreader extending past a second outer edge along the second side past the second memory device.5. The circuit package of further comprising claim 2 , at least one additional first memory device stacked on top of the first memory device.6. The circuit package of further comprising claim 5 , at least one additional second memory device stacked on top of the second memory device.7. The circuit package of claim 6 , wherein the at least one additional first memory device claim 6 , the first memory device claim 6 , the at least one additional second memory device claim 6 , and the second memory device have heights that are less than a processor height for the processor on the packaging board of the processor assembly.8. The circuit package of claim 7 , wherein a first outer edge of the first memory device overhangs beyond a first side edge of the packaging board claim 7 , and wherein a second outer edge of the second memory device overhangs beyond a second side edge of the packaging board.9. The circuit ...

Подробнее
02-02-2017 дата публикации

Mems device and process

Номер: US20170029267A1
Принадлежит: Cirrus Logic Inc

A MEMS capacitive transducer with increased robustness and resilience to acoustic shock. The transducer structure includes a flexible membrane supported between a first volume and a second volume, and at least one variable vent structure in communication with at least one of the first and second volumes. The variable vent structure includes at least one moveable portion which is moveable in response to a pressure differential across the moveable portion so as to vary the size of a flow path through the vent structure. The variable vent may be formed through the membrane and the moveable portion may be a part of the membrane, defined by one or more channels, that is deflectable away from the surface of the membrane. The variable vent is preferably closed in the normal range of pressure differentials but opens at high pressure differentials to provide more rapid equalisation of the air volumes above and below the membrane.

Подробнее
01-02-2018 дата публикации

Vacuum Sealed MEMS and CMOS Package

Номер: US20180029881A1
Принадлежит:

A vacuum sealed MEMS and CMOS package and a process for making the same may include a capping wafer having a surface with a plurality of first cavities, a first device having a first surface with a second plurality of second cavities, a hermetic seal between the first surface of the first device and the surface of the capping wafer, and a second device having a first surface bonded to a second surface of the first device. The second device is a CMOS device with conductive through vias connecting the first device to a second surface of the second device, and conductive bumps on the second surface of the second device. Conductive bumps connect to the conductive through vias and wherein a plurality of conductive bumps connect to the second device. The hermetic seal forms a plurality of micro chambers between the capping wafer and the first device. 1. A method comprising:forming a MEMS device on a MEMS substrate;depositing an oxide layer on the MEMS substrate;etching a plurality of openings in a CMOS device layer on a CMOS substrate;bonding the oxide layer to the CMOS device layer;thinning the MEMS substrate;depositing a first bond metal layer on the thinned MEMS substrate;forming a suspended substrate structure in the thinned MEMS substrate;bonding a cap wafer on the thinned MEMS substrate;thinning the CMOS substrate;etching a plurality of through vias through a backside of the CMOS substrate to expose the openings in the CMOS device layer;depositing oxides in the through vias;depositing and patterning conductive material in the through vias and on portions of the thinned CMOS substrate; andforming a plurality of bumps over the patterned conductive material.2. The method of claim 1 , wherein the bonding a cap wafer comprises heating to a first temperature in a range of approximately 100° C. to approximately 500° C. and applying a pressure in a range of approximately 10 KN to approximately 100 KN in a vacuum environment.3. The method of claim 1 , wherein the bonding the ...

Подробнее
01-05-2014 дата публикации

Sensor with masking

Номер: US20140116149A1
Принадлежит: INFINEON TECHNOLOGIES AG

A sensor may include a sensor membrane, wherein one side of the sensor membrane at least partly has a glob top and wherein the glob top furthermore has structurings.

Подробнее
05-02-2015 дата публикации

Integrated Circuit with Stress Isolation

Номер: US20150035130A1
Автор: You Chye HOW
Принадлежит: Texas Instruments Inc

A packaged semiconductor device has a semiconductor substrate with circuitry formed thereon. A shield plate is mounted over a designated region of the substrate and separated from the semiconductor substrate by a separator, such that the shield plate is separated from the designated region of the substrate by a distance. Mold compound encapsulates the semiconductor substrate and the shield plate, but is prevented from touching the designated region of the substrate by the shield plate.

Подробнее
05-02-2015 дата публикации

Electronic modules and methods of making electronic modules

Номер: US20150035133A1
Автор: Wing Shenq Wong
Принадлежит: STMICROELECTRONICS PTE LTD

A method is described for making electronic modules includes molding onto a substrate panel a matrix panel defining a plurality of cavities, attaching semiconductor die to the substrate panel in respective cavities of the molded matrix panel, electrically connecting the semiconductor die to the substrate panel, affixing a cover to the molded matrix panel to form an electronic module assembly, mounting the electronic module assembly on a carrier tape, and separating the electronic module assembly into individual electronic modules. An electronic module is described which includes a substrate, a wall member molded onto the substrate, the molded wall member defining a cavity, at least one semiconductor die attached to the substrate in the cavity and electrically connected to the substrate, and a cover affixed to the molded wall member over the cavity.

Подробнее
04-02-2016 дата публикации

Method of manufacturing semiconductor device

Номер: US20160035787A1
Автор: Shintaro Matsuda
Принадлежит: Renesas Electronics Corp

To protect a plurality of semiconductor chips of a sawn wafer housed in a shipping case. A method of manufacturing a semiconductor device includes a step of vacuum packing a sawn wafer while being housed in a shipping case. The shipping case has the following structure. The shipping case has a lid portion that covers the upper surface of the sawn wafer and a body portion that covers the lower surface of the sawn wafer. The lid portion has a recess portion that covers a plurality of semiconductor chips and a ventilation route communicated with the recess portion. In a step of reducing pressure in the shipping case, a gas in the shipping case is discharged outside via a ventilation route.

Подробнее
01-02-2018 дата публикации

SEALING CAP FOR ELECTRONIC COMPONENT

Номер: US20180033706A1
Принадлежит:

An electronic component cap for producing a package having a sealed region by being bonded to a base, having a brazing material-fused surface to which a brazing material is fused and a sealing surface corresponding to the sealed region. The brazing material-fused surface has a non-flat work surface formed by plastic working, and a ratio (Sc/Sf) of a surface area (Sc) of the brazing material-fused surface per unit area to a surface area (Sf) of the sealing surface per unit area satisfies 1 Подробнее

01-02-2018 дата публикации

SEMICONDUCTOR PACKAGE ASSEMBLY WITH PASSIVE DEVICE

Номер: US20180033774A1
Принадлежит:

A semiconductor package assembly includes a first substrate. A first semiconductor die is disposed on the first substrate. A passive device is located directly on the first semiconductor die. The passive device is disposed within a boundary of the first semiconductor die in a plan view. 1. A semiconductor package assembly , comprising:a first substrate;a first semiconductor die disposed on the first substrate; anda passive device located directly above the first semiconductor die, wherein the passive device is disposed within a boundary of the first semiconductor die in a plan view.2. The semiconductor package assembly as claimed in claim 1 , wherein pads of the passive device connect directly to pads of the first semiconductor die.3. The semiconductor package assembly as claimed in claim 1 , further comprising a second substrate between the first semiconductor die and the passive device claim 1 , wherein pads of the first semiconductor die are exposed form the second substrate.4. The semiconductor package assembly as claimed in claim 3 , wherein the pads of the passive device directly attach onto pads of the second substrate.5. The semiconductor package assembly as claimed in claim 3 , wherein an area of the second substrate is less than that of the first semiconductor die and that of the first substrate.6. The semiconductor package assembly as claimed in claim 3 , wherein the second substrate is coupled to the pads of the first semiconductor die only through conductive wires.7. The semiconductor package assembly as claimed in claim 3 , further comprising a second semiconductor die disposed directly on the second substrate.8. The semiconductor package assembly as claimed in claim 3 , wherein the passive device is disposed beside the second semiconductor die.9. A semiconductor package assembly claim 3 , comprising:a first substrate;a first semiconductor die disposed on the first substrate; anda discrete passive device located directly above the first semiconductor ...

Подробнее
17-02-2022 дата публикации

Packaging stacked substrates and an integrated circuit die using a lid and a stiffening structure

Номер: US20220051963A1
Принадлежит: Marvell Asia Pte Ltd

An electronic device disposed in a package that includes: an interposer, fan-out interconnect (FOI), and a lid. The interposer having first size and first surface upon which die terminals (DTs) are disposed and are configured to electrically couple to integrated circuit die (IC), and second surface upon which substrate terminals (STs) are disposed and are configured to electrically couple to substrate. The IC has second size smaller than the first size, and the IC is mounted on the first surface in electrical contact with the DTs, the interposer is mounted on third surface, and the package substrate has third size, larger than the first size. The FOI establishes electrical interconnection between DTs and STs, the DTs have first pitch size and the STs have second pitch size, larger than first pitch size. The lid has first section, configured to abut fourth surface, and second section, mounted on the third surface.

Подробнее
05-02-2015 дата публикации

Semiconductor devices including electromagnetic interference shield

Номер: US20150037937A1
Автор: Jong-ho Lee, Su-min Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided are a semiconductor device including an EMI shield, a method of manufacturing the same, a semiconductor module including the semiconductor device, and an electronic system including the semiconductor device. The semiconductor device includes a lower semiconductor package, an upper semiconductor package, a package bump, and an EMI shield. The lower semiconductor package includes a lower substrate, a lower semiconductor chip mounted on the lower substrate, and a ground wire separated from the lower semiconductor chip. The upper semiconductor package includes an upper substrate stacked on the lower semiconductor package, and an upper semiconductor chip stacked on the upper substrate. The package bump electrically connects the upper semiconductor package and the lower semiconductor package. The EMI shield covers the upper and lower semiconductor packages and is electrically connected to the ground wire.

Подробнее
04-02-2016 дата публикации

High-frequency component and high-frequency module including the same

Номер: US20160037640A1
Принадлежит: Murata Manufacturing Co Ltd

In a method for mounting a filter circuit component to obtain desired frequency characteristics of the filter circuit component without receiving the influence of a parasitic inductance and a parasitic capacitance, and to increase the packing density of components, since the ground terminal of the filter circuit component connected to the mounting electrode is connected to the ground electrode through the via conductors at the shortest distance, the occurrence of an unnecessary parasitic inductance and an unnecessary parasitic capacitance is prevented. The filter circuit component is mounted on the high-frequency component to obtain the desired frequency characteristics of the filter circuit component without the influence of a parasitic inductance and a parasitic capacitance. Since the component is located in a space surrounded by the inner peripheral surface of the supporting frame body, the packing density of components is increased.

Подробнее
30-01-2020 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20200035582A1
Автор: HIROBE Masao
Принадлежит:

There is provided a semiconductor device including a substrate whose surface is made of an insulation material, a semiconductor chip flip-chip connected on the substrate, and a heat sink bonded to the semiconductor chip via a thermal interface material and fixed to the substrate outside the semiconductor chip, in which the heat sink has a protrusion part protruding toward the substrate and bonded to the substrate via a conductive resin between a part bonded to semiconductor chip and a part fixed to the substrate and the heat sink has a stress absorbing part. According to the present invention, the protrusion part of the heat sink is prevented from being peeled off from the substrate at the part where the protrusion part of the heat sink is bonded to the substrate. 19-. (canceled)10. A semiconductor device , comprising:a substrate;a semiconductor chip on a top side of the substrate; and a central portion over a top side of the semiconductor chip;', 'a fixing part coupled to the top side of the substrate;', 'a protrusion part coupled to the top side of the substrate between the fixing part and the semiconductor device; and', 'a recession between the central portion and the fixing part;, 'a heatsink on a top side of the substrate, wherein the heat sink compriseswherein a thickness of the heatsink at the recession is less than a thickness of the heatsink between the protrusion part and the fixing part.11. The semiconductor device of claim 10 , further comprising a thermal interface material (TIM) contacting the central portion of the heatsink and the top side of the substrate.12. The semiconductor device of claim 10 , wherein the fixing part is attached to the top side of the substrate via an adhesive.13. The semiconductor device of claim 10 , wherein the protrusion part is coupled to the top side of the substrate via a conductive adhesive.14. The semiconductor device of claim 10 , wherein the heatsink has a lower rigidity at the recession than between the protrusion ...

Подробнее
04-02-2021 дата публикации

Combination stiffener and capacitor

Номер: US20210035738A1
Принадлежит: Intel Corp

Electronic device package stiffener and capacitor technology is disclosed. A combination stiffener and capacitor can include a structural material configured to be coupled to a substrate. The structural material can have a shape configured to provide mechanical support for the substrate. The combination stiffener and capacitor can also include first and second electrodes forming a capacitor. An electronic device package and a package substrate configured to receive the combination stiffener and capacitor are also disclosed.

Подробнее
04-02-2021 дата публикации

Magnetic shielding material with insulator-coated ferromagnetic particles

Номер: US20210035920A1

A non-conductive magnetic shield material is provided for use in magnetic shields of semiconductor packaging. The material is made magnetic by the incorporation of ferromagnetic particles into a polymer matrix, and is made non-conductive by the provision of an insulating coating on the ferromagnetic particles.

Подробнее
09-02-2017 дата публикации

Interconnections for a substrate associated with a backside reveal

Номер: US20170040268A1
Автор: Cyprian Emeka Uzoh
Принадлежит: Invensas LLC

An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.

Подробнее
08-02-2018 дата публикации

Semiconductor packages having an electric device with a recess

Номер: US20180040514A1
Принадлежит: STMICROELECTRONICS PTE LTD

Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.

Подробнее
08-02-2018 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20180040598A1
Принадлежит:

To improve the assemblability of a semiconductor device. 120-. (canceled)21. A method for manufacturing a semiconductor device , comprising the steps of:(a) mounting a first semiconductor chip over a second semiconductor chip such that a first surface of the first semiconductor chip faces to a second surface of the second semiconductor chip,wherein the second semiconductor chip includes a plurality of electrode pads and a recognition mark arranged on the second surface, and a plurality of through electrodes electrically coupled with the electrode pads respectively, andwherein the first semiconductor chip includes a plurality of projection electrodes arranged on the first surface, (a1) recognizing the recognition mark;', '(a2) performing alignment of the first semiconductor chip and the second semiconductor chip based on a result of having recognized the recognition mark; and', '(a3) mounting the first semiconductor chip over the second semiconductor chip, and electrically coupling the electrode pads of the second semiconductor chip and the projection electrodes of the first semiconductor chip respectively,, 'the (a) step including the steps of(b) before the (a) step, forming the through electrodes such that the through electrodes are formed penetrating a silicon base portion of the first semiconductor chip, and(c) after the (b) step, forming the recognition mark on the second surface such that the recognition mark is electrically separated from the through electrodes and not overlapped with the through electrodes in plan view.22. The method for manufacturing the semiconductor device according to claim 21 , further comprising the steps of:(d) after the (b) step and before the (c) step, forming the electrode pads on the through electrodes such that the electrode pads are electrically coupled with the through electrodes respectively; andwherein, in the (c) step, the recognition mark is formed by plating.23. The method for manufacturing the semiconductor device ...

Подробнее
08-02-2018 дата публикации

TRANSMITTER CIRCUIT, SEMICONDUCTOR APPARATUS AND DATA TRANSMISSION METHOD

Номер: US20180041233A1
Принадлежит:

The transmitter circuit according to one embodiment includes a pulse generating circuit generating a pulse signal based on edges of input data, a first output driver outputting, based on the pulse signal, a first output pulse signal according to one of the edges to a first end of an external insulating coupling element, a second output driver outputting, based on the pulse signal, a second output pulse signal according to other one of the edges to a second end of the insulating coupling element, and an output stop circuit stopping the first and second output pulse signals from being output for a prescribed period from when a power supply voltage is turned on. 1. A transmitter circuit comprising:a pulse generating circuit generating a pulse signal based on edges of input data;a first output driver outputting, based on the pulse signal, a first output pulse signal according to one of the edges to a first end of an external insulating coupling element;a second output driver outputting, based on the pulse signal, a second output pulse signal according to other one of the edges to a second end of the insulating coupling element; andan output stop circuit stopping the first and second output pulse signals from being output for a prescribed period from when a power supply voltage is turned on, wherein the output stop circuit includes:a first capacitor element connected between a power supply and a first node;a first transistor connected between the first node and a ground;a second transistor connected between the power supply and a second node; anda second capacitor element connected between the second node and the ground, whereina gate of the first transistor is connected to the second node and a gate of the second transistor is connected to the first node, andthe stop of the output of the first and second output pulse signals is released in accordance with a voltage of the first node and a voltage of the second node.2. The transmitter circuit according to claim 1 , ...

Подробнее
18-02-2021 дата публикации

Support structure for mems device with particle filter

Номер: US20210047176A1

Various embodiments of the present disclosure are directed towards a microphone including a support structure layer disposed between a particle filter and a microelectromechanical systems (MEMS) structure. A carrier substrate is disposed below the particle filter and has opposing sidewalls that define a carrier substrate opening. The MEMS structure overlies the carrier substrate and includes a diaphragm having opposing sidewalls that define a diaphragm opening overlying the carrier substrate opening. The particle filter is disposed between the carrier substrate and the MEMS structure. A plurality of filter openings extend through the particle filter. The support structure layer includes a support structure having one or more segments spaced laterally between the opposing sidewalls of the carrier substrate. The one or more segments of the support structure are spaced laterally between the plurality of filter openings.

Подробнее
15-02-2018 дата публикации

ELECTRO-OPTICAL DEVICE, MANUFACTURING METHOD OF ELECTRO-OPTICAL DEVICE, AND ELECTRONIC APPARATUS

Номер: US20180045912A1
Автор: KONDO Manabu
Принадлежит: SEIKO EPSON CORPORATION

An electro-optical apparatus has an element substrate that is provided with a mirror and a sealing member which seals the mirror, and the sealing member includes a light-transmitting cover which faces the mirror opposite from the element substrate. An infrared cut filter is laminated on the light-transmitting cover. 1. An electro-optical device comprising:an element substrate;a mirror that is provided on a first face side of the element substrate;a driving element that drives the mirror;a sealing member that has a light-transmitting cover and is provided such that the mirror is positioned between the light-transmitting cover and the element substrate;an infrared cut filter that is provided on the light-transmitting cover;a substrate on which the element substrate is mounted; anda lead terminal that extends outside from the substrate, the lead terminal having a bent section that is bent in a direction in which a leading end section of the lead terminal is away from the substrate.2. The electro-optical device according to claim 1 ,wherein the infrared cut filter is formed of a film that is laminated on at least one of a second face of the light-transmitting cover and a third face of the light-transmitting cover, the second face faces the mirror, and the third face is on an opposite side from the second face.3. (canceled)4. The electro-optical device according to claim 1 ,wherein the lead terminal includes a convex section that protrudes in a direction which intersects with an extension direction of the lead terminal.5. The electro-optical device according to claim 1 ,wherein a heat dissipation unit is provided on a face on an opposite side from the element substrate of the substrate.6. The electro-optical device according to claim 5 ,wherein the heat dissipation unit is a heat sink on which a heat dissipation fin is provided.7. The electro-optical device according to claim 1 ,wherein the sealing member includes a spacer that surrounds a region in which the mirror is ...

Подробнее
06-02-2020 дата публикации

Ceramic package for high current signals

Номер: US20200043825A1
Принадлежит: Texas Instruments Inc

A hermetic ceramic package for high current signals includes a substrate made of a plurality of ceramic green sheets that form an upper body portion having an upper surface and a lower body portion having a lower surface and an intermediate surface between the upper surface and the lower surface. A first conductive plate is formed on the intermediate surface and a first plurality of conductive pad vias are formed in the lower body portion, extending from the first conductive plate to the lower surface of the lower body portion. A heat sink if coupled to the lower surface of the lower body portion and a first conductive pad also coupled to the lower surface such that the first conductive pad is electrically coupled to the first plurality of conductive pad vias.

Подробнее
06-02-2020 дата публикации

Thermal and stress isolation for precision circuit

Номер: US20200043828A1
Принадлежит: Texas Instruments Inc

Described examples include microelectronic devices and integrated circuits with an active first circuit in a first segment of a first wafer, a second circuit in a second segment of the first wafer, and second and third wafers bonded to different surfaces of the first wafer to provide first and second cavities with surfaces spaced from the first segment. An opening extends through the first wafer between the first and second cavities to separate portions of the first and second segments and to form a sealed cavity that surrounds the first segment. A bridge segment of the first wafer supports the first segment in the sealed cavity and includes one or more conductive structures to electrically connect the first and second circuits.

Подробнее
18-02-2021 дата публикации

Semiconductor package structure and manufacturing method thereof

Номер: US20210050296A1
Принадлежит: Powertech Technology Inc

A semiconductor package structure including a circuit substrate, a redistribution layer, and at least two dies is provided. The circuit substrate has a first surface and a second surface opposite the first surface. The redistribution layer is located on the first surface. The redistribution layer is electrically connected to the circuit substrate. The spacing of the opposing sidewalls of the redistribution layer is less than the spacing of the opposing sidewalls of the circuit substrate. The redistribution layer is directly in contact with the circuit substrate. At least two dies are disposed on the redistribution layer. Each of the at least two dies has an active surface facing the circuit substrate. One of the at least two dies is electrically connected to the other of the at least two dies by the redistribution layer. A manufacturing method of a semiconductor package structure is also provided.

Подробнее
18-02-2016 дата публикации

Module Arrangement For Power Semiconductor Devices

Номер: US20160049342A1
Автор: Hamit Duran, Munaf Rahimo
Принадлежит: ABB TECHNOLOGY AG

A module arrangement for power semiconductor devices, including one or more power semiconductor modules, wherein the one or more power semiconductor modules include a substrate with a first surface and a second surface being arranged opposite to the first surface, wherein the substrate is at least partially electrically insulating, wherein a conductive structure is arranged at the first surface of the substrate, wherein at least one power semiconductor device is arranged on the conductive structure and electrically connected thereto, wherein the one or more modules includes an inner volume for receiving the at least one power semiconductor device which volume is hermetically sealed from its surrounding by a module enclosure, wherein the module arrangement includes an arrangement enclosure at least partly defining a volume for receiving the one or more modules, and wherein the arrangement enclosure seals covers the volume.

Подробнее
15-02-2018 дата публикации

LIMITING ELECTRONIC PACKAGE WARPAGE

Номер: US20180047590A1
Автор: LI SHIDONG
Принадлежит:

An electronic package includes a carrier, semiconductor chip, a lid, and a lid-ring. The carrier includes a top surface and a bottom surface configured to be electrically connected to a system board. The semiconductor chip is electrically connected to the top surface. The lid is attached to the top surface enclosing semiconductor chip and includes a perimeter recess. The lid-ring is juxtaposed within the perimeter recess. The lid-ring exerts a reverse bending moment upon the lid to limit warpage of the electronic package. 1. A electronic package comprising:a carrier comprising a top surface and a bottom surface configured to be electrically connected to a system board;a semiconductor chip electrically connected to the top surface of the carrier;a lid attached to the top surface of the carrier that encloses semiconductor chip, the lid comprising a perimeter recess within the upper half of the lid, the perimeter recess comprising a horizontal recess and vertical recess comprising two recess sidewalls; anda lid-ring attached to the lid within the perimeter recess, the lid ring comprising a horizontal portion orthogonal and distally connected to a vertical portion, wherein the horizontal portion comprises a greater width than height, is parallel with the semiconductor chip, and is juxtaposed within the horizontal recess, wherein the vertical portion comprises a greater height than width and is juxtaposed between the two vertical recess sidewalls, wherein a perimeter sidewall of the lid-ring horizontal portion is coplanar with a perimeter sidewall of the lid, and wherein the lid-ring applies a contracting force against the upper half of the lid to exert a reverse bending moment upon the lid.2. The electronic package of claim 1 , wherein the lid is in thermal contact with the semiconductor chip.3. The electronic package of claim 1 , wherein a top surface of the lid and a top surface the lid-ring are coplanar.4. The electronic package of claim 1 , wherein the lid and the ...

Подробнее
15-02-2018 дата публикации

THERMAL INTERFACE MATERIAL ON PACKAGE

Номер: US20180047655A1
Принадлежит:

A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly. 1. A method , comprising:dispensing a thermal interface material (TIM) on an electronic assembly;placing a lid on the TIM, over the electronic assembly;pressing the lid onto the electronic assembly to perform a packaged assembly;curing the packaged assembly; andperforming a sonoscan of the packaged assembly to determine a presence of voiding in the TIM.2. The method of claim 1 , further comprising removing volatile species of the TIM prior to lid placement.3. The method of claim 2 , wherein the volatile species comprises cyclic siloxanes and decyl trimethoxysilane.4. The method of claim 2 , wherein the removal of the volatile species comprises maintaining the TIM at room temperature for a predetermined time period prior to the lid placement.5. The method of claim 4 , wherein the predetermined time period is about 60 minutes.6. The method of claim 2 , wherein the removal of the volatile species comprises subjecting the TIM to a predetermined temperature claim 2 , in an oven claim 2 , for a predetermined time period.7. The method of claim 6 , wherein the predetermined temperature is about 45° C. to 55° C. and the predetermined time period is about 15-30 minutes.8. The method of claim 6 , wherein the predetermined temperature is about 50° C. and the predetermined time period is about 20 minutes.9. The method of claim 6 , wherein the predetermined temperature is about 50° C. and the predetermined time period is about 15 minutes.10. The method of claim 2 , wherein the removal ...

Подробнее
15-02-2018 дата публикации

Electronic Component Package Structure and Electronic Device

Номер: US20180049351A1
Принадлежит:

An electronic component package structure and an electronic device where the electronic component package structure includes at least a substrate having a set attachment area for attaching an electronic component; a conductive lid having a top and a sidewall that extends toward the substrate, where one side of the sidewall close to the substrate has a bonding end, where the bonding end bonds the conductive lid to the substrate by using a non-conductive adhesive, and the conductive lid bonded to the substrate encloses the attachment area and forms a shielding space over the attachment area; and the non-conductive adhesive is located between the substrate and the bonding end, and has a dielectric constant not less than 7 and a coating thickness not greater than 0.07 millimeters (mm). With the present disclosure, an Electromagnetic Interference (EMI) shielding effect of the shielding space can be improved. 1. An electronic component package structure , comprising:a substrate;a conductive lid; anda non-conductive adhesive,wherein the substrate has a set attachment area for attaching an electronic component,wherein the conductive lid has a top and a sidewall that extend toward the substrate,wherein one side of the sidewall proximate to the substrate has a bonding end,wherein the bonding end bonds the conductive lid to the substrate using the non-conductive adhesive,wherein the conductive lid bonded to the substrate encloses the attachment area and forms a shielding space over the attachment area,wherein the non-conductive adhesive is located between the substrate and the bonding end,wherein the electronic component package structure further comprises a solder mask disposed on a surface of one side of the substrate facing the conductive lid, andwherein in the solder mask, a first open window is disposed in a position in which the non-conductive adhesive is disposed.2. The electronic component package structure according to claim 1 , wherein an air hole is disposed in the ...

Подробнее
03-03-2022 дата публикации

Semiconductor package

Номер: US20220068845A1

A semiconductor package includes a multilayer substrate, a device die, an insulating encapsulant, and a shielding structure. The multilayer substrate has a first surface and a second surface opposite to the first surface. The multilayer substrate includes through holes, and each of the through holes extends from the first surface to the second surface. The device die is disposed on the first surface of the multilayer substrate. The insulating encapsulant is disposed on the first surface of the multilayered substrate and encapsulating the device die. The shielding structure is disposed over the first surface of the multilayer substrate. The shielding structure includes a cover body and conductive pillars. The cover body covers the device die and the insulating encapsulant. The conductive pillars are connected to the cover body and fitted into the through holes of the multilayer substrate.

Подробнее
03-03-2022 дата публикации

Method of fabricating a semiconductor device

Номер: US20220068852A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

Подробнее
22-02-2018 дата публикации

Adjustable heat sink fin spacing

Номер: US20180051940A1
Принадлежит: International Business Machines Corp

A heat sink includes a heat sink base/riser, a first fin, and a second fin. The spacing between the base/riser and the first fin and the second fin, restively, may be adjusted by rotating a threaded rod. The threaded rod includes a first threaded knurl that is engaged with the first fin and a second threaded knurl that is engaged with the second fin. The thread pitch of the first threaded knurl and the second threaded knurl may differ. For example, the pitch of the first threaded knurl may be smaller than the pitch of the second threaded knurl if the first fin is located nearest the heat sink base/riser relative to the second fin. The spacing of the heat sink fins may be adjusted based upon the current operating conditions of the electronic device to maintain an optimal temperature of a heat generating device during device operation.

Подробнее